20#ifndef STM32H7xx_HAL_SWPMI_H
21#define STM32H7xx_HAL_SWPMI_H
86#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
87typedef struct __SWPMI_HandleTypeDef
118#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
119 void (*RxCpltCallback)(
struct __SWPMI_HandleTypeDef *hswpmi);
120 void (*RxHalfCpltCallback)(
struct __SWPMI_HandleTypeDef *hswpmi);
121 void (*TxCpltCallback)(
struct __SWPMI_HandleTypeDef *hswpmi);
122 void (*TxHalfCpltCallback)(
struct __SWPMI_HandleTypeDef *hswpmi);
123 void (*ErrorCallback)(
struct __SWPMI_HandleTypeDef *hswpmi);
124 void (*MspInitCallback)(
struct __SWPMI_HandleTypeDef *hswpmi);
125 void (*MspDeInitCallback)(
struct __SWPMI_HandleTypeDef *hswpmi);
130#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
136 HAL_SWPMI_RX_COMPLETE_CB_ID = 0x00U,
137 HAL_SWPMI_RX_HALFCOMPLETE_CB_ID = 0x01U,
138 HAL_SWPMI_TX_COMPLETE_CB_ID = 0x02U,
139 HAL_SWPMI_TX_HALFCOMPLETE_CB_ID = 0x03U,
140 HAL_SWPMI_ERROR_CB_ID = 0x04U,
141 HAL_SWPMI_MSPINIT_CB_ID = 0x05U,
142 HAL_SWPMI_MSPDEINIT_CB_ID = 0x06U
143} HAL_SWPMI_CallbackIDTypeDef;
166#define HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000)
167#define HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004)
168#define HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008)
169#define HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C)
170#define HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010)
171#define HAL_SWPMI_ERROR_TIMEOUT ((uint32_t)0x00000020)
172#define HAL_SWPMI_ERROR_TXBEF_TIMEOUT ((uint32_t)0x00000040)
173#define HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY ((uint32_t)0x00000080)
174#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
175#define HAL_SWPMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100)
185#define SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
186#define SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS
195#define SWPMI_TX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
196#define SWPMI_TX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
197#define SWPMI_TX_MULTI_SOFTWAREBUFFER SWPMI_CR_TXMODE
206#define SWPMI_RX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
207#define SWPMI_RX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
208#define SWPMI_RX_MULTI_SOFTWAREBUFFER SWPMI_CR_RXMODE
219#define SWPMI_FLAG_RXBFF SWPMI_ISR_RXBFF
220#define SWPMI_FLAG_TXBEF SWPMI_ISR_TXBEF
221#define SWPMI_FLAG_RXBERF SWPMI_ISR_RXBERF
222#define SWPMI_FLAG_RXOVRF SWPMI_ISR_RXOVRF
223#define SWPMI_FLAG_TXUNRF SWPMI_ISR_TXUNRF
224#define SWPMI_FLAG_RXNE SWPMI_ISR_RXNE
225#define SWPMI_FLAG_TXE SWPMI_ISR_TXE
226#define SWPMI_FLAG_TCF SWPMI_ISR_TCF
227#define SWPMI_FLAG_SRF SWPMI_ISR_SRF
228#define SWPMI_FLAG_SUSP SWPMI_ISR_SUSP
229#define SWPMI_FLAG_DEACTF SWPMI_ISR_DEACTF
230#define SWPMI_FLAG_RDYF SWPMI_ISR_RDYF
241#define SWPMI_IT_RDYIE SWPMI_IER_RDYIE
242#define SWPMI_IT_SRIE SWPMI_IER_SRIE
243#define SWPMI_IT_TCIE SWPMI_IER_TCIE
244#define SWPMI_IT_TIE SWPMI_IER_TIE
245#define SWPMI_IT_RIE SWPMI_IER_RIE
246#define SWPMI_IT_TXUNRIE SWPMI_IER_TXUNRIE
247#define SWPMI_IT_RXOVRIE SWPMI_IER_RXOVRIE
248#define SWPMI_IT_RXBERIE SWPMI_IER_RXBERIE
249#define SWPMI_IT_TXBEIE SWPMI_IER_TXBEIE
250#define SWPMI_IT_RXBFIE SWPMI_IER_RXBFIE
269#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
270#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{ \
271 (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \
272 (__HANDLE__)->MspInitCallback = NULL; \
273 (__HANDLE__)->MspDeInitCallback = NULL; \
276#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
284#define __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
291#define __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
298#define __HAL_SWPMI_TRANSCEIVER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
305#define __HAL_SWPMI_TRANSCEIVER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
325#define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
341#define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
359#define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
377#define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
395#define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
413#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
430#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
433 HAL_SWPMI_CallbackIDTypeDef CallbackID,
434 pSWPMI_CallbackTypeDef pCallback);
436 HAL_SWPMI_CallbackIDTypeDef CallbackID);
501#define IS_SWPMI_VOLTAGE_CLASS(__CLASS__) (((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \
502 ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B))
504#define IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 255U))
507#define IS_SWPMI_TX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \
508 ((__MODE__) == SWPMI_TX_MULTI_SOFTWAREBUFFER))
511#define IS_SWPMI_RX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_RX_NO_SOFTWAREBUFFER) || \
512 ((__MODE__) == SWPMI_RX_MULTI_SOFTWAREBUFFER))
#define __IO
Definition: core_cm4.h:239
HAL_SWPMI_StateTypeDef
HAL SWPMI State structures definition.
Definition: stm32h7xx_hal_swpmi.h:72
@ HAL_SWPMI_STATE_BUSY
Definition: stm32h7xx_hal_swpmi.h:75
@ HAL_SWPMI_STATE_RESET
Definition: stm32h7xx_hal_swpmi.h:73
@ HAL_SWPMI_STATE_ERROR
Definition: stm32h7xx_hal_swpmi.h:80
@ HAL_SWPMI_STATE_TIMEOUT
Definition: stm32h7xx_hal_swpmi.h:79
@ HAL_SWPMI_STATE_BUSY_TX
Definition: stm32h7xx_hal_swpmi.h:76
@ HAL_SWPMI_STATE_BUSY_TX_RX
Definition: stm32h7xx_hal_swpmi.h:78
@ HAL_SWPMI_STATE_BUSY_RX
Definition: stm32h7xx_hal_swpmi.h:77
@ HAL_SWPMI_STATE_READY
Definition: stm32h7xx_hal_swpmi.h:74
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32h7xx_hal_def.h:58
SWPMI handle Structure definition.
Definition: stm32h7xx_hal_swpmi.h:91
uint32_t * pTxBuffPtr
Definition: stm32h7xx_hal_swpmi.h:96
uint32_t TxXferSize
Definition: stm32h7xx_hal_swpmi.h:98
DMA_HandleTypeDef * hdmatx
Definition: stm32h7xx_hal_swpmi.h:108
SWPMI_TypeDef * Instance
Definition: stm32h7xx_hal_swpmi.h:92
__IO HAL_SWPMI_StateTypeDef State
Definition: stm32h7xx_hal_swpmi.h:114
uint32_t RxXferSize
Definition: stm32h7xx_hal_swpmi.h:104
SWPMI_InitTypeDef Init
Definition: stm32h7xx_hal_swpmi.h:94
uint32_t TxXferCount
Definition: stm32h7xx_hal_swpmi.h:100
uint32_t * pRxBuffPtr
Definition: stm32h7xx_hal_swpmi.h:102
uint32_t RxXferCount
Definition: stm32h7xx_hal_swpmi.h:106
HAL_LockTypeDef Lock
Definition: stm32h7xx_hal_swpmi.h:112
__IO uint32_t ErrorCode
Definition: stm32h7xx_hal_swpmi.h:116
DMA_HandleTypeDef * hdmarx
Definition: stm32h7xx_hal_swpmi.h:110
SWPMI Init Structure definition.
Definition: stm32h7xx_hal_swpmi.h:49
uint32_t TxBufferingMode
Definition: stm32h7xx_hal_swpmi.h:59
uint32_t BitRate
Definition: stm32h7xx_hal_swpmi.h:53
uint32_t RxBufferingMode
Definition: stm32h7xx_hal_swpmi.h:62
uint32_t VoltageClass
Definition: stm32h7xx_hal_swpmi.h:50
Single Wire Protocol Master Interface SPWMI.
Definition: stm32h723xx.h:1615
DMA handle Structure definition.
Definition: stm32h7xx_hal_dma.h:138