20#ifndef STM32H7xx_HAL_FMAC_H
21#define STM32H7xx_HAL_FMAC_H
50 HAL_FMAC_STATE_RESET = 0x00U,
51 HAL_FMAC_STATE_READY = 0x20U,
52 HAL_FMAC_STATE_BUSY = 0x24U,
53 HAL_FMAC_STATE_BUSY_RD = 0x25U,
54 HAL_FMAC_STATE_BUSY_WR = 0x26U,
55 HAL_FMAC_STATE_TIMEOUT = 0xA0U,
56 HAL_FMAC_STATE_ERROR = 0xE0U
57} HAL_FMAC_StateTypeDef;
62#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
63typedef struct __FMAC_HandleTypeDef
83 uint16_t InputCurrentSize;
91 uint16_t OutputCurrentSize;
93 uint16_t *pOutputSize;
104#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
105 void (* ErrorCallback)(
struct __FMAC_HandleTypeDef *hfmac);
107 void (* HalfGetDataCallback)(
struct __FMAC_HandleTypeDef *hfmac);
109 void (* GetDataCallback)(
struct __FMAC_HandleTypeDef *hfmac);
111 void (* HalfOutputDataReadyCallback)(
struct __FMAC_HandleTypeDef *hfmac);
113 void (* OutputDataReadyCallback)(
struct __FMAC_HandleTypeDef *hfmac);
115 void (* FilterConfigCallback)(
struct __FMAC_HandleTypeDef *hfmac);
117 void (* FilterPreloadCallback)(
struct __FMAC_HandleTypeDef *hfmac);
119 void (* MspInitCallback)(
struct __FMAC_HandleTypeDef *hfmac);
121 void (* MspDeInitCallback)(
struct __FMAC_HandleTypeDef *hfmac);
127 __IO HAL_FMAC_StateTypeDef State;
130 __IO HAL_FMAC_StateTypeDef RdState;
133 __IO HAL_FMAC_StateTypeDef WrState;
136 __IO uint32_t ErrorCode;
141#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
147 HAL_FMAC_ERROR_CB_ID = 0x00U,
148 HAL_FMAC_HALF_GET_DATA_CB_ID = 0x01U,
149 HAL_FMAC_GET_DATA_CB_ID = 0x02U,
150 HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID = 0x03U,
151 HAL_FMAC_OUTPUT_DATA_READY_CB_ID = 0x04U,
152 HAL_FMAC_FILTER_CONFIG_CB_ID = 0x05U,
153 HAL_FMAC_FILTER_PRELOAD_CB_ID = 0x06U,
155 HAL_FMAC_MSPINIT_CB_ID = 0x07U,
156 HAL_FMAC_MSPDEINIT_CB_ID = 0x08U,
157} HAL_FMAC_CallbackIDTypeDef;
162typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac);
171 uint8_t InputBaseAddress;
176 uint8_t InputBufferSize;
180 uint32_t InputThreshold;
185 uint8_t CoeffBaseAddress;
190 uint8_t CoeffBufferSize;
193 uint8_t OutputBaseAddress;
198 uint8_t OutputBufferSize;
202 uint32_t OutputThreshold;
222 uint8_t OutputAccess;
241} FMAC_FilterConfigTypeDef;
260#define HAL_FMAC_ERROR_NONE 0x00000000U
261#define HAL_FMAC_ERROR_SAT 0x00000001U
262#define HAL_FMAC_ERROR_UNFL 0x00000002U
263#define HAL_FMAC_ERROR_OVFL 0x00000004U
264#define HAL_FMAC_ERROR_DMA 0x00000008U
265#define HAL_FMAC_ERROR_RESET 0x00000010U
266#define HAL_FMAC_ERROR_PARAM 0x00000020U
267#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
268#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U
270#define HAL_FMAC_ERROR_TIMEOUT 0x00000080U
280#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0)
281#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1)
282#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)
283#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3)
284#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)
294#define FMAC_THRESHOLD_1 0x00000000U
298#define FMAC_THRESHOLD_2 0x01000000U
302#define FMAC_THRESHOLD_4 0x02000000U
306#define FMAC_THRESHOLD_8 0x03000000U
310#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU
319#define FMAC_BUFFER_ACCESS_NONE 0x00U
320#define FMAC_BUFFER_ACCESS_DMA 0x01U
321#define FMAC_BUFFER_ACCESS_POLLING 0x02U
322#define FMAC_BUFFER_ACCESS_IT 0x03U
331#define FMAC_CLIP_DISABLED 0x00000000U
332#define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN
341#define FMAC_FLAG_YEMPTY FMAC_SR_YEMPTY
342#define FMAC_FLAG_X1FULL FMAC_SR_X1FULL
343#define FMAC_FLAG_OVFL FMAC_SR_OVFL
344#define FMAC_FLAG_UNFL FMAC_SR_UNFL
345#define FMAC_FLAG_SAT FMAC_SR_SAT
355#define FMAC_IT_RIEN FMAC_CR_RIEN
356#define FMAC_IT_WIEN FMAC_CR_WIEN
357#define FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN
358#define FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN
359#define FMAC_IT_SATIEN FMAC_CR_SATIEN
390#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
391#define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) do{ \
392 (__HANDLE__)->State = HAL_FMAC_STATE_RESET; \
393 (__HANDLE__)->MspInitCallback = NULL; \
394 (__HANDLE__)->MspDeInitCallback = NULL; \
397#define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMAC_STATE_RESET)
412#define __HAL_FMAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
413 (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
427#define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
428 (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
442#define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \
443 (((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))
452#define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__)
466#define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \
467 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
476#define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__)
490#define __HAL_FMAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
491 (((__HANDLE__)->Instance->CR) & (__INTERRUPT__))
502#define FMAC_PARAM_P_MAX_IIR 64U
503#define FMAC_PARAM_P_MAX_FIR 127U
504#define FMAC_PARAM_P_MIN 2U
505#define FMAC_PARAM_Q_MAX 63U
506#define FMAC_PARAM_Q_MIN 1U
507#define FMAC_PARAM_R_MAX 7U
523#define IS_FMAC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
524 ((__FUNCTION__) == FMAC_FUNC_LOAD_X2) || \
525 ((__FUNCTION__) == FMAC_FUNC_LOAD_Y) || \
526 ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
527 ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
534#define IS_FMAC_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
535 ((__FUNCTION__) == FMAC_FUNC_LOAD_X2) || \
536 ((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
543#define IS_FMAC_N_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
544 ((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
551#define IS_FMAC_N_M_LOAD_FUNCTION(__FUNCTION__) ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)
558#define IS_FMAC_FILTER_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
559 ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
567#define IS_FMAC_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == FMAC_THRESHOLD_1) || \
568 ((__THRESHOLD__) == FMAC_THRESHOLD_2) || \
569 ((__THRESHOLD__) == FMAC_THRESHOLD_4) || \
570 ((__THRESHOLD__) == FMAC_THRESHOLD_NO_VALUE) || \
571 ((__THRESHOLD__) == FMAC_THRESHOLD_8))
579#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ((((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \
580 (((__P__) >= FMAC_PARAM_P_MIN) && \
581 ((__P__) <= FMAC_PARAM_P_MAX_FIR))) || \
582 (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
583 (((__P__) >= FMAC_PARAM_P_MIN) && \
584 ((__P__) <= FMAC_PARAM_P_MAX_IIR))))
592#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
593 (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
594 (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) )
602#define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
603 ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) && \
604 ((__R__) <= FMAC_PARAM_R_MAX))
611#define IS_FMAC_BUFFER_ACCESS(__BUFFER_ACCESS__) (((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_NONE) || \
612 ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_DMA) || \
613 ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_POLLING) || \
614 ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_IT))
621#define IS_FMAC_CLIP_STATE(__CLIP_STATE__) (((__CLIP_STATE__) == FMAC_CLIP_DISABLED) || \
622 ((__CLIP_STATE__) == FMAC_CLIP_ENABLED))
631#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) \
632 (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
633 ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
634 ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
635 ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \
636 ((__WM__) == FMAC_THRESHOLD_1))|| \
637 ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
654void HAL_FMAC_MspInit(FMAC_HandleTypeDef *hfmac);
655void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac);
657#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
659HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
660 pFMAC_CallbackTypeDef pCallback);
661HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID);
671HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
672HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
673HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
674 int16_t *pOutput, uint8_t OutputSize);
675HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
676 int16_t *pOutput, uint8_t OutputSize);
677HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
678HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize);
679HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
680HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout);
690void HAL_FMAC_ErrorCallback(FMAC_HandleTypeDef *hfmac);
691void HAL_FMAC_HalfGetDataCallback(FMAC_HandleTypeDef *hfmac);
692void HAL_FMAC_GetDataCallback(FMAC_HandleTypeDef *hfmac);
693void HAL_FMAC_HalfOutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
694void HAL_FMAC_OutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
695void HAL_FMAC_FilterConfigCallback(FMAC_HandleTypeDef *hfmac);
696void HAL_FMAC_FilterPreloadCallback(FMAC_HandleTypeDef *hfmac);
705void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac);
714HAL_FMAC_StateTypeDef HAL_FMAC_GetState(
const FMAC_HandleTypeDef *hfmac);
715uint32_t HAL_FMAC_GetError(
const FMAC_HandleTypeDef *hfmac);
#define __IO
Definition: core_cm4.h:239
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32h7xx_hal_def.h:58
Filter and Mathematical ACcelerator.
Definition: stm32h723xx.h:990
DMA handle Structure definition.
Definition: stm32h7xx_hal_dma.h:138