RTEMS 6.1-rc4
Loading...
Searching...
No Matches
stm32h7xx_hal_dfsdm.h
Go to the documentation of this file.
1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_DFSDM_H
21#define STM32H7xx_HAL_DFSDM_H
22
23#ifdef __cplusplus
24 extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
38/* Exported types ------------------------------------------------------------*/
47typedef enum
48{
49 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U,
50 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U,
51 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU
52} HAL_DFSDM_Channel_StateTypeDef;
53
57typedef struct
58{
59 FunctionalState Activation;
60 uint32_t Selection;
62 uint32_t Divider;
64} DFSDM_Channel_OutputClockTypeDef;
65
69typedef struct
70{
71 uint32_t Multiplexer;
73 uint32_t DataPacking;
75 uint32_t Pins;
77} DFSDM_Channel_InputTypeDef;
78
82typedef struct
83{
84 uint32_t Type;
86 uint32_t SpiClock;
88} DFSDM_Channel_SerialInterfaceTypeDef;
89
93typedef struct
94{
95 uint32_t FilterOrder;
97 uint32_t Oversampling;
99} DFSDM_Channel_AwdTypeDef;
100
104typedef struct
105{
106 DFSDM_Channel_OutputClockTypeDef OutputClock;
107 DFSDM_Channel_InputTypeDef Input;
108 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface;
109 DFSDM_Channel_AwdTypeDef Awd;
110 int32_t Offset;
112 uint32_t RightBitShift;
114} DFSDM_Channel_InitTypeDef;
115
119#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
120typedef struct __DFSDM_Channel_HandleTypeDef
121#else
122typedef struct
123#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
124{
125 DFSDM_Channel_TypeDef *Instance;
126 DFSDM_Channel_InitTypeDef Init;
127 HAL_DFSDM_Channel_StateTypeDef State;
128#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
129 void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
130 void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
131 void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
132 void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
133#endif
134} DFSDM_Channel_HandleTypeDef;
135
136#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
140typedef enum
141{
142 HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U,
143 HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U,
144 HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U,
145 HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U
146} HAL_DFSDM_Channel_CallbackIDTypeDef;
147
151typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
152#endif
153
157typedef enum
158{
159 HAL_DFSDM_FILTER_STATE_RESET = 0x00U,
160 HAL_DFSDM_FILTER_STATE_READY = 0x01U,
161 HAL_DFSDM_FILTER_STATE_REG = 0x02U,
162 HAL_DFSDM_FILTER_STATE_INJ = 0x03U,
163 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U,
164 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU
165} HAL_DFSDM_Filter_StateTypeDef;
166
170typedef struct
171{
172 uint32_t Trigger;
174 FunctionalState FastMode;
175 FunctionalState DmaMode;
176} DFSDM_Filter_RegularParamTypeDef;
177
181typedef struct
182{
183 uint32_t Trigger;
185 FunctionalState ScanMode;
186 FunctionalState DmaMode;
187 uint32_t ExtTrigger;
189 uint32_t ExtTriggerEdge;
191} DFSDM_Filter_InjectedParamTypeDef;
192
196typedef struct
197{
198 uint32_t SincOrder;
200 uint32_t Oversampling;
202 uint32_t IntOversampling;
204} DFSDM_Filter_FilterParamTypeDef;
205
209typedef struct
210{
211 DFSDM_Filter_RegularParamTypeDef RegularParam;
212 DFSDM_Filter_InjectedParamTypeDef InjectedParam;
213 DFSDM_Filter_FilterParamTypeDef FilterParam;
214} DFSDM_Filter_InitTypeDef;
215
219#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
220typedef struct __DFSDM_Filter_HandleTypeDef
221#else
222typedef struct
223#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
224{
225 DFSDM_Filter_TypeDef *Instance;
226 DFSDM_Filter_InitTypeDef Init;
227 DMA_HandleTypeDef *hdmaReg;
228 DMA_HandleTypeDef *hdmaInj;
229 uint32_t RegularContMode;
230 uint32_t RegularTrigger;
231 uint32_t InjectedTrigger;
232 uint32_t ExtTriggerEdge;
233 FunctionalState InjectedScanMode;
234 uint32_t InjectedChannelsNbr;
235 uint32_t InjConvRemaining;
236 HAL_DFSDM_Filter_StateTypeDef State;
237 uint32_t ErrorCode;
238#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
239 void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
240 uint32_t Channel, uint32_t Threshold);
241 void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
242 void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
243 void (*InjConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
244 void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
245 void (*ErrorCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
246 void (*MspInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
247 void (*MspDeInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
248#endif
249}DFSDM_Filter_HandleTypeDef;
250
254typedef struct
255{
256 uint32_t DataSource;
258 uint32_t Channel;
260 int32_t HighThreshold;
262 int32_t LowThreshold;
264 uint32_t HighBreakSignal;
266 uint32_t LowBreakSignal;
268} DFSDM_Filter_AwdParamTypeDef;
269
270#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
274typedef enum
275{
276 HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U,
277 HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U,
278 HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U,
279 HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U,
280 HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U,
281 HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U,
282 HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U
283} HAL_DFSDM_Filter_CallbackIDTypeDef;
284
288typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
289typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
290#endif
291
295/* End of exported types -----------------------------------------------------*/
296
297/* Exported constants --------------------------------------------------------*/
307#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U
308#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC
317#define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U
318#define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0
319#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1
328#define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U
329#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0
330#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1
339#define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U
340#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL
349#define DFSDM_CHANNEL_SPI_RISING 0x00000000U
350#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0
351#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1
352#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP
361#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U
362#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0
363#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1
364#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL
373#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U
374#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0
375#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1
376#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD
385#define DFSDM_FILTER_SW_TRIGGER 0x00000000U
386#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U
387#define DFSDM_FILTER_EXT_TRIGGER 0x00000002U
396#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U
397#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0
398#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1
399#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
400#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2
401#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
402#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
403#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
404#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3
405#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
406#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
407#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3)
408#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
409#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
410#define DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0)
411#define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)
412#if (STM32H7_DEV_ID == 0x480UL)
413#define DFSDM_FILTER_EXT_TRIG_COMP1_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
414 DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_0)
415#define DFSDM_FILTER_EXT_TRIG_COMP2_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
416 DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
417#elif (STM32H7_DEV_ID == 0x483UL)
418#define DFSDM_FILTER_EXT_TRIG_TIM23_TRGO (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | \
419 DFSDM_FLTCR1_JEXTSEL_0)
420#define DFSDM_FILTER_EXT_TRIG_TIM24_TRGO (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2 )
421#endif /* STM32H7_DEV_ID == 0x480UL */
430#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0
431#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1
432#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN
441#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U
442#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0
443#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1
444#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)
445#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2
446#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)
455#define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U
456#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL
465#define DFSDM_FILTER_ERROR_NONE 0x00000000U
466#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U
467#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U
468#define DFSDM_FILTER_ERROR_DMA 0x00000003U
469#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
470#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U
471#endif
480#define DFSDM_NO_BREAK_SIGNAL 0x00000000U
481#define DFSDM_BREAK_SIGNAL_0 0x00000001U
482#define DFSDM_BREAK_SIGNAL_1 0x00000002U
483#define DFSDM_BREAK_SIGNAL_2 0x00000004U
484#define DFSDM_BREAK_SIGNAL_3 0x00000008U
493/* DFSDM Channels ------------------------------------------------------------*/
494/* The DFSDM channels are defined as follows:
495 - in 16-bit LSB the channel mask is set
496 - in 16-bit MSB the channel number is set
497 e.g. for channel 5 definition:
498 - the channel mask is 0x00000020 (bit 5 is set)
499 - the channel number 5 is 0x00050000
500 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
501#define DFSDM_CHANNEL_0 0x00000001U
502#define DFSDM_CHANNEL_1 0x00010002U
503#define DFSDM_CHANNEL_2 0x00020004U
504#define DFSDM_CHANNEL_3 0x00030008U
505#define DFSDM_CHANNEL_4 0x00040010U
506#define DFSDM_CHANNEL_5 0x00050020U
507#define DFSDM_CHANNEL_6 0x00060040U
508#define DFSDM_CHANNEL_7 0x00070080U
517#define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U
518#define DFSDM_CONTINUOUS_CONV_ON 0x00000001U
527#define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U
528#define DFSDM_AWD_LOW_THRESHOLD 0x00000001U
536/* End of exported constants -------------------------------------------------*/
537
538/* Exported macros -----------------------------------------------------------*/
548#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
549#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \
550 (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \
551 (__HANDLE__)->MspInitCallback = NULL; \
552 (__HANDLE__)->MspDeInitCallback = NULL; \
553 } while(0)
554#else
555#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
556#endif
557
562#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
563#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \
564 (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \
565 (__HANDLE__)->MspInitCallback = NULL; \
566 (__HANDLE__)->MspDeInitCallback = NULL; \
567 } while(0)
568#else
569#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
570#endif
571
575/* End of exported macros ----------------------------------------------------*/
576
577#if defined(DFSDM_CHDLYR_PLSSKP)
578/* Include DFSDM HAL Extension module */
579#include "stm32h7xx_hal_dfsdm_ex.h"
580#endif /* DFSDM_CHDLYR_PLSSKP */
581
582/* Exported functions --------------------------------------------------------*/
590/* Channel initialization and de-initialization functions *********************/
591HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
592HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
593void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
594void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
595
596#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
597/* Channel callbacks register/unregister functions ****************************/
598HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
599 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
600 pDFSDM_Channel_CallbackTypeDef pCallback);
601HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
602 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);
603#endif
611/* Channel operation functions ************************************************/
612HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
613HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
614HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
615HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
616
617HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
618HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
619HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
620HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
621
622int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
623HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
624
625HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
626HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
627
628void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
629void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
638/* Channel state function *****************************************************/
639HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
647/* Filter initialization and de-initialization functions *********************/
648HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
649HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
650void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
651void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
652
653#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
654/* Filter callbacks register/unregister functions ****************************/
655HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
656 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
657 pDFSDM_Filter_CallbackTypeDef pCallback);
658HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
659 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);
660HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
661 pDFSDM_Filter_AwdCallbackTypeDef pCallback);
662HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
663#endif
671/* Filter control functions *********************/
672HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
673 uint32_t Channel,
674 uint32_t ContinuousMode);
675HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
676 uint32_t Channel);
684/* Filter operation functions *********************/
685HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
686HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
687HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
688HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
689HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
690HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
691HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
692HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
693HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
694HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
695HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
696HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
697HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
698HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
699HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
700 const DFSDM_Filter_AwdParamTypeDef *awdParam);
701HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
702HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
703HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
704
705int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
706int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
707int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
708int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
709uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
710
711void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
712
713HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
714HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
715
716void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
717void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
718void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
719void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
720void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
721void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
730/* Filter state functions *****************************************************/
731HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
732uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
740/* End of exported functions -------------------------------------------------*/
741
742/* Private macros ------------------------------------------------------------*/
747#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
748 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
749#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
750#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
751 ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
752 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
753#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
754 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
755 ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
756#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
757 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
758#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
759 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
760 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
761 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
762#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
763 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
764 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
765 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
766#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
767 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
768 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
769 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
770#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U))
771#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
772#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU)
773#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU)
774#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
775 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
776#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
777 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
778 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
779#if (STM32H7_DEV_ID == 0x480UL)
780#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
781 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
782 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
783 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
784 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
785 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
786 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
787 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
788 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
789 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
790 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
791 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
792 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
793 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT) || \
794 ((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP1_OUT) || \
795 ((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP2_OUT))
796#elif (STM32H7_DEV_ID == 0x483UL)
797#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
798 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
799 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
800 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
801 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
802 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
803 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
804 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
805 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
806 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
807 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
808 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
809 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
810 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT) || \
811 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM23_TRGO) || \
812 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM24_TRGO))
813
814#else
815#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
816 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
817 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
818 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
819 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
820 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
821 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
822 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
823 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
824 ((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1) || \
825 ((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3) || \
826 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
827 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
828 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
829 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
830 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT))
831#endif /* STM32H7_DEV_ID == 0x480UL */
832#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
833 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
834 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
835#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
836 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
837 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
838 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
839 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
840 ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
841#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U))
842#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U))
843#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
844 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
845#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
846#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
847#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
848 ((CHANNEL) == DFSDM_CHANNEL_1) || \
849 ((CHANNEL) == DFSDM_CHANNEL_2) || \
850 ((CHANNEL) == DFSDM_CHANNEL_3) || \
851 ((CHANNEL) == DFSDM_CHANNEL_4) || \
852 ((CHANNEL) == DFSDM_CHANNEL_5) || \
853 ((CHANNEL) == DFSDM_CHANNEL_6) || \
854 ((CHANNEL) == DFSDM_CHANNEL_7))
855#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
856#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
857 ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
858#if defined(DFSDM2_Channel0)
859#define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
860 ((INSTANCE) == DFSDM1_Channel1) || \
861 ((INSTANCE) == DFSDM1_Channel2) || \
862 ((INSTANCE) == DFSDM1_Channel3) || \
863 ((INSTANCE) == DFSDM1_Channel4) || \
864 ((INSTANCE) == DFSDM1_Channel5) || \
865 ((INSTANCE) == DFSDM1_Channel6) || \
866 ((INSTANCE) == DFSDM1_Channel7))
867#define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
868 ((INSTANCE) == DFSDM1_Filter1) || \
869 ((INSTANCE) == DFSDM1_Filter2) || \
870 ((INSTANCE) == DFSDM1_Filter3) || \
871 ((INSTANCE) == DFSDM1_Filter4) || \
872 ((INSTANCE) == DFSDM1_Filter5) || \
873 ((INSTANCE) == DFSDM1_Filter6) || \
874 ((INSTANCE) == DFSDM1_Filter7))
875#endif /* DFSDM2_Channel0 */
879/* End of private macros -----------------------------------------------------*/
880
889#ifdef __cplusplus
890}
891#endif
892
893#endif /* STM32H7xx_HAL_DFSDM_H */
894
HAL_DFSDM_Channel_StateTypeDef
HAL_DFSDM_Channel_StateTypeDef
HAL DFSDM Channel states definition.
Definition: stm32h7xx_hal_dfsdm.h:48
HAL_DFSDM_Filter_StateTypeDef
HAL_DFSDM_Filter_StateTypeDef
HAL DFSDM Filter states definition.
Definition: stm32h7xx_hal_dfsdm.h:158
HAL_DFSDM_CHANNEL_STATE_READY
@ HAL_DFSDM_CHANNEL_STATE_READY
Definition: stm32h7xx_hal_dfsdm.h:50
HAL_DFSDM_CHANNEL_STATE_RESET
@ HAL_DFSDM_CHANNEL_STATE_RESET
Definition: stm32h7xx_hal_dfsdm.h:49
HAL_DFSDM_CHANNEL_STATE_ERROR
@ HAL_DFSDM_CHANNEL_STATE_ERROR
Definition: stm32h7xx_hal_dfsdm.h:51
HAL_DFSDM_FILTER_STATE_INJ
@ HAL_DFSDM_FILTER_STATE_INJ
Definition: stm32h7xx_hal_dfsdm.h:162
HAL_DFSDM_FILTER_STATE_ERROR
@ HAL_DFSDM_FILTER_STATE_ERROR
Definition: stm32h7xx_hal_dfsdm.h:164
HAL_DFSDM_FILTER_STATE_REG
@ HAL_DFSDM_FILTER_STATE_REG
Definition: stm32h7xx_hal_dfsdm.h:161
HAL_DFSDM_FILTER_STATE_REG_INJ
@ HAL_DFSDM_FILTER_STATE_REG_INJ
Definition: stm32h7xx_hal_dfsdm.h:163
HAL_DFSDM_FILTER_STATE_READY
@ HAL_DFSDM_FILTER_STATE_READY
Definition: stm32h7xx_hal_dfsdm.h:160
HAL_DFSDM_FILTER_STATE_RESET
@ HAL_DFSDM_FILTER_STATE_RESET
Definition: stm32h7xx_hal_dfsdm.h:159
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
stm32h7xx_hal_dfsdm_ex.h
Header file of DFSDM HAL extended module.
DFSDM_Channel_AwdTypeDef
DFSDM channel analog watchdog structure definition.
Definition: stm32h7xx_hal_dfsdm.h:94
DFSDM_Channel_AwdTypeDef::FilterOrder
uint32_t FilterOrder
Definition: stm32h7xx_hal_dfsdm.h:95
DFSDM_Channel_AwdTypeDef::Oversampling
uint32_t Oversampling
Definition: stm32h7xx_hal_dfsdm.h:97
DFSDM_Channel_HandleTypeDef
DFSDM channel handle structure definition.
Definition: stm32h7xx_hal_dfsdm.h:124
DFSDM_Channel_HandleTypeDef::Init
DFSDM_Channel_InitTypeDef Init
Definition: stm32h7xx_hal_dfsdm.h:126
DFSDM_Channel_HandleTypeDef::Instance
DFSDM_Channel_TypeDef * Instance
Definition: stm32h7xx_hal_dfsdm.h:125
DFSDM_Channel_HandleTypeDef::State
HAL_DFSDM_Channel_StateTypeDef State
Definition: stm32h7xx_hal_dfsdm.h:127
DFSDM_Channel_InitTypeDef
DFSDM channel init structure definition.
Definition: stm32h7xx_hal_dfsdm.h:105
DFSDM_Channel_InitTypeDef::Offset
int32_t Offset
Definition: stm32h7xx_hal_dfsdm.h:110
DFSDM_Channel_InitTypeDef::SerialInterface
DFSDM_Channel_SerialInterfaceTypeDef SerialInterface
Definition: stm32h7xx_hal_dfsdm.h:108
DFSDM_Channel_InitTypeDef::Input
DFSDM_Channel_InputTypeDef Input
Definition: stm32h7xx_hal_dfsdm.h:107
DFSDM_Channel_InitTypeDef::RightBitShift
uint32_t RightBitShift
Definition: stm32h7xx_hal_dfsdm.h:112
DFSDM_Channel_InitTypeDef::Awd
DFSDM_Channel_AwdTypeDef Awd
Definition: stm32h7xx_hal_dfsdm.h:109
DFSDM_Channel_InitTypeDef::OutputClock
DFSDM_Channel_OutputClockTypeDef OutputClock
Definition: stm32h7xx_hal_dfsdm.h:106
DFSDM_Channel_InputTypeDef
DFSDM channel input structure definition.
Definition: stm32h7xx_hal_dfsdm.h:70
DFSDM_Channel_InputTypeDef::Pins
uint32_t Pins
Definition: stm32h7xx_hal_dfsdm.h:75
DFSDM_Channel_InputTypeDef::DataPacking
uint32_t DataPacking
Definition: stm32h7xx_hal_dfsdm.h:73
DFSDM_Channel_InputTypeDef::Multiplexer
uint32_t Multiplexer
Definition: stm32h7xx_hal_dfsdm.h:71
DFSDM_Channel_OutputClockTypeDef
DFSDM channel output clock structure definition.
Definition: stm32h7xx_hal_dfsdm.h:58
DFSDM_Channel_OutputClockTypeDef::Activation
FunctionalState Activation
Definition: stm32h7xx_hal_dfsdm.h:59
DFSDM_Channel_OutputClockTypeDef::Selection
uint32_t Selection
Definition: stm32h7xx_hal_dfsdm.h:60
DFSDM_Channel_OutputClockTypeDef::Divider
uint32_t Divider
Definition: stm32h7xx_hal_dfsdm.h:62
DFSDM_Channel_SerialInterfaceTypeDef
DFSDM channel serial interface structure definition.
Definition: stm32h7xx_hal_dfsdm.h:83
DFSDM_Channel_SerialInterfaceTypeDef::SpiClock
uint32_t SpiClock
Definition: stm32h7xx_hal_dfsdm.h:86
DFSDM_Channel_SerialInterfaceTypeDef::Type
uint32_t Type
Definition: stm32h7xx_hal_dfsdm.h:84
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32h723xx.h:518
DFSDM_Filter_AwdParamTypeDef
DFSDM filter analog watchdog parameters structure definition.
Definition: stm32h7xx_hal_dfsdm.h:255
DFSDM_Filter_AwdParamTypeDef::LowThreshold
int32_t LowThreshold
Definition: stm32h7xx_hal_dfsdm.h:262
DFSDM_Filter_AwdParamTypeDef::HighBreakSignal
uint32_t HighBreakSignal
Definition: stm32h7xx_hal_dfsdm.h:264
DFSDM_Filter_AwdParamTypeDef::HighThreshold
int32_t HighThreshold
Definition: stm32h7xx_hal_dfsdm.h:260
DFSDM_Filter_AwdParamTypeDef::LowBreakSignal
uint32_t LowBreakSignal
Definition: stm32h7xx_hal_dfsdm.h:266
DFSDM_Filter_AwdParamTypeDef::Channel
uint32_t Channel
Definition: stm32h7xx_hal_dfsdm.h:258
DFSDM_Filter_AwdParamTypeDef::DataSource
uint32_t DataSource
Definition: stm32h7xx_hal_dfsdm.h:256
DFSDM_Filter_FilterParamTypeDef
DFSDM filter parameters structure definition.
Definition: stm32h7xx_hal_dfsdm.h:197
DFSDM_Filter_FilterParamTypeDef::IntOversampling
uint32_t IntOversampling
Definition: stm32h7xx_hal_dfsdm.h:202
DFSDM_Filter_FilterParamTypeDef::Oversampling
uint32_t Oversampling
Definition: stm32h7xx_hal_dfsdm.h:200
DFSDM_Filter_FilterParamTypeDef::SincOrder
uint32_t SincOrder
Definition: stm32h7xx_hal_dfsdm.h:198
DFSDM_Filter_HandleTypeDef
DFSDM filter handle structure definition.
Definition: stm32h7xx_hal_dfsdm.h:224
DFSDM_Filter_HandleTypeDef::RegularContMode
uint32_t RegularContMode
Definition: stm32h7xx_hal_dfsdm.h:229
DFSDM_Filter_HandleTypeDef::InjectedScanMode
FunctionalState InjectedScanMode
Definition: stm32h7xx_hal_dfsdm.h:233
DFSDM_Filter_HandleTypeDef::ExtTriggerEdge
uint32_t ExtTriggerEdge
Definition: stm32h7xx_hal_dfsdm.h:232
DFSDM_Filter_HandleTypeDef::ErrorCode
uint32_t ErrorCode
Definition: stm32h7xx_hal_dfsdm.h:237
DFSDM_Filter_HandleTypeDef::hdmaInj
DMA_HandleTypeDef * hdmaInj
Definition: stm32h7xx_hal_dfsdm.h:228
DFSDM_Filter_HandleTypeDef::hdmaReg
DMA_HandleTypeDef * hdmaReg
Definition: stm32h7xx_hal_dfsdm.h:227
DFSDM_Filter_HandleTypeDef::State
HAL_DFSDM_Filter_StateTypeDef State
Definition: stm32h7xx_hal_dfsdm.h:236
DFSDM_Filter_HandleTypeDef::InjConvRemaining
uint32_t InjConvRemaining
Definition: stm32h7xx_hal_dfsdm.h:235
DFSDM_Filter_HandleTypeDef::RegularTrigger
uint32_t RegularTrigger
Definition: stm32h7xx_hal_dfsdm.h:230
DFSDM_Filter_HandleTypeDef::Init
DFSDM_Filter_InitTypeDef Init
Definition: stm32h7xx_hal_dfsdm.h:226
DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr
uint32_t InjectedChannelsNbr
Definition: stm32h7xx_hal_dfsdm.h:234
DFSDM_Filter_HandleTypeDef::Instance
DFSDM_Filter_TypeDef * Instance
Definition: stm32h7xx_hal_dfsdm.h:225
DFSDM_Filter_HandleTypeDef::InjectedTrigger
uint32_t InjectedTrigger
Definition: stm32h7xx_hal_dfsdm.h:231
DFSDM_Filter_InitTypeDef
DFSDM filter init structure definition.
Definition: stm32h7xx_hal_dfsdm.h:210
DFSDM_Filter_InitTypeDef::RegularParam
DFSDM_Filter_RegularParamTypeDef RegularParam
Definition: stm32h7xx_hal_dfsdm.h:211
DFSDM_Filter_InitTypeDef::InjectedParam
DFSDM_Filter_InjectedParamTypeDef InjectedParam
Definition: stm32h7xx_hal_dfsdm.h:212
DFSDM_Filter_InitTypeDef::FilterParam
DFSDM_Filter_FilterParamTypeDef FilterParam
Definition: stm32h7xx_hal_dfsdm.h:213
DFSDM_Filter_InjectedParamTypeDef
DFSDM filter injected conversion parameters structure definition.
Definition: stm32h7xx_hal_dfsdm.h:182
DFSDM_Filter_InjectedParamTypeDef::ScanMode
FunctionalState ScanMode
Definition: stm32h7xx_hal_dfsdm.h:185
DFSDM_Filter_InjectedParamTypeDef::DmaMode
FunctionalState DmaMode
Definition: stm32h7xx_hal_dfsdm.h:186
DFSDM_Filter_InjectedParamTypeDef::ExtTriggerEdge
uint32_t ExtTriggerEdge
Definition: stm32h7xx_hal_dfsdm.h:189
DFSDM_Filter_InjectedParamTypeDef::Trigger
uint32_t Trigger
Definition: stm32h7xx_hal_dfsdm.h:183
DFSDM_Filter_InjectedParamTypeDef::ExtTrigger
uint32_t ExtTrigger
Definition: stm32h7xx_hal_dfsdm.h:187
DFSDM_Filter_RegularParamTypeDef
DFSDM filter regular conversion parameters structure definition.
Definition: stm32h7xx_hal_dfsdm.h:171
DFSDM_Filter_RegularParamTypeDef::FastMode
FunctionalState FastMode
Definition: stm32h7xx_hal_dfsdm.h:174
DFSDM_Filter_RegularParamTypeDef::Trigger
uint32_t Trigger
Definition: stm32h7xx_hal_dfsdm.h:172
DFSDM_Filter_RegularParamTypeDef::DmaMode
FunctionalState DmaMode
Definition: stm32h7xx_hal_dfsdm.h:175
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32h723xx.h:496
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32h7xx_hal_dma.h:138
Generated by doxygen 1.9.6