RTEMS 6.1-rc4
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This header file defines the SPWTDP register block interface. More...
#include <stdint.h>
Go to the source code of this file.
Data Structures | |
struct | spwtdp |
This structure defines the SPWTDP register block memory map. More... | |
Macros | |
#define | SPWTDP_CONF0_JE 0x1000000U |
#define | SPWTDP_CONF0_ST 0x200000U |
#define | SPWTDP_CONF0_EP 0x100000U |
#define | SPWTDP_CONF0_ET 0x80000U |
#define | SPWTDP_CONF0_SP 0x40000U |
#define | SPWTDP_CONF0_SE 0x20000U |
#define | SPWTDP_CONF0_LE 0x10000U |
#define | SPWTDP_CONF0_AE 0x8000U |
#define | SPWTDP_CONF0_MAPPING_SHIFT 8 |
#define | SPWTDP_CONF0_MAPPING_MASK 0x1f00U |
#define | SPWTDP_CONF0_MAPPING_GET(_reg) |
#define | SPWTDP_CONF0_MAPPING_SET(_reg, _val) |
#define | SPWTDP_CONF0_MAPPING(_val) |
#define | SPWTDP_CONF0_TD 0x80U |
#define | SPWTDP_CONF0_MU 0x40U |
#define | SPWTDP_CONF0_SEL_SHIFT 4 |
#define | SPWTDP_CONF0_SEL_MASK 0x30U |
#define | SPWTDP_CONF0_SEL_GET(_reg) |
#define | SPWTDP_CONF0_SEL_SET(_reg, _val) |
#define | SPWTDP_CONF0_SEL(_val) |
#define | SPWTDP_CONF0_ME 0x8U |
#define | SPWTDP_CONF0_RE 0x4U |
#define | SPWTDP_CONF0_TE 0x2U |
#define | SPWTDP_CONF0_RS 0x1U |
#define | SPWTDP_CONF3_STM_SHIFT 16 |
#define | SPWTDP_CONF3_STM_MASK 0x3f0000U |
#define | SPWTDP_CONF3_STM_GET(_reg) |
#define | SPWTDP_CONF3_STM_SET(_reg, _val) |
#define | SPWTDP_CONF3_STM(_val) |
#define | SPWTDP_CONF3_DI64R 0x2000U |
#define | SPWTDP_CONF3_DI64T 0x1000U |
#define | SPWTDP_CONF3_DI64 0x800U |
#define | SPWTDP_CONF3_DI 0x400U |
#define | SPWTDP_CONF3_INRX_SHIFT 5 |
#define | SPWTDP_CONF3_INRX_MASK 0x3e0U |
#define | SPWTDP_CONF3_INRX_GET(_reg) |
#define | SPWTDP_CONF3_INRX_SET(_reg, _val) |
#define | SPWTDP_CONF3_INRX(_val) |
#define | SPWTDP_CONF3_INTX_SHIFT 0 |
#define | SPWTDP_CONF3_INTX_MASK 0x1fU |
#define | SPWTDP_CONF3_INTX_GET(_reg) |
#define | SPWTDP_CONF3_INTX_SET(_reg, _val) |
#define | SPWTDP_CONF3_INTX(_val) |
#define | SPWTDP_CTRL_NC 0x80000000U |
#define | SPWTDP_CTRL_IS 0x40000000U |
#define | SPWTDP_CTRL_SPWTC_SHIFT 16 |
#define | SPWTDP_CTRL_SPWTC_MASK 0xff0000U |
#define | SPWTDP_CTRL_SPWTC_GET(_reg) |
#define | SPWTDP_CTRL_SPWTC_SET(_reg, _val) |
#define | SPWTDP_CTRL_SPWTC(_val) |
#define | SPWTDP_CTRL_CPF_SHIFT 0 |
#define | SPWTDP_CTRL_CPF_MASK 0xffffU |
#define | SPWTDP_CTRL_CPF_GET(_reg) |
#define | SPWTDP_CTRL_CPF_SET(_reg, _val) |
#define | SPWTDP_CTRL_CPF(_val) |
#define | SPWTDP_CET0_CET0_SHIFT 0 |
#define | SPWTDP_CET0_CET0_MASK 0xffffffffU |
#define | SPWTDP_CET0_CET0_GET(_reg) |
#define | SPWTDP_CET0_CET0_SET(_reg, _val) |
#define | SPWTDP_CET0_CET0(_val) |
#define | SPWTDP_CET1_CET1_SHIFT 0 |
#define | SPWTDP_CET1_CET1_MASK 0xffffffffU |
#define | SPWTDP_CET1_CET1_GET(_reg) |
#define | SPWTDP_CET1_CET1_SET(_reg, _val) |
#define | SPWTDP_CET1_CET1(_val) |
#define | SPWTDP_CET2_CET2_SHIFT 0 |
#define | SPWTDP_CET2_CET2_MASK 0xffffffffU |
#define | SPWTDP_CET2_CET2_GET(_reg) |
#define | SPWTDP_CET2_CET2_SET(_reg, _val) |
#define | SPWTDP_CET2_CET2(_val) |
#define | SPWTDP_CET3_CET3_SHIFT 0 |
#define | SPWTDP_CET3_CET3_MASK 0xffffffffU |
#define | SPWTDP_CET3_CET3_GET(_reg) |
#define | SPWTDP_CET3_CET3_SET(_reg, _val) |
#define | SPWTDP_CET3_CET3(_val) |
#define | SPWTDP_CET4_CET4_SHIFT 24 |
#define | SPWTDP_CET4_CET4_MASK 0xff000000U |
#define | SPWTDP_CET4_CET4_GET(_reg) |
#define | SPWTDP_CET4_CET4_SET(_reg, _val) |
#define | SPWTDP_CET4_CET4(_val) |
#define | SPWTDP_DPF_DPF_SHIFT 0 |
#define | SPWTDP_DPF_DPF_MASK 0xffffU |
#define | SPWTDP_DPF_DPF_GET(_reg) |
#define | SPWTDP_DPF_DPF_SET(_reg, _val) |
#define | SPWTDP_DPF_DPF(_val) |
#define | SPWTDP_DET0_DET0_SHIFT 0 |
#define | SPWTDP_DET0_DET0_MASK 0xffffffffU |
#define | SPWTDP_DET0_DET0_GET(_reg) |
#define | SPWTDP_DET0_DET0_SET(_reg, _val) |
#define | SPWTDP_DET0_DET0(_val) |
#define | SPWTDP_DET1_DET1_SHIFT 0 |
#define | SPWTDP_DET1_DET1_MASK 0xffffffffU |
#define | SPWTDP_DET1_DET1_GET(_reg) |
#define | SPWTDP_DET1_DET1_SET(_reg, _val) |
#define | SPWTDP_DET1_DET1(_val) |
#define | SPWTDP_DET2_DET2_SHIFT 0 |
#define | SPWTDP_DET2_DET2_MASK 0xffffffffU |
#define | SPWTDP_DET2_DET2_GET(_reg) |
#define | SPWTDP_DET2_DET2_SET(_reg, _val) |
#define | SPWTDP_DET2_DET2(_val) |
#define | SPWTDP_DET3_DET3_SHIFT 0 |
#define | SPWTDP_DET3_DET3_MASK 0xffffffffU |
#define | SPWTDP_DET3_DET3_GET(_reg) |
#define | SPWTDP_DET3_DET3_SET(_reg, _val) |
#define | SPWTDP_DET3_DET3(_val) |
#define | SPWTDP_DET4_DET4_SHIFT 24 |
#define | SPWTDP_DET4_DET4_MASK 0xff000000U |
#define | SPWTDP_DET4_DET4_GET(_reg) |
#define | SPWTDP_DET4_DET4_SET(_reg, _val) |
#define | SPWTDP_DET4_DET4(_val) |
#define | SPWTDP_TRPFRX_TRPF_SHIFT 0 |
#define | SPWTDP_TRPFRX_TRPF_MASK 0xffffU |
#define | SPWTDP_TRPFRX_TRPF_GET(_reg) |
#define | SPWTDP_TRPFRX_TRPF_SET(_reg, _val) |
#define | SPWTDP_TRPFRX_TRPF(_val) |
#define | SPWTDP_TR0_TR0_SHIFT 0 |
#define | SPWTDP_TR0_TR0_MASK 0xffffffffU |
#define | SPWTDP_TR0_TR0_GET(_reg) |
#define | SPWTDP_TR0_TR0_SET(_reg, _val) |
#define | SPWTDP_TR0_TR0(_val) |
#define | SPWTDP_TR1_TR1_SHIFT 0 |
#define | SPWTDP_TR1_TR1_MASK 0xffffffffU |
#define | SPWTDP_TR1_TR1_GET(_reg) |
#define | SPWTDP_TR1_TR1_SET(_reg, _val) |
#define | SPWTDP_TR1_TR1(_val) |
#define | SPWTDP_TR2_TR2_SHIFT 0 |
#define | SPWTDP_TR2_TR2_MASK 0xffffffffU |
#define | SPWTDP_TR2_TR2_GET(_reg) |
#define | SPWTDP_TR2_TR2_SET(_reg, _val) |
#define | SPWTDP_TR2_TR2(_val) |
#define | SPWTDP_TR3_TR3_SHIFT 0 |
#define | SPWTDP_TR3_TR3_MASK 0xffffffffU |
#define | SPWTDP_TR3_TR3_GET(_reg) |
#define | SPWTDP_TR3_TR3_SET(_reg, _val) |
#define | SPWTDP_TR3_TR3(_val) |
#define | SPWTDP_TR4_TR4_SHIFT 24 |
#define | SPWTDP_TR4_TR4_MASK 0xff000000U |
#define | SPWTDP_TR4_TR4_GET(_reg) |
#define | SPWTDP_TR4_TR4_SET(_reg, _val) |
#define | SPWTDP_TR4_TR4(_val) |
#define | SPWTDP_TTPFTX_TSTC_SHIFT 24 |
#define | SPWTDP_TTPFTX_TSTC_MASK 0xff000000U |
#define | SPWTDP_TTPFTX_TSTC_GET(_reg) |
#define | SPWTDP_TTPFTX_TSTC_SET(_reg, _val) |
#define | SPWTDP_TTPFTX_TSTC(_val) |
#define | SPWTDP_TTPFTX_TTPF_SHIFT 0 |
#define | SPWTDP_TTPFTX_TTPF_MASK 0xffffU |
#define | SPWTDP_TTPFTX_TTPF_GET(_reg) |
#define | SPWTDP_TTPFTX_TTPF_SET(_reg, _val) |
#define | SPWTDP_TTPFTX_TTPF(_val) |
#define | SPWTDP_TT0_TT0_SHIFT 0 |
#define | SPWTDP_TT0_TT0_MASK 0xffffffffU |
#define | SPWTDP_TT0_TT0_GET(_reg) |
#define | SPWTDP_TT0_TT0_SET(_reg, _val) |
#define | SPWTDP_TT0_TT0(_val) |
#define | SPWTDP_TT1_TT1_SHIFT 0 |
#define | SPWTDP_TT1_TT1_MASK 0xffffffffU |
#define | SPWTDP_TT1_TT1_GET(_reg) |
#define | SPWTDP_TT1_TT1_SET(_reg, _val) |
#define | SPWTDP_TT1_TT1(_val) |
#define | SPWTDP_TT2_TT2_SHIFT 0 |
#define | SPWTDP_TT2_TT2_MASK 0xffffffffU |
#define | SPWTDP_TT2_TT2_GET(_reg) |
#define | SPWTDP_TT2_TT2_SET(_reg, _val) |
#define | SPWTDP_TT2_TT2(_val) |
#define | SPWTDP_TT3_TT3_SHIFT 0 |
#define | SPWTDP_TT3_TT3_MASK 0xffffffffU |
#define | SPWTDP_TT3_TT3_GET(_reg) |
#define | SPWTDP_TT3_TT3_SET(_reg, _val) |
#define | SPWTDP_TT3_TT3(_val) |
#define | SPWTDP_TT4_TT4_SHIFT 24 |
#define | SPWTDP_TT4_TT4_MASK 0xff000000U |
#define | SPWTDP_TT4_TT4_GET(_reg) |
#define | SPWTDP_TT4_TT4_SET(_reg, _val) |
#define | SPWTDP_TT4_TT4(_val) |
#define | SPWTDP_LPF_LPF_SHIFT 0 |
#define | SPWTDP_LPF_LPF_MASK 0xffffU |
#define | SPWTDP_LPF_LPF_GET(_reg) |
#define | SPWTDP_LPF_LPF_SET(_reg, _val) |
#define | SPWTDP_LPF_LPF(_val) |
#define | SPWTDP_IE_NCTCE 0x80000U |
#define | SPWTDP_IE_SETE 0x400U |
#define | SPWTDP_IE_EDIE3 0x200U |
#define | SPWTDP_IE_EDIE2 0x100U |
#define | SPWTDP_IE_EDIE1 0x80U |
#define | SPWTDP_IE_EDIE0 0x40U |
#define | SPWTDP_IE_DITE 0x20U |
#define | SPWTDP_IE_DIRE 0x10U |
#define | SPWTDP_IE_TTE 0x8U |
#define | SPWTDP_IE_TME 0x4U |
#define | SPWTDP_IE_TRE 0x2U |
#define | SPWTDP_IE_SE 0x1U |
#define | SPWTDP_DC_DC_SHIFT 0 |
#define | SPWTDP_DC_DC_MASK 0x7fffU |
#define | SPWTDP_DC_DC_GET(_reg) |
#define | SPWTDP_DC_DC_SET(_reg, _val) |
#define | SPWTDP_DC_DC(_val) |
#define | SPWTDP_DS_EN 0x80000000U |
#define | SPWTDP_DS_CD_SHIFT 0 |
#define | SPWTDP_DS_CD_MASK 0xffffffU |
#define | SPWTDP_DS_CD_GET(_reg) |
#define | SPWTDP_DS_CD_SET(_reg, _val) |
#define | SPWTDP_DS_CD(_val) |
#define | SPWTDP_EDM0_EDM0_SHIFT 0 |
#define | SPWTDP_EDM0_EDM0_MASK 0xffffffffU |
#define | SPWTDP_EDM0_EDM0_GET(_reg) |
#define | SPWTDP_EDM0_EDM0_SET(_reg, _val) |
#define | SPWTDP_EDM0_EDM0(_val) |
#define | SPWTDP_EDPF0_EDPF0_SHIFT 0 |
#define | SPWTDP_EDPF0_EDPF0_MASK 0xffffU |
#define | SPWTDP_EDPF0_EDPF0_GET(_reg) |
#define | SPWTDP_EDPF0_EDPF0_SET(_reg, _val) |
#define | SPWTDP_EDPF0_EDPF0(_val) |
#define | SPWTDP_ED0ET0_ED0ET0_SHIFT 0 |
#define | SPWTDP_ED0ET0_ED0ET0_MASK 0xffffffffU |
#define | SPWTDP_ED0ET0_ED0ET0_GET(_reg) |
#define | SPWTDP_ED0ET0_ED0ET0_SET(_reg, _val) |
#define | SPWTDP_ED0ET0_ED0ET0(_val) |
#define | SPWTDP_ED0ET1_ED0ET1_SHIFT 0 |
#define | SPWTDP_ED0ET1_ED0ET1_MASK 0xffffffffU |
#define | SPWTDP_ED0ET1_ED0ET1_GET(_reg) |
#define | SPWTDP_ED0ET1_ED0ET1_SET(_reg, _val) |
#define | SPWTDP_ED0ET1_ED0ET1(_val) |
#define | SPWTDP_ED0ET2_ED0ET2_SHIFT 0 |
#define | SPWTDP_ED0ET2_ED0ET2_MASK 0xffffffffU |
#define | SPWTDP_ED0ET2_ED0ET2_GET(_reg) |
#define | SPWTDP_ED0ET2_ED0ET2_SET(_reg, _val) |
#define | SPWTDP_ED0ET2_ED0ET2(_val) |
#define | SPWTDP_ED0ET3_ED0ET3_SHIFT 0 |
#define | SPWTDP_ED0ET3_ED0ET3_MASK 0xffffffffU |
#define | SPWTDP_ED0ET3_ED0ET3_GET(_reg) |
#define | SPWTDP_ED0ET3_ED0ET3_SET(_reg, _val) |
#define | SPWTDP_ED0ET3_ED0ET3(_val) |
#define | SPWTDP_ED0ET4_ED0ET4_SHIFT 24 |
#define | SPWTDP_ED0ET4_ED0ET4_MASK 0xff000000U |
#define | SPWTDP_ED0ET4_ED0ET4_GET(_reg) |
#define | SPWTDP_ED0ET4_ED0ET4_SET(_reg, _val) |
#define | SPWTDP_ED0ET4_ED0ET4(_val) |
Typedefs | |
typedef struct spwtdp | spwtdp |
This structure defines the SPWTDP register block memory map. | |
This header file defines the SPWTDP register block interface.