RTEMS 6.1-rc4
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reg_rti.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/* The header file is generated by make_header.py from RTI.json */
12/* Current script's version can be found at: */
13/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
14
15/*
16 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
17 *
18 * Czech Technical University in Prague
19 * Zikova 1903/4
20 * 166 36 Praha 6
21 * Czech Republic
22 *
23 * All rights reserved.
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following disclaimer in the documentation
32 * and/or other materials provided with the distribution.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
38 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
40 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
41 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
43 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * The views and conclusions contained in the software and documentation are those
46 * of the authors and should not be interpreted as representing official policies,
47 * either expressed or implied, of the FreeBSD Project.
48*/
49#ifndef LIBBSP_ARM_TMS570_RTI
50#define LIBBSP_ARM_TMS570_RTI
51
52#include <bsp/utility.h>
53
54typedef struct{
55 uint32_t COMPx; /*RTI Compare x Register*/
56 uint32_t UDCPx; /*RTI Update Compare x Register*/
58
59typedef struct{
60 uint32_t FRCx; /*RTI Free Running Counter x Register*/
61 uint32_t UCx; /*RTI Up Counter x Register*/
62 uint32_t CPUCx; /*RTI Compare Up Counter x Register*/
63 uint8_t reserved1 [4];
64 uint32_t CAFRCx; /*RTI Capture Free Running Counter x Register*/
65 uint32_t CAUCx; /*RTI Capture Up Counter x Register*/
66 uint32_t rsvd[2]; /*Reserved*/
68
69typedef struct{
70 uint32_t GCTRL; /*RTI Global Control Register*/
71 uint32_t TBCTRL; /*RTI Timebase Control Register*/
72 uint32_t CAPCTRL; /*RTI Capture Control Register*/
73 uint32_t COMPCTRL; /*RTI Compare Control Register*/
74 tms570_rti_counter_t CNT[2];/*Counters*/
75 tms570_rti_compare_t CMP[4];/*Compares*/
76 uint32_t TBLCOMP; /*RTI Timebase Low Compare Register*/
77 uint32_t TBHCOMP; /*RTI Timebase High Compare Register*/
78 uint8_t reserved2 [8];
79 uint32_t SETINTENA; /*RTI Set Interrupt Enable Register*/
80 uint32_t CLEARINTENA; /*RTI Clear Interrupt Enable Register*/
81 uint32_t INTFLAG; /*RTI Interrupt Flag Register*/
82 uint8_t reserved3 [4];
83 uint32_t DWDCTRL; /*Digital Watchdog Control Register*/
84 uint32_t DWDPRLD; /*Digital Watchdog Preload Register*/
85 uint32_t WDSTATUS; /*Watchdog Status Register*/
86 uint32_t WDKEY; /*RTI Watchdog Key Register*/
87 uint32_t DWDCNTR; /*RTI Digital Watchdog Down Counter Register*/
88 uint32_t WWDRXNCTRL; /*Digital Windowed Watchdog Reaction Control Register*/
89 uint32_t WWDSIZECTRL; /*Digital Windowed Watchdog Window Size Control Register*/
90 uint32_t INTCLRENABLE; /*RTI Compare Interrupt Clear Enable Register*/
91 uint32_t COMP0CLR; /*RTI Compare 0 Clear Register*/
92 uint32_t COMP1CLR; /*RTI Compare 1 Clear Register*/
93 uint32_t COMP2CLR; /*RTI Compare 2 Clear Register*/
94 uint32_t COMP3CLR; /*RTI Compare 3 Clear Register*/
96
97
98/*----------------------TMS570_RTI_COMPx----------------------*/
99/* field: COMPx - Compare x. */
100/* Whole 32 bits */
101
102/*----------------------TMS570_RTI_UDCPx----------------------*/
103/* field: UDCPx - Update compare x. */
104/* Whole 32 bits */
105
106/*----------------------TMS570_RTI_FRCx----------------------*/
107/* field: FRC0 - FRC0 */
108/* Whole 32 bits */
109
110/*-----------------------TMS570_RTI_UCx-----------------------*/
111/* field: UC0 - Up counter 0. */
112/* Whole 32 bits */
113
114/*----------------------TMS570_RTI_CPUCx----------------------*/
115/* field: CPUC0 - Compare up counter 0. This register holds the value that is compared with the up counter 0. */
116/* Whole 32 bits */
117
118/*---------------------TMS570_RTI_CAFRCx---------------------*/
119/* field: CAFRC0 - Capture free running counter 0. */
120/* Whole 32 bits */
121
122/*----------------------TMS570_RTI_CAUCx----------------------*/
123/* field: CAUC0 - Capture up counter 0. */
124/* Whole 32 bits */
125
126/*----------------------TMS570_RTI_rsvd----------------------*/
127/* field: CAUC0 - Capture up counter 0. */
128/* Whole 32 bits */
129
130/*----------------------TMS570_RTI_GCTRL----------------------*/
131/* field: NTUSEL - Select NTU signal. */
132#define TMS570_RTI_GCTRL_NTUSEL(val) BSP_FLD32(val,16, 19)
133#define TMS570_RTI_GCTRL_NTUSEL_GET(reg) BSP_FLD32GET(reg,16, 19)
134#define TMS570_RTI_GCTRL_NTUSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
135
136/* field: COS - Continue on suspend. */
137#define TMS570_RTI_GCTRL_COS BSP_BIT32(15)
138
139/* field: CNT1EN - Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1). */
140#define TMS570_RTI_GCTRL_CNT1EN BSP_BIT32(1)
141
142/* field: CNT0EN - Counter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0). */
143#define TMS570_RTI_GCTRL_CNT0EN BSP_BIT32(0)
144
145
146/*---------------------TMS570_RTI_TBCTRL---------------------*/
147/* field: INC - Increment free running counter 0. */
148#define TMS570_RTI_TBCTRL_INC BSP_BIT32(1)
149
150/* field: TBEXT - Timebase external. */
151#define TMS570_RTI_TBCTRL_TBEXT BSP_BIT32(0)
152
153
154/*---------------------TMS570_RTI_CAPCTRL---------------------*/
155/* field: CAPCNTR1 - Capture counter 1. */
156#define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_BIT32(1)
157
158/* field: CAPCNTR0 - Capture counter 0. */
159#define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_BIT32(0)
160
161
162/*--------------------TMS570_RTI_COMPCTRL--------------------*/
163/* field: COMPSEL3 - Compare select 3. */
164#define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_BIT32(12)
165
166/* field: COMPSEL2 - Compare select 2. */
167#define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_BIT32(8)
168
169/* field: COMPSEL1 - Compare select 1. */
170#define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_BIT32(4)
171
172/* field: COMPSEL0 - Compare select 0. */
173#define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_BIT32(0)
174
175
176/*---------------------TMS570_RTI_TBLCOMP---------------------*/
177/* field: TBLCOMP - Timebase low compare value. */
178/* Whole 32 bits */
179
180/*---------------------TMS570_RTI_TBHCOMP---------------------*/
181/* field: TBHCOMP - Timebase high compare value. */
182/* Whole 32 bits */
183
184/*--------------------TMS570_RTI_SETINTENA--------------------*/
185/* field: SETOVL1INT - Set free running counter 1 overflow interrupt. */
186#define TMS570_RTI_SETINTENA_SETOVL1INT BSP_BIT32(18)
187
188/* field: SETOVL0INT - Set free running counter 0 overflow interrupt. */
189#define TMS570_RTI_SETINTENA_SETOVL0INT BSP_BIT32(17)
190
191/* field: SETTBINT - Set timebase interrupt. */
192#define TMS570_RTI_SETINTENA_SETTBINT BSP_BIT32(16)
193
194/* field: SETDMA3 - Set compare DMA request 3. */
195#define TMS570_RTI_SETINTENA_SETDMA3 BSP_BIT32(11)
196
197/* field: SETDMA2 - Set compare DMA request 2. */
198#define TMS570_RTI_SETINTENA_SETDMA2 BSP_BIT32(10)
199
200/* field: SETDMA1 - Set compare DMA request 1. */
201#define TMS570_RTI_SETINTENA_SETDMA1 BSP_BIT32(9)
202
203/* field: SETDMA0 - Set compare DMA request 0. */
204#define TMS570_RTI_SETINTENA_SETDMA0 BSP_BIT32(8)
205
206/* field: SETINT3 - Set compare interrupt 3. */
207#define TMS570_RTI_SETINTENA_SETINT3 BSP_BIT32(3)
208
209/* field: SETINT2 - Set compare interrupt 2. */
210#define TMS570_RTI_SETINTENA_SETINT2 BSP_BIT32(2)
211
212/* field: SETINT1 - Set compare interrupt 1. */
213#define TMS570_RTI_SETINTENA_SETINT1 BSP_BIT32(1)
214
215/* field: SETINT0 - Set compare interrupt 0. */
216#define TMS570_RTI_SETINTENA_SETINT0 BSP_BIT32(0)
217
218
219/*-------------------TMS570_RTI_CLEARINTENA-------------------*/
220/* field: CLEAROVL1INT - Clear free running counter 1 overflow interrupt. */
221#define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_BIT32(18)
222
223/* field: CLEAROVL0INT - Clear free running counter 0 overflow interrupt. */
224#define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_BIT32(17)
225
226/* field: CLEARTBINT - Clear timebase interrupt. */
227#define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_BIT32(16)
228
229/* field: CLEARDMA3 - Clear compare DMA request 3. */
230#define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_BIT32(11)
231
232/* field: CLEARDMA2 - Clear compare DMA request 2. */
233#define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_BIT32(10)
234
235/* field: CLEARDMA1 - Clear compare DMA request 1. */
236#define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_BIT32(9)
237
238/* field: CLEARDMA0 - Clear compare DMA request 0. */
239#define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_BIT32(8)
240
241/* field: CLEARINT3 - Clear compare interrupt 3. */
242#define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_BIT32(3)
243
244/* field: CLEARINT2 - Clear compare interrupt 2. */
245#define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_BIT32(2)
246
247/* field: CLEARINT1 - Clear compare interrupt 1. */
248#define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_BIT32(1)
249
250/* field: CLEARINT0 - Clear compare interrupt 0. */
251#define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_BIT32(0)
252
253
254/*---------------------TMS570_RTI_INTFLAG---------------------*/
255/* field: OVL1INT - Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending. */
256#define TMS570_RTI_INTFLAG_OVL1INT BSP_BIT32(18)
257
258/* field: OVL0INT - Free running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending. */
259#define TMS570_RTI_INTFLAG_OVL0INT BSP_BIT32(17)
260
261/* field: TBINT - Timebase interrupt flag. */
262#define TMS570_RTI_INTFLAG_TBINT BSP_BIT32(16)
263
264/* field: INT3 - Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending. */
265#define TMS570_RTI_INTFLAG_INT3 BSP_BIT32(3)
266
267/* field: INT2 - Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending. */
268#define TMS570_RTI_INTFLAG_INT2 BSP_BIT32(2)
269
270/* field: INT1 - Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. */
271#define TMS570_RTI_INTFLAG_INT1 BSP_BIT32(1)
272
273/* field: INT0 - Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending. */
274#define TMS570_RTI_INTFLAG_INT0 BSP_BIT32(0)
275
276
277/*---------------------TMS570_RTI_DWDCTRL---------------------*/
278/* field: DWDCTRL - DWDCTRL Digital Watchdog Control. */
279/* Whole 32 bits */
280
281/*---------------------TMS570_RTI_DWDPRLD---------------------*/
282/* field: DWDPRLD - Digital Watchdog Preload Value. */
283#define TMS570_RTI_DWDPRLD_DWDPRLD(val) BSP_FLD32(val,0, 15)
284#define TMS570_RTI_DWDPRLD_DWDPRLD_GET(reg) BSP_FLD32GET(reg,0, 15)
285#define TMS570_RTI_DWDPRLD_DWDPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
286
287
288/*--------------------TMS570_RTI_WDSTATUS--------------------*/
289/* field: DWWD_ST - Windowed Watchdog Status */
290#define TMS570_RTI_WDSTATUS_DWWD_ST BSP_BIT32(5)
291
292/* field: END_TIME_VIOL - Windowed Watchdog End Time Violation Status. */
293#define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_BIT32(4)
294
295/* field: START_TIME_VIOL - Windowed Watchdog Start Time Violation Status. */
296#define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_BIT32(3)
297
298/* field: KEY_ST - Watchdog key status. */
299#define TMS570_RTI_WDSTATUS_KEY_ST BSP_BIT32(2)
300
301/* field: DWD_ST - DWD status. */
302#define TMS570_RTI_WDSTATUS_DWD_ST BSP_BIT32(1)
303
304
305/*----------------------TMS570_RTI_WDKEY----------------------*/
306/* field: WDKEY - Watchdog key. These bits provide the key sequence location. */
307#define TMS570_RTI_WDKEY_WDKEY(val) BSP_FLD32(val,0, 15)
308#define TMS570_RTI_WDKEY_WDKEY_GET(reg) BSP_FLD32GET(reg,0, 15)
309#define TMS570_RTI_WDKEY_WDKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
310
311
312/*---------------------TMS570_RTI_DWDCNTR---------------------*/
313/* field: DWDCNTR - DWD down counter. */
314#define TMS570_RTI_DWDCNTR_DWDCNTR(val) BSP_FLD32(val,0, 24)
315#define TMS570_RTI_DWDCNTR_DWDCNTR_GET(reg) BSP_FLD32GET(reg,0, 24)
316#define TMS570_RTI_DWDCNTR_DWDCNTR_SET(reg,val) BSP_FLD32SET(reg, val,0, 24)
317
318
319/*-------------------TMS570_RTI_WWDRXNCTRL-------------------*/
320/* field: WWDRXN - The DWWD reaction */
321#define TMS570_RTI_WWDRXNCTRL_WWDRXN(val) BSP_FLD32(val,0, 3)
322#define TMS570_RTI_WWDRXNCTRL_WWDRXN_GET(reg) BSP_FLD32GET(reg,0, 3)
323#define TMS570_RTI_WWDRXNCTRL_WWDRXN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
324
325
326/*-------------------TMS570_RTI_WWDSIZECTRL-------------------*/
327/* field: WWDSIZE - The DWWD window size */
328/* Whole 32 bits */
329
330/*------------------TMS570_RTI_INTCLRENABLE------------------*/
331/* field: INTCLRENABLE3 - Enables the auto-clear functionality on the compare 3 interrupt. */
332#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3(val) BSP_FLD32(val,24, 27)
333#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_GET(reg) BSP_FLD32GET(reg,24, 27)
334#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
335
336/* field: INTCLRENABLE2 - Enables the auto-clear functionality on the compare 2 interrupt. */
337#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2(val) BSP_FLD32(val,16, 19)
338#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_GET(reg) BSP_FLD32GET(reg,16, 19)
339#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
340
341/* field: INTCLRENABLE1 - Enables the auto-clear functionality on the compare 1 interrupt. */
342#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1(val) BSP_FLD32(val,8, 11)
343#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_GET(reg) BSP_FLD32GET(reg,8, 11)
344#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
345
346/* field: INTCLRENABLE0 - Enables the auto-clear functionality on the compare 0 interrupt. */
347#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0(val) BSP_FLD32(val,0, 3)
348#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_GET(reg) BSP_FLD32GET(reg,0, 3)
349#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
350
351
352/*--------------------TMS570_RTI_COMP0CLR--------------------*/
353/* field: CMP0CLR - Compare 0 clear. */
354/* Whole 32 bits */
355
356/*--------------------TMS570_RTI_COMP1CLR--------------------*/
357/* field: CMP0CLR - Compare 1 clear. */
358/* Whole 32 bits */
359
360/*--------------------TMS570_RTI_COMP2CLR--------------------*/
361/* field: CMP2CLR - Compare 2 clear. */
362/* Whole 32 bits */
363
364/*--------------------TMS570_RTI_COMP3CLR--------------------*/
365/* field: CMP3CLR - Compare 3 clear. */
366/* Whole 32 bits */
367
368
369#endif /* LIBBSP_ARM_TMS570_RTI */
This header file provides utility macros for BSPs.
Definition: reg_rti.h:54
Definition: reg_rti.h:59
Definition: reg_rti.h:69