RTEMS 6.1-rc4
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reg_pll.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/* The header file is generated by make_header.py from PLL.json */
12/* Current script's version can be found at: */
13/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
14
15/*
16 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
17 *
18 * Czech Technical University in Prague
19 * Zikova 1903/4
20 * 166 36 Praha 6
21 * Czech Republic
22 *
23 * All rights reserved.
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following disclaimer in the documentation
32 * and/or other materials provided with the distribution.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
38 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
40 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
41 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
43 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * The views and conclusions contained in the software and documentation are those
46 * of the authors and should not be interpreted as representing official policies,
47 * either expressed or implied, of the FreeBSD Project.
48*/
49#ifndef LIBBSP_ARM_TMS570_PLL
50#define LIBBSP_ARM_TMS570_PLL
51
52#include <bsp/utility.h>
53
54typedef struct{
55 uint32_t PLLCTL3; /*PLL Control 3 Register*/
56 uint8_t reserved1 [108];
57 uint32_t CLKSLIP; /*PLL Clock Slip Control Register*/
58 uint8_t reserved2 [7600];
59 uint32_t SSWPLL1; /*PLL Modulation Depth Measurement Control Register*/
60 uint32_t SSWPLL2; /*SSW PLL BIST Control Register 2*/
61 uint32_t SSWPLL3; /*SSW PLL BIST Control Register 3*/
62 uint32_t CSDIS; /*Clock Source Disable Register*/
63 uint32_t CSDISSET; /*Clock Source Disable Set Register*/
64 uint32_t CSDISCLR; /*Clock Source Disable Clear Register*/
65 uint8_t reserved3 [24];
66 uint32_t CSVSTAT; /*Clock Source Valid Status Register*/
67 uint8_t reserved4 [24];
68 uint32_t PLLCTL1; /*PLL Control 1 Register*/
69 uint32_t PLLCTL2; /*PLL Control 2 Register*/
70 uint8_t reserved5 [16];
71 uint32_t LPOMONCTL; /*LPO/Clock Monitor Control Register*/
72 uint32_t CLKTEST; /*Clock Test Register*/
73 uint8_t reserved6 [16];
74 uint32_t GPREG1; /*General Purpose Register*/
75 uint8_t reserved7 [72];
76 uint32_t GLBSTAT; /*Global Status Register*/
78
79
80/*---------------------TMS570_PLL_PLLCTL3---------------------*/
81/* field: ODPLL2 - Internal PLL Output Divider */
82#define TMS570_PLL_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
83#define TMS570_PLL_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
84#define TMS570_PLL_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31)
85
86/* field: PLLDIV2 - PLL2 Output Clock Divider */
87#define TMS570_PLL_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28)
88#define TMS570_PLL_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28)
89#define TMS570_PLL_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
90
91/* field: REFCLKDIV2 - Reference Clock Divider */
92#define TMS570_PLL_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21)
93#define TMS570_PLL_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21)
94#define TMS570_PLL_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
95
96/* field: PLLMUL2 - PLL2 Multiplication Factor */
97#define TMS570_PLL_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15)
98#define TMS570_PLL_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15)
99#define TMS570_PLL_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
100
101
102/*---------------------TMS570_PLL_CLKSLIP---------------------*/
103/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
104#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
105#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
106#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
107
108/* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */
109#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3)
110#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
111#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
112
113
114/*---------------------TMS570_PLL_SSWPLL1---------------------*/
115/* field: CAPTURE_WINDOW_INDEX - The capture counter present in the PLL wrapper will count the PLL clock edges when */
116#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX(val) BSP_FLD32(val,8, 15)
117#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_GET(reg) BSP_FLD32GET(reg,8, 15)
118#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
119
120/* field: COUNTER_READ_READY - Counter read ready. */
121#define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_BIT32(6)
122
123/* field: COUNTER_RESET - Counter reset. */
124#define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_BIT32(5)
125
126/* field: COUNTER_EN - Counter enable. */
127#define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_BIT32(4)
128
129/* field: TAP_COUNTER_DIS - The value in this register is used to program a particular bit in CLKOUT counter. */
130#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS(val) BSP_FLD32(val,1, 3)
131#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_GET(reg) BSP_FLD32GET(reg,1, 3)
132#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_SET(reg,val) BSP_FLD32SET(reg, val,1, 3)
133
134/* field: EXT_COUNTER_EN - Modulation Depth Measurement mode */
135#define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_BIT32(0)
136
137
138/*---------------------TMS570_PLL_SSWPLL2---------------------*/
139/* field: SSW_CAPTURE_COUNT - Capture count. This register returns the value of the capture count. */
140/* Whole 32 bits */
141
142/*---------------------TMS570_PLL_SSWPLL3---------------------*/
143/* field: SSW_CAPTURE_COUNT - Value of CLKout count register. */
144/* Whole 32 bits */
145
146/*----------------------TMS570_PLL_CSDIS----------------------*/
147/* field: CLKSR_7_3_OFF - Clock source[7-3] off. */
148#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
149#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
150#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
151
152/* field: CLKSR_1_0_OFF - Clock source[1-0] off. */
153#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
154#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
155#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
156
157
158/*--------------------TMS570_PLL_CSDISSET--------------------*/
159/* field: SETCLKSR_7_3_OFF - Set clock source[7-3] to the disabled state. */
160#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
161#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
162#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
163
164/* field: SETCLKSR_1_0_OFF - Set clock source[1-0] to the disabled state. */
165#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
166#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
167#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
168
169
170/*--------------------TMS570_PLL_CSDISCLR--------------------*/
171/* field: CLRCLKSR_7_3_OFF - Enables clock source[7-3]. */
172#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
173#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
174#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
175
176/* field: CLRCLKSR_1_0_OFF - Enables clock source[1-0]. */
177#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
178#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
179#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
180
181
182/*---------------------TMS570_PLL_CSVSTAT---------------------*/
183/* field: CLKSR_7_3V - Clock source[7-0] valid. */
184#define TMS570_PLL_CSVSTAT_CLKSR_7_3V(val) BSP_FLD32(val,3, 7)
185#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_GET(reg) BSP_FLD32GET(reg,3, 7)
186#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
187
188/* field: CLKSR_1_0V - Clock source[1-0] valid. */
189#define TMS570_PLL_CSVSTAT_CLKSR_1_0V(val) BSP_FLD32(val,0, 1)
190#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_GET(reg) BSP_FLD32GET(reg,0, 1)
191#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
192
193
194/*---------------------TMS570_PLL_PLLCTL1---------------------*/
195/* field: ROS - Reset on PLL Slip */
196#define TMS570_PLL_PLLCTL1_ROS BSP_BIT32(31)
197
198/* field: MASK_SLIP - Mask detection of PLL slip */
199#define TMS570_PLL_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
200#define TMS570_PLL_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30)
201#define TMS570_PLL_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
202
203/* field: PLLDIV - PLL Output Clock Divider */
204#define TMS570_PLL_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28)
205#define TMS570_PLL_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28)
206#define TMS570_PLL_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
207
208/* field: ROF - Reset on Oscillator Fail */
209#define TMS570_PLL_PLLCTL1_ROF BSP_BIT32(23)
210
211/* field: REFCLKDIV - Reference Clock Divider */
212#define TMS570_PLL_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
213#define TMS570_PLL_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21)
214#define TMS570_PLL_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
215
216/* field: PLLMUL - PLL Multiplication Factor */
217#define TMS570_PLL_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15)
218#define TMS570_PLL_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15)
219#define TMS570_PLL_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
220
221
222/*---------------------TMS570_PLL_PLLCTL2---------------------*/
223/* field: FMENA - Frequency Modulation Enable. */
224#define TMS570_PLL_PLLCTL2_FMENA BSP_BIT32(31)
225
226/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
227#define TMS570_PLL_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
228#define TMS570_PLL_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30)
229#define TMS570_PLL_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30)
230
231/* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */
232#define TMS570_PLL_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20)
233#define TMS570_PLL_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20)
234#define TMS570_PLL_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20)
235
236/* field: ODPLL - Internal PLL Output Divider. */
237#define TMS570_PLL_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11)
238#define TMS570_PLL_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11)
239#define TMS570_PLL_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
240
241/* field: SPR_AMOUNT - Spreading Amount. */
242#define TMS570_PLL_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8)
243#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8)
244#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
245
246
247/*--------------------TMS570_PLL_LPOMONCTL--------------------*/
248/* field: BIAS_ENABLE - Bias enable. */
249#define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24)
250
251/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
252#define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16)
253
254/* field: HFTRIM - High frequency oscillator trim value. */
255#define TMS570_PLL_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
256#define TMS570_PLL_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12)
257#define TMS570_PLL_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
258
259
260/*---------------------TMS570_PLL_CLKTEST---------------------*/
261/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
262#define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26)
263
264/* field: RANGEDETCTRL - Range detection control. */
265#define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_BIT32(25)
266
267/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
268#define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_BIT32(24)
269
270/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
271#define TMS570_PLL_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
272#define TMS570_PLL_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
273#define TMS570_PLL_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
274
275
276/*---------------------TMS570_PLL_GPREG1---------------------*/
277/* field: EMIF_FUNC - Enable EMIF functions to be output. */
278#define TMS570_PLL_GPREG1_EMIF_FUNC BSP_BIT32(31)
279
280/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
281#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
282#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25)
283#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
284
285/* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */
286#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19)
287#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19)
288#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
289
290/* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */
291#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15)
292#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15)
293#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
294
295
296/*---------------------TMS570_PLL_GLBSTAT---------------------*/
297/* field: FBSLIP - PLL over cycle slip detection. */
298#define TMS570_PLL_GLBSTAT_FBSLIP BSP_BIT32(9)
299
300/* field: RFSLIP - PLL under cycle slip detection. */
301#define TMS570_PLL_GLBSTAT_RFSLIP BSP_BIT32(8)
302
303/* field: OSCFAIL - Oscillator fail flag bit. */
304#define TMS570_PLL_GLBSTAT_OSCFAIL BSP_BIT32(0)
305
306
307
308#endif /* LIBBSP_ARM_TMS570_PLL */
This header file provides utility macros for BSPs.
Definition: reg_pll.h:54