RTEMS 6.1-rc4
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reg_emif.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/* The header file is generated by make_header.py from EMIF.json */
12/* Current script's version can be found at: */
13/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
14
15/*
16 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
17 *
18 * Czech Technical University in Prague
19 * Zikova 1903/4
20 * 166 36 Praha 6
21 * Czech Republic
22 *
23 * All rights reserved.
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following disclaimer in the documentation
32 * and/or other materials provided with the distribution.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
38 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
40 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
41 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
43 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * The views and conclusions contained in the software and documentation are those
46 * of the authors and should not be interpreted as representing official policies,
47 * either expressed or implied, of the FreeBSD Project.
48*/
49#ifndef LIBBSP_ARM_TMS570_EMIF
50#define LIBBSP_ARM_TMS570_EMIF
51
52#include <bsp/utility.h>
53
54typedef struct{
55 uint32_t MIDR; /*Module ID Register*/
56 uint32_t AWCC; /*Asynchronous Wait Cycle Configuration Register*/
57 uint32_t SDCR; /*SDRAM Configuration Register*/
58 uint32_t SDRCR; /*SDRAM Refresh Control Register*/
59 uint32_t CE2CFG; /*Asynchronous 1 Configuration Register*/
60 uint32_t CE3CFG; /*Asynchronous 2 Configuration Register*/
61 uint32_t CE4CFG; /*Asynchronous 3 Configuration Register*/
62 uint32_t CE5CFG; /*Asynchronous 4 Configuration Register*/
63 uint32_t SDTIMR; /*SDRAM Timing Register*/
64 uint8_t reserved1 [24];
65 uint32_t SDSRETR; /*SDRAM Self Refresh Exit Timing Register*/
66 uint32_t INTRAW; /*EMIF Interrupt Raw Register*/
67 uint32_t INTMSK; /*EMIF Interrupt Mask Register*/
68 uint32_t INTMSKSET; /*EMIF Interrupt Mask Set Register*/
69 uint32_t INTMSKCLR; /*EMIF Interrupt Mask Clear Register*/
70 uint8_t reserved2 [24];
71 uint32_t PMCR; /*Page Mode Control Register*/
72} tms570_emif_t;
73
74
75/*----------------------TMS570_EMIF_MIDR----------------------*/
76/* field: REV - Module ID of EMIF. See the device-specific data manual. */
77/* Whole 32 bits */
78
79/*----------------------TMS570_EMIF_AWCC----------------------*/
80/* field: WP1 - EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin. */
81#define TMS570_EMIF_AWCC_WP1 BSP_BIT32(29)
82
83/* field: WP0 - EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin. */
84#define TMS570_EMIF_AWCC_WP0 BSP_BIT32(28)
85
86/* field: CS5_WAIT - Chip Select 5 WAIT signal selection. */
87#define TMS570_EMIF_AWCC_CS5_WAIT(val) BSP_FLD32(val,22, 23)
88#define TMS570_EMIF_AWCC_CS5_WAIT_GET(reg) BSP_FLD32GET(reg,22, 23)
89#define TMS570_EMIF_AWCC_CS5_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,22, 23)
90
91/* field: CS4_WAIT - Chip Select 4 WAIT signal selection. */
92#define TMS570_EMIF_AWCC_CS4_WAIT(val) BSP_FLD32(val,20, 21)
93#define TMS570_EMIF_AWCC_CS4_WAIT_GET(reg) BSP_FLD32GET(reg,20, 21)
94#define TMS570_EMIF_AWCC_CS4_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,20, 21)
95
96/* field: CS3_WAIT - be used for memory accesses to chip select 3 memory space. */
97#define TMS570_EMIF_AWCC_CS3_WAIT(val) BSP_FLD32(val,18, 19)
98#define TMS570_EMIF_AWCC_CS3_WAIT_GET(reg) BSP_FLD32GET(reg,18, 19)
99#define TMS570_EMIF_AWCC_CS3_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,18, 19)
100
101/* field: CS2_WAIT - Chip Select 2 WAIT signal selection. */
102#define TMS570_EMIF_AWCC_CS2_WAIT(val) BSP_FLD32(val,16, 17)
103#define TMS570_EMIF_AWCC_CS2_WAIT_GET(reg) BSP_FLD32GET(reg,16, 17)
104#define TMS570_EMIF_AWCC_CS2_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
105
106/* field: MAX_EXT_WAIT - Maximum extended wait cycles. */
107#define TMS570_EMIF_AWCC_MAX_EXT_WAIT(val) BSP_FLD32(val,0, 7)
108#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_GET(reg) BSP_FLD32GET(reg,0, 7)
109#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
110
111
112/*----------------------TMS570_EMIF_SDCR----------------------*/
113/* field: SR - Self-Refresh mode bit. */
114#define TMS570_EMIF_SDCR_SR BSP_BIT32(31)
115
116/* field: PD - Power Down bit. This bit controls entering and exiting of the power-down mode. */
117#define TMS570_EMIF_SDCR_PD BSP_BIT32(30)
118
119/* field: PDWR - Perform refreshes during power down. */
120#define TMS570_EMIF_SDCR_PDWR BSP_BIT32(29)
121
122/* field: NM - Narrow mode bit. This bit defines whether a 16- or 32-bit-wide SDRAM is connected to the EMIF. */
123#define TMS570_EMIF_SDCR_NM BSP_BIT32(14)
124
125/* field: CL - CAS Latency. */
126#define TMS570_EMIF_SDCR_CL(val) BSP_FLD32(val,9, 11)
127#define TMS570_EMIF_SDCR_CL_GET(reg) BSP_FLD32GET(reg,9, 11)
128#define TMS570_EMIF_SDCR_CL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
129
130/* field: BIT11_9LOCK - Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
131#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_BIT32(8)
132
133/* field: IBANK - Internal SDRAM Bank size. */
134#define TMS570_EMIF_SDCR_IBANK(val) BSP_FLD32(val,4, 6)
135#define TMS570_EMIF_SDCR_IBANK_GET(reg) BSP_FLD32GET(reg,4, 6)
136#define TMS570_EMIF_SDCR_IBANK_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
137
138/* field: PAGESIZE - Page Size. This field defines the internal page size of connected SDRAM devices. */
139#define TMS570_EMIF_SDCR_PAGESIZE(val) BSP_FLD32(val,0, 2)
140#define TMS570_EMIF_SDCR_PAGESIZE_GET(reg) BSP_FLD32GET(reg,0, 2)
141#define TMS570_EMIF_SDCR_PAGESIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
142
143
144/*---------------------TMS570_EMIF_SDRCR---------------------*/
145/* field: RR - Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles. */
146#define TMS570_EMIF_SDRCR_RR(val) BSP_FLD32(val,0, 12)
147#define TMS570_EMIF_SDRCR_RR_GET(reg) BSP_FLD32GET(reg,0, 12)
148#define TMS570_EMIF_SDRCR_RR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
149
150
151/*---------------------TMS570_EMIF_CE2CFG---------------------*/
152/* field: SS - Select Strobe bit. */
153#define TMS570_EMIF_CE2CFG_SS BSP_BIT32(31)
154
155/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
156#define TMS570_EMIF_CE2CFG_EW BSP_BIT32(30)
157
158/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
159#define TMS570_EMIF_CE2CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
160#define TMS570_EMIF_CE2CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
161#define TMS570_EMIF_CE2CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
162
163/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
164#define TMS570_EMIF_CE2CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
165#define TMS570_EMIF_CE2CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
166#define TMS570_EMIF_CE2CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
167
168/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
169#define TMS570_EMIF_CE2CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
170#define TMS570_EMIF_CE2CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
171#define TMS570_EMIF_CE2CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
172
173/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
174#define TMS570_EMIF_CE2CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
175#define TMS570_EMIF_CE2CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
176#define TMS570_EMIF_CE2CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
177
178/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
179#define TMS570_EMIF_CE2CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
180#define TMS570_EMIF_CE2CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
181#define TMS570_EMIF_CE2CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
182
183/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
184#define TMS570_EMIF_CE2CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
185#define TMS570_EMIF_CE2CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
186#define TMS570_EMIF_CE2CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
187
188/* field: TA - Minimum Turn-Around time. */
189#define TMS570_EMIF_CE2CFG_TA(val) BSP_FLD32(val,2, 3)
190#define TMS570_EMIF_CE2CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
191#define TMS570_EMIF_CE2CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
192
193/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
194#define TMS570_EMIF_CE2CFG_ASIZE(val) BSP_FLD32(val,0, 1)
195#define TMS570_EMIF_CE2CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
196#define TMS570_EMIF_CE2CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
197
198
199/*---------------------TMS570_EMIF_CE3CFG---------------------*/
200/* field: SS - Select Strobe bit. */
201#define TMS570_EMIF_CE3CFG_SS BSP_BIT32(31)
202
203/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
204#define TMS570_EMIF_CE3CFG_EW BSP_BIT32(30)
205
206/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
207#define TMS570_EMIF_CE3CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
208#define TMS570_EMIF_CE3CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
209#define TMS570_EMIF_CE3CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
210
211/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
212#define TMS570_EMIF_CE3CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
213#define TMS570_EMIF_CE3CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
214#define TMS570_EMIF_CE3CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
215
216/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
217#define TMS570_EMIF_CE3CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
218#define TMS570_EMIF_CE3CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
219#define TMS570_EMIF_CE3CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
220
221/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
222#define TMS570_EMIF_CE3CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
223#define TMS570_EMIF_CE3CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
224#define TMS570_EMIF_CE3CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
225
226/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
227#define TMS570_EMIF_CE3CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
228#define TMS570_EMIF_CE3CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
229#define TMS570_EMIF_CE3CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
230
231/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
232#define TMS570_EMIF_CE3CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
233#define TMS570_EMIF_CE3CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
234#define TMS570_EMIF_CE3CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
235
236/* field: TA - Minimum Turn-Around time. */
237#define TMS570_EMIF_CE3CFG_TA(val) BSP_FLD32(val,2, 3)
238#define TMS570_EMIF_CE3CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
239#define TMS570_EMIF_CE3CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
240
241/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
242#define TMS570_EMIF_CE3CFG_ASIZE(val) BSP_FLD32(val,0, 1)
243#define TMS570_EMIF_CE3CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
244#define TMS570_EMIF_CE3CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
245
246
247/*---------------------TMS570_EMIF_CE4CFG---------------------*/
248/* field: SS - Select Strobe bit. */
249#define TMS570_EMIF_CE4CFG_SS BSP_BIT32(31)
250
251/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
252#define TMS570_EMIF_CE4CFG_EW BSP_BIT32(30)
253
254/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
255#define TMS570_EMIF_CE4CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
256#define TMS570_EMIF_CE4CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
257#define TMS570_EMIF_CE4CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
258
259/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
260#define TMS570_EMIF_CE4CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
261#define TMS570_EMIF_CE4CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
262#define TMS570_EMIF_CE4CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
263
264/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
265#define TMS570_EMIF_CE4CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
266#define TMS570_EMIF_CE4CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
267#define TMS570_EMIF_CE4CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
268
269/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
270#define TMS570_EMIF_CE4CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
271#define TMS570_EMIF_CE4CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
272#define TMS570_EMIF_CE4CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
273
274/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
275#define TMS570_EMIF_CE4CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
276#define TMS570_EMIF_CE4CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
277#define TMS570_EMIF_CE4CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
278
279/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
280#define TMS570_EMIF_CE4CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
281#define TMS570_EMIF_CE4CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
282#define TMS570_EMIF_CE4CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
283
284/* field: TA - Minimum Turn-Around time. */
285#define TMS570_EMIF_CE4CFG_TA(val) BSP_FLD32(val,2, 3)
286#define TMS570_EMIF_CE4CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
287#define TMS570_EMIF_CE4CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
288
289/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
290#define TMS570_EMIF_CE4CFG_ASIZE(val) BSP_FLD32(val,0, 1)
291#define TMS570_EMIF_CE4CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
292#define TMS570_EMIF_CE4CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
293
294
295/*---------------------TMS570_EMIF_CE5CFG---------------------*/
296/* field: SS - Select Strobe bit. */
297#define TMS570_EMIF_CE5CFG_SS BSP_BIT32(31)
298
299/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
300#define TMS570_EMIF_CE5CFG_EW BSP_BIT32(30)
301
302/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
303#define TMS570_EMIF_CE5CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
304#define TMS570_EMIF_CE5CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
305#define TMS570_EMIF_CE5CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
306
307/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
308#define TMS570_EMIF_CE5CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
309#define TMS570_EMIF_CE5CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
310#define TMS570_EMIF_CE5CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
311
312/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
313#define TMS570_EMIF_CE5CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
314#define TMS570_EMIF_CE5CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
315#define TMS570_EMIF_CE5CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
316
317/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
318#define TMS570_EMIF_CE5CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
319#define TMS570_EMIF_CE5CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
320#define TMS570_EMIF_CE5CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
321
322/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
323#define TMS570_EMIF_CE5CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
324#define TMS570_EMIF_CE5CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
325#define TMS570_EMIF_CE5CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
326
327/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
328#define TMS570_EMIF_CE5CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
329#define TMS570_EMIF_CE5CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
330#define TMS570_EMIF_CE5CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
331
332/* field: TA - and writes, minus one cycle. See Section 17.2.6.3 for details. */
333#define TMS570_EMIF_CE5CFG_TA(val) BSP_FLD32(val,2, 3)
334#define TMS570_EMIF_CE5CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
335#define TMS570_EMIF_CE5CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
336
337/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
338#define TMS570_EMIF_CE5CFG_ASIZE(val) BSP_FLD32(val,0, 1)
339#define TMS570_EMIF_CE5CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
340#define TMS570_EMIF_CE5CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
341
342
343/*---------------------TMS570_EMIF_SDTIMR---------------------*/
344/* field: T_RFC - Specifies the Trfc value of the SDRAM. */
345#define TMS570_EMIF_SDTIMR_T_RFC(val) BSP_FLD32(val,27, 31)
346#define TMS570_EMIF_SDTIMR_T_RFC_GET(reg) BSP_FLD32GET(reg,27, 31)
347#define TMS570_EMIF_SDTIMR_T_RFC_SET(reg,val) BSP_FLD32SET(reg, val,27, 31)
348
349/* field: T_RP - Precharge (PRE) to Activate (ACTV) or Refresh (REFR) command, minus 1: */
350#define TMS570_EMIF_SDTIMR_T_RP(val) BSP_FLD32(val,24, 26)
351#define TMS570_EMIF_SDTIMR_T_RP_GET(reg) BSP_FLD32GET(reg,24, 26)
352#define TMS570_EMIF_SDTIMR_T_RP_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
353
354/* field: T_RCD - Specifies the Trcd value of the SDRAM. */
355#define TMS570_EMIF_SDTIMR_T_RCD(val) BSP_FLD32(val,20, 22)
356#define TMS570_EMIF_SDTIMR_T_RCD_GET(reg) BSP_FLD32GET(reg,20, 22)
357#define TMS570_EMIF_SDTIMR_T_RCD_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
358
359/* field: T_WR - Specifies the Twr value of the SDRAM. */
360#define TMS570_EMIF_SDTIMR_T_WR(val) BSP_FLD32(val,16, 18)
361#define TMS570_EMIF_SDTIMR_T_WR_GET(reg) BSP_FLD32GET(reg,16, 18)
362#define TMS570_EMIF_SDTIMR_T_WR_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
363
364/* field: T_RAS - Specifies the Tras value of the SDRAM. */
365#define TMS570_EMIF_SDTIMR_T_RAS(val) BSP_FLD32(val,12, 15)
366#define TMS570_EMIF_SDTIMR_T_RAS_GET(reg) BSP_FLD32GET(reg,12, 15)
367#define TMS570_EMIF_SDTIMR_T_RAS_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
368
369/* field: T_RC - Specifies the Trc value of the SDRAM. */
370#define TMS570_EMIF_SDTIMR_T_RC(val) BSP_FLD32(val,8, 11)
371#define TMS570_EMIF_SDTIMR_T_RC_GET(reg) BSP_FLD32GET(reg,8, 11)
372#define TMS570_EMIF_SDTIMR_T_RC_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
373
374/* field: T_RRD - Specifies the Trrd value of the SDRAM. */
375#define TMS570_EMIF_SDTIMR_T_RRD(val) BSP_FLD32(val,4, 6)
376#define TMS570_EMIF_SDTIMR_T_RRD_GET(reg) BSP_FLD32GET(reg,4, 6)
377#define TMS570_EMIF_SDTIMR_T_RRD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
378
379
380/*--------------------TMS570_EMIF_SDSRETR--------------------*/
381/* field: T_XS - This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, */
382#define TMS570_EMIF_SDSRETR_T_XS(val) BSP_FLD32(val,0, 4)
383#define TMS570_EMIF_SDSRETR_T_XS_GET(reg) BSP_FLD32GET(reg,0, 4)
384#define TMS570_EMIF_SDSRETR_T_XS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
385
386
387/*---------------------TMS570_EMIF_INTRAW---------------------*/
388/* field: WR - Wait Rise. */
389#define TMS570_EMIF_INTRAW_WR BSP_BIT32(2)
390
391/* field: LT - Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size. */
392#define TMS570_EMIF_INTRAW_LT BSP_BIT32(1)
393
394/* field: AT - Asynchronous Timeout. */
395#define TMS570_EMIF_INTRAW_AT BSP_BIT32(0)
396
397
398/*---------------------TMS570_EMIF_INTMSK---------------------*/
399/* field: WR_MASKED - Wait Rise Masked. */
400#define TMS570_EMIF_INTMSK_WR_MASKED BSP_BIT32(2)
401
402/* field: LT_MASKED - Masked Line Trap. */
403#define TMS570_EMIF_INTMSK_LT_MASKED BSP_BIT32(1)
404
405/* field: AT_MASKED - Asynchronous Timeout Masked. */
406#define TMS570_EMIF_INTMSK_AT_MASKED BSP_BIT32(0)
407
408
409/*-------------------TMS570_EMIF_INTMSKSET-------------------*/
410/* field: WR_MASK_SET - Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. */
411#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_BIT32(2)
412
413/* field: LT_MASK_SET - LT_MASK_SET Mask set for LT_MASKED bit in the EMIF interrupt mask register (INTMSK). */
414#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_BIT32(1)
415
416/* field: AT_MASK_SET - Asynchronous Timeout Mask Set. */
417#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_BIT32(0)
418
419
420/*-------------------TMS570_EMIF_INTMSKCLR-------------------*/
421/* field: WR_MASK_CLR - Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. */
422#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_BIT32(2)
423
424/* field: LT_MASK_CLR - 1 to this bit clears this bit, clears the LT_MASK_SET bit in the EMIF interrupt mask set register */
425#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_BIT32(1)
426
427/* field: AT_MASK_CLR - Asynchronous Timeout Mask Clear. */
428#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_BIT32(0)
429
430
431/*----------------------TMS570_EMIF_PMCR----------------------*/
432/* field: CS5_PG_DEL - Page access delay for NOR Flash connected on CS5. CS5 is not available on this device. */
433#define TMS570_EMIF_PMCR_CS5_PG_DEL(val) BSP_FLD32(val,26, 31)
434#define TMS570_EMIF_PMCR_CS5_PG_DEL_GET(reg) BSP_FLD32GET(reg,26, 31)
435#define TMS570_EMIF_PMCR_CS5_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,26, 31)
436
437/* field: CS5_PG_SIZE - Page Size for NOR Flash connected on CS5. CS5 is not available on this device. */
438#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_BIT32(25)
439
440/* field: CS5_PG_MD_EN - Page Mode enable for NOR Flash connected on CS5. CS5 is not available on this device. */
441#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_BIT32(24)
442
443/* field: CS4_PG_DEL - Page access delay for NOR Flash connected on CS4. */
444#define TMS570_EMIF_PMCR_CS4_PG_DEL(val) BSP_FLD32(val,18, 23)
445#define TMS570_EMIF_PMCR_CS4_PG_DEL_GET(reg) BSP_FLD32GET(reg,18, 23)
446#define TMS570_EMIF_PMCR_CS4_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,18, 23)
447
448/* field: CS4_PG_SIZE - Page Size for NOR Flash connected on CS4. */
449#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_BIT32(17)
450
451/* field: CS4_PG_MD_EN - Page Mode enable for NOR Flash connected on CS4. */
452#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_BIT32(16)
453
454/* field: CS3_PG_DEL - the page read data to be valid, minus one cycle. This value must not be cleared to 0. */
455#define TMS570_EMIF_PMCR_CS3_PG_DEL(val) BSP_FLD32(val,10, 15)
456#define TMS570_EMIF_PMCR_CS3_PG_DEL_GET(reg) BSP_FLD32GET(reg,10, 15)
457#define TMS570_EMIF_PMCR_CS3_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,10, 15)
458
459/* field: CS3_PG_SIZE - Page Size for NOR Flash connected on CS3. */
460#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_BIT32(9)
461
462/* field: CS3_PG_MD_EN - Page Mode enable for NOR Flash connected on CS3. */
463#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_BIT32(8)
464
465/* field: CS2_PG_DEL - Page access delay for NOR Flash connected on CS2. */
466#define TMS570_EMIF_PMCR_CS2_PG_DEL(val) BSP_FLD32(val,2, 7)
467#define TMS570_EMIF_PMCR_CS2_PG_DEL_GET(reg) BSP_FLD32GET(reg,2, 7)
468#define TMS570_EMIF_PMCR_CS2_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 7)
469
470/* field: CS2_PG_SIZE - Page Size for NOR Flash connected on CS2. */
471#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_BIT32(1)
472
473/* field: CS2_PG_MD_EN - Page Mode enable for NOR Flash connected on CS2. */
474#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_BIT32(0)
475
476
477
478#endif /* LIBBSP_ARM_TMS570_EMIF */
utility.h
This header file provides utility macros for BSPs.
tms570_emif_t
Definition: reg_emif.h:54
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