RTEMS 6.1-rc4
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reg_emacm.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/* The header file is generated by make_header.py from EMACM.json */
12/* Current script's version can be found at: */
13/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
14
15/*
16 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
17 *
18 * Czech Technical University in Prague
19 * Zikova 1903/4
20 * 166 36 Praha 6
21 * Czech Republic
22 *
23 * All rights reserved.
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following disclaimer in the documentation
32 * and/or other materials provided with the distribution.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
38 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
40 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
41 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
43 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * The views and conclusions contained in the software and documentation are those
46 * of the authors and should not be interpreted as representing official policies,
47 * either expressed or implied, of the FreeBSD Project.
48*/
49#ifndef LIBBSP_ARM_TMS570_EMACM
50#define LIBBSP_ARM_TMS570_EMACM
51
52#include <bsp/utility.h>
53
54typedef struct{
55 uint32_t TXREVID; /*Transmit Revision ID Register*/
56 uint32_t TXCONTROL; /*Transmit Control Register*/
57 uint32_t TXTEARDOWN; /*Transmit Teardown Register*/
58 uint8_t reserved1 [4];
59 uint32_t RXREVID; /*Receive Revision ID Register*/
60 uint32_t RXCONTROL; /*Receive Control Register*/
61 uint32_t RXTEARDOWN; /*Receive Teardown Register*/
62 uint8_t reserved2 [100];
63 uint32_t TXINTSTATRAW; /*Transmit Interrupt Status (Unmasked) Register*/
64 uint32_t TXINTSTATMASKED; /*Transmit Interrupt Status (Masked) Register*/
65 uint32_t TXINTMASKSET; /*Transmit Interrupt Mask Set Register*/
66 uint32_t TXINTMASKCLEAR; /*Transmit Interrupt Clear Register*/
67 uint32_t MACINVECTOR; /*MAC Input Vector Register*/
68 uint32_t MACEOIVECTOR; /*MAC End Of Interrupt Vector Register*/
69 uint8_t reserved3 [8];
70 uint32_t RXINTSTATRAW; /*Receive Interrupt Status (Unmasked) Register*/
71 uint32_t RXINTSTATMASKED; /*Receive Interrupt Status (Masked) Register*/
72 uint32_t RXINTMASKSET; /*Receive Interrupt Mask Set Register*/
73 uint32_t RXINTMASKCLEAR; /*Receive Interrupt Mask Clear Register*/
74 uint32_t MACINTSTATRAW; /*MAC Interrupt Status (Unmasked) Register*/
75 uint32_t MACINTSTATMASKED; /*MAC Interrupt Status (Masked) Register*/
76 uint32_t MACINTMASKSET; /*MAC Interrupt Mask Set Register*/
77 uint32_t MACINTMASKCLEAR; /*MAC Interrupt Mask Clear Register*/
78 uint8_t reserved4 [64];
79 uint32_t RXMBPENABLE; /*Receive Multicast/Broadcast/Promiscuous Channel Enable*/
80 uint32_t RXUNICASTSET; /*Receive Unicast Enable Set Register*/
81 uint32_t RXUNICASTCLEAR; /*Receive Unicast Clear Register*/
82 uint32_t RXMAXLEN; /*Receive Maximum Length Register*/
83 uint32_t RXBUFFEROFFSET; /*Receive Buffer Offset Register*/
84 uint32_t RXFILTERLOWTHRESH; /*Receive Filter Low Priority Frame Threshold Register*/
85 uint8_t reserved5 [8];
86 uint32_t RXFLOWTHRESH[8]; /*Receive Channel Flow Control Threshold Register*/
87 uint32_t RXFREEBUFFER[8]; /*Receive Channel Free Buffer Count Register*/
88 uint32_t MACCONTROL; /*MAC Control Register*/
89 uint32_t MACSTATUS; /*MAC Status Register*/
90 uint32_t EMCONTROL; /*Emulation Control Register*/
91 uint32_t FIFOCONTROL; /*FIFO Control Register*/
92 uint32_t MACCONFIG; /*MAC Configuration Register*/
93 uint32_t SOFTRESET; /*Soft Reset Register*/
94 uint8_t reserved6 [88];
95 uint32_t MACSRCADDRLO; /*MAC Source Address Low Bytes Register*/
96 uint32_t MACSRCADDRHI; /*MAC Source Address High Bytes Register*/
97 uint32_t MACHASH1; /*MAC Hash Address Register 1*/
98 uint32_t MACHASH2; /*MAC Hash Address Register 2*/
99 uint32_t BOFFTEST; /*Back Off Test Register*/
100 uint32_t TPACETEST; /*Transmit Pacing Algorithm Test Register*/
101 uint32_t RXPAUSE; /*Receive Pause Timer Register*/
102 uint32_t TXPAUSE; /*Transmit Pause Timer Register*/
103 uint8_t reserved7 [784];
104 uint32_t MACADDRLO; /*MAC Address Low Bytes Register*/
105 uint32_t MACADDRHI; /*MAC Address High Bytes Register*/
106 uint32_t MACINDEX; /*MAC Index Register*/
107 uint8_t reserved8 [244];
108 uint32_t TXHDP[8]; /*Transmit Channel DMA Head Descriptor Pointer Register*/
109 uint32_t RXHDP[8]; /*Receive Channel DMA Head Descriptor Pointer Register*/
110 uint32_t TXCP[8]; /*Transmit Channel Completion Pointer Register*/
111 uint32_t RXCP[8]; /*Receive Channel Completion Pointer Register*/
112} tms570_emacm_t;
113
114
115/*--------------------TMS570_EMACM_TXREVID--------------------*/
116/* field: TXREV - Transmit module revision */
117/* Whole 32 bits */
118
119/*-------------------TMS570_EMACM_TXCONTROL-------------------*/
120/* field: TXEN - Transmit enable */
121#define TMS570_EMACM_TXCONTROL_TXEN BSP_BIT32(0)
122
123
124/*------------------TMS570_EMACM_TXTEARDOWN------------------*/
125/* field: TXTDNCH - Transmit teardown channel. */
126#define TMS570_EMACM_TXTEARDOWN_TXTDNCH(val) BSP_FLD32(val,0, 2)
127#define TMS570_EMACM_TXTEARDOWN_TXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2)
128#define TMS570_EMACM_TXTEARDOWN_TXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
129
130
131/*--------------------TMS570_EMACM_RXREVID--------------------*/
132/* field: RXREV - Receive module revision */
133/* Whole 32 bits */
134
135/*-------------------TMS570_EMACM_RXCONTROL-------------------*/
136/* field: RXEN - Receive enable */
137#define TMS570_EMACM_RXCONTROL_RXEN BSP_BIT32(0)
138
139
140/*------------------TMS570_EMACM_RXTEARDOWN------------------*/
141/* field: RXTDNCH - Receive teardown channel. */
142#define TMS570_EMACM_RXTEARDOWN_RXTDNCH(val) BSP_FLD32(val,0, 2)
143#define TMS570_EMACM_RXTEARDOWN_RXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2)
144#define TMS570_EMACM_RXTEARDOWN_RXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
145
146
147/*-----------------TMS570_EMACM_TXINTSTATRAW-----------------*/
148/* field: TX7PEND - TX7PEND raw interrupt read (before mask) */
149#define TMS570_EMACM_TXINTSTATRAW_TX7PEND BSP_BIT32(7)
150
151/* field: TX6PEND - TX6PEND raw interrupt read (before mask) */
152#define TMS570_EMACM_TXINTSTATRAW_TX6PEND BSP_BIT32(6)
153
154/* field: TX5PEND - TX5PEND raw interrupt read (before mask) */
155#define TMS570_EMACM_TXINTSTATRAW_TX5PEND BSP_BIT32(5)
156
157/* field: TX4PEND - X4PEND raw interrupt read (before mask) */
158#define TMS570_EMACM_TXINTSTATRAW_TX4PEND BSP_BIT32(4)
159
160/* field: TX3PEND - TX3PEND raw interrupt read (before mask) */
161#define TMS570_EMACM_TXINTSTATRAW_TX3PEND BSP_BIT32(3)
162
163/* field: TX2PEND - TX2PEND raw interrupt read (before mask) */
164#define TMS570_EMACM_TXINTSTATRAW_TX2PEND BSP_BIT32(2)
165
166/* field: TX1PEND - TX1PEND raw interrupt read (before mask) */
167#define TMS570_EMACM_TXINTSTATRAW_TX1PEND BSP_BIT32(1)
168
169/* field: TX0PEND - TX0PEND raw interrupt read (before mask) */
170#define TMS570_EMACM_TXINTSTATRAW_TX0PEND BSP_BIT32(0)
171
172
173/*----------------TMS570_EMACM_TXINTSTATMASKED----------------*/
174/* field: TX7PEND - TX7PEND masked interrupt read */
175#define TMS570_EMACM_TXINTSTATMASKED_TX7PEND BSP_BIT32(7)
176
177/* field: TX6PEND - TX6PEND masked interrupt read */
178#define TMS570_EMACM_TXINTSTATMASKED_TX6PEND BSP_BIT32(6)
179
180/* field: TX5PEND - TX5PEND masked interrupt read */
181#define TMS570_EMACM_TXINTSTATMASKED_TX5PEND BSP_BIT32(5)
182
183/* field: TX4PEND - TX4PEND masked interrupt read */
184#define TMS570_EMACM_TXINTSTATMASKED_TX4PEND BSP_BIT32(4)
185
186/* field: TX3PEND - TX3PEND masked interrupt read */
187#define TMS570_EMACM_TXINTSTATMASKED_TX3PEND BSP_BIT32(3)
188
189/* field: TX2PEND - TX2PEND masked interrupt read */
190#define TMS570_EMACM_TXINTSTATMASKED_TX2PEND BSP_BIT32(2)
191
192/* field: TX1PEND - TX1PEND masked interrupt read */
193#define TMS570_EMACM_TXINTSTATMASKED_TX1PEND BSP_BIT32(1)
194
195/* field: TX0PEND - TX0PEND masked interrupt read */
196#define TMS570_EMACM_TXINTSTATMASKED_TX0PEND BSP_BIT32(0)
197
198
199/*-----------------TMS570_EMACM_TXINTMASKSET-----------------*/
200/* field: TX7MASK - Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
201#define TMS570_EMACM_TXINTMASKSET_TX7MASK BSP_BIT32(7)
202
203/* field: TX6MASK - Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
204#define TMS570_EMACM_TXINTMASKSET_TX6MASK BSP_BIT32(6)
205
206/* field: TX5MASK - Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
207#define TMS570_EMACM_TXINTMASKSET_TX5MASK BSP_BIT32(5)
208
209/* field: TX4MASK - Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
210#define TMS570_EMACM_TXINTMASKSET_TX4MASK BSP_BIT32(4)
211
212/* field: TX3MASK - Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
213#define TMS570_EMACM_TXINTMASKSET_TX3MASK BSP_BIT32(3)
214
215/* field: TX2MASK - Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
216#define TMS570_EMACM_TXINTMASKSET_TX2MASK BSP_BIT32(2)
217
218/* field: TX1MASK - Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
219#define TMS570_EMACM_TXINTMASKSET_TX1MASK BSP_BIT32(1)
220
221/* field: TX0MASK - Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
222#define TMS570_EMACM_TXINTMASKSET_TX0MASK BSP_BIT32(0)
223
224
225/*----------------TMS570_EMACM_TXINTMASKCLEAR----------------*/
226/* field: TX7MASK - Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
227#define TMS570_EMACM_TXINTMASKCLEAR_TX7MASK BSP_BIT32(7)
228
229/* field: TX6MASK - Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
230#define TMS570_EMACM_TXINTMASKCLEAR_TX6MASK BSP_BIT32(6)
231
232/* field: TX5MASK - Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
233#define TMS570_EMACM_TXINTMASKCLEAR_TX5MASK BSP_BIT32(5)
234
235/* field: TX4MASK - Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
236#define TMS570_EMACM_TXINTMASKCLEAR_TX4MASK BSP_BIT32(4)
237
238/* field: TX3MASK - Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
239#define TMS570_EMACM_TXINTMASKCLEAR_TX3MASK BSP_BIT32(3)
240
241/* field: TX2MASK - Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
242#define TMS570_EMACM_TXINTMASKCLEAR_TX2MASK BSP_BIT32(2)
243
244/* field: TX1MASK - Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
245#define TMS570_EMACM_TXINTMASKCLEAR_TX1MASK BSP_BIT32(1)
246
247/* field: TX0MASK - Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
248#define TMS570_EMACM_TXINTMASKCLEAR_TX0MASK BSP_BIT32(0)
249
250
251/*------------------TMS570_EMACM_MACINVECTOR------------------*/
252/* field: STATPEND - EMAC module statistics interrupt (STATPEND) pending status bit */
253#define TMS570_EMACM_MACINVECTOR_STATPEND BSP_BIT32(27)
254
255/* field: HOSTPEND - EMAC module host error interrupt (HOSTPEND) pending status bit */
256#define TMS570_EMACM_MACINVECTOR_HOSTPEND BSP_BIT32(26)
257
258/* field: LINKINT0 - MDIO module USERPHYSEL0 (LINKINT0) status bit */
259#define TMS570_EMACM_MACINVECTOR_LINKINT0 BSP_BIT32(25)
260
261/* field: USERINT0 - MDIO module USERACCESS0 (USERINT0) status bit */
262#define TMS570_EMACM_MACINVECTOR_USERINT0 BSP_BIT32(24)
263
264/* field: TXPEND - Transmit channels 0-7 interrupt (TXnPEND) pending status. Bit 16 is TX0PEND. */
265#define TMS570_EMACM_MACINVECTOR_TXPEND(val) BSP_FLD32(val,16, 23)
266#define TMS570_EMACM_MACINVECTOR_TXPEND_GET(reg) BSP_FLD32GET(reg,16, 23)
267#define TMS570_EMACM_MACINVECTOR_TXPEND_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
268
269/* field: RXTHRESHPEND - Receive channels 0-7 interrupt (RXnTHRESHPEND) pending status. */
270#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND(val) BSP_FLD32(val,8, 15)
271#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND_GET(reg) BSP_FLD32GET(reg,8, 15)
272#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
273
274/* field: RXPEND - Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 0 is RX0PEND. */
275#define TMS570_EMACM_MACINVECTOR_RXPEND(val) BSP_FLD32(val,0, 7)
276#define TMS570_EMACM_MACINVECTOR_RXPEND_GET(reg) BSP_FLD32GET(reg,0, 7)
277#define TMS570_EMACM_MACINVECTOR_RXPEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
278
279
280/*-----------------TMS570_EMACM_MACEOIVECTOR-----------------*/
281/* field: INTVECT - Acknowledge EMAC Control Module Interrupts */
282#define TMS570_EMACM_MACEOIVECTOR_INTVECT(val) BSP_FLD32(val,0, 4)
283#define TMS570_EMACM_MACEOIVECTOR_INTVECT_GET(reg) BSP_FLD32GET(reg,0, 4)
284#define TMS570_EMACM_MACEOIVECTOR_INTVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
285
286
287/*-----------------TMS570_EMACM_RXINTSTATRAW-----------------*/
288/* field: RX7THRESHPEND - RX7THRESHPEND raw interrupt read (before mask) */
289#define TMS570_EMACM_RXINTSTATRAW_RX7THRESHPEND BSP_BIT32(15)
290
291/* field: RX6THRESHPEND - RX6THRESHPEND raw interrupt read (before mask) */
292#define TMS570_EMACM_RXINTSTATRAW_RX6THRESHPEND BSP_BIT32(14)
293
294/* field: RX5THRESHPEND - RX5THRESHPEND raw interrupt read (before mask) */
295#define TMS570_EMACM_RXINTSTATRAW_RX5THRESHPEND BSP_BIT32(13)
296
297/* field: RX4THRESHPEND - RX4THRESHPEND raw interrupt read (before mask) */
298#define TMS570_EMACM_RXINTSTATRAW_RX4THRESHPEND BSP_BIT32(12)
299
300/* field: RX3THRESHPEND - RX3THRESHPEND raw interrupt read (before mask) */
301#define TMS570_EMACM_RXINTSTATRAW_RX3THRESHPEND BSP_BIT32(11)
302
303/* field: RX2THRESHPEND - RX2THRESHPEND raw interrupt read (before mask) */
304#define TMS570_EMACM_RXINTSTATRAW_RX2THRESHPEND BSP_BIT32(10)
305
306/* field: RX1THRESHPEND - RX1THRESHPEND raw interrupt read (before mask) */
307#define TMS570_EMACM_RXINTSTATRAW_RX1THRESHPEND BSP_BIT32(9)
308
309/* field: RX0THRESHPEND - RX0THRESHPEND raw interrupt read (before mask) */
310#define TMS570_EMACM_RXINTSTATRAW_RX0THRESHPEND BSP_BIT32(8)
311
312/* field: RX7PEND - RX7PEND raw interrupt read (before mask) */
313#define TMS570_EMACM_RXINTSTATRAW_RX7PEND BSP_BIT32(7)
314
315/* field: RX6PEND - RX6PEND raw interrupt read (before mask) */
316#define TMS570_EMACM_RXINTSTATRAW_RX6PEND BSP_BIT32(6)
317
318/* field: RX5PEND - RX5PEND raw interrupt read (before mask) */
319#define TMS570_EMACM_RXINTSTATRAW_RX5PEND BSP_BIT32(5)
320
321/* field: RX4PEND - RX4PEND raw interrupt read (before mask) */
322#define TMS570_EMACM_RXINTSTATRAW_RX4PEND BSP_BIT32(4)
323
324/* field: RX3PEND - RX3PEND raw interrupt read (before mask) */
325#define TMS570_EMACM_RXINTSTATRAW_RX3PEND BSP_BIT32(3)
326
327/* field: RX2PEND - RX2PEND raw interrupt read (before mask) */
328#define TMS570_EMACM_RXINTSTATRAW_RX2PEND BSP_BIT32(2)
329
330/* field: RX1PEND - RX1PEND raw interrupt read (before mask) */
331#define TMS570_EMACM_RXINTSTATRAW_RX1PEND BSP_BIT32(1)
332
333/* field: RX0PEND - RX0PEND raw interrupt read (before mask) */
334#define TMS570_EMACM_RXINTSTATRAW_RX0PEND BSP_BIT32(0)
335
336
337/*----------------TMS570_EMACM_RXINTSTATMASKED----------------*/
338/* field: RX7THRESHPEND - RX7THRESHPEND masked interrupt read */
339#define TMS570_EMACM_RXINTSTATMASKED_RX7THRESHPEND BSP_BIT32(15)
340
341/* field: RX6THRESHPEND - RX6THRESHPEND masked interrupt read */
342#define TMS570_EMACM_RXINTSTATMASKED_RX6THRESHPEND BSP_BIT32(14)
343
344/* field: RX5THRESHPEND - RX5THRESHPEND masked interrupt read */
345#define TMS570_EMACM_RXINTSTATMASKED_RX5THRESHPEND BSP_BIT32(13)
346
347/* field: RX4THRESHPEND - RX4THRESHPEND masked interrupt read */
348#define TMS570_EMACM_RXINTSTATMASKED_RX4THRESHPEND BSP_BIT32(12)
349
350/* field: RX3THRESHPEND - RX3THRESHPEND masked interrupt read */
351#define TMS570_EMACM_RXINTSTATMASKED_RX3THRESHPEND BSP_BIT32(11)
352
353/* field: RX2THRESHPEND - RX2THRESHPEND masked interrupt read */
354#define TMS570_EMACM_RXINTSTATMASKED_RX2THRESHPEND BSP_BIT32(10)
355
356/* field: RX1THRESHPEND - RX1THRESHPEND masked interrupt read */
357#define TMS570_EMACM_RXINTSTATMASKED_RX1THRESHPEND BSP_BIT32(9)
358
359/* field: RX0THRESHPEND - RX0THRESHPEND masked interrupt read */
360#define TMS570_EMACM_RXINTSTATMASKED_RX0THRESHPEND BSP_BIT32(8)
361
362/* field: RX7PEND - RX7PEND masked interrupt read */
363#define TMS570_EMACM_RXINTSTATMASKED_RX7PEND BSP_BIT32(7)
364
365/* field: RX6PEND - RX6PEND masked interrupt read */
366#define TMS570_EMACM_RXINTSTATMASKED_RX6PEND BSP_BIT32(6)
367
368/* field: RX5PEND - RX5PEND masked interrupt read */
369#define TMS570_EMACM_RXINTSTATMASKED_RX5PEND BSP_BIT32(5)
370
371/* field: RX4PEND - RX4PEND masked interrupt read */
372#define TMS570_EMACM_RXINTSTATMASKED_RX4PEND BSP_BIT32(4)
373
374/* field: RX3PEND - RX3PEND masked interrupt read */
375#define TMS570_EMACM_RXINTSTATMASKED_RX3PEND BSP_BIT32(3)
376
377/* field: RX2PEND - RX2PEND masked interrupt read */
378#define TMS570_EMACM_RXINTSTATMASKED_RX2PEND BSP_BIT32(2)
379
380/* field: RX1PEND - RX1PEND masked interrupt read */
381#define TMS570_EMACM_RXINTSTATMASKED_RX1PEND BSP_BIT32(1)
382
383/* field: RX0PEND - RX0PEND masked interrupt read */
384#define TMS570_EMACM_RXINTSTATMASKED_RX0PEND BSP_BIT32(0)
385
386
387/*-----------------TMS570_EMACM_RXINTMASKSET-----------------*/
388/* field: RX7THRESHMASK - Receive channel 7 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
389#define TMS570_EMACM_RXINTMASKSET_RX7THRESHMASK BSP_BIT32(15)
390
391/* field: RX6THRESHMASK - Receive channel 6 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
392#define TMS570_EMACM_RXINTMASKSET_RX6THRESHMASK BSP_BIT32(14)
393
394/* field: RX5THRESHMASK - Receive channel 5 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
395#define TMS570_EMACM_RXINTMASKSET_RX5THRESHMASK BSP_BIT32(13)
396
397/* field: RX4THRESHMASK - Receive channel 4 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
398#define TMS570_EMACM_RXINTMASKSET_RX4THRESHMASK BSP_BIT32(12)
399
400/* field: RX3THRESHMASK - Receive channel 3 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
401#define TMS570_EMACM_RXINTMASKSET_RX3THRESHMASK BSP_BIT32(11)
402
403/* field: RX2THRESHMASK - Receive channel 2 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
404#define TMS570_EMACM_RXINTMASKSET_RX2THRESHMASK BSP_BIT32(10)
405
406/* field: RX1THRESHMASK - Receive channel 1 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
407#define TMS570_EMACM_RXINTMASKSET_RX1THRESHMASK BSP_BIT32(9)
408
409/* field: RX0THRESHMASK - Receive channel 0 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
410#define TMS570_EMACM_RXINTMASKSET_RX0THRESHMASK BSP_BIT32(8)
411
412/* field: RX7MASK - Receive channel 7 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
413#define TMS570_EMACM_RXINTMASKSET_RX7MASK BSP_BIT32(7)
414
415/* field: RX6MASK - Receive channel 6 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
416#define TMS570_EMACM_RXINTMASKSET_RX6MASK BSP_BIT32(6)
417
418/* field: RX5MASK - Receive channel 5 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
419#define TMS570_EMACM_RXINTMASKSET_RX5MASK BSP_BIT32(5)
420
421/* field: RX4MASK - Receive channel 4 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
422#define TMS570_EMACM_RXINTMASKSET_RX4MASK BSP_BIT32(4)
423
424/* field: RX3MASK - Receive channel 3 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
425#define TMS570_EMACM_RXINTMASKSET_RX3MASK BSP_BIT32(3)
426
427/* field: RX2MASK - Receive channel 2 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
428#define TMS570_EMACM_RXINTMASKSET_RX2MASK BSP_BIT32(2)
429
430/* field: RX1MASK - Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
431#define TMS570_EMACM_RXINTMASKSET_RX1MASK BSP_BIT32(1)
432
433/* field: RX0MASK - Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
434#define TMS570_EMACM_RXINTMASKSET_RX0MASK BSP_BIT32(0)
435
436
437/*----------------TMS570_EMACM_RXINTMASKCLEAR----------------*/
438/* field: RX7THRESHMASK - Receive channel 7 threshold mask clear bit. */
439#define TMS570_EMACM_RXINTMASKCLEAR_RX7THRESHMASK BSP_BIT32(15)
440
441/* field: RX6THRESHMASK - Receive channel 6 threshold mask clear bit. */
442#define TMS570_EMACM_RXINTMASKCLEAR_RX6THRESHMASK BSP_BIT32(14)
443
444/* field: RX5THRESHMASK - Receive channel 5 threshold mask clear bit. */
445#define TMS570_EMACM_RXINTMASKCLEAR_RX5THRESHMASK BSP_BIT32(13)
446
447/* field: RX4THRESHMASK - Receive channel 4 threshold mask clear bit. */
448#define TMS570_EMACM_RXINTMASKCLEAR_RX4THRESHMASK BSP_BIT32(12)
449
450/* field: RX3THRESHMASK - Receive channel 3 threshold mask clear bit. */
451#define TMS570_EMACM_RXINTMASKCLEAR_RX3THRESHMASK BSP_BIT32(11)
452
453/* field: RX2THRESHMASK - Receive channel 2 threshold mask clear bit. */
454#define TMS570_EMACM_RXINTMASKCLEAR_RX2THRESHMASK BSP_BIT32(10)
455
456/* field: RX1THRESHMASK - Receive channel 1 threshold mask clear bit. */
457#define TMS570_EMACM_RXINTMASKCLEAR_RX1THRESHMASK BSP_BIT32(9)
458
459/* field: RX0THRESHMASK - Receive channel 0 threshold mask clear bit. */
460#define TMS570_EMACM_RXINTMASKCLEAR_RX0THRESHMASK BSP_BIT32(8)
461
462/* field: RX7MASK - Receive channel 7 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
463#define TMS570_EMACM_RXINTMASKCLEAR_RX7MASK BSP_BIT32(7)
464
465/* field: RX6MASK - Receive channel 6 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
466#define TMS570_EMACM_RXINTMASKCLEAR_RX6MASK BSP_BIT32(6)
467
468/* field: RX5MASK - Receive channel 5 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
469#define TMS570_EMACM_RXINTMASKCLEAR_RX5MASK BSP_BIT32(5)
470
471/* field: RX4MASK - Receive channel 4 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
472#define TMS570_EMACM_RXINTMASKCLEAR_RX4MASK BSP_BIT32(4)
473
474/* field: RX3MASK - Receive channel 3 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
475#define TMS570_EMACM_RXINTMASKCLEAR_RX3MASK BSP_BIT32(3)
476
477/* field: RX2MASK - Receive channel 2 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
478#define TMS570_EMACM_RXINTMASKCLEAR_RX2MASK BSP_BIT32(2)
479
480/* field: RX1MASK - Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
481#define TMS570_EMACM_RXINTMASKCLEAR_RX1MASK BSP_BIT32(1)
482
483/* field: RX0MASK - Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
484#define TMS570_EMACM_RXINTMASKCLEAR_RX0MASK BSP_BIT32(0)
485
486
487/*-----------------TMS570_EMACM_MACINTSTATRAW-----------------*/
488/* field: HOSTPEND - Host pending interrupt (HOSTPEND); raw interrupt read (before mask). */
489#define TMS570_EMACM_MACINTSTATRAW_HOSTPEND BSP_BIT32(1)
490
491/* field: STATPEND - Statistics pending interrupt (STATPEND); raw interrupt read (before mask). */
492#define TMS570_EMACM_MACINTSTATRAW_STATPEND BSP_BIT32(0)
493
494
495/*---------------TMS570_EMACM_MACINTSTATMASKED---------------*/
496/* field: HOSTPEND - Host pending interrupt (HOSTPEND); masked interrupt read. */
497#define TMS570_EMACM_MACINTSTATMASKED_HOSTPEND BSP_BIT32(1)
498
499/* field: STATPEND - Statistics pending interrupt (STATPEND); masked interrupt read. */
500#define TMS570_EMACM_MACINTSTATMASKED_STATPEND BSP_BIT32(0)
501
502
503/*-----------------TMS570_EMACM_MACINTMASKSET-----------------*/
504/* field: HOSTMASK - Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
505#define TMS570_EMACM_MACINTMASKSET_HOSTMASK BSP_BIT32(1)
506
507/* field: STATMASK - Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
508#define TMS570_EMACM_MACINTMASKSET_STATMASK BSP_BIT32(0)
509
510
511/*----------------TMS570_EMACM_MACINTMASKCLEAR----------------*/
512/* field: HOSTMASK - Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
513#define TMS570_EMACM_MACINTMASKCLEAR_HOSTMASK BSP_BIT32(1)
514
515/* field: STATMASK - Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
516#define TMS570_EMACM_MACINTMASKCLEAR_STATMASK BSP_BIT32(0)
517
518
519/*------------------TMS570_EMACM_RXMBPENABLE------------------*/
520/* field: RXPASSCRC - Pass receive CRC enable bit */
521#define TMS570_EMACM_RXMBPENABLE_RXPASSCRC BSP_BIT32(30)
522
523/* field: RXQOSEN - Receive quality of service enable bit */
524#define TMS570_EMACM_RXMBPENABLE_RXQOSEN BSP_BIT32(29)
525
526/* field: RXNOCHAIN - Receive no buffer chaining bit */
527#define TMS570_EMACM_RXMBPENABLE_RXNOCHAIN BSP_BIT32(28)
528
529/* field: RXCMFEN - Receive copy MAC control frames enable bit. */
530#define TMS570_EMACM_RXMBPENABLE_RXCMFEN BSP_BIT32(24)
531
532/* field: RXCSFEN - Receive copy short frames enable bit. */
533#define TMS570_EMACM_RXMBPENABLE_RXCSFEN BSP_BIT32(23)
534
535/* field: RXCEFEN - Receive copy error frames enable bit. */
536#define TMS570_EMACM_RXMBPENABLE_RXCEFEN BSP_BIT32(22)
537
538/* field: RXCAFEN - Receive copy all frames enable bit. */
539#define TMS570_EMACM_RXMBPENABLE_RXCAFEN BSP_BIT32(21)
540
541/* field: RXPROMCH - Receive promiscuous channel select */
542#define TMS570_EMACM_RXMBPENABLE_RXPROMCH(val) BSP_FLD32(val,16, 18)
543#define TMS570_EMACM_RXMBPENABLE_RXPROMCH_GET(reg) BSP_FLD32GET(reg,16, 18)
544#define TMS570_EMACM_RXMBPENABLE_RXPROMCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
545
546/* field: RXBROADEN - Receive broadcast enable. */
547#define TMS570_EMACM_RXMBPENABLE_RXBROADEN BSP_BIT32(13)
548
549/* field: RXBROADCH - Receive broadcast channel select */
550#define TMS570_EMACM_RXMBPENABLE_RXBROADCH(val) BSP_FLD32(val,8, 10)
551#define TMS570_EMACM_RXMBPENABLE_RXBROADCH_GET(reg) BSP_FLD32GET(reg,8, 10)
552#define TMS570_EMACM_RXMBPENABLE_RXBROADCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
553
554/* field: RXMULTEN - RX multicast enable. */
555#define TMS570_EMACM_RXMBPENABLE_RXMULTEN BSP_BIT32(5)
556
557
558/*-----------------TMS570_EMACM_RXUNICASTSET-----------------*/
559/* field: RXCH7EN - Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
560#define TMS570_EMACM_RXUNICASTSET_RXCH7EN BSP_BIT32(7)
561
562/* field: RXCH6EN - Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
563#define TMS570_EMACM_RXUNICASTSET_RXCH6EN BSP_BIT32(6)
564
565/* field: RXCH5EN - Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
566#define TMS570_EMACM_RXUNICASTSET_RXCH5EN BSP_BIT32(5)
567
568/* field: RXCH4EN - Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
569#define TMS570_EMACM_RXUNICASTSET_RXCH4EN BSP_BIT32(4)
570
571/* field: RXCH3EN - Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
572#define TMS570_EMACM_RXUNICASTSET_RXCH3EN BSP_BIT32(3)
573
574/* field: RXCH2EN - Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
575#define TMS570_EMACM_RXUNICASTSET_RXCH2EN BSP_BIT32(2)
576
577/* field: RXCH1EN - Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
578#define TMS570_EMACM_RXUNICASTSET_RXCH1EN BSP_BIT32(1)
579
580/* field: RXCH0EN - Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
581#define TMS570_EMACM_RXUNICASTSET_RXCH0EN BSP_BIT32(0)
582
583
584/*----------------TMS570_EMACM_RXUNICASTCLEAR----------------*/
585/* field: RXCH7EN - Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
586#define TMS570_EMACM_RXUNICASTCLEAR_RXCH7EN BSP_BIT32(7)
587
588/* field: RXCH6EN - Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
589#define TMS570_EMACM_RXUNICASTCLEAR_RXCH6EN BSP_BIT32(6)
590
591/* field: RXCH5EN - Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
592#define TMS570_EMACM_RXUNICASTCLEAR_RXCH5EN BSP_BIT32(5)
593
594/* field: RXCH4EN - Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
595#define TMS570_EMACM_RXUNICASTCLEAR_RXCH4EN BSP_BIT32(4)
596
597/* field: RXCH3EN - Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
598#define TMS570_EMACM_RXUNICASTCLEAR_RXCH3EN BSP_BIT32(3)
599
600/* field: RXCH2EN - Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
601#define TMS570_EMACM_RXUNICASTCLEAR_RXCH2EN BSP_BIT32(2)
602
603/* field: RXCH1EN - Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
604#define TMS570_EMACM_RXUNICASTCLEAR_RXCH1EN BSP_BIT32(1)
605
606/* field: RXCH0EN - Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
607#define TMS570_EMACM_RXUNICASTCLEAR_RXCH0EN BSP_BIT32(0)
608
609
610/*-------------------TMS570_EMACM_RXMAXLEN-------------------*/
611/* field: RXMAXLEN - Receive maximum frame length. These bits determine the maximum length of a received frame. */
612#define TMS570_EMACM_RXMAXLEN_RXMAXLEN(val) BSP_FLD32(val,0, 15)
613#define TMS570_EMACM_RXMAXLEN_RXMAXLEN_GET(reg) BSP_FLD32GET(reg,0, 15)
614#define TMS570_EMACM_RXMAXLEN_RXMAXLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
615
616
617/*----------------TMS570_EMACM_RXBUFFEROFFSET----------------*/
618/* field: RXBUFFEROFFSET - Receive buffer offset value. */
619#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET(val) BSP_FLD32(val,0, 15)
620#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_GET(reg) BSP_FLD32GET(reg,0, 15)
621#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
622
623
624/*---------------TMS570_EMACM_RXFILTERLOWTHRESH---------------*/
625/* field: RXFILTERTHRESH - Receive filter low threshold. */
626#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH(val) BSP_FLD32(val,0, 7)
627#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7)
628#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
629
630
631/*-----------------TMS570_EMACM_RXFLOWTHRESH-----------------*/
632/* field: RXnFLOWTHRESH - Receive flow threshold. */
633#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH(val) BSP_FLD32(val,0, 7)
634#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7)
635#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
636
637
638/*-----------------TMS570_EMACM_RXFREEBUFFER-----------------*/
639/* field: RXnFREEBUF - Receive free buffer count. These bits contain the count of free buffers available. */
640#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF(val) BSP_FLD32(val,0, 15)
641#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_GET(reg) BSP_FLD32GET(reg,0, 15)
642#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
643
644
645/*------------------TMS570_EMACM_MACCONTROL------------------*/
646/* field: RMIISPEED - RMII interface transmit and receive speed select. */
647#define TMS570_EMACM_MACCONTROL_RMIISPEED BSP_BIT32(15)
648
649/* field: RXOFFLENBLOCK - Receive offset / length word write block. */
650#define TMS570_EMACM_MACCONTROL_RXOFFLENBLOCK BSP_BIT32(14)
651
652/* field: RXOWNERSHIP - Receive ownership write bit value. */
653#define TMS570_EMACM_MACCONTROL_RXOWNERSHIP BSP_BIT32(13)
654
655/* field: CMDIDLE - Command Idle bit */
656#define TMS570_EMACM_MACCONTROL_CMDIDLE BSP_BIT32(11)
657
658/* field: TXSHORTGAPEN - Transmit Short Gap Enable */
659#define TMS570_EMACM_MACCONTROL_TXSHORTGAPEN BSP_BIT32(10)
660
661/* field: TXPTYPE - Transmit queue priority type */
662#define TMS570_EMACM_MACCONTROL_TXPTYPE BSP_BIT32(9)
663
664/* field: TXPACE - Transmit pacing enable bit */
665#define TMS570_EMACM_MACCONTROL_TXPACE BSP_BIT32(6)
666
667/* field: GMIIEN - GMII enable bit */
668#define TMS570_EMACM_MACCONTROL_GMIIEN BSP_BIT32(5)
669
670/* field: TXFLOWEN - Transmit flow control enable bit. */
671#define TMS570_EMACM_MACCONTROL_TXFLOWEN BSP_BIT32(4)
672
673/* field: RXBUFFERFLOWEN - Receive buffer flow control enable bit */
674#define TMS570_EMACM_MACCONTROL_RXBUFFERFLOWEN BSP_BIT32(3)
675
676/* field: LOOPBACK - Loopback mode. The loopback mode forces internal full-duplex mode regardless of the FULLDUPLEX bit. */
677#define TMS570_EMACM_MACCONTROL_LOOPBACK BSP_BIT32(1)
678
679/* field: FULLDUPLEX - Full duplex mode. */
680#define TMS570_EMACM_MACCONTROL_FULLDUPLEX BSP_BIT32(0)
681
682
683/*-------------------TMS570_EMACM_MACSTATUS-------------------*/
684/* field: IDLE - EMAC idle bit. This bit is cleared to 0 at reset; one clock after reset, it goes to 1. */
685#define TMS570_EMACM_MACSTATUS_IDLE BSP_BIT32(31)
686
687/* field: TXERRCODE - Transmit host error code. These bits indicate that EMAC detected transmit DMA related host errors. */
688#define TMS570_EMACM_MACSTATUS_TXERRCODE(val) BSP_FLD32(val,20, 23)
689#define TMS570_EMACM_MACSTATUS_TXERRCODE_GET(reg) BSP_FLD32GET(reg,20, 23)
690#define TMS570_EMACM_MACSTATUS_TXERRCODE_SET(reg,val) BSP_FLD32SET(reg, val,20, 23)
691
692/* field: TXERRCH - Transmit host error channel. These bits indicate which transmit channel the host error occurred on. */
693#define TMS570_EMACM_MACSTATUS_TXERRCH(val) BSP_FLD32(val,16, 18)
694#define TMS570_EMACM_MACSTATUS_TXERRCH_GET(reg) BSP_FLD32GET(reg,16, 18)
695#define TMS570_EMACM_MACSTATUS_TXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
696
697/* field: RXERRCODE - Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. */
698#define TMS570_EMACM_MACSTATUS_RXERRCODE(val) BSP_FLD32(val,12, 15)
699#define TMS570_EMACM_MACSTATUS_RXERRCODE_GET(reg) BSP_FLD32GET(reg,12, 15)
700#define TMS570_EMACM_MACSTATUS_RXERRCODE_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
701
702/* field: RXERRCH - Receive host error channel. These bits indicate which receive channel the host error occurred on. */
703#define TMS570_EMACM_MACSTATUS_RXERRCH(val) BSP_FLD32(val,8, 10)
704#define TMS570_EMACM_MACSTATUS_RXERRCH_GET(reg) BSP_FLD32GET(reg,8, 10)
705#define TMS570_EMACM_MACSTATUS_RXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
706
707/* field: RXQOSACT - Receive Quality of Service (QOS) active bit. */
708#define TMS570_EMACM_MACSTATUS_RXQOSACT BSP_BIT32(2)
709
710/* field: RXFLOWACT - Receive flow control active bit. */
711#define TMS570_EMACM_MACSTATUS_RXFLOWACT BSP_BIT32(1)
712
713/* field: TXFLOWACT - Transmit flow control active bit. */
714#define TMS570_EMACM_MACSTATUS_TXFLOWACT BSP_BIT32(0)
715
716
717/*-------------------TMS570_EMACM_EMCONTROL-------------------*/
718/* field: SOFT - Emulation soft bit. */
719#define TMS570_EMACM_EMCONTROL_SOFT BSP_BIT32(1)
720
721/* field: FREE - Emulation free bit. */
722#define TMS570_EMACM_EMCONTROL_FREE BSP_BIT32(0)
723
724
725/*------------------TMS570_EMACM_FIFOCONTROL------------------*/
726/* field: TXCELLTHRESH - Transmit FIFO cell threshold. */
727#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH(val) BSP_FLD32(val,0, 1)
728#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_GET(reg) BSP_FLD32GET(reg,0, 1)
729#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
730
731
732/*-------------------TMS570_EMACM_MACCONFIG-------------------*/
733/* field: TXCELLDEPTH - Transmit cell depth. These bits indicate the number of cells in the transmit FIFO. */
734#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH(val) BSP_FLD32(val,24, 31)
735#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,24, 31)
736#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
737
738/* field: RXCELLDEPTH - Receive cell depth. These bits indicate the number of cells in the receive FIFO. */
739#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH(val) BSP_FLD32(val,16, 23)
740#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,16, 23)
741#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
742
743/* field: ADDRESSTYPE - Address type */
744#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE(val) BSP_FLD32(val,8, 15)
745#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE_GET(reg) BSP_FLD32GET(reg,8, 15)
746#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
747
748/* field: MACCFIG - MAC configuration value */
749#define TMS570_EMACM_MACCONFIG_MACCFIG(val) BSP_FLD32(val,0, 7)
750#define TMS570_EMACM_MACCONFIG_MACCFIG_GET(reg) BSP_FLD32GET(reg,0, 7)
751#define TMS570_EMACM_MACCONFIG_MACCFIG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
752
753
754/*-------------------TMS570_EMACM_SOFTRESET-------------------*/
755/* field: SOFTRESET - Software reset. Writing a 1 to this bit causes the EMAC logic to be reset. */
756#define TMS570_EMACM_SOFTRESET_SOFTRESET BSP_BIT32(0)
757
758
759/*-----------------TMS570_EMACM_MACSRCADDRLO-----------------*/
760/* field: MACSRCADDR0 - MAC source address lower 8-0 bits (byte 0) */
761#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0(val) BSP_FLD32(val,8, 15)
762#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_GET(reg) BSP_FLD32GET(reg,8, 15)
763#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
764
765/* field: MACSRCADDR1 - MAC source address bits 15-8 (byte 1) */
766#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1(val) BSP_FLD32(val,0, 7)
767#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_GET(reg) BSP_FLD32GET(reg,0, 7)
768#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
769
770
771/*-----------------TMS570_EMACM_MACSRCADDRHI-----------------*/
772/* field: MACSRCADDR2 - MAC source address bits 23-16 (byte 2) */
773#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2(val) BSP_FLD32(val,24, 31)
774#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_GET(reg) BSP_FLD32GET(reg,24, 31)
775#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
776
777/* field: MACSRCADDR3 - MAC source address bits 31-24 (byte 3) */
778#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3(val) BSP_FLD32(val,16, 23)
779#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3_GET(reg) BSP_FLD32GET(reg,16, 23)
780#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
781
782/* field: MACSRCADDR4 - MAC source address bits 39-32 (byte 4) */
783#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4(val) BSP_FLD32(val,8, 15)
784#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4_GET(reg) BSP_FLD32GET(reg,8, 15)
785#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
786
787/* field: MACSRCADDR5 - MAC source address bits 47-40 (byte 5) */
788#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5(val) BSP_FLD32(val,0, 7)
789#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_GET(reg) BSP_FLD32GET(reg,0, 7)
790#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
791
792
793/*-------------------TMS570_EMACM_MACHASH1-------------------*/
794/* field: MACHASH1 - Least-significant 32 bits of the hash table corresponding to hash values 0 to 31. */
795/* Whole 32 bits */
796
797/*-------------------TMS570_EMACM_MACHASH2-------------------*/
798/* field: MACHASH2 - Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. */
799/* Whole 32 bits */
800
801/*-------------------TMS570_EMACM_BOFFTEST-------------------*/
802/* field: RNDNUM - Backoff random number generator. */
803#define TMS570_EMACM_BOFFTEST_RNDNUM(val) BSP_FLD32(val,16, 25)
804#define TMS570_EMACM_BOFFTEST_RNDNUM_GET(reg) BSP_FLD32GET(reg,16, 25)
805#define TMS570_EMACM_BOFFTEST_RNDNUM_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
806
807/* field: COLLCOUNT - Collision count. These bits indicate the number of collisions the current frame has experienced. */
808#define TMS570_EMACM_BOFFTEST_COLLCOUNT(val) BSP_FLD32(val,12, 15)
809#define TMS570_EMACM_BOFFTEST_COLLCOUNT_GET(reg) BSP_FLD32GET(reg,12, 15)
810#define TMS570_EMACM_BOFFTEST_COLLCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
811
812/* field: TXBACKOFF - Backoff count. */
813#define TMS570_EMACM_BOFFTEST_TXBACKOFF(val) BSP_FLD32(val,0, 9)
814#define TMS570_EMACM_BOFFTEST_TXBACKOFF_GET(reg) BSP_FLD32GET(reg,0, 9)
815#define TMS570_EMACM_BOFFTEST_TXBACKOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
816
817
818/*-------------------TMS570_EMACM_TPACETEST-------------------*/
819/* field: PACEVAL - Pacing register current value. A nonzero value in this field indicates that transmit pacing is active. */
820#define TMS570_EMACM_TPACETEST_PACEVAL(val) BSP_FLD32(val,0, 4)
821#define TMS570_EMACM_TPACETEST_PACEVAL_GET(reg) BSP_FLD32GET(reg,0, 4)
822#define TMS570_EMACM_TPACETEST_PACEVAL_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
823
824
825/*--------------------TMS570_EMACM_RXPAUSE--------------------*/
826/* field: PAUSETIMER - Receive pause timer value. */
827#define TMS570_EMACM_RXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
828#define TMS570_EMACM_RXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15)
829#define TMS570_EMACM_RXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
830
831
832/*--------------------TMS570_EMACM_TXPAUSE--------------------*/
833/* field: PAUSETIMER - Transmit pause timer value. */
834#define TMS570_EMACM_TXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
835#define TMS570_EMACM_TXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15)
836#define TMS570_EMACM_TXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
837
838
839/*-------------------TMS570_EMACM_MACADDRLO-------------------*/
840/* field: VALID - Address valid bit. */
841#define TMS570_EMACM_MACADDRLO_VALID BSP_BIT32(20)
842
843/* field: MATCHFILT - Match or filter bit */
844#define TMS570_EMACM_MACADDRLO_MATCHFILT BSP_BIT32(19)
845
846/* field: CHANNEL - Channel select. Determines which receive channel a valid address match will be transferred to. */
847#define TMS570_EMACM_MACADDRLO_CHANNEL(val) BSP_FLD32(val,16, 18)
848#define TMS570_EMACM_MACADDRLO_CHANNEL_GET(reg) BSP_FLD32GET(reg,16, 18)
849#define TMS570_EMACM_MACADDRLO_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
850
851/* field: MACADDR0 - MAC address lower 8-0 bits (byte 0) */
852#define TMS570_EMACM_MACADDRLO_MACADDR0(val) BSP_FLD32(val,8, 15)
853#define TMS570_EMACM_MACADDRLO_MACADDR0_GET(reg) BSP_FLD32GET(reg,8, 15)
854#define TMS570_EMACM_MACADDRLO_MACADDR0_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
855
856/* field: MACADDR1 - MAC address bits 15-8 (byte 1) */
857#define TMS570_EMACM_MACADDRLO_MACADDR1(val) BSP_FLD32(val,0, 7)
858#define TMS570_EMACM_MACADDRLO_MACADDR1_GET(reg) BSP_FLD32GET(reg,0, 7)
859#define TMS570_EMACM_MACADDRLO_MACADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
860
861
862/*-------------------TMS570_EMACM_MACADDRHI-------------------*/
863/* field: MACADDR2 - MAC source address bits 23-16 (byte 2) */
864#define TMS570_EMACM_MACADDRHI_MACADDR2(val) BSP_FLD32(val,24, 31)
865#define TMS570_EMACM_MACADDRHI_MACADDR2_GET(reg) BSP_FLD32GET(reg,24, 31)
866#define TMS570_EMACM_MACADDRHI_MACADDR2_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
867
868/* field: MACADDR3 - MAC source address bits 31-24 (byte 3) */
869#define TMS570_EMACM_MACADDRHI_MACADDR3(val) BSP_FLD32(val,16, 23)
870#define TMS570_EMACM_MACADDRHI_MACADDR3_GET(reg) BSP_FLD32GET(reg,16, 23)
871#define TMS570_EMACM_MACADDRHI_MACADDR3_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
872
873/* field: MACADDR4 - MAC source address bits 39-32 (byte 4) */
874#define TMS570_EMACM_MACADDRHI_MACADDR4(val) BSP_FLD32(val,8, 15)
875#define TMS570_EMACM_MACADDRHI_MACADDR4_GET(reg) BSP_FLD32GET(reg,8, 15)
876#define TMS570_EMACM_MACADDRHI_MACADDR4_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
877
878/* field: MACADDR5 - MAC source address bits 47-40 (byte 5). Bit 40 is the group bit. It is forced to 0 and read as 0. */
879#define TMS570_EMACM_MACADDRHI_MACADDR5(val) BSP_FLD32(val,0, 7)
880#define TMS570_EMACM_MACADDRHI_MACADDR5_GET(reg) BSP_FLD32GET(reg,0, 7)
881#define TMS570_EMACM_MACADDRHI_MACADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
882
883
884/*-------------------TMS570_EMACM_MACINDEX-------------------*/
885/* field: MACINDEX - MAC address index. All eight addresses share the upper 40 bits. */
886#define TMS570_EMACM_MACINDEX_MACINDEX(val) BSP_FLD32(val,0, 2)
887#define TMS570_EMACM_MACINDEX_MACINDEX_GET(reg) BSP_FLD32GET(reg,0, 2)
888#define TMS570_EMACM_MACINDEX_MACINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
889
890
891/*---------------------TMS570_EMACM_TXHDP---------------------*/
892/* field: TXnHDP - Transmit channel n DMA Head Descriptor pointer. */
893/* Whole 32 bits */
894
895/*---------------------TMS570_EMACM_RXHDP---------------------*/
896/* field: RXnHDP - Receive channel n DMA Head Descriptor pointer. */
897/* Whole 32 bits */
898
899/*---------------------TMS570_EMACM_TXCP---------------------*/
900/* field: TXnCP - Transmit channel n completion pointer register is written by the host with the buffer descriptor */
901/* Whole 32 bits */
902
903/*---------------------TMS570_EMACM_RXCP---------------------*/
904/* field: RXnCP - Receive channel n completion pointer register is written by the host with the buffer descriptor */
905/* Whole 32 bits */
906
907
908#endif /* LIBBSP_ARM_TMS570_EMACM */
utility.h
This header file provides utility macros for BSPs.
tms570_emacm_t
Definition: reg_emacm.h:54
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