RTEMS 6.1-rc4
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reg_emacc.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/* The header file is generated by make_header.py from EMACC.json */
12/* Current script's version can be found at: */
13/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
14
15/*
16 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
17 *
18 * Czech Technical University in Prague
19 * Zikova 1903/4
20 * 166 36 Praha 6
21 * Czech Republic
22 *
23 * All rights reserved.
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following disclaimer in the documentation
32 * and/or other materials provided with the distribution.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
38 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
40 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
41 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
43 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * The views and conclusions contained in the software and documentation are those
46 * of the authors and should not be interpreted as representing official policies,
47 * either expressed or implied, of the FreeBSD Project.
48*/
49#ifndef LIBBSP_ARM_TMS570_EMACC
50#define LIBBSP_ARM_TMS570_EMACC
51
52#include <bsp/utility.h>
53
54typedef struct{
55 uint32_t REVID; /*EMAC Control Module Revision ID Register*/
56 uint32_t SOFTRESET; /*EMAC Control Module Software Reset Register*/
57 uint8_t reserved1 [4];
58 uint32_t INTCONTROL; /*EMAC Control Module Interrupt Control Register*/
59 uint32_t C0RXTHRESHEN; /*EMAC Control Module Receive Threshold Interrupt Enable Register*/
60 uint32_t C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/
61 uint32_t C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/
62 uint32_t C0MISCEN; /*EMAC Control Module Miscellaneous Interrupt Enable Register*/
63 uint8_t reserved2 [32];
64 uint32_t C0RXTHRESHSTAT; /*EMAC Control Module Receive Threshold Interrupt Status Register*/
65 uint32_t C0RXSTAT; /*EMAC Control Module Receive Interrupt Status Register*/
66 uint32_t C0TXSTAT; /*EMAC Control Module Transmit Interrupt Status Register*/
67 uint32_t C0MISCSTAT; /*EMAC Control Module Miscellaneous Interrupt Status Register*/
68 uint8_t reserved3 [32];
69 uint32_t C0RXIMAX; /*EMAC Control Module Receive Interrupts Per Millisecond Register*/
70 uint32_t C0TXIMAX; /*EMAC Control Module Transmit Interrupts Per Millisecond Register*/
71} tms570_emacc_t;
72
73
74/*---------------------TMS570_EMACC_REVID---------------------*/
75/* field: REV - Identifies the EMAC Control Module revision. */
76/* Whole 32 bits */
77
78/*-------------------TMS570_EMACC_SOFTRESET-------------------*/
79/* field: RESET - Software reset bit for the EMAC Control Module. */
80#define TMS570_EMACC_SOFTRESET_RESET BSP_BIT32(0)
81
82
83/*------------------TMS570_EMACC_INTCONTROL------------------*/
84/* field: C0TXPACEEN - Enable pacing for TX interrupt pulse generation */
85#define TMS570_EMACC_INTCONTROL_C0TXPACEEN BSP_BIT32(17)
86
87/* field: C0RXPACEEN - Enable pacing for RX interrupt pulse generation */
88#define TMS570_EMACC_INTCONTROL_C0RXPACEEN BSP_BIT32(16)
89
90/* field: INTPRESCALE - Number of internal EMAC module reference clock periods within a 4 us time window (see */
91#define TMS570_EMACC_INTCONTROL_INTPRESCALE(val) BSP_FLD32(val,0, 11)
92#define TMS570_EMACC_INTCONTROL_INTPRESCALE_GET(reg) BSP_FLD32GET(reg,0, 11)
93#define TMS570_EMACC_INTCONTROL_INTPRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
94
95
96/*-----------------TMS570_EMACC_C0RXTHRESHEN-----------------*/
97/* field: RXCH7THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 7 */
98#define TMS570_EMACC_C0RXTHRESHEN_RXCH7THRESHEN BSP_BIT32(7)
99
100/* field: RXCH6THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 6 */
101#define TMS570_EMACC_C0RXTHRESHEN_RXCH6THRESHEN BSP_BIT32(6)
102
103/* field: RXCH5THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 5 */
104#define TMS570_EMACC_C0RXTHRESHEN_RXCH5THRESHEN BSP_BIT32(5)
105
106/* field: RXCH4THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 4 */
107#define TMS570_EMACC_C0RXTHRESHEN_RXCH4THRESHEN BSP_BIT32(4)
108
109/* field: RXCH3THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 3 */
110#define TMS570_EMACC_C0RXTHRESHEN_RXCH3THRESHEN BSP_BIT32(3)
111
112/* field: RXCH2THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 2 */
113#define TMS570_EMACC_C0RXTHRESHEN_RXCH2THRESHEN BSP_BIT32(2)
114
115/* field: RXCH1THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 1 */
116#define TMS570_EMACC_C0RXTHRESHEN_RXCH1THRESHEN BSP_BIT32(1)
117
118/* field: RXCH0THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 0 */
119#define TMS570_EMACC_C0RXTHRESHEN_RXCH0THRESHEN BSP_BIT32(0)
120
121
122/*--------------------TMS570_EMACC_C0RXEN--------------------*/
123/* field: RXCH7EN - Enable C0RXPULSE interrupt generation for RX Channel 7 */
124#define TMS570_EMACC_C0RXEN_RXCH7EN BSP_BIT32(7)
125
126/* field: RXCH6EN - Enable C0RXPULSE interrupt generation for RX Channel 6 */
127#define TMS570_EMACC_C0RXEN_RXCH6EN BSP_BIT32(6)
128
129/* field: RXCH5EN - Enable C0RXPULSE interrupt generation for RX Channel 5 */
130#define TMS570_EMACC_C0RXEN_RXCH5EN BSP_BIT32(5)
131
132/* field: RXCH4EN - Enable C0RXPULSE interrupt generation for RX Channel 4 */
133#define TMS570_EMACC_C0RXEN_RXCH4EN BSP_BIT32(4)
134
135/* field: RXCH3EN - Enable C0RXPULSE interrupt generation for RX Channel 3 */
136#define TMS570_EMACC_C0RXEN_RXCH3EN BSP_BIT32(3)
137
138/* field: RXCH2EN - Enable C0RXPULSE interrupt generation for RX Channel 2 */
139#define TMS570_EMACC_C0RXEN_RXCH2EN BSP_BIT32(2)
140
141/* field: RXCH1EN - Enable C0RXPULSE interrupt generation for RX Channel 1 */
142#define TMS570_EMACC_C0RXEN_RXCH1EN BSP_BIT32(1)
143
144/* field: RXCH0EN - Enable C0RXPULSE interrupt generation for RX Channel 0 */
145#define TMS570_EMACC_C0RXEN_RXCH0EN BSP_BIT32(0)
146
147
148/*--------------------TMS570_EMACC_C0TXEN--------------------*/
149/* field: TXCH7EN - Enable C0TXPULSE interrupt generation for TX Channel 7 */
150#define TMS570_EMACC_C0TXEN_TXCH7EN BSP_BIT32(7)
151
152/* field: TXCH6EN - TXCH6EN */
153#define TMS570_EMACC_C0TXEN_TXCH6EN BSP_BIT32(6)
154
155/* field: TXCH5EN - Enable C0TXPULSE interrupt generation for TX Channel 5 */
156#define TMS570_EMACC_C0TXEN_TXCH5EN BSP_BIT32(5)
157
158/* field: TXCH4EN - Enable C0TXPULSE interrupt generation for TX Channel 4 */
159#define TMS570_EMACC_C0TXEN_TXCH4EN BSP_BIT32(4)
160
161/* field: TXCH3EN - Enable C0TXPULSE interrupt generation for TX Channel 3 */
162#define TMS570_EMACC_C0TXEN_TXCH3EN BSP_BIT32(3)
163
164/* field: TXCH2EN - Enable C0TXPULSE interrupt generation for TX Channel 2 */
165#define TMS570_EMACC_C0TXEN_TXCH2EN BSP_BIT32(2)
166
167/* field: TXCH1EN - Enable C0TXPULSE interrupt generation for TX Channel 1 */
168#define TMS570_EMACC_C0TXEN_TXCH1EN BSP_BIT32(1)
169
170/* field: TXCH0EN - Enable C0TXPULSE interrupt generation for TX Channel 0 */
171#define TMS570_EMACC_C0TXEN_TXCH0EN BSP_BIT32(0)
172
173
174/*-------------------TMS570_EMACC_C0MISCEN-------------------*/
175/* field: STATPENDEN - Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated */
176#define TMS570_EMACC_C0MISCEN_STATPENDEN BSP_BIT32(3)
177
178/* field: HOSTPENDEN - HOSTPENDEN */
179#define TMS570_EMACC_C0MISCEN_HOSTPENDEN BSP_BIT32(2)
180
181/* field: LINKINT0EN - Enable C0MISCPULSE interrupt generation when MDIO LINKINT0 interrupts (corresponding to */
182#define TMS570_EMACC_C0MISCEN_LINKINT0EN BSP_BIT32(1)
183
184/* field: USERINT0EN - Enable C0MISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding */
185#define TMS570_EMACC_C0MISCEN_USERINT0EN BSP_BIT32(0)
186
187
188/*----------------TMS570_EMACC_C0RXTHRESHSTAT----------------*/
189/* field: RXCH7THRESHSTAT - Interrupt status for RX Channel 7 masked by the C0RXTHRESHEN register */
190#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH7THRESHSTAT BSP_BIT32(7)
191
192/* field: RXCH6THRESHSTAT - Interrupt status for RX Channel 6 masked by the C0RXTHRESHEN register */
193#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH6THRESHSTAT BSP_BIT32(6)
194
195/* field: RXCH5THRESHSTAT - Interrupt status for RX Channel 5 masked by the C0RXTHRESHEN register */
196#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH5THRESHSTAT BSP_BIT32(5)
197
198/* field: RXCH4THRESHSTAT - Interrupt status for RX Channel 4 masked by the C0RXTHRESHEN register */
199#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH4THRESHSTAT BSP_BIT32(4)
200
201/* field: RXCH3THRESHSTAT - Interrupt status for RX Channel 3 masked by the C0RXTHRESHEN register */
202#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH3THRESHSTAT BSP_BIT32(3)
203
204/* field: RXCH2THRESHSTAT - Interrupt status for RX Channel 2 masked by the C0RXTHRESHEN register */
205#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH2THRESHSTAT BSP_BIT32(2)
206
207/* field: RXCH1THRESHSTAT - Interrupt status for RX Channel 1 masked by the C0RXTHRESHEN register */
208#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH1THRESHSTAT BSP_BIT32(1)
209
210/* field: RXCH0THRESHSTAT - Interrupt status for RX Channel 0 masked by the C0RXTHRESHEN register */
211#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH0THRESHSTAT BSP_BIT32(0)
212
213
214/*-------------------TMS570_EMACC_C0RXSTAT-------------------*/
215/* field: RXCH7STAT - RXCH7STAT */
216#define TMS570_EMACC_C0RXSTAT_RXCH7STAT BSP_BIT32(7)
217
218/* field: RXCH6STAT - Interrupt status for RX Channel 6 masked by the C0RXEN register */
219#define TMS570_EMACC_C0RXSTAT_RXCH6STAT BSP_BIT32(6)
220
221/* field: RXCH5STAT - Interrupt status for RX Channel 5 masked by the C0RXEN register */
222#define TMS570_EMACC_C0RXSTAT_RXCH5STAT BSP_BIT32(5)
223
224/* field: RXCH4STAT - Interrupt status for RX Channel 4 masked by the C0RXEN register */
225#define TMS570_EMACC_C0RXSTAT_RXCH4STAT BSP_BIT32(4)
226
227/* field: RXCH3STAT - Interrupt status for RX Channel 3 masked by the C0RXEN register */
228#define TMS570_EMACC_C0RXSTAT_RXCH3STAT BSP_BIT32(3)
229
230/* field: RXCH2STAT - H2STAT Interrupt status for RX Channel 2 masked by the C0RXEN register */
231#define TMS570_EMACC_C0RXSTAT_RXCH2STAT BSP_BIT32(2)
232
233/* field: RXCH1STAT - Interrupt status for RX Channel 1 masked by the C0RXEN register */
234#define TMS570_EMACC_C0RXSTAT_RXCH1STAT BSP_BIT32(1)
235
236/* field: RXCH0STAT - Interrupt status for RX Channel 0 masked by the C0RXEN register */
237#define TMS570_EMACC_C0RXSTAT_RXCH0STAT BSP_BIT32(0)
238
239
240/*-------------------TMS570_EMACC_C0TXSTAT-------------------*/
241/* field: TXCH7STAT - Interrupt status for TX Channel 7 masked by the C0TXEN register */
242#define TMS570_EMACC_C0TXSTAT_TXCH7STAT BSP_BIT32(7)
243
244/* field: TXCH6STAT - TXCH6STAT */
245#define TMS570_EMACC_C0TXSTAT_TXCH6STAT BSP_BIT32(6)
246
247/* field: TXCH5STAT - Interrupt status for TX Channel 5 masked by the C0TXEN register */
248#define TMS570_EMACC_C0TXSTAT_TXCH5STAT BSP_BIT32(5)
249
250/* field: TXCH4STAT - Interrupt status for TX Channel 4 masked by the C0TXEN register */
251#define TMS570_EMACC_C0TXSTAT_TXCH4STAT BSP_BIT32(4)
252
253/* field: TXCH3STAT - Interrupt status for TX Channel 3 masked by the C0TXEN register */
254#define TMS570_EMACC_C0TXSTAT_TXCH3STAT BSP_BIT32(3)
255
256/* field: TXCH2STAT - Interrupt status for TX Channel 2 masked by the C0TXEN register */
257#define TMS570_EMACC_C0TXSTAT_TXCH2STAT BSP_BIT32(2)
258
259/* field: TXCH1STAT - Interrupt status for TX Channel 1 masked by the C0TXEN register */
260#define TMS570_EMACC_C0TXSTAT_TXCH1STAT BSP_BIT32(1)
261
262/* field: TXCH0STAT - Interrupt status for TX Channel 0 masked by the C0TXEN register */
263#define TMS570_EMACC_C0TXSTAT_TXCH0STAT BSP_BIT32(0)
264
265
266/*------------------TMS570_EMACC_C0MISCSTAT------------------*/
267/* field: STATPENDSTAT - Interrupt status for EMAC STATPEND masked by the C0MISCEN register */
268#define TMS570_EMACC_C0MISCSTAT_STATPENDSTAT BSP_BIT32(3)
269
270/* field: HOSTPENDSTAT - Interrupt status for EMAC HOSTPEND masked by the C0MISCEN register */
271#define TMS570_EMACC_C0MISCSTAT_HOSTPENDSTAT BSP_BIT32(2)
272
273/* field: LINKINT0STAT - Interrupt status for MDIO LINKINT0 masked by the C0MISCEN register */
274#define TMS570_EMACC_C0MISCSTAT_LINKINT0STAT BSP_BIT32(1)
275
276/* field: USERINT0STAT - Interrupt status for MDIO USERINT0 masked by the C0MISCEN register */
277#define TMS570_EMACC_C0MISCSTAT_USERINT0STAT BSP_BIT32(0)
278
279
280/*-------------------TMS570_EMACC_C0RXIMAX-------------------*/
281/* field: RXIMAX - RXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond when */
282#define TMS570_EMACC_C0RXIMAX_RXIMAX(val) BSP_FLD32(val,0, 5)
283#define TMS570_EMACC_C0RXIMAX_RXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5)
284#define TMS570_EMACC_C0RXIMAX_RXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
285
286
287/*-------------------TMS570_EMACC_C0TXIMAX-------------------*/
288/* field: TXIMAX - TXIMAX is the desired number of C0TXPULSE interrupts generated per millisecond when */
289#define TMS570_EMACC_C0TXIMAX_TXIMAX(val) BSP_FLD32(val,0, 5)
290#define TMS570_EMACC_C0TXIMAX_TXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5)
291#define TMS570_EMACC_C0TXIMAX_TXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
292
293
294
295#endif /* LIBBSP_ARM_TMS570_EMACC */
utility.h
This header file provides utility macros for BSPs.
tms570_emacc_t
Definition: reg_emacc.h:54
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