RTEMS 6.1-rc4
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reg_dma.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/* The header file is generated by make_header.py from DMA.json */
12/* Current script's version can be found at: */
13/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
14
15/*
16 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
17 *
18 * Czech Technical University in Prague
19 * Zikova 1903/4
20 * 166 36 Praha 6
21 * Czech Republic
22 *
23 * All rights reserved.
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following disclaimer in the documentation
32 * and/or other materials provided with the distribution.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
38 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
40 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
41 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
43 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * The views and conclusions contained in the software and documentation are those
46 * of the authors and should not be interpreted as representing official policies,
47 * either expressed or implied, of the FreeBSD Project.
48*/
49#ifndef LIBBSP_ARM_TMS570_DMA
50#define LIBBSP_ARM_TMS570_DMA
51
52#include <bsp/utility.h>
53
54typedef struct{
55 uint32_t STARTADD; /*DMA Memory Protection Region start Address Register*/
56 uint32_t ENDADD; /*DMA Memory Protection Region End Address Register*/
57} tms570_memory_prot_t;
58
59typedef struct{
60 uint32_t GCTRL; /*Global Control Register*/
61 uint32_t PEND; /*Channel Pending Register*/
62 uint8_t reserved1 [4];
63 uint32_t DMASTAT; /*DMA Status Register*/
64 uint8_t reserved2 [4];
65 uint32_t HWCHENAS; /*HW Channel Enable Set and Status Register*/
66 uint8_t reserved3 [4];
67 uint32_t HWCHENAR; /*HW Channel Enable Reset and Status Register*/
68 uint8_t reserved4 [4];
69 uint32_t SWCHENAS; /*SW Channel Enable Set and Status Register*/
70 uint8_t reserved5 [4];
71 uint32_t SWCHENAR; /*SW Channel Enable Reset and Status Register*/
72 uint8_t reserved6 [4];
73 uint32_t CHPRIOS; /*Channel Priority Set Register*/
74 uint8_t reserved7 [4];
75 uint32_t CHPRIOR; /*Channel Priority Reset Register*/
76 uint8_t reserved8 [4];
77 uint32_t GCHIENAS; /*Global Channel Interrupt Enable Set Register*/
78 uint8_t reserved9 [4];
79 uint32_t GCHIENAR; /*Global Channel Interrupt Enable Reset Register*/
80 uint8_t reserved10 [4];
81 uint32_t DREQASI[4]; /*DMA Request Assignment Register 0*/
82 uint8_t reserved11 [48];
83 uint32_t PAR0; /*Port Assignment Register 0*/
84 uint32_t PAR1; /*Port Assignment Register 1*/
85 uint8_t reserved12 [24];
86 uint32_t FTCMAP; /*FTC Interrupt Mapping Register*/
87 uint8_t reserved13 [4];
88 uint32_t LFSMAP; /*LFS Interrupt Mapping Register*/
89 uint8_t reserved14 [4];
90 uint32_t HBCMAP; /*HBC Interrupt Mapping Register*/
91 uint8_t reserved15 [4];
92 uint32_t BTCMAP; /*BTC Interrupt Mapping Register*/
93 uint8_t reserved16 [4];
94 uint32_t BERMAP; /*BER Interrupt Mapping Register*/
95 uint8_t reserved17 [4];
96 uint32_t FTCINTENAS; /*FTC Interrupt Enable Set*/
97 uint8_t reserved18 [4];
98 uint32_t FTCINTENAR; /*FTC Interrupt Enable Reset*/
99 uint8_t reserved19 [4];
100 uint32_t LFSINTENAS; /*LFS Interrupt Enable Set*/
101 uint8_t reserved20 [4];
102 uint32_t LFSINTENAR; /*LFS Interrupt Enable Reset*/
103 uint8_t reserved21 [4];
104 uint32_t HBCINTENAS; /*HBC Interrupt Enable Set*/
105 uint8_t reserved22 [4];
106 uint32_t HBCINTENAR; /*HBC Interrupt Enable Reset*/
107 uint8_t reserved23 [4];
108 uint32_t BTCINTENAS; /*BTC Interrupt Enable Set*/
109 uint8_t reserved24 [4];
110 uint32_t BTCINTENAR; /*BTC Interrupt Enable Reset*/
111 uint8_t reserved25 [4];
112 uint32_t GINTFLAG; /*Global Interrupt Flag Register*/
113 uint8_t reserved26 [4];
114 uint32_t FTCFLAG; /*FTC Interrupt Flag Register*/
115 uint8_t reserved27 [4];
116 uint32_t LFSFLAG; /*LFS Interrupt Flag Register*/
117 uint8_t reserved28 [4];
118 uint32_t HBCFLAG; /*HBC Interrupt Flag Register*/
119 uint8_t reserved29 [4];
120 uint32_t BTCFLAG; /*BTC Interrupt Flag Register*/
121 uint8_t reserved30 [4];
122 uint32_t BERFLAG; /*BER Interrupt Flag Register*/
123 uint8_t reserved31 [4];
124 uint32_t FTCAOFFSET; /*FTCA Interrupt Channel Offset Register*/
125 uint32_t LFSAOFFSET; /*LFSA Interrupt Channel Offset Register*/
126 uint32_t HBCAOFFSET; /*HBCA Interrupt Channel Offset Register*/
127 uint32_t BTCAOFFSET; /*BTCA Interrupt Channel Offset Register*/
128 uint32_t BERAOFFSET; /*BERA Interrupt Channel Offset Register*/
129 uint32_t FTCBOFFSET; /*FTCB Interrupt Channel Offset Register*/
130 uint32_t LFSBOFFSET; /*LFSB Interrupt Channel Offset Register*/
131 uint32_t HBCBOFFSET; /*HBCB Interrupt Channel Offset Register*/
132 uint32_t BTCBOFFSET; /*BTCB Interrupt Channel Offset Register*/
133 uint32_t BERBOFFSET; /*BERB Interrupt Channel Offset Register*/
134 uint8_t reserved32 [4];
135 uint32_t PTCRL; /*Port Control Register*/
136 uint32_t RTCTRL; /*RAM Test Control Register*/
137 uint32_t DCTRL; /*Debug Control*/
138 uint32_t WPR; /*Watch Point Register*/
139 uint32_t WMR; /*Watch Mask Register*/
140 uint8_t reserved33 [12];
141 uint32_t PBACSADDR; /*Port B Active Channel Source Address Register*/
142 uint32_t PBACDADDR; /*Port B Active Channel Destination Address Register*/
143 uint32_t PBACTC; /*Port B Active Channel Transfer Count Register*/
144 uint8_t reserved34 [4];
145 uint32_t DMAPCR; /*Parity Control Register*/
146 uint32_t DMAPAR; /*DMA Parity Error Address Register*/
147 uint32_t DMAMPCTRL; /*DMA Memory Protection Control Register*/
148 uint32_t DMAMPST; /*DMA Memory Protection Status Register*/
149 tms570_memory_prot_t DMAMPROS[4];/*DMA Memory Protection Regions*/
150} tms570_dma_t;
151
152
153/*--------------------TMS570_DMA_STARTADD--------------------*/
154/* field: STARTADDRESS - Start Address defines the address at which the region begins. */
155/* Whole 32 bits */
156
157/*---------------------TMS570_DMA_ENDADD---------------------*/
158/* field: ENDADDRESS - End Address defines the address at which the region ends. */
159/* Whole 32 bits */
160
161/*----------------------TMS570_DMA_GCTRL----------------------*/
162/* field: DMA_EN - DMA enable bit. */
163#define TMS570_DMA_GCTRL_DMA_EN BSP_BIT32(16)
164
165/* field: BUS_BUSY - This bit indicates status of DMA external AHB bus status. */
166#define TMS570_DMA_GCTRL_BUS_BUSY BSP_BIT32(14)
167
168/* field: DEBUG_MODE - Debug Mode. */
169#define TMS570_DMA_GCTRL_DEBUG_MODE(val) BSP_FLD32(val,8, 9)
170#define TMS570_DMA_GCTRL_DEBUG_MODE_GET(reg) BSP_FLD32GET(reg,8, 9)
171#define TMS570_DMA_GCTRL_DEBUG_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
172
173/* field: DMA_RES - DMA software reset */
174#define TMS570_DMA_GCTRL_DMA_RES BSP_BIT32(0)
175
176
177/*----------------------TMS570_DMA_PEND----------------------*/
178/* field: PEND - Channel pending register. */
179#define TMS570_DMA_PEND_PEND(val) BSP_FLD32(val,0, 15)
180#define TMS570_DMA_PEND_PEND_GET(reg) BSP_FLD32GET(reg,0, 15)
181#define TMS570_DMA_PEND_PEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
182
183
184/*---------------------TMS570_DMA_DMASTAT---------------------*/
185/* field: STCH - Status of DMA channels. */
186#define TMS570_DMA_DMASTAT_STCH(val) BSP_FLD32(val,0, 15)
187#define TMS570_DMA_DMASTAT_STCH_GET(reg) BSP_FLD32GET(reg,0, 15)
188#define TMS570_DMA_DMASTAT_STCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
189
190
191/*--------------------TMS570_DMA_HWCHENAS--------------------*/
192/* field: HWCHENA - Hardware channel enable bit. */
193#define TMS570_DMA_HWCHENAS_HWCHENA(val) BSP_FLD32(val,0, 15)
194#define TMS570_DMA_HWCHENAS_HWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
195#define TMS570_DMA_HWCHENAS_HWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
196
197
198/*--------------------TMS570_DMA_HWCHENAR--------------------*/
199/* field: HWCHDIS - HW channel disable bit. */
200#define TMS570_DMA_HWCHENAR_HWCHDIS(val) BSP_FLD32(val,0, 15)
201#define TMS570_DMA_HWCHENAR_HWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
202#define TMS570_DMA_HWCHENAR_HWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
203
204
205/*--------------------TMS570_DMA_SWCHENAS--------------------*/
206/* field: SWCHENA - SW channel enable bit. */
207#define TMS570_DMA_SWCHENAS_SWCHENA(val) BSP_FLD32(val,0, 15)
208#define TMS570_DMA_SWCHENAS_SWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
209#define TMS570_DMA_SWCHENAS_SWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
210
211
212/*--------------------TMS570_DMA_SWCHENAR--------------------*/
213/* field: SWCHDIS - SW channel disable bit. */
214#define TMS570_DMA_SWCHENAR_SWCHDIS(val) BSP_FLD32(val,0, 15)
215#define TMS570_DMA_SWCHENAR_SWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
216#define TMS570_DMA_SWCHENAR_SWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
217
218
219/*---------------------TMS570_DMA_CHPRIOS---------------------*/
220/* field: CPS - Channel priority set bit. */
221#define TMS570_DMA_CHPRIOS_CPS(val) BSP_FLD32(val,0, 15)
222#define TMS570_DMA_CHPRIOS_CPS_GET(reg) BSP_FLD32GET(reg,0, 15)
223#define TMS570_DMA_CHPRIOS_CPS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
224
225
226/*---------------------TMS570_DMA_CHPRIOR---------------------*/
227/* field: CPR - Channel priority reset bit. */
228#define TMS570_DMA_CHPRIOR_CPR(val) BSP_FLD32(val,0, 15)
229#define TMS570_DMA_CHPRIOR_CPR_GET(reg) BSP_FLD32GET(reg,0, 15)
230#define TMS570_DMA_CHPRIOR_CPR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
231
232
233/*--------------------TMS570_DMA_GCHIENAS--------------------*/
234/* field: GCHIE - Global channel interrupt enable bit. */
235#define TMS570_DMA_GCHIENAS_GCHIE(val) BSP_FLD32(val,0, 15)
236#define TMS570_DMA_GCHIENAS_GCHIE_GET(reg) BSP_FLD32GET(reg,0, 15)
237#define TMS570_DMA_GCHIENAS_GCHIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
238
239
240/*--------------------TMS570_DMA_GCHIENAR--------------------*/
241/* field: GCHID - Global channel interrupt disable bit. */
242#define TMS570_DMA_GCHIENAR_GCHID(val) BSP_FLD32(val,0, 15)
243#define TMS570_DMA_GCHIENAR_GCHID_GET(reg) BSP_FLD32GET(reg,0, 15)
244#define TMS570_DMA_GCHIENAR_GCHID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
245
246
247/*---------------------TMS570_DMA_DREQASI---------------------*/
248/* field: CH0ASI - Channel 0 assignment. This bit field chooses the DMA request assignment for channel 0. */
249#define TMS570_DMA_DREQASI_CH0ASI(val) BSP_FLD32(val,24, 29)
250#define TMS570_DMA_DREQASI_CH0ASI_GET(reg) BSP_FLD32GET(reg,24, 29)
251#define TMS570_DMA_DREQASI_CH0ASI_SET(reg,val) BSP_FLD32SET(reg, val,24, 29)
252
253/* field: CH1ASI - Channel 1 assignment. This bit field chooses the DMA request assignment for channel 1. */
254#define TMS570_DMA_DREQASI_CH1ASI(val) BSP_FLD32(val,16, 21)
255#define TMS570_DMA_DREQASI_CH1ASI_GET(reg) BSP_FLD32GET(reg,16, 21)
256#define TMS570_DMA_DREQASI_CH1ASI_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
257
258/* field: CH2ASI - Channel 2 assignment. This bit field chooses the DMA request assignment for channel 2. */
259#define TMS570_DMA_DREQASI_CH2ASI(val) BSP_FLD32(val,8, 13)
260#define TMS570_DMA_DREQASI_CH2ASI_GET(reg) BSP_FLD32GET(reg,8, 13)
261#define TMS570_DMA_DREQASI_CH2ASI_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
262
263/* field: CH3ASI - Channel 3 assignment. This bit field chooses the DMA request assignment for channel 3. */
264#define TMS570_DMA_DREQASI_CH3ASI(val) BSP_FLD32(val,0, 5)
265#define TMS570_DMA_DREQASI_CH3ASI_GET(reg) BSP_FLD32GET(reg,0, 5)
266#define TMS570_DMA_DREQASI_CH3ASI_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
267
268
269/*----------------------TMS570_DMA_PAR0----------------------*/
270/* field: CH0PA - These bit fields determine to which port channel 0 is assigned. */
271#define TMS570_DMA_PAR0_CH0PA(val) BSP_FLD32(val,28, 30)
272#define TMS570_DMA_PAR0_CH0PA_GET(reg) BSP_FLD32GET(reg,28, 30)
273#define TMS570_DMA_PAR0_CH0PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30)
274
275/* field: CH1PA - These bit fields determine to which port channel 1 is assigned. */
276#define TMS570_DMA_PAR0_CH1PA(val) BSP_FLD32(val,24, 26)
277#define TMS570_DMA_PAR0_CH1PA_GET(reg) BSP_FLD32GET(reg,24, 26)
278#define TMS570_DMA_PAR0_CH1PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
279
280/* field: CH2PA - These bit fields determine to which port channel 2 is assigned. */
281#define TMS570_DMA_PAR0_CH2PA(val) BSP_FLD32(val,20, 22)
282#define TMS570_DMA_PAR0_CH2PA_GET(reg) BSP_FLD32GET(reg,20, 22)
283#define TMS570_DMA_PAR0_CH2PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
284
285/* field: CH3PA - These bit fields determine to which port channel 3 is assigned. */
286#define TMS570_DMA_PAR0_CH3PA(val) BSP_FLD32(val,16, 18)
287#define TMS570_DMA_PAR0_CH3PA_GET(reg) BSP_FLD32GET(reg,16, 18)
288#define TMS570_DMA_PAR0_CH3PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
289
290/* field: CH4PA - These bit fields determine to which port channel 4 is assigned. */
291#define TMS570_DMA_PAR0_CH4PA(val) BSP_FLD32(val,12, 14)
292#define TMS570_DMA_PAR0_CH4PA_GET(reg) BSP_FLD32GET(reg,12, 14)
293#define TMS570_DMA_PAR0_CH4PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
294
295/* field: CH5PA - These bit fields determine to which port channel 5 is assigned. */
296#define TMS570_DMA_PAR0_CH5PA(val) BSP_FLD32(val,8, 10)
297#define TMS570_DMA_PAR0_CH5PA_GET(reg) BSP_FLD32GET(reg,8, 10)
298#define TMS570_DMA_PAR0_CH5PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
299
300/* field: CH6PA - These bit fields determine to which port channel 6 is assigned. */
301#define TMS570_DMA_PAR0_CH6PA(val) BSP_FLD32(val,4, 6)
302#define TMS570_DMA_PAR0_CH6PA_GET(reg) BSP_FLD32GET(reg,4, 6)
303#define TMS570_DMA_PAR0_CH6PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
304
305/* field: CH7PA - These bit fields determine to which port channel 7 is assigned. */
306#define TMS570_DMA_PAR0_CH7PA(val) BSP_FLD32(val,0, 2)
307#define TMS570_DMA_PAR0_CH7PA_GET(reg) BSP_FLD32GET(reg,0, 2)
308#define TMS570_DMA_PAR0_CH7PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
309
310
311/*----------------------TMS570_DMA_PAR1----------------------*/
312/* field: CH8PA - These bit fields determine to which port channel 8 is assigned. */
313#define TMS570_DMA_PAR1_CH8PA(val) BSP_FLD32(val,28, 30)
314#define TMS570_DMA_PAR1_CH8PA_GET(reg) BSP_FLD32GET(reg,28, 30)
315#define TMS570_DMA_PAR1_CH8PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30)
316
317/* field: CH9PA - These bit fields determine to which port channel 9 is assigned. */
318#define TMS570_DMA_PAR1_CH9PA(val) BSP_FLD32(val,24, 26)
319#define TMS570_DMA_PAR1_CH9PA_GET(reg) BSP_FLD32GET(reg,24, 26)
320#define TMS570_DMA_PAR1_CH9PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
321
322/* field: CH10PA - These bit fields determine to which port channel 10 is assigned. */
323#define TMS570_DMA_PAR1_CH10PA(val) BSP_FLD32(val,20, 22)
324#define TMS570_DMA_PAR1_CH10PA_GET(reg) BSP_FLD32GET(reg,20, 22)
325#define TMS570_DMA_PAR1_CH10PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
326
327/* field: CH11PA - These bit fields determine to which port channel 11 is assigned. */
328#define TMS570_DMA_PAR1_CH11PA(val) BSP_FLD32(val,16, 18)
329#define TMS570_DMA_PAR1_CH11PA_GET(reg) BSP_FLD32GET(reg,16, 18)
330#define TMS570_DMA_PAR1_CH11PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
331
332/* field: CH12PA - These bit fields determine to which port channel 12 is assigned. */
333#define TMS570_DMA_PAR1_CH12PA(val) BSP_FLD32(val,12, 14)
334#define TMS570_DMA_PAR1_CH12PA_GET(reg) BSP_FLD32GET(reg,12, 14)
335#define TMS570_DMA_PAR1_CH12PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
336
337/* field: CH13PA - These bit fields determine to which port channel 13 is assigned. */
338#define TMS570_DMA_PAR1_CH13PA(val) BSP_FLD32(val,8, 10)
339#define TMS570_DMA_PAR1_CH13PA_GET(reg) BSP_FLD32GET(reg,8, 10)
340#define TMS570_DMA_PAR1_CH13PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
341
342/* field: CH14PA - These bit fields determine to which port channel 14 is assigned. */
343#define TMS570_DMA_PAR1_CH14PA(val) BSP_FLD32(val,4, 6)
344#define TMS570_DMA_PAR1_CH14PA_GET(reg) BSP_FLD32GET(reg,4, 6)
345#define TMS570_DMA_PAR1_CH14PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
346
347/* field: CH15PA - These bit fields determine to which port channel 15 is assigned. */
348#define TMS570_DMA_PAR1_CH15PA(val) BSP_FLD32(val,0, 2)
349#define TMS570_DMA_PAR1_CH15PA_GET(reg) BSP_FLD32GET(reg,0, 2)
350#define TMS570_DMA_PAR1_CH15PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
351
352
353/*---------------------TMS570_DMA_FTCMAP---------------------*/
354/* field: FTCAB - Frame transfer complete (FTC) interrupt to Group A or Group B. */
355#define TMS570_DMA_FTCMAP_FTCAB(val) BSP_FLD32(val,0, 15)
356#define TMS570_DMA_FTCMAP_FTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
357#define TMS570_DMA_FTCMAP_FTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
358
359
360/*---------------------TMS570_DMA_LFSMAP---------------------*/
361/* field: LFSAB - Last frame started (LFS) interrupt to Group A or Group B. */
362#define TMS570_DMA_LFSMAP_LFSAB(val) BSP_FLD32(val,0, 15)
363#define TMS570_DMA_LFSMAP_LFSAB_GET(reg) BSP_FLD32GET(reg,0, 15)
364#define TMS570_DMA_LFSMAP_LFSAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
365
366
367/*---------------------TMS570_DMA_HBCMAP---------------------*/
368/* field: HBCAB - Half block complete (HBC) interrupt to Group A or Group B. */
369#define TMS570_DMA_HBCMAP_HBCAB(val) BSP_FLD32(val,0, 15)
370#define TMS570_DMA_HBCMAP_HBCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
371#define TMS570_DMA_HBCMAP_HBCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
372
373
374/*---------------------TMS570_DMA_BTCMAP---------------------*/
375/* field: BTCAB - Block transfer complete (BTC) interrupt to Group A or Group B */
376#define TMS570_DMA_BTCMAP_BTCAB(val) BSP_FLD32(val,0, 15)
377#define TMS570_DMA_BTCMAP_BTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
378#define TMS570_DMA_BTCMAP_BTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
379
380
381/*---------------------TMS570_DMA_BERMAP---------------------*/
382/* field: BERAB - Bus error (BER) interrupt to Group A or Group B. */
383#define TMS570_DMA_BERMAP_BERAB(val) BSP_FLD32(val,0, 15)
384#define TMS570_DMA_BERMAP_BERAB_GET(reg) BSP_FLD32GET(reg,0, 15)
385#define TMS570_DMA_BERMAP_BERAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
386
387
388/*-------------------TMS570_DMA_FTCINTENAS-------------------*/
389/* field: FTCINTENA - Frame transfer complete (FTC) interrupt enable. */
390#define TMS570_DMA_FTCINTENAS_FTCINTENA(val) BSP_FLD32(val,0, 15)
391#define TMS570_DMA_FTCINTENAS_FTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
392#define TMS570_DMA_FTCINTENAS_FTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
393
394
395/*-------------------TMS570_DMA_FTCINTENAR-------------------*/
396/* field: FTCINTDIS - Frame transfer complete (FTC) interrupt disable. */
397#define TMS570_DMA_FTCINTENAR_FTCINTDIS(val) BSP_FLD32(val,0, 15)
398#define TMS570_DMA_FTCINTENAR_FTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
399#define TMS570_DMA_FTCINTENAR_FTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
400
401
402/*-------------------TMS570_DMA_LFSINTENAS-------------------*/
403/* field: LFSINTENA - Last frame started (LFS) interrupt enable. */
404#define TMS570_DMA_LFSINTENAS_LFSINTENA(val) BSP_FLD32(val,0, 15)
405#define TMS570_DMA_LFSINTENAS_LFSINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
406#define TMS570_DMA_LFSINTENAS_LFSINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
407
408
409/*-------------------TMS570_DMA_LFSINTENAR-------------------*/
410/* field: LFSINTDIS - Last frame started (LFS) interrupt disable. */
411#define TMS570_DMA_LFSINTENAR_LFSINTDIS(val) BSP_FLD32(val,0, 15)
412#define TMS570_DMA_LFSINTENAR_LFSINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
413#define TMS570_DMA_LFSINTENAR_LFSINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
414
415
416/*-------------------TMS570_DMA_HBCINTENAS-------------------*/
417/* field: HBCINTENA - Half block complete (HBC) interrupt enable. */
418#define TMS570_DMA_HBCINTENAS_HBCINTENA(val) BSP_FLD32(val,0, 15)
419#define TMS570_DMA_HBCINTENAS_HBCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
420#define TMS570_DMA_HBCINTENAS_HBCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
421
422
423/*-------------------TMS570_DMA_HBCINTENAR-------------------*/
424/* field: HBCINTDIS - Half block complete (HBC) interrupt disable. */
425#define TMS570_DMA_HBCINTENAR_HBCINTDIS(val) BSP_FLD32(val,0, 15)
426#define TMS570_DMA_HBCINTENAR_HBCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
427#define TMS570_DMA_HBCINTENAR_HBCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
428
429
430/*-------------------TMS570_DMA_BTCINTENAS-------------------*/
431/* field: BTCINTENA - Block transfer complete (BTC) interrupt enable. */
432#define TMS570_DMA_BTCINTENAS_BTCINTENA(val) BSP_FLD32(val,0, 15)
433#define TMS570_DMA_BTCINTENAS_BTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
434#define TMS570_DMA_BTCINTENAS_BTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
435
436
437/*-------------------TMS570_DMA_BTCINTENAR-------------------*/
438/* field: BTCINTDIS - Block transfer complete (BTC) interurpt disable. */
439#define TMS570_DMA_BTCINTENAR_BTCINTDIS(val) BSP_FLD32(val,0, 15)
440#define TMS570_DMA_BTCINTENAR_BTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
441#define TMS570_DMA_BTCINTENAR_BTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
442
443
444/*--------------------TMS570_DMA_GINTFLAG--------------------*/
445/* field: GINT - Global interrupt flags. */
446#define TMS570_DMA_GINTFLAG_GINT(val) BSP_FLD32(val,0, 15)
447#define TMS570_DMA_GINTFLAG_GINT_GET(reg) BSP_FLD32GET(reg,0, 15)
448#define TMS570_DMA_GINTFLAG_GINT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
449
450
451/*---------------------TMS570_DMA_FTCFLAG---------------------*/
452/* field: FTCI - Frame transfer complete (FTC) flags. */
453#define TMS570_DMA_FTCFLAG_FTCI(val) BSP_FLD32(val,0, 15)
454#define TMS570_DMA_FTCFLAG_FTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
455#define TMS570_DMA_FTCFLAG_FTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
456
457
458/*---------------------TMS570_DMA_LFSFLAG---------------------*/
459/* field: LFSI - Last frame started (LFS) flags. */
460#define TMS570_DMA_LFSFLAG_LFSI(val) BSP_FLD32(val,0, 15)
461#define TMS570_DMA_LFSFLAG_LFSI_GET(reg) BSP_FLD32GET(reg,0, 15)
462#define TMS570_DMA_LFSFLAG_LFSI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
463
464
465/*---------------------TMS570_DMA_HBCFLAG---------------------*/
466/* field: HBCI - Half block transfer (HBC) complete flags. */
467#define TMS570_DMA_HBCFLAG_HBCI(val) BSP_FLD32(val,0, 15)
468#define TMS570_DMA_HBCFLAG_HBCI_GET(reg) BSP_FLD32GET(reg,0, 15)
469#define TMS570_DMA_HBCFLAG_HBCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
470
471
472/*---------------------TMS570_DMA_BTCFLAG---------------------*/
473/* field: BTCI - Block transfer complete (BTC) flags. */
474#define TMS570_DMA_BTCFLAG_BTCI(val) BSP_FLD32(val,0, 15)
475#define TMS570_DMA_BTCFLAG_BTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
476#define TMS570_DMA_BTCFLAG_BTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
477
478
479/*---------------------TMS570_DMA_BERFLAG---------------------*/
480/* field: BERI - Bus error (BER) flags. */
481#define TMS570_DMA_BERFLAG_BERI(val) BSP_FLD32(val,0, 15)
482#define TMS570_DMA_BERFLAG_BERI_GET(reg) BSP_FLD32GET(reg,0, 15)
483#define TMS570_DMA_BERFLAG_BERI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
484
485
486/*-------------------TMS570_DMA_FTCAOFFSET-------------------*/
487/* field: sbz - These bits should always be programmed as zero. */
488#define TMS570_DMA_FTCAOFFSET_sbz(val) BSP_FLD32(val,6, 7)
489#define TMS570_DMA_FTCAOFFSET_sbz_GET(reg) BSP_FLD32GET(reg,6, 7)
490#define TMS570_DMA_FTCAOFFSET_sbz_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
491
492/* field: FTCA - Channel causing FTC interrupt Group A. */
493#define TMS570_DMA_FTCAOFFSET_FTCA(val) BSP_FLD32(val,0, 5)
494#define TMS570_DMA_FTCAOFFSET_FTCA_GET(reg) BSP_FLD32GET(reg,0, 5)
495#define TMS570_DMA_FTCAOFFSET_FTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
496
497
498/*-------------------TMS570_DMA_LFSAOFFSET-------------------*/
499/* field: LFSA - Channel causing LFS interrupt Group A. */
500#define TMS570_DMA_LFSAOFFSET_LFSA(val) BSP_FLD32(val,0, 5)
501#define TMS570_DMA_LFSAOFFSET_LFSA_GET(reg) BSP_FLD32GET(reg,0, 5)
502#define TMS570_DMA_LFSAOFFSET_LFSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
503
504
505/*-------------------TMS570_DMA_HBCAOFFSET-------------------*/
506/* field: HBCA - Channel causing HBC interrupt Group A. */
507#define TMS570_DMA_HBCAOFFSET_HBCA(val) BSP_FLD32(val,0, 5)
508#define TMS570_DMA_HBCAOFFSET_HBCA_GET(reg) BSP_FLD32GET(reg,0, 5)
509#define TMS570_DMA_HBCAOFFSET_HBCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
510
511
512/*-------------------TMS570_DMA_BTCAOFFSET-------------------*/
513/* field: BTCA - Channel causing BTC interrupt Group A. */
514#define TMS570_DMA_BTCAOFFSET_BTCA(val) BSP_FLD32(val,0, 5)
515#define TMS570_DMA_BTCAOFFSET_BTCA_GET(reg) BSP_FLD32GET(reg,0, 5)
516#define TMS570_DMA_BTCAOFFSET_BTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
517
518
519/*-------------------TMS570_DMA_BERAOFFSET-------------------*/
520/* field: BERA - Channel causing BER interrupt Group A. */
521#define TMS570_DMA_BERAOFFSET_BERA(val) BSP_FLD32(val,0, 5)
522#define TMS570_DMA_BERAOFFSET_BERA_GET(reg) BSP_FLD32GET(reg,0, 5)
523#define TMS570_DMA_BERAOFFSET_BERA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
524
525
526/*-------------------TMS570_DMA_FTCBOFFSET-------------------*/
527/* field: FTCB - Channel causing FTC interrupt Group B. */
528#define TMS570_DMA_FTCBOFFSET_FTCB(val) BSP_FLD32(val,0, 5)
529#define TMS570_DMA_FTCBOFFSET_FTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
530#define TMS570_DMA_FTCBOFFSET_FTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
531
532
533/*-------------------TMS570_DMA_LFSBOFFSET-------------------*/
534/* field: LFSB - Channel causing LFS interrupt Group B. */
535#define TMS570_DMA_LFSBOFFSET_LFSB(val) BSP_FLD32(val,0, 5)
536#define TMS570_DMA_LFSBOFFSET_LFSB_GET(reg) BSP_FLD32GET(reg,0, 5)
537#define TMS570_DMA_LFSBOFFSET_LFSB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
538
539
540/*-------------------TMS570_DMA_HBCBOFFSET-------------------*/
541/* field: HBCB - Channel causing HBC interrupt Group B. */
542#define TMS570_DMA_HBCBOFFSET_HBCB(val) BSP_FLD32(val,0, 5)
543#define TMS570_DMA_HBCBOFFSET_HBCB_GET(reg) BSP_FLD32GET(reg,0, 5)
544#define TMS570_DMA_HBCBOFFSET_HBCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
545
546
547/*-------------------TMS570_DMA_BTCBOFFSET-------------------*/
548/* field: BTCB - interrupt for Group B if the corresponding interrupt enable is set. */
549#define TMS570_DMA_BTCBOFFSET_BTCB(val) BSP_FLD32(val,0, 5)
550#define TMS570_DMA_BTCBOFFSET_BTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
551#define TMS570_DMA_BTCBOFFSET_BTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
552
553
554/*-------------------TMS570_DMA_BERBOFFSET-------------------*/
555/* field: BERB - Channel causing BER interrupt Group B. */
556#define TMS570_DMA_BERBOFFSET_BERB(val) BSP_FLD32(val,0, 5)
557#define TMS570_DMA_BERBOFFSET_BERB_GET(reg) BSP_FLD32GET(reg,0, 5)
558#define TMS570_DMA_BERBOFFSET_BERB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
559
560
561/*----------------------TMS570_DMA_PTCRL----------------------*/
562/* field: PENDB - Transfers pending for Port B. This flag determines if transfers are ongoing on port B. */
563#define TMS570_DMA_PTCRL_PENDB BSP_BIT32(24)
564
565/* field: BYB - Bypass FIFO B. */
566#define TMS570_DMA_PTCRL_BYB BSP_BIT32(18)
567
568/* field: PSFRHQPB - Priority scheme fix or rotate for high priority queue of Port B. */
569#define TMS570_DMA_PTCRL_PSFRHQPB BSP_BIT32(17)
570
571/* field: PSFRLQPB - Priority scheme fix or rotate for low priority queue of Port B. */
572#define TMS570_DMA_PTCRL_PSFRLQPB BSP_BIT32(16)
573
574
575/*---------------------TMS570_DMA_RTCTRL---------------------*/
576/* field: RTC - RAM Test Control. */
577#define TMS570_DMA_RTCTRL_RTC BSP_BIT32(0)
578
579
580/*----------------------TMS570_DMA_DCTRL----------------------*/
581/* field: CHNUM - Channel Number. */
582#define TMS570_DMA_DCTRL_CHNUM(val) BSP_FLD32(val,24, 28)
583#define TMS570_DMA_DCTRL_CHNUM_GET(reg) BSP_FLD32GET(reg,24, 28)
584#define TMS570_DMA_DCTRL_CHNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
585
586/* field: DMADBGS - DMA debug status. */
587#define TMS570_DMA_DCTRL_DMADBGS BSP_BIT32(16)
588
589/* field: DBGEN - Debug Enable. */
590#define TMS570_DMA_DCTRL_DBGEN BSP_BIT32(0)
591
592
593/*-----------------------TMS570_DMA_WPR-----------------------*/
594/* field: WP - Watch point. */
595/* Whole 32 bits */
596
597/*-----------------------TMS570_DMA_WMR-----------------------*/
598/* field: WM - Watch mask. */
599/* Whole 32 bits */
600
601/*--------------------TMS570_DMA_PBACSADDR--------------------*/
602/* field: PBACSA - Port B Active Channel Source Address. */
603/* Whole 32 bits */
604
605/*--------------------TMS570_DMA_PBACDADDR--------------------*/
606/* field: PBACDA - address of the active channel as broadcasted in Section 16.3.1.3 for Port B. */
607/* Whole 32 bits */
608
609/*---------------------TMS570_DMA_PBACTC---------------------*/
610/* field: PBFTCOUNT - Port B active channel frame count. */
611#define TMS570_DMA_PBACTC_PBFTCOUNT(val) BSP_FLD32(val,16, 28)
612#define TMS570_DMA_PBACTC_PBFTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 28)
613#define TMS570_DMA_PBACTC_PBFTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 28)
614
615/* field: PBETCOUNT - Port B active channel element count. */
616#define TMS570_DMA_PBACTC_PBETCOUNT(val) BSP_FLD32(val,0, 12)
617#define TMS570_DMA_PBACTC_PBETCOUNT_GET(reg) BSP_FLD32GET(reg,0, 12)
618#define TMS570_DMA_PBACTC_PBETCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
619
620
621/*---------------------TMS570_DMA_DMAPCR---------------------*/
622/* field: ERRA - Error action. */
623#define TMS570_DMA_DMAPCR_ERRA BSP_BIT32(16)
624
625/* field: TEST - When this bit is set, the parity bits are memory mapped to make them accessible by the CPU. */
626#define TMS570_DMA_DMAPCR_TEST BSP_BIT32(8)
627
628/* field: PARITY_ENA - Parity error detection enable. */
629#define TMS570_DMA_DMAPCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
630#define TMS570_DMA_DMAPCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
631#define TMS570_DMA_DMAPCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
632
633
634/*---------------------TMS570_DMA_DMAPAR---------------------*/
635/* field: EDFLAG - Parity Error Detection Flag. */
636#define TMS570_DMA_DMAPAR_EDFLAG BSP_BIT32(24)
637
638/* field: ERRORADDRESS - Error address. These bits hold the address of the first parity error generated in the RAM. */
639#define TMS570_DMA_DMAPAR_ERRORADDRESS(val) BSP_FLD32(val,0, 11)
640#define TMS570_DMA_DMAPAR_ERRORADDRESS_GET(reg) BSP_FLD32GET(reg,0, 11)
641#define TMS570_DMA_DMAPAR_ERRORADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
642
643
644/*--------------------TMS570_DMA_DMAMPCTRL--------------------*/
645/* field: INT3AB - Interrupt assignment of region 3 to Group A or Group B. */
646#define TMS570_DMA_DMAMPCTRL_INT3AB BSP_BIT32(28)
647
648/* field: INT3ENA - Interrupt enable of region 3. */
649#define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_BIT32(27)
650
651/* field: REG3AP - Region 3 access permission. */
652#define TMS570_DMA_DMAMPCTRL_REG3AP(val) BSP_FLD32(val,25, 26)
653#define TMS570_DMA_DMAMPCTRL_REG3AP_GET(reg) BSP_FLD32GET(reg,25, 26)
654#define TMS570_DMA_DMAMPCTRL_REG3AP_SET(reg,val) BSP_FLD32SET(reg, val,25, 26)
655
656/* field: REG3ENA - Region 3 enable. */
657#define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_BIT32(24)
658
659/* field: INT2AB - Interrupt assignment of region 2 to Group A or Group B. */
660#define TMS570_DMA_DMAMPCTRL_INT2AB BSP_BIT32(20)
661
662/* field: INT2ENA - Interrupt enable of region 2. */
663#define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_BIT32(19)
664
665/* field: REG2AP - Region 2 access permission. These bits determine the access permission for region 2. */
666#define TMS570_DMA_DMAMPCTRL_REG2AP(val) BSP_FLD32(val,17, 18)
667#define TMS570_DMA_DMAMPCTRL_REG2AP_GET(reg) BSP_FLD32GET(reg,17, 18)
668#define TMS570_DMA_DMAMPCTRL_REG2AP_SET(reg,val) BSP_FLD32SET(reg, val,17, 18)
669
670/* field: REG2ENA - Region 2 enable. */
671#define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_BIT32(16)
672
673/* field: INT1AB - Interrupt assignment of region 1 to Group A or Group B. */
674#define TMS570_DMA_DMAMPCTRL_INT1AB BSP_BIT32(12)
675
676/* field: INT1ENA - Interrupt enable of region 1. */
677#define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_BIT32(11)
678
679/* field: REG1AP - Region 1 access permission. */
680#define TMS570_DMA_DMAMPCTRL_REG1AP(val) BSP_FLD32(val,9, 10)
681#define TMS570_DMA_DMAMPCTRL_REG1AP_GET(reg) BSP_FLD32GET(reg,9, 10)
682#define TMS570_DMA_DMAMPCTRL_REG1AP_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
683
684/* field: REG1ENA - Region 1 enable. */
685#define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_BIT32(8)
686
687/* field: INT0AB - Interrupt assignment of region 0 to Group A or Group B. */
688#define TMS570_DMA_DMAMPCTRL_INT0AB BSP_BIT32(4)
689
690/* field: INT0ENA - Interrupt enable of region 0. */
691#define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_BIT32(3)
692
693/* field: REG0AP - Region 0 access permission. These bits determine the access permission for region 0. */
694#define TMS570_DMA_DMAMPCTRL_REG0AP(val) BSP_FLD32(val,1, 2)
695#define TMS570_DMA_DMAMPCTRL_REG0AP_GET(reg) BSP_FLD32GET(reg,1, 2)
696#define TMS570_DMA_DMAMPCTRL_REG0AP_SET(reg,val) BSP_FLD32SET(reg, val,1, 2)
697
698/* field: REG0ENA - Region 0 enable. */
699#define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_BIT32(0)
700
701
702/*---------------------TMS570_DMA_DMAMPST---------------------*/
703/* field: REG3FT - Region 3 fault. */
704#define TMS570_DMA_DMAMPST_REG3FT BSP_BIT32(24)
705
706/* field: REG2FT - Region 2 fault. */
707#define TMS570_DMA_DMAMPST_REG2FT BSP_BIT32(16)
708
709/* field: REG1FT - Region 1 fault. */
710#define TMS570_DMA_DMAMPST_REG1FT BSP_BIT32(8)
711
712/* field: REG0FT - Region 0 fault. */
713#define TMS570_DMA_DMAMPST_REG0FT BSP_BIT32(0)
714
715
716/*--------------------TMS570_DMA_DMAMPROS--------------------*/
717/* field: STARTADDRESS - Start Address defines the address at which the region begins. */
718/* Whole 32 bits */
719
720
721#endif /* LIBBSP_ARM_TMS570_DMA */
utility.h
This header file provides utility macros for BSPs.
tms570_dma_t
Definition: reg_dma.h:59
tms570_memory_prot_t
Definition: reg_dma.h:54
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