RTEMS
6.1-rc4
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bsps
x86_64
amd64
include
pic.h
Go to the documentation of this file.
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (c) 2018 Amaan Cheval <amaan.cheval@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _AMD64_PIC_H
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#define _AMD64_PIC_H
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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#define PIC1 0x20
/* IO base address for master PIC */
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#define PIC2 0xA0
/* IO base address for slave PIC */
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#define PIC1_COMMAND PIC1
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#define PIC1_DATA (PIC1+1)
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#define PIC2_COMMAND PIC2
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#define PIC2_DATA (PIC2+1)
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/* reinitialize the PIC controllers, giving them specified vector offsets
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rather than 8h and 70h, as configured by default */
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#define PIC_ICW1_ICW4 0x01
/* ICW4 (not) needed */
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#define PIC_ICW1_SINGLE 0x02
/* Single (cascade) mode */
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#define PIC_ICW1_INTERVAL4 0x04
/* Call address interval 4 (8) */
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#define PIC_ICW1_LEVEL 0x08
/* Level triggered (edge) mode */
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#define PIC_ICW1_INIT 0x10
/* Initialization - required! */
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#define PIC_ICW4_8086 0x01
/* 8086/88 (MCS-80/85) mode */
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#define PIC_ICW4_AUTO 0x02
/* Auto (normal) EOI */
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#define PIC_ICW4_BUF_SLAVE 0x08
/* Buffered mode/slave */
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#define PIC_ICW4_BUF_MASTER 0x0C
/* Buffered mode/master */
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#define PIC_ICW4_SFNM 0x10
/* Special fully nested (not) */
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/* This remaps IRQ0 to vector number 0x20 and so on (i.e. IDT[32]) */
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#define PIC1_REMAP_DEST 0x20
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#define PIC2_REMAP_DEST 0x28
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/* Remap PIC1's interrupts to offset1 and PIC2's to offset2 */
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void
pic_remap(uint8_t offset1, uint8_t offset2);
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void
pic_disable
(
void
);
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#ifdef __cplusplus
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}
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#endif
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#endif
/* _AMD64_PIC_H */
pic_disable
void pic_disable(void)
Definition:
pic.c:80
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