RTEMS 6.1-rc4
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mc68681_p.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 *
5 * COPYRIGHT (c) 1989-1999.
6 * On-Line Applications Research Corporation (OAR).
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef _MC68681_P_H_
31#define _MC68681_P_H_
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37/*
38 * Define MC68681_STATIC to nothing while debugging so the entry points
39 * will show up in the symbol table.
40 */
41
42#define MC68681_STATIC
43
44/* #define MC68681_STATIC static */
45
46/*
47 * mc68681 register offsets Read/Write Addresses
48 */
49
50#define MC68681_MODE_REG_1A 0 /* MR1A-MR Prior to Read */
51#define MC68681_MODE_REG_2A 0 /* MR2A-MR After Read */
52
53#define MC68681_COUNT_MODE_CURRENT_MSB 6 /* CTU */
54#define MC68681_COUNTER_TIMER_UPPER_REG 6 /* CTU */
55#define MC68681_COUNT_MODE_CURRENT_LSB 7 /* CTL */
56#define MC68681_COUNTER_TIMER_LOWER_REG 7 /* CTL */
57#define MC68681_INTERRUPT_VECTOR_REG 12 /* IVR */
58
59#define MC68681_MODE_REG_1B 8 /* MR1B-MR Prior to Read */
60#define MC68681_MODE_REG_2B 8 /* MR2BA-MR After Read */
61
62/*
63 * mc68681 register offsets Read Only Addresses
64 */
65
66#define MC68681_STATUS_REG_A 1 /* SRA */
67#define MC68681_MASK_ISR_REG 2 /* MISR */
68#define MC68681_RECEIVE_BUFFER_A 3 /* RHRA */
69#define MC68681_INPUT_PORT_CHANGE_REG 4 /* IPCR */
70#define MC68681_INTERRUPT_STATUS_REG 5 /* ISR */
71#define MC68681_STATUS_REG_B 9 /* SRB */
72#define MC68681_RECEIVE_BUFFER_B 11 /* RHRB */
73#define MC68681_INPUT_PORT 13 /* IP */
74#define MC68681_START_COUNT_CMD 14 /* SCC */
75#define MC68681_STOP_COUNT_CMD 15 /* STC */
76
77/*
78 * mc68681 register offsets Write Only Addresses
79 */
80
81#define MC68681_CLOCK_SELECT_REG_A 1 /* CSRA */
82#define MC68681_COMMAND_REG_A 2 /* CRA */
83#define MC68681_TRANSMIT_BUFFER_A 3 /* THRA */
84#define MC68681_AUX_CTRL_REG 4 /* ACR */
85#define MC68681_INTERRUPT_MASK_REG 5 /* IMR */
86#define MC68681_CLOCK_SELECT_REG_B 9 /* CSRB */
87#define MC68681_COMMAND_REG_B 10 /* CRB */
88#define MC68681_TRANSMIT_BUFFER_B 11 /* THRB */
89#define MC68681_OUTPUT_PORT_CONFIG_REG 13 /* OPCR */
90#define MC68681_OUTPUT_PORT_SET_REG 14 /* SOPBC */
91#define MC68681_OUTPUT_PORT_RESET_BITS 15 /* COPBC */
92
93/*
94 * DUART Command Register Definitions:
95 *
96 * MC68681_COMMAND_REG_A,MC68681_COMMAND_REG_B
97 */
98
99#define MC68681_MODE_REG_ENABLE_RX 0x01
100#define MC68681_MODE_REG_DISABLE_RX 0x02
101#define MC68681_MODE_REG_ENABLE_TX 0x04
102#define MC68681_MODE_REG_DISABLE_TX 0x08
103#define MC68681_MODE_REG_RESET_MR_PTR 0x10
104#define MC68681_MODE_REG_RESET_RX 0x20
105#define MC68681_MODE_REG_RESET_TX 0x30
106#define MC68681_MODE_REG_RESET_ERROR 0x40
107#define MC68681_MODE_REG_RESET_BREAK 0x50
108#define MC68681_MODE_REG_START_BREAK 0x60
109#define MC68681_MODE_REG_STOP_BREAK 0x70
110#define MC68681_MODE_REG_SET_RX_BRG 0x80
111#define MC68681_MODE_REG_CLEAR_RX_BRG 0x90
112#define MC68681_MODE_REG_SET_TX_BRG 0xa0
113#define MC68681_MODE_REG_CLEAR_TX_BRG 0xb0
114#define MC68681_MODE_REG_SET_STANDBY 0xc0
115#define MC68681_MODE_REG_SET_ACTIVE 0xd0
116
117/*
118 * Mode Register Definitions
119 *
120 * MC68681_MODE_REG_1A
121 * MC68681_MODE_REG_1B
122 */
123
124#define MC68681_5BIT_CHARS 0x00
125#define MC68681_6BIT_CHARS 0x01
126#define MC68681_7BIT_CHARS 0x02
127#define MC68681_8BIT_CHARS 0x03
128
129#define MC68681_ODD_PARITY 0x00
130#define MC68681_EVEN_PARITY 0x04
131
132#define MC68681_WITH_PARITY 0x00
133#define MC68681_FORCE_PARITY 0x08
134#define MC68681_NO_PARITY 0x10
135#define MC68681_MULTI_DROP 0x18
136
137#define MC68681_ERR_MODE_CHAR 0x00
138#define MC68681_ERR_MODE_BLOCK 0x20
139
140#define MC68681_RX_INTR_RX_READY 0x00
141#define MC68681_RX_INTR_FFULL 0x40
142
143#define MC68681_NO_RX_RTS_CTL 0x00
144#define MC68681_RX_RTS_CTRL 0x80
145
146/*
147 * Mode Register Definitions
148 *
149 * MC68681_MODE_REG_2A
150 * MC68681_MODE_REG_2B
151 */
152
153#define MC68681_STOP_BIT_LENGTH__563 0x00
154#define MC68681_STOP_BIT_LENGTH__625 0x01
155#define MC68681_STOP_BIT_LENGTH__688 0x02
156#define MC68681_STOP_BIT_LENGTH__75 0x03
157#define MC68681_STOP_BIT_LENGTH__813 0x04
158#define MC68681_STOP_BIT_LENGTH__875 0x05
159#define MC68681_STOP_BIT_LENGTH__938 0x06
160#define MC68681_STOP_BIT_LENGTH_1 0x07
161#define MC68681_STOP_BIT_LENGTH_1_563 0x08
162#define MC68681_STOP_BIT_LENGTH_1_625 0x09
163#define MC68681_STOP_BIT_LENGTH_1_688 0x0a
164#define MC68681_STOP_BIT_LENGTH_1_75 0x0b
165#define MC68681_STOP_BIT_LENGTH_1_813 0x0c
166#define MC68681_STOP_BIT_LENGTH_1_875 0x0d
167#define MC68681_STOP_BIT_LENGTH_1_938 0x0e
168#define MC68681_STOP_BIT_LENGTH_2 0x0f
169
170#define MC68681_CTS_ENABLE_TX 0x10
171#define MC68681_TX_RTS_CTRL 0x20
172
173#define MC68681_CHANNEL_MODE_NORMAL 0x00
174#define MC68681_CHANNEL_MODE_ECHO 0x40
175#define MC68681_CHANNEL_MODE_LOCAL_LOOP 0x80
176#define MC68681_CHANNEL_MODE_REMOTE_LOOP 0xc0
177
178/*
179 * Status Register Definitions
180 *
181 * MC68681_STATUS_REG_A, MC68681_STATUS_REG_B
182 */
183
184#define MC68681_RX_READY 0x01
185#define MC68681_FFULL 0x02
186#define MC68681_TX_READY 0x04
187#define MC68681_TX_EMPTY 0x08
188#define MC68681_OVERRUN_ERROR 0x10
189#define MC68681_PARITY_ERROR 0x20
190#define MC68681_FRAMING_ERROR 0x40
191#define MC68681_RECEIVED_BREAK 0x80
192
193#define MC68681_RX_ERRORS \
194 (MC68681_OVERRUN_ERROR|MC68681_PARITY_ERROR| \
195 MC68681_FRAMING_ERROR|MC68681_RECEIVED_BREAK)
196
197/*
198 * Interupt Status Register Definitions.
199 *
200 * MC68681_INTERRUPT_STATUS_REG
201 */
202
203/*
204 * Interupt Mask Register Definitions
205 *
206 * MC68681_INTERRUPT_MASK_REG
207 */
208
209/* These are passed to mc68681_build_imr */
210#define MC68681_IR_TX_READY 0x01
211#define MC68681_IR_RX_READY 0x02
212#define MC68681_IR_BREAK 0x04
213#define MC68681_IMR_ENABLE_ALL 0x07
214#define MC68681_IMR_DISABLE_ALL 0x00
215#define MC68681_IMR_ENABLE_ALL_EXCEPT_TX 0x06
216
217#define MC68681_IR_TX_READY_A 0x01
218#define MC68681_IR_RX_READY_A 0x02
219#define MC68681_IR_BREAK_A 0x04
220#define MC68681_IR_COUNTER_READY 0x08
221#define MC68681_IR_TX_READY_B 0x10
222#define MC68681_IR_RX_READY_B 0x20
223#define MC68681_IR_BREAK_B 0x40
224#define MC68681_IR_INPUT_PORT_CHANGE 0x80
225
226/*
227 * Status Register Definitions.
228 *
229 * MC68681_STATUS_REG_A,MC68681_STATUS_REG_B
230 */
231
232#define MC68681_STATUS_RXRDY 0x01
233#define MC68681_STATUS_FFULL 0x02
234#define MC68681_STATUS_TXRDY 0x04
235#define MC68681_STATUS_TXEMT 0x08
236#define MC68681_STATUS_OVERRUN_ERROR 0x10
237#define MC68681_STATUS_PARITY_ERROR 0x20
238#define MC68681_STATUS_FRAMING_ERROR 0x40
239#define MC68681_STATUS_RECEIVED_BREAK 0x80
240
241/*
242 * Definitions for the Interrupt Vector Register:
243 *
244 * MC68681_INTERRUPT_VECTOR_REG
245 */
246
247#define MC68681_INTERRUPT_VECTOR_INIT 0x0f
248
249/*
250 * Definitions for the Auxiliary Control Register
251 *
252 * MC68681_AUX_CTRL_REG
253 */
254
255#define MC68681_AUX_BRG_SET1 0x00
256#define MC68681_AUX_BRG_SET2 0x80
257
258/*
259 * Per chip context control
260 */
261
262typedef struct _mc68681_context
263{
264 int mate;
265 unsigned char imr;
267
268/*
269 * Driver functions
270 */
271MC68681_STATIC void mc68681_initialize_context(
272 int minor,
273 mc68681_context *pmc68681Context
274);
275
276MC68681_STATIC bool mc68681_probe(int minor);
277
278MC68681_STATIC int mc68681_set_attributes(
279 int minor,
280 const struct termios *t
281);
282
283MC68681_STATIC void mc68681_init(int minor);
284
285MC68681_STATIC int mc68681_open(
286 int major,
287 int minor,
288 void * arg
289);
290
291MC68681_STATIC int mc68681_close(
292 int major,
293 int minor,
294 void * arg
295);
296
297MC68681_STATIC void mc68681_write_polled(
298 int minor,
299 char cChar
300);
301
302MC68681_STATIC void mc68681_initialize_interrupts(int minor);
303
304MC68681_STATIC ssize_t mc68681_write_support_int(
305 int minor,
306 const char *buf,
307 size_t len
308);
309
310MC68681_STATIC ssize_t mc68681_write_support_polled(
311 int minor,
312 const char *buf,
313 size_t len
314 );
315
316MC68681_STATIC int mc68681_inbyte_nonblocking_polled(
317 int minor
318);
319
320MC68681_STATIC unsigned int mc68681_build_imr(
321 int minor,
322 int enable_flag
323);
324
325MC68681_STATIC void mc68681_process(
326 int minor
327);
328
329MC68681_STATIC void mc68681_enable_interrupts(
330 int minor,
331 int imr_mask
332);
333
334MC68681_STATIC rtems_isr mc68681_isr(
336);
337
338#ifdef __cplusplus
339}
340#endif
341
342#endif /* _MC68681_P_H_ */
ISR_Handler rtems_isr
This type defines the return type of interrupt service routines.
Definition: intr.h:123
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition: intr.h:102
Definition: mc68681_p.h:263