22#ifndef LIBBSP_ARM_LPC176X_H
23#define LIBBSP_ARM_LPC176X_H
27#define LPC176X_PLL_CON_PLLE BSP_BIT32( 0 )
28#define LPC176X_PLL_CON_PLLC BSP_BIT32( 1 )
29#define LPC176X_PLL_SEL_MSEL( val ) BSP_FLD32( val, 0, 14 )
30#define LPC176X_PLL_SEL_MSEL_GET( reg ) BSP_FLD32GET( reg, 0, 14 )
31#define LPC176X_PLL_SEL_MSEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 14 )
32#define LPC176X_PLL_SEL_PSEL( val ) BSP_FLD32( val, 16, 23 )
33#define LPC176X_PLL_SEL_PSEL_GET( reg ) BSP_FLD32GET( reg, 16, 23 )
34#define LPC176X_PLL_SEL_PSEL_SET( reg, val ) BSP_FLD32SET( reg, val, 16, 23 )
35#define LPC176X_PLL_STAT_PLLE BSP_BIT32( 24 )
36#define LPC176X_PLL_STAT_PLLC BSP_BIT32( 25 )
37#define LPC176X_PLL_STAT_PLOCK BSP_BIT32( 26 )
61#define LPC176X_SCB_BASE_ADDR 0x400FC000U
62#define LPC176X_SCB_FLASHCFG_FLASHTIM( val ) BSP_FLD32( val, 12, 15 )
63#define LPC176X_SCB_FLASHCFG_FLASHTIM_GET( reg ) BSP_FLD32GET( reg, 12, 15 )
64#define LPC176X_SCB_FLASHCFG_FLASHTIM_SET( reg, val ) BSP_FLD32SET( reg, val, \
66#define LPC176X_SCB_MEMMAP_MAP BSP_BIT32( 0 )
69#define LPC176X_SCB_PCON_PM0 BSP_BIT32( 0 )
71#define LPC176X_SCB_PCON_PM1 BSP_BIT32( 1 )
73#define LPC176X_SCB_PCON_BODRPM BSP_BIT32( 2 )
75#define LPC176X_SCB_PCON_BOGD BSP_BIT32( 3 )
77#define LPC176X_SCB_PCON_BORD BSP_BIT32( 4 )
79#define LPC176X_SCB_PCON_SMFLAG BSP_BIT32( 8 )
81#define LPC176X_SCB_PCON_DSFLAG BSP_BIT32( 9 )
83#define LPC176X_SCB_PCON_PDFLAG BSP_BIT32( 10 )
85#define LPC176X_SCB_PCON_DPDFLAG BSP_BIT32( 11 )
89#define LPC176X_SCB_PCONP_TIMER_0 BSP_BIT32( 1 )
91#define LPC176X_SCB_PCONP_TIMER_1 BSP_BIT32( 2 )
93#define LPC176X_SCB_PCONP_UART_0 BSP_BIT32( 3 )
95#define LPC176X_SCB_PCONP_UART_1 BSP_BIT32( 4 )
98#define LPC176X_SCB_PCONP_PWM_0 BSP_BIT32( 6 )
100#define LPC176X_SCB_PCONP_I2C_0 BSP_BIT32( 7 )
102#define LPC176X_SCB_PCONP_SPI BSP_BIT32( 8 )
104#define LPC176X_SCB_PCONP_RTC BSP_BIT32( 9 )
106#define LPC176X_SCB_PCONP_SSP_1 BSP_BIT32( 10 )
109#define LPC176X_SCB_PCONP_ADC BSP_BIT32( 12 )
111#define LPC176X_SCB_PCONP_CAN_1 BSP_BIT32( 13 )
113#define LPC176X_SCB_PCONP_CAN_2 BSP_BIT32( 14 )
115#define LPC176X_SCB_PCONP_GPIO BSP_BIT32( 15 )
117#define LPC176X_SCB_PCONP_RIT BSP_BIT32( 16 )
119#define LPC176X_SCB_PCONP_MCPWM BSP_BIT32( 17 )
121#define LPC176X_SCB_PCONP_QEI BSP_BIT32( 18 )
123#define LPC176X_SCB_PCONP_I2C_1 BSP_BIT32( 19 )
126#define LPC176X_SCB_PCONP_SSP_0 BSP_BIT32( 21 )
128#define LPC176X_SCB_PCONP_TIMER_2 BSP_BIT32( 22 )
130#define LPC176X_SCB_PCONP_TIMER_3 BSP_BIT32( 23 )
132#define LPC176X_SCB_PCONP_UART_2 BSP_BIT32( 24 )
134#define LPC176X_SCB_PCONP_UART_3 BSP_BIT32( 25 )
136#define LPC176X_SCB_PCONP_I2C_2 BSP_BIT32( 26 )
138#define LPC176X_SCB_PCONP_I2S BSP_BIT32( 27 )
141#define LPC176X_SCB_PCONP_GPDMA BSP_BIT32( 29 )
143#define LPC176X_SCB_PCONP_ENET BSP_BIT32( 30 )
145#define LPC176X_SCB_PCONP_USB BSP_BIT32( 31 )
146#define LPC176X_SCB_CCLKSEL_CCLKDIV( val ) BSP_FLD32( val, 0, 7 )
147#define LPC176X_SCB_CCLKSEL_CCLKDIV_GET( reg ) BSP_FLD32GET( reg, 0, 7 )
148#define LPC176X_SCB_CCLKSEL_CCLKDIV_SET( reg, val ) BSP_FLD32SET( reg, \
152#define LPC176X_SCB_CCLKSEL_CCLKSEL BSP_BIT32( 8 )
153#define LPC176X_SCB_USBCLKSEL_USBDIV( val ) BSP_FLD32( val, 0, 4 )
154#define LPC176X_SCB_USBCLKSEL_USBDIV_GET( reg ) BSP_FLD32GET( reg, 0, 4 )
155#define LPC176X_SCB_USBCLKSEL_USBDIV_SET( reg, val ) BSP_FLD32SET( reg, \
159#define LPC176X_SCB_USBCLKSEL_USBSEL( val ) BSP_FLD32( val, 8, 9 )
160#define LPC176X_SCB_USBCLKSEL_USBSEL_GET( reg ) BSP_FLD32GET( reg, 8, 9 )
161#define LPC176X_SCB_USBCLKSEL_USBSEL_SET( reg, val ) BSP_FLD32SET( reg, \
165#define LPC176X_SCB_CLKSRCSEL_CLKSRC BSP_BIT32( 0 )
166#define LPC176X_SCB_SCS_MCIPWR BSP_BIT32( 3 )
167#define LPC176X_SCB_SCS_OSC_RANGE_SEL BSP_BIT32( 4 )
168#define LPC176X_SCB_SCS_OSC_ENABLE BSP_BIT32( 5 )
169#define LPC176X_SCB_SCS_OSC_STATUS BSP_BIT32( 6 )
170#define LPC176X_SCB_PCLKSEL_PCLKDIV( val ) BSP_FLD32( val, 0, 4 )
171#define LPC176X_SCB_PCLKSEL_PCLKDIV_GET( reg ) BSP_FLD32GET( reg, 0, 4 )
172#define LPC176X_SCB_PCLKSEL_PCLKDIV_SET( reg, val ) BSP_FLD32SET( reg, \
176#define LPC176X_SCB_PBOOST_BOOST BSP_BIT32( 0 )
177#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL( val ) BSP_FLD32( val, 3, 0 )
178#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL_GET( reg ) BSP_FLD32GET( reg, 3, 0 )
179#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL_SET( reg, val ) BSP_FLD32SET( reg, \
181#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV( val ) BSP_FLD32( val, 7, 4 )
182#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV_GET( reg ) BSP_FLD32GET( reg, 7, 4 )
183#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV_SET( reg, val ) BSP_FLD32SET( reg, \
185#define LPC176X_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32( 8 )
186#define LPC176X_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32( 9 )
196 uint32_t reserved_04[ 15 ];
201 uint32_t reserved_44[ 15 ];
206 uint32_t reserved_90[ 4 ];
211 uint32_t reserved_b0[ 4 ];
220 uint32_t reserved_c8[ 15 ];
235 uint32_t reserved_110[ 12 ];
240 uint32_t reserved_144;
249 uint32_t reserved_150[ 12 ];
254 uint32_t reserved_184[ 7 ];
259 uint32_t reserved_1a4;
263 uint32_t pclksel[ 2 ];
268 uint32_t reserved_1b4[ 5 ];
276 uint32_t rstcon[ 2 ];
277 uint32_t reserved_1d4[ 4 ];
280#define LPC176X_BASE 0x00u
281#define LPC176X_SCB ( *(volatile lpc176x_scb *) ( LPC176X_SCB_BASE_ADDR ) )
284#define LPC176X_FIO_BASE_ADDR 0x2009C000U
285#define LPC176X_FIO ( (volatile lpc176x_fio *) LPC176X_FIO_BASE_ADDR )
287#define FIO0DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) )
288#define FIO0MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) )
289#define FIO0PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) )
290#define FIO0SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) )
291#define FIO0CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) )
293#define FIO1DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) )
294#define FIO1MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) )
295#define FIO1PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) )
296#define FIO1SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) )
297#define FIO1CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) )
299#define FIO2DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) )
300#define FIO2MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) )
301#define FIO2PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) )
302#define FIO2SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) )
303#define FIO2CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) )
305#define FIO3DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) )
306#define FIO3MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) )
307#define FIO3PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) )
308#define FIO3SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) )
309#define FIO3CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) )
311#define FIO4DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) )
312#define FIO4MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) )
313#define FIO4PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) )
314#define FIO4SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) )
315#define FIO4CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) )
318#define FIO0DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) )
319#define FIO1DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) )
320#define FIO2DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) )
321#define FIO3DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) )
322#define FIO4DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) )
324#define FIO0DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x01U ) )
325#define FIO1DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x21U ) )
326#define FIO2DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x41U ) )
327#define FIO3DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x61U ) )
328#define FIO4DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x81U ) )
330#define FIO0DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x02U ) )
331#define FIO1DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x22U ) )
332#define FIO2DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x42U ) )
333#define FIO3DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x62U ) )
334#define FIO4DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x82U ) )
336#define FIO0DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x03U ) )
337#define FIO1DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x23U ) )
338#define FIO2DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x43U ) )
339#define FIO3DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x63U ) )
340#define FIO4DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x83U ) )
342#define FIO0DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) )
343#define FIO1DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) )
344#define FIO2DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) )
345#define FIO3DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) )
346#define FIO4DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) )
348#define FIO0DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x02U ) )
349#define FIO1DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x22U ) )
350#define FIO2DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x42U ) )
351#define FIO3DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x62U ) )
352#define FIO4DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x82U ) )
354#define FIO0MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) )
355#define FIO1MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) )
356#define FIO2MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) )
357#define FIO3MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) )
358#define FIO4MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) )
360#define FIO0MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x11U ) )
361#define FIO1MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x21U ) )
362#define FIO2MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x51U ) )
363#define FIO3MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x71U ) )
364#define FIO4MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x91U ) )
366#define FIO0MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x12U ) )
367#define FIO1MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x32U ) )
368#define FIO2MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x52U ) )
369#define FIO3MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x72U ) )
370#define FIO4MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x92U ) )
372#define FIO0MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x13U ) )
373#define FIO1MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x33U ) )
374#define FIO2MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x53U ) )
375#define FIO3MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x73U ) )
376#define FIO4MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x93U ) )
378#define FIO0MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) )
379#define FIO1MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) )
380#define FIO2MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) )
381#define FIO3MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) )
382#define FIO4MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) )
384#define FIO0MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x12U ) )
385#define FIO1MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x32U ) )
386#define FIO2MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x52U ) )
387#define FIO3MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x72U ) )
388#define FIO4MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x92U ) )
390#define FIO0PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) )
391#define FIO1PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) )
392#define FIO2PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) )
393#define FIO3PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) )
394#define FIO4PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) )
396#define FIO0PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x15U ) )
397#define FIO1PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x25U ) )
398#define FIO2PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x55U ) )
399#define FIO3PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x75U ) )
400#define FIO4PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x95U ) )
402#define FIO0PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x16U ) )
403#define FIO1PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x36U ) )
404#define FIO2PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x56U ) )
405#define FIO3PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x76U ) )
406#define FIO4PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x96U ) )
408#define FIO0PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x17U ) )
409#define FIO1PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x37U ) )
410#define FIO2PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x57U ) )
411#define FIO3PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x77U ) )
412#define FIO4PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x97U ) )
414#define FIO0PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) )
415#define FIO1PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) )
416#define FIO2PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) )
417#define FIO3PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) )
418#define FIO4PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) )
420#define FIO0PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x16U ) )
421#define FIO1PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x36U ) )
422#define FIO2PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x56U ) )
423#define FIO3PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x76U ) )
424#define FIO4PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x96U ) )
426#define FIO0SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) )
427#define FIO1SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) )
428#define FIO2SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) )
429#define FIO3SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) )
430#define FIO4SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) )
432#define FIO0SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x19U ) )
433#define FIO1SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x29U ) )
434#define FIO2SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x59U ) )
435#define FIO3SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x79U ) )
436#define FIO4SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x99U ) )
438#define FIO0SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1AU ) )
439#define FIO1SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3AU ) )
440#define FIO2SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5AU ) )
441#define FIO3SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7AU ) )
442#define FIO4SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9AU ) )
444#define FIO0SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1BU ) )
445#define FIO1SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3BU ) )
446#define FIO2SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5BU ) )
447#define FIO3SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7BU ) )
448#define FIO4SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9BU ) )
450#define FIO0SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) )
451#define FIO1SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) )
452#define FIO2SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) )
453#define FIO3SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) )
454#define FIO4SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) )
456#define FIO0SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1AU ) )
457#define FIO1SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3AU ) )
458#define FIO2SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5AU ) )
459#define FIO3SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7AU ) )
460#define FIO4SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x9AU ) )
462#define FIO0CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) )
463#define FIO1CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) )
464#define FIO2CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) )
465#define FIO3CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) )
466#define FIO4CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) )
468#define FIO0CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1DU ) )
469#define FIO1CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x2DU ) )
470#define FIO2CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5DU ) )
471#define FIO3CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7DU ) )
472#define FIO4CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9DU ) )
474#define FIO0CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1EU ) )
475#define FIO1CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3EU ) )
476#define FIO2CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5EU ) )
477#define FIO3CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7EU ) )
478#define FIO4CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9EU ) )
480#define FIO0CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1FU ) )
481#define FIO1CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3FU ) )
482#define FIO2CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5FU ) )
483#define FIO3CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7FU ) )
484#define FIO4CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9FU ) )
486#define FIO0CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) )
487#define FIO1CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) )
488#define FIO2CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) )
489#define FIO3CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) )
490#define FIO4CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) )
492#define FIO0CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1EU ) )
493#define FIO1CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3EU ) )
494#define FIO2CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5EU ) )
495#define FIO3CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7EU ) )
496#define FIO4CLRU ( *(volatile uint16_t *) ( FIO_BASE_ADDR + 0x9EU ) )
498#define LPC176X_USB_CLOCK 48000000U
499#define LPC176X_MODULE_CLOCK_MASK 0x3U
502#define PINSEL_BASE_ADDR 0x4002C000U
504#define PINSEL0 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x00U ) )
505#define PINSEL1 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x04U ) )
506#define PINSEL2 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x08U ) )
507#define PINSEL3 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x0CU ) )
508#define PINSEL4 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x10U ) )
509#define PINSEL5 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x14U ) )
510#define PINSEL6 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x18U ) )
511#define PINSEL7 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x1CU ) )
512#define PINSEL8 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x20U ) )
513#define PINSEL9 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x24U ) )
514#define PINSEL10 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x28U ) )
515#define PINSEL11 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x2CU ) )
517#define PINMODE0 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x40U ) )
518#define PINMODE1 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x44U ) )
519#define PINMODE2 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x48U ) )
520#define PINMODE3 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x4CU ) )
521#define PINMODE4 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x50U ) )
522#define PINMODE5 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x54U ) )
523#define PINMODE6 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x58U ) )
524#define PINMODE7 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x5CU ) )
525#define PINMODE8 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x60U ) )
526#define PINMODE9 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x64U ) )
529#define PWM0_BASE_ADDR 0x40014000
531#define PWM0IR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x00 ) )
532#define PWM0TCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x04 ) )
533#define PWM0TC ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x08 ) )
534#define PWM0PR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x0C ) )
535#define PWM0PC ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x10 ) )
536#define PWM0MCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x14 ) )
537#define PWM0MR0 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x18 ) )
538#define PWM0MR1 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x1C ) )
539#define PWM0MR2 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x20 ) )
540#define PWM0MR3 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x24 ) )
541#define PWM0CCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x28 ) )
542#define PWM0CR0 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x2C ) )
543#define PWM0CR1 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x30 ) )
544#define PWM0CR2 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x34 ) )
545#define PWM0CR3 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x38 ) )
546#define PWM0EMR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x3C ) )
547#define PWM0MR4 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x40 ) )
548#define PWM0MR5 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x44 ) )
549#define PWM0MR6 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x48 ) )
550#define PWM0PCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x4C ) )
551#define PWM0LER ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x50 ) )
552#define PWM0CTCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x70 ) )
554#define PWM1_BASE_ADDR 0x40018000
556#define PWM1IR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x00 ) )
557#define PWM1TCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x04 ) )
558#define PWM1TC ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x08 ) )
559#define PWM1PR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x0C ) )
560#define PWM1PC ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x10 ) )
561#define PWM1MCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x14 ) )
562#define PWM1MR0 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x18 ) )
563#define PWM1MR1 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x1C ) )
564#define PWM1MR2 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x20 ) )
565#define PWM1MR3 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x24 ) )
566#define PWM1CCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x28 ) )
567#define PWM1CR0 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x2C ) )
568#define PWM1CR1 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x30 ) )
569#define PWM1CR2 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x34 ) )
570#define PWM1CR3 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x38 ) )
571#define PWM1EMR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x3C ) )
572#define PWM1MR4 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x40 ) )
573#define PWM1MR5 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x44 ) )
574#define PWM1MR6 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x48 ) )
575#define PWM1PCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x4C ) )
576#define PWM1LER ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x50 ) )
577#define PWM1CTCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x70 ) )
580#define UART0_BASE_ADDR 0x4000C000
582#define U0RBR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) )
583#define U0THR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) )
584#define U0DLL ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) )
585#define U0DLM ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x04 ) )
586#define U0IER ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x04 ) )
587#define U0IIR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x08 ) )
588#define U0FCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x08 ) )
589#define U0LCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x0C ) )
590#define U0LSR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x14 ) )
591#define U0SCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x1C ) )
592#define U0ACR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x20 ) )
593#define U0ICR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x24 ) )
594#define U0FDR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x28 ) )
595#define U0TER ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x30 ) )
598#define UART1_BASE_ADDR 0x40010000
600#define U1RBR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) )
601#define U1THR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) )
602#define U1DLL ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) )
603#define U1DLM ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x04 ) )
604#define U1IER ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x04 ) )
605#define U1IIR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x08 ) )
606#define U1FCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x08 ) )
607#define U1LCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x0C ) )
608#define U1MCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x10 ) )
609#define U1LSR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x14 ) )
610#define U1MSR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x18 ) )
611#define U1SCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x1C ) )
612#define U1ACR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x20 ) )
613#define U1FDR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x28 ) )
614#define U1TER ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x30 ) )
617#define UART2_BASE_ADDR 0x40098000
619#define U2RBR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) )
620#define U2THR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) )
621#define U2DLL ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) )
622#define U2DLM ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x04 ) )
623#define U2IER ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x04 ) )
624#define U2IIR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x08 ) )
625#define U2FCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x08 ) )
626#define U2LCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x0C ) )
627#define U2LSR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x14 ) )
628#define U2SCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x1C ) )
629#define U2ACR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x20 ) )
630#define U2ICR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x24 ) )
631#define U2FDR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x28 ) )
632#define U2TER ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x30 ) )
635#define UART3_BASE_ADDR 0x4009C000
637#define U3RBR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) )
638#define U3THR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) )
639#define U3DLL ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) )
640#define U3DLM ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x04 ) )
641#define U3IER ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x04 ) )
642#define U3IIR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x08 ) )
643#define U3FCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x08 ) )
644#define U3LCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x0C ) )
645#define U3LSR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x14 ) )
646#define U3SCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x1C ) )
647#define U3ACR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x20 ) )
648#define U3ICR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x24 ) )
649#define U3FDR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x28 ) )
650#define U3TER ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x30 ) )
653#define SPI0_BASE_ADDR 0xE0020000
654#define S0SPCR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x00 ) )
655#define S0SPSR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x04 ) )
656#define S0SPDR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x08 ) )
657#define S0SPCCR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x0C ) )
658#define S0SPINT ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x1C ) )
661#define RTC_BASE_ADDR 0x40024000
663#define RTC_ILR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x00 ) )
664#define RTC_CTC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x04 ) )
665#define RTC_CCR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x08 ) )
666#define RTC_CIIR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x0C ) )
667#define RTC_AMR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x10 ) )
668#define RTC_CTIME0 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x14 ) )
669#define RTC_CTIME1 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x18 ) )
670#define RTC_CTIME2 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x1C ) )
671#define RTC_SEC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x20 ) )
672#define RTC_MIN ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x24 ) )
673#define RTC_HOUR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x28 ) )
674#define RTC_DOM ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x2C ) )
675#define RTC_DOW ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x30 ) )
676#define RTC_DOY ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x34 ) )
677#define RTC_MONTH ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x38 ) )
678#define RTC_YEAR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x3C ) )
679#define RTC_CISS ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x40 ) )
680#define RTC_ALSEC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x60 ) )
681#define RTC_ALMIN ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x64 ) )
682#define RTC_ALHOUR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x68 ) )
683#define RTC_ALDOM ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x6C ) )
684#define RTC_ALDOW ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x70 ) )
685#define RTC_ALDOY ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x74 ) )
686#define RTC_ALMON ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x78 ) )
687#define RTC_ALYEAR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x7C ) )
688#define RTC_PREINT ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x80 ) )
689#define RTC_PREFRAC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x84 ) )
692#define AD0_BASE_ADDR 0x40034000
694#define AD0CR ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x00 ) )
695#define AD0GDR ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x04 ) )
696#define AD0INTEN ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x0C ) )
697#define AD0_DATA_START ( (volatile uint32_t *) ( AD0_BASE_ADDR + 0x10 ) )
698#define AD0DR0 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x10 ) )
699#define AD0DR1 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x14 ) )
700#define AD0DR2 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x18 ) )
701#define AD0DR3 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x1C ) )
702#define AD0DR4 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x20 ) )
703#define AD0DR5 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x24 ) )
704#define AD0DR6 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x28 ) )
705#define AD0DR7 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x2C ) )
706#define AD0STAT ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x30 ) )
709#define DAC_BASE_ADDR 0x4008C000
711#define DACR ( *(volatile uint32_t *) ( DAC_BASE_ADDR + 0x00 ) )
714#define CAN_ACCEPT_BASE_ADDR 0x4003C000
716#define CAN_AFMR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x00 ) )
717#define CAN_SFF_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x04 ) )
718#define CAN_SFF_GRP_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \
720#define CAN_EFF_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x0C ) )
721#define CAN_EFF_GRP_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \
723#define CAN_EOT ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x14 ) )
724#define CAN_LUT_ERR_ADR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \
726#define CAN_LUT_ERR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x1C ) )
728#define CAN_CENTRAL_BASE_ADDR 0x40040000
730#define CAN_TX_SR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x00 ) )
731#define CAN_RX_SR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x04 ) )
732#define CAN_MSR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x08 ) )
734#define CAN1_BASE_ADDR 0x40044000
736#define CAN1MOD ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x00 ) )
737#define CAN1CMR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x04 ) )
738#define CAN1GSR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x08 ) )
739#define CAN1ICR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x0C ) )
740#define CAN1IER ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x10 ) )
741#define CAN1BTR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x14 ) )
742#define CAN1EWL ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x18 ) )
743#define CAN1SR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x1C ) )
744#define CAN1RFS ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x20 ) )
745#define CAN1RID ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x24 ) )
746#define CAN1RDA ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x28 ) )
747#define CAN1RDB ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x2C ) )
749#define CAN1TFI1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x30 ) )
750#define CAN1TID1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x34 ) )
751#define CAN1TDA1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x38 ) )
752#define CAN1TDB1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x3C ) )
753#define CAN1TFI2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x40 ) )
754#define CAN1TID2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x44 ) )
755#define CAN1TDA2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x48 ) )
756#define CAN1TDB2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x4C ) )
757#define CAN1TFI3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x50 ) )
758#define CAN1TID3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x54 ) )
759#define CAN1TDA3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x58 ) )
760#define CAN1TDB3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x5C ) )
762#define CAN2_BASE_ADDR 0x40048000
764#define CAN2MOD ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x00 ) )
765#define CAN2CMR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x04 ) )
766#define CAN2GSR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x08 ) )
767#define CAN2ICR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x0C ) )
768#define CAN2IER ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x10 ) )
769#define CAN2BTR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x14 ) )
770#define CAN2EWL ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x18 ) )
771#define CAN2SR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x1C ) )
772#define CAN2RFS ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x20 ) )
773#define CAN2RID ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x24 ) )
774#define CAN2RDA ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x28 ) )
775#define CAN2RDB ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x2C ) )
777#define CAN2TFI1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x30 ) )
778#define CAN2TID1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x34 ) )
779#define CAN2TDA1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x38 ) )
780#define CAN2TDB1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x3C ) )
781#define CAN2TFI2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x40 ) )
782#define CAN2TID2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x44 ) )
783#define CAN2TDA2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x48 ) )
784#define CAN2TDB2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x4C ) )
785#define CAN2TFI3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x50 ) )
786#define CAN2TID3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x54 ) )
787#define CAN2TDA3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x58 ) )
788#define CAN2TDB3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x5C ) )
791#define MCI_BASE_ADDR 0x400c0000
793#define MCI_POWER ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x00 ) )
794#define MCI_CLOCK ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x04 ) )
795#define MCI_ARGUMENT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x08 ) )
796#define MCI_COMMAND ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x0C ) )
797#define MCI_RESP_CMD ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x10 ) )
798#define MCI_RESP0 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x14 ) )
799#define MCI_RESP1 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x18 ) )
800#define MCI_RESP2 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x1C ) )
801#define MCI_RESP3 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x20 ) )
802#define MCI_DATA_TMR ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x24 ) )
803#define MCI_DATA_LEN ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x28 ) )
804#define MCI_DATA_CTRL ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x2C ) )
805#define MCI_DATA_CNT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x30 ) )
806#define MCI_STATUS ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x34 ) )
807#define MCI_CLEAR ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x38 ) )
808#define MCI_MASK0 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x3C ) )
809#define MCI_MASK1 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x40 ) )
810#define MCI_FIFO_CNT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x48 ) )
811#define MCI_FIFO ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x80 ) )
814#define I2S_BASE_ADDR 0x400a8000
816#define I2S_DAO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x00 ) )
817#define I2S_DAI ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x04 ) )
818#define I2S_TX_FIFO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x08 ) )
819#define I2S_RX_FIFO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x0C ) )
820#define I2S_STATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x10 ) )
821#define I2S_DMA1 ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x14 ) )
822#define I2S_DMA2 ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x18 ) )
823#define I2S_IRQ ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x1C ) )
824#define I2S_TXRATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x20 ) )
825#define I2S_RXRATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x24 ) )
828#define DMA_BASE_ADDR 0x50004000
830#define GPDMA_INT_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x000 ) )
831#define GPDMA_INT_TCSTAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x004 ) )
832#define GPDMA_INT_TCCLR ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x008 ) )
833#define GPDMA_INT_ERR_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x00C ) )
834#define GPDMA_INT_ERR_CLR ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x010 ) )
835#define GPDMA_RAW_INT_TCSTAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + \
837#define GPDMA_RAW_INT_ERR_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + \
839#define GPDMA_ENABLED_CHNS ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x01C ) )
840#define GPDMA_SOFT_BREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x020 ) )
841#define GPDMA_SOFT_SREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x024 ) )
842#define GPDMA_SOFT_LBREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x028 ) )
843#define GPDMA_SOFT_LSREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x02C ) )
844#define GPDMA_CONFIG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x030 ) )
845#define GPDMA_SYNC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x034 ) )
848#define GPDMA_CH0_BASE_ADDR ( DMA_BASE_ADDR + 0x100 )
849#define GPDMA_CH0_SRC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x100 ) )
850#define GPDMA_CH0_DEST ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x104 ) )
851#define GPDMA_CH0_LLI ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x108 ) )
852#define GPDMA_CH0_CTRL ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x10C ) )
853#define GPDMA_CH0_CFG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x110 ) )
856#define GPDMA_CH1_BASE_ADDR ( DMA_BASE_ADDR + 0x120 )
857#define GPDMA_CH1_SRC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x120 ) )
858#define GPDMA_CH1_DEST ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x124 ) )
859#define GPDMA_CH1_LLI ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x128 ) )
860#define GPDMA_CH1_CTRL ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x12C ) )
861#define GPDMA_CH1_CFG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x130 ) )
864#define USB_INT_BASE_ADDR 0x400fc1c0
865#define USB_BASE_ADDR 0x2008c200
867#define USB_INT_STAT ( *(volatile uint32_t *) ( USB_INT_BASE_ADDR + 0x00 ) )
870#define DEV_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x00 ) )
871#define DEV_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x04 ) )
872#define DEV_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x08 ) )
873#define DEV_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x0C ) )
874#define DEV_INT_PRIO ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x2C ) )
877#define EP_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x30 ) )
878#define EP_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x34 ) )
879#define EP_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x38 ) )
880#define EP_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x3C ) )
881#define EP_INT_PRIO ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x40 ) )
884#define REALIZE_EP ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x44 ) )
885#define EP_INDEX ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x48 ) )
886#define MAXPACKET_SIZE ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x4C ) )
889#define CMD_CODE ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x10 ) )
890#define CMD_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x14 ) )
893#define RX_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x18 ) )
894#define TX_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x1C ) )
895#define RX_PLENGTH ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x20 ) )
896#define TX_PLENGTH ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x24 ) )
897#define USB_CTRL ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x28 ) )
900#define DMA_REQ_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x50 ) )
901#define DMA_REQ_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x54 ) )
902#define DMA_REQ_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x58 ) )
903#define UDCA_HEAD ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x80 ) )
904#define EP_DMA_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x84 ) )
905#define EP_DMA_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x88 ) )
906#define EP_DMA_DIS ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x8C ) )
907#define DMA_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x90 ) )
908#define DMA_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x94 ) )
909#define EOT_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA0 ) )
910#define EOT_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA4 ) )
911#define EOT_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA8 ) )
912#define NDD_REQ_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xAC ) )
913#define NDD_REQ_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB0 ) )
914#define NDD_REQ_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB4 ) )
915#define SYS_ERR_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB8 ) )
916#define SYS_ERR_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xBC ) )
917#define SYS_ERR_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xC0 ) )
920#define USBHC_BASE_ADDR 0x2008c000
922#define HC_REVISION ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x00 ) )
923#define HC_CONTROL ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x04 ) )
924#define HC_CMD_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x08 ) )
925#define HC_INT_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x0C ) )
926#define HC_INT_EN ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x10 ) )
927#define HC_INT_DIS ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x14 ) )
928#define HC_HCCA ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x18 ) )
929#define HC_PERIOD_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x1C ) )
930#define HC_CTRL_HEAD_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x20 ) )
931#define HC_CTRL_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x24 ) )
932#define HC_BULK_HEAD_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x28 ) )
933#define HC_BULK_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x2C ) )
934#define HC_DONE_HEAD ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x30 ) )
935#define HC_FM_INTERVAL ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x34 ) )
936#define HC_FM_REMAINING ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x38 ) )
937#define HC_FM_NUMBER ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x3C ) )
938#define HC_PERIOD_START ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x40 ) )
939#define HC_LS_THRHLD ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x44 ) )
940#define HC_RH_DESCA ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x48 ) )
941#define HC_RH_DESCB ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x4C ) )
942#define HC_RH_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x50 ) )
943#define HC_RH_PORT_STAT1 ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x54 ) )
944#define HC_RH_PORT_STAT2 ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x58 ) )
947#define USBOTG_BASE_ADDR 0x2008c100
949#define OTG_INT_STAT ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x00 ) )
950#define OTG_INT_EN ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x04 ) )
951#define OTG_INT_SET ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x08 ) )
952#define OTG_INT_CLR ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x0C ) )
953#define OTG_STAT_CTRL ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x10 ) )
954#define OTG_TIMER ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x14 ) )
956#define USBOTG_I2C_BASE_ADDR 0x2008c300
958#define OTG_I2C_RX ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x00 ) )
959#define OTG_I2C_TX ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x00 ) )
960#define OTG_I2C_STS ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x04 ) )
961#define OTG_I2C_CTL ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x08 ) )
962#define OTG_I2C_CLKHI ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + \
964#define OTG_I2C_CLKLO ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + \
967#define USBOTG_CLK_BASE_ADDR 0x2008CFF0U
969#define OTG_CLK_CTRL ( *(volatile uint32_t *) ( USBOTG_CLK_BASE_ADDR + \
971#define OTG_CLK_STAT ( *(volatile uint32_t *) ( USBOTG_CLK_BASE_ADDR + \
975#define GET_FIELD( val, mask, shift ) \
976 ( ( ( val ) & ( mask ) ) >> ( shift ) )
978#define SET_FIELD( val, field, mask, shift ) \
979 ( ( ( val ) & ~( mask ) ) | ( ( ( field ) << ( shift ) ) & ( mask ) ) )
982#define CLKSRCSEL_CLKSRC_MASK 0x00000003U
984#define GET_CLKSRCSEL_CLKSRC( reg ) \
985 GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0 )
987#define SET_CLKSRCSEL_CLKSRC( reg, val ) \
988 SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0 )
991#define PLLCON_PLLE 0x00000001U
993#define PLLCON_PLLC 0x00000002U
996#define PLLCFG_MSEL_MASK 0x00007fffU
998#define GET_PLLCFG_MSEL( reg ) \
999 GET_FIELD( reg, PLLCFG_MSEL_MASK, 0 )
1001#define SET_PLLCFG_MSEL( reg, val ) \
1002 SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0 )
1004#define PLLCFG_NSEL_MASK 0x00ff0000U
1006#define GET_PLLCFG_NSEL( reg ) \
1007 GET_FIELD( reg, PLLCFG_NSEL_MASK, 16 )
1009#define SET_PLLCFG_NSEL( reg, val ) \
1010 SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16 )
1013#define PLLSTAT_MSEL_MASK 0x00007fffU
1015#define GET_PLLSTAT_MSEL( reg ) \
1016 GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0 )
1018#define SET_PLLSTAT_MSEL( reg, val ) \
1019 SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0 )
1021#define PLLSTAT_NSEL_MASK 0x00ff0000U
1023#define GET_PLLSTAT_NSEL( reg ) \
1024 GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16 )
1026#define SET_PLLSTAT_NSEL( reg, val ) \
1027 SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16 )
1029#define PLLSTAT_PLLE 0x01000000U
1031#define PLLSTAT_PLLC 0x02000000U
1033#define PLLSTAT_PLOCK 0x04000000U
1036#define CCLKCFG_CCLKSEL_MASK 0x000000ffU
1038#define GET_CCLKCFG_CCLKSEL( reg ) \
1039 GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0 )
1041#define SET_CCLKCFG_CCLKSEL( reg, val ) \
1042 SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0 )
1045#define MEMMAP_MAP_MASK 0x00000003U
1047#define GET_MEMMAP_MAP( reg ) \
1048 GET_FIELD( reg, MEMMAP_MAP_MASK, 0 )
1050#define SET_MEMMAP_MAP( reg, val ) \
1051 SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0 )
1054#define TIR_MR0 0x00000001U
1055#define TIR_MR1 0x00000002U
1056#define TIR_MR2 0x00000004U
1057#define TIR_MR3 0x00000008U
1058#define TIR_CR0 0x00000010U
1059#define TIR_CR1 0x00000020U
1060#define TIR_CR2 0x00000040U
1061#define TIR_CR3 0x00000080U
1064#define TCR_EN 0x00000001U
1065#define TCR_RST 0x00000002U
1068#define TMCR_MR0I 0x00000001U
1069#define TMCR_MR0R 0x00000002U
1070#define TMCR_MR0S 0x00000004U
1071#define TMCR_MR1I 0x00000008U
1072#define TMCR_MR1R 0x00000010U
1073#define TMCR_MR1S 0x00000020U
1074#define TMCR_MR2I 0x00000040U
1075#define TMCR_MR2R 0x00000080U
1076#define TMCR_MR2S 0x00000100U
1077#define TMCR_MR3I 0x00000200U
1078#define TMCR_MR3R 0x00000400U
1079#define TMCR_MR3S 0x00000800U
1082#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
1084#define GET_PCLKSEL0_PCLK_WDT( reg ) \
1085 GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0 )
1087#define SET_PCLKSEL0_PCLK_WDT( reg, val ) \
1088 SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0 )
1090#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
1092#define GET_PCLKSEL0_PCLK_TIMER0( reg ) \
1093 GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2 )
1095#define SET_PCLKSEL0_PCLK_TIMER0( reg, val ) \
1096 SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2 )
1098#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
1100#define GET_PCLKSEL0_PCLK_TIMER1( reg ) \
1101 GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4 )
1103#define SET_PCLKSEL0_PCLK_TIMER1( reg, val ) \
1104 SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4 )
1106#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
1108#define GET_PCLKSEL0_PCLK_UART0( reg ) \
1109 GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6 )
1111#define SET_PCLKSEL0_PCLK_UART0( reg, val ) \
1112 SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6 )
1114#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
1116#define GET_PCLKSEL0_PCLK_UART1( reg ) \
1117 GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8 )
1119#define SET_PCLKSEL0_PCLK_UART1( reg, val ) \
1120 SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8 )
1122#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
1124#define GET_PCLKSEL0_PCLK_PWM0( reg ) \
1125 GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10 )
1127#define SET_PCLKSEL0_PCLK_PWM0( reg, val ) \
1128 SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10 )
1130#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
1132#define GET_PCLKSEL0_PCLK_PWM1( reg ) \
1133 GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12 )
1135#define SET_PCLKSEL0_PCLK_PWM1( reg, val ) \
1136 SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12 )
1138#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
1140#define GET_PCLKSEL0_PCLK_I2C0( reg ) \
1141 GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14 )
1143#define SET_PCLKSEL0_PCLK_I2C0( reg, val ) \
1144 SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14 )
1146#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
1148#define GET_PCLKSEL0_PCLK_SPI( reg ) \
1149 GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16 )
1151#define SET_PCLKSEL0_PCLK_SPI( reg, val ) \
1152 SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16 )
1154#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
1156#define GET_PCLKSEL0_PCLK_RTC( reg ) \
1157 GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18 )
1159#define SET_PCLKSEL0_PCLK_RTC( reg, val ) \
1160 SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18 )
1162#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
1164#define GET_PCLKSEL0_PCLK_SSP1( reg ) \
1165 GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20 )
1167#define SET_PCLKSEL0_PCLK_SSP1( reg, val ) \
1168 SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20 )
1170#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
1172#define GET_PCLKSEL0_PCLK_DAC( reg ) \
1173 GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22 )
1175#define SET_PCLKSEL0_PCLK_DAC( reg, val ) \
1176 SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22 )
1178#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
1180#define GET_PCLKSEL0_PCLK_ADC( reg ) \
1181 GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24 )
1183#define SET_PCLKSEL0_PCLK_ADC( reg, val ) \
1184 SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24 )
1186#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
1188#define GET_PCLKSEL0_PCLK_CAN1( reg ) \
1189 GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26 )
1191#define SET_PCLKSEL0_PCLK_CAN1( reg, val ) \
1192 SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26 )
1194#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
1196#define GET_PCLKSEL0_PCLK_CAN2( reg ) \
1197 GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28 )
1199#define SET_PCLKSEL0_PCLK_CAN2( reg, val ) \
1200 SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28 )
1203#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
1205#define GET_PCLKSEL1_PCLK_BAT_RAM( reg ) \
1206 GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0 )
1208#define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val ) \
1209 SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0 )
1211#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
1213#define GET_PCLKSEL1_PCLK_GPIO( reg ) \
1214 GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2 )
1216#define SET_PCLKSEL1_PCLK_GPIO( reg, val ) \
1217 SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2 )
1219#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
1221#define GET_PCLKSEL1_PCLK_PCB( reg ) \
1222 GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4 )
1224#define SET_PCLKSEL1_PCLK_PCB( reg, val ) \
1225 SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4 )
1227#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
1229#define GET_PCLKSEL1_PCLK_I2C1( reg ) \
1230 GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6 )
1232#define SET_PCLKSEL1_PCLK_I2C1( reg, val ) \
1233 SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6 )
1235#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
1237#define GET_PCLKSEL1_PCLK_SSP0( reg ) \
1238 GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10 )
1240#define SET_PCLKSEL1_PCLK_SSP0( reg, val ) \
1241 SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10 )
1243#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
1245#define GET_PCLKSEL1_PCLK_TIMER2( reg ) \
1246 GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12 )
1248#define SET_PCLKSEL1_PCLK_TIMER2( reg, val ) \
1249 SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12 )
1251#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
1253#define GET_PCLKSEL1_PCLK_TIMER3( reg ) \
1254 GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14 )
1256#define SET_PCLKSEL1_PCLK_TIMER3( reg, val ) \
1257 SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14 )
1259#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
1261#define GET_PCLKSEL1_PCLK_UART2( reg ) \
1262 GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16 )
1264#define SET_PCLKSEL1_PCLK_UART2( reg, val ) \
1265 SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16 )
1267#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
1269#define GET_PCLKSEL1_PCLK_UART3( reg ) \
1270 GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18 )
1272#define SET_PCLKSEL1_PCLK_UART3( reg, val ) \
1273 SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18 )
1275#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
1277#define GET_PCLKSEL1_PCLK_I2C2( reg ) \
1278 GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20 )
1280#define SET_PCLKSEL1_PCLK_I2C2( reg, val ) \
1281 SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20 )
1283#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
1285#define GET_PCLKSEL1_PCLK_I2S( reg ) \
1286 GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22 )
1288#define SET_PCLKSEL1_PCLK_I2S( reg, val ) \
1289 SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22 )
1291#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
1293#define GET_PCLKSEL1_PCLK_MCI( reg ) \
1294 GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24 )
1296#define SET_PCLKSEL1_PCLK_MCI( reg, val ) \
1297 SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24 )
1299#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
1301#define GET_PCLKSEL1_PCLK_SYSCON( reg ) \
1302 GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28 )
1304#define SET_PCLKSEL1_PCLK_SYSCON( reg, val ) \
1305 SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28 )
1308#define RTC_ILR_RTCCIF 0x00000001U
1309#define RTC_ILR_RTCALF 0x00000002U
1310#define RTC_ILR_RTSSF 0x00000004U
1313#define RTC_CCR_CLKEN 0x00000001U
1314#define RTC_CCR_CTCRST 0x00000002U
1315#define RTC_CCR_CLKSRC 0x00000010U
1330#define GPDMA_CH_NUMBER 2
1331#define GPDMA_STATUS_CH_0 0x00000001U
1332#define GPDMA_STATUS_CH_1 0x00000002U
1333#define GPDMA_CH_BASE_ADDR( i ) \
1334 ( (volatile lpc176x_dma_channel *) \
1335 ( ( i ) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR ) )
1338#define GPDMA_CONFIG_EN 0x00000001U
1339#define GPDMA_CONFIG_MODE 0x00000002U
1342#define GPDMA_ENABLED_CHNS_CH0 0x00000001U
1343#define GPDMA_ENABLED_CHNS_CH1 0x00000002U
1346#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
1348#define GET_GPDMA_CH_CTRL_TSZ( reg ) \
1349 GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0 )
1351#define SET_GPDMA_CH_CTRL_TSZ( reg, val ) \
1352 SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0 )
1354#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
1356#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
1358#define GET_GPDMA_CH_CTRL_SBSZ( reg ) \
1359 GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12 )
1361#define SET_GPDMA_CH_CTRL_SBSZ( reg, val ) \
1362 SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12 )
1364#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
1366#define GET_GPDMA_CH_CTRL_DBSZ( reg ) \
1367 GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15 )
1369#define SET_GPDMA_CH_CTRL_DBSZ( reg, val ) \
1370 SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15 )
1372#define GPDMA_CH_CTRL_BSZ_1 0x00000000U
1374#define GPDMA_CH_CTRL_BSZ_4 0x00000001U
1376#define GPDMA_CH_CTRL_BSZ_8 0x00000002U
1378#define GPDMA_CH_CTRL_BSZ_16 0x00000003U
1380#define GPDMA_CH_CTRL_BSZ_32 0x00000004U
1382#define GPDMA_CH_CTRL_BSZ_64 0x00000005U
1384#define GPDMA_CH_CTRL_BSZ_128 0x00000006U
1386#define GPDMA_CH_CTRL_BSZ_256 0x00000007U
1388#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
1390#define GET_GPDMA_CH_CTRL_SW( reg ) \
1391 GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18 )
1393#define SET_GPDMA_CH_CTRL_SW( reg, val ) \
1394 SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18 )
1396#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
1398#define GET_GPDMA_CH_CTRL_DW( reg ) \
1399 GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21 )
1401#define SET_GPDMA_CH_CTRL_DW( reg, val ) \
1402 SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21 )
1404#define GPDMA_CH_CTRL_W_8 0x00000000U
1406#define GPDMA_CH_CTRL_W_16 0x00000001U
1408#define GPDMA_CH_CTRL_W_32 0x00000002U
1410#define GPDMA_CH_CTRL_SI 0x04000000U
1412#define GPDMA_CH_CTRL_DI 0x08000000U
1414#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
1416#define GET_GPDMA_CH_CTRL_PROT( reg ) \
1417 GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28 )
1419#define SET_GPDMA_CH_CTRL_PROT( reg, val ) \
1420 SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28 )
1422#define GPDMA_CH_CTRL_ITC 0x80000000U
1425#define GPDMA_CH_CFG_EN 0x00000001U
1427#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
1429#define GET_GPDMA_CH_CFG_SRCPER( reg ) \
1430 GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1 )
1432#define SET_GPDMA_CH_CFG_SRCPER( reg, val ) \
1433 SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1 )
1435#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
1437#define GET_GPDMA_CH_CFG_DESTPER( reg ) \
1438 GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6 )
1440#define SET_GPDMA_CH_CFG_DESTPER( reg, val ) \
1441 SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6 )
1443#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
1445#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U
1447#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U
1449#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U
1451#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U
1453#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U
1455#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U
1457#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
1459#define GET_GPDMA_CH_CFG_FLOW( reg ) \
1460 GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11 )
1462#define SET_GPDMA_CH_CFG_FLOW( reg, val ) \
1463 SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11 )
1465#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
1467#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U
1469#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U
1471#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U
1473#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U
1475#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U
1477#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U
1479#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U
1481#define GPDMA_CH_CFG_IE 0x00004000U
1483#define GPDMA_CH_CFG_ITC 0x00008000U
1485#define GPDMA_CH_CFG_LOCK 0x00010000U
1487#define GPDMA_CH_CFG_ACTIVE 0x00020000U
1489#define GPDMA_CH_CFG_HALT 0x00040000U
1492#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U
1494#define AHBCFG_BREAK_BURST_MASK 0x00000006U
1496#define GET_AHBCFG_BREAK_BURST( reg ) \
1497 GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1 )
1499#define SET_AHBCFG_BREAK_BURST( reg, val ) \
1500 SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1 )
1502#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
1504#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
1506#define GET_AHBCFG_QUANTUM_SIZE( reg ) \
1507 GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4 )
1509#define SET_AHBCFG_QUANTUM_SIZE( reg, val ) \
1510 SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4 )
1512#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
1514#define GET_AHBCFG_DEFAULT_MASTER( reg ) \
1515 GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8 )
1517#define SET_AHBCFG_DEFAULT_MASTER( reg, val ) \
1518 SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8 )
1520#define AHBCFG_EP1_MASK 0x00007000U
1522#define GET_AHBCFG_EP1( reg ) \
1523 GET_FIELD( reg, AHBCFG_EP1_MASK, 12 )
1525#define SET_AHBCFG_EP1( reg, val ) \
1526 SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12 )
1528#define AHBCFG_EP2_MASK 0x00070000U
1530#define GET_AHBCFG_EP2( reg ) \
1531 GET_FIELD( reg, AHBCFG_EP2_MASK, 16 )
1533#define SET_AHBCFG_EP2( reg, val ) \
1534 SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16 )
1536#define AHBCFG_EP3_MASK 0x00700000U
1538#define GET_AHBCFG_EP3( reg ) \
1539 GET_FIELD( reg, AHBCFG_EP3_MASK, 20 )
1541#define SET_AHBCFG_EP3( reg, val ) \
1542 SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20 )
1544#define AHBCFG_EP4_MASK 0x07000000U
1546#define GET_AHBCFG_EP4( reg ) \
1547 GET_FIELD( reg, AHBCFG_EP4_MASK, 24 )
1549#define SET_AHBCFG_EP4( reg, val ) \
1550 SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24 )
1552#define AHBCFG_EP5_MASK 0x70000000U
1554#define GET_AHBCFG_EP5( reg ) \
1555 GET_FIELD( reg, AHBCFG_EP5_MASK, 28 )
1557#define SET_AHBCFG_EP5( reg, val ) \
1558 SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28 )
1561static volatile lpc_i2s *
const lpc176x_i2s = (
lpc_i2s *) I2S_BASE_ADDR;
1564#define ADC_CR_SEL( val ) BSP_FLD32( val, 0, 7 )
1565#define ADC_CR_SEL_GET( val ) BSP_FLD32GET( val, 0, 7 )
1566#define ADC_CR_SEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 7 )
1567#define ADC_CR_CLKDIV( val ) BSP_FLD32( val, 8, 15 )
1568#define ADC_CR_CLKDIV_GET( reg ) BSP_FLD32GET( reg, 8, 15 )
1569#define ADC_CR_CLKDIV_SET( reg, val ) BSP_FLD32SET( reg, val, 8, 15 )
1570#define ADC_CR_BURST BSP_BIT32( 16 )
1571#define ADC_CR_CLKS( val ) BSP_FLD32( val, 17, 19 )
1572#define ADC_CR_PDN BSP_BIT32( 21 )
1573#define ADC_CR_START( val ) BSP_FLD32( val, 24, 26 )
1574#define ADC_CR_EDGE BSP_BIT32( 27 )
1576#define ADC_DR_VALUE( reg ) BSP_FLD32GET( reg, 6, 15 )
1577#define ADC_DR_OVERRUN BSP_BIT32( 30 )
1578#define ADC_DR_DONE BSP_BIT32( 31 )
1581#define DAC_STEPS 1024
1582#define DAC_VALUE( val ) BSP_FLD32( val, 6, 15 )
1583#define DAC_BIAS BSP_BIT32( 16 )
Definition: lpc176x.h:1325
Definition: lpc176x.h:1318
Phase-Locked Loop representation.
Definition: lpc176x.h:42
uint32_t stat
PLL Status Register.
Definition: lpc176x.h:54
uint32_t feed
PLL Feed Register.
Definition: lpc176x.h:58
uint32_t cfg
PLL Configuration Register.
Definition: lpc176x.h:50
uint32_t con
PLL Control Register.
Definition: lpc176x.h:46
System Control Block representation.
Definition: lpc176x.h:191
uint32_t flashcfg
Flash Accelerator Configuration Register.
Definition: lpc176x.h:195
uint32_t extint
External Interrupt flag register.
Definition: lpc176x.h:239
lpc176x_pll pll_0
Phase-Locked Loop 0.
Definition: lpc176x.h:205
uint32_t clksrcsel
Clock Source Select register.
Definition: lpc176x.h:234
lpc176x_pll pll_1
Phase-Locked Loop 1.
Definition: lpc176x.h:210
uint32_t usbclksel
Selects the divide value for creating the USB clock from the PPL0 output.
Definition: lpc176x.h:230
uint32_t pboost
Peripheral boost.
Definition: lpc176x.h:267
uint32_t extmode
External Interrupt Mode register.
Definition: lpc176x.h:244
uint32_t pconp
Power Control for Peripherals register.
Definition: lpc176x.h:219
uint32_t clkoutcfg
Clock Output Configuration Register.
Definition: lpc176x.h:272
uint32_t rsid
Reset Source Identification Register.
Definition: lpc176x.h:253
uint32_t memmap
Memopry Map Control.
Definition: lpc176x.h:200
uint32_t cclksel
Selects the divide valuefor creating the CPU clock from the PPL0 output.
Definition: lpc176x.h:225
uint32_t pcon
Power Mode Control register.
Definition: lpc176x.h:215
uint32_t scs
System Controls and Status Register.
Definition: lpc176x.h:258
uint32_t extpolar
External Interrupt Polarity register.
Definition: lpc176x.h:248
I2S control block.
Definition: lpc-i2s.h:59