55#ifndef _GRLIB_L4STAT_REGS_H
56#define _GRLIB_L4STAT_REGS_H
84#define L4STAT_CVAL_CVAL_SHIFT 0
85#define L4STAT_CVAL_CVAL_MASK 0xffffffffU
86#define L4STAT_CVAL_CVAL_GET( _reg ) \
87 ( ( ( _reg ) & L4STAT_CVAL_CVAL_MASK ) >> \
88 L4STAT_CVAL_CVAL_SHIFT )
89#define L4STAT_CVAL_CVAL_SET( _reg, _val ) \
90 ( ( ( _reg ) & ~L4STAT_CVAL_CVAL_MASK ) | \
91 ( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & \
92 L4STAT_CVAL_CVAL_MASK ) )
93#define L4STAT_CVAL_CVAL( _val ) \
94 ( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & \
95 L4STAT_CVAL_CVAL_MASK )
107#define L4STAT_CCTRL_NCPU_SHIFT 28
108#define L4STAT_CCTRL_NCPU_MASK 0xf0000000U
109#define L4STAT_CCTRL_NCPU_GET( _reg ) \
110 ( ( ( _reg ) & L4STAT_CCTRL_NCPU_MASK ) >> \
111 L4STAT_CCTRL_NCPU_SHIFT )
112#define L4STAT_CCTRL_NCPU_SET( _reg, _val ) \
113 ( ( ( _reg ) & ~L4STAT_CCTRL_NCPU_MASK ) | \
114 ( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \
115 L4STAT_CCTRL_NCPU_MASK ) )
116#define L4STAT_CCTRL_NCPU( _val ) \
117 ( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \
118 L4STAT_CCTRL_NCPU_MASK )
120#define L4STAT_CCTRL_NCNT_SHIFT 23
121#define L4STAT_CCTRL_NCNT_MASK 0xf800000U
122#define L4STAT_CCTRL_NCNT_GET( _reg ) \
123 ( ( ( _reg ) & L4STAT_CCTRL_NCNT_MASK ) >> \
124 L4STAT_CCTRL_NCNT_SHIFT )
125#define L4STAT_CCTRL_NCNT_SET( _reg, _val ) \
126 ( ( ( _reg ) & ~L4STAT_CCTRL_NCNT_MASK ) | \
127 ( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \
128 L4STAT_CCTRL_NCNT_MASK ) )
129#define L4STAT_CCTRL_NCNT( _val ) \
130 ( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \
131 L4STAT_CCTRL_NCNT_MASK )
133#define L4STAT_CCTRL_MC 0x400000U
135#define L4STAT_CCTRL_IA 0x200000U
137#define L4STAT_CCTRL_DS 0x100000U
139#define L4STAT_CCTRL_EE 0x80000U
141#define L4STAT_CCTRL_AE 0x40000U
143#define L4STAT_CCTRL_EL 0x20000U
145#define L4STAT_CCTRL_CD 0x10000U
147#define L4STAT_CCTRL_SU_SHIFT 14
148#define L4STAT_CCTRL_SU_MASK 0xc000U
149#define L4STAT_CCTRL_SU_GET( _reg ) \
150 ( ( ( _reg ) & L4STAT_CCTRL_SU_MASK ) >> \
151 L4STAT_CCTRL_SU_SHIFT )
152#define L4STAT_CCTRL_SU_SET( _reg, _val ) \
153 ( ( ( _reg ) & ~L4STAT_CCTRL_SU_MASK ) | \
154 ( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \
155 L4STAT_CCTRL_SU_MASK ) )
156#define L4STAT_CCTRL_SU( _val ) \
157 ( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \
158 L4STAT_CCTRL_SU_MASK )
160#define L4STAT_CCTRL_CL 0x2000U
162#define L4STAT_CCTRL_EN 0x1000U
164#define L4STAT_CCTRL_EVENT_ID_SHIFT 4
165#define L4STAT_CCTRL_EVENT_ID_MASK 0xff0U
166#define L4STAT_CCTRL_EVENT_ID_GET( _reg ) \
167 ( ( ( _reg ) & L4STAT_CCTRL_EVENT_ID_MASK ) >> \
168 L4STAT_CCTRL_EVENT_ID_SHIFT )
169#define L4STAT_CCTRL_EVENT_ID_SET( _reg, _val ) \
170 ( ( ( _reg ) & ~L4STAT_CCTRL_EVENT_ID_MASK ) | \
171 ( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \
172 L4STAT_CCTRL_EVENT_ID_MASK ) )
173#define L4STAT_CCTRL_EVENT_ID( _val ) \
174 ( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \
175 L4STAT_CCTRL_EVENT_ID_MASK )
177#define L4STAT_CCTRL_CPU_AHBM_SHIFT 0
178#define L4STAT_CCTRL_CPU_AHBM_MASK 0xfU
179#define L4STAT_CCTRL_CPU_AHBM_GET( _reg ) \
180 ( ( ( _reg ) & L4STAT_CCTRL_CPU_AHBM_MASK ) >> \
181 L4STAT_CCTRL_CPU_AHBM_SHIFT )
182#define L4STAT_CCTRL_CPU_AHBM_SET( _reg, _val ) \
183 ( ( ( _reg ) & ~L4STAT_CCTRL_CPU_AHBM_MASK ) | \
184 ( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \
185 L4STAT_CCTRL_CPU_AHBM_MASK ) )
186#define L4STAT_CCTRL_CPU_AHBM( _val ) \
187 ( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \
188 L4STAT_CCTRL_CPU_AHBM_MASK )
201#define L4STAT_CSVAL_CSVAL_SHIFT 0
202#define L4STAT_CSVAL_CSVAL_MASK 0xffffffffU
203#define L4STAT_CSVAL_CSVAL_GET( _reg ) \
204 ( ( ( _reg ) & L4STAT_CSVAL_CSVAL_MASK ) >> \
205 L4STAT_CSVAL_CSVAL_SHIFT )
206#define L4STAT_CSVAL_CSVAL_SET( _reg, _val ) \
207 ( ( ( _reg ) & ~L4STAT_CSVAL_CSVAL_MASK ) | \
208 ( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & \
209 L4STAT_CSVAL_CSVAL_MASK ) )
210#define L4STAT_CSVAL_CSVAL( _val ) \
211 ( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & \
212 L4STAT_CSVAL_CSVAL_MASK )
224#define L4STAT_TSTAMP_TSTAMP_SHIFT 0
225#define L4STAT_TSTAMP_TSTAMP_MASK 0xffffffffU
226#define L4STAT_TSTAMP_TSTAMP_GET( _reg ) \
227 ( ( ( _reg ) & L4STAT_TSTAMP_TSTAMP_MASK ) >> \
228 L4STAT_TSTAMP_TSTAMP_SHIFT )
229#define L4STAT_TSTAMP_TSTAMP_SET( _reg, _val ) \
230 ( ( ( _reg ) & ~L4STAT_TSTAMP_TSTAMP_MASK ) | \
231 ( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & \
232 L4STAT_TSTAMP_TSTAMP_MASK ) )
233#define L4STAT_TSTAMP_TSTAMP( _val ) \
234 ( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & \
235 L4STAT_TSTAMP_TSTAMP_MASK )
248 uint32_t reserved_4_3c[ 14 ];
255 uint32_t reserved_40_80[ 16 ];
262 uint32_t reserved_84_cc[ 18 ];
269 uint32_t reserved_d0_100[ 12 ];
276 uint32_t reserved_104_13c[ 14 ];
283 uint32_t reserved_140_180[ 16 ];
This structure defines the L4STAT register block memory map.
Definition: l4stat-regs.h:242
uint32_t csval_0
See Counter 0-15 max/latch register (CSVAL).
Definition: l4stat-regs.h:274
uint32_t cctrl_0
See Counter 0-15 control register (CCTRL).
Definition: l4stat-regs.h:260
uint32_t csval_1
See Counter 0-15 max/latch register (CSVAL).
Definition: l4stat-regs.h:281
uint32_t cctrl_1
See Counter 0-15 control register (CCTRL).
Definition: l4stat-regs.h:267
uint32_t cval_1
See Counter 0-15 value register (CVAL).
Definition: l4stat-regs.h:253
uint32_t cval_0
See Counter 0-15 value register (CVAL).
Definition: l4stat-regs.h:246
uint32_t tstamp
See Timestamp register (TSTAMP).
Definition: l4stat-regs.h:288