|
RTEMS 6.1-rc4
|
Loading...
Searching...
No Matches
Go to the documentation of this file.
33#ifndef _RTEMS_MIPS_IDTCPU_H
34#define _RTEMS_MIPS_IDTCPU_H
53#define K0BASE 0x80000000
54#define K0SIZE 0x20000000
55#define K1BASE 0xa0000000
56#define K1SIZE 0x20000000
57#define K2BASE 0xc0000000
58#define K2SIZE 0x20000000
60#define KSBASE 0xe0000000
61#define KSSIZE 0x20000000
65#define KUSIZE 0x80000000
72#define DB_VEC (K0BASE+0x40)
73#define E_VEC (K0BASE+0x80)
75#define T_VEC (K0BASE+0x000)
76#define X_VEC (K0BASE+0x080)
77#define C_VEC (K0BASE+0x100)
78#define E_VEC (K0BASE+0x180)
80#define T_VEC (K0BASE+0x000)
81#define X_VEC (K0BASE+0x080)
82#define C_VEC (K0BASE+0x100)
83#define E_VEC (K0BASE+0x180)
85#error "EXCEPTION VECTORS: unknown ISA level"
87#define R_VEC (K1BASE+0x1fc00000)
97#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000)
98#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF)
99#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF)
100#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF)
101#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000)
102#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000)
107#define MINCACHE 0x200
108#define MAXCACHE 0x40000
112#define CFG_CM 0x80000000
113#define CFG_ECMASK 0x70000000
114#define CFG_ECBY2 0x00000000
115#define CFG_ECBY3 0x10000000
116#define CFG_ECBY4 0x20000000
117#define CFG_EPMASK 0x0f000000
118#define CFG_EPD 0x00000000
119#define CFG_EPDDX 0x01000000
120#define CFG_EPDDXX 0x02000000
121#define CFG_EPDXDX 0x03000000
122#define CFG_EPDDXXX 0x04000000
123#define CFG_EPDDXXXX 0x05000000
124#define CFG_EPDXXDXX 0x06000000
125#define CFG_EPDDXXXXX 0x07000000
126#define CFG_EPDXXXDXXX 0x08000000
127#define CFG_SBMASK 0x00c00000
128#define CFG_SBSHIFT 22
129#define CFG_SB4 0x00000000
130#define CFG_SB8 0x00400000
131#define CFG_SB16 0x00800000
132#define CFG_SB32 0x00c00000
133#define CFG_SS 0x00200000
134#define CFG_SW 0x00100000
135#define CFG_EWMASK 0x000c0000
136#define CFG_EWSHIFT 18
137#define CFG_EW64 0x00000000
138#define CFG_EW32 0x00010000
139#define CFG_SC 0x00020000
140#define CFG_SM 0x00010000
141#define CFG_BE 0x00008000
142#define CFG_EM 0x00004000
143#define CFG_EB 0x00002000
144#define CFG_ICMASK 0x00000e00
146#define CFG_DCMASK 0x000001c0
148#define CFG_IB 0x00000020
149#define CFG_DB 0x00000010
150#define CFG_CU 0x00000008
151#define CFG_K0MASK 0x00000007
156#define CFG_C_UNCACHED 2
157#define CFG_C_NONCOHERENT 3
158#define CFG_C_COHERENTXCL 4
159#define CFG_C_COHERENTXCLW 5
160#define CFG_C_COHERENTUPD 6
165#define Index_Invalidate_I 0x0
166#define Index_Writeback_Inv_D 0x1
167#define Index_Invalidate_SI 0x2
168#define Index_Writeback_Inv_SD 0x3
169#define Index_Load_Tag_I 0x4
170#define Index_Load_Tag_D 0x5
171#define Index_Load_Tag_SI 0x6
172#define Index_Load_Tag_SD 0x7
173#define Index_Store_Tag_I 0x8
174#define Index_Store_Tag_D 0x9
175#define Index_Store_Tag_SI 0xA
176#define Index_Store_Tag_SD 0xB
177#define Create_Dirty_Exc_D 0xD
178#define Create_Dirty_Exc_SD 0xF
179#define Hit_Invalidate_I 0x10
180#define Hit_Invalidate_D 0x11
181#define Hit_Invalidate_SI 0x12
182#define Hit_Invalidate_SD 0x13
183#define Hit_Writeback_Inv_D 0x15
184#define Hit_Writeback_Inv_SD 0x17
186#define Hit_Writeback_D 0x19
187#define Hit_Writeback_SD 0x1B
188#define Hit_Writeback_I 0x18
189#define Hit_Set_Virtual_SI 0x1E
190#define Hit_Set_Virtual_SD 0x1F
207#define CFG_CM 0x80000000
208#define CFG_ECMASK 0x70000000
209#define CFG_ECBY2 0x00000000
210#define CFG_ECBY3 0x10000000
211#define CFG_ECBY4 0x20000000
212#define CFG_EPMASK 0x0f000000
213#define CFG_EPD 0x00000000
214#define CFG_EPDDX 0x01000000
215#define CFG_EPDDXX 0x02000000
216#define CFG_EPDXDX 0x03000000
217#define CFG_EPDDXXX 0x04000000
218#define CFG_EPDDXXXX 0x05000000
219#define CFG_EPDXXDXX 0x06000000
220#define CFG_EPDDXXXXX 0x07000000
221#define CFG_EPDXXXDXXX 0x08000000
222#define CFG_SBMASK 0x00c00000
223#define CFG_SBSHIFT 22
224#define CFG_SB4 0x00000000
225#define CFG_SB8 0x00400000
226#define CFG_SB16 0x00800000
227#define CFG_SB32 0x00c00000
228#define CFG_SS 0x00200000
229#define CFG_SW 0x00100000
230#define CFG_EWMASK 0x000c0000
231#define CFG_EWSHIFT 18
232#define CFG_EW64 0x00000000
233#define CFG_EW32 0x00010000
234#define CFG_SC 0x00020000
235#define CFG_SM 0x00010000
236#define CFG_BE 0x00008000
237#define CFG_EM 0x00004000
238#define CFG_EB 0x00002000
239#define CFG_ICMASK 0x00000e00
241#define CFG_DCMASK 0x000001c0
243#define CFG_IB 0x00000020
244#define CFG_DB 0x00000010
245#define CFG_CU 0x00000008
246#define CFG_K0MASK 0x00000007
251#define CFG_C_UNCACHED 2
252#define CFG_C_NONCOHERENT 3
253#define CFG_C_COHERENTXCL 4
254#define CFG_C_COHERENTXCLW 5
255#define CFG_C_COHERENTUPD 6
260#define Index_Invalidate_I 0x0
261#define Index_Writeback_Inv_D 0x1
262#define Index_Invalidate_SI 0x2
263#define Index_Writeback_Inv_SD 0x3
264#define Index_Load_Tag_I 0x4
265#define Index_Load_Tag_D 0x5
266#define Index_Load_Tag_SI 0x6
267#define Index_Load_Tag_SD 0x7
268#define Index_Store_Tag_I 0x8
269#define Index_Store_Tag_D 0x9
270#define Index_Store_Tag_SI 0xA
271#define Index_Store_Tag_SD 0xB
272#define Create_Dirty_Exc_D 0xD
273#define Create_Dirty_Exc_SD 0xF
274#define Hit_Invalidate_I 0x10
275#define Hit_Invalidate_D 0x11
276#define Hit_Invalidate_SI 0x12
277#define Hit_Invalidate_SD 0x13
278#define Hit_Writeback_Inv_D 0x15
279#define Hit_Writeback_Inv_SD 0x17
281#define Hit_Writeback_D 0x19
282#define Hit_Writeback_SD 0x1B
283#define Hit_Writeback_I 0x18
284#define Hit_Set_Virtual_SI 0x1E
285#define Hit_Set_Virtual_SD 0x1F
304#define N_TLB_ENTRIES 64
305#define TLB_PGSIZE 0x1000
307#define TLBLO_PFNMASK 0xfffff000
308#define TLBLO_PFNSHIFT 12
314#define TLBHI_VPNMASK 0xfffff000
315#define TLBHI_VPNSHIFT 12
316#define TLBHI_PIDMASK 0xfc0
317#define TLBHI_PIDSHIFT 6
320#define TLBINX_PROBE 0x80000000
321#define TLBINX_INXMASK 0x00003f00
322#define TLBINX_INXSHIFT 8
324#define TLBRAND_RANDMASK 0x00003f00
325#define TLBRAND_RANDSHIFT 8
327#define TLBCTXT_BASEMASK 0xffe00000
328#define TLBCTXT_BASESHIFT 21
330#define TLBCTXT_VPNMASK 0x001ffffc
331#define TLBCTXT_VPNSHIFT 2
334#define N_TLB_ENTRIES 48
336#define TLBHI_VPN2MASK 0xffffe000
337#define TLBHI_PIDMASK 0x000000ff
338#define TLBHI_NPID 256
340#define TLBLO_PFNMASK 0x3fffffc0
341#define TLBLO_PFNSHIFT 6
342#define TLBLO_D 0x00000004
343#define TLBLO_V 0x00000002
344#define TLBLO_G 0x00000001
345#define TLBLO_CMASK 0x00000038
346#define TLBLO_CSHIFT 3
348#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT)
349#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
350#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
351#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
352#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
354#define TLBINX_PROBE 0x80000000
355#define TLBINX_INXMASK 0x0000003f
357#define TLBRAND_RANDMASK 0x0000003f
359#define TLBCTXT_BASEMASK 0xff800000
360#define TLBCTXT_BASESHIFT 23
362#define TLBCTXT_VPN2MASK 0x007ffff0
363#define TLBCTXT_VPN2SHIFT 4
365#define TLBPGMASK_MASK 0x01ffe000
369#define N_TLB_ENTRIES 16
371#define TLBHI_VPN2MASK 0xffffe000
372#define TLBHI_PIDMASK 0x000000ff
373#define TLBHI_NPID 256
375#define TLBLO_PFNMASK 0x3fffffc0
376#define TLBLO_PFNSHIFT 6
377#define TLBLO_D 0x00000004
378#define TLBLO_V 0x00000002
379#define TLBLO_G 0x00000001
380#define TLBLO_CMASK 0x00000038
381#define TLBLO_CSHIFT 3
383#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT)
384#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
385#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
386#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
387#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
389#define TLBINX_PROBE 0x80000000
390#define TLBINX_INXMASK 0x0000003f
392#define TLBRAND_RANDMASK 0x0000003f
394#define TLBCTXT_BASEMASK 0xff800000
395#define TLBCTXT_BASESHIFT 23
397#define TLBCTXT_VPN2MASK 0x007ffff0
398#define TLBCTXT_VPN2SHIFT 4
400#define TLBPGMASK_MASK 0x01ffe000
407#define DCIC_TR 0x80000000
408#define DCIC_UD 0x40000000
409#define DCIC_KD 0x20000000
410#define DCIC_TE 0x10000000
411#define DCIC_DW 0x08000000
412#define DCIC_DR 0x04000000
413#define DCIC_DAE 0x02000000
414#define DCIC_PCE 0x01000000
415#define DCIC_DE 0x00800000
416#define DCIC_DL 0x00008000
417#define DCIC_IL 0x00004000
418#define DCIC_D 0x00002000
419#define DCIC_I 0x00001000
420#define DCIC_T 0x00000020
421#define DCIC_W 0x00000010
422#define DCIC_R 0x00000008
423#define DCIC_DA 0x00000004
424#define DCIC_PC 0x00000002
425#define DCIC_DB 0x00000001
430#define SR_CUMASK 0xf0000000
431#define SR_CU3 0x80000000
432#define SR_CU2 0x40000000
433#define SR_CU1 0x20000000
434#define SR_CU0 0x10000000
436#define SR_BEV 0x00400000
439#define SR_TS 0x00200000
440#define SR_PE 0x00100000
441#define SR_CM 0x00080000
442#define SR_PZ 0x00040000
443#define SR_SWC 0x00020000
444#define SR_ISC 0x00010000
450#define SR_IMASK 0x0000ff00
451#define SR_IMASK8 0x00000000
452#define SR_IMASK7 0x00008000
453#define SR_IMASK6 0x0000c000
454#define SR_IMASK5 0x0000e000
455#define SR_IMASK4 0x0000f000
456#define SR_IMASK3 0x0000f800
457#define SR_IMASK2 0x0000fc00
458#define SR_IMASK1 0x0000fe00
459#define SR_IMASK0 0x0000ff00
461#define SR_IMASKSHIFT 8
463#define SR_IBIT8 0x00008000
464#define SR_IBIT7 0x00004000
465#define SR_IBIT6 0x00002000
466#define SR_IBIT5 0x00001000
467#define SR_IBIT4 0x00000800
468#define SR_IBIT3 0x00000400
469#define SR_IBIT2 0x00000200
470#define SR_IBIT1 0x00000100
472#define SR_KUO 0x00000020
473#define SR_IEO 0x00000010
474#define SR_KUP 0x00000008
475#define SR_IEP 0x00000004
476#define SR_KUC 0x00000002
477#define SR_IEC 0x00000001
481#define SR_CUMASK 0xf0000000
482#define SR_CU3 0x80000000
483#define SR_CU2 0x40000000
484#define SR_CU1 0x20000000
485#define SR_CU0 0x10000000
487#define SR_RP 0x08000000
488#define SR_FR 0x04000000
489#define SR_RE 0x02000000
491#define SR_BEV 0x00400000
492#define SR_TS 0x00200000
493#define SR_SR 0x00100000
494#define SR_CH 0x00040000
495#define SR_CE 0x00020000
496#define SR_DE 0x00010000
502#define SR_IMASK 0x0000ff00
503#define SR_IMASK8 0x00000000
504#define SR_IMASK7 0x00008000
505#define SR_IMASK6 0x0000c000
506#define SR_IMASK5 0x0000e000
507#define SR_IMASK4 0x0000f000
508#define SR_IMASK3 0x0000f800
509#define SR_IMASK2 0x0000fc00
510#define SR_IMASK1 0x0000fe00
511#define SR_IMASK0 0x0000ff00
513#define SR_IMASKSHIFT 8
515#define SR_IBIT8 0x00008000
516#define SR_IBIT7 0x00004000
517#define SR_IBIT6 0x00002000
518#define SR_IBIT5 0x00001000
519#define SR_IBIT4 0x00000800
520#define SR_IBIT3 0x00000400
521#define SR_IBIT2 0x00000200
522#define SR_IBIT1 0x00000100
524#define SR_KSMASK 0x00000018
525#define SR_KSUSER 0x00000010
526#define SR_KSSUPER 0x00000008
527#define SR_KSKERNEL 0x00000000
528#define SR_ERL 0x00000004
529#define SR_EXL 0x00000002
530#define SR_IE 0x00000001
534#define SR_CUMASK 0xf0000000
535#define SR_CU3 0x80000000
536#define SR_CU2 0x40000000
537#define SR_CU1 0x20000000
538#define SR_CU0 0x10000000
540#define SR_RP 0x08000000
541#define SR_FR 0x04000000
542#define SR_RE 0x02000000
544#define SR_BEV 0x00400000
545#define SR_TS 0x00200000
546#define SR_SR 0x00100000
547#define SR_CH 0x00040000
548#define SR_CE 0x00020000
549#define SR_DE 0x00010000
555#define SR_IMASK 0x0000ff00
556#define SR_IMASK8 0x00000000
557#define SR_IMASK7 0x00008000
558#define SR_IMASK6 0x0000c000
559#define SR_IMASK5 0x0000e000
560#define SR_IMASK4 0x0000f000
561#define SR_IMASK3 0x0000f800
562#define SR_IMASK2 0x0000fc00
563#define SR_IMASK1 0x0000fe00
564#define SR_IMASK0 0x0000ff00
566#define SR_IMASKSHIFT 8
568#define SR_IBIT8 0x00008000
569#define SR_IBIT7 0x00004000
570#define SR_IBIT6 0x00002000
571#define SR_IBIT5 0x00001000
572#define SR_IBIT4 0x00000800
573#define SR_IBIT3 0x00000400
574#define SR_IBIT2 0x00000200
575#define SR_IBIT1 0x00000100
577#define SR_KSMASK 0x00000018
578#define SR_KSUSER 0x00000010
579#define SR_KSSUPER 0x00000008
580#define SR_KSKERNEL 0x00000000
581#define SR_ERL 0x00000004
582#define SR_EXL 0x00000002
583#define SR_IE 0x00000001
589#define CAUSE_BD 0x80000000
590#define CAUSE_BT 0x40000000
591#define CAUSE_CEMASK 0x30000000
592#define CAUSE_CESHIFT 28
595#define CAUSE_IPMASK 0x0000FF00
596#define CAUSE_IPSHIFT 8
598#define CAUSE_EXCMASK 0x0000003C
599#define CAUSE_EXCSHIFT 2
624#define C0_PAGEMASK $5
629#define C0_PAGEMASK $5
637#define C0_BADVADDR $8
649#define C0_COMPARE $11
653#define C0_COMPARE $11
668#define C0_WATCHLO $18
669#define C0_WATCHHI $19
672#define C0_CACHEERR $27
681#define C0_WATCHLO $18
682#define C0_WATCHHI $19
685#define C0_CACHEERR $27
692#define C1_REVISION $0