RTEMS 6.1-rc4
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grspw_router.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * GRSPW ROUTER APB-Register Driver.
5 *
6 * COPYRIGHT (c) 2010-2017.
7 * Cobham Gaisler AB.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __GRSPW_ROUTER_H__
32#define __GRSPW_ROUTER_H__
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38/* Maximum number of ROUTER devices supported by driver */
39#define ROUTER_MAX 2
40
41#define ROUTER_ERR_OK 0
42#define ROUTER_ERR_EINVAL -1
43#define ROUTER_ERR_ERROR -2
44#define ROUTER_ERR_TOOMANY -3
45#define ROUTER_ERR_IMPLEMENTED -4
46
47/* Hardware Information */
48struct router_hw_info {
49 uint8_t nports_spw;
50 uint8_t nports_amba;
51 uint8_t nports_fifo;
52 int8_t srouting;
53 int8_t pnp_enable;
54 int8_t timers_avail;
55 int8_t pnp_avail;
56 uint8_t ver_major;
57 uint8_t ver_minor;
58 uint8_t ver_patch;
59 uint8_t iid;
60
61 /* Router capabilities */
62 uint8_t amba_port_fifo_size;
63 uint8_t spw_port_fifo_size;
64 uint8_t rmap_maxdlen;
65 int8_t aux_async;
66 int8_t aux_dist_int_support;
67 int8_t dual_port_support;
68 int8_t dist_int_support;
69 int8_t spwd_support;
70 uint8_t pktcnt_support;
71 uint8_t charcnt_support;
72};
73
74#define ROUTER_FLG_CFG 0x01
75#define ROUTER_FLG_IID 0x02
76#define ROUTER_FLG_IDIV 0x04
77#define ROUTER_FLG_TPRES 0x08
78#define ROUTER_FLG_TRLD 0x10
79#define ROUTER_FLG_ALL 0x1f /* All Above Flags */
80
81struct router_config {
82 uint32_t flags; /* Determine what configuration should be updated */
83
84 /* Router Configuration Register */
85 uint32_t config;
86
87 /* Set Instance ID */
88 uint8_t iid;
89
90 /* SpaceWire Link Initialization Clock Divisor */
91 uint8_t idiv;
92
93 /* Timer Prescaler */
94 uint32_t timer_prescaler;
95};
96
97/* Routing table address control */
98struct router_route_acontrol {
99 uint32_t control[31];
100 uint32_t control_logical[224];
101};
102
103/* Routing table port mapping */
104struct router_route_portmap {
105 uint32_t pmap[31]; /* Port Setup for ports 1-31 */
106 uint32_t pmap_logical[224]; /* Port setup for locgical addresses 32-255 */
107};
108
109/* Routing table */
110#define ROUTER_ROUTE_FLG_MAP 0x01
111#define ROUTER_ROUTE_FLG_CTRL 0x02
112#define ROUTER_ROUTE_FLG_ALL 0x3 /* All Above Flags */
113struct router_routing_table {
114 uint32_t flags; /* Determine what configuration should be updated */
115
116 struct router_route_acontrol acontrol;
117 struct router_route_portmap portmap;
118};
119
120/* Set/Get Port Control/Status */
121#define ROUTER_PORT_FLG_SET_CTRL 0x01
122#define ROUTER_PORT_FLG_GET_CTRL 0x02
123#define ROUTER_PORT_FLG_SET_STS 0x04
124#define ROUTER_PORT_FLG_GET_STS 0x08
125#define ROUTER_PORT_FLG_SET_CTRL2 0x10
126#define ROUTER_PORT_FLG_GET_CTRL2 0x20
127#define ROUTER_PORT_FLG_SET_TIMER 0x40
128#define ROUTER_PORT_FLG_GET_TIMER 0x80
129#define ROUTER_PORT_FLG_SET_PKTLEN 0x100
130#define ROUTER_PORT_FLG_GET_PKTLEN 0x200
131struct router_port {
132 uint32_t flag;
133 /* Port control */
134 uint32_t ctrl;
135 /* Port status */
136 uint32_t sts;
137 /* Port control 2 */
138 uint32_t ctrl2;
139 /* Timer Reload */
140 uint32_t timer_reload;
141 /* Maximum packet length */
142 uint32_t packet_length;
143};
144
145/* Register GRSPW Router driver to Driver Manager */
146void router_register_drv(void);
147
148extern void *router_open(unsigned int dev_no);
149extern int router_close(void *d);
150extern int router_print(void *d);
151extern int router_hwinfo_get(void *d, struct router_hw_info *hwinfo);
152
153/* Router general config */
154extern int router_config_set(void *d, struct router_config *cfg);
155extern int router_config_get(void *d, struct router_config *cfg);
156
157/* Routing table config */
158extern int router_routing_table_set(void *d,
159 struct router_routing_table *cfg);
160extern int router_routing_table_get(void *d,
161 struct router_routing_table *cfg);
162
163/*
164 * ROUTER PCTRL register fields
165 */
166#define PCTRL_RD (0xff << PCTRL_RD_BIT)
167#define PCTRL_ST (0x1 << PCTRL_ST_BIT)
168#define PCTRL_SR (0x1 << PCTRL_SR_BIT)
169#define PCTRL_AD (0x1 << PCTRL_AD_BIT)
170#define PCTRL_LR (0x1 << PCTRL_LR_BIT)
171#define PCTRL_PL (0x1 << PCTRL_PL_BIT)
172#define PCTRL_TS (0x1 << PCTRL_TS_BIT)
173#define PCTRL_IC (0x1 << PCTRL_IC_BIT)
174#define PCTRL_ET (0x1 << PCTRL_ET_BIT)
175#define PCTRL_NP (0x1 << PCTRL_NP_BIT)
176#define PCTRL_PS (0x1 << PCTRL_PS_BIT)
177#define PCTRL_BE (0x1 << PCTRL_BE_BIT)
178#define PCTRL_DI (0x1 << PCTRL_DI_BIT)
179#define PCTRL_TR (0x1 << PCTRL_TR_BIT)
180#define PCTRL_PR (0x1 << PCTRL_PR_BIT)
181#define PCTRL_TF (0x1 << PCTRL_TF_BIT)
182#define PCTRL_RS (0x1 << PCTRL_RS_BIT)
183#define PCTRL_TE (0x1 << PCTRL_TE_BIT)
184#define PCTRL_CE (0x1 << PCTRL_CE_BIT)
185#define PCTRL_AS (0x1 << PCTRL_AS_BIT)
186#define PCTRL_LS (0x1 << PCTRL_LS_BIT)
187#define PCTRL_LD (0x1 << PCTRL_LD_BIT)
188
189#define PCTRL_RD_BIT 24
190#define PCTRL_ST_BIT 21
191#define PCTRL_SR_BIT 20
192#define PCTRL_AD_BIT 19
193#define PCTRL_LR_BIT 18
194#define PCTRL_PL_BIT 17
195#define PCTRL_TS_BIT 16
196#define PCTRL_IC_BIT 15
197#define PCTRL_ET_BIT 14
198#define PCTRL_NP_BIT 13
199#define PCTRL_PS_BIT 12
200#define PCTRL_BE_BIT 11
201#define PCTRL_DI_BIT 10
202#define PCTRL_TR_BIT 9
203#define PCTRL_PR_BIT 8
204#define PCTRL_TF_BIT 7
205#define PCTRL_RS_BIT 6
206#define PCTRL_TE_BIT 5
207#define PCTRL_CE_BIT 3
208#define PCTRL_AS_BIT 2
209#define PCTRL_LS_BIT 1
210#define PCTRL_LD_BIT 0
211
212/*
213 * ROUTER PCTRL2 register fields
214 */
215#define PCTRL2_SM (0xff << PCTRL2_SM_BIT)
216#define PCTRL2_SV (0xff << PCTRL2_SV_BIT)
217#define PCTRL2_OR (0x1 << PCTRL2_OR_BIT)
218#define PCTRL2_UR (0x1 << PCTRL2_UR_BIT)
219#define PCTRL2_AT (0x1 << PCTRL2_AT_BIT)
220#define PCTRL2_AR (0x1 << PCTRL2_AR_BIT)
221#define PCTRL2_IT (0x1 << PCTRL2_IT_BIT)
222#define PCTRL2_IR (0x1 << PCTRL2_IR_BIT)
223#define PCTRL2_SD (0x1f << PCTRL2_SD_BIT)
224#define PCTRL2_SC (0x1f << PCTRL2_SC_BIT)
225
226#define PCTRL2_SM_BIT 24
227#define PCTRL2_SV_BIT 16
228#define PCTRL2_OR_BIT 15
229#define PCTRL2_UR_BIT 14
230#define PCTRL2_AT_BIT 12
231#define PCTRL2_AR_BIT 11
232#define PCTRL2_IT_BIT 10
233#define PCTRL2_IR_BIT 9
234#define PCTRL2_SD_BIT 1
235#define PCTRL2_SC_BIT 0
236
237/* Router Set/Get Port configuration */
238extern int router_port_ioc(void *d, int port, struct router_port *cfg);
239
240/* Read-modify-write Port Control register */
241extern int router_port_ctrl_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value);
242/* Read-modify-write Port Control2 register */
243extern int router_port_ctrl2_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value);
244/* Read Port Control register */
245extern int router_port_ctrl_get(void *d, int port, uint32_t *ctrl);
246/* Read Port Control2 register */
247extern int router_port_ctrl2_get(void *d, int port, uint32_t *ctrl2);
248/* Write Port Control Register */
249extern int router_port_ctrl_set(void *d, int port, uint32_t mask, uint32_t ctrl);
250/* Write Port Control2 Register */
251extern int router_port_ctrl2_set(void *d, int port, uint32_t mask, uint32_t ctrl2);
252/* Set Timer Reload Value for a specific port */
253extern int router_port_treload_set(void *d, int port, uint32_t reload);
254/* Get Timer Reload Value for a specific port */
255extern int router_port_treload_get(void *d, int port, uint32_t *reload);
256/* Get Maximum packet length for a specific port */
257extern int router_port_maxplen_get(void *d, int port, uint32_t *length);
258/* Set Maximum packet length for a specific port */
259extern int router_port_maxplen_set(void *d, int port, uint32_t length);
260
261/*
262 * ROUTER PSTSCFG register fields
263 */
264#define PSTSCFG_EO (0x1 << PSTSCFG_EO_BIT)
265#define PSTSCFG_EE (0x1 << PSTSCFG_EE_BIT)
266#define PSTSCFG_PL (0x1 << PSTSCFG_PL_BIT)
267#define PSTSCFG_TT (0x1 << PSTSCFG_TT_BIT)
268#define PSTSCFG_PT (0x1 << PSTSCFG_PT_BIT)
269#define PSTSCFG_HC (0x1 << PSTSCFG_HC_BIT)
270#define PSTSCFG_PI (0x1 << PSTSCFG_PI_BIT)
271#define PSTSCFG_CE (0x1 << PSTSCFG_CE_BIT)
272#define PSTSCFG_EC (0xf << PSTSCFG_EC_BIT)
273#define PSTSCFG_TS (0x1 << PSTSCFG_TS_BIT)
274#define PSTSCFG_ME (0x1 << PSTSCFG_ME_BIT)
275#define PSTSCFG_IP (0x1f << PSTSCFG_IP_BIT)
276#define PSTSCFG_CP (0x1 << PSTSCFG_CP_BIT)
277#define PSTSCFG_PC (0xf << PSTSCFG_PC_BIT)
278#define PSTSCFG_WCLEAR (PSTSCFG_EO | PSTSCFG_EE | PSTSCFG_PL | \
279 PSTSCFG_TT | PSTSCFG_PT | PSTSCFG_HC | \
280 PSTSCFG_PI | PSTSCFG_CE | PSTSCFG_TS | \
281 PSTSCFG_ME | PSTSCFG_CP)
282#define PSTSCFG_WCLEAR2 (PSTSCFG_CE | PSTSCFG_CP)
283
284#define PSTSCFG_EO_BIT 31
285#define PSTSCFG_EE_BIT 30
286#define PSTSCFG_PL_BIT 29
287#define PSTSCFG_TT_BIT 28
288#define PSTSCFG_PT_BIT 27
289#define PSTSCFG_HC_BIT 26
290#define PSTSCFG_PI_BIT 25
291#define PSTSCFG_CE_BIT 24
292#define PSTSCFG_EC_BIT 20
293#define PSTSCFG_TS_BIT 18
294#define PSTSCFG_ME_BIT 17
295#define PSTSCFG_IP_BIT 7
296#define PSTSCFG_CP_BIT 4
297#define PSTSCFG_PC_BIT 0
298
299/*
300 * ROUTER PSTS register fields
301 */
302#define PSTS_PT (0x3 << PSTS_PT_BIT)
303#define PSTS_PL (0x1 << PSTS_PL_BIT)
304#define PSTS_TT (0x1 << PSTS_TT_BIT)
305#define PSTS_RS (0x1 << PSTS_RS_BIT)
306#define PSTS_SR (0x1 << PSTS_SR_BIT)
307#define PSTS_LR (0x1 << PSTS_LR_BIT)
308#define PSTS_SP (0x1 << PSTS_SP_BIT)
309#define PSTS_AC (0x1 << PSTS_AC_BIT)
310#define PSTS_TS (0x1 << PSTS_TS_BIT)
311#define PSTS_ME (0x1 << PSTS_ME_BIT)
312#define PSTS_TF (0x1 << PSTS_TF_BIT)
313#define PSTS_RE (0x1 << PSTS_RE_BIT)
314#define PSTS_LS (0x7 << PSTS_LS_BIT)
315#define PSTS_IP (0x1f << PSTS_IP_BIT)
316#define PSTS_PR (0x1 << PSTS_PR_BIT)
317#define PSTS_PB (0x1 << PSTS_PB_BIT)
318#define PSTS_IA (0x1 << PSTS_IA_BIT)
319#define PSTS_CE (0x1 << PSTS_CE_BIT)
320#define PSTS_ER (0x1 << PSTS_ER_BIT)
321#define PSTS_DE (0x1 << PSTS_DE_BIT)
322#define PSTS_PE (0x1 << PSTS_PE_BIT)
323#define PSTS_WCLEAR (PSTS_PL | PSTS_TT | PSTS_RS | PSTS_SR | \
324 PSTS_TS | PSTS_ME | PSTS_IA | PSTS_CE | \
325 PSTS_ER | PSTS_DE | PSTS_PE)
326
327#define PSTS_PT_BIT 30
328#define PSTS_PL_BIT 29
329#define PSTS_TT_BIT 28
330#define PSTS_RS_BIT 27
331#define PSTS_SR_BIT 26
332#define PSTS_LR_BIT 22
333#define PSTS_SP_BIT 21
334#define PSTS_AC_BIT 20
335#define PSTS_TS_BIT 18
336#define PSTS_ME_BIT 17
337#define PSTS_TF_BIT 16
338#define PSTS_RE_BIT 15
339#define PSTS_LS_BIT 12
340#define PSTS_IP_BIT 7
341#define PSTS_PR_BIT 6
342#define PSTS_PB_BIT 5
343#define PSTS_IA_BIT 4
344#define PSTS_CE_BIT 3
345#define PSTS_ER_BIT 2
346#define PSTS_DE_BIT 1
347#define PSTS_PE_BIT 0
348
349/* Check Port Status register and clear errors if there are */
350extern int router_port_status(void *d, int port, uint32_t *sts, uint32_t clrmsk);
351
352#define ROUTER_LINK_STATUS_ERROR_RESET 0
353#define ROUTER_LINK_STATUS_ERROR_WAIT 1
354#define ROUTER_LINK_STATUS_READY 2
355#define ROUTER_LINK_STATUS_STARTED 3
356#define ROUTER_LINK_STATUS_CONNECTING 4
357#define ROUTER_LINK_STATUS_RUN_STATE 5
358/* Get Link status */
359extern int router_port_link_status(void *d, int port);
360/* Operate a Link */
361extern int router_port_enable(void *d, int port);
362extern int router_port_disable(void *d, int port);
363extern int router_port_link_stop(void *d, int port);
364extern int router_port_link_start(void *d, int port);
365extern int router_port_link_div(void *d, int port, int rundiv);
366extern int router_port_link_receive_spill(void *d, int port);
367extern int router_port_link_transmit_reset(void *d, int port);
368
369/* Get port credit counter register */
370extern int router_port_cred_get(void *d, int port, uint32_t *cred);
371
372/*
373 * ROUTER RTACTRL register fields
374 */
375#define RTACTRL_SR (0x1 << RTACTRL_SR_BIT)
376#define RTACTRL_EN (0x1 << RTACTRL_EN_BIT)
377#define RTACTRL_PR (0x1 << RTACTRL_PR_BIT)
378#define RTACTRL_HD (0x1 << RTACTRL_HD_BIT)
379
380#define RTACTRL_SR_BIT 3
381#define RTACTRL_EN_BIT 2
382#define RTACTRL_PR_BIT 1
383#define RTACTRL_HD_BIT 0
384
385/* Individual route modification */
386#define ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE (0x1 << 16)
387#define ROUTER_ROUTE_PACKETDISTRIBUTION_DISABLE (0x0 << 16)
388#define ROUTER_ROUTE_SPILLIFNOTREADY_ENABLE RTACTRL_SR
389#define ROUTER_ROUTE_SPILLIFNOTREADY_DISABLE 0
390#define ROUTER_ROUTE_ENABLE RTACTRL_EN
391#define ROUTER_ROUTE_DISABLE 0
392#define ROUTER_ROUTE_PRIORITY_HIGH RTACTRL_PR
393#define ROUTER_ROUTE_PRIORITY_LOW 0
394#define ROUTER_ROUTE_HEADERDELETION_ENABLE RTACTRL_HD
395#define ROUTER_ROUTE_HEADERDELETION_DISABLE 0
396struct router_route {
397 uint8_t from_address;
398 uint8_t to_port[32];
399 int count;
400 int options;
401};
402extern int router_route_set(void *d, struct router_route *route);
403extern int router_route_get(void *d, struct router_route *route);
404
405/* Router configuration port write enable */
406extern int router_write_enable(void *d);
407extern int router_write_disable(void *d);
408
409/* Router reset */
410extern int router_reset(void *d);
411
412/* Set Instance ID */
413extern int router_instance_set(void *d, uint8_t iid);
414/* Get Instance ID */
415extern int router_instance_get(void *d, uint8_t *iid);
416
417/* Set SpaceWire Link Initialization Clock Divisor */
418extern int router_idiv_set(void *d, uint8_t idiv);
419/* Get SpaceWire Link Initialization Clock Divisor */
420extern int router_idiv_get(void *d, uint8_t *idiv);
421
422/* Set Timer Prescaler */
423extern int router_tpresc_set(void *d, uint32_t prescaler);
424/* Get Timer Prescaler */
425extern int router_tpresc_get(void *d, uint32_t *prescaler);
426
427/* Set/get Router configuration */
428extern int router_cfgsts_set(void *d, uint32_t cfgsts);
429extern int router_cfgsts_get(void *d, uint32_t *cfgsts);
430
431/* Router timecode */
432extern int router_tc_enable(void *d);
433extern int router_tc_disable(void *d);
434extern int router_tc_reset(void *d);
435extern int router_tc_get(void *d);
436
437/* Router Interrupts */
438/*
439 * ROUTER IMASK register fields
440 */
441#define IMASK_PE (0x1 << IMASK_PE_BIT)
442#define IMASK_SR (0x1 << IMASK_SR_BIT)
443#define IMASK_RS (0x1 << IMASK_RS_BIT)
444#define IMASK_TT (0x1 << IMASK_TT_BIT)
445#define IMASK_PL (0x1 << IMASK_PL_BIT)
446#define IMASK_TS (0x1 << IMASK_TS_BIT)
447#define IMASK_AC (0x1 << IMASK_AC_BIT)
448#define IMASK_RE (0x1 << IMASK_RE_BIT)
449#define IMASK_IA (0x1 << IMASK_IA_BIT)
450#define IMASK_LE (0x1 << IMASK_LE_BIT)
451#define IMASK_ME (0x1 << IMASK_ME_BIT)
452#define IMASK_ALL ( IMASK_PE | IMASK_SR | IMASK_RS | IMASK_TT \
453 IMASK_PL | IMASK_TS | IMASK_AC | IMASK_RE | IMASK_IA \
454 IMASK_LE | IMASK_ME)
455
456#define IMASK_PE_BIT 10
457#define IMASK_SR_BIT 9
458#define IMASK_RS_BIT 8
459#define IMASK_TT_BIT 7
460#define IMASK_PL_BIT 6
461#define IMASK_TS_BIT 5
462#define IMASK_AC_BIT 4
463#define IMASK_RE_BIT 3
464#define IMASK_IA_BIT 2
465#define IMASK_LE_BIT 1
466#define IMASK_ME_BIT 0
467
468#define ROUTER_INTERRUPT_ALL IMASK_ALL
469#define ROUTER_INTERRUPT_SPWPNP_ERROR IMASK_PE
470#define ROUTER_INTERRUPT_SPILLED IMASK_SR
471#define ROUTER_INTERRUPT_RUNSTATE IMASK_RS
472#define ROUTER_INTERRUPT_TC_TRUNCATION IMASK_TT
473#define ROUTER_INTERRUPT_PACKET_TRUNCATION IMASK_PL
474#define ROUTER_INTERRUPT_TIMEOUT IMASK_TS
475#define ROUTER_INTERRUPT_CFGPORT IMASK_AC
476#define ROUTER_INTERRUPT_RMAP_ERROR IMASK_RE
477#define ROUTER_INTERRUPT_INVALID_ADDRESS IMASK_IA
478#define ROUTER_INTERRUPT_LINK_ERROR IMASK_LE
479#define ROUTER_INTERRUPT_MEMORY_ERROR IMASK_ME
480extern int router_port_interrupt_unmask(void *d, int port);
481extern int router_port_interrupt_mask(void *d, int port);
482extern int router_interrupt_unmask(void *d, int options);
483extern int router_interrupt_mask(void *d, int options);
484
485/* Router Interrupt code generation */
486/*
487 * ROUTER ICODEGEN register fields
488 */
489#define ICODEGEN_UA (0x1 << ICODEGEN_UA_BIT)
490#define ICODEGEN_AH (0x1 << ICODEGEN_AH_BIT)
491#define ICODEGEN_IT (0x1 << ICODEGEN_IT_BIT)
492#define ICODEGEN_TE (0x1 << ICODEGEN_TE_BIT)
493#define ICODEGEN_EN (0x1 << ICODEGEN_EN_BIT)
494#define ICODEGEN_IN (0x1f << ICODEGEN_IN_BIT)
495
496#define ICODEGEN_UA_BIT 20
497#define ICODEGEN_AH_BIT 19
498#define ICODEGEN_IT_BIT 18
499#define ICODEGEN_TE_BIT 17
500#define ICODEGEN_EN_BIT 16
501#define ICODEGEN_IN_BIT 0
502
503#define ROUTER_ICODEGEN_ITYPE_EDGE ICODEGEN_IT
504#define ROUTER_ICODEGEN_ITYPE_LEVEL 0
505#define ROUTER_ICODEGEN_AUTOUNACK_ENABLE ICODEGEN_UA
506#define ROUTER_ICODEGEN_AUTOUNACK_DISABLE 0
507#define ROUTER_ICODEGEN_AUTOACK_ENABLE ICODEGEN_AH
508#define ROUTER_ICODEGEN_AUTOACK_DISABLE 0
509extern int router_icodegen_enable(void *d, uint8_t intn, uint32_t aitimer,
510 int options);
511extern int router_icodegen_disable(void *d);
512
513/* Router interrupt change timers */
514extern int router_isrctimer_set(void *d, uint32_t reloadvalue);
515extern int router_isrctimer_get(void *d, uint32_t *reloadvalue);
516
517/* Router interrupt timers */
518extern int router_isrtimer_set(void *d, uint32_t reloadvalue);
519extern int router_isrtimer_get(void *d, uint32_t *reloadvalue);
520
521#ifdef __cplusplus
522}
523#endif
524
525#endif
config_s
Definition: deflate.c:114
control
Definition: intercom.c:87
router_config
Definition: grspw_router.h:81
router_hw_info
Definition: grspw_router.h:48
router_port
Definition: grspw_router.h:131
router_route_acontrol
Definition: grspw_router.h:98
router_route_portmap
Definition: grspw_router.h:104
router_route
Definition: grspw_router.h:396
router_routing_table
Definition: grspw_router.h:113
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