RTEMS 6.1-rc4
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grpci2-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * This file is part of the RTEMS quality process and was automatically
38 * generated. If you find something that needs to be fixed or
39 * worded better please post a report or patch to an RTEMS mailing list
40 * or raise a bug report:
41 *
42 * https://www.rtems.org/bugs.html
43 *
44 * For information on updating and regenerating please refer to the How-To
45 * section in the Software Requirements Engineering chapter of the
46 * RTEMS Software Engineering manual. The manual is provided as a part of
47 * a release. For development sources please refer to the online
48 * documentation at:
49 *
50 * https://docs.rtems.org
51 */
52
53/* Generated from spec:/dev/grlib/if/grpci2-header */
54
55#ifndef _GRLIB_GRPCI2_REGS_H
56#define _GRLIB_GRPCI2_REGS_H
57
58#include <stdint.h>
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64/* Generated from spec:/dev/grlib/if/grpci2 */
65
84#define GRPCI2_CTRL_RE 0x80000000U
85
86#define GRPCI2_CTRL_MR 0x40000000U
87
88#define GRPCI2_CTRL_TR 0x20000000U
89
90#define GRPCI2_CTRL_SI 0x8000000U
91
92#define GRPCI2_CTRL_PE 0x4000000U
93
94#define GRPCI2_CTRL_ER 0x2000000U
95
96#define GRPCI2_CTRL_EI 0x1000000U
97
98#define GRPCI2_CTRL_BUS_NUMBER_SHIFT 16
99#define GRPCI2_CTRL_BUS_NUMBER_MASK 0xff0000U
100#define GRPCI2_CTRL_BUS_NUMBER_GET( _reg ) \
101 ( ( ( _reg ) & GRPCI2_CTRL_BUS_NUMBER_MASK ) >> \
102 GRPCI2_CTRL_BUS_NUMBER_SHIFT )
103#define GRPCI2_CTRL_BUS_NUMBER_SET( _reg, _val ) \
104 ( ( ( _reg ) & ~GRPCI2_CTRL_BUS_NUMBER_MASK ) | \
105 ( ( ( _val ) << GRPCI2_CTRL_BUS_NUMBER_SHIFT ) & \
106 GRPCI2_CTRL_BUS_NUMBER_MASK ) )
107#define GRPCI2_CTRL_BUS_NUMBER( _val ) \
108 ( ( ( _val ) << GRPCI2_CTRL_BUS_NUMBER_SHIFT ) & \
109 GRPCI2_CTRL_BUS_NUMBER_MASK )
110
111#define GRPCI2_CTRL_DFA 0x800U
112
113#define GRPCI2_CTRL_IB 0x400U
114
115#define GRPCI2_CTRL_CB 0x200U
116
117#define GRPCI2_CTRL_DIF 0x100U
118
119#define GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT 4
120#define GRPCI2_CTRL_DEVICE_INT_MASK_MASK 0xf0U
121#define GRPCI2_CTRL_DEVICE_INT_MASK_GET( _reg ) \
122 ( ( ( _reg ) & GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) >> \
123 GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT )
124#define GRPCI2_CTRL_DEVICE_INT_MASK_SET( _reg, _val ) \
125 ( ( ( _reg ) & ~GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) | \
126 ( ( ( _val ) << GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT ) & \
127 GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) )
128#define GRPCI2_CTRL_DEVICE_INT_MASK( _val ) \
129 ( ( ( _val ) << GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT ) & \
130 GRPCI2_CTRL_DEVICE_INT_MASK_MASK )
131
132#define GRPCI2_CTRL_HOST_INT_MASK_SHIFT 0
133#define GRPCI2_CTRL_HOST_INT_MASK_MASK 0xfU
134#define GRPCI2_CTRL_HOST_INT_MASK_GET( _reg ) \
135 ( ( ( _reg ) & GRPCI2_CTRL_HOST_INT_MASK_MASK ) >> \
136 GRPCI2_CTRL_HOST_INT_MASK_SHIFT )
137#define GRPCI2_CTRL_HOST_INT_MASK_SET( _reg, _val ) \
138 ( ( ( _reg ) & ~GRPCI2_CTRL_HOST_INT_MASK_MASK ) | \
139 ( ( ( _val ) << GRPCI2_CTRL_HOST_INT_MASK_SHIFT ) & \
140 GRPCI2_CTRL_HOST_INT_MASK_MASK ) )
141#define GRPCI2_CTRL_HOST_INT_MASK( _val ) \
142 ( ( ( _val ) << GRPCI2_CTRL_HOST_INT_MASK_SHIFT ) & \
143 GRPCI2_CTRL_HOST_INT_MASK_MASK )
144
155#define GRPCI2_STATCAP_HOST 0x80000000U
156
157#define GRPCI2_STATCAP_MST 0x40000000U
158
159#define GRPCI2_STATCAP_TAR 0x20000000U
160
161#define GRPCI2_STATCAP_DMA 0x10000000U
162
163#define GRPCI2_STATCAP_DI 0x8000000U
164
165#define GRPCI2_STATCAP_HI 0x4000000U
166
167#define GRPCI2_STATCAP_IRQ_MODE_SHIFT 24
168#define GRPCI2_STATCAP_IRQ_MODE_MASK 0x3000000U
169#define GRPCI2_STATCAP_IRQ_MODE_GET( _reg ) \
170 ( ( ( _reg ) & GRPCI2_STATCAP_IRQ_MODE_MASK ) >> \
171 GRPCI2_STATCAP_IRQ_MODE_SHIFT )
172#define GRPCI2_STATCAP_IRQ_MODE_SET( _reg, _val ) \
173 ( ( ( _reg ) & ~GRPCI2_STATCAP_IRQ_MODE_MASK ) | \
174 ( ( ( _val ) << GRPCI2_STATCAP_IRQ_MODE_SHIFT ) & \
175 GRPCI2_STATCAP_IRQ_MODE_MASK ) )
176#define GRPCI2_STATCAP_IRQ_MODE( _val ) \
177 ( ( ( _val ) << GRPCI2_STATCAP_IRQ_MODE_SHIFT ) & \
178 GRPCI2_STATCAP_IRQ_MODE_MASK )
179
180#define GRPCI2_STATCAP_TRACE 0x800000U
181
182#define GRPCI2_STATCAP_CFGDO 0x100000U
183
184#define GRPCI2_STATCAP_CFGER 0x80000U
185
186#define GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT 12
187#define GRPCI2_STATCAP_CORE_INT_STATUS_MASK 0x7f000U
188#define GRPCI2_STATCAP_CORE_INT_STATUS_GET( _reg ) \
189 ( ( ( _reg ) & GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) >> \
190 GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT )
191#define GRPCI2_STATCAP_CORE_INT_STATUS_SET( _reg, _val ) \
192 ( ( ( _reg ) & ~GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) | \
193 ( ( ( _val ) << GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT ) & \
194 GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) )
195#define GRPCI2_STATCAP_CORE_INT_STATUS( _val ) \
196 ( ( ( _val ) << GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT ) & \
197 GRPCI2_STATCAP_CORE_INT_STATUS_MASK )
198
199#define GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT 8
200#define GRPCI2_STATCAP_HOST_INT_STATUS_MASK 0xf00U
201#define GRPCI2_STATCAP_HOST_INT_STATUS_GET( _reg ) \
202 ( ( ( _reg ) & GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) >> \
203 GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT )
204#define GRPCI2_STATCAP_HOST_INT_STATUS_SET( _reg, _val ) \
205 ( ( ( _reg ) & ~GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) | \
206 ( ( ( _val ) << GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT ) & \
207 GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) )
208#define GRPCI2_STATCAP_HOST_INT_STATUS( _val ) \
209 ( ( ( _val ) << GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT ) & \
210 GRPCI2_STATCAP_HOST_INT_STATUS_MASK )
211
212#define GRPCI2_STATCAP_FDEPTH_SHIFT 2
213#define GRPCI2_STATCAP_FDEPTH_MASK 0x1cU
214#define GRPCI2_STATCAP_FDEPTH_GET( _reg ) \
215 ( ( ( _reg ) & GRPCI2_STATCAP_FDEPTH_MASK ) >> \
216 GRPCI2_STATCAP_FDEPTH_SHIFT )
217#define GRPCI2_STATCAP_FDEPTH_SET( _reg, _val ) \
218 ( ( ( _reg ) & ~GRPCI2_STATCAP_FDEPTH_MASK ) | \
219 ( ( ( _val ) << GRPCI2_STATCAP_FDEPTH_SHIFT ) & \
220 GRPCI2_STATCAP_FDEPTH_MASK ) )
221#define GRPCI2_STATCAP_FDEPTH( _val ) \
222 ( ( ( _val ) << GRPCI2_STATCAP_FDEPTH_SHIFT ) & \
223 GRPCI2_STATCAP_FDEPTH_MASK )
224
225#define GRPCI2_STATCAP_FNUM_SHIFT 0
226#define GRPCI2_STATCAP_FNUM_MASK 0x3U
227#define GRPCI2_STATCAP_FNUM_GET( _reg ) \
228 ( ( ( _reg ) & GRPCI2_STATCAP_FNUM_MASK ) >> \
229 GRPCI2_STATCAP_FNUM_SHIFT )
230#define GRPCI2_STATCAP_FNUM_SET( _reg, _val ) \
231 ( ( ( _reg ) & ~GRPCI2_STATCAP_FNUM_MASK ) | \
232 ( ( ( _val ) << GRPCI2_STATCAP_FNUM_SHIFT ) & \
233 GRPCI2_STATCAP_FNUM_MASK ) )
234#define GRPCI2_STATCAP_FNUM( _val ) \
235 ( ( ( _val ) << GRPCI2_STATCAP_FNUM_SHIFT ) & \
236 GRPCI2_STATCAP_FNUM_MASK )
237
248#define GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT 16
249#define GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK 0xffff0000U
250#define GRPCI2_BCIM_AHB_MASTER_UNMASK_GET( _reg ) \
251 ( ( ( _reg ) & GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) >> \
252 GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT )
253#define GRPCI2_BCIM_AHB_MASTER_UNMASK_SET( _reg, _val ) \
254 ( ( ( _reg ) & ~GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) | \
255 ( ( ( _val ) << GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT ) & \
256 GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) )
257#define GRPCI2_BCIM_AHB_MASTER_UNMASK( _val ) \
258 ( ( ( _val ) << GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT ) & \
259 GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK )
260
261#define GRPCI2_BCIM_BURST_LENGTH_SHIFT 0
262#define GRPCI2_BCIM_BURST_LENGTH_MASK 0xffU
263#define GRPCI2_BCIM_BURST_LENGTH_GET( _reg ) \
264 ( ( ( _reg ) & GRPCI2_BCIM_BURST_LENGTH_MASK ) >> \
265 GRPCI2_BCIM_BURST_LENGTH_SHIFT )
266#define GRPCI2_BCIM_BURST_LENGTH_SET( _reg, _val ) \
267 ( ( ( _reg ) & ~GRPCI2_BCIM_BURST_LENGTH_MASK ) | \
268 ( ( ( _val ) << GRPCI2_BCIM_BURST_LENGTH_SHIFT ) & \
269 GRPCI2_BCIM_BURST_LENGTH_MASK ) )
270#define GRPCI2_BCIM_BURST_LENGTH( _val ) \
271 ( ( ( _val ) << GRPCI2_BCIM_BURST_LENGTH_SHIFT ) & \
272 GRPCI2_BCIM_BURST_LENGTH_MASK )
273
284#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT 16
285#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK 0xffff0000U
286#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_GET( _reg ) \
287 ( ( ( _reg ) & GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) >> \
288 GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT )
289#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SET( _reg, _val ) \
290 ( ( ( _reg ) & ~GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) | \
291 ( ( ( _val ) << GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT ) & \
292 GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) )
293#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO( _val ) \
294 ( ( ( _val ) << GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT ) & \
295 GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK )
296
307#define GRPCI2_DMACTRL_SAFE 0x80000000U
308
309#define GRPCI2_DMACTRL_CHIRQ_SHIFT 12
310#define GRPCI2_DMACTRL_CHIRQ_MASK 0xff000U
311#define GRPCI2_DMACTRL_CHIRQ_GET( _reg ) \
312 ( ( ( _reg ) & GRPCI2_DMACTRL_CHIRQ_MASK ) >> \
313 GRPCI2_DMACTRL_CHIRQ_SHIFT )
314#define GRPCI2_DMACTRL_CHIRQ_SET( _reg, _val ) \
315 ( ( ( _reg ) & ~GRPCI2_DMACTRL_CHIRQ_MASK ) | \
316 ( ( ( _val ) << GRPCI2_DMACTRL_CHIRQ_SHIFT ) & \
317 GRPCI2_DMACTRL_CHIRQ_MASK ) )
318#define GRPCI2_DMACTRL_CHIRQ( _val ) \
319 ( ( ( _val ) << GRPCI2_DMACTRL_CHIRQ_SHIFT ) & \
320 GRPCI2_DMACTRL_CHIRQ_MASK )
321
322#define GRPCI2_DMACTRL_MA 0x800U
323
324#define GRPCI2_DMACTRL_TA 0x400U
325
326#define GRPCI2_DMACTRL_PE 0x200U
327
328#define GRPCI2_DMACTRL_AE 0x100U
329
330#define GRPCI2_DMACTRL_DE 0x80U
331
332#define GRPCI2_DMACTRL_NUMCH_SHIFT 4
333#define GRPCI2_DMACTRL_NUMCH_MASK 0x70U
334#define GRPCI2_DMACTRL_NUMCH_GET( _reg ) \
335 ( ( ( _reg ) & GRPCI2_DMACTRL_NUMCH_MASK ) >> \
336 GRPCI2_DMACTRL_NUMCH_SHIFT )
337#define GRPCI2_DMACTRL_NUMCH_SET( _reg, _val ) \
338 ( ( ( _reg ) & ~GRPCI2_DMACTRL_NUMCH_MASK ) | \
339 ( ( ( _val ) << GRPCI2_DMACTRL_NUMCH_SHIFT ) & \
340 GRPCI2_DMACTRL_NUMCH_MASK ) )
341#define GRPCI2_DMACTRL_NUMCH( _val ) \
342 ( ( ( _val ) << GRPCI2_DMACTRL_NUMCH_SHIFT ) & \
343 GRPCI2_DMACTRL_NUMCH_MASK )
344
345#define GRPCI2_DMACTRL_ACTIVE 0x8U
346
347#define GRPCI2_DMACTRL_DIS 0x4U
348
349#define GRPCI2_DMACTRL_IE 0x2U
350
351#define GRPCI2_DMACTRL_EN 0x1U
352
364#define GRPCI2_DMABASE_BASE_SHIFT 0
365#define GRPCI2_DMABASE_BASE_MASK 0xffffffffU
366#define GRPCI2_DMABASE_BASE_GET( _reg ) \
367 ( ( ( _reg ) & GRPCI2_DMABASE_BASE_MASK ) >> \
368 GRPCI2_DMABASE_BASE_SHIFT )
369#define GRPCI2_DMABASE_BASE_SET( _reg, _val ) \
370 ( ( ( _reg ) & ~GRPCI2_DMABASE_BASE_MASK ) | \
371 ( ( ( _val ) << GRPCI2_DMABASE_BASE_SHIFT ) & \
372 GRPCI2_DMABASE_BASE_MASK ) )
373#define GRPCI2_DMABASE_BASE( _val ) \
374 ( ( ( _val ) << GRPCI2_DMABASE_BASE_SHIFT ) & \
375 GRPCI2_DMABASE_BASE_MASK )
376
387#define GRPCI2_DMACHAN_CHAN_SHIFT 0
388#define GRPCI2_DMACHAN_CHAN_MASK 0xffffffffU
389#define GRPCI2_DMACHAN_CHAN_GET( _reg ) \
390 ( ( ( _reg ) & GRPCI2_DMACHAN_CHAN_MASK ) >> \
391 GRPCI2_DMACHAN_CHAN_SHIFT )
392#define GRPCI2_DMACHAN_CHAN_SET( _reg, _val ) \
393 ( ( ( _reg ) & ~GRPCI2_DMACHAN_CHAN_MASK ) | \
394 ( ( ( _val ) << GRPCI2_DMACHAN_CHAN_SHIFT ) & \
395 GRPCI2_DMACHAN_CHAN_MASK ) )
396#define GRPCI2_DMACHAN_CHAN( _val ) \
397 ( ( ( _val ) << GRPCI2_DMACHAN_CHAN_SHIFT ) & \
398 GRPCI2_DMACHAN_CHAN_MASK )
399
411#define GRPCI2_PCI2AHB_ADDR_SHIFT 0
412#define GRPCI2_PCI2AHB_ADDR_MASK 0xffffffffU
413#define GRPCI2_PCI2AHB_ADDR_GET( _reg ) \
414 ( ( ( _reg ) & GRPCI2_PCI2AHB_ADDR_MASK ) >> \
415 GRPCI2_PCI2AHB_ADDR_SHIFT )
416#define GRPCI2_PCI2AHB_ADDR_SET( _reg, _val ) \
417 ( ( ( _reg ) & ~GRPCI2_PCI2AHB_ADDR_MASK ) | \
418 ( ( ( _val ) << GRPCI2_PCI2AHB_ADDR_SHIFT ) & \
419 GRPCI2_PCI2AHB_ADDR_MASK ) )
420#define GRPCI2_PCI2AHB_ADDR( _val ) \
421 ( ( ( _val ) << GRPCI2_PCI2AHB_ADDR_SHIFT ) & \
422 GRPCI2_PCI2AHB_ADDR_MASK )
423
435#define GRPCI2_AHBM2PCI_ADDR_SHIFT 0
436#define GRPCI2_AHBM2PCI_ADDR_MASK 0xffffffffU
437#define GRPCI2_AHBM2PCI_ADDR_GET( _reg ) \
438 ( ( ( _reg ) & GRPCI2_AHBM2PCI_ADDR_MASK ) >> \
439 GRPCI2_AHBM2PCI_ADDR_SHIFT )
440#define GRPCI2_AHBM2PCI_ADDR_SET( _reg, _val ) \
441 ( ( ( _reg ) & ~GRPCI2_AHBM2PCI_ADDR_MASK ) | \
442 ( ( ( _val ) << GRPCI2_AHBM2PCI_ADDR_SHIFT ) & \
443 GRPCI2_AHBM2PCI_ADDR_MASK ) )
444#define GRPCI2_AHBM2PCI_ADDR( _val ) \
445 ( ( ( _val ) << GRPCI2_AHBM2PCI_ADDR_SHIFT ) & \
446 GRPCI2_AHBM2PCI_ADDR_MASK )
447
459#define GRPCI2_TCTRC_TRIG_INDEX_SHIFT 16
460#define GRPCI2_TCTRC_TRIG_INDEX_MASK 0xffff0000U
461#define GRPCI2_TCTRC_TRIG_INDEX_GET( _reg ) \
462 ( ( ( _reg ) & GRPCI2_TCTRC_TRIG_INDEX_MASK ) >> \
463 GRPCI2_TCTRC_TRIG_INDEX_SHIFT )
464#define GRPCI2_TCTRC_TRIG_INDEX_SET( _reg, _val ) \
465 ( ( ( _reg ) & ~GRPCI2_TCTRC_TRIG_INDEX_MASK ) | \
466 ( ( ( _val ) << GRPCI2_TCTRC_TRIG_INDEX_SHIFT ) & \
467 GRPCI2_TCTRC_TRIG_INDEX_MASK ) )
468#define GRPCI2_TCTRC_TRIG_INDEX( _val ) \
469 ( ( ( _val ) << GRPCI2_TCTRC_TRIG_INDEX_SHIFT ) & \
470 GRPCI2_TCTRC_TRIG_INDEX_MASK )
471
472#define GRPCI2_TCTRC_AR 0x8000U
473
474#define GRPCI2_TCTRC_EN 0x4000U
475
476#define GRPCI2_TCTRC_DEPTH_SHIFT 4
477#define GRPCI2_TCTRC_DEPTH_MASK 0xff0U
478#define GRPCI2_TCTRC_DEPTH_GET( _reg ) \
479 ( ( ( _reg ) & GRPCI2_TCTRC_DEPTH_MASK ) >> \
480 GRPCI2_TCTRC_DEPTH_SHIFT )
481#define GRPCI2_TCTRC_DEPTH_SET( _reg, _val ) \
482 ( ( ( _reg ) & ~GRPCI2_TCTRC_DEPTH_MASK ) | \
483 ( ( ( _val ) << GRPCI2_TCTRC_DEPTH_SHIFT ) & \
484 GRPCI2_TCTRC_DEPTH_MASK ) )
485#define GRPCI2_TCTRC_DEPTH( _val ) \
486 ( ( ( _val ) << GRPCI2_TCTRC_DEPTH_SHIFT ) & \
487 GRPCI2_TCTRC_DEPTH_MASK )
488
489#define GRPCI2_TCTRC_SO 0x2U
490
491#define GRPCI2_TCTRC_SA 0x1U
492
503#define GRPCI2_TMODE_TRACING_MODE_SHIFT 24
504#define GRPCI2_TMODE_TRACING_MODE_MASK 0xf000000U
505#define GRPCI2_TMODE_TRACING_MODE_GET( _reg ) \
506 ( ( ( _reg ) & GRPCI2_TMODE_TRACING_MODE_MASK ) >> \
507 GRPCI2_TMODE_TRACING_MODE_SHIFT )
508#define GRPCI2_TMODE_TRACING_MODE_SET( _reg, _val ) \
509 ( ( ( _reg ) & ~GRPCI2_TMODE_TRACING_MODE_MASK ) | \
510 ( ( ( _val ) << GRPCI2_TMODE_TRACING_MODE_SHIFT ) & \
511 GRPCI2_TMODE_TRACING_MODE_MASK ) )
512#define GRPCI2_TMODE_TRACING_MODE( _val ) \
513 ( ( ( _val ) << GRPCI2_TMODE_TRACING_MODE_SHIFT ) & \
514 GRPCI2_TMODE_TRACING_MODE_MASK )
515
516#define GRPCI2_TMODE_TRIG_COUNT_SHIFT 16
517#define GRPCI2_TMODE_TRIG_COUNT_MASK 0xff0000U
518#define GRPCI2_TMODE_TRIG_COUNT_GET( _reg ) \
519 ( ( ( _reg ) & GRPCI2_TMODE_TRIG_COUNT_MASK ) >> \
520 GRPCI2_TMODE_TRIG_COUNT_SHIFT )
521#define GRPCI2_TMODE_TRIG_COUNT_SET( _reg, _val ) \
522 ( ( ( _reg ) & ~GRPCI2_TMODE_TRIG_COUNT_MASK ) | \
523 ( ( ( _val ) << GRPCI2_TMODE_TRIG_COUNT_SHIFT ) & \
524 GRPCI2_TMODE_TRIG_COUNT_MASK ) )
525#define GRPCI2_TMODE_TRIG_COUNT( _val ) \
526 ( ( ( _val ) << GRPCI2_TMODE_TRIG_COUNT_SHIFT ) & \
527 GRPCI2_TMODE_TRIG_COUNT_MASK )
528
529#define GRPCI2_TMODE_DELAYED_STOP_SHIFT 0
530#define GRPCI2_TMODE_DELAYED_STOP_MASK 0xffffU
531#define GRPCI2_TMODE_DELAYED_STOP_GET( _reg ) \
532 ( ( ( _reg ) & GRPCI2_TMODE_DELAYED_STOP_MASK ) >> \
533 GRPCI2_TMODE_DELAYED_STOP_SHIFT )
534#define GRPCI2_TMODE_DELAYED_STOP_SET( _reg, _val ) \
535 ( ( ( _reg ) & ~GRPCI2_TMODE_DELAYED_STOP_MASK ) | \
536 ( ( ( _val ) << GRPCI2_TMODE_DELAYED_STOP_SHIFT ) & \
537 GRPCI2_TMODE_DELAYED_STOP_MASK ) )
538#define GRPCI2_TMODE_DELAYED_STOP( _val ) \
539 ( ( ( _val ) << GRPCI2_TMODE_DELAYED_STOP_SHIFT ) & \
540 GRPCI2_TMODE_DELAYED_STOP_MASK )
541
552#define GRPCI2_TADP_PATTERN_SHIFT 0
553#define GRPCI2_TADP_PATTERN_MASK 0xffffffffU
554#define GRPCI2_TADP_PATTERN_GET( _reg ) \
555 ( ( ( _reg ) & GRPCI2_TADP_PATTERN_MASK ) >> \
556 GRPCI2_TADP_PATTERN_SHIFT )
557#define GRPCI2_TADP_PATTERN_SET( _reg, _val ) \
558 ( ( ( _reg ) & ~GRPCI2_TADP_PATTERN_MASK ) | \
559 ( ( ( _val ) << GRPCI2_TADP_PATTERN_SHIFT ) & \
560 GRPCI2_TADP_PATTERN_MASK ) )
561#define GRPCI2_TADP_PATTERN( _val ) \
562 ( ( ( _val ) << GRPCI2_TADP_PATTERN_SHIFT ) & \
563 GRPCI2_TADP_PATTERN_MASK )
564
575#define GRPCI2_TADM_MASK_SHIFT 0
576#define GRPCI2_TADM_MASK_MASK 0xffffffffU
577#define GRPCI2_TADM_MASK_GET( _reg ) \
578 ( ( ( _reg ) & GRPCI2_TADM_MASK_MASK ) >> \
579 GRPCI2_TADM_MASK_SHIFT )
580#define GRPCI2_TADM_MASK_SET( _reg, _val ) \
581 ( ( ( _reg ) & ~GRPCI2_TADM_MASK_MASK ) | \
582 ( ( ( _val ) << GRPCI2_TADM_MASK_SHIFT ) & \
583 GRPCI2_TADM_MASK_MASK ) )
584#define GRPCI2_TADM_MASK( _val ) \
585 ( ( ( _val ) << GRPCI2_TADM_MASK_SHIFT ) & \
586 GRPCI2_TADM_MASK_MASK )
587
598#define GRPCI2_TCP_CBE_3_0_SHIFT 16
599#define GRPCI2_TCP_CBE_3_0_MASK 0xf0000U
600#define GRPCI2_TCP_CBE_3_0_GET( _reg ) \
601 ( ( ( _reg ) & GRPCI2_TCP_CBE_3_0_MASK ) >> \
602 GRPCI2_TCP_CBE_3_0_SHIFT )
603#define GRPCI2_TCP_CBE_3_0_SET( _reg, _val ) \
604 ( ( ( _reg ) & ~GRPCI2_TCP_CBE_3_0_MASK ) | \
605 ( ( ( _val ) << GRPCI2_TCP_CBE_3_0_SHIFT ) & \
606 GRPCI2_TCP_CBE_3_0_MASK ) )
607#define GRPCI2_TCP_CBE_3_0( _val ) \
608 ( ( ( _val ) << GRPCI2_TCP_CBE_3_0_SHIFT ) & \
609 GRPCI2_TCP_CBE_3_0_MASK )
610
611#define GRPCI2_TCP_FRAME 0x8000U
612
613#define GRPCI2_TCP_IRDY 0x4000U
614
615#define GRPCI2_TCP_TRDY 0x2000U
616
617#define GRPCI2_TCP_STOP 0x1000U
618
619#define GRPCI2_TCP_DEVSEL 0x800U
620
621#define GRPCI2_TCP_PAR 0x400U
622
623#define GRPCI2_TCP_PERR 0x200U
624
625#define GRPCI2_TCP_SERR 0x100U
626
627#define GRPCI2_TCP_IDSEL 0x80U
628
629#define GRPCI2_TCP_REQ 0x40U
630
631#define GRPCI2_TCP_GNT 0x20U
632
633#define GRPCI2_TCP_LOCK 0x10U
634
635#define GRPCI2_TCP_RST 0x8U
636
647#define GRPCI2_TCM_CBE_3_0_SHIFT 16
648#define GRPCI2_TCM_CBE_3_0_MASK 0xf0000U
649#define GRPCI2_TCM_CBE_3_0_GET( _reg ) \
650 ( ( ( _reg ) & GRPCI2_TCM_CBE_3_0_MASK ) >> \
651 GRPCI2_TCM_CBE_3_0_SHIFT )
652#define GRPCI2_TCM_CBE_3_0_SET( _reg, _val ) \
653 ( ( ( _reg ) & ~GRPCI2_TCM_CBE_3_0_MASK ) | \
654 ( ( ( _val ) << GRPCI2_TCM_CBE_3_0_SHIFT ) & \
655 GRPCI2_TCM_CBE_3_0_MASK ) )
656#define GRPCI2_TCM_CBE_3_0( _val ) \
657 ( ( ( _val ) << GRPCI2_TCM_CBE_3_0_SHIFT ) & \
658 GRPCI2_TCM_CBE_3_0_MASK )
659
660#define GRPCI2_TCM_FRAME 0x8000U
661
662#define GRPCI2_TCM_IRDY 0x4000U
663
664#define GRPCI2_TCM_TRDY 0x2000U
665
666#define GRPCI2_TCM_STOP 0x1000U
667
668#define GRPCI2_TCM_DEVSEL 0x800U
669
670#define GRPCI2_TCM_PAR 0x400U
671
672#define GRPCI2_TCM_PERR 0x200U
673
674#define GRPCI2_TCM_SERR 0x100U
675
676#define GRPCI2_TCM_IDSEL 0x80U
677
678#define GRPCI2_TCM_REQ 0x40U
679
680#define GRPCI2_TCM_GNT 0x20U
681
682#define GRPCI2_TCM_LOCK 0x10U
683
684#define GRPCI2_TCM_RST 0x8U
685
696#define GRPCI2_TADS_SIGNAL_SHIFT 0
697#define GRPCI2_TADS_SIGNAL_MASK 0xffffffffU
698#define GRPCI2_TADS_SIGNAL_GET( _reg ) \
699 ( ( ( _reg ) & GRPCI2_TADS_SIGNAL_MASK ) >> \
700 GRPCI2_TADS_SIGNAL_SHIFT )
701#define GRPCI2_TADS_SIGNAL_SET( _reg, _val ) \
702 ( ( ( _reg ) & ~GRPCI2_TADS_SIGNAL_MASK ) | \
703 ( ( ( _val ) << GRPCI2_TADS_SIGNAL_SHIFT ) & \
704 GRPCI2_TADS_SIGNAL_MASK ) )
705#define GRPCI2_TADS_SIGNAL( _val ) \
706 ( ( ( _val ) << GRPCI2_TADS_SIGNAL_SHIFT ) & \
707 GRPCI2_TADS_SIGNAL_MASK )
708
720#define GRPCI2_TCS_CBE_3_0_SHIFT 16
721#define GRPCI2_TCS_CBE_3_0_MASK 0xf0000U
722#define GRPCI2_TCS_CBE_3_0_GET( _reg ) \
723 ( ( ( _reg ) & GRPCI2_TCS_CBE_3_0_MASK ) >> \
724 GRPCI2_TCS_CBE_3_0_SHIFT )
725#define GRPCI2_TCS_CBE_3_0_SET( _reg, _val ) \
726 ( ( ( _reg ) & ~GRPCI2_TCS_CBE_3_0_MASK ) | \
727 ( ( ( _val ) << GRPCI2_TCS_CBE_3_0_SHIFT ) & \
728 GRPCI2_TCS_CBE_3_0_MASK ) )
729#define GRPCI2_TCS_CBE_3_0( _val ) \
730 ( ( ( _val ) << GRPCI2_TCS_CBE_3_0_SHIFT ) & \
731 GRPCI2_TCS_CBE_3_0_MASK )
732
733#define GRPCI2_TCS_FRAME 0x8000U
734
735#define GRPCI2_TCS_IRDY 0x4000U
736
737#define GRPCI2_TCS_TRDY 0x2000U
738
739#define GRPCI2_TCS_STOP 0x1000U
740
741#define GRPCI2_TCS_DEVSEL 0x800U
742
743#define GRPCI2_TCS_PAR 0x400U
744
745#define GRPCI2_TCS_PERR 0x200U
746
747#define GRPCI2_TCS_SERR 0x100U
748
749#define GRPCI2_TCS_IDSEL 0x80U
750
751#define GRPCI2_TCS_REQ 0x40U
752
753#define GRPCI2_TCS_GNT 0x20U
754
755#define GRPCI2_TCS_LOCK 0x10U
756
757#define GRPCI2_TCS_RST 0x8U
758
764typedef struct grpci2 {
768 uint32_t ctrl;
769
773 uint32_t statcap;
774
778 uint32_t bcim;
779
783 uint32_t ahb2pci;
784
788 uint32_t dmactrl;
789
793 uint32_t dmabase;
794
798 uint32_t dmachan;
799
800 uint32_t reserved_1c_20;
801
805 uint32_t pci2ahb_0;
806
807 uint32_t reserved_24_34[ 4 ];
808
812 uint32_t pci2ahb_1;
813
814 uint32_t reserved_38_40[ 2 ];
815
819 uint32_t ahbm2pci_0;
820
821 uint32_t reserved_44_7c[ 14 ];
822
826 uint32_t ahbm2pci_1;
827
831 uint32_t tctrc;
832
836 uint32_t tmode;
837
841 uint32_t tadp;
842
846 uint32_t tadm;
847
851 uint32_t tcp;
852
856 uint32_t tcm;
857
861 uint32_t tads;
862
866 uint32_t tcs;
867} grpci2;
868
871#ifdef __cplusplus
872}
873#endif
874
875#endif /* _GRLIB_GRPCI2_REGS_H */
grpci2
This structure defines the GRPCI2 register block memory map.
Definition: grpci2-regs.h:764
grpci2::tadm
uint32_t tadm
See PCI trace AD mask register (TADM).
Definition: grpci2-regs.h:846
grpci2::pci2ahb_1
uint32_t pci2ahb_1
See PCI BAR to AHB address mapping register (PCI2AHB).
Definition: grpci2-regs.h:812
grpci2::ahbm2pci_1
uint32_t ahbm2pci_1
See AHB master to PCI memory address mapping register (AHBM2PCI).
Definition: grpci2-regs.h:826
grpci2::pci2ahb_0
uint32_t pci2ahb_0
See PCI BAR to AHB address mapping register (PCI2AHB).
Definition: grpci2-regs.h:805
grpci2::dmactrl
uint32_t dmactrl
See DMA control and status register (DMACTRL).
Definition: grpci2-regs.h:788
grpci2::dmabase
uint32_t dmabase
See DMA descriptor base address register (DMABASE).
Definition: grpci2-regs.h:793
grpci2::tadp
uint32_t tadp
See PCI trace AD pattern register (TADP).
Definition: grpci2-regs.h:841
grpci2::dmachan
uint32_t dmachan
See DMA channel active register (DMACHAN).
Definition: grpci2-regs.h:798
grpci2::statcap
uint32_t statcap
See Status and Capability register (STATCAP).
Definition: grpci2-regs.h:773
grpci2::tctrc
uint32_t tctrc
See PCI trace Control and Status register (TCTRC).
Definition: grpci2-regs.h:831
grpci2::tcp
uint32_t tcp
See PCI trace Ctrl signal pattern register (TCP).
Definition: grpci2-regs.h:851
grpci2::tmode
uint32_t tmode
See PCI trace counter and mode register (TMODE).
Definition: grpci2-regs.h:836
grpci2::bcim
uint32_t bcim
See PCI master prefetch burst limit (BCIM).
Definition: grpci2-regs.h:778
grpci2::ctrl
uint32_t ctrl
See Control register (CTRL).
Definition: grpci2-regs.h:768
grpci2::tcm
uint32_t tcm
See PCI trace Ctrl signal mask register (TCM).
Definition: grpci2-regs.h:856
grpci2::ahb2pci
uint32_t ahb2pci
See AHB to PCI mapping for PCI IO (AHB2PCI).
Definition: grpci2-regs.h:783
grpci2::tcs
uint32_t tcs
See PCI trace PCI Ctrl signal state register (TCS).
Definition: grpci2-regs.h:866
grpci2::tads
uint32_t tads
See PCI trace PCI AD state register (TADS).
Definition: grpci2-regs.h:861
grpci2::ahbm2pci_0
uint32_t ahbm2pci_0
See AHB master to PCI memory address mapping register (AHBM2PCI).
Definition: grpci2-regs.h:819
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