RTEMS 6.1-rc4
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griommu-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * This file is part of the RTEMS quality process and was automatically
38 * generated. If you find something that needs to be fixed or
39 * worded better please post a report or patch to an RTEMS mailing list
40 * or raise a bug report:
41 *
42 * https://www.rtems.org/bugs.html
43 *
44 * For information on updating and regenerating please refer to the How-To
45 * section in the Software Requirements Engineering chapter of the
46 * RTEMS Software Engineering manual. The manual is provided as a part of
47 * a release. For development sources please refer to the online
48 * documentation at:
49 *
50 * https://docs.rtems.org
51 */
52
53/* Generated from spec:/dev/grlib/if/griommu-header */
54
55#ifndef _GRLIB_GRIOMMU_REGS_H
56#define _GRLIB_GRIOMMU_REGS_H
57
58#include <stdint.h>
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64/* Generated from spec:/dev/grlib/if/griommu */
65
84#define GRIOMMU_CAP0_A 0x80000000U
85
86#define GRIOMMU_CAP0_AC 0x40000000U
87
88#define GRIOMMU_CAP0_CA 0x20000000U
89
90#define GRIOMMU_CAP0_CP 0x10000000U
91
92#define GRIOMMU_CAP0_NARB_SHIFT 20
93#define GRIOMMU_CAP0_NARB_MASK 0xf00000U
94#define GRIOMMU_CAP0_NARB_GET( _reg ) \
95 ( ( ( _reg ) & GRIOMMU_CAP0_NARB_MASK ) >> \
96 GRIOMMU_CAP0_NARB_SHIFT )
97#define GRIOMMU_CAP0_NARB_SET( _reg, _val ) \
98 ( ( ( _reg ) & ~GRIOMMU_CAP0_NARB_MASK ) | \
99 ( ( ( _val ) << GRIOMMU_CAP0_NARB_SHIFT ) & \
100 GRIOMMU_CAP0_NARB_MASK ) )
101#define GRIOMMU_CAP0_NARB( _val ) \
102 ( ( ( _val ) << GRIOMMU_CAP0_NARB_SHIFT ) & \
103 GRIOMMU_CAP0_NARB_MASK )
104
105#define GRIOMMU_CAP0_CS 0x80000U
106
107#define GRIOMMU_CAP0_FT_SHIFT 17
108#define GRIOMMU_CAP0_FT_MASK 0x60000U
109#define GRIOMMU_CAP0_FT_GET( _reg ) \
110 ( ( ( _reg ) & GRIOMMU_CAP0_FT_MASK ) >> \
111 GRIOMMU_CAP0_FT_SHIFT )
112#define GRIOMMU_CAP0_FT_SET( _reg, _val ) \
113 ( ( ( _reg ) & ~GRIOMMU_CAP0_FT_MASK ) | \
114 ( ( ( _val ) << GRIOMMU_CAP0_FT_SHIFT ) & \
115 GRIOMMU_CAP0_FT_MASK ) )
116#define GRIOMMU_CAP0_FT( _val ) \
117 ( ( ( _val ) << GRIOMMU_CAP0_FT_SHIFT ) & \
118 GRIOMMU_CAP0_FT_MASK )
119
120#define GRIOMMU_CAP0_ST 0x10000U
121
122#define GRIOMMU_CAP0_I 0x8000U
123
124#define GRIOMMU_CAP0_IT 0x4000U
125
126#define GRIOMMU_CAP0_IA 0x2000U
127
128#define GRIOMMU_CAP0_IP 0x1000U
129
130#define GRIOMMU_CAP0_MB 0x100U
131
132#define GRIOMMU_CAP0_GRPS_SHIFT 4
133#define GRIOMMU_CAP0_GRPS_MASK 0xf0U
134#define GRIOMMU_CAP0_GRPS_GET( _reg ) \
135 ( ( ( _reg ) & GRIOMMU_CAP0_GRPS_MASK ) >> \
136 GRIOMMU_CAP0_GRPS_SHIFT )
137#define GRIOMMU_CAP0_GRPS_SET( _reg, _val ) \
138 ( ( ( _reg ) & ~GRIOMMU_CAP0_GRPS_MASK ) | \
139 ( ( ( _val ) << GRIOMMU_CAP0_GRPS_SHIFT ) & \
140 GRIOMMU_CAP0_GRPS_MASK ) )
141#define GRIOMMU_CAP0_GRPS( _val ) \
142 ( ( ( _val ) << GRIOMMU_CAP0_GRPS_SHIFT ) & \
143 GRIOMMU_CAP0_GRPS_MASK )
144
145#define GRIOMMU_CAP0_MSTS_SHIFT 0
146#define GRIOMMU_CAP0_MSTS_MASK 0xfU
147#define GRIOMMU_CAP0_MSTS_GET( _reg ) \
148 ( ( ( _reg ) & GRIOMMU_CAP0_MSTS_MASK ) >> \
149 GRIOMMU_CAP0_MSTS_SHIFT )
150#define GRIOMMU_CAP0_MSTS_SET( _reg, _val ) \
151 ( ( ( _reg ) & ~GRIOMMU_CAP0_MSTS_MASK ) | \
152 ( ( ( _val ) << GRIOMMU_CAP0_MSTS_SHIFT ) & \
153 GRIOMMU_CAP0_MSTS_MASK ) )
154#define GRIOMMU_CAP0_MSTS( _val ) \
155 ( ( ( _val ) << GRIOMMU_CAP0_MSTS_SHIFT ) & \
156 GRIOMMU_CAP0_MSTS_MASK )
157
168#define GRIOMMU_CAP1_CADDR_SHIFT 20
169#define GRIOMMU_CAP1_CADDR_MASK 0xfff00000U
170#define GRIOMMU_CAP1_CADDR_GET( _reg ) \
171 ( ( ( _reg ) & GRIOMMU_CAP1_CADDR_MASK ) >> \
172 GRIOMMU_CAP1_CADDR_SHIFT )
173#define GRIOMMU_CAP1_CADDR_SET( _reg, _val ) \
174 ( ( ( _reg ) & ~GRIOMMU_CAP1_CADDR_MASK ) | \
175 ( ( ( _val ) << GRIOMMU_CAP1_CADDR_SHIFT ) & \
176 GRIOMMU_CAP1_CADDR_MASK ) )
177#define GRIOMMU_CAP1_CADDR( _val ) \
178 ( ( ( _val ) << GRIOMMU_CAP1_CADDR_SHIFT ) & \
179 GRIOMMU_CAP1_CADDR_MASK )
180
181#define GRIOMMU_CAP1_CMASK_SHIFT 16
182#define GRIOMMU_CAP1_CMASK_MASK 0xf0000U
183#define GRIOMMU_CAP1_CMASK_GET( _reg ) \
184 ( ( ( _reg ) & GRIOMMU_CAP1_CMASK_MASK ) >> \
185 GRIOMMU_CAP1_CMASK_SHIFT )
186#define GRIOMMU_CAP1_CMASK_SET( _reg, _val ) \
187 ( ( ( _reg ) & ~GRIOMMU_CAP1_CMASK_MASK ) | \
188 ( ( ( _val ) << GRIOMMU_CAP1_CMASK_SHIFT ) & \
189 GRIOMMU_CAP1_CMASK_MASK ) )
190#define GRIOMMU_CAP1_CMASK( _val ) \
191 ( ( ( _val ) << GRIOMMU_CAP1_CMASK_SHIFT ) & \
192 GRIOMMU_CAP1_CMASK_MASK )
193
194#define GRIOMMU_CAP1_CTAGBITS_SHIFT 8
195#define GRIOMMU_CAP1_CTAGBITS_MASK 0xff00U
196#define GRIOMMU_CAP1_CTAGBITS_GET( _reg ) \
197 ( ( ( _reg ) & GRIOMMU_CAP1_CTAGBITS_MASK ) >> \
198 GRIOMMU_CAP1_CTAGBITS_SHIFT )
199#define GRIOMMU_CAP1_CTAGBITS_SET( _reg, _val ) \
200 ( ( ( _reg ) & ~GRIOMMU_CAP1_CTAGBITS_MASK ) | \
201 ( ( ( _val ) << GRIOMMU_CAP1_CTAGBITS_SHIFT ) & \
202 GRIOMMU_CAP1_CTAGBITS_MASK ) )
203#define GRIOMMU_CAP1_CTAGBITS( _val ) \
204 ( ( ( _val ) << GRIOMMU_CAP1_CTAGBITS_SHIFT ) & \
205 GRIOMMU_CAP1_CTAGBITS_MASK )
206
207#define GRIOMMU_CAP1_CISIZE_SHIFT 5
208#define GRIOMMU_CAP1_CISIZE_MASK 0xe0U
209#define GRIOMMU_CAP1_CISIZE_GET( _reg ) \
210 ( ( ( _reg ) & GRIOMMU_CAP1_CISIZE_MASK ) >> \
211 GRIOMMU_CAP1_CISIZE_SHIFT )
212#define GRIOMMU_CAP1_CISIZE_SET( _reg, _val ) \
213 ( ( ( _reg ) & ~GRIOMMU_CAP1_CISIZE_MASK ) | \
214 ( ( ( _val ) << GRIOMMU_CAP1_CISIZE_SHIFT ) & \
215 GRIOMMU_CAP1_CISIZE_MASK ) )
216#define GRIOMMU_CAP1_CISIZE( _val ) \
217 ( ( ( _val ) << GRIOMMU_CAP1_CISIZE_SHIFT ) & \
218 GRIOMMU_CAP1_CISIZE_MASK )
219
220#define GRIOMMU_CAP1_CLINES_SHIFT 0
221#define GRIOMMU_CAP1_CLINES_MASK 0x1fU
222#define GRIOMMU_CAP1_CLINES_GET( _reg ) \
223 ( ( ( _reg ) & GRIOMMU_CAP1_CLINES_MASK ) >> \
224 GRIOMMU_CAP1_CLINES_SHIFT )
225#define GRIOMMU_CAP1_CLINES_SET( _reg, _val ) \
226 ( ( ( _reg ) & ~GRIOMMU_CAP1_CLINES_MASK ) | \
227 ( ( ( _val ) << GRIOMMU_CAP1_CLINES_SHIFT ) & \
228 GRIOMMU_CAP1_CLINES_MASK ) )
229#define GRIOMMU_CAP1_CLINES( _val ) \
230 ( ( ( _val ) << GRIOMMU_CAP1_CLINES_SHIFT ) & \
231 GRIOMMU_CAP1_CLINES_MASK )
232
243#define GRIOMMU_CAP2_TMASK_SHIFT 24
244#define GRIOMMU_CAP2_TMASK_MASK 0xff000000U
245#define GRIOMMU_CAP2_TMASK_GET( _reg ) \
246 ( ( ( _reg ) & GRIOMMU_CAP2_TMASK_MASK ) >> \
247 GRIOMMU_CAP2_TMASK_SHIFT )
248#define GRIOMMU_CAP2_TMASK_SET( _reg, _val ) \
249 ( ( ( _reg ) & ~GRIOMMU_CAP2_TMASK_MASK ) | \
250 ( ( ( _val ) << GRIOMMU_CAP2_TMASK_SHIFT ) & \
251 GRIOMMU_CAP2_TMASK_MASK ) )
252#define GRIOMMU_CAP2_TMASK( _val ) \
253 ( ( ( _val ) << GRIOMMU_CAP2_TMASK_SHIFT ) & \
254 GRIOMMU_CAP2_TMASK_MASK )
255
256#define GRIOMMU_CAP2_MTYPE_SHIFT 18
257#define GRIOMMU_CAP2_MTYPE_MASK 0xc0000U
258#define GRIOMMU_CAP2_MTYPE_GET( _reg ) \
259 ( ( ( _reg ) & GRIOMMU_CAP2_MTYPE_MASK ) >> \
260 GRIOMMU_CAP2_MTYPE_SHIFT )
261#define GRIOMMU_CAP2_MTYPE_SET( _reg, _val ) \
262 ( ( ( _reg ) & ~GRIOMMU_CAP2_MTYPE_MASK ) | \
263 ( ( ( _val ) << GRIOMMU_CAP2_MTYPE_SHIFT ) & \
264 GRIOMMU_CAP2_MTYPE_MASK ) )
265#define GRIOMMU_CAP2_MTYPE( _val ) \
266 ( ( ( _val ) << GRIOMMU_CAP2_MTYPE_SHIFT ) & \
267 GRIOMMU_CAP2_MTYPE_MASK )
268
269#define GRIOMMU_CAP2_TTYPE_SHIFT 16
270#define GRIOMMU_CAP2_TTYPE_MASK 0x30000U
271#define GRIOMMU_CAP2_TTYPE_GET( _reg ) \
272 ( ( ( _reg ) & GRIOMMU_CAP2_TTYPE_MASK ) >> \
273 GRIOMMU_CAP2_TTYPE_SHIFT )
274#define GRIOMMU_CAP2_TTYPE_SET( _reg, _val ) \
275 ( ( ( _reg ) & ~GRIOMMU_CAP2_TTYPE_MASK ) | \
276 ( ( ( _val ) << GRIOMMU_CAP2_TTYPE_SHIFT ) & \
277 GRIOMMU_CAP2_TTYPE_MASK ) )
278#define GRIOMMU_CAP2_TTYPE( _val ) \
279 ( ( ( _val ) << GRIOMMU_CAP2_TTYPE_SHIFT ) & \
280 GRIOMMU_CAP2_TTYPE_MASK )
281
282#define GRIOMMU_CAP2_TTAGBITS_SHIFT 8
283#define GRIOMMU_CAP2_TTAGBITS_MASK 0xff00U
284#define GRIOMMU_CAP2_TTAGBITS_GET( _reg ) \
285 ( ( ( _reg ) & GRIOMMU_CAP2_TTAGBITS_MASK ) >> \
286 GRIOMMU_CAP2_TTAGBITS_SHIFT )
287#define GRIOMMU_CAP2_TTAGBITS_SET( _reg, _val ) \
288 ( ( ( _reg ) & ~GRIOMMU_CAP2_TTAGBITS_MASK ) | \
289 ( ( ( _val ) << GRIOMMU_CAP2_TTAGBITS_SHIFT ) & \
290 GRIOMMU_CAP2_TTAGBITS_MASK ) )
291#define GRIOMMU_CAP2_TTAGBITS( _val ) \
292 ( ( ( _val ) << GRIOMMU_CAP2_TTAGBITS_SHIFT ) & \
293 GRIOMMU_CAP2_TTAGBITS_MASK )
294
295#define GRIOMMU_CAP2_ISIZE_SHIFT 5
296#define GRIOMMU_CAP2_ISIZE_MASK 0xe0U
297#define GRIOMMU_CAP2_ISIZE_GET( _reg ) \
298 ( ( ( _reg ) & GRIOMMU_CAP2_ISIZE_MASK ) >> \
299 GRIOMMU_CAP2_ISIZE_SHIFT )
300#define GRIOMMU_CAP2_ISIZE_SET( _reg, _val ) \
301 ( ( ( _reg ) & ~GRIOMMU_CAP2_ISIZE_MASK ) | \
302 ( ( ( _val ) << GRIOMMU_CAP2_ISIZE_SHIFT ) & \
303 GRIOMMU_CAP2_ISIZE_MASK ) )
304#define GRIOMMU_CAP2_ISIZE( _val ) \
305 ( ( ( _val ) << GRIOMMU_CAP2_ISIZE_SHIFT ) & \
306 GRIOMMU_CAP2_ISIZE_MASK )
307
308#define GRIOMMU_CAP2_TLBENT_SHIFT 0
309#define GRIOMMU_CAP2_TLBENT_MASK 0x1fU
310#define GRIOMMU_CAP2_TLBENT_GET( _reg ) \
311 ( ( ( _reg ) & GRIOMMU_CAP2_TLBENT_MASK ) >> \
312 GRIOMMU_CAP2_TLBENT_SHIFT )
313#define GRIOMMU_CAP2_TLBENT_SET( _reg, _val ) \
314 ( ( ( _reg ) & ~GRIOMMU_CAP2_TLBENT_MASK ) | \
315 ( ( ( _val ) << GRIOMMU_CAP2_TLBENT_SHIFT ) & \
316 GRIOMMU_CAP2_TLBENT_MASK ) )
317#define GRIOMMU_CAP2_TLBENT( _val ) \
318 ( ( ( _val ) << GRIOMMU_CAP2_TLBENT_SHIFT ) & \
319 GRIOMMU_CAP2_TLBENT_MASK )
320
331#define GRIOMMU_CTRL_PGSZ_SHIFT 18
332#define GRIOMMU_CTRL_PGSZ_MASK 0x1c0000U
333#define GRIOMMU_CTRL_PGSZ_GET( _reg ) \
334 ( ( ( _reg ) & GRIOMMU_CTRL_PGSZ_MASK ) >> \
335 GRIOMMU_CTRL_PGSZ_SHIFT )
336#define GRIOMMU_CTRL_PGSZ_SET( _reg, _val ) \
337 ( ( ( _reg ) & ~GRIOMMU_CTRL_PGSZ_MASK ) | \
338 ( ( ( _val ) << GRIOMMU_CTRL_PGSZ_SHIFT ) & \
339 GRIOMMU_CTRL_PGSZ_MASK ) )
340#define GRIOMMU_CTRL_PGSZ( _val ) \
341 ( ( ( _val ) << GRIOMMU_CTRL_PGSZ_SHIFT ) & \
342 GRIOMMU_CTRL_PGSZ_MASK )
343
344#define GRIOMMU_CTRL_LB 0x20000U
345
346#define GRIOMMU_CTRL_SP 0x10000U
347
348#define GRIOMMU_CTRL_ITR_SHIFT 12
349#define GRIOMMU_CTRL_ITR_MASK 0xf000U
350#define GRIOMMU_CTRL_ITR_GET( _reg ) \
351 ( ( ( _reg ) & GRIOMMU_CTRL_ITR_MASK ) >> \
352 GRIOMMU_CTRL_ITR_SHIFT )
353#define GRIOMMU_CTRL_ITR_SET( _reg, _val ) \
354 ( ( ( _reg ) & ~GRIOMMU_CTRL_ITR_MASK ) | \
355 ( ( ( _val ) << GRIOMMU_CTRL_ITR_SHIFT ) & \
356 GRIOMMU_CTRL_ITR_MASK ) )
357#define GRIOMMU_CTRL_ITR( _val ) \
358 ( ( ( _val ) << GRIOMMU_CTRL_ITR_SHIFT ) & \
359 GRIOMMU_CTRL_ITR_MASK )
360
361#define GRIOMMU_CTRL_DP 0x800U
362
363#define GRIOMMU_CTRL_SIV 0x400U
364
365#define GRIOMMU_CTRL_HPROT_SHIFT 8
366#define GRIOMMU_CTRL_HPROT_MASK 0x300U
367#define GRIOMMU_CTRL_HPROT_GET( _reg ) \
368 ( ( ( _reg ) & GRIOMMU_CTRL_HPROT_MASK ) >> \
369 GRIOMMU_CTRL_HPROT_SHIFT )
370#define GRIOMMU_CTRL_HPROT_SET( _reg, _val ) \
371 ( ( ( _reg ) & ~GRIOMMU_CTRL_HPROT_MASK ) | \
372 ( ( ( _val ) << GRIOMMU_CTRL_HPROT_SHIFT ) & \
373 GRIOMMU_CTRL_HPROT_MASK ) )
374#define GRIOMMU_CTRL_HPROT( _val ) \
375 ( ( ( _val ) << GRIOMMU_CTRL_HPROT_SHIFT ) & \
376 GRIOMMU_CTRL_HPROT_MASK )
377
378#define GRIOMMU_CTRL_AU 0x80U
379
380#define GRIOMMU_CTRL_WP 0x40U
381
382#define GRIOMMU_CTRL_DM 0x20U
383
384#define GRIOMMU_CTRL_GS 0x10U
385
386#define GRIOMMU_CTRL_CE 0x8U
387
388#define GRIOMMU_CTRL_PM_SHIFT 1
389#define GRIOMMU_CTRL_PM_MASK 0x6U
390#define GRIOMMU_CTRL_PM_GET( _reg ) \
391 ( ( ( _reg ) & GRIOMMU_CTRL_PM_MASK ) >> \
392 GRIOMMU_CTRL_PM_SHIFT )
393#define GRIOMMU_CTRL_PM_SET( _reg, _val ) \
394 ( ( ( _reg ) & ~GRIOMMU_CTRL_PM_MASK ) | \
395 ( ( ( _val ) << GRIOMMU_CTRL_PM_SHIFT ) & \
396 GRIOMMU_CTRL_PM_MASK ) )
397#define GRIOMMU_CTRL_PM( _val ) \
398 ( ( ( _val ) << GRIOMMU_CTRL_PM_SHIFT ) & \
399 GRIOMMU_CTRL_PM_MASK )
400
401#define GRIOMMU_CTRL_EN 0x1U
402
413#define GRIOMMU_FLUSH_FGRP_SHIFT 4
414#define GRIOMMU_FLUSH_FGRP_MASK 0xf0U
415#define GRIOMMU_FLUSH_FGRP_GET( _reg ) \
416 ( ( ( _reg ) & GRIOMMU_FLUSH_FGRP_MASK ) >> \
417 GRIOMMU_FLUSH_FGRP_SHIFT )
418#define GRIOMMU_FLUSH_FGRP_SET( _reg, _val ) \
419 ( ( ( _reg ) & ~GRIOMMU_FLUSH_FGRP_MASK ) | \
420 ( ( ( _val ) << GRIOMMU_FLUSH_FGRP_SHIFT ) & \
421 GRIOMMU_FLUSH_FGRP_MASK ) )
422#define GRIOMMU_FLUSH_FGRP( _val ) \
423 ( ( ( _val ) << GRIOMMU_FLUSH_FGRP_SHIFT ) & \
424 GRIOMMU_FLUSH_FGRP_MASK )
425
426#define GRIOMMU_FLUSH_GF 0x2U
427
428#define GRIOMMU_FLUSH_F 0x1U
429
440#define GRIOMMU_STATUS_PE 0x20U
441
442#define GRIOMMU_STATUS_DE 0x10U
443
444#define GRIOMMU_STATUS_FC 0x8U
445
446#define GRIOMMU_STATUS_FL 0x4U
447
448#define GRIOMMU_STATUS_AD 0x2U
449
450#define GRIOMMU_STATUS_TE 0x1U
451
462#define GRIOMMU_IMASK_PEI 0x20U
463
464#define GRIOMMU_IMASK_FCI 0x8U
465
466#define GRIOMMU_IMASK_FLI 0x4U
467
468#define GRIOMMU_IMASK_ADI 0x2U
469
470#define GRIOMMU_IMASK_TEI 0x1U
471
482#define GRIOMMU_AHBFAS_FADDR_31_5_SHIFT 5
483#define GRIOMMU_AHBFAS_FADDR_31_5_MASK 0xffffffe0U
484#define GRIOMMU_AHBFAS_FADDR_31_5_GET( _reg ) \
485 ( ( ( _reg ) & GRIOMMU_AHBFAS_FADDR_31_5_MASK ) >> \
486 GRIOMMU_AHBFAS_FADDR_31_5_SHIFT )
487#define GRIOMMU_AHBFAS_FADDR_31_5_SET( _reg, _val ) \
488 ( ( ( _reg ) & ~GRIOMMU_AHBFAS_FADDR_31_5_MASK ) | \
489 ( ( ( _val ) << GRIOMMU_AHBFAS_FADDR_31_5_SHIFT ) & \
490 GRIOMMU_AHBFAS_FADDR_31_5_MASK ) )
491#define GRIOMMU_AHBFAS_FADDR_31_5( _val ) \
492 ( ( ( _val ) << GRIOMMU_AHBFAS_FADDR_31_5_SHIFT ) & \
493 GRIOMMU_AHBFAS_FADDR_31_5_MASK )
494
495#define GRIOMMU_AHBFAS_FW 0x10U
496
497#define GRIOMMU_AHBFAS_FMASTER_SHIFT 0
498#define GRIOMMU_AHBFAS_FMASTER_MASK 0xfU
499#define GRIOMMU_AHBFAS_FMASTER_GET( _reg ) \
500 ( ( ( _reg ) & GRIOMMU_AHBFAS_FMASTER_MASK ) >> \
501 GRIOMMU_AHBFAS_FMASTER_SHIFT )
502#define GRIOMMU_AHBFAS_FMASTER_SET( _reg, _val ) \
503 ( ( ( _reg ) & ~GRIOMMU_AHBFAS_FMASTER_MASK ) | \
504 ( ( ( _val ) << GRIOMMU_AHBFAS_FMASTER_SHIFT ) & \
505 GRIOMMU_AHBFAS_FMASTER_MASK ) )
506#define GRIOMMU_AHBFAS_FMASTER( _val ) \
507 ( ( ( _val ) << GRIOMMU_AHBFAS_FMASTER_SHIFT ) & \
508 GRIOMMU_AHBFAS_FMASTER_MASK )
509
521#define GRIOMMU_MSTCFG_VENDOR_SHIFT 24
522#define GRIOMMU_MSTCFG_VENDOR_MASK 0xff000000U
523#define GRIOMMU_MSTCFG_VENDOR_GET( _reg ) \
524 ( ( ( _reg ) & GRIOMMU_MSTCFG_VENDOR_MASK ) >> \
525 GRIOMMU_MSTCFG_VENDOR_SHIFT )
526#define GRIOMMU_MSTCFG_VENDOR_SET( _reg, _val ) \
527 ( ( ( _reg ) & ~GRIOMMU_MSTCFG_VENDOR_MASK ) | \
528 ( ( ( _val ) << GRIOMMU_MSTCFG_VENDOR_SHIFT ) & \
529 GRIOMMU_MSTCFG_VENDOR_MASK ) )
530#define GRIOMMU_MSTCFG_VENDOR( _val ) \
531 ( ( ( _val ) << GRIOMMU_MSTCFG_VENDOR_SHIFT ) & \
532 GRIOMMU_MSTCFG_VENDOR_MASK )
533
534#define GRIOMMU_MSTCFG_DEVICE_SHIFT 12
535#define GRIOMMU_MSTCFG_DEVICE_MASK 0xfff000U
536#define GRIOMMU_MSTCFG_DEVICE_GET( _reg ) \
537 ( ( ( _reg ) & GRIOMMU_MSTCFG_DEVICE_MASK ) >> \
538 GRIOMMU_MSTCFG_DEVICE_SHIFT )
539#define GRIOMMU_MSTCFG_DEVICE_SET( _reg, _val ) \
540 ( ( ( _reg ) & ~GRIOMMU_MSTCFG_DEVICE_MASK ) | \
541 ( ( ( _val ) << GRIOMMU_MSTCFG_DEVICE_SHIFT ) & \
542 GRIOMMU_MSTCFG_DEVICE_MASK ) )
543#define GRIOMMU_MSTCFG_DEVICE( _val ) \
544 ( ( ( _val ) << GRIOMMU_MSTCFG_DEVICE_SHIFT ) & \
545 GRIOMMU_MSTCFG_DEVICE_MASK )
546
547#define GRIOMMU_MSTCFG_BS 0x10U
548
549#define GRIOMMU_MSTCFG_GROUP_SHIFT 0
550#define GRIOMMU_MSTCFG_GROUP_MASK 0xfU
551#define GRIOMMU_MSTCFG_GROUP_GET( _reg ) \
552 ( ( ( _reg ) & GRIOMMU_MSTCFG_GROUP_MASK ) >> \
553 GRIOMMU_MSTCFG_GROUP_SHIFT )
554#define GRIOMMU_MSTCFG_GROUP_SET( _reg, _val ) \
555 ( ( ( _reg ) & ~GRIOMMU_MSTCFG_GROUP_MASK ) | \
556 ( ( ( _val ) << GRIOMMU_MSTCFG_GROUP_SHIFT ) & \
557 GRIOMMU_MSTCFG_GROUP_MASK ) )
558#define GRIOMMU_MSTCFG_GROUP( _val ) \
559 ( ( ( _val ) << GRIOMMU_MSTCFG_GROUP_SHIFT ) & \
560 GRIOMMU_MSTCFG_GROUP_MASK )
561
572#define GRIOMMU_GRPCTRL_BASE_31_4_SHIFT 4
573#define GRIOMMU_GRPCTRL_BASE_31_4_MASK 0xfffffff0U
574#define GRIOMMU_GRPCTRL_BASE_31_4_GET( _reg ) \
575 ( ( ( _reg ) & GRIOMMU_GRPCTRL_BASE_31_4_MASK ) >> \
576 GRIOMMU_GRPCTRL_BASE_31_4_SHIFT )
577#define GRIOMMU_GRPCTRL_BASE_31_4_SET( _reg, _val ) \
578 ( ( ( _reg ) & ~GRIOMMU_GRPCTRL_BASE_31_4_MASK ) | \
579 ( ( ( _val ) << GRIOMMU_GRPCTRL_BASE_31_4_SHIFT ) & \
580 GRIOMMU_GRPCTRL_BASE_31_4_MASK ) )
581#define GRIOMMU_GRPCTRL_BASE_31_4( _val ) \
582 ( ( ( _val ) << GRIOMMU_GRPCTRL_BASE_31_4_SHIFT ) & \
583 GRIOMMU_GRPCTRL_BASE_31_4_MASK )
584
585#define GRIOMMU_GRPCTRL_P 0x2U
586
587#define GRIOMMU_GRPCTRL_AG 0x1U
588
600#define GRIOMMU_DIAGCTRL_DA 0x80000000U
601
602#define GRIOMMU_DIAGCTRL_RW 0x40000000U
603
604#define GRIOMMU_DIAGCTRL_DP 0x200000U
605
606#define GRIOMMU_DIAGCTRL_TP 0x100000U
607
608#define GRIOMMU_DIAGCTRL_SETADDR_SHIFT 0
609#define GRIOMMU_DIAGCTRL_SETADDR_MASK 0x7ffffU
610#define GRIOMMU_DIAGCTRL_SETADDR_GET( _reg ) \
611 ( ( ( _reg ) & GRIOMMU_DIAGCTRL_SETADDR_MASK ) >> \
612 GRIOMMU_DIAGCTRL_SETADDR_SHIFT )
613#define GRIOMMU_DIAGCTRL_SETADDR_SET( _reg, _val ) \
614 ( ( ( _reg ) & ~GRIOMMU_DIAGCTRL_SETADDR_MASK ) | \
615 ( ( ( _val ) << GRIOMMU_DIAGCTRL_SETADDR_SHIFT ) & \
616 GRIOMMU_DIAGCTRL_SETADDR_MASK ) )
617#define GRIOMMU_DIAGCTRL_SETADDR( _val ) \
618 ( ( ( _val ) << GRIOMMU_DIAGCTRL_SETADDR_SHIFT ) & \
619 GRIOMMU_DIAGCTRL_SETADDR_MASK )
620
632#define GRIOMMU_DIAGD_CDATAN_SHIFT 0
633#define GRIOMMU_DIAGD_CDATAN_MASK 0xffffffffU
634#define GRIOMMU_DIAGD_CDATAN_GET( _reg ) \
635 ( ( ( _reg ) & GRIOMMU_DIAGD_CDATAN_MASK ) >> \
636 GRIOMMU_DIAGD_CDATAN_SHIFT )
637#define GRIOMMU_DIAGD_CDATAN_SET( _reg, _val ) \
638 ( ( ( _reg ) & ~GRIOMMU_DIAGD_CDATAN_MASK ) | \
639 ( ( ( _val ) << GRIOMMU_DIAGD_CDATAN_SHIFT ) & \
640 GRIOMMU_DIAGD_CDATAN_MASK ) )
641#define GRIOMMU_DIAGD_CDATAN( _val ) \
642 ( ( ( _val ) << GRIOMMU_DIAGD_CDATAN_SHIFT ) & \
643 GRIOMMU_DIAGD_CDATAN_MASK )
644
656#define GRIOMMU_DIAGT_TAG_SHIFT 1
657#define GRIOMMU_DIAGT_TAG_MASK 0xfffffffeU
658#define GRIOMMU_DIAGT_TAG_GET( _reg ) \
659 ( ( ( _reg ) & GRIOMMU_DIAGT_TAG_MASK ) >> \
660 GRIOMMU_DIAGT_TAG_SHIFT )
661#define GRIOMMU_DIAGT_TAG_SET( _reg, _val ) \
662 ( ( ( _reg ) & ~GRIOMMU_DIAGT_TAG_MASK ) | \
663 ( ( ( _val ) << GRIOMMU_DIAGT_TAG_SHIFT ) & \
664 GRIOMMU_DIAGT_TAG_MASK ) )
665#define GRIOMMU_DIAGT_TAG( _val ) \
666 ( ( ( _val ) << GRIOMMU_DIAGT_TAG_SHIFT ) & \
667 GRIOMMU_DIAGT_TAG_MASK )
668
669#define GRIOMMU_DIAGT_V 0x1U
670
681#define GRIOMMU_DERRI_DPERRINJ_SHIFT 0
682#define GRIOMMU_DERRI_DPERRINJ_MASK 0xffffffffU
683#define GRIOMMU_DERRI_DPERRINJ_GET( _reg ) \
684 ( ( ( _reg ) & GRIOMMU_DERRI_DPERRINJ_MASK ) >> \
685 GRIOMMU_DERRI_DPERRINJ_SHIFT )
686#define GRIOMMU_DERRI_DPERRINJ_SET( _reg, _val ) \
687 ( ( ( _reg ) & ~GRIOMMU_DERRI_DPERRINJ_MASK ) | \
688 ( ( ( _val ) << GRIOMMU_DERRI_DPERRINJ_SHIFT ) & \
689 GRIOMMU_DERRI_DPERRINJ_MASK ) )
690#define GRIOMMU_DERRI_DPERRINJ( _val ) \
691 ( ( ( _val ) << GRIOMMU_DERRI_DPERRINJ_SHIFT ) & \
692 GRIOMMU_DERRI_DPERRINJ_MASK )
693
704#define GRIOMMU_TERRI_TPERRINJ_SHIFT 0
705#define GRIOMMU_TERRI_TPERRINJ_MASK 0xffffffffU
706#define GRIOMMU_TERRI_TPERRINJ_GET( _reg ) \
707 ( ( ( _reg ) & GRIOMMU_TERRI_TPERRINJ_MASK ) >> \
708 GRIOMMU_TERRI_TPERRINJ_SHIFT )
709#define GRIOMMU_TERRI_TPERRINJ_SET( _reg, _val ) \
710 ( ( ( _reg ) & ~GRIOMMU_TERRI_TPERRINJ_MASK ) | \
711 ( ( ( _val ) << GRIOMMU_TERRI_TPERRINJ_SHIFT ) & \
712 GRIOMMU_TERRI_TPERRINJ_MASK ) )
713#define GRIOMMU_TERRI_TPERRINJ( _val ) \
714 ( ( ( _val ) << GRIOMMU_TERRI_TPERRINJ_SHIFT ) & \
715 GRIOMMU_TERRI_TPERRINJ_MASK )
716
728#define GRIOMMU_ASMPCTRL_FC 0x40000U
729
730#define GRIOMMU_ASMPCTRL_SC 0x20000U
731
732#define GRIOMMU_ASMPCTRL_MC 0x10000U
733
734#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT 0
735#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK 0xffffU
736#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_GET( _reg ) \
737 ( ( ( _reg ) & GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) >> \
738 GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT )
739#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SET( _reg, _val ) \
740 ( ( ( _reg ) & ~GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) | \
741 ( ( ( _val ) << GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT ) & \
742 GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) )
743#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL( _val ) \
744 ( ( ( _val ) << GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT ) & \
745 GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK )
746
752typedef struct griommu {
756 uint32_t cap0;
757
761 uint32_t cap1;
762
766 uint32_t cap2;
767
768 uint32_t reserved_c_10;
769
773 uint32_t ctrl;
774
778 uint32_t flush;
779
783 uint32_t status;
784
788 uint32_t imask;
789
793 uint32_t ahbfas;
794
795 uint32_t reserved_24_40[ 7 ];
796
800 uint32_t mstcfg_0;
801
802 uint32_t reserved_44_64[ 8 ];
803
807 uint32_t mstcfg_1;
808
809 uint32_t reserved_68_80[ 6 ];
810
814 uint32_t grpctrl_0;
815
816 uint32_t reserved_84_9c[ 6 ];
817
821 uint32_t grpctrl_1;
822
823 uint32_t reserved_a0_c0[ 8 ];
824
828 uint32_t diagctrl;
829
833 uint32_t diagd_0;
834
835 uint32_t reserved_c8_e0[ 6 ];
836
840 uint32_t diagd_1;
841
845 uint32_t diagt;
846
850 uint32_t derri;
851
855 uint32_t terri;
856
857 uint32_t reserved_f0_100[ 4 ];
858
862 uint32_t asmpctrl_0;
863
864 uint32_t reserved_104_10c[ 2 ];
865
869 uint32_t asmpctrl_1;
870} griommu;
871
874#ifdef __cplusplus
875}
876#endif
877
878#endif /* _GRLIB_GRIOMMU_REGS_H */
griommu
This structure defines the GRIOMMU register block memory map.
Definition: griommu-regs.h:752
griommu::cap2
uint32_t cap2
See Capability register 2 (CAP2).
Definition: griommu-regs.h:766
griommu::imask
uint32_t imask
See Interrupt mask register (IMASK).
Definition: griommu-regs.h:788
griommu::derri
uint32_t derri
See Data RAM error injection register (DERRI).
Definition: griommu-regs.h:850
griommu::diagctrl
uint32_t diagctrl
See Diagnostic cache access register (DIAGCTRL).
Definition: griommu-regs.h:828
griommu::diagd_1
uint32_t diagd_1
See Diagnostic cache access data register 0 - 7 (DIAGD).
Definition: griommu-regs.h:840
griommu::grpctrl_1
uint32_t grpctrl_1
See Group control register 0 - 7 (GRPCTRL).
Definition: griommu-regs.h:821
griommu::ahbfas
uint32_t ahbfas
See AHB failing access register (AHBFAS).
Definition: griommu-regs.h:793
griommu::asmpctrl_0
uint32_t asmpctrl_0
See ASMP access control registers 0 - 3 (ASMPCTRL).
Definition: griommu-regs.h:862
griommu::asmpctrl_1
uint32_t asmpctrl_1
See ASMP access control registers 0 - 3 (ASMPCTRL).
Definition: griommu-regs.h:869
griommu::grpctrl_0
uint32_t grpctrl_0
See Group control register 0 - 7 (GRPCTRL).
Definition: griommu-regs.h:814
griommu::status
uint32_t status
See Status register (STATUS).
Definition: griommu-regs.h:783
griommu::cap1
uint32_t cap1
See Capability register 1 (CAP1).
Definition: griommu-regs.h:761
griommu::mstcfg_0
uint32_t mstcfg_0
See Master configuration register 0 - 9 (MSTCFG).
Definition: griommu-regs.h:800
griommu::diagd_0
uint32_t diagd_0
See Diagnostic cache access data register 0 - 7 (DIAGD).
Definition: griommu-regs.h:833
griommu::cap0
uint32_t cap0
See Capability register 0 (CAP0).
Definition: griommu-regs.h:756
griommu::ctrl
uint32_t ctrl
See Control register (CTRL).
Definition: griommu-regs.h:773
griommu::mstcfg_1
uint32_t mstcfg_1
See Master configuration register 0 - 9 (MSTCFG).
Definition: griommu-regs.h:807
griommu::flush
uint32_t flush
See TLB/cache flush register (FLUSH).
Definition: griommu-regs.h:778
griommu::terri
uint32_t terri
See Tag RAM error injection register (TERRI).
Definition: griommu-regs.h:855
griommu::diagt
uint32_t diagt
See Diagnostic cache access tag register (DIAGT).
Definition: griommu-regs.h:845
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