RTEMS 6.1-rc4
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grgpio-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * This file is part of the RTEMS quality process and was automatically
38 * generated. If you find something that needs to be fixed or
39 * worded better please post a report or patch to an RTEMS mailing list
40 * or raise a bug report:
41 *
42 * https://www.rtems.org/bugs.html
43 *
44 * For information on updating and regenerating please refer to the How-To
45 * section in the Software Requirements Engineering chapter of the
46 * RTEMS Software Engineering manual. The manual is provided as a part of
47 * a release. For development sources please refer to the online
48 * documentation at:
49 *
50 * https://docs.rtems.org
51 */
52
53/* Generated from spec:/dev/grlib/if/grgpio-header */
54
55#ifndef _GRLIB_GRGPIO_REGS_H
56#define _GRLIB_GRGPIO_REGS_H
57
58#include <stdint.h>
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64/* Generated from spec:/dev/grlib/if/grgpio */
65
84#define GRGPIO_DATA_DATA_SHIFT 0
85#define GRGPIO_DATA_DATA_MASK 0xffffffffU
86#define GRGPIO_DATA_DATA_GET( _reg ) \
87 ( ( ( _reg ) & GRGPIO_DATA_DATA_MASK ) >> \
88 GRGPIO_DATA_DATA_SHIFT )
89#define GRGPIO_DATA_DATA_SET( _reg, _val ) \
90 ( ( ( _reg ) & ~GRGPIO_DATA_DATA_MASK ) | \
91 ( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & \
92 GRGPIO_DATA_DATA_MASK ) )
93#define GRGPIO_DATA_DATA( _val ) \
94 ( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & \
95 GRGPIO_DATA_DATA_MASK )
96
107#define GRGPIO_OUTPUT_DATA_SHIFT 0
108#define GRGPIO_OUTPUT_DATA_MASK 0xffffffffU
109#define GRGPIO_OUTPUT_DATA_GET( _reg ) \
110 ( ( ( _reg ) & GRGPIO_OUTPUT_DATA_MASK ) >> \
111 GRGPIO_OUTPUT_DATA_SHIFT )
112#define GRGPIO_OUTPUT_DATA_SET( _reg, _val ) \
113 ( ( ( _reg ) & ~GRGPIO_OUTPUT_DATA_MASK ) | \
114 ( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & \
115 GRGPIO_OUTPUT_DATA_MASK ) )
116#define GRGPIO_OUTPUT_DATA( _val ) \
117 ( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & \
118 GRGPIO_OUTPUT_DATA_MASK )
119
130#define GRGPIO_DIRECTION_DIR_SHIFT 0
131#define GRGPIO_DIRECTION_DIR_MASK 0xffffffffU
132#define GRGPIO_DIRECTION_DIR_GET( _reg ) \
133 ( ( ( _reg ) & GRGPIO_DIRECTION_DIR_MASK ) >> \
134 GRGPIO_DIRECTION_DIR_SHIFT )
135#define GRGPIO_DIRECTION_DIR_SET( _reg, _val ) \
136 ( ( ( _reg ) & ~GRGPIO_DIRECTION_DIR_MASK ) | \
137 ( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & \
138 GRGPIO_DIRECTION_DIR_MASK ) )
139#define GRGPIO_DIRECTION_DIR( _val ) \
140 ( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & \
141 GRGPIO_DIRECTION_DIR_MASK )
142
153#define GRGPIO_IMASK_MASK_SHIFT 0
154#define GRGPIO_IMASK_MASK_MASK 0xffffffffU
155#define GRGPIO_IMASK_MASK_GET( _reg ) \
156 ( ( ( _reg ) & GRGPIO_IMASK_MASK_MASK ) >> \
157 GRGPIO_IMASK_MASK_SHIFT )
158#define GRGPIO_IMASK_MASK_SET( _reg, _val ) \
159 ( ( ( _reg ) & ~GRGPIO_IMASK_MASK_MASK ) | \
160 ( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & \
161 GRGPIO_IMASK_MASK_MASK ) )
162#define GRGPIO_IMASK_MASK( _val ) \
163 ( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & \
164 GRGPIO_IMASK_MASK_MASK )
165
176#define GRGPIO_IPOL_POL_SHIFT 0
177#define GRGPIO_IPOL_POL_MASK 0xffffffffU
178#define GRGPIO_IPOL_POL_GET( _reg ) \
179 ( ( ( _reg ) & GRGPIO_IPOL_POL_MASK ) >> \
180 GRGPIO_IPOL_POL_SHIFT )
181#define GRGPIO_IPOL_POL_SET( _reg, _val ) \
182 ( ( ( _reg ) & ~GRGPIO_IPOL_POL_MASK ) | \
183 ( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & \
184 GRGPIO_IPOL_POL_MASK ) )
185#define GRGPIO_IPOL_POL( _val ) \
186 ( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & \
187 GRGPIO_IPOL_POL_MASK )
188
199#define GRGPIO_IEDGE_EDGE_SHIFT 0
200#define GRGPIO_IEDGE_EDGE_MASK 0xffffffffU
201#define GRGPIO_IEDGE_EDGE_GET( _reg ) \
202 ( ( ( _reg ) & GRGPIO_IEDGE_EDGE_MASK ) >> \
203 GRGPIO_IEDGE_EDGE_SHIFT )
204#define GRGPIO_IEDGE_EDGE_SET( _reg, _val ) \
205 ( ( ( _reg ) & ~GRGPIO_IEDGE_EDGE_MASK ) | \
206 ( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & \
207 GRGPIO_IEDGE_EDGE_MASK ) )
208#define GRGPIO_IEDGE_EDGE( _val ) \
209 ( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & \
210 GRGPIO_IEDGE_EDGE_MASK )
211
222#define GRGPIO_BYPASS_BYPASS_SHIFT 0
223#define GRGPIO_BYPASS_BYPASS_MASK 0xffffffffU
224#define GRGPIO_BYPASS_BYPASS_GET( _reg ) \
225 ( ( ( _reg ) & GRGPIO_BYPASS_BYPASS_MASK ) >> \
226 GRGPIO_BYPASS_BYPASS_SHIFT )
227#define GRGPIO_BYPASS_BYPASS_SET( _reg, _val ) \
228 ( ( ( _reg ) & ~GRGPIO_BYPASS_BYPASS_MASK ) | \
229 ( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & \
230 GRGPIO_BYPASS_BYPASS_MASK ) )
231#define GRGPIO_BYPASS_BYPASS( _val ) \
232 ( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & \
233 GRGPIO_BYPASS_BYPASS_MASK )
234
245#define GRGPIO_CAP_PU 0x40000U
246
247#define GRGPIO_CAP_IER 0x20000U
248
249#define GRGPIO_CAP_IFL 0x10000U
250
251#define GRGPIO_CAP_IRQGEN_SHIFT 8
252#define GRGPIO_CAP_IRQGEN_MASK 0x1f00U
253#define GRGPIO_CAP_IRQGEN_GET( _reg ) \
254 ( ( ( _reg ) & GRGPIO_CAP_IRQGEN_MASK ) >> \
255 GRGPIO_CAP_IRQGEN_SHIFT )
256#define GRGPIO_CAP_IRQGEN_SET( _reg, _val ) \
257 ( ( ( _reg ) & ~GRGPIO_CAP_IRQGEN_MASK ) | \
258 ( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & \
259 GRGPIO_CAP_IRQGEN_MASK ) )
260#define GRGPIO_CAP_IRQGEN( _val ) \
261 ( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & \
262 GRGPIO_CAP_IRQGEN_MASK )
263
264#define GRGPIO_CAP_NLINES_SHIFT 0
265#define GRGPIO_CAP_NLINES_MASK 0x1fU
266#define GRGPIO_CAP_NLINES_GET( _reg ) \
267 ( ( ( _reg ) & GRGPIO_CAP_NLINES_MASK ) >> \
268 GRGPIO_CAP_NLINES_SHIFT )
269#define GRGPIO_CAP_NLINES_SET( _reg, _val ) \
270 ( ( ( _reg ) & ~GRGPIO_CAP_NLINES_MASK ) | \
271 ( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & \
272 GRGPIO_CAP_NLINES_MASK ) )
273#define GRGPIO_CAP_NLINES( _val ) \
274 ( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & \
275 GRGPIO_CAP_NLINES_MASK )
276
288#define GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT 24
289#define GRGPIO_IRQMAPR_IRQMAP_I_0_MASK 0x1f000000U
290#define GRGPIO_IRQMAPR_IRQMAP_I_0_GET( _reg ) \
291 ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) >> \
292 GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT )
293#define GRGPIO_IRQMAPR_IRQMAP_I_0_SET( _reg, _val ) \
294 ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) | \
295 ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \
296 GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) )
297#define GRGPIO_IRQMAPR_IRQMAP_I_0( _val ) \
298 ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \
299 GRGPIO_IRQMAPR_IRQMAP_I_0_MASK )
300
301#define GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT 16
302#define GRGPIO_IRQMAPR_IRQMAP_I_1_MASK 0x1f0000U
303#define GRGPIO_IRQMAPR_IRQMAP_I_1_GET( _reg ) \
304 ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) >> \
305 GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT )
306#define GRGPIO_IRQMAPR_IRQMAP_I_1_SET( _reg, _val ) \
307 ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) | \
308 ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) & \
309 GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) )
310#define GRGPIO_IRQMAPR_IRQMAP_I_1( _val ) \
311 ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) & \
312 GRGPIO_IRQMAPR_IRQMAP_I_1_MASK )
313
314#define GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT 8
315#define GRGPIO_IRQMAPR_IRQMAP_I_2_MASK 0x1f00U
316#define GRGPIO_IRQMAPR_IRQMAP_I_2_GET( _reg ) \
317 ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) >> \
318 GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT )
319#define GRGPIO_IRQMAPR_IRQMAP_I_2_SET( _reg, _val ) \
320 ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) | \
321 ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \
322 GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) )
323#define GRGPIO_IRQMAPR_IRQMAP_I_2( _val ) \
324 ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \
325 GRGPIO_IRQMAPR_IRQMAP_I_2_MASK )
326
327#define GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT 0
328#define GRGPIO_IRQMAPR_IRQMAP_I_3_MASK 0x1fU
329#define GRGPIO_IRQMAPR_IRQMAP_I_3_GET( _reg ) \
330 ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) >> \
331 GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT )
332#define GRGPIO_IRQMAPR_IRQMAP_I_3_SET( _reg, _val ) \
333 ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) | \
334 ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \
335 GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) )
336#define GRGPIO_IRQMAPR_IRQMAP_I_3( _val ) \
337 ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \
338 GRGPIO_IRQMAPR_IRQMAP_I_3_MASK )
339
350#define GRGPIO_IAVAIL_IMASK_SHIFT 0
351#define GRGPIO_IAVAIL_IMASK_MASK 0xffffffffU
352#define GRGPIO_IAVAIL_IMASK_GET( _reg ) \
353 ( ( ( _reg ) & GRGPIO_IAVAIL_IMASK_MASK ) >> \
354 GRGPIO_IAVAIL_IMASK_SHIFT )
355#define GRGPIO_IAVAIL_IMASK_SET( _reg, _val ) \
356 ( ( ( _reg ) & ~GRGPIO_IAVAIL_IMASK_MASK ) | \
357 ( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & \
358 GRGPIO_IAVAIL_IMASK_MASK ) )
359#define GRGPIO_IAVAIL_IMASK( _val ) \
360 ( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & \
361 GRGPIO_IAVAIL_IMASK_MASK )
362
373#define GRGPIO_IFLAG_IFLAG_SHIFT 0
374#define GRGPIO_IFLAG_IFLAG_MASK 0xffffffffU
375#define GRGPIO_IFLAG_IFLAG_GET( _reg ) \
376 ( ( ( _reg ) & GRGPIO_IFLAG_IFLAG_MASK ) >> \
377 GRGPIO_IFLAG_IFLAG_SHIFT )
378#define GRGPIO_IFLAG_IFLAG_SET( _reg, _val ) \
379 ( ( ( _reg ) & ~GRGPIO_IFLAG_IFLAG_MASK ) | \
380 ( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & \
381 GRGPIO_IFLAG_IFLAG_MASK ) )
382#define GRGPIO_IFLAG_IFLAG( _val ) \
383 ( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & \
384 GRGPIO_IFLAG_IFLAG_MASK )
385
396#define GRGPIO_IPEN_IPEN_SHIFT 0
397#define GRGPIO_IPEN_IPEN_MASK 0xffffffffU
398#define GRGPIO_IPEN_IPEN_GET( _reg ) \
399 ( ( ( _reg ) & GRGPIO_IPEN_IPEN_MASK ) >> \
400 GRGPIO_IPEN_IPEN_SHIFT )
401#define GRGPIO_IPEN_IPEN_SET( _reg, _val ) \
402 ( ( ( _reg ) & ~GRGPIO_IPEN_IPEN_MASK ) | \
403 ( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & \
404 GRGPIO_IPEN_IPEN_MASK ) )
405#define GRGPIO_IPEN_IPEN( _val ) \
406 ( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & \
407 GRGPIO_IPEN_IPEN_MASK )
408
419#define GRGPIO_PULSE_PULSE_SHIFT 0
420#define GRGPIO_PULSE_PULSE_MASK 0xffffffffU
421#define GRGPIO_PULSE_PULSE_GET( _reg ) \
422 ( ( ( _reg ) & GRGPIO_PULSE_PULSE_MASK ) >> \
423 GRGPIO_PULSE_PULSE_SHIFT )
424#define GRGPIO_PULSE_PULSE_SET( _reg, _val ) \
425 ( ( ( _reg ) & ~GRGPIO_PULSE_PULSE_MASK ) | \
426 ( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & \
427 GRGPIO_PULSE_PULSE_MASK ) )
428#define GRGPIO_PULSE_PULSE( _val ) \
429 ( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & \
430 GRGPIO_PULSE_PULSE_MASK )
431
442#define GRGPIO_LOR_DATA_SHIFT 0
443#define GRGPIO_LOR_DATA_MASK 0xffffffffU
444#define GRGPIO_LOR_DATA_GET( _reg ) \
445 ( ( ( _reg ) & GRGPIO_LOR_DATA_MASK ) >> \
446 GRGPIO_LOR_DATA_SHIFT )
447#define GRGPIO_LOR_DATA_SET( _reg, _val ) \
448 ( ( ( _reg ) & ~GRGPIO_LOR_DATA_MASK ) | \
449 ( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & \
450 GRGPIO_LOR_DATA_MASK ) )
451#define GRGPIO_LOR_DATA( _val ) \
452 ( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & \
453 GRGPIO_LOR_DATA_MASK )
454
465#define GRGPIO_LAND_DATA_SHIFT 0
466#define GRGPIO_LAND_DATA_MASK 0xffffffffU
467#define GRGPIO_LAND_DATA_GET( _reg ) \
468 ( ( ( _reg ) & GRGPIO_LAND_DATA_MASK ) >> \
469 GRGPIO_LAND_DATA_SHIFT )
470#define GRGPIO_LAND_DATA_SET( _reg, _val ) \
471 ( ( ( _reg ) & ~GRGPIO_LAND_DATA_MASK ) | \
472 ( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & \
473 GRGPIO_LAND_DATA_MASK ) )
474#define GRGPIO_LAND_DATA( _val ) \
475 ( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & \
476 GRGPIO_LAND_DATA_MASK )
477
488#define GRGPIO_LXOR_DATA_SHIFT 0
489#define GRGPIO_LXOR_DATA_MASK 0xffffffffU
490#define GRGPIO_LXOR_DATA_GET( _reg ) \
491 ( ( ( _reg ) & GRGPIO_LXOR_DATA_MASK ) >> \
492 GRGPIO_LXOR_DATA_SHIFT )
493#define GRGPIO_LXOR_DATA_SET( _reg, _val ) \
494 ( ( ( _reg ) & ~GRGPIO_LXOR_DATA_MASK ) | \
495 ( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & \
496 GRGPIO_LXOR_DATA_MASK ) )
497#define GRGPIO_LXOR_DATA( _val ) \
498 ( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & \
499 GRGPIO_LXOR_DATA_MASK )
500
506typedef struct grgpio {
510 uint32_t data;
511
515 uint32_t output;
516
520 uint32_t direction;
521
525 uint32_t imask;
526
530 uint32_t ipol;
531
535 uint32_t iedge;
536
540 uint32_t bypass;
541
545 uint32_t cap;
546
550 uint32_t irqmapr[ 8 ];
551
555 uint32_t iavail;
556
560 uint32_t iflag;
561
565 uint32_t ipen;
566
570 uint32_t pulse;
571
572 uint32_t reserved_50_54;
573
577 uint32_t lor_output;
578
583
587 uint32_t lor_imask;
588
589 uint32_t reserved_60_64;
590
594 uint32_t land_output;
595
600
604 uint32_t land_imask;
605
606 uint32_t reserved_70_74;
607
611 uint32_t lxor_output;
612
617
621 uint32_t lxor_imask;
623
626#ifdef __cplusplus
627}
628#endif
629
630#endif /* _GRLIB_GRGPIO_REGS_H */
This structure defines the GRGPIO register block memory map.
Definition: grgpio-regs.h:506
uint32_t lor_imask
See Logical-OR registers (LOR).
Definition: grgpio-regs.h:587
uint32_t land_output
See Logical-AND registers (LAND).
Definition: grgpio-regs.h:594
uint32_t lxor_output
See Logical-XOR registers (LXOR).
Definition: grgpio-regs.h:611
uint32_t output
See I/O port output register (OUTPUT).
Definition: grgpio-regs.h:515
uint32_t data
See I/O port data register (DATA).
Definition: grgpio-regs.h:510
uint32_t land_imask
See Logical-AND registers (LAND).
Definition: grgpio-regs.h:604
uint32_t iedge
See Interrupt edge register (IEDGE).
Definition: grgpio-regs.h:535
uint32_t pulse
See Pulse register (PULSE).
Definition: grgpio-regs.h:570
uint32_t lxor_imask
See Logical-XOR registers (LXOR).
Definition: grgpio-regs.h:621
uint32_t imask
See Interrupt mask register (IMASK).
Definition: grgpio-regs.h:525
uint32_t iavail
See Interrupt available register (IAVAIL).
Definition: grgpio-regs.h:555
uint32_t direction
See I/O port direction register (DIRECTION).
Definition: grgpio-regs.h:520
uint32_t irqmapr[8]
See Interrupt map register n, where n = 0 .. 3 (IRQMAPR).
Definition: grgpio-regs.h:550
uint32_t ipen
See Interrupt enable register (IPEN).
Definition: grgpio-regs.h:565
uint32_t lor_output
See Logical-OR registers (LOR).
Definition: grgpio-regs.h:577
uint32_t bypass
See Bypass register (BYPASS).
Definition: grgpio-regs.h:540
uint32_t lxor_direction
See Logical-XOR registers (LXOR).
Definition: grgpio-regs.h:616
uint32_t iflag
See Interrupt flag register (IFLAG).
Definition: grgpio-regs.h:560
uint32_t lor_direction
See Logical-OR registers (LOR).
Definition: grgpio-regs.h:582
uint32_t land_direction
See Logical-AND registers (LAND).
Definition: grgpio-regs.h:599
uint32_t cap
See Capability register (CAP).
Definition: grgpio-regs.h:545
uint32_t ipol
See Interrupt polarity register (IPOL).
Definition: grgpio-regs.h:530