RTEMS 6.1-rc4
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grethgbit-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * This file is part of the RTEMS quality process and was automatically
38 * generated. If you find something that needs to be fixed or
39 * worded better please post a report or patch to an RTEMS mailing list
40 * or raise a bug report:
41 *
42 * https://www.rtems.org/bugs.html
43 *
44 * For information on updating and regenerating please refer to the How-To
45 * section in the Software Requirements Engineering chapter of the
46 * RTEMS Software Engineering manual. The manual is provided as a part of
47 * a release. For development sources please refer to the online
48 * documentation at:
49 *
50 * https://docs.rtems.org
51 */
52
53/* Generated from spec:/dev/grlib/if/grethgbit-header */
54
55#ifndef _GRLIB_GRETHGBIT_REGS_H
56#define _GRLIB_GRETHGBIT_REGS_H
57
58#include <stdint.h>
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64/* Generated from spec:/dev/grlib/if/grethgbit */
65
84#define GRETHGBIT_CR_EA 0x80000000U
85
86#define GRETHGBIT_CR_BS_SHIFT 28
87#define GRETHGBIT_CR_BS_MASK 0x70000000U
88#define GRETHGBIT_CR_BS_GET( _reg ) \
89 ( ( ( _reg ) & GRETHGBIT_CR_BS_MASK ) >> \
90 GRETHGBIT_CR_BS_SHIFT )
91#define GRETHGBIT_CR_BS_SET( _reg, _val ) \
92 ( ( ( _reg ) & ~GRETHGBIT_CR_BS_MASK ) | \
93 ( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \
94 GRETHGBIT_CR_BS_MASK ) )
95#define GRETHGBIT_CR_BS( _val ) \
96 ( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \
97 GRETHGBIT_CR_BS_MASK )
98
99#define GRETHGBIT_CR_GA 0x8000000U
100
101#define GRETHGBIT_CR_MA 0x4000000U
102
103#define GRETHGBIT_CR_MC 0x2000000U
104
105#define GRETHGBIT_CR_ED 0x4000U
106
107#define GRETHGBIT_CR_RD 0x2000U
108
109#define GRETHGBIT_CR_DD 0x1000U
110
111#define GRETHGBIT_CR_ME 0x800U
112
113#define GRETHGBIT_CR_PI 0x400U
114
115#define GRETHGBIT_CR_BM 0x200U
116
117#define GRETHGBIT_CR_GB 0x100U
118
119#define GRETHGBIT_CR_SP 0x80U
120
121#define GRETHGBIT_CR_RS 0x40U
122
123#define GRETHGBIT_CR_PM 0x20U
124
125#define GRETHGBIT_CR_FD 0x10U
126
127#define GRETHGBIT_CR_RI 0x8U
128
129#define GRETHGBIT_CR_TI 0x4U
130
131#define GRETHGBIT_CR_RE 0x2U
132
133#define GRETHGBIT_CR_TE 0x1U
134
145#define GRETHGBIT_SR_PS 0x100U
146
147#define GRETHGBIT_SR_IA 0x80U
148
149#define GRETHGBIT_SR_TS 0x40U
150
151#define GRETHGBIT_SR_TA 0x20U
152
153#define GRETHGBIT_SR_RA 0x10U
154
155#define GRETHGBIT_SR_TI 0x8U
156
157#define GRETHGBIT_SR_RI 0x4U
158
159#define GRETHGBIT_SR_TE 0x2U
160
161#define GRETHGBIT_SR_RE 0x1U
162
173#define GRETHGBIT_MACMSB_MSB_SHIFT 0
174#define GRETHGBIT_MACMSB_MSB_MASK 0xffffU
175#define GRETHGBIT_MACMSB_MSB_GET( _reg ) \
176 ( ( ( _reg ) & GRETHGBIT_MACMSB_MSB_MASK ) >> \
177 GRETHGBIT_MACMSB_MSB_SHIFT )
178#define GRETHGBIT_MACMSB_MSB_SET( _reg, _val ) \
179 ( ( ( _reg ) & ~GRETHGBIT_MACMSB_MSB_MASK ) | \
180 ( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \
181 GRETHGBIT_MACMSB_MSB_MASK ) )
182#define GRETHGBIT_MACMSB_MSB( _val ) \
183 ( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \
184 GRETHGBIT_MACMSB_MSB_MASK )
185
196#define GRETHGBIT_MACLSB_LSB_SHIFT 0
197#define GRETHGBIT_MACLSB_LSB_MASK 0xffffffffU
198#define GRETHGBIT_MACLSB_LSB_GET( _reg ) \
199 ( ( ( _reg ) & GRETHGBIT_MACLSB_LSB_MASK ) >> \
200 GRETHGBIT_MACLSB_LSB_SHIFT )
201#define GRETHGBIT_MACLSB_LSB_SET( _reg, _val ) \
202 ( ( ( _reg ) & ~GRETHGBIT_MACLSB_LSB_MASK ) | \
203 ( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \
204 GRETHGBIT_MACLSB_LSB_MASK ) )
205#define GRETHGBIT_MACLSB_LSB( _val ) \
206 ( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \
207 GRETHGBIT_MACLSB_LSB_MASK )
208
219#define GRETHGBIT_MDIO_DATA_SHIFT 16
220#define GRETHGBIT_MDIO_DATA_MASK 0xffff0000U
221#define GRETHGBIT_MDIO_DATA_GET( _reg ) \
222 ( ( ( _reg ) & GRETHGBIT_MDIO_DATA_MASK ) >> \
223 GRETHGBIT_MDIO_DATA_SHIFT )
224#define GRETHGBIT_MDIO_DATA_SET( _reg, _val ) \
225 ( ( ( _reg ) & ~GRETHGBIT_MDIO_DATA_MASK ) | \
226 ( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \
227 GRETHGBIT_MDIO_DATA_MASK ) )
228#define GRETHGBIT_MDIO_DATA( _val ) \
229 ( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \
230 GRETHGBIT_MDIO_DATA_MASK )
231
232#define GRETHGBIT_MDIO_PHYADDR_SHIFT 11
233#define GRETHGBIT_MDIO_PHYADDR_MASK 0xf800U
234#define GRETHGBIT_MDIO_PHYADDR_GET( _reg ) \
235 ( ( ( _reg ) & GRETHGBIT_MDIO_PHYADDR_MASK ) >> \
236 GRETHGBIT_MDIO_PHYADDR_SHIFT )
237#define GRETHGBIT_MDIO_PHYADDR_SET( _reg, _val ) \
238 ( ( ( _reg ) & ~GRETHGBIT_MDIO_PHYADDR_MASK ) | \
239 ( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \
240 GRETHGBIT_MDIO_PHYADDR_MASK ) )
241#define GRETHGBIT_MDIO_PHYADDR( _val ) \
242 ( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \
243 GRETHGBIT_MDIO_PHYADDR_MASK )
244
245#define GRETHGBIT_MDIO_REGADDR_SHIFT 6
246#define GRETHGBIT_MDIO_REGADDR_MASK 0x7c0U
247#define GRETHGBIT_MDIO_REGADDR_GET( _reg ) \
248 ( ( ( _reg ) & GRETHGBIT_MDIO_REGADDR_MASK ) >> \
249 GRETHGBIT_MDIO_REGADDR_SHIFT )
250#define GRETHGBIT_MDIO_REGADDR_SET( _reg, _val ) \
251 ( ( ( _reg ) & ~GRETHGBIT_MDIO_REGADDR_MASK ) | \
252 ( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \
253 GRETHGBIT_MDIO_REGADDR_MASK ) )
254#define GRETHGBIT_MDIO_REGADDR( _val ) \
255 ( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \
256 GRETHGBIT_MDIO_REGADDR_MASK )
257
258#define GRETHGBIT_MDIO_BU 0x8U
259
260#define GRETHGBIT_MDIO_LF 0x4U
261
262#define GRETHGBIT_MDIO_RD 0x2U
263
264#define GRETHGBIT_MDIO_WR 0x1U
265
277#define GRETHGBIT_TDTBA_BASEADDR_SHIFT 10
278#define GRETHGBIT_TDTBA_BASEADDR_MASK 0xfffffc00U
279#define GRETHGBIT_TDTBA_BASEADDR_GET( _reg ) \
280 ( ( ( _reg ) & GRETHGBIT_TDTBA_BASEADDR_MASK ) >> \
281 GRETHGBIT_TDTBA_BASEADDR_SHIFT )
282#define GRETHGBIT_TDTBA_BASEADDR_SET( _reg, _val ) \
283 ( ( ( _reg ) & ~GRETHGBIT_TDTBA_BASEADDR_MASK ) | \
284 ( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \
285 GRETHGBIT_TDTBA_BASEADDR_MASK ) )
286#define GRETHGBIT_TDTBA_BASEADDR( _val ) \
287 ( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \
288 GRETHGBIT_TDTBA_BASEADDR_MASK )
289
290#define GRETHGBIT_TDTBA_DESCPNT_SHIFT 3
291#define GRETHGBIT_TDTBA_DESCPNT_MASK 0x3f8U
292#define GRETHGBIT_TDTBA_DESCPNT_GET( _reg ) \
293 ( ( ( _reg ) & GRETHGBIT_TDTBA_DESCPNT_MASK ) >> \
294 GRETHGBIT_TDTBA_DESCPNT_SHIFT )
295#define GRETHGBIT_TDTBA_DESCPNT_SET( _reg, _val ) \
296 ( ( ( _reg ) & ~GRETHGBIT_TDTBA_DESCPNT_MASK ) | \
297 ( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \
298 GRETHGBIT_TDTBA_DESCPNT_MASK ) )
299#define GRETHGBIT_TDTBA_DESCPNT( _val ) \
300 ( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \
301 GRETHGBIT_TDTBA_DESCPNT_MASK )
302
314#define GRETHGBIT_RDTBA_BASEADDR_SHIFT 10
315#define GRETHGBIT_RDTBA_BASEADDR_MASK 0xfffffc00U
316#define GRETHGBIT_RDTBA_BASEADDR_GET( _reg ) \
317 ( ( ( _reg ) & GRETHGBIT_RDTBA_BASEADDR_MASK ) >> \
318 GRETHGBIT_RDTBA_BASEADDR_SHIFT )
319#define GRETHGBIT_RDTBA_BASEADDR_SET( _reg, _val ) \
320 ( ( ( _reg ) & ~GRETHGBIT_RDTBA_BASEADDR_MASK ) | \
321 ( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \
322 GRETHGBIT_RDTBA_BASEADDR_MASK ) )
323#define GRETHGBIT_RDTBA_BASEADDR( _val ) \
324 ( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \
325 GRETHGBIT_RDTBA_BASEADDR_MASK )
326
327#define GRETHGBIT_RDTBA_DESCPNT_SHIFT 3
328#define GRETHGBIT_RDTBA_DESCPNT_MASK 0x3f8U
329#define GRETHGBIT_RDTBA_DESCPNT_GET( _reg ) \
330 ( ( ( _reg ) & GRETHGBIT_RDTBA_DESCPNT_MASK ) >> \
331 GRETHGBIT_RDTBA_DESCPNT_SHIFT )
332#define GRETHGBIT_RDTBA_DESCPNT_SET( _reg, _val ) \
333 ( ( ( _reg ) & ~GRETHGBIT_RDTBA_DESCPNT_MASK ) | \
334 ( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \
335 GRETHGBIT_RDTBA_DESCPNT_MASK ) )
336#define GRETHGBIT_RDTBA_DESCPNT( _val ) \
337 ( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \
338 GRETHGBIT_RDTBA_DESCPNT_MASK )
339
350#define GRETHGBIT_EDCLMACMSB_MSB_SHIFT 0
351#define GRETHGBIT_EDCLMACMSB_MSB_MASK 0xffffU
352#define GRETHGBIT_EDCLMACMSB_MSB_GET( _reg ) \
353 ( ( ( _reg ) & GRETHGBIT_EDCLMACMSB_MSB_MASK ) >> \
354 GRETHGBIT_EDCLMACMSB_MSB_SHIFT )
355#define GRETHGBIT_EDCLMACMSB_MSB_SET( _reg, _val ) \
356 ( ( ( _reg ) & ~GRETHGBIT_EDCLMACMSB_MSB_MASK ) | \
357 ( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \
358 GRETHGBIT_EDCLMACMSB_MSB_MASK ) )
359#define GRETHGBIT_EDCLMACMSB_MSB( _val ) \
360 ( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \
361 GRETHGBIT_EDCLMACMSB_MSB_MASK )
362
373#define GRETHGBIT_EDCLMACLSB_LSB_SHIFT 0
374#define GRETHGBIT_EDCLMACLSB_LSB_MASK 0xffffffffU
375#define GRETHGBIT_EDCLMACLSB_LSB_GET( _reg ) \
376 ( ( ( _reg ) & GRETHGBIT_EDCLMACLSB_LSB_MASK ) >> \
377 GRETHGBIT_EDCLMACLSB_LSB_SHIFT )
378#define GRETHGBIT_EDCLMACLSB_LSB_SET( _reg, _val ) \
379 ( ( ( _reg ) & ~GRETHGBIT_EDCLMACLSB_LSB_MASK ) | \
380 ( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \
381 GRETHGBIT_EDCLMACLSB_LSB_MASK ) )
382#define GRETHGBIT_EDCLMACLSB_LSB( _val ) \
383 ( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \
384 GRETHGBIT_EDCLMACLSB_LSB_MASK )
385
391typedef struct grethgbit {
395 uint32_t cr;
396
400 uint32_t sr;
401
405 uint32_t macmsb;
406
410 uint32_t maclsb;
411
415 uint32_t mdio;
416
420 uint32_t tdtba;
421
425 uint32_t rdtba;
426
427 uint32_t reserved_1c_28[ 3 ];
428
432 uint32_t edclmacmsb;
433
437 uint32_t edclmaclsb;
439
442#ifdef __cplusplus
443}
444#endif
445
446#endif /* _GRLIB_GRETHGBIT_REGS_H */
This structure defines the GRETH_GBIT register block memory map.
Definition: grethgbit-regs.h:391
uint32_t tdtba
See transmitter descriptor table base address register. (TDTBA).
Definition: grethgbit-regs.h:420
uint32_t sr
See status register. (SR).
Definition: grethgbit-regs.h:400
uint32_t edclmaclsb
See EDCL MAC address LSB. (EDCLMACLSB).
Definition: grethgbit-regs.h:437
uint32_t mdio
See MDIO control/status register. (MDIO).
Definition: grethgbit-regs.h:415
uint32_t cr
See control register (CR).
Definition: grethgbit-regs.h:395
uint32_t rdtba
See receiver descriptor table base address register. (RDTBA).
Definition: grethgbit-regs.h:425
uint32_t maclsb
See MAC address LSB. (MACLSB).
Definition: grethgbit-regs.h:410
uint32_t macmsb
See MAC address MSB. (MACMSB).
Definition: grethgbit-regs.h:405
uint32_t edclmacmsb
See EDCL MAC address MSB. (EDCLMACMSB).
Definition: grethgbit-regs.h:432