RTEMS 6.1-rc4
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grcan-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * This file is part of the RTEMS quality process and was automatically
38 * generated. If you find something that needs to be fixed or
39 * worded better please post a report or patch to an RTEMS mailing list
40 * or raise a bug report:
41 *
42 * https://www.rtems.org/bugs.html
43 *
44 * For information on updating and regenerating please refer to the How-To
45 * section in the Software Requirements Engineering chapter of the
46 * RTEMS Software Engineering manual. The manual is provided as a part of
47 * a release. For development sources please refer to the online
48 * documentation at:
49 *
50 * https://docs.rtems.org
51 */
52
53/* Generated from spec:/dev/grlib/if/grcan-header */
54
55#ifndef _GRLIB_GRCAN_REGS_H
56#define _GRLIB_GRCAN_REGS_H
57
58#include <stdint.h>
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64/* Generated from spec:/dev/grlib/if/grcan */
65
84#define GRCAN_CANCONF_SCALER_SHIFT 24
85#define GRCAN_CANCONF_SCALER_MASK 0xff000000U
86#define GRCAN_CANCONF_SCALER_GET( _reg ) \
87 ( ( ( _reg ) & GRCAN_CANCONF_SCALER_MASK ) >> \
88 GRCAN_CANCONF_SCALER_SHIFT )
89#define GRCAN_CANCONF_SCALER_SET( _reg, _val ) \
90 ( ( ( _reg ) & ~GRCAN_CANCONF_SCALER_MASK ) | \
91 ( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & \
92 GRCAN_CANCONF_SCALER_MASK ) )
93#define GRCAN_CANCONF_SCALER( _val ) \
94 ( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & \
95 GRCAN_CANCONF_SCALER_MASK )
96
97#define GRCAN_CANCONF_PS1_SHIFT 20
98#define GRCAN_CANCONF_PS1_MASK 0xf00000U
99#define GRCAN_CANCONF_PS1_GET( _reg ) \
100 ( ( ( _reg ) & GRCAN_CANCONF_PS1_MASK ) >> \
101 GRCAN_CANCONF_PS1_SHIFT )
102#define GRCAN_CANCONF_PS1_SET( _reg, _val ) \
103 ( ( ( _reg ) & ~GRCAN_CANCONF_PS1_MASK ) | \
104 ( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & \
105 GRCAN_CANCONF_PS1_MASK ) )
106#define GRCAN_CANCONF_PS1( _val ) \
107 ( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & \
108 GRCAN_CANCONF_PS1_MASK )
109
110#define GRCAN_CANCONF_PS2_SHIFT 16
111#define GRCAN_CANCONF_PS2_MASK 0xf0000U
112#define GRCAN_CANCONF_PS2_GET( _reg ) \
113 ( ( ( _reg ) & GRCAN_CANCONF_PS2_MASK ) >> \
114 GRCAN_CANCONF_PS2_SHIFT )
115#define GRCAN_CANCONF_PS2_SET( _reg, _val ) \
116 ( ( ( _reg ) & ~GRCAN_CANCONF_PS2_MASK ) | \
117 ( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & \
118 GRCAN_CANCONF_PS2_MASK ) )
119#define GRCAN_CANCONF_PS2( _val ) \
120 ( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & \
121 GRCAN_CANCONF_PS2_MASK )
122
123#define GRCAN_CANCONF_RSJ_SHIFT 12
124#define GRCAN_CANCONF_RSJ_MASK 0x7000U
125#define GRCAN_CANCONF_RSJ_GET( _reg ) \
126 ( ( ( _reg ) & GRCAN_CANCONF_RSJ_MASK ) >> \
127 GRCAN_CANCONF_RSJ_SHIFT )
128#define GRCAN_CANCONF_RSJ_SET( _reg, _val ) \
129 ( ( ( _reg ) & ~GRCAN_CANCONF_RSJ_MASK ) | \
130 ( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & \
131 GRCAN_CANCONF_RSJ_MASK ) )
132#define GRCAN_CANCONF_RSJ( _val ) \
133 ( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & \
134 GRCAN_CANCONF_RSJ_MASK )
135
136#define GRCAN_CANCONF_BPR_SHIFT 8
137#define GRCAN_CANCONF_BPR_MASK 0x300U
138#define GRCAN_CANCONF_BPR_GET( _reg ) \
139 ( ( ( _reg ) & GRCAN_CANCONF_BPR_MASK ) >> \
140 GRCAN_CANCONF_BPR_SHIFT )
141#define GRCAN_CANCONF_BPR_SET( _reg, _val ) \
142 ( ( ( _reg ) & ~GRCAN_CANCONF_BPR_MASK ) | \
143 ( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & \
144 GRCAN_CANCONF_BPR_MASK ) )
145#define GRCAN_CANCONF_BPR( _val ) \
146 ( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & \
147 GRCAN_CANCONF_BPR_MASK )
148
149#define GRCAN_CANCONF_SAM 0x20U
150
151#define GRCAN_CANCONF_SILNT 0x10U
152
153#define GRCAN_CANCONF_SELECT 0x8U
154
155#define GRCAN_CANCONF_ENABLE1 0x4U
156
157#define GRCAN_CANCONF_ENABLE0 0x2U
158
159#define GRCAN_CANCONF_ABORT 0x1U
160
171#define GRCAN_CANSTAT_TXCHANNELS_SHIFT 28
172#define GRCAN_CANSTAT_TXCHANNELS_MASK 0xf0000000U
173#define GRCAN_CANSTAT_TXCHANNELS_GET( _reg ) \
174 ( ( ( _reg ) & GRCAN_CANSTAT_TXCHANNELS_MASK ) >> \
175 GRCAN_CANSTAT_TXCHANNELS_SHIFT )
176#define GRCAN_CANSTAT_TXCHANNELS_SET( _reg, _val ) \
177 ( ( ( _reg ) & ~GRCAN_CANSTAT_TXCHANNELS_MASK ) | \
178 ( ( ( _val ) << GRCAN_CANSTAT_TXCHANNELS_SHIFT ) & \
179 GRCAN_CANSTAT_TXCHANNELS_MASK ) )
180#define GRCAN_CANSTAT_TXCHANNELS( _val ) \
181 ( ( ( _val ) << GRCAN_CANSTAT_TXCHANNELS_SHIFT ) & \
182 GRCAN_CANSTAT_TXCHANNELS_MASK )
183
184#define GRCAN_CANSTAT_RXCHANNELS_SHIFT 24
185#define GRCAN_CANSTAT_RXCHANNELS_MASK 0xf000000U
186#define GRCAN_CANSTAT_RXCHANNELS_GET( _reg ) \
187 ( ( ( _reg ) & GRCAN_CANSTAT_RXCHANNELS_MASK ) >> \
188 GRCAN_CANSTAT_RXCHANNELS_SHIFT )
189#define GRCAN_CANSTAT_RXCHANNELS_SET( _reg, _val ) \
190 ( ( ( _reg ) & ~GRCAN_CANSTAT_RXCHANNELS_MASK ) | \
191 ( ( ( _val ) << GRCAN_CANSTAT_RXCHANNELS_SHIFT ) & \
192 GRCAN_CANSTAT_RXCHANNELS_MASK ) )
193#define GRCAN_CANSTAT_RXCHANNELS( _val ) \
194 ( ( ( _val ) << GRCAN_CANSTAT_RXCHANNELS_SHIFT ) & \
195 GRCAN_CANSTAT_RXCHANNELS_MASK )
196
197#define GRCAN_CANSTAT_TXERRCNT_SHIFT 16
198#define GRCAN_CANSTAT_TXERRCNT_MASK 0xff0000U
199#define GRCAN_CANSTAT_TXERRCNT_GET( _reg ) \
200 ( ( ( _reg ) & GRCAN_CANSTAT_TXERRCNT_MASK ) >> \
201 GRCAN_CANSTAT_TXERRCNT_SHIFT )
202#define GRCAN_CANSTAT_TXERRCNT_SET( _reg, _val ) \
203 ( ( ( _reg ) & ~GRCAN_CANSTAT_TXERRCNT_MASK ) | \
204 ( ( ( _val ) << GRCAN_CANSTAT_TXERRCNT_SHIFT ) & \
205 GRCAN_CANSTAT_TXERRCNT_MASK ) )
206#define GRCAN_CANSTAT_TXERRCNT( _val ) \
207 ( ( ( _val ) << GRCAN_CANSTAT_TXERRCNT_SHIFT ) & \
208 GRCAN_CANSTAT_TXERRCNT_MASK )
209
210#define GRCAN_CANSTAT_RXERRCNT_SHIFT 8
211#define GRCAN_CANSTAT_RXERRCNT_MASK 0xff00U
212#define GRCAN_CANSTAT_RXERRCNT_GET( _reg ) \
213 ( ( ( _reg ) & GRCAN_CANSTAT_RXERRCNT_MASK ) >> \
214 GRCAN_CANSTAT_RXERRCNT_SHIFT )
215#define GRCAN_CANSTAT_RXERRCNT_SET( _reg, _val ) \
216 ( ( ( _reg ) & ~GRCAN_CANSTAT_RXERRCNT_MASK ) | \
217 ( ( ( _val ) << GRCAN_CANSTAT_RXERRCNT_SHIFT ) & \
218 GRCAN_CANSTAT_RXERRCNT_MASK ) )
219#define GRCAN_CANSTAT_RXERRCNT( _val ) \
220 ( ( ( _val ) << GRCAN_CANSTAT_RXERRCNT_SHIFT ) & \
221 GRCAN_CANSTAT_RXERRCNT_MASK )
222
223#define GRCAN_CANSTAT_ACTIVE 0x10U
224
225#define GRCAN_CANSTAT_AHBERR 0x8U
226
227#define GRCAN_CANSTAT_OR 0x4U
228
229#define GRCAN_CANSTAT_OFF 0x2U
230
231#define GRCAN_CANSTAT_PASS 0x1U
232
243#define GRCAN_CANCTRL_RESET 0x2U
244
245#define GRCAN_CANCTRL_ENABLE 0x1U
246
257#define GRCAN_CANMASK_MASK_SHIFT 0
258#define GRCAN_CANMASK_MASK_MASK 0x1fffffffU
259#define GRCAN_CANMASK_MASK_GET( _reg ) \
260 ( ( ( _reg ) & GRCAN_CANMASK_MASK_MASK ) >> \
261 GRCAN_CANMASK_MASK_SHIFT )
262#define GRCAN_CANMASK_MASK_SET( _reg, _val ) \
263 ( ( ( _reg ) & ~GRCAN_CANMASK_MASK_MASK ) | \
264 ( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & \
265 GRCAN_CANMASK_MASK_MASK ) )
266#define GRCAN_CANMASK_MASK( _val ) \
267 ( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & \
268 GRCAN_CANMASK_MASK_MASK )
269
280#define GRCAN_CANCODE_SYNC_SHIFT 0
281#define GRCAN_CANCODE_SYNC_MASK 0x1fffffffU
282#define GRCAN_CANCODE_SYNC_GET( _reg ) \
283 ( ( ( _reg ) & GRCAN_CANCODE_SYNC_MASK ) >> \
284 GRCAN_CANCODE_SYNC_SHIFT )
285#define GRCAN_CANCODE_SYNC_SET( _reg, _val ) \
286 ( ( ( _reg ) & ~GRCAN_CANCODE_SYNC_MASK ) | \
287 ( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & \
288 GRCAN_CANCODE_SYNC_MASK ) )
289#define GRCAN_CANCODE_SYNC( _val ) \
290 ( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & \
291 GRCAN_CANCODE_SYNC_MASK )
292
304#define GRCAN_CANTXCTRL_SINGLE 0x4U
305
306#define GRCAN_CANTXCTRL_ONGOING 0x2U
307
308#define GRCAN_CANTXCTRL_ENABLE 0x1U
309
321#define GRCAN_CANTXADDR_ADDR_SHIFT 10
322#define GRCAN_CANTXADDR_ADDR_MASK 0xfffffc00U
323#define GRCAN_CANTXADDR_ADDR_GET( _reg ) \
324 ( ( ( _reg ) & GRCAN_CANTXADDR_ADDR_MASK ) >> \
325 GRCAN_CANTXADDR_ADDR_SHIFT )
326#define GRCAN_CANTXADDR_ADDR_SET( _reg, _val ) \
327 ( ( ( _reg ) & ~GRCAN_CANTXADDR_ADDR_MASK ) | \
328 ( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & \
329 GRCAN_CANTXADDR_ADDR_MASK ) )
330#define GRCAN_CANTXADDR_ADDR( _val ) \
331 ( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & \
332 GRCAN_CANTXADDR_ADDR_MASK )
333
345#define GRCAN_CANTXSIZE_SIZE_SHIFT 6
346#define GRCAN_CANTXSIZE_SIZE_MASK 0x1fffc0U
347#define GRCAN_CANTXSIZE_SIZE_GET( _reg ) \
348 ( ( ( _reg ) & GRCAN_CANTXSIZE_SIZE_MASK ) >> \
349 GRCAN_CANTXSIZE_SIZE_SHIFT )
350#define GRCAN_CANTXSIZE_SIZE_SET( _reg, _val ) \
351 ( ( ( _reg ) & ~GRCAN_CANTXSIZE_SIZE_MASK ) | \
352 ( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & \
353 GRCAN_CANTXSIZE_SIZE_MASK ) )
354#define GRCAN_CANTXSIZE_SIZE( _val ) \
355 ( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & \
356 GRCAN_CANTXSIZE_SIZE_MASK )
357
368#define GRCAN_CANTXWR_WRITE_SHIFT 4
369#define GRCAN_CANTXWR_WRITE_MASK 0xffff0U
370#define GRCAN_CANTXWR_WRITE_GET( _reg ) \
371 ( ( ( _reg ) & GRCAN_CANTXWR_WRITE_MASK ) >> \
372 GRCAN_CANTXWR_WRITE_SHIFT )
373#define GRCAN_CANTXWR_WRITE_SET( _reg, _val ) \
374 ( ( ( _reg ) & ~GRCAN_CANTXWR_WRITE_MASK ) | \
375 ( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & \
376 GRCAN_CANTXWR_WRITE_MASK ) )
377#define GRCAN_CANTXWR_WRITE( _val ) \
378 ( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & \
379 GRCAN_CANTXWR_WRITE_MASK )
380
391#define GRCAN_CANTXRD_READ_SHIFT 4
392#define GRCAN_CANTXRD_READ_MASK 0xffff0U
393#define GRCAN_CANTXRD_READ_GET( _reg ) \
394 ( ( ( _reg ) & GRCAN_CANTXRD_READ_MASK ) >> \
395 GRCAN_CANTXRD_READ_SHIFT )
396#define GRCAN_CANTXRD_READ_SET( _reg, _val ) \
397 ( ( ( _reg ) & ~GRCAN_CANTXRD_READ_MASK ) | \
398 ( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & \
399 GRCAN_CANTXRD_READ_MASK ) )
400#define GRCAN_CANTXRD_READ( _val ) \
401 ( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & \
402 GRCAN_CANTXRD_READ_MASK )
403
415#define GRCAN_CANTXIRQ_IRQ_SHIFT 4
416#define GRCAN_CANTXIRQ_IRQ_MASK 0xffff0U
417#define GRCAN_CANTXIRQ_IRQ_GET( _reg ) \
418 ( ( ( _reg ) & GRCAN_CANTXIRQ_IRQ_MASK ) >> \
419 GRCAN_CANTXIRQ_IRQ_SHIFT )
420#define GRCAN_CANTXIRQ_IRQ_SET( _reg, _val ) \
421 ( ( ( _reg ) & ~GRCAN_CANTXIRQ_IRQ_MASK ) | \
422 ( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \
423 GRCAN_CANTXIRQ_IRQ_MASK ) )
424#define GRCAN_CANTXIRQ_IRQ( _val ) \
425 ( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \
426 GRCAN_CANTXIRQ_IRQ_MASK )
427
439#define GRCAN_CANRXCTRL_ONGOING 0x2U
440
441#define GRCAN_CANRXCTRL_ENABLE 0x1U
442
454#define GRCAN_CANRXADDR_ADDR_SHIFT 10
455#define GRCAN_CANRXADDR_ADDR_MASK 0xfffffc00U
456#define GRCAN_CANRXADDR_ADDR_GET( _reg ) \
457 ( ( ( _reg ) & GRCAN_CANRXADDR_ADDR_MASK ) >> \
458 GRCAN_CANRXADDR_ADDR_SHIFT )
459#define GRCAN_CANRXADDR_ADDR_SET( _reg, _val ) \
460 ( ( ( _reg ) & ~GRCAN_CANRXADDR_ADDR_MASK ) | \
461 ( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & \
462 GRCAN_CANRXADDR_ADDR_MASK ) )
463#define GRCAN_CANRXADDR_ADDR( _val ) \
464 ( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & \
465 GRCAN_CANRXADDR_ADDR_MASK )
466
478#define GRCAN_CANRXSIZE_SIZE_SHIFT 6
479#define GRCAN_CANRXSIZE_SIZE_MASK 0x1fffc0U
480#define GRCAN_CANRXSIZE_SIZE_GET( _reg ) \
481 ( ( ( _reg ) & GRCAN_CANRXSIZE_SIZE_MASK ) >> \
482 GRCAN_CANRXSIZE_SIZE_SHIFT )
483#define GRCAN_CANRXSIZE_SIZE_SET( _reg, _val ) \
484 ( ( ( _reg ) & ~GRCAN_CANRXSIZE_SIZE_MASK ) | \
485 ( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & \
486 GRCAN_CANRXSIZE_SIZE_MASK ) )
487#define GRCAN_CANRXSIZE_SIZE( _val ) \
488 ( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & \
489 GRCAN_CANRXSIZE_SIZE_MASK )
490
501#define GRCAN_CANRXWR_WRITE_SHIFT 4
502#define GRCAN_CANRXWR_WRITE_MASK 0xffff0U
503#define GRCAN_CANRXWR_WRITE_GET( _reg ) \
504 ( ( ( _reg ) & GRCAN_CANRXWR_WRITE_MASK ) >> \
505 GRCAN_CANRXWR_WRITE_SHIFT )
506#define GRCAN_CANRXWR_WRITE_SET( _reg, _val ) \
507 ( ( ( _reg ) & ~GRCAN_CANRXWR_WRITE_MASK ) | \
508 ( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & \
509 GRCAN_CANRXWR_WRITE_MASK ) )
510#define GRCAN_CANRXWR_WRITE( _val ) \
511 ( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & \
512 GRCAN_CANRXWR_WRITE_MASK )
513
524#define GRCAN_CANRXRD_READ_SHIFT 4
525#define GRCAN_CANRXRD_READ_MASK 0xffff0U
526#define GRCAN_CANRXRD_READ_GET( _reg ) \
527 ( ( ( _reg ) & GRCAN_CANRXRD_READ_MASK ) >> \
528 GRCAN_CANRXRD_READ_SHIFT )
529#define GRCAN_CANRXRD_READ_SET( _reg, _val ) \
530 ( ( ( _reg ) & ~GRCAN_CANRXRD_READ_MASK ) | \
531 ( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & \
532 GRCAN_CANRXRD_READ_MASK ) )
533#define GRCAN_CANRXRD_READ( _val ) \
534 ( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & \
535 GRCAN_CANRXRD_READ_MASK )
536
548#define GRCAN_CANRXIRQ_IRQ_SHIFT 4
549#define GRCAN_CANRXIRQ_IRQ_MASK 0xffff0U
550#define GRCAN_CANRXIRQ_IRQ_GET( _reg ) \
551 ( ( ( _reg ) & GRCAN_CANRXIRQ_IRQ_MASK ) >> \
552 GRCAN_CANRXIRQ_IRQ_SHIFT )
553#define GRCAN_CANRXIRQ_IRQ_SET( _reg, _val ) \
554 ( ( ( _reg ) & ~GRCAN_CANRXIRQ_IRQ_MASK ) | \
555 ( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & \
556 GRCAN_CANRXIRQ_IRQ_MASK ) )
557#define GRCAN_CANRXIRQ_IRQ( _val ) \
558 ( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & \
559 GRCAN_CANRXIRQ_IRQ_MASK )
560
572#define GRCAN_CANRXMASK_AM_SHIFT 0
573#define GRCAN_CANRXMASK_AM_MASK 0x1fffffffU
574#define GRCAN_CANRXMASK_AM_GET( _reg ) \
575 ( ( ( _reg ) & GRCAN_CANRXMASK_AM_MASK ) >> \
576 GRCAN_CANRXMASK_AM_SHIFT )
577#define GRCAN_CANRXMASK_AM_SET( _reg, _val ) \
578 ( ( ( _reg ) & ~GRCAN_CANRXMASK_AM_MASK ) | \
579 ( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & \
580 GRCAN_CANRXMASK_AM_MASK ) )
581#define GRCAN_CANRXMASK_AM( _val ) \
582 ( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & \
583 GRCAN_CANRXMASK_AM_MASK )
584
596#define GRCAN_CANRXCODE_AC_SHIFT 0
597#define GRCAN_CANRXCODE_AC_MASK 0x1fffffffU
598#define GRCAN_CANRXCODE_AC_GET( _reg ) \
599 ( ( ( _reg ) & GRCAN_CANRXCODE_AC_MASK ) >> \
600 GRCAN_CANRXCODE_AC_SHIFT )
601#define GRCAN_CANRXCODE_AC_SET( _reg, _val ) \
602 ( ( ( _reg ) & ~GRCAN_CANRXCODE_AC_MASK ) | \
603 ( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & \
604 GRCAN_CANRXCODE_AC_MASK ) )
605#define GRCAN_CANRXCODE_AC( _val ) \
606 ( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & \
607 GRCAN_CANRXCODE_AC_MASK )
608
614typedef struct grcan {
618 uint32_t canconf;
619
623 uint32_t canstat;
624
628 uint32_t canctrl;
629
630 uint32_t reserved_c_18[ 3 ];
631
635 uint32_t canmask;
636
640 uint32_t cancode;
641
642 uint32_t reserved_20_200[ 120 ];
643
647 uint32_t cantxctrl;
648
652 uint32_t cantxaddr;
653
657 uint32_t cantxsize;
658
662 uint32_t cantxwr;
663
667 uint32_t cantxrd;
668
672 uint32_t cantxirq;
673
674 uint32_t reserved_218_300[ 58 ];
675
679 uint32_t canrxctrl;
680
684 uint32_t canrxaddr;
685
689 uint32_t canrxsize;
690
694 uint32_t canrxwr;
695
699 uint32_t canrxrd;
700
704 uint32_t canrxirq;
705
709 uint32_t canrxmask;
710
714 uint32_t canrxcode;
715} grcan;
716
719#ifdef __cplusplus
720}
721#endif
722
723#endif /* _GRLIB_GRCAN_REGS_H */
grcan
This structure defines the GRCAN register block memory map.
Definition: grcan-regs.h:614
grcan::cantxaddr
uint32_t cantxaddr
See Transmit Channel Address Register (CanTxADDR).
Definition: grcan-regs.h:652
grcan::cantxirq
uint32_t cantxirq
See Transmit Channel Interrupt Register (CanTxIRQ).
Definition: grcan-regs.h:672
grcan::canrxwr
uint32_t canrxwr
See Receive Channel Write Register (CanRxWR).
Definition: grcan-regs.h:694
grcan::cancode
uint32_t cancode
See SYNC Code Filter Register (CanCODE).
Definition: grcan-regs.h:640
grcan::canrxsize
uint32_t canrxsize
See Receive Channel Size Register (CanRxSIZE).
Definition: grcan-regs.h:689
grcan::canrxaddr
uint32_t canrxaddr
See Receive Channel Address Register (CanRxADDR).
Definition: grcan-regs.h:684
grcan::canrxmask
uint32_t canrxmask
See Receive Channel Mask Register (CanRxMASK).
Definition: grcan-regs.h:709
grcan::canrxcode
uint32_t canrxcode
See Receive Channel Code Register (CanRxCODE).
Definition: grcan-regs.h:714
grcan::cantxctrl
uint32_t cantxctrl
See Transmit Channel Control Register (CanTxCTRL).
Definition: grcan-regs.h:647
grcan::cantxwr
uint32_t cantxwr
See Transmit Channel Write Register (CanTxWR).
Definition: grcan-regs.h:662
grcan::canconf
uint32_t canconf
See Configuration Register (CanCONF).
Definition: grcan-regs.h:618
grcan::canrxctrl
uint32_t canrxctrl
See Receive Channel Control Register (CanRxCTRL).
Definition: grcan-regs.h:679
grcan::canrxrd
uint32_t canrxrd
See Receive Channel Read Register (CanRxRD).
Definition: grcan-regs.h:699
grcan::cantxsize
uint32_t cantxsize
See Transmit Channel Size Register (CanTxSIZE).
Definition: grcan-regs.h:657
grcan::cantxrd
uint32_t cantxrd
See Transmit Channel Read Register (CanTxRD).
Definition: grcan-regs.h:667
grcan::canmask
uint32_t canmask
See SYNC Mask Filter Register (CanMASK).
Definition: grcan-regs.h:635
grcan::canrxirq
uint32_t canrxirq
See Receive Channel Interrupt Register (CanRxIRQ).
Definition: grcan-regs.h:704
grcan::canctrl
uint32_t canctrl
See Control Register (CanCTRL).
Definition: grcan-regs.h:628
grcan::canstat
uint32_t canstat
See Status Register (CanSTAT).
Definition: grcan-regs.h:623
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