RTEMS 6.1-rc4
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This header file defines the GR1553B register block interface. More...
#include <stdint.h>
Go to the source code of this file.
Data Structures | |
struct | gr1553b |
This structure defines the GR1553B register block memory map. More... | |
Macros | |
#define | GR1553B_IRQ_BMTOF 0x20000U |
#define | GR1553B_IRQ_BMD 0x10000U |
#define | GR1553B_IRQ_RTTE 0x400U |
#define | GR1553B_IRQ_RTD 0x200U |
#define | GR1553B_IRQ_RTEV 0x100U |
#define | GR1553B_IRQ_BCWK 0x4U |
#define | GR1553B_IRQ_BCD 0x2U |
#define | GR1553B_IRQ_BCEV 0x1U |
#define | GR1553B_IRQE_BMTOE 0x20000U |
#define | GR1553B_IRQE_BMDE 0x10000U |
#define | GR1553B_IRQE_RTTEE 0x400U |
#define | GR1553B_IRQE_RTDE 0x200U |
#define | GR1553B_IRQE_RTEVE 0x100U |
#define | GR1553B_IRQE_BCWKE 0x4U |
#define | GR1553B_IRQE_BCDE 0x2U |
#define | GR1553B_IRQE_BCEVE 0x1U |
#define | GR1553B_HC_MOD 0x80000000U |
#define | GR1553B_HC_CVER 0x1000U |
#define | GR1553B_HC_XKEYS 0x800U |
#define | GR1553B_HC_ENDIAN_SHIFT 9 |
#define | GR1553B_HC_ENDIAN_MASK 0x600U |
#define | GR1553B_HC_ENDIAN_GET(_reg) |
#define | GR1553B_HC_ENDIAN_SET(_reg, _val) |
#define | GR1553B_HC_ENDIAN(_val) |
#define | GR1553B_HC_SCLK 0x100U |
#define | GR1553B_HC_CCFREQ_SHIFT 0 |
#define | GR1553B_HC_CCFREQ_MASK 0xffU |
#define | GR1553B_HC_CCFREQ_GET(_reg) |
#define | GR1553B_HC_CCFREQ_SET(_reg, _val) |
#define | GR1553B_HC_CCFREQ(_val) |
#define | GR1553B_BCSC_BCSUP 0x80000000U |
#define | GR1553B_BCSC_BCFEAT_SHIFT 28 |
#define | GR1553B_BCSC_BCFEAT_MASK 0x70000000U |
#define | GR1553B_BCSC_BCFEAT_GET(_reg) |
#define | GR1553B_BCSC_BCFEAT_SET(_reg, _val) |
#define | GR1553B_BCSC_BCFEAT(_val) |
#define | GR1553B_BCSC_BCCHK 0x10000U |
#define | GR1553B_BCSC_ASADL_SHIFT 11 |
#define | GR1553B_BCSC_ASADL_MASK 0xf800U |
#define | GR1553B_BCSC_ASADL_GET(_reg) |
#define | GR1553B_BCSC_ASADL_SET(_reg, _val) |
#define | GR1553B_BCSC_ASADL(_val) |
#define | GR1553B_BCSC_ASST_SHIFT 8 |
#define | GR1553B_BCSC_ASST_MASK 0x300U |
#define | GR1553B_BCSC_ASST_GET(_reg) |
#define | GR1553B_BCSC_ASST_SET(_reg, _val) |
#define | GR1553B_BCSC_ASST(_val) |
#define | GR1553B_BCSC_SCADL_SHIFT 3 |
#define | GR1553B_BCSC_SCADL_MASK 0xf8U |
#define | GR1553B_BCSC_SCADL_GET(_reg) |
#define | GR1553B_BCSC_SCADL_SET(_reg, _val) |
#define | GR1553B_BCSC_SCADL(_val) |
#define | GR1553B_BCSC_SCST_SHIFT 0 |
#define | GR1553B_BCSC_SCST_MASK 0x7U |
#define | GR1553B_BCSC_SCST_GET(_reg) |
#define | GR1553B_BCSC_SCST_SET(_reg, _val) |
#define | GR1553B_BCSC_SCST(_val) |
#define | GR1553B_BCA_BCKEY_SHIFT 16 |
#define | GR1553B_BCA_BCKEY_MASK 0xffff0000U |
#define | GR1553B_BCA_BCKEY_GET(_reg) |
#define | GR1553B_BCA_BCKEY_SET(_reg, _val) |
#define | GR1553B_BCA_BCKEY(_val) |
#define | GR1553B_BCA_ASSTP 0x200U |
#define | GR1553B_BCA_ASSRT 0x100U |
#define | GR1553B_BCA_CLRT 0x10U |
#define | GR1553B_BCA_SETT 0x8U |
#define | GR1553B_BCA_SCSTP 0x4U |
#define | GR1553B_BCA_SCSUS 0x2U |
#define | GR1553B_BCA_SCSRT 0x1U |
#define | GR1553B_BCTNP_POINTER_SHIFT 0 |
#define | GR1553B_BCTNP_POINTER_MASK 0xffffffffU |
#define | GR1553B_BCTNP_POINTER_GET(_reg) |
#define | GR1553B_BCTNP_POINTER_SET(_reg, _val) |
#define | GR1553B_BCTNP_POINTER(_val) |
#define | GR1553B_BCANP_POINTER_SHIFT 0 |
#define | GR1553B_BCANP_POINTER_MASK 0xffffffffU |
#define | GR1553B_BCANP_POINTER_GET(_reg) |
#define | GR1553B_BCANP_POINTER_SET(_reg, _val) |
#define | GR1553B_BCANP_POINTER(_val) |
#define | GR1553B_BCT_SCTM_SHIFT 0 |
#define | GR1553B_BCT_SCTM_MASK 0xffffffU |
#define | GR1553B_BCT_SCTM_GET(_reg) |
#define | GR1553B_BCT_SCTM_SET(_reg, _val) |
#define | GR1553B_BCT_SCTM(_val) |
#define | GR1553B_BCRP_POSITION_SHIFT 0 |
#define | GR1553B_BCRP_POSITION_MASK 0xffffffffU |
#define | GR1553B_BCRP_POSITION_GET(_reg) |
#define | GR1553B_BCRP_POSITION_SET(_reg, _val) |
#define | GR1553B_BCRP_POSITION(_val) |
#define | GR1553B_BCBS_SWAP_SHIFT 0 |
#define | GR1553B_BCBS_SWAP_MASK 0xffffffffU |
#define | GR1553B_BCBS_SWAP_GET(_reg) |
#define | GR1553B_BCBS_SWAP_SET(_reg, _val) |
#define | GR1553B_BCBS_SWAP(_val) |
#define | GR1553B_BCTCP_POINTER_SHIFT 0 |
#define | GR1553B_BCTCP_POINTER_MASK 0xffffffffU |
#define | GR1553B_BCTCP_POINTER_GET(_reg) |
#define | GR1553B_BCTCP_POINTER_SET(_reg, _val) |
#define | GR1553B_BCTCP_POINTER(_val) |
#define | GR1553B_BCACP_POINTER_SHIFT 0 |
#define | GR1553B_BCACP_POINTER_MASK 0xffffffffU |
#define | GR1553B_BCACP_POINTER_GET(_reg) |
#define | GR1553B_BCACP_POINTER_SET(_reg, _val) |
#define | GR1553B_BCACP_POINTER(_val) |
#define | GR1553B_RTS_RTSUP 0x80000000U |
#define | GR1553B_RTS_ACT 0x8U |
#define | GR1553B_RTS_SHDA 0x4U |
#define | GR1553B_RTS_SHDB 0x2U |
#define | GR1553B_RTS_RUN 0x1U |
#define | GR1553B_RTC_RTKEY_SHIFT 16 |
#define | GR1553B_RTC_RTKEY_MASK 0xffff0000U |
#define | GR1553B_RTC_RTKEY_GET(_reg) |
#define | GR1553B_RTC_RTKEY_SET(_reg, _val) |
#define | GR1553B_RTC_RTKEY(_val) |
#define | GR1553B_RTC_SYS 0x8000U |
#define | GR1553B_RTC_SYDS 0x4000U |
#define | GR1553B_RTC_BRS 0x2000U |
#define | GR1553B_RTC_RTEIS 0x40U |
#define | GR1553B_RTC_RTADDR_SHIFT 1 |
#define | GR1553B_RTC_RTADDR_MASK 0x3eU |
#define | GR1553B_RTC_RTADDR_GET(_reg) |
#define | GR1553B_RTC_RTADDR_SET(_reg, _val) |
#define | GR1553B_RTC_RTADDR(_val) |
#define | GR1553B_RTC_RTEN 0x1U |
#define | GR1553B_RTBS_TFDE 0x100U |
#define | GR1553B_RTBS_SREQ 0x10U |
#define | GR1553B_RTBS_BUSY 0x8U |
#define | GR1553B_RTBS_SSF 0x4U |
#define | GR1553B_RTBS_DBCA 0x2U |
#define | GR1553B_RTBS_TFLG 0x1U |
#define | GR1553B_RTSW_BITW_SHIFT 16 |
#define | GR1553B_RTSW_BITW_MASK 0xffff0000U |
#define | GR1553B_RTSW_BITW_GET(_reg) |
#define | GR1553B_RTSW_BITW_SET(_reg, _val) |
#define | GR1553B_RTSW_BITW(_val) |
#define | GR1553B_RTSW_VECW_SHIFT 0 |
#define | GR1553B_RTSW_VECW_MASK 0xffffU |
#define | GR1553B_RTSW_VECW_GET(_reg) |
#define | GR1553B_RTSW_VECW_SET(_reg, _val) |
#define | GR1553B_RTSW_VECW(_val) |
#define | GR1553B_RTSY_SYTM_SHIFT 16 |
#define | GR1553B_RTSY_SYTM_MASK 0xffff0000U |
#define | GR1553B_RTSY_SYTM_GET(_reg) |
#define | GR1553B_RTSY_SYTM_SET(_reg, _val) |
#define | GR1553B_RTSY_SYTM(_val) |
#define | GR1553B_RTSY_SYD_SHIFT 0 |
#define | GR1553B_RTSY_SYD_MASK 0xffffU |
#define | GR1553B_RTSY_SYD_GET(_reg) |
#define | GR1553B_RTSY_SYD_SET(_reg, _val) |
#define | GR1553B_RTSY_SYD(_val) |
#define | GR1553B_RTSTBA_SATB_SHIFT 9 |
#define | GR1553B_RTSTBA_SATB_MASK 0xfffffe00U |
#define | GR1553B_RTSTBA_SATB_GET(_reg) |
#define | GR1553B_RTSTBA_SATB_SET(_reg, _val) |
#define | GR1553B_RTSTBA_SATB(_val) |
#define | GR1553B_RTMCC_RRTB_SHIFT 28 |
#define | GR1553B_RTMCC_RRTB_MASK 0x30000000U |
#define | GR1553B_RTMCC_RRTB_GET(_reg) |
#define | GR1553B_RTMCC_RRTB_SET(_reg, _val) |
#define | GR1553B_RTMCC_RRTB(_val) |
#define | GR1553B_RTMCC_RRT_SHIFT 26 |
#define | GR1553B_RTMCC_RRT_MASK 0xc000000U |
#define | GR1553B_RTMCC_RRT_GET(_reg) |
#define | GR1553B_RTMCC_RRT_SET(_reg, _val) |
#define | GR1553B_RTMCC_RRT(_val) |
#define | GR1553B_RTMCC_ITFB_SHIFT 24 |
#define | GR1553B_RTMCC_ITFB_MASK 0x3000000U |
#define | GR1553B_RTMCC_ITFB_GET(_reg) |
#define | GR1553B_RTMCC_ITFB_SET(_reg, _val) |
#define | GR1553B_RTMCC_ITFB(_val) |
#define | GR1553B_RTMCC_ITF_SHIFT 22 |
#define | GR1553B_RTMCC_ITF_MASK 0xc00000U |
#define | GR1553B_RTMCC_ITF_GET(_reg) |
#define | GR1553B_RTMCC_ITF_SET(_reg, _val) |
#define | GR1553B_RTMCC_ITF(_val) |
#define | GR1553B_RTMCC_ISTB_SHIFT 20 |
#define | GR1553B_RTMCC_ISTB_MASK 0x300000U |
#define | GR1553B_RTMCC_ISTB_GET(_reg) |
#define | GR1553B_RTMCC_ISTB_SET(_reg, _val) |
#define | GR1553B_RTMCC_ISTB(_val) |
#define | GR1553B_RTMCC_IST_SHIFT 18 |
#define | GR1553B_RTMCC_IST_MASK 0xc0000U |
#define | GR1553B_RTMCC_IST_GET(_reg) |
#define | GR1553B_RTMCC_IST_SET(_reg, _val) |
#define | GR1553B_RTMCC_IST(_val) |
#define | GR1553B_RTMCC_DBC_SHIFT 16 |
#define | GR1553B_RTMCC_DBC_MASK 0x30000U |
#define | GR1553B_RTMCC_DBC_GET(_reg) |
#define | GR1553B_RTMCC_DBC_SET(_reg, _val) |
#define | GR1553B_RTMCC_DBC(_val) |
#define | GR1553B_RTMCC_TBW_SHIFT 14 |
#define | GR1553B_RTMCC_TBW_MASK 0xc000U |
#define | GR1553B_RTMCC_TBW_GET(_reg) |
#define | GR1553B_RTMCC_TBW_SET(_reg, _val) |
#define | GR1553B_RTMCC_TBW(_val) |
#define | GR1553B_RTMCC_TVW_SHIFT 12 |
#define | GR1553B_RTMCC_TVW_MASK 0x3000U |
#define | GR1553B_RTMCC_TVW_GET(_reg) |
#define | GR1553B_RTMCC_TVW_SET(_reg, _val) |
#define | GR1553B_RTMCC_TVW(_val) |
#define | GR1553B_RTMCC_TSB_SHIFT 10 |
#define | GR1553B_RTMCC_TSB_MASK 0xc00U |
#define | GR1553B_RTMCC_TSB_GET(_reg) |
#define | GR1553B_RTMCC_TSB_SET(_reg, _val) |
#define | GR1553B_RTMCC_TSB(_val) |
#define | GR1553B_RTMCC_TS_SHIFT 8 |
#define | GR1553B_RTMCC_TS_MASK 0x300U |
#define | GR1553B_RTMCC_TS_GET(_reg) |
#define | GR1553B_RTMCC_TS_SET(_reg, _val) |
#define | GR1553B_RTMCC_TS(_val) |
#define | GR1553B_RTMCC_SDB_SHIFT 6 |
#define | GR1553B_RTMCC_SDB_MASK 0xc0U |
#define | GR1553B_RTMCC_SDB_GET(_reg) |
#define | GR1553B_RTMCC_SDB_SET(_reg, _val) |
#define | GR1553B_RTMCC_SDB(_val) |
#define | GR1553B_RTMCC_SD_SHIFT 4 |
#define | GR1553B_RTMCC_SD_MASK 0x30U |
#define | GR1553B_RTMCC_SD_GET(_reg) |
#define | GR1553B_RTMCC_SD_SET(_reg, _val) |
#define | GR1553B_RTMCC_SD(_val) |
#define | GR1553B_RTMCC_SB_SHIFT 2 |
#define | GR1553B_RTMCC_SB_MASK 0xcU |
#define | GR1553B_RTMCC_SB_GET(_reg) |
#define | GR1553B_RTMCC_SB_SET(_reg, _val) |
#define | GR1553B_RTMCC_SB(_val) |
#define | GR1553B_RTMCC_S_SHIFT 0 |
#define | GR1553B_RTMCC_S_MASK 0x3U |
#define | GR1553B_RTMCC_S_GET(_reg) |
#define | GR1553B_RTMCC_S_SET(_reg, _val) |
#define | GR1553B_RTMCC_S(_val) |
#define | GR1553B_RTTTC_TRES_SHIFT 16 |
#define | GR1553B_RTTTC_TRES_MASK 0xffff0000U |
#define | GR1553B_RTTTC_TRES_GET(_reg) |
#define | GR1553B_RTTTC_TRES_SET(_reg, _val) |
#define | GR1553B_RTTTC_TRES(_val) |
#define | GR1553B_RTTTC_TVAL_SHIFT 0 |
#define | GR1553B_RTTTC_TVAL_MASK 0xffffU |
#define | GR1553B_RTTTC_TVAL_GET(_reg) |
#define | GR1553B_RTTTC_TVAL_SET(_reg, _val) |
#define | GR1553B_RTTTC_TVAL(_val) |
#define | GR1553B_RTELM_MASK_SHIFT 0 |
#define | GR1553B_RTELM_MASK_MASK 0xffffffffU |
#define | GR1553B_RTELM_MASK_GET(_reg) |
#define | GR1553B_RTELM_MASK_SET(_reg, _val) |
#define | GR1553B_RTELM_MASK(_val) |
#define | GR1553B_RTELP_POINTER_SHIFT 0 |
#define | GR1553B_RTELP_POINTER_MASK 0xffffffffU |
#define | GR1553B_RTELP_POINTER_GET(_reg) |
#define | GR1553B_RTELP_POINTER_SET(_reg, _val) |
#define | GR1553B_RTELP_POINTER(_val) |
#define | GR1553B_RTELIP_POINTER_SHIFT 0 |
#define | GR1553B_RTELIP_POINTER_MASK 0xffffffffU |
#define | GR1553B_RTELIP_POINTER_GET(_reg) |
#define | GR1553B_RTELIP_POINTER_SET(_reg, _val) |
#define | GR1553B_RTELIP_POINTER(_val) |
#define | GR1553B_BMS_BMSUP 0x80000000U |
#define | GR1553B_BMS_KEYEN 0x40000000U |
#define | GR1553B_BMC_BMKEY_SHIFT 16 |
#define | GR1553B_BMC_BMKEY_MASK 0xffff0000U |
#define | GR1553B_BMC_BMKEY_GET(_reg) |
#define | GR1553B_BMC_BMKEY_SET(_reg, _val) |
#define | GR1553B_BMC_BMKEY(_val) |
#define | GR1553B_BMC_WRSTP 0x20U |
#define | GR1553B_BMC_EXST 0x10U |
#define | GR1553B_BMC_IMCL 0x8U |
#define | GR1553B_BMC_UDWL 0x4U |
#define | GR1553B_BMC_MANL 0x2U |
#define | GR1553B_BMC_BMEN 0x1U |
#define | GR1553B_BMRTAF_MASK_SHIFT 0 |
#define | GR1553B_BMRTAF_MASK_MASK 0xffffffffU |
#define | GR1553B_BMRTAF_MASK_GET(_reg) |
#define | GR1553B_BMRTAF_MASK_SET(_reg, _val) |
#define | GR1553B_BMRTAF_MASK(_val) |
#define | GR1553B_BMRTSF_MASK_SHIFT 0 |
#define | GR1553B_BMRTSF_MASK_MASK 0xffffffffU |
#define | GR1553B_BMRTSF_MASK_GET(_reg) |
#define | GR1553B_BMRTSF_MASK_SET(_reg, _val) |
#define | GR1553B_BMRTSF_MASK(_val) |
#define | GR1553B_BMRTMC_STSB 0x40000U |
#define | GR1553B_BMRTMC_STS 0x20000U |
#define | GR1553B_BMRTMC_TLC 0x10000U |
#define | GR1553B_BMRTMC_TSW 0x8000U |
#define | GR1553B_BMRTMC_RRTB 0x4000U |
#define | GR1553B_BMRTMC_RRT 0x2000U |
#define | GR1553B_BMRTMC_ITFB 0x1000U |
#define | GR1553B_BMRTMC_ITF 0x800U |
#define | GR1553B_BMRTMC_ISTB 0x400U |
#define | GR1553B_BMRTMC_IST 0x200U |
#define | GR1553B_BMRTMC_DBC 0x100U |
#define | GR1553B_BMRTMC_TBW 0x80U |
#define | GR1553B_BMRTMC_TVW 0x40U |
#define | GR1553B_BMRTMC_TSB 0x20U |
#define | GR1553B_BMRTMC_TS 0x10U |
#define | GR1553B_BMRTMC_SDB 0x8U |
#define | GR1553B_BMRTMC_SD 0x4U |
#define | GR1553B_BMRTMC_SB 0x2U |
#define | GR1553B_BMRTMC_S 0x1U |
#define | GR1553B_BMLBS_START_SHIFT 0 |
#define | GR1553B_BMLBS_START_MASK 0xffffffffU |
#define | GR1553B_BMLBS_START_GET(_reg) |
#define | GR1553B_BMLBS_START_SET(_reg, _val) |
#define | GR1553B_BMLBS_START(_val) |
#define | GR1553B_BMLBE_END_SHIFT 0 |
#define | GR1553B_BMLBE_END_MASK 0xffffffffU |
#define | GR1553B_BMLBE_END_GET(_reg) |
#define | GR1553B_BMLBE_END_SET(_reg, _val) |
#define | GR1553B_BMLBE_END(_val) |
#define | GR1553B_BMLBP_POSITION_SHIFT 0 |
#define | GR1553B_BMLBP_POSITION_MASK 0xffffffffU |
#define | GR1553B_BMLBP_POSITION_GET(_reg) |
#define | GR1553B_BMLBP_POSITION_SET(_reg, _val) |
#define | GR1553B_BMLBP_POSITION(_val) |
#define | GR1553B_BMTTC_TRES_SHIFT 24 |
#define | GR1553B_BMTTC_TRES_MASK 0xff000000U |
#define | GR1553B_BMTTC_TRES_GET(_reg) |
#define | GR1553B_BMTTC_TRES_SET(_reg, _val) |
#define | GR1553B_BMTTC_TRES(_val) |
#define | GR1553B_BMTTC_TVAL_SHIFT 0 |
#define | GR1553B_BMTTC_TVAL_MASK 0xffffffU |
#define | GR1553B_BMTTC_TVAL_GET(_reg) |
#define | GR1553B_BMTTC_TVAL_SET(_reg, _val) |
#define | GR1553B_BMTTC_TVAL(_val) |
Typedefs | |
typedef struct gr1553b | gr1553b |
This structure defines the GR1553B register block memory map. | |
This header file defines the GR1553B register block interface.