fsl_ssarc.h

/*
 * Copyright 2020-2021 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _FSL_SSARC_H_
#define _FSL_SSARC_H_
 
#include "fsl_common.h"
 
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
#define FSL_SSARC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
#define SSARC_INT_STATUS_ALL                                                                                       \
    (SSARC_LP_INT_STATUS_ADDR_ERR_MASK | SSARC_LP_INT_STATUS_AHB_ERR_MASK | SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK | \
     SSARC_LP_INT_STATUS_TIMEOUT_MASK | SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK)
 
enum _ssarc_interrupt_status_flags
{
    kSSARC_AddressErrorFlag = SSARC_LP_INT_STATUS_ADDR_ERR_MASK, 
    kSSARC_AHBErrorFlag = SSARC_LP_INT_STATUS_AHB_ERR_MASK,      
    kSSARC_SoftwareRequestDoneFlag = SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK, 
    kSSARC_TimeoutFlag = SSARC_LP_INT_STATUS_TIMEOUT_MASK,              
    kSSARC_GroupConflictFlag = SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK, 
};
 
typedef enum _ssarc_descriptor_register_size
{
    kSSARC_DescriptorRegister8bitWidth  = 0x0U, 
    kSSARC_DescriptorRegister16bitWidth = 0x1U, 
    kSSARC_DescriptorRegister32bitWidth = 0x2U, 
} ssarc_descriptor_register_size_t;
 
typedef enum _ssarc_descriptor_operation
{
    kSSARC_SaveDisableRestoreDisable = 0x0U, 
    kSSARC_SaveEnableRestoreDisable  = SSARC_HP_SRAM2_SV_EN_MASK, 
    kSSARC_SaveDisableRestoreEnable = SSARC_HP_SRAM2_RT_EN_MASK,  
    kSSARC_SaveEnableRestoreEnable = (SSARC_HP_SRAM2_RT_EN_MASK | SSARC_HP_SRAM2_SV_EN_MASK),
} ssarc_descriptor_operation_t;
 
typedef enum _ssarc_descriptor_type
{
    kSSARC_ReadValueWriteBack = 0x00U, 
    kSSARC_WriteFixedValue = 0x01U,    
    kSSARC_RMWOr           = 0x02U,    
    kSSARC_RMWAnd          = 0x03U,    
    kSSARC_DelayCycles     = 0x04U,    
    kSSARC_Polling0        = 0x05U,    
    kSSARC_Polling1        = 0x06U,    
} ssarc_descriptor_type_t;
 
typedef enum _ssarc_save_restore_order
{
    kSSARC_ProcessFromStartToEnd = 0U, 
    kSSARC_ProcessFromEndToStart = 1U, 
} ssarc_save_restore_order_t;
 
typedef enum _ssarc_software_trigger_mode
{
    kSSARC_TriggerSaveRequest = SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK, 
    kSSARC_TriggerRestoreRequest = SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK, 
} ssarc_software_trigger_mode_t;
 
typedef struct _ssarc_descriptor_config
{
    uint32_t address; 
    uint32_t data;    
    ssarc_descriptor_register_size_t size;  
    ssarc_descriptor_operation_t operation; 
    ssarc_descriptor_type_t type;           
} ssarc_descriptor_config_t;
 
typedef struct _ssarc_group_config
{
    ssarc_cpu_domain_name_t cpuDomain;       
    uint32_t startIndex;                     
    uint32_t endIndex;                       
    ssarc_save_restore_order_t restoreOrder; 
    ssarc_save_restore_order_t saveOrder;    
    uint8_t restorePriority;                 
    uint8_t savePriority;                    
    ssarc_power_domain_name_t powerDomain;   
    uint32_t highestAddress; 
    uint32_t lowestAddress;  
} ssarc_group_config_t;
 
/*******************************************************************************
 * API
 ******************************************************************************/
 
#if defined(__cplusplus)
extern "C" {
#endif
 
static inline uint32_t SSARC_GetDescriptorRegisterAddress(SSARC_HP_Type *base, uint32_t index)
{
    assert(index < SSARC_HP_SRAM0_COUNT);
 
    return (base->DESC[index].SRAM0);
}
 
static inline uint32_t SSARC_GetDescriptorRegisterData(SSARC_HP_Type *base, uint32_t index)
{
    assert(index < SSARC_HP_SRAM0_COUNT);
 
    return (base->DESC[index].SRAM1);
}
 
void SSARC_SetDescriptorConfig(SSARC_HP_Type *base, uint32_t index, const ssarc_descriptor_config_t *config);
 
void SSARC_GroupInit(SSARC_LP_Type *base, uint8_t groupID, const ssarc_group_config_t *config);
 
static inline void SSARC_GroupDeinit(SSARC_LP_Type *base, uint8_t groupID)
{
    assert(groupID < SSARC_LP_DESC_CTRL0_COUNT);
 
    base->GROUPS[groupID].DESC_CTRL1 &= ~SSARC_LP_DESC_CTRL1_GP_EN_MASK;
}
 
static inline void SSARC_LockGroupDomain(SSARC_LP_Type *base, uint8_t groupID)
{
    assert(groupID < SSARC_LP_DESC_CTRL0_COUNT);
 
    base->GROUPS[groupID].DESC_CTRL1 |= SSARC_LP_DESC_CTRL1_DL_MASK;
}
 
static inline void SSARC_LockGroupWrite(SSARC_LP_Type *base, uint8_t groupID)
{
    assert(groupID < SSARC_LP_DESC_CTRL0_COUNT);
 
    base->GROUPS[groupID].DESC_CTRL1 |= SSARC_LP_DESC_CTRL1_WL_MASK;
}
 
static inline void SSARC_LockGroupRead(SSARC_LP_Type *base, uint8_t groupID)
{
    assert(groupID < SSARC_LP_DESC_CTRL0_COUNT);
 
    base->GROUPS[groupID].DESC_CTRL1 |= SSARC_LP_DESC_CTRL1_RL_MASK;
}
 
void SSARC_TriggerSoftwareRequest(SSARC_LP_Type *base, uint8_t groupID, ssarc_software_trigger_mode_t mode);
 
static inline void SSARC_ResetWholeBlock(SSARC_LP_Type *base)
{
    base->CTRL |= SSARC_LP_CTRL_SW_RESET_MASK;
    base->CTRL &= ~SSARC_LP_CTRL_SW_RESET_MASK;
}
 
static inline void SSARC_EnableHardwareRequest(SSARC_LP_Type *base, bool enable)
{
    if (enable)
    {
        base->CTRL &= ~SSARC_LP_CTRL_DIS_HW_REQ_MASK;
    }
    else
    {
        base->CTRL |= SSARC_LP_CTRL_DIS_HW_REQ_MASK;
    }
}
 
static inline uint32_t SSARC_GetStatusFlags(SSARC_LP_Type *base)
{
    return ((base->INT_STATUS) & SSARC_INT_STATUS_ALL);
}
 
static inline void SSARC_ClearStatusFlags(SSARC_LP_Type *base, uint32_t mask)
{
    base->INT_STATUS = mask;
}
 
static inline uint32_t SSARC_GetErrorIndex(SSARC_LP_Type *base)
{
    return (base->INT_STATUS & SSARC_LP_INT_STATUS_ERR_INDEX_MASK);
}
 
static inline void SSARC_SetTimeoutValue(SSARC_LP_Type *base, uint32_t value)
{
    base->HP_TIMEOUT = value;
}
 
static inline uint32_t SSARC_GetTimeoutValue(SSARC_LP_Type *base)
{
    return base->HP_TIMEOUT;
}
 
static inline uint16_t SSARC_GetHardwareRequestRestorePendingGroup(SSARC_LP_Type *base)
{
    return (uint16_t)(((base->HW_GROUP_PENDING) & SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK) >>
                      SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT);
}
 
static inline uint16_t SSARC_GetHardwareRequestSavePendingGroup(SSARC_LP_Type *base)
{
    return (uint16_t)(((base->HW_GROUP_PENDING) & SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK) >>
                      SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT);
}
 
static inline uint16_t SSARC_GetSoftwareRequestRestorePendingGroup(SSARC_LP_Type *base)
{
    return (uint16_t)(((base->SW_GROUP_PENDING) & SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK) >>
                      SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT);
}
 
static inline uint16_t SSARC_GetSoftwareRequestSavePendingGroup(SSARC_LP_Type *base)
{
    return (uint16_t)(((base->SW_GROUP_PENDING) & SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK) >>
                      SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT);
}
 
#if defined(__cplusplus)
}
#endif
 
#endif /* _FSL_SSARC_H_ */