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#define | EBI_CSA 0x00 /* Chip Select Assignment Register */ |
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#define | EBI_CFGR 0x04 /* Configuration Register */ |
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#define | EBI_CSA_CS4_CF BIT4 /* 1 = CS4-6 are assigned to Compact Flash, 0 = Chip Selects */ |
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#define | EBI_CSA_CS3_SMM BIT3 /* 1 = CS3 is assigned to SmartMedia, 0 = Chip Select */ |
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#define | EBI_CSA_CS1_SDRAM BIT1 /* 1 = CS1 is assigned to SDRAM, 0 = Chip Select */ |
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#define | EBI_CSA_CS0_BF BIT0 /* 1 = CS0 is assigned to Burst Flash, 0 = Chip Select */ |
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#define | EBI_CFGR_DBPU BIT0 /* 1 = Disable D0-15 pullups */ |
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#define | SMC_CSR0 0x00 /* Chip Select Register 0 */ |
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#define | SMC_CSR1 0x04 /* Chip Select Register 1 */ |
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#define | SMC_CSR2 0x08 /* Chip Select Register 2 */ |
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#define | SMC_CSR3 0x0C /* Chip Select Register 3 */ |
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#define | SMC_CSR4 0x10 /* Chip Select Register 4 */ |
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#define | SMC_CSR5 0x14 /* Chip Select Register 5 */ |
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#define | SMC_CSR6 0x18 /* Chip Select Register 6 */ |
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#define | SMC_CSR7 0x1C /* Chip Select Register 7 */ |
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#define | SMC_CSR_RWHOLD(_x_) ((_x_ & 0x3) << 28) /* Hold CS after R/W strobes */ |
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#define | SMC_CSR_RWSETUP(_x_) ((_x_ & 0x3) << 24) /* Setup CS before R/W strobes */ |
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#define | SMC_CSR_ACSS_0 (0 << 16) /* Setup/Hold Address 0 clocks before/after CS */ |
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#define | SMC_CSR_ACSS_1 (1 << 16) /* Setup/Hold Address 1 clock before/after CS */ |
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#define | SMC_CSR_ACSS_2 (2 << 16) /* Setup/Hold Address 2 clocks before/after CS */ |
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#define | SMC_CSR_ACSS_3 (3 << 16) /* Setup/Hold Address 3 clocks before/after CS */ |
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#define | SMC_CSR_DRP_NORMAL 0 /* 0 = normal read protocol */ |
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#define | SMC_CSR_DRP_EARLY BIT15 /* 1 = early read protocol */ |
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#define | SMC_CSR_DBW_16 (1 << 13) /* CS DataBus Width = 16-Bits */ |
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#define | SMC_CSR_DBW_8 (2 << 13) /* CS DataBus Width = 8 Bits */ |
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#define | SMC_CSR_BAT_16_1 0 /* Single 16-Bit device (when DBW is 16) */ |
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#define | SMC_CSR_BAT_16_2 BIT12 /* Dual 8-Bit devices (when DBW is 16) */ |
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#define | SMC_CSR_TDF(_x_) ((_x_ & 0xf) << 8) /* Intercycle Data Float Time */ |
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#define | SMC_CSR_WSEN BIT7 /* 1 = wait states are enabled */ |
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#define | SMC_CSR_NWS(_x_) ((_x_ & 0x7f) << 0) /* Wait States + 1 */ |
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#define | SDRC_MR 0x00 /* Mode Register */ |
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#define | SDRC_TR 0x04 /* Refresh Timer Register */ |
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#define | SDRC_CR 0x08 /* Configuration Register */ |
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#define | SDRC_SRR 0x0C /* Self Refresh Register */ |
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#define | SDRC_LPR 0x10 /* Low Power Register */ |
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#define | SDRC_IER 0x14 /* Interrupt Enable Register */ |
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#define | SDRC_IDR 0x18 /* Interrupt Disable Register */ |
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#define | SDRC_IMR 0x1C /* Interrupt Mask Register */ |
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#define | SDRC_ISR 0x20 /* Interrupt Status Register */ |
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#define | SDRC_MR_DBW_16 BIT4 /* 1 = SDRAM is 16-bits wide, 0 = 32-bits */ |
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#define | SDRC_MR_NORM (0 << 0) /* Normal Mode - All accesses to SDRAM are decoded normally */ |
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#define | SDRC_MR_NOP (1 << 0) /* NOP Command is sent to SDRAM */ |
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#define | SDRC_MR_PRE (2 << 0) /* Precharge All Command is sent to SDRAM */ |
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#define | SDRC_MR_MRS (3 << 0) /* Mode Register Set Command is sent to SDRAM */ |
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#define | SDRC_MR_REF (4 << 0) /* Refresh Command is sent to SDRAM */ |
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#define | SDRC_TR_COUNT(_x_) ((_x_ & 0xfff) << 0) |
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#define | SDRC_CR_TXSR(_x_) ((_x_ & 0xf) << 27) /* CKE to ACT Time */ |
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#define | SDRC_CR_TRAS(_x_) ((_x_ & 0xf) << 23) /* ACT to PRE Time */ |
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#define | SDRC_CR_TRCD(_x_) ((_x_ & 0xf) << 19) /* RAS to CAS Time */ |
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#define | SDRC_CR_TRP(_x_) ((_x_ & 0xf) << 15) /* PRE to ACT Time */ |
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#define | SDRC_CR_TRC(_x_) ((_x_ & 0xf) << 11) /* REF to ACT Time */ |
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#define | SDRC_CR_TWR(_x_) ((_x_ & 0xf) << 7) /* Write Recovery Time */ |
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#define | SDRC_CR_CAS_2 (2 << 5) /* Cas Delay = 2, this is the only supported value */ |
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#define | SDRC_CR_NB_2 0 /* 2 Banks per device */ |
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#define | SDRC_CR_NB_4 BIT4 /* 4 Banks per device */ |
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#define | SDRC_CR_NR_11 (0 << 2) /* Number of rows = 11 */ |
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#define | SDRC_CR_NR_12 (1 << 2) /* Number of rows = 12 */ |
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#define | SDRC_CR_NR_13 (2 << 2) /* Number of rows = 13 */ |
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#define | SDRC_CR_NC_8 (0 << 0) /* Number of columns = 8 */ |
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#define | SDRC_CR_NC_9 (1 << 0) /* Number of columns = 9 */ |
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#define | SDRC_CR_NC_10 (2 << 0) /* Number of columns = 10 */ |
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#define | SDRC_CR_NC_11 (3 << 0) /* Number of columns = 11 */ |
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#define | SDRC_SRR_SRCB BIT0 /* 1 = Enter Self Refresh */ |
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#define | SDRC_LPR_LPCB BIT0 /* 1 = De-assert CKE between accesses */ |
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#define | SDRC_INT_RES BIT0 /* Refresh Error Status */ |
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AT91RM9200 Memory Controller definitions.
1.9.6