enum | ALT_DMA_PERIPH_e {
ALT_DMA_PERIPH_FPGA_0 = 0
, ALT_DMA_PERIPH_FPGA_1 = 1
, ALT_DMA_PERIPH_FPGA_2 = 2
, ALT_DMA_PERIPH_FPGA_3 = 3
,
ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4
, ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5
, ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6
, ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7
,
ALT_DMA_PERIPH_FPGA_4 = 4
, ALT_DMA_PERIPH_FPGA_5 = 5
, ALT_DMA_PERIPH_FPGA_6 = 6
, ALT_DMA_PERIPH_FPGA_7 = 7
,
ALT_DMA_PERIPH_CAN0_IF1 = 4
, ALT_DMA_PERIPH_CAN0_IF2 = 5
, ALT_DMA_PERIPH_CAN1_IF1 = 6
, ALT_DMA_PERIPH_CAN1_IF2 = 7
,
ALT_DMA_PERIPH_I2C0_TX = 8
, ALT_DMA_PERIPH_I2C0_RX = 9
, ALT_DMA_PERIPH_I2C1_TX = 10
, ALT_DMA_PERIPH_I2C1_RX = 11
,
ALT_DMA_PERIPH_I2C2_TX = 12
, ALT_DMA_PERIPH_I2C2_RX = 13
, ALT_DMA_PERIPH_I2C3_TX = 14
, ALT_DMA_PERIPH_I2C3_RX = 15
,
ALT_DMA_PERIPH_SPI0_MASTER_TX = 16
, ALT_DMA_PERIPH_SPI0_MASTER_RX = 17
, ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18
, ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19
,
ALT_DMA_PERIPH_SPI1_MASTER_TX = 20
, ALT_DMA_PERIPH_SPI1_MASTER_RX = 21
, ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22
, ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23
,
ALT_DMA_PERIPH_QSPI_FLASH_TX = 24
, ALT_DMA_PERIPH_QSPI_FLASH_RX = 25
, ALT_DMA_PERIPH_STM = 26
, ALT_DMA_PERIPH_RESERVED = 27
,
ALT_DMA_PERIPH_UART0_TX = 28
, ALT_DMA_PERIPH_UART0_RX = 29
, ALT_DMA_PERIPH_UART1_TX = 30
, ALT_DMA_PERIPH_UART1_RX = 31
} |