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RTEMS 6.1-rc2
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Go to the source code of this file.
Macros | |
#define | Xil_ExceptionEnableMask(Mask) |
Enable Exceptions. | |
#define | Xil_ExceptionEnable() Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) |
Enable the IRQ exception. | |
#define | Xil_ExceptionDisableMask(Mask) |
Disable Exceptions. | |
#define | Xil_ExceptionDisable() Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) |
#define | Xil_EnableNestedInterrupts() |
Enable nested interrupts by clearing the I and F bits in CPSR. This API is defined for cortex-a9 and cortex-r5. | |
#define | Xil_DisableNestedInterrupts() |
Disable the nested interrupts by setting the I and F bits. This API is defined for cortex-a9 and cortex-r5. | |
This header file contains ARM Cortex A53,A9,R5 specific exception related APIs. For exception related functions that can be used across all Xilinx supported processors, please use xil_exception.h.