51#ifndef _RTEMS_SCORE_CPU_H
52#define _RTEMS_SCORE_CPU_H
55#if defined(RTEMS_PARAVIRT)
56#include <rtems/score/paravirt.h>
66#if defined(ARM_MULTILIB_ARCH_V4)
68#if defined(__thumb__) && !defined(__thumb2__)
69 #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg
70 #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n"
71 #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n"
72 #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg)
73 #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT
75 #define ARM_SWITCH_REGISTERS
76 #define ARM_SWITCH_TO_ARM
77 #define ARM_SWITCH_BACK
78 #define ARM_SWITCH_OUTPUT
79 #define ARM_SWITCH_ADDITIONAL_OUTPUT
87#define ARM_PSR_N (1 << 31)
88#define ARM_PSR_Z (1 << 30)
89#define ARM_PSR_C (1 << 29)
90#define ARM_PSR_V (1 << 28)
91#define ARM_PSR_Q (1 << 27)
92#define ARM_PSR_J (1 << 24)
93#define ARM_PSR_GE_SHIFT 16
94#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT)
95#define ARM_PSR_E (1 << 9)
96#define ARM_PSR_A (1 << 8)
97#define ARM_PSR_I (1 << 7)
98#define ARM_PSR_F (1 << 6)
99#define ARM_PSR_T (1 << 5)
100#define ARM_PSR_M_SHIFT 0
101#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT)
102#define ARM_PSR_M_USR 0x10
103#define ARM_PSR_M_FIQ 0x11
104#define ARM_PSR_M_IRQ 0x12
105#define ARM_PSR_M_SVC 0x13
106#define ARM_PSR_M_ABT 0x17
107#define ARM_PSR_M_HYP 0x1a
108#define ARM_PSR_M_UND 0x1b
109#define ARM_PSR_M_SYS 0x1f
118#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
120#define CPU_ISR_PASSES_FRAME_POINTER FALSE
122#define CPU_HARDWARE_FP FALSE
124#define CPU_SOFTWARE_FP FALSE
126#define CPU_ALL_TASKS_ARE_FP FALSE
128#define CPU_IDLE_TASK_IS_FP FALSE
130#define CPU_USE_DEFERRED_FP_SWITCH FALSE
132#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE
134#define CPU_STACK_GROWS_UP FALSE
136#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64)
137 #define CPU_CACHE_LINE_BYTES 64
139 #define CPU_CACHE_LINE_BYTES 32
142#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
144#define CPU_MODES_INTERRUPT_MASK 0x1
146#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
148#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
150#define CPU_STACK_MINIMUM_SIZE (1024 * 4)
153#define CPU_SIZEOF_POINTER 4
156#define CPU_ALIGNMENT 8
158#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
161#define CPU_STACK_ALIGNMENT 8
163#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
176#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
178#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
180#define CPU_MAXIMUM_PROCESSORS 32
182#define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
184#ifdef ARM_MULTILIB_VFP
185 #define ARM_CONTEXT_CONTROL_D8_OFFSET 48
188#ifdef ARM_MULTILIB_ARCH_V4
189 #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 40
193 #if defined(ARM_MULTILIB_VFP)
194 #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112
196 #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
200#define ARM_EXCEPTION_FRAME_SIZE 80
202#define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52
204#define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72
206#define ARM_VFP_CONTEXT_SIZE 264
215#if defined(ARM_MULTILIB_ARCH_V4)
216 uint32_t register_r4;
217 uint32_t register_r5;
218 uint32_t register_r6;
219 uint32_t register_r7;
220 uint32_t register_r8;
221 uint32_t register_r9;
222 uint32_t register_r10;
223 uint32_t register_fp;
224 uint32_t register_sp;
225 uint32_t register_lr;
226 uint32_t isr_dispatch_disable;
227#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
228 uint32_t register_r4;
229 uint32_t register_r5;
230 uint32_t register_r6;
231 uint32_t register_r7;
232 uint32_t register_r8;
233 uint32_t register_r9;
234 uint32_t register_r10;
235 uint32_t register_r11;
238 uint32_t isr_nest_level;
243#ifdef ARM_MULTILIB_VFP
244 uint64_t register_d8;
245 uint64_t register_d9;
246 uint64_t register_d10;
247 uint64_t register_d11;
248 uint64_t register_d12;
249 uint64_t register_d13;
250 uint64_t register_d14;
251 uint64_t register_d15;
254 volatile bool is_executing;
258static inline void _ARM_Data_memory_barrier(
void )
260#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
261 __asm__
volatile (
"dmb" : : :
"memory" );
267static inline void _ARM_Data_synchronization_barrier(
void )
269#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
270 __asm__
volatile (
"dsb" : : :
"memory" );
276static inline void _ARM_Instruction_synchronization_barrier(
void )
278#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
279 __asm__
volatile (
"isb" : : :
"memory" );
285#if defined(ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE)
286uint32_t arm_interrupt_disable(
void );
287void arm_interrupt_enable( uint32_t level );
288void arm_interrupt_flash( uint32_t level );
290static inline uint32_t arm_interrupt_disable(
void )
294#if defined(ARM_MULTILIB_ARCH_V4)
317 uint32_t arm_switch_reg;
321 "mrs %[level], cpsr\n"
322 "orr %[arm_switch_reg], %[level], #0x80\n"
323 "msr cpsr, %[arm_switch_reg]\n"
325 : [arm_switch_reg]
"=&r" (arm_switch_reg), [level]
"=&r" (level)
328#elif defined(ARM_MULTILIB_ARCH_V7M)
329 uint32_t basepri = 0x80;
332 "mrs %[level], basepri\n"
333 "msr basepri_max, %[basepri]\n"
334 : [level]
"=&r" (level)
335 : [basepri]
"r" (basepri)
342static inline void arm_interrupt_enable( uint32_t level )
344#if defined(ARM_MULTILIB_ARCH_V4)
345 ARM_SWITCH_REGISTERS;
349 "msr cpsr, %[level]\n"
352 : [level]
"r" (level)
354#elif defined(ARM_MULTILIB_ARCH_V7M)
356 "msr basepri, %[level]\n"
358 : [level]
"r" (level)
363static inline void arm_interrupt_flash( uint32_t level )
365#if defined(ARM_MULTILIB_ARCH_V4)
366 uint32_t arm_switch_reg;
370 "mrs %[arm_switch_reg], cpsr\n"
371 "msr cpsr, %[level]\n"
372 "msr cpsr, %[arm_switch_reg]\n"
374 : [arm_switch_reg]
"=&r" (arm_switch_reg)
375 : [level]
"r" (level)
377#elif defined(ARM_MULTILIB_ARCH_V7M)
381 "mrs %[basepri], basepri\n"
382 "msr basepri, %[level]\n"
383 "msr basepri, %[basepri]\n"
384 : [basepri]
"=&r" (basepri)
385 : [level]
"r" (level)
391#define _CPU_ISR_Disable( _isr_cookie ) \
393 _isr_cookie = arm_interrupt_disable(); \
396#define _CPU_ISR_Enable( _isr_cookie ) \
397 arm_interrupt_enable( _isr_cookie )
399#define _CPU_ISR_Flash( _isr_cookie ) \
400 arm_interrupt_flash( _isr_cookie )
402static inline bool _CPU_ISR_Is_enabled( uint32_t level )
404#if defined(ARM_MULTILIB_ARCH_V4)
405 return ( level & 0x80 ) == 0;
406#elif defined(ARM_MULTILIB_ARCH_V7M)
415void _CPU_Context_Initialize(
417 void *stack_area_begin,
418 size_t stack_area_size,
420 void (*entry_point)(
void ),
425#define _CPU_Context_Get_SP( _context ) \
426 (_context)->register_sp
429 static inline bool _CPU_Context_Get_is_executing(
436 static inline void _CPU_Context_Set_is_executing(
441 context->is_executing = is_executing;
446 #define _CPU_Start_multitasking( _heir ) _ARM_Start_multitasking( _heir )
449#define _CPU_Context_Restart_self( _the_context ) \
450 _CPU_Context_restore( (_the_context) );
452#define _CPU_Context_Initialize_fp( _destination ) \
454 *(*(_destination)) = _CPU_Null_fp_context; \
462typedef void ( *CPU_ISR_handler )( void );
466 CPU_ISR_handler new_handler,
467 CPU_ISR_handler *old_handler
482#if defined(ARM_MULTILIB_ARCH_V7M)
484 #define _CPU_Start_multitasking _ARMV7M_Start_multitasking
488 uint32_t _CPU_SMP_Initialize(
void );
490 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
492 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
494 void _CPU_SMP_Prepare_start_multitasking(
void );
496 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
502 "mrc p15, 0, %[mpidr], c0, c0, 5\n"
503 : [mpidr]
"=&r" (mpidr)
506 return mpidr & 0xffU;
509 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
511 static inline void _ARM_Send_event(
void )
513 __asm__
volatile (
"sev" : : :
"memory" );
516 static inline void _ARM_Wait_for_event(
void )
518 __asm__
volatile (
"wfe" : : :
"memory" );
523static inline uint32_t CPU_swap_u32( uint32_t value )
525#if defined(__thumb2__)
532#elif defined(__thumb__)
533 uint32_t byte1, byte2, byte3, byte4, swapped;
535 byte4 = (value >> 24) & 0xff;
536 byte3 = (value >> 16) & 0xff;
537 byte2 = (value >> 8) & 0xff;
538 byte1 = value & 0xff;
540 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
543 uint32_t tmp = value;
544 __asm__
volatile (
"EOR %1, %0, %0, ROR #16\n"
545 "BIC %1, %1, #0xff0000\n"
546 "MOV %0, %0, ROR #8\n"
547 "EOR %0, %0, %1, LSR #8\n"
548 :
"=r" (value),
"=r" (tmp)
549 :
"0" (value),
"1" (tmp));
556#if defined(__thumb2__)
564 return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
568typedef uint32_t CPU_Counter_ticks;
576#if defined(ARM_MULTILIB_ARCH_V4)
579 ARM_EXCEPTION_RESET = 0,
580 ARM_EXCEPTION_UNDEF = 1,
581 ARM_EXCEPTION_SWI = 2,
582 ARM_EXCEPTION_PREF_ABORT = 3,
583 ARM_EXCEPTION_DATA_ABORT = 4,
584 ARM_EXCEPTION_RESERVED = 5,
585 ARM_EXCEPTION_IRQ = 6,
586 ARM_EXCEPTION_FIQ = 7,
588 ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0x7fffffff
589} Arm_symbolic_exception_name;
594 uint32_t register_fpexc;
595 uint32_t register_fpscr;
596 uint64_t register_d0;
597 uint64_t register_d1;
598 uint64_t register_d2;
599 uint64_t register_d3;
600 uint64_t register_d4;
601 uint64_t register_d5;
602 uint64_t register_d6;
603 uint64_t register_d7;
604 uint64_t register_d8;
605 uint64_t register_d9;
606 uint64_t register_d10;
607 uint64_t register_d11;
608 uint64_t register_d12;
609 uint64_t register_d13;
610 uint64_t register_d14;
611 uint64_t register_d15;
612 uint64_t register_d16;
613 uint64_t register_d17;
614 uint64_t register_d18;
615 uint64_t register_d19;
616 uint64_t register_d20;
617 uint64_t register_d21;
618 uint64_t register_d22;
619 uint64_t register_d23;
620 uint64_t register_d24;
621 uint64_t register_d25;
622 uint64_t register_d26;
623 uint64_t register_d27;
624 uint64_t register_d28;
625 uint64_t register_d29;
626 uint64_t register_d30;
627 uint64_t register_d31;
631 uint32_t register_r0;
632 uint32_t register_r1;
633 uint32_t register_r2;
634 uint32_t register_r3;
635 uint32_t register_r4;
636 uint32_t register_r5;
637 uint32_t register_r6;
638 uint32_t register_r7;
639 uint32_t register_r8;
640 uint32_t register_r9;
641 uint32_t register_r10;
642 uint32_t register_r11;
643 uint32_t register_r12;
644 uint32_t register_sp;
647#if defined(ARM_MULTILIB_ARCH_V4)
648 uint32_t register_cpsr;
649 Arm_symbolic_exception_name vector;
650#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
651 uint32_t register_xpsr;
655 uint32_t reserved_for_stack_alignment;
This header file provides defines derived from ARM multilib defines.
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_COMPILER_MEMORY_BARRIER()
This macro forbids the compiler to reorder read and write commands around it.
Definition: basedefs.h:258
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:165
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler hdl, CPU_ISR_handler *oldHdl)
SPARC specific RTEMS ISR installer.
Definition: idt.c:106
#define CPU_swap_u16(value)
Definition: cpu.h:597
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
rtems_termios_device_context * context
Definition: console-config.c:62
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Thread register context.
Definition: cpu.h:169