48#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
49 XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
51#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
52 XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
54#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
55 XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
57#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
58 XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
60#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
61 XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
63#elif defined (__ICCARM__)
65#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
66 XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
68#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
69 XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
71#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
72 XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
74#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
75 XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
77#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
78 XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
91void Xil_DCacheFlushRange(INTPTR adr, u32 len);
void Xil_ICacheInvalidate(void)
Invalidate the entire instruction cache.
Definition: xil_cache.c:627
void Xil_DCacheEnable(void)
Enable the Data cache.
Definition: xil_cache.c:90
void Xil_ICacheDisable(void)
Disable the instruction cache.
Definition: xil_cache.c:594
void Xil_DCacheDisable(void)
Disable the Data cache.
Definition: xil_cache.c:127
void Xil_DCacheInvalidate(void)
Invalidate the Data cache. The contents present in the cache are cleaned and invalidated.
Definition: xil_cache.c:257
void Xil_ICacheEnable(void)
Enable the instruction cache.
Definition: xil_cache.c:558
void Xil_DCacheFlush(void)
Flush the Data cache.
Definition: xil_cache.c:429
#define Xil_ICacheInvalidateRange(Addr, Len)
Invalidate the instruction cache for the given address range. If the bytes specified by the address (...
Definition: xil_cache.h:376
#define Xil_DCacheInvalidateRange(Addr, Len)
Invalidate the Data cache for the given address range. If the bytes specified by the address (adr) ar...
Definition: xil_cache.h:313