RTEMS 6.1-rc2
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arm-gic-arch.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
13 * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
38#define _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
39
40#include <rtems/score/cpu.h>
41#include <rtems/score/cpu_irq.h>
42
43#include <bsp/irq-generic.h>
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector)
50{
51 uint32_t interrupt_level = _CPU_ISR_Get_level();
52 /* Enable interrupts for nesting */
54 bsp_interrupt_handler_dispatch(vector);
55 /* Restore interrupts to previous level */
56 _CPU_ISR_Set_level(interrupt_level);
57}
58
59static inline void arm_interrupt_facility_set_exception_handler(void)
60{
61 AArch64_set_exception_handler(
62 AARCH64_EXCEPTION_SPx_IRQ,
63 _AArch64_Exception_interrupt_no_nest
64 );
65 AArch64_set_exception_handler(
66 AARCH64_EXCEPTION_SP0_IRQ,
67 _AArch64_Exception_interrupt_nest
68 );
69}
70
71#ifdef __cplusplus
72}
73#endif
74
75#endif /* _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H */
AArch64 IRQ definitions.
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition: intr.h:102
uint32_t _CPU_ISR_Get_level(void)
Returns the interrupt level of the executing thread.
Definition: cpu.c:165
#define _CPU_ISR_Set_level(_new_level)
Definition: cpu.h:378
This header file provides interfaces of the Interrupt Manager implementation.