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RTEMS 6.1-rc2
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26#ifndef XREG_CORTEXA53_H
27#define XREG_CORTEXA53_H
93#define XREG_CPSR_THUMB_MODE 0x20
94#define XREG_CPSR_MODE_BITS 0x1F
95#define XREG_CPSR_SYSTEM_MODE 0x1F
96#define XREG_CPSR_UNDEFINED_MODE 0x1B
97#define XREG_CPSR_DATA_ABORT_MODE 0x17
98#define XREG_CPSR_SVC_MODE 0x13
99#define XREG_CPSR_IRQ_MODE 0x12
100#define XREG_CPSR_FIQ_MODE 0x11
101#define XREG_CPSR_USER_MODE 0x10
103#define XREG_CPSR_IRQ_ENABLE 0x80
104#define XREG_CPSR_FIQ_ENABLE 0x40
106#define XREG_CPSR_N_BIT 0x80000000
107#define XREG_CPSR_Z_BIT 0x40000000
108#define XREG_CPSR_C_BIT 0x20000000
109#define XREG_CPSR_V_BIT 0x10000000
115#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
116#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
117#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
118#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
119#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
121#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
122#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
123#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
124#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
125#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
126#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
127#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
129#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
130#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
131#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
132#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
133#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
135#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
136#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
137#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
139#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
142#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
143#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
144#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
146#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
147#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
148#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
149#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
153#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
154#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
155#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
156#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
157#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
158#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
159#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
160#define XREG_CP15_CONTROL_V_BIT 0x00002000U
161#define XREG_CP15_CONTROL_I_BIT 0x00001000U
162#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
163#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
164#define XREG_CP15_CONTROL_B_BIT 0x00000080U
165#define XREG_CP15_CONTROL_C_BIT 0x00000004U
166#define XREG_CP15_CONTROL_A_BIT 0x00000002U
167#define XREG_CP15_CONTROL_M_BIT 0x00000001U
171#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
172#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
173#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
176#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
182#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
183#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
185#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
186#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
189#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
190#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
193#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
195#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
196#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
198#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
200#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
201#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
206#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
207#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
209#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
210#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
212#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
213#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
214#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
215#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
217#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
218#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
219#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
220#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
222#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
223#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
228#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
229#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
231#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
233#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
235#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
236#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
239#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
240#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
241#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
242#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
244#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
245#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
246#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
248#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
249#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
250#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
252#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
253#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
254#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
255#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
258#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
259#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
260#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
261#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
262#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
263#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
265#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
266#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
267#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
269#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
270#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
271#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
274#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
276#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
277#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
283#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
284#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
286#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
287#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
290#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
291#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
292#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
293#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
299#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
300#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
302#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
303#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
305#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
307#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
309#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
317#define XREG_FPINST c9
318#define XREG_FPINST2 c10
321#define XREG_FPSID_IMPLEMENTER_BIT (24)
322#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
323#define XREG_FPSID_SOFTWARE (1<<23)
324#define XREG_FPSID_ARCH_BIT (16)
325#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
326#define XREG_FPSID_PART_BIT (8)
327#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
328#define XREG_FPSID_VARIANT_BIT (4)
329#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
330#define XREG_FPSID_REV_BIT (0)
331#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
334#define XREG_FPSCR_N_BIT (1 << 31)
335#define XREG_FPSCR_Z_BIT (1 << 30)
336#define XREG_FPSCR_C_BIT (1 << 29)
337#define XREG_FPSCR_V_BIT (1 << 28)
338#define XREG_FPSCR_QC (1 << 27)
339#define XREG_FPSCR_AHP (1 << 26)
340#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
341#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
342#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
343#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
344#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
345#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
346#define XREG_FPSCR_RMODE_BIT (22)
347#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
348#define XREG_FPSCR_STRIDE_BIT (20)
349#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
350#define XREG_FPSCR_LENGTH_BIT (16)
351#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
352#define XREG_FPSCR_IDC (1 << 7)
353#define XREG_FPSCR_IXC (1 << 4)
354#define XREG_FPSCR_UFC (1 << 3)
355#define XREG_FPSCR_OFC (1 << 2)
356#define XREG_FPSCR_DZC (1 << 1)
357#define XREG_FPSCR_IOC (1 << 0)
360#define XREG_MVFR0_RMODE_BIT (28)
361#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
362#define XREG_MVFR0_SHORT_VEC_BIT (24)
363#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
364#define XREG_MVFR0_SQRT_BIT (20)
365#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
366#define XREG_MVFR0_DIVIDE_BIT (16)
367#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
368#define XREG_MVFR0_EXEC_TRAP_BIT (12)
369#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
370#define XREG_MVFR0_DP_BIT (8)
371#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
372#define XREG_MVFR0_SP_BIT (4)
373#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
374#define XREG_MVFR0_A_SIMD_BIT (0)
375#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
378#define XREG_FPEXC_EX (1 << 31)
379#define XREG_FPEXC_EN (1 << 30)
380#define XREG_FPEXC_DEX (1 << 29)
383#define XREG_CONTROL_DCACHE_BIT (0X00000001U<<2U)
384#define XREG_CONTROL_ICACHE_BIT (0X00000001U<<12U)