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void | Xil_DCacheEnable (void) |
| Enable the Data cache.
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void | Xil_DCacheDisable (void) |
| Disable the Data cache.
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void | Xil_DCacheInvalidate (void) |
| Invalidate the entire Data cache.
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void | Xil_DCacheInvalidateLine (INTPTR adr) |
| Invalidate a Data cache line. If the byte specified by the address (adr) is cached by the data cache, the cacheline containing that byte is invalidated.If the cacheline is modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.
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void | Xil_DCacheInvalidateRange (INTPTR adr, u32 len) |
| Invalidate the Data cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache,the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.
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void | Xil_DCacheFlush (void) |
| Flush the entire Data cache.
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void | Xil_DCacheFlushLine (INTPTR adr) |
| Flush a Data cache line. If the byte specified by the address (adr) is cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory before the line is invalidated.
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void | Xil_DCacheFlushRange (INTPTR adr, u32 len) |
| Flush the Data cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing those bytes is invalidated.If the cacheline is modified (dirty), the written to system memory before the lines are invalidated.
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void | Xil_DCacheStoreLine (INTPTR adr) |
| Store a Data cache line. If the byte specified by the address (adr) is cached by the Data cache and the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory.After the store completes, the cacheline is marked as unmodified (not dirty).
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void | Xil_ICacheEnable (void) |
| Enable the instruction cache.
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void | Xil_ICacheDisable (void) |
| Disable the instruction cache.
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void | Xil_ICacheInvalidate (void) |
| Invalidate the entire instruction cache.
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void | Xil_ICacheInvalidateLine (INTPTR adr) |
| Invalidate an instruction cache line.If the instruction specified by the address is cached by the instruction cache, the cacheline containing that instruction is invalidated.
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void | Xil_ICacheInvalidateRange (INTPTR adr, u32 len) |
| Invalidate the instruction cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing that byte is invalidated. If the cachelineis modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.
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Contains required functions for the ARM cache functionality.
MODIFICATION HISTORY:
Ver Who Date Changes
----- ---- -------- -----------------------------------------------
5.00 pkp 02/20/14 First release
6.2 mus 01/27/17 Updated to support IAR compiler
7.3 dp 06/25/20 Updated to support armclang compiler
7.7 sk 01/10/22 Update IRQ_FIQ_MASK macro from signed to unsigned
to fix misra_c_2012_rule_10_4 violation.
7.7 sk 01/10/22 Typecast to fix wider essential type misra_c_2012_rule_10_7
violation.
7.7 mus 02/21/22 Existing note in cache API's says, "bottom 4 bits of input
address are forced to 0 as per architecture". As cache line
length is of 32 byte, bottom 5 bits of input address would
be forced to 0. Updated note to have correct details.
It fixes CR#1122561.