RTEMS 6.1-rc2
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MIMXRT1166_cm7.h
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1/*
2** ###################################################################
3** Processors: MIMXRT1166CVM5A_cm7
4** MIMXRT1166DVM6A_cm7
5** MIMXRT1166XVM5A_cm7
6**
7** Compilers: Freescale C/C++ for Embedded ARM
8** GNU C Compiler
9** IAR ANSI C/C++ Compiler for ARM
10** Keil ARM C/C++ Compiler
11** MCUXpresso Compiler
12**
13** Reference manual: IMXRT1160RM, Rev 0, 03/2021
14** Version: rev. 0.1, 2020-12-29
15** Build: b221010
16**
17** Abstract:
18** CMSIS Peripheral Access Layer for MIMXRT1166_cm7
19**
20** Copyright 1997-2016 Freescale Semiconductor, Inc.
21** Copyright 2016-2022 NXP
22** All rights reserved.
23**
24** SPDX-License-Identifier: BSD-3-Clause
25**
26** http: www.nxp.com
27** mail: support@nxp.com
28**
29** Revisions:
30** - rev. 0.1 (2020-12-29)
31** Initial version.
32**
33** ###################################################################
34*/
35
45#ifndef _MIMXRT1166_CM7_H_
46#define _MIMXRT1166_CM7_H_
50#define MCU_MEM_MAP_VERSION 0x0000U
52#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
53
54/* ----------------------------------------------------------------------------
55 --
56 ---------------------------------------------------------------------------- */
57
58/* Extra XRDC2 definition */
59#define XRDC2_MAKE_MEM(mrc, mrgd) (((mrc) << 5U) | (mrgd))
60#define XRDC2_GET_MRC(mem) ((mem) >> 5U)
61#define XRDC2_GET_MRGD(mem) ((mem) & 31U)
62#define XRDC2_MAKE_PERIPH(pac, pdac) (((pac) << 8U) | (pdac))
63#define XRDC2_GET_PAC(periph) ((periph) >> 8U)
64#define XRDC2_GET_PDAC(periph) ((periph) & 255U)
65
66
67
68/* ----------------------------------------------------------------------------
69 -- Interrupt vector numbers
70 ---------------------------------------------------------------------------- */
71
78#define NUMBER_OF_INT_VECTORS 234
80typedef enum IRQn {
81 /* Auxiliary constants */
84 /* Core interrupts */
95 /* Device specific interrupts */
147 KPP_IRQn = 51,
152 CSI_IRQn = 56,
153 PXP_IRQn = 57,
159 DAC_IRQn = 63,
188 RDC_IRQn = 92,
210 EWM_IRQn = 114,
213 GPC_IRQn = 117,
214 MUA_IRQn = 118,
215 GPT1_IRQn = 119,
216 GPT2_IRQn = 120,
217 GPT3_IRQn = 121,
218 GPT4_IRQn = 122,
219 GPT5_IRQn = 123,
220 GPT6_IRQn = 124,
228 SEMC_IRQn = 132,
233 ENET_IRQn = 137,
251 PIT1_IRQn = 155,
252 PIT2_IRQn = 156,
261 ENC1_IRQn = 165,
262 ENC2_IRQn = 166,
263 ENC3_IRQn = 167,
264 ENC4_IRQn = 168,
267 TMR1_IRQn = 171,
268 TMR2_IRQn = 172,
269 TMR3_IRQn = 173,
270 TMR4_IRQn = 174,
313 Reserved233_IRQn = 217
315 /* end of group Interrupt_vector_numbers */
319
320
321/* ----------------------------------------------------------------------------
322 -- Cortex M7 Core Configuration
323 ---------------------------------------------------------------------------- */
324
330#define __MPU_PRESENT 1
331#define __ICACHE_PRESENT 1
332#define __DCACHE_PRESENT 1
333#define __DTCM_PRESENT 1
334#define __NVIC_PRIO_BITS 4
335#define __Vendor_SysTickConfig 0
336#define __FPU_PRESENT 1
338#include "core_cm7.h" /* Core Peripheral Access Layer */
339#include "system_MIMXRT1166_cm7.h" /* Device specific configuration file */
340 /* end of group Cortex_Core_Configuration */
344
345
346/* ----------------------------------------------------------------------------
347 -- Mapping Information
348 ---------------------------------------------------------------------------- */
349
361/*******************************************************************************
362 * Definitions
363 ******************************************************************************/
364
370/*
371 * Domain of these masters are not assigned by RDC
372 * CM7, CM7_DMA: Always use domain ID 0.
373 * CM4, CM4_DMA: Use domain ID 0 in single core case, 1 in dual core case.
374 * CAAM: Defined in CAAM mst_a[x]icid[10]
375 * LCDIFv2: Defined in LCDIF2 user bit[0]
376 * SSARC: Defined in SSARC user bit[0]
377 */
378
379typedef enum _rdc_master
380{
393
394typedef enum _rdc_mem
395{
396 kRDC_Mem_MRC0_0 = 0U,
397 kRDC_Mem_MRC0_1 = 1U,
398 kRDC_Mem_MRC0_2 = 2U,
399 kRDC_Mem_MRC0_3 = 3U,
400 kRDC_Mem_MRC0_4 = 4U,
401 kRDC_Mem_MRC0_5 = 5U,
402 kRDC_Mem_MRC0_6 = 6U,
403 kRDC_Mem_MRC0_7 = 7U,
404 kRDC_Mem_MRC1_0 = 8U,
405 kRDC_Mem_MRC1_1 = 9U,
406 kRDC_Mem_MRC1_2 = 10U,
407 kRDC_Mem_MRC1_3 = 11U,
408 kRDC_Mem_MRC1_4 = 12U,
409 kRDC_Mem_MRC1_5 = 13U,
410 kRDC_Mem_MRC1_6 = 14U,
411 kRDC_Mem_MRC1_7 = 15U,
412 kRDC_Mem_MRC2_0 = 16U,
413 kRDC_Mem_MRC2_1 = 17U,
414 kRDC_Mem_MRC2_2 = 18U,
415 kRDC_Mem_MRC2_3 = 19U,
416 kRDC_Mem_MRC2_4 = 20U,
417 kRDC_Mem_MRC2_5 = 21U,
418 kRDC_Mem_MRC2_6 = 22U,
419 kRDC_Mem_MRC2_7 = 23U,
420 kRDC_Mem_MRC3_0 = 24U,
421 kRDC_Mem_MRC3_1 = 25U,
422 kRDC_Mem_MRC3_2 = 26U,
423 kRDC_Mem_MRC3_3 = 27U,
424 kRDC_Mem_MRC3_4 = 28U,
425 kRDC_Mem_MRC3_5 = 29U,
426 kRDC_Mem_MRC3_6 = 30U,
427 kRDC_Mem_MRC3_7 = 31U,
428 kRDC_Mem_MRC4_0 = 32U,
429 kRDC_Mem_MRC4_1 = 33U,
430 kRDC_Mem_MRC4_2 = 34U,
431 kRDC_Mem_MRC4_3 = 35U,
432 kRDC_Mem_MRC4_4 = 36U,
433 kRDC_Mem_MRC4_5 = 37U,
434 kRDC_Mem_MRC4_6 = 38U,
435 kRDC_Mem_MRC4_7 = 39U,
436 kRDC_Mem_MRC5_0 = 40U,
437 kRDC_Mem_MRC5_1 = 41U,
438 kRDC_Mem_MRC5_2 = 42U,
439 kRDC_Mem_MRC5_3 = 43U,
440 kRDC_Mem_MRC6_0 = 44U,
441 kRDC_Mem_MRC6_1 = 45U,
442 kRDC_Mem_MRC6_2 = 46U,
443 kRDC_Mem_MRC6_3 = 47U,
444 kRDC_Mem_MRC7_0 = 48U,
445 kRDC_Mem_MRC7_1 = 49U,
446 kRDC_Mem_MRC7_2 = 50U,
447 kRDC_Mem_MRC7_3 = 51U,
448 kRDC_Mem_MRC7_4 = 52U,
449 kRDC_Mem_MRC7_5 = 53U,
450 kRDC_Mem_MRC7_6 = 54U,
451 kRDC_Mem_MRC7_7 = 55U,
452 kRDC_Mem_MRC8_0 = 56U,
453 kRDC_Mem_MRC8_1 = 57U,
454 kRDC_Mem_MRC8_2 = 58U,
455} rdc_mem_t;
456
457typedef enum _rdc_periph
458{
591} rdc_periph_t;
592
593/* @} */
594
596{
937} xbar_input_signal_t;
938
940{
1073 kXBARA1_OutputCan1 = 132|0x100U,
1074 kXBARA1_OutputCan2 = 133|0x100U,
1148} xbar_output_signal_t;
1149
1154/*******************************************************************************
1155 * Definitions
1156*******************************************************************************/
1157
1164{
1182
1183/* @} */
1184
1189/*******************************************************************************
1190 * Definitions
1191*******************************************************************************/
1192
1199{
1217
1218/* @} */
1219
1226{
1252
1258/*******************************************************************************
1259 * Definitions
1260 ******************************************************************************/
1261
1269{
1279
1280 /*
1281 * @brief The name of cpu domain.
1282 */
1284{
1287} ssarc_cpu_domain_name_t;
1288
1289/* @} */
1290
1296/*******************************************************************************
1297 * Definitions
1298 ******************************************************************************/
1299
1306typedef enum _xrdc2_master
1307{
1329
1330typedef enum _xrdc2_mem
1331{
1332 kXRDC2_Mem_CAAM_Region0 = XRDC2_MAKE_MEM(0, 0),
1333 kXRDC2_Mem_CAAM_Region1 = XRDC2_MAKE_MEM(0, 1),
1334 kXRDC2_Mem_CAAM_Region2 = XRDC2_MAKE_MEM(0, 2),
1335 kXRDC2_Mem_CAAM_Region3 = XRDC2_MAKE_MEM(0, 3),
1336 kXRDC2_Mem_CAAM_Region4 = XRDC2_MAKE_MEM(0, 4),
1337 kXRDC2_Mem_CAAM_Region5 = XRDC2_MAKE_MEM(0, 5),
1338 kXRDC2_Mem_CAAM_Region6 = XRDC2_MAKE_MEM(0, 6),
1339 kXRDC2_Mem_CAAM_Region7 = XRDC2_MAKE_MEM(0, 7),
1340 kXRDC2_Mem_CAAM_Region8 = XRDC2_MAKE_MEM(0, 8),
1341 kXRDC2_Mem_CAAM_Region9 = XRDC2_MAKE_MEM(0, 9),
1342 kXRDC2_Mem_CAAM_Region10 = XRDC2_MAKE_MEM(0, 10),
1343 kXRDC2_Mem_CAAM_Region11 = XRDC2_MAKE_MEM(0, 11),
1344 kXRDC2_Mem_CAAM_Region12 = XRDC2_MAKE_MEM(0, 12),
1345 kXRDC2_Mem_CAAM_Region13 = XRDC2_MAKE_MEM(0, 13),
1346 kXRDC2_Mem_CAAM_Region14 = XRDC2_MAKE_MEM(0, 14),
1347 kXRDC2_Mem_CAAM_Region15 = XRDC2_MAKE_MEM(0, 15),
1348 kXRDC2_Mem_FLEXSPI1_Region0 = XRDC2_MAKE_MEM(1, 0),
1349 kXRDC2_Mem_FLEXSPI1_Region1 = XRDC2_MAKE_MEM(1, 1),
1350 kXRDC2_Mem_FLEXSPI1_Region2 = XRDC2_MAKE_MEM(1, 2),
1351 kXRDC2_Mem_FLEXSPI1_Region3 = XRDC2_MAKE_MEM(1, 3),
1352 kXRDC2_Mem_FLEXSPI1_Region4 = XRDC2_MAKE_MEM(1, 4),
1353 kXRDC2_Mem_FLEXSPI1_Region5 = XRDC2_MAKE_MEM(1, 5),
1354 kXRDC2_Mem_FLEXSPI1_Region6 = XRDC2_MAKE_MEM(1, 6),
1355 kXRDC2_Mem_FLEXSPI1_Region7 = XRDC2_MAKE_MEM(1, 7),
1356 kXRDC2_Mem_FLEXSPI1_Region8 = XRDC2_MAKE_MEM(1, 8),
1357 kXRDC2_Mem_FLEXSPI1_Region9 = XRDC2_MAKE_MEM(1, 9),
1358 kXRDC2_Mem_FLEXSPI1_Region10 = XRDC2_MAKE_MEM(1, 10),
1359 kXRDC2_Mem_FLEXSPI1_Region11 = XRDC2_MAKE_MEM(1, 11),
1360 kXRDC2_Mem_FLEXSPI1_Region12 = XRDC2_MAKE_MEM(1, 12),
1361 kXRDC2_Mem_FLEXSPI1_Region13 = XRDC2_MAKE_MEM(1, 13),
1362 kXRDC2_Mem_FLEXSPI1_Region14 = XRDC2_MAKE_MEM(1, 14),
1363 kXRDC2_Mem_FLEXSPI1_Region15 = XRDC2_MAKE_MEM(1, 15),
1364 kXRDC2_Mem_FLEXSPI2_Region0 = XRDC2_MAKE_MEM(2, 0),
1365 kXRDC2_Mem_FLEXSPI2_Region1 = XRDC2_MAKE_MEM(2, 1),
1366 kXRDC2_Mem_FLEXSPI2_Region2 = XRDC2_MAKE_MEM(2, 2),
1367 kXRDC2_Mem_FLEXSPI2_Region3 = XRDC2_MAKE_MEM(2, 3),
1368 kXRDC2_Mem_FLEXSPI2_Region4 = XRDC2_MAKE_MEM(2, 4),
1369 kXRDC2_Mem_FLEXSPI2_Region5 = XRDC2_MAKE_MEM(2, 5),
1370 kXRDC2_Mem_FLEXSPI2_Region6 = XRDC2_MAKE_MEM(2, 6),
1371 kXRDC2_Mem_FLEXSPI2_Region7 = XRDC2_MAKE_MEM(2, 7),
1372 kXRDC2_Mem_FLEXSPI2_Region8 = XRDC2_MAKE_MEM(2, 8),
1373 kXRDC2_Mem_FLEXSPI2_Region9 = XRDC2_MAKE_MEM(2, 9),
1374 kXRDC2_Mem_FLEXSPI2_Region10 = XRDC2_MAKE_MEM(2, 10),
1375 kXRDC2_Mem_FLEXSPI2_Region11 = XRDC2_MAKE_MEM(2, 11),
1376 kXRDC2_Mem_FLEXSPI2_Region12 = XRDC2_MAKE_MEM(2, 12),
1377 kXRDC2_Mem_FLEXSPI2_Region13 = XRDC2_MAKE_MEM(2, 13),
1378 kXRDC2_Mem_FLEXSPI2_Region14 = XRDC2_MAKE_MEM(2, 14),
1379 kXRDC2_Mem_FLEXSPI2_Region15 = XRDC2_MAKE_MEM(2, 15),
1380 kXRDC2_Mem_M4LMEM_Region0 = XRDC2_MAKE_MEM(3, 0),
1381 kXRDC2_Mem_M4LMEM_Region1 = XRDC2_MAKE_MEM(3, 1),
1382 kXRDC2_Mem_M4LMEM_Region2 = XRDC2_MAKE_MEM(3, 2),
1383 kXRDC2_Mem_M4LMEM_Region3 = XRDC2_MAKE_MEM(3, 3),
1384 kXRDC2_Mem_M4LMEM_Region4 = XRDC2_MAKE_MEM(3, 4),
1385 kXRDC2_Mem_M4LMEM_Region5 = XRDC2_MAKE_MEM(3, 5),
1386 kXRDC2_Mem_M4LMEM_Region6 = XRDC2_MAKE_MEM(3, 6),
1387 kXRDC2_Mem_M4LMEM_Region7 = XRDC2_MAKE_MEM(3, 7),
1388 kXRDC2_Mem_M4LMEM_Region8 = XRDC2_MAKE_MEM(3, 8),
1389 kXRDC2_Mem_M4LMEM_Region9 = XRDC2_MAKE_MEM(3, 9),
1390 kXRDC2_Mem_M4LMEM_Region10 = XRDC2_MAKE_MEM(3, 10),
1391 kXRDC2_Mem_M4LMEM_Region11 = XRDC2_MAKE_MEM(3, 11),
1392 kXRDC2_Mem_M4LMEM_Region12 = XRDC2_MAKE_MEM(3, 12),
1393 kXRDC2_Mem_M4LMEM_Region13 = XRDC2_MAKE_MEM(3, 13),
1394 kXRDC2_Mem_M4LMEM_Region14 = XRDC2_MAKE_MEM(3, 14),
1395 kXRDC2_Mem_M4LMEM_Region15 = XRDC2_MAKE_MEM(3, 15),
1396 kXRDC2_Mem_M7OC_Region0 = XRDC2_MAKE_MEM(4, 0),
1397 kXRDC2_Mem_M7OC_Region1 = XRDC2_MAKE_MEM(4, 1),
1398 kXRDC2_Mem_M7OC_Region2 = XRDC2_MAKE_MEM(4, 2),
1399 kXRDC2_Mem_M7OC_Region3 = XRDC2_MAKE_MEM(4, 3),
1400 kXRDC2_Mem_M7OC_Region4 = XRDC2_MAKE_MEM(4, 4),
1401 kXRDC2_Mem_M7OC_Region5 = XRDC2_MAKE_MEM(4, 5),
1402 kXRDC2_Mem_M7OC_Region6 = XRDC2_MAKE_MEM(4, 6),
1403 kXRDC2_Mem_M7OC_Region7 = XRDC2_MAKE_MEM(4, 7),
1404 kXRDC2_Mem_M7OC_Region8 = XRDC2_MAKE_MEM(4, 8),
1405 kXRDC2_Mem_M7OC_Region9 = XRDC2_MAKE_MEM(4, 9),
1406 kXRDC2_Mem_M7OC_Region10 = XRDC2_MAKE_MEM(4, 10),
1407 kXRDC2_Mem_M7OC_Region11 = XRDC2_MAKE_MEM(4, 11),
1408 kXRDC2_Mem_M7OC_Region12 = XRDC2_MAKE_MEM(4, 12),
1409 kXRDC2_Mem_M7OC_Region13 = XRDC2_MAKE_MEM(4, 13),
1410 kXRDC2_Mem_M7OC_Region14 = XRDC2_MAKE_MEM(4, 14),
1411 kXRDC2_Mem_M7OC_Region15 = XRDC2_MAKE_MEM(4, 15),
1412 kXRDC2_Mem_MECC1_Region0 = XRDC2_MAKE_MEM(5, 0),
1413 kXRDC2_Mem_MECC1_Region1 = XRDC2_MAKE_MEM(5, 1),
1414 kXRDC2_Mem_MECC1_Region2 = XRDC2_MAKE_MEM(5, 2),
1415 kXRDC2_Mem_MECC1_Region3 = XRDC2_MAKE_MEM(5, 3),
1416 kXRDC2_Mem_MECC1_Region4 = XRDC2_MAKE_MEM(5, 4),
1417 kXRDC2_Mem_MECC1_Region5 = XRDC2_MAKE_MEM(5, 5),
1418 kXRDC2_Mem_MECC1_Region6 = XRDC2_MAKE_MEM(5, 6),
1419 kXRDC2_Mem_MECC1_Region7 = XRDC2_MAKE_MEM(5, 7),
1420 kXRDC2_Mem_MECC1_Region8 = XRDC2_MAKE_MEM(5, 8),
1421 kXRDC2_Mem_MECC1_Region9 = XRDC2_MAKE_MEM(5, 9),
1422 kXRDC2_Mem_MECC1_Region10 = XRDC2_MAKE_MEM(5, 10),
1423 kXRDC2_Mem_MECC1_Region11 = XRDC2_MAKE_MEM(5, 11),
1424 kXRDC2_Mem_MECC1_Region12 = XRDC2_MAKE_MEM(5, 12),
1425 kXRDC2_Mem_MECC1_Region13 = XRDC2_MAKE_MEM(5, 13),
1426 kXRDC2_Mem_MECC1_Region14 = XRDC2_MAKE_MEM(5, 14),
1427 kXRDC2_Mem_MECC1_Region15 = XRDC2_MAKE_MEM(5, 15),
1428 kXRDC2_Mem_MECC2_Region0 = XRDC2_MAKE_MEM(6, 0),
1429 kXRDC2_Mem_MECC2_Region1 = XRDC2_MAKE_MEM(6, 1),
1430 kXRDC2_Mem_MECC2_Region2 = XRDC2_MAKE_MEM(6, 2),
1431 kXRDC2_Mem_MECC2_Region3 = XRDC2_MAKE_MEM(6, 3),
1432 kXRDC2_Mem_MECC2_Region4 = XRDC2_MAKE_MEM(6, 4),
1433 kXRDC2_Mem_MECC2_Region5 = XRDC2_MAKE_MEM(6, 5),
1434 kXRDC2_Mem_MECC2_Region6 = XRDC2_MAKE_MEM(6, 6),
1435 kXRDC2_Mem_MECC2_Region7 = XRDC2_MAKE_MEM(6, 7),
1436 kXRDC2_Mem_MECC2_Region8 = XRDC2_MAKE_MEM(6, 8),
1437 kXRDC2_Mem_MECC2_Region9 = XRDC2_MAKE_MEM(6, 9),
1438 kXRDC2_Mem_MECC2_Region10 = XRDC2_MAKE_MEM(6, 10),
1439 kXRDC2_Mem_MECC2_Region11 = XRDC2_MAKE_MEM(6, 11),
1440 kXRDC2_Mem_MECC2_Region12 = XRDC2_MAKE_MEM(6, 12),
1441 kXRDC2_Mem_MECC2_Region13 = XRDC2_MAKE_MEM(6, 13),
1442 kXRDC2_Mem_MECC2_Region14 = XRDC2_MAKE_MEM(6, 14),
1443 kXRDC2_Mem_MECC2_Region15 = XRDC2_MAKE_MEM(6, 15),
1444 kXRDC2_Mem_SEMC_Region0 = XRDC2_MAKE_MEM(7, 0),
1445 kXRDC2_Mem_SEMC_Region1 = XRDC2_MAKE_MEM(7, 1),
1446 kXRDC2_Mem_SEMC_Region2 = XRDC2_MAKE_MEM(7, 2),
1447 kXRDC2_Mem_SEMC_Region3 = XRDC2_MAKE_MEM(7, 3),
1448 kXRDC2_Mem_SEMC_Region4 = XRDC2_MAKE_MEM(7, 4),
1449 kXRDC2_Mem_SEMC_Region5 = XRDC2_MAKE_MEM(7, 5),
1450 kXRDC2_Mem_SEMC_Region6 = XRDC2_MAKE_MEM(7, 6),
1451 kXRDC2_Mem_SEMC_Region7 = XRDC2_MAKE_MEM(7, 7),
1452 kXRDC2_Mem_SEMC_Region8 = XRDC2_MAKE_MEM(7, 8),
1453 kXRDC2_Mem_SEMC_Region9 = XRDC2_MAKE_MEM(7, 9),
1454 kXRDC2_Mem_SEMC_Region10 = XRDC2_MAKE_MEM(7, 10),
1455 kXRDC2_Mem_SEMC_Region11 = XRDC2_MAKE_MEM(7, 11),
1456 kXRDC2_Mem_SEMC_Region12 = XRDC2_MAKE_MEM(7, 12),
1457 kXRDC2_Mem_SEMC_Region13 = XRDC2_MAKE_MEM(7, 13),
1458 kXRDC2_Mem_SEMC_Region14 = XRDC2_MAKE_MEM(7, 14),
1459 kXRDC2_Mem_SEMC_Region15 = XRDC2_MAKE_MEM(7, 15),
1460} xrdc2_mem_t;
1461
1463{
1468} xrdc2_mem_slot_t;
1469
1470typedef enum _xrdc2_periph
1471{
1472 kXRDC2_Periph_ACMP4 = XRDC2_MAKE_PERIPH(0, 108),
1473 kXRDC2_Periph_ACMP3 = XRDC2_MAKE_PERIPH(0, 107),
1474 kXRDC2_Periph_ACMP2 = XRDC2_MAKE_PERIPH(0, 106),
1475 kXRDC2_Periph_ACMP1 = XRDC2_MAKE_PERIPH(0, 105),
1476 kXRDC2_Periph_FLEXPWM4 = XRDC2_MAKE_PERIPH(0, 102),
1477 kXRDC2_Periph_FLEXPWM3 = XRDC2_MAKE_PERIPH(0, 101),
1478 kXRDC2_Periph_FLEXPWM2 = XRDC2_MAKE_PERIPH(0, 100),
1479 kXRDC2_Periph_FLEXPWM1 = XRDC2_MAKE_PERIPH(0, 99 ),
1480 kXRDC2_Periph_ENC4 = XRDC2_MAKE_PERIPH(0, 96 ),
1481 kXRDC2_Periph_ENC3 = XRDC2_MAKE_PERIPH(0, 95 ),
1482 kXRDC2_Periph_ENC2 = XRDC2_MAKE_PERIPH(0, 94 ),
1483 kXRDC2_Periph_ENC1 = XRDC2_MAKE_PERIPH(0, 93 ),
1484 kXRDC2_Periph_QTIMER4 = XRDC2_MAKE_PERIPH(0, 90 ),
1485 kXRDC2_Periph_QTIMER3 = XRDC2_MAKE_PERIPH(0, 89 ),
1486 kXRDC2_Periph_QTIMER2 = XRDC2_MAKE_PERIPH(0, 88 ),
1487 kXRDC2_Periph_QTIMER1 = XRDC2_MAKE_PERIPH(0, 87 ),
1488 kXRDC2_Periph_SIM2 = XRDC2_MAKE_PERIPH(0, 86 ),
1489 kXRDC2_Periph_SIM1 = XRDC2_MAKE_PERIPH(0, 85 ),
1490 kXRDC2_Periph_CCM_OBS = XRDC2_MAKE_PERIPH(0, 84 ),
1491 kXRDC2_Periph_GPIO6 = XRDC2_MAKE_PERIPH(0, 80 ),
1492 kXRDC2_Periph_GPIO5 = XRDC2_MAKE_PERIPH(0, 79 ),
1493 kXRDC2_Periph_GPIO4 = XRDC2_MAKE_PERIPH(0, 78 ),
1494 kXRDC2_Periph_GPIO3 = XRDC2_MAKE_PERIPH(0, 77 ),
1495 kXRDC2_Periph_GPIO2 = XRDC2_MAKE_PERIPH(0, 76 ),
1496 kXRDC2_Periph_GPIO1 = XRDC2_MAKE_PERIPH(0, 75 ),
1497 kXRDC2_Periph_LPSPI4 = XRDC2_MAKE_PERIPH(0, 72 ),
1498 kXRDC2_Periph_LPSPI3 = XRDC2_MAKE_PERIPH(0, 71 ),
1499 kXRDC2_Periph_LPSPI2 = XRDC2_MAKE_PERIPH(0, 70 ),
1500 kXRDC2_Periph_LPSPI1 = XRDC2_MAKE_PERIPH(0, 69 ),
1501 kXRDC2_Periph_LPI2C4 = XRDC2_MAKE_PERIPH(0, 68 ),
1502 kXRDC2_Periph_LPI2C3 = XRDC2_MAKE_PERIPH(0, 67 ),
1503 kXRDC2_Periph_LPI2C2 = XRDC2_MAKE_PERIPH(0, 66 ),
1504 kXRDC2_Periph_LPI2C1 = XRDC2_MAKE_PERIPH(0, 65 ),
1505 kXRDC2_Periph_GPT6 = XRDC2_MAKE_PERIPH(0, 64 ),
1506 kXRDC2_Periph_GPT5 = XRDC2_MAKE_PERIPH(0, 63 ),
1507 kXRDC2_Periph_GPT4 = XRDC2_MAKE_PERIPH(0, 62 ),
1508 kXRDC2_Periph_GPT3 = XRDC2_MAKE_PERIPH(0, 61 ),
1509 kXRDC2_Periph_GPT2 = XRDC2_MAKE_PERIPH(0, 60 ),
1510 kXRDC2_Periph_GPT1 = XRDC2_MAKE_PERIPH(0, 59 ),
1511 kXRDC2_Periph_IOMUXC = XRDC2_MAKE_PERIPH(0, 58 ),
1512 kXRDC2_Periph_IOMUXC_GPR = XRDC2_MAKE_PERIPH(0, 57 ),
1513 kXRDC2_Periph_KPP = XRDC2_MAKE_PERIPH(0, 56 ),
1514 kXRDC2_Periph_PIT1 = XRDC2_MAKE_PERIPH(0, 54 ),
1515 kXRDC2_Periph_SEMC = XRDC2_MAKE_PERIPH(0, 53 ),
1516 kXRDC2_Periph_FLEXSPI2 = XRDC2_MAKE_PERIPH(0, 52 ),
1517 kXRDC2_Periph_FLEXSPI1 = XRDC2_MAKE_PERIPH(0, 51 ),
1518 kXRDC2_Periph_CAN2 = XRDC2_MAKE_PERIPH(0, 50 ),
1519 kXRDC2_Periph_CAN1 = XRDC2_MAKE_PERIPH(0, 49 ),
1520 kXRDC2_Periph_AOI2 = XRDC2_MAKE_PERIPH(0, 47 ),
1521 kXRDC2_Periph_AOI1 = XRDC2_MAKE_PERIPH(0, 46 ),
1522 kXRDC2_Periph_FLEXIO2 = XRDC2_MAKE_PERIPH(0, 44 ),
1523 kXRDC2_Periph_FLEXIO1 = XRDC2_MAKE_PERIPH(0, 43 ),
1524 kXRDC2_Periph_LPUART10 = XRDC2_MAKE_PERIPH(0, 40 ),
1525 kXRDC2_Periph_LPUART9 = XRDC2_MAKE_PERIPH(0, 39 ),
1526 kXRDC2_Periph_LPUART8 = XRDC2_MAKE_PERIPH(0, 38 ),
1527 kXRDC2_Periph_LPUART7 = XRDC2_MAKE_PERIPH(0, 37 ),
1528 kXRDC2_Periph_LPUART6 = XRDC2_MAKE_PERIPH(0, 36 ),
1529 kXRDC2_Periph_LPUART5 = XRDC2_MAKE_PERIPH(0, 35 ),
1530 kXRDC2_Periph_LPUART4 = XRDC2_MAKE_PERIPH(0, 34 ),
1531 kXRDC2_Periph_LPUART3 = XRDC2_MAKE_PERIPH(0, 33 ),
1532 kXRDC2_Periph_LPUART2 = XRDC2_MAKE_PERIPH(0, 32 ),
1533 kXRDC2_Periph_LPUART1 = XRDC2_MAKE_PERIPH(0, 31 ),
1534 kXRDC2_Periph_DMA_CH_MUX = XRDC2_MAKE_PERIPH(0, 29 ),
1535 kXRDC2_Periph_EDMA = XRDC2_MAKE_PERIPH(0, 28 ),
1536 kXRDC2_Periph_IEE = XRDC2_MAKE_PERIPH(0, 27 ),
1537 kXRDC2_Periph_DAC = XRDC2_MAKE_PERIPH(0, 25 ),
1538 kXRDC2_Periph_TSC_DIG = XRDC2_MAKE_PERIPH(0, 23 ),
1539 kXRDC2_Periph_ADC2 = XRDC2_MAKE_PERIPH(0, 21 ),
1540 kXRDC2_Periph_ADC1 = XRDC2_MAKE_PERIPH(0, 20 ),
1541 kXRDC2_Periph_ADC_ETC = XRDC2_MAKE_PERIPH(0, 18 ),
1542 kXRDC2_Periph_XBAR3 = XRDC2_MAKE_PERIPH(0, 17 ),
1543 kXRDC2_Periph_XBAR2 = XRDC2_MAKE_PERIPH(0, 16 ),
1544 kXRDC2_Periph_XBAR1 = XRDC2_MAKE_PERIPH(0, 15 ),
1545 kXRDC2_Periph_WDOG3 = XRDC2_MAKE_PERIPH(0, 14 ),
1546 kXRDC2_Periph_WDOG2 = XRDC2_MAKE_PERIPH(0, 13 ),
1547 kXRDC2_Periph_WDOG1 = XRDC2_MAKE_PERIPH(0, 12 ),
1548 kXRDC2_Periph_EWM = XRDC2_MAKE_PERIPH(0, 11 ),
1549 kXRDC2_Periph_FLEXRAM = XRDC2_MAKE_PERIPH(0, 10 ),
1550 kXRDC2_Periph_XECC_SEMC = XRDC2_MAKE_PERIPH(0, 9 ),
1551 kXRDC2_Periph_XECC_FLEXSPI2 = XRDC2_MAKE_PERIPH(0, 8 ),
1552 kXRDC2_Periph_XECC_FLEXSPI1 = XRDC2_MAKE_PERIPH(0, 7 ),
1553 kXRDC2_Periph_MECC2 = XRDC2_MAKE_PERIPH(0, 6 ),
1554 kXRDC2_Periph_MECC1 = XRDC2_MAKE_PERIPH(0, 5 ),
1555 kXRDC2_Periph_MTR = XRDC2_MAKE_PERIPH(0, 4 ),
1556 kXRDC2_Periph_SFA = XRDC2_MAKE_PERIPH(0, 3 ),
1557 kXRDC2_Periph_CAAM_DEBUG_3 = XRDC2_MAKE_PERIPH(1, 51 ),
1558 kXRDC2_Periph_CAAM_DEBUG_2 = XRDC2_MAKE_PERIPH(1, 50 ),
1559 kXRDC2_Periph_CAAM_DEBUG_1 = XRDC2_MAKE_PERIPH(1, 49 ),
1560 kXRDC2_Periph_CAAM_DEBUG_0 = XRDC2_MAKE_PERIPH(1, 48 ),
1561 kXRDC2_Periph_CAAM_RTIC_3 = XRDC2_MAKE_PERIPH(1, 43 ),
1562 kXRDC2_Periph_CAAM_RTIC_2 = XRDC2_MAKE_PERIPH(1, 42 ),
1563 kXRDC2_Periph_CAAM_RTIC_1 = XRDC2_MAKE_PERIPH(1, 41 ),
1564 kXRDC2_Periph_CAAM_RTIC_0 = XRDC2_MAKE_PERIPH(1, 40 ),
1565 kXRDC2_Periph_CAAM_JR3_3 = XRDC2_MAKE_PERIPH(1, 35 ),
1566 kXRDC2_Periph_CAAM_JR3_2 = XRDC2_MAKE_PERIPH(1, 34 ),
1567 kXRDC2_Periph_CAAM_JR3_1 = XRDC2_MAKE_PERIPH(1, 33 ),
1568 kXRDC2_Periph_CAAM_JR3_0 = XRDC2_MAKE_PERIPH(1, 32 ),
1569 kXRDC2_Periph_CAAM_JR2_3 = XRDC2_MAKE_PERIPH(1, 31 ),
1570 kXRDC2_Periph_CAAM_JR2_2 = XRDC2_MAKE_PERIPH(1, 30 ),
1571 kXRDC2_Periph_CAAM_JR2_1 = XRDC2_MAKE_PERIPH(1, 29 ),
1572 kXRDC2_Periph_CAAM_JR2_0 = XRDC2_MAKE_PERIPH(1, 28 ),
1573 kXRDC2_Periph_CAAM_JR1_3 = XRDC2_MAKE_PERIPH(1, 27 ),
1574 kXRDC2_Periph_CAAM_JR1_2 = XRDC2_MAKE_PERIPH(1, 26 ),
1575 kXRDC2_Periph_CAAM_JR1_1 = XRDC2_MAKE_PERIPH(1, 25 ),
1576 kXRDC2_Periph_CAAM_JR1_0 = XRDC2_MAKE_PERIPH(1, 24 ),
1577 kXRDC2_Periph_CAAM_JR0_3 = XRDC2_MAKE_PERIPH(1, 23 ),
1578 kXRDC2_Periph_CAAM_JR0_2 = XRDC2_MAKE_PERIPH(1, 22 ),
1579 kXRDC2_Periph_CAAM_JR0_1 = XRDC2_MAKE_PERIPH(1, 21 ),
1580 kXRDC2_Periph_CAAM_JR0_0 = XRDC2_MAKE_PERIPH(1, 20 ),
1581 kXRDC2_Periph_CAAM_GENERAL_3 = XRDC2_MAKE_PERIPH(1, 19 ),
1582 kXRDC2_Periph_CAAM_GENERAL_2 = XRDC2_MAKE_PERIPH(1, 18 ),
1583 kXRDC2_Periph_CAAM_GENERAL_1 = XRDC2_MAKE_PERIPH(1, 17 ),
1584 kXRDC2_Periph_CAAM_GENERAL_0 = XRDC2_MAKE_PERIPH(1, 16 ),
1585 kXRDC2_Periph_ENET_QOS = XRDC2_MAKE_PERIPH(1, 15 ),
1586 kXRDC2_Periph_USBPHY2 = XRDC2_MAKE_PERIPH(1, 14 ),
1587 kXRDC2_Periph_USBPHY1 = XRDC2_MAKE_PERIPH(1, 13 ),
1588 kXRDC2_Periph_USB_OTG = XRDC2_MAKE_PERIPH(1, 12 ),
1589 kXRDC2_Periph_USB_OTG2 = XRDC2_MAKE_PERIPH(1, 11 ),
1590 kXRDC2_Periph_USB_PL301 = XRDC2_MAKE_PERIPH(1, 10 ),
1591 kXRDC2_Periph_ENET = XRDC2_MAKE_PERIPH(1, 9 ),
1592 kXRDC2_Periph_ENET_1G = XRDC2_MAKE_PERIPH(1, 8 ),
1593 kXRDC2_Periph_USDHC2 = XRDC2_MAKE_PERIPH(1, 7 ),
1594 kXRDC2_Periph_USDHC1 = XRDC2_MAKE_PERIPH(1, 6 ),
1595 kXRDC2_Periph_ASRC = XRDC2_MAKE_PERIPH(1, 5 ),
1596 kXRDC2_Periph_SAI3 = XRDC2_MAKE_PERIPH(1, 3 ),
1597 kXRDC2_Periph_SAI2 = XRDC2_MAKE_PERIPH(1, 2 ),
1598 kXRDC2_Periph_SAI1 = XRDC2_MAKE_PERIPH(1, 1 ),
1599 kXRDC2_Periph_SPDIF = XRDC2_MAKE_PERIPH(1, 0 ),
1600 kXRDC2_Periph_VIDEO_MUX = XRDC2_MAKE_PERIPH(2, 6 ),
1601 kXRDC2_Periph_PXP = XRDC2_MAKE_PERIPH(2, 5 ),
1602 kXRDC2_Periph_MIPI_CSI = XRDC2_MAKE_PERIPH(2, 4 ),
1603 kXRDC2_Periph_MIPI_DSI = XRDC2_MAKE_PERIPH(2, 3 ),
1604 kXRDC2_Periph_LCDIFV2 = XRDC2_MAKE_PERIPH(2, 2 ),
1605 kXRDC2_Periph_LCDIF = XRDC2_MAKE_PERIPH(2, 1 ),
1606 kXRDC2_Periph_CSI = XRDC2_MAKE_PERIPH(2, 0 ),
1607 kXRDC2_Periph_XRDC2_MGR_M7_3 = XRDC2_MAKE_PERIPH(3, 59 ),
1608 kXRDC2_Periph_XRDC2_MGR_M7_2 = XRDC2_MAKE_PERIPH(3, 58 ),
1609 kXRDC2_Periph_XRDC2_MGR_M7_1 = XRDC2_MAKE_PERIPH(3, 57 ),
1610 kXRDC2_Periph_XRDC2_MGR_M7_0 = XRDC2_MAKE_PERIPH(3, 56 ),
1611 kXRDC2_Periph_XRDC2_MGR_M4_3 = XRDC2_MAKE_PERIPH(3, 55 ),
1612 kXRDC2_Periph_XRDC2_MGR_M4_2 = XRDC2_MAKE_PERIPH(3, 54 ),
1613 kXRDC2_Periph_XRDC2_MGR_M4_1 = XRDC2_MAKE_PERIPH(3, 53 ),
1614 kXRDC2_Periph_XRDC2_MGR_M4_0 = XRDC2_MAKE_PERIPH(3, 52 ),
1615 kXRDC2_Periph_SEMA2 = XRDC2_MAKE_PERIPH(3, 51 ),
1616 kXRDC2_Periph_SEMA_HS = XRDC2_MAKE_PERIPH(3, 50 ),
1617 kXRDC2_Periph_CCM_1 = XRDC2_MAKE_PERIPH(3, 49 ),
1618 kXRDC2_Periph_CCM_0 = XRDC2_MAKE_PERIPH(3, 48 ),
1619 kXRDC2_Periph_SSARC_LP = XRDC2_MAKE_PERIPH(3, 46 ),
1620 kXRDC2_Periph_SSARC_HP = XRDC2_MAKE_PERIPH(3, 45 ),
1621 kXRDC2_Periph_PIT2 = XRDC2_MAKE_PERIPH(3, 44 ),
1622 kXRDC2_Periph_OCOTP_CTRL_WRAPPER = XRDC2_MAKE_PERIPH(3, 43 ),
1623 kXRDC2_Periph_DCDC = XRDC2_MAKE_PERIPH(3, 42 ),
1624 kXRDC2_Periph_ROMCP = XRDC2_MAKE_PERIPH(3, 41 ),
1625 kXRDC2_Periph_GPIO13 = XRDC2_MAKE_PERIPH(3, 40 ),
1626 kXRDC2_Periph_SNVS_SRAM = XRDC2_MAKE_PERIPH(3, 39 ),
1627 kXRDC2_Periph_IOMUXC_SNVS_GPR = XRDC2_MAKE_PERIPH(3, 38 ),
1628 kXRDC2_Periph_IOMUXC_SNVS = XRDC2_MAKE_PERIPH(3, 37 ),
1629 kXRDC2_Periph_SNVS_HP_WRAPPER = XRDC2_MAKE_PERIPH(3, 36 ),
1630 kXRDC2_Periph_PGMC = XRDC2_MAKE_PERIPH(3, 34 ),
1631 kXRDC2_Periph_ANATOP = XRDC2_MAKE_PERIPH(3, 33 ),
1632 kXRDC2_Periph_KEY_MANAGER = XRDC2_MAKE_PERIPH(3, 32 ),
1633 kXRDC2_Periph_RDC = XRDC2_MAKE_PERIPH(3, 30 ),
1634 kXRDC2_Periph_GPIO12 = XRDC2_MAKE_PERIPH(3, 28 ),
1635 kXRDC2_Periph_GPIO11 = XRDC2_MAKE_PERIPH(3, 27 ),
1636 kXRDC2_Periph_GPIO10 = XRDC2_MAKE_PERIPH(3, 26 ),
1637 kXRDC2_Periph_GPIO9 = XRDC2_MAKE_PERIPH(3, 25 ),
1638 kXRDC2_Periph_GPIO8 = XRDC2_MAKE_PERIPH(3, 24 ),
1639 kXRDC2_Periph_GPIO7 = XRDC2_MAKE_PERIPH(3, 23 ),
1640 kXRDC2_Periph_MU_B = XRDC2_MAKE_PERIPH(3, 19 ),
1641 kXRDC2_Periph_MU_A = XRDC2_MAKE_PERIPH(3, 18 ),
1642 kXRDC2_Periph_SEMA1 = XRDC2_MAKE_PERIPH(3, 17 ),
1643 kXRDC2_Periph_SAI4 = XRDC2_MAKE_PERIPH(3, 16 ),
1644 kXRDC2_Periph_CAN3 = XRDC2_MAKE_PERIPH(3, 15 ),
1645 kXRDC2_Periph_LPI2C6 = XRDC2_MAKE_PERIPH(3, 14 ),
1646 kXRDC2_Periph_LPI2C5 = XRDC2_MAKE_PERIPH(3, 13 ),
1647 kXRDC2_Periph_LPSPI6 = XRDC2_MAKE_PERIPH(3, 12 ),
1648 kXRDC2_Periph_LPSPI5 = XRDC2_MAKE_PERIPH(3, 11 ),
1649 kXRDC2_Periph_LPUART12 = XRDC2_MAKE_PERIPH(3, 10 ),
1650 kXRDC2_Periph_LPUART11 = XRDC2_MAKE_PERIPH(3, 9 ),
1651 kXRDC2_Periph_MIC = XRDC2_MAKE_PERIPH(3, 8 ),
1652 kXRDC2_Periph_DMA_CH_MUX_LPSR = XRDC2_MAKE_PERIPH(3, 6 ),
1653 kXRDC2_Periph_EDMA_LPSR = XRDC2_MAKE_PERIPH(3, 5 ),
1654 kXRDC2_Periph_WDOG4 = XRDC2_MAKE_PERIPH(3, 4 ),
1655 kXRDC2_Periph_IOMUXC_LPSR_GPR = XRDC2_MAKE_PERIPH(3, 3 ),
1656 kXRDC2_Periph_IOMUXC_LPSR = XRDC2_MAKE_PERIPH(3, 2 ),
1657 kXRDC2_Periph_SRC = XRDC2_MAKE_PERIPH(3, 1 ),
1658 kXRDC2_Periph_GPC = XRDC2_MAKE_PERIPH(3, 0 ),
1659 kXRDC2_Periph_GPU = XRDC2_MAKE_PERIPH(4, 0 ),
1660} xrdc2_periph_t;
1661
1662/* @} */
1663
1669/*******************************************************************************
1670 * Definitions
1671 ******************************************************************************/
1672
1678{
1696
1702/*******************************************************************************
1703 * Definitions
1704 ******************************************************************************/
1705
1714{
1746 kDmaRequestMuxCSI = 32|0x100U,
1747 kDmaRequestMuxPxp = 33|0x100U,
1858 kDmaRequestMuxPdm = 181|0x100U,
1863 kDmaRequestMuxCAN1 = 186|0x100U,
1864 kDmaRequestMuxCAN2 = 187|0x100U,
1865 kDmaRequestMuxCAN3 = 188|0x100U,
1866 kDmaRequestMuxDAC = 189|0x100U,
1878
1879/* @} */
1880
1885/*******************************************************************************
1886 * Definitions
1887*******************************************************************************/
1888
1895{
2042
2043/* @} */
2044
2049/*******************************************************************************
2050 * Definitions
2051*******************************************************************************/
2052
2059{
2206
2207/* @} */
2208
2215{
2364
2365 /* end of group Mapping_Information */
2369
2370
2371/* ----------------------------------------------------------------------------
2372 -- Device Peripheral Access Layer
2373 ---------------------------------------------------------------------------- */
2374
2381/*
2382** Start of section using anonymous unions
2383*/
2384
2385#if defined(__ARMCC_VERSION)
2386 #if (__ARMCC_VERSION >= 6010050)
2387 #pragma clang diagnostic push
2388 #else
2389 #pragma push
2390 #pragma anon_unions
2391 #endif
2392#elif defined(__CWCC__)
2393 #pragma push
2394 #pragma cpp_extensions on
2395#elif defined(__GNUC__)
2396 /* anonymous unions are enabled by default */
2397#elif defined(__IAR_SYSTEMS_ICC__)
2398 #pragma language=extended
2399#else
2400 #error Not supported compiler type
2401#endif
2402
2403/* ----------------------------------------------------------------------------
2404 -- ADC Peripheral Access Layer
2405 ---------------------------------------------------------------------------- */
2406
2413typedef struct {
2414 __I uint32_t VERID;
2415 __I uint32_t PARAM;
2416 uint8_t RESERVED_0[8];
2417 __IO uint32_t CTRL;
2418 __IO uint32_t STAT;
2419 __IO uint32_t IE;
2420 __IO uint32_t DE;
2421 __IO uint32_t CFG;
2422 __IO uint32_t PAUSE;
2423 uint8_t RESERVED_1[8];
2424 __IO uint32_t FCTRL;
2425 __O uint32_t SWTRIG;
2426 uint8_t RESERVED_2[136];
2427 __IO uint32_t TCTRL[8];
2428 uint8_t RESERVED_3[32];
2429 struct { /* offset: 0x100, array step: 0x8 */
2430 __IO uint32_t CMDL;
2431 __IO uint32_t CMDH;
2432 } CMD[15];
2433 uint8_t RESERVED_4[136];
2434 __IO uint32_t CV[4];
2435 uint8_t RESERVED_5[240];
2436 __I uint32_t RESFIFO;
2437} ADC_Type;
2438
2439/* ----------------------------------------------------------------------------
2440 -- ADC Register Masks
2441 ---------------------------------------------------------------------------- */
2442
2451#define ADC_VERID_RES_MASK (0x1U)
2452#define ADC_VERID_RES_SHIFT (0U)
2457#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
2458
2459#define ADC_VERID_DIFFEN_MASK (0x2U)
2460#define ADC_VERID_DIFFEN_SHIFT (1U)
2465#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
2466
2467#define ADC_VERID_MVI_MASK (0x8U)
2468#define ADC_VERID_MVI_SHIFT (3U)
2473#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
2474
2475#define ADC_VERID_CSW_MASK (0x70U)
2476#define ADC_VERID_CSW_SHIFT (4U)
2482#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
2483
2484#define ADC_VERID_VR1RNGI_MASK (0x100U)
2485#define ADC_VERID_VR1RNGI_SHIFT (8U)
2490#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
2491
2492#define ADC_VERID_IADCKI_MASK (0x200U)
2493#define ADC_VERID_IADCKI_SHIFT (9U)
2498#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
2499
2500#define ADC_VERID_CALOFSI_MASK (0x400U)
2501#define ADC_VERID_CALOFSI_SHIFT (10U)
2506#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
2507
2508#define ADC_VERID_MINOR_MASK (0xFF0000U)
2509#define ADC_VERID_MINOR_SHIFT (16U)
2512#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
2513
2514#define ADC_VERID_MAJOR_MASK (0xFF000000U)
2515#define ADC_VERID_MAJOR_SHIFT (24U)
2518#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
2524#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
2525#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
2529#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
2530
2531#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
2532#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
2536#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
2537
2538#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
2539#define ADC_PARAM_CV_NUM_SHIFT (16U)
2543#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
2544
2545#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
2546#define ADC_PARAM_CMD_NUM_SHIFT (24U)
2550#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
2556#define ADC_CTRL_ADCEN_MASK (0x1U)
2557#define ADC_CTRL_ADCEN_SHIFT (0U)
2562#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
2563
2564#define ADC_CTRL_RST_MASK (0x2U)
2565#define ADC_CTRL_RST_SHIFT (1U)
2570#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
2571
2572#define ADC_CTRL_DOZEN_MASK (0x4U)
2573#define ADC_CTRL_DOZEN_SHIFT (2U)
2578#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
2579
2580#define ADC_CTRL_TRIG_SRC_MASK (0x18U)
2581#define ADC_CTRL_TRIG_SRC_SHIFT (3U)
2588#define ADC_CTRL_TRIG_SRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TRIG_SRC_SHIFT)) & ADC_CTRL_TRIG_SRC_MASK)
2589
2590#define ADC_CTRL_RSTFIFO_MASK (0x100U)
2591#define ADC_CTRL_RSTFIFO_SHIFT (8U)
2596#define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
2602#define ADC_STAT_RDY_MASK (0x1U)
2603#define ADC_STAT_RDY_SHIFT (0U)
2608#define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
2609
2610#define ADC_STAT_FOF_MASK (0x2U)
2611#define ADC_STAT_FOF_SHIFT (1U)
2616#define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
2617
2618#define ADC_STAT_ADC_ACTIVE_MASK (0x100U)
2619#define ADC_STAT_ADC_ACTIVE_SHIFT (8U)
2624#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
2625
2626#define ADC_STAT_TRGACT_MASK (0x70000U)
2627#define ADC_STAT_TRGACT_SHIFT (16U)
2634#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
2635
2636#define ADC_STAT_CMDACT_MASK (0xF000000U)
2637#define ADC_STAT_CMDACT_SHIFT (24U)
2644#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
2650#define ADC_IE_FWMIE_MASK (0x1U)
2651#define ADC_IE_FWMIE_SHIFT (0U)
2656#define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
2657
2658#define ADC_IE_FOFIE_MASK (0x2U)
2659#define ADC_IE_FOFIE_SHIFT (1U)
2664#define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
2670#define ADC_DE_FWMDE_MASK (0x1U)
2671#define ADC_DE_FWMDE_SHIFT (0U)
2676#define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
2682#define ADC_CFG_TPRICTRL_MASK (0x1U)
2683#define ADC_CFG_TPRICTRL_SHIFT (0U)
2692#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
2693
2694#define ADC_CFG_PWRSEL_MASK (0x30U)
2695#define ADC_CFG_PWRSEL_SHIFT (4U)
2702#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
2703
2704#define ADC_CFG_REFSEL_MASK (0xC0U)
2705#define ADC_CFG_REFSEL_SHIFT (6U)
2712#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
2713
2714#define ADC_CFG_PUDLY_MASK (0xFF0000U)
2715#define ADC_CFG_PUDLY_SHIFT (16U)
2718#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
2719
2720#define ADC_CFG_PWREN_MASK (0x10000000U)
2721#define ADC_CFG_PWREN_SHIFT (28U)
2728#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
2734#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
2735#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
2738#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
2739
2740#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
2741#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
2746#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
2752#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
2753#define ADC_FCTRL_FCOUNT_SHIFT (0U)
2762#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
2763
2764#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
2765#define ADC_FCTRL_FWMARK_SHIFT (16U)
2784#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
2790#define ADC_SWTRIG_SWT0_MASK (0x1U)
2791#define ADC_SWTRIG_SWT0_SHIFT (0U)
2796#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
2797
2798#define ADC_SWTRIG_SWT1_MASK (0x2U)
2799#define ADC_SWTRIG_SWT1_SHIFT (1U)
2804#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
2805
2806#define ADC_SWTRIG_SWT2_MASK (0x4U)
2807#define ADC_SWTRIG_SWT2_SHIFT (2U)
2812#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
2813
2814#define ADC_SWTRIG_SWT3_MASK (0x8U)
2815#define ADC_SWTRIG_SWT3_SHIFT (3U)
2820#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
2821
2822#define ADC_SWTRIG_SWT4_MASK (0x10U)
2823#define ADC_SWTRIG_SWT4_SHIFT (4U)
2828#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
2829
2830#define ADC_SWTRIG_SWT5_MASK (0x20U)
2831#define ADC_SWTRIG_SWT5_SHIFT (5U)
2836#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
2837
2838#define ADC_SWTRIG_SWT6_MASK (0x40U)
2839#define ADC_SWTRIG_SWT6_SHIFT (6U)
2844#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
2845
2846#define ADC_SWTRIG_SWT7_MASK (0x80U)
2847#define ADC_SWTRIG_SWT7_SHIFT (7U)
2852#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
2858#define ADC_TCTRL_HTEN_MASK (0x1U)
2859#define ADC_TCTRL_HTEN_SHIFT (0U)
2864#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
2865
2866#define ADC_TCTRL_CMD_SEL_MASK (0x2U)
2867#define ADC_TCTRL_CMD_SEL_SHIFT (1U)
2873#define ADC_TCTRL_CMD_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_CMD_SEL_SHIFT)) & ADC_TCTRL_CMD_SEL_MASK)
2874
2875#define ADC_TCTRL_TPRI_MASK (0x700U)
2876#define ADC_TCTRL_TPRI_SHIFT (8U)
2882#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
2883
2884#define ADC_TCTRL_TDLY_MASK (0xF0000U)
2885#define ADC_TCTRL_TDLY_SHIFT (16U)
2888#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
2889
2890#define ADC_TCTRL_TCMD_MASK (0xF000000U)
2891#define ADC_TCTRL_TCMD_SHIFT (24U)
2898#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
2901/* The count of ADC_TCTRL */
2902#define ADC_TCTRL_COUNT (8U)
2903
2907#define ADC_CMDL_ADCH_MASK (0x1FU)
2908#define ADC_CMDL_ADCH_SHIFT (0U)
2918#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
2919
2920#define ADC_CMDL_ABSEL_MASK (0x20U)
2921#define ADC_CMDL_ABSEL_SHIFT (5U)
2926#define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
2927
2928#define ADC_CMDL_DIFF_MASK (0x40U)
2929#define ADC_CMDL_DIFF_SHIFT (6U)
2934#define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
2935
2936#define ADC_CMDL_CSCALE_MASK (0x2000U)
2937#define ADC_CMDL_CSCALE_SHIFT (13U)
2942#define ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
2945/* The count of ADC_CMDL */
2946#define ADC_CMDL_COUNT (15U)
2947
2951#define ADC_CMDH_CMPEN_MASK (0x3U)
2952#define ADC_CMDH_CMPEN_SHIFT (0U)
2959#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
2960
2961#define ADC_CMDH_LWI_MASK (0x80U)
2962#define ADC_CMDH_LWI_SHIFT (7U)
2967#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
2968
2969#define ADC_CMDH_STS_MASK (0x700U)
2970#define ADC_CMDH_STS_SHIFT (8U)
2981#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
2982
2983#define ADC_CMDH_AVGS_MASK (0x7000U)
2984#define ADC_CMDH_AVGS_SHIFT (12U)
2995#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
2996
2997#define ADC_CMDH_LOOP_MASK (0xF0000U)
2998#define ADC_CMDH_LOOP_SHIFT (16U)
3006#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
3007
3008#define ADC_CMDH_NEXT_MASK (0xF000000U)
3009#define ADC_CMDH_NEXT_SHIFT (24U)
3017#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
3020/* The count of ADC_CMDH */
3021#define ADC_CMDH_COUNT (15U)
3022
3026#define ADC_CV_CVL_MASK (0xFFFFU)
3027#define ADC_CV_CVL_SHIFT (0U)
3030#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
3031
3032#define ADC_CV_CVH_MASK (0xFFFF0000U)
3033#define ADC_CV_CVH_SHIFT (16U)
3036#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
3039/* The count of ADC_CV */
3040#define ADC_CV_COUNT (4U)
3041
3045#define ADC_RESFIFO_D_MASK (0xFFFFU)
3046#define ADC_RESFIFO_D_SHIFT (0U)
3049#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
3050
3051#define ADC_RESFIFO_TSRC_MASK (0x70000U)
3052#define ADC_RESFIFO_TSRC_SHIFT (16U)
3059#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
3060
3061#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
3062#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
3069#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
3070
3071#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
3072#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
3080#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
3081
3082#define ADC_RESFIFO_VALID_MASK (0x80000000U)
3083#define ADC_RESFIFO_VALID_SHIFT (31U)
3088#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) /* end of group ADC_Register_Masks */
3095
3096
3097/* ADC - Peripheral instance base addresses */
3099#define LPADC1_BASE (0x40050000u)
3101#define LPADC1 ((ADC_Type *)LPADC1_BASE)
3103#define LPADC2_BASE (0x40054000u)
3105#define LPADC2 ((ADC_Type *)LPADC2_BASE)
3107#define ADC_BASE_ADDRS { 0u, LPADC1_BASE, LPADC2_BASE }
3109#define ADC_BASE_PTRS { (ADC_Type *)0u, LPADC1, LPADC2 }
3111#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
3112 /* end of group ADC_Peripheral_Access_Layer */
3116
3117
3118/* ----------------------------------------------------------------------------
3119 -- ADC_ETC Peripheral Access Layer
3120 ---------------------------------------------------------------------------- */
3121
3128typedef struct {
3129 __IO uint32_t CTRL;
3130 __IO uint32_t DONE0_1_IRQ;
3131 __IO uint32_t DONE2_3_ERR_IRQ;
3132 __IO uint32_t DMA_CTRL;
3133 struct { /* offset: 0x10, array step: 0x28 */
3134 __IO uint32_t TRIGn_CTRL;
3144 } TRIG[8];
3145} ADC_ETC_Type;
3146
3147/* ----------------------------------------------------------------------------
3148 -- ADC_ETC Register Masks
3149 ---------------------------------------------------------------------------- */
3150
3159#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
3160#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
3168#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
3169
3170#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
3171#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
3172#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
3173
3174#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
3175#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
3180#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
3181
3182#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
3183#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
3188#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
3194#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
3195#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
3200#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
3201
3202#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
3203#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
3208#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
3209
3210#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
3211#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
3216#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
3217
3218#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
3219#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
3224#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
3225
3226#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
3227#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
3232#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
3233
3234#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
3235#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
3240#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
3241
3242#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
3243#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
3248#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
3249
3250#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
3251#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
3256#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
3257
3258#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
3259#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
3264#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
3265
3266#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
3267#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
3272#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
3273
3274#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
3275#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
3280#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
3281
3282#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
3283#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
3288#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
3289
3290#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
3291#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
3296#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
3297
3298#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
3299#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
3304#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
3305
3306#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
3307#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
3312#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
3313
3314#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
3315#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
3320#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
3326#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
3327#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
3332#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK)
3333
3334#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
3335#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
3340#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK)
3341
3342#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
3343#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
3348#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK)
3349
3350#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
3351#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
3356#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK)
3357
3358#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
3359#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
3364#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK)
3365
3366#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
3367#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
3372#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK)
3373
3374#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
3375#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
3380#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK)
3381
3382#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
3383#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
3388#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK)
3389
3390#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK (0x100U)
3391#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT (8U)
3396#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK)
3397
3398#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK (0x200U)
3399#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT (9U)
3404#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK)
3405
3406#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK (0x400U)
3407#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT (10U)
3412#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK)
3413
3414#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK (0x800U)
3415#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT (11U)
3420#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK)
3421
3422#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK (0x1000U)
3423#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT (12U)
3428#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK)
3429
3430#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK (0x2000U)
3431#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT (13U)
3436#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK)
3437
3438#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK (0x4000U)
3439#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT (14U)
3444#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK)
3445
3446#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK (0x8000U)
3447#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT (15U)
3452#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK)
3453
3454#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
3455#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
3460#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK)
3461
3462#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
3463#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
3468#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK)
3469
3470#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
3471#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
3476#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK)
3477
3478#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
3479#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
3484#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK)
3485
3486#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
3487#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
3492#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK)
3493
3494#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
3495#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
3500#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK)
3501
3502#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
3503#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
3508#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK)
3509
3510#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
3511#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
3516#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK)
3522#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
3523#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
3528#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
3529
3530#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
3531#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
3536#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
3537
3538#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
3539#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
3544#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
3545
3546#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
3547#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
3552#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
3553
3554#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
3555#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
3560#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
3561
3562#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
3563#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
3568#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
3569
3570#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
3571#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
3576#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
3577
3578#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
3579#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
3584#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
3585
3586#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
3587#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
3592#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
3593
3594#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
3595#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
3600#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
3601
3602#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
3603#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
3608#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
3609
3610#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
3611#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
3616#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
3617
3618#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
3619#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
3624#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
3625
3626#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
3627#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
3632#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
3633
3634#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
3635#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
3640#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
3641
3642#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
3643#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
3648#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
3654#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
3655#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
3660#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
3661
3662#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
3663#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
3668#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
3669
3670#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
3671#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
3682#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
3683
3684#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
3685#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
3686#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
3687
3688#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
3689#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
3694#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
3695
3696#define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK (0xFF000000U)
3697#define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT (24U)
3702#define ADC_ETC_TRIGn_CTRL_CHAINx_DONE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT)) & ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK)
3705/* The count of ADC_ETC_TRIGn_CTRL */
3706#define ADC_ETC_TRIGn_CTRL_COUNT (8U)
3707
3711#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
3712#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
3713#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
3714
3715#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
3716#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
3717#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
3720/* The count of ADC_ETC_TRIGn_COUNTER */
3721#define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
3722
3726#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
3727#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
3746#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
3747
3748#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
3749#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
3761#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
3762
3763#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
3764#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
3769#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
3770
3771#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
3772#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
3779#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
3780
3781#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK (0x8000U)
3782#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT (15U)
3787#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK)
3788
3789#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
3790#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
3809#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
3810
3811#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
3812#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
3824#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
3825
3826#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
3827#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
3832#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
3833
3834#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
3835#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
3842#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
3843
3844#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK (0x80000000U)
3845#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT (31U)
3850#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK)
3853/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
3854#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
3855
3859#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
3860#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
3879#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
3880
3881#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
3882#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
3894#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
3895
3896#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
3897#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
3902#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
3903
3904#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
3905#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
3912#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
3913
3914#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK (0x8000U)
3915#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT (15U)
3920#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK)
3921
3922#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
3923#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
3942#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
3943
3944#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
3945#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
3957#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
3958
3959#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
3960#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
3965#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
3966
3967#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
3968#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
3975#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
3976
3977#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK (0x80000000U)
3978#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT (31U)
3983#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK)
3986/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
3987#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
3988
3992#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
3993#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
4012#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
4013
4014#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
4015#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
4027#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
4028
4029#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
4030#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
4035#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
4036
4037#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
4038#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
4045#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
4046
4047#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK (0x8000U)
4048#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT (15U)
4053#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK)
4054
4055#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
4056#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
4075#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
4076
4077#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
4078#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
4090#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
4091
4092#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
4093#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
4098#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
4099
4100#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
4101#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
4108#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
4109
4110#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK (0x80000000U)
4111#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT (31U)
4116#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK)
4119/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
4120#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
4121
4125#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
4126#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
4145#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
4146
4147#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
4148#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
4160#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
4161
4162#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
4163#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
4168#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
4169
4170#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
4171#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
4178#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
4179
4180#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK (0x8000U)
4181#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT (15U)
4186#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK)
4187
4188#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
4189#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
4208#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
4209
4210#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
4211#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
4223#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
4224
4225#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
4226#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
4231#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
4232
4233#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
4234#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
4241#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
4242
4243#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK (0x80000000U)
4244#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT (31U)
4249#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK)
4252/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
4253#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
4254
4258#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
4259#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
4260#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
4261
4262#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
4263#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
4264#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
4267/* The count of ADC_ETC_TRIGn_RESULT_1_0 */
4268#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
4269
4273#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
4274#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
4275#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
4276
4277#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
4278#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
4279#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
4282/* The count of ADC_ETC_TRIGn_RESULT_3_2 */
4283#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
4284
4288#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
4289#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
4290#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
4291
4292#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
4293#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
4294#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
4297/* The count of ADC_ETC_TRIGn_RESULT_5_4 */
4298#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
4299
4303#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
4304#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
4305#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
4306
4307#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
4308#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
4309#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
4312/* The count of ADC_ETC_TRIGn_RESULT_7_6 */
4313#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
4314
4315 /* end of group ADC_ETC_Register_Masks */
4319
4320
4321/* ADC_ETC - Peripheral instance base addresses */
4323#define ADC_ETC_BASE (0x40048000u)
4325#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
4327#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
4329#define ADC_ETC_BASE_PTRS { ADC_ETC }
4331#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn, ADC_ETC_IRQ3_IRQn } }
4332#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
4333 /* end of group ADC_ETC_Peripheral_Access_Layer */
4337
4338
4339/* ----------------------------------------------------------------------------
4340 -- ANADIG_LDO_SNVS Peripheral Access Layer
4341 ---------------------------------------------------------------------------- */
4342
4349typedef struct {
4350 uint8_t RESERVED_0[1296];
4351 __IO uint32_t PMU_LDO_LPSR_ANA;
4352 uint8_t RESERVED_1[12];
4353 __IO uint32_t PMU_LDO_LPSR_DIG_2;
4354 uint8_t RESERVED_2[12];
4355 __IO uint32_t PMU_LDO_LPSR_DIG;
4357
4358/* ----------------------------------------------------------------------------
4359 -- ANADIG_LDO_SNVS Register Masks
4360 ---------------------------------------------------------------------------- */
4361
4370#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK (0x1U)
4371#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT (0U)
4374#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK)
4375
4376#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK (0x4U)
4377#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT (2U)
4380#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK)
4381
4382#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK (0x8U)
4383#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT (3U)
4386#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK)
4387
4388#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK (0x10U)
4389#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT (4U)
4394#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK)
4395
4396#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK (0x20U)
4397#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT (5U)
4400#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK)
4401
4402#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK (0x40U)
4403#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT (6U)
4406#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK)
4407
4408#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK (0x100U)
4409#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT (8U)
4412#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK)
4413
4414#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK (0x80000U)
4415#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT (19U)
4420#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK)
4421
4422#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK (0x100000U)
4423#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT (20U)
4426#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK)
4432#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK (0x3U)
4433#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT (0U)
4436#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK)
4442#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK (0x4U)
4443#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT (2U)
4446#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK)
4447
4448#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK (0x20U)
4449#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT (5U)
4454#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK)
4455
4456#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK (0x40U)
4457#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT (6U)
4460#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK)
4461
4462#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK (0x20000U)
4463#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT (17U)
4466#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK)
4467
4468#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK (0x40000U)
4469#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT (18U)
4472#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK)
4473
4474#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK (0x1F00000U)
4475#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT (20U)
4510#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK) /* end of group ANADIG_LDO_SNVS_Register_Masks */
4517
4518
4519/* ANADIG_LDO_SNVS - Peripheral instance base addresses */
4521#define ANADIG_LDO_SNVS_BASE (0x40C84000u)
4523#define ANADIG_LDO_SNVS ((ANADIG_LDO_SNVS_Type *)ANADIG_LDO_SNVS_BASE)
4525#define ANADIG_LDO_SNVS_BASE_ADDRS { ANADIG_LDO_SNVS_BASE }
4527#define ANADIG_LDO_SNVS_BASE_PTRS { ANADIG_LDO_SNVS }
4528 /* end of group ANADIG_LDO_SNVS_Peripheral_Access_Layer */
4532
4533
4534/* ----------------------------------------------------------------------------
4535 -- ANADIG_LDO_SNVS_DIG Peripheral Access Layer
4536 ---------------------------------------------------------------------------- */
4537
4544typedef struct {
4545 uint8_t RESERVED_0[1344];
4546 __IO uint32_t PMU_LDO_SNVS_DIG;
4548
4549/* ----------------------------------------------------------------------------
4550 -- ANADIG_LDO_SNVS_DIG Register Masks
4551 ---------------------------------------------------------------------------- */
4552
4561#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK (0x1U)
4562#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT (0U)
4565#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK)
4566
4567#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK (0x2U)
4568#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT (1U)
4571#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK)
4572
4573#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK (0x4U)
4574#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT (2U)
4577#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK) /* end of group ANADIG_LDO_SNVS_DIG_Register_Masks */
4584
4585
4586/* ANADIG_LDO_SNVS_DIG - Peripheral instance base addresses */
4588#define ANADIG_LDO_SNVS_DIG_BASE (0x40C84000u)
4590#define ANADIG_LDO_SNVS_DIG ((ANADIG_LDO_SNVS_DIG_Type *)ANADIG_LDO_SNVS_DIG_BASE)
4592#define ANADIG_LDO_SNVS_DIG_BASE_ADDRS { ANADIG_LDO_SNVS_DIG_BASE }
4594#define ANADIG_LDO_SNVS_DIG_BASE_PTRS { ANADIG_LDO_SNVS_DIG }
4595 /* end of group ANADIG_LDO_SNVS_DIG_Peripheral_Access_Layer */
4599
4600
4601/* ----------------------------------------------------------------------------
4602 -- ANADIG_MISC Peripheral Access Layer
4603 ---------------------------------------------------------------------------- */
4604
4611typedef struct {
4612 uint8_t RESERVED_0[2048];
4613 __I uint32_t MISC_DIFPROG;
4614 uint8_t RESERVED_1[28];
4615 __IO uint32_t VDDSOC_AI_CTRL;
4616 uint8_t RESERVED_2[12];
4617 __IO uint32_t VDDSOC_AI_WDATA;
4618 uint8_t RESERVED_3[12];
4619 __I uint32_t VDDSOC_AI_RDATA;
4620 uint8_t RESERVED_4[12];
4621 __IO uint32_t VDDSOC2PLL_AI_CTRL_1G;
4622 uint8_t RESERVED_5[12];
4623 __IO uint32_t VDDSOC2PLL_AI_WDATA_1G;
4624 uint8_t RESERVED_6[12];
4625 __I uint32_t VDDSOC2PLL_AI_RDATA_1G;
4626 uint8_t RESERVED_7[12];
4627 __IO uint32_t VDDSOC2PLL_AI_CTRL_AUDIO;
4628 uint8_t RESERVED_8[12];
4629 __IO uint32_t VDDSOC2PLL_AI_WDATA_AUDIO;
4630 uint8_t RESERVED_9[12];
4631 __I uint32_t VDDSOC2PLL_AI_RDATA_AUDIO;
4632 uint8_t RESERVED_10[12];
4633 __IO uint32_t VDDSOC2PLL_AI_CTRL_VIDEO;
4634 uint8_t RESERVED_11[12];
4635 __IO uint32_t VDDSOC2PLL_AI_WDATA_VIDEO;
4636 uint8_t RESERVED_12[12];
4637 __I uint32_t VDDSOC2PLL_AI_RDATA_VIDEO;
4638 uint8_t RESERVED_13[12];
4639 __IO uint32_t VDDLPSR_AI_CTRL;
4640 uint8_t RESERVED_14[12];
4641 __IO uint32_t VDDLPSR_AI_WDATA;
4642 uint8_t RESERVED_15[12];
4643 __I uint32_t VDDLPSR_AI_RDATA_REFTOP;
4644 uint8_t RESERVED_16[12];
4645 __I uint32_t VDDLPSR_AI_RDATA_TMPSNS;
4646 uint8_t RESERVED_17[12];
4647 __IO uint32_t VDDLPSR_AI400M_CTRL;
4648 uint8_t RESERVED_18[12];
4649 __IO uint32_t VDDLPSR_AI400M_WDATA;
4650 uint8_t RESERVED_19[12];
4651 __I uint32_t VDDLPSR_AI400M_RDATA;
4653
4654/* ----------------------------------------------------------------------------
4655 -- ANADIG_MISC Register Masks
4656 ---------------------------------------------------------------------------- */
4657
4666#define ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK (0xFFFFFFFFU)
4667#define ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT (0U)
4670#define ANADIG_MISC_MISC_DIFPROG_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT)) & ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK)
4676#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK (0xFFU)
4677#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT (0U)
4680#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK)
4681
4682#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK (0x10000U)
4683#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT (16U)
4686#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK)
4692#define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK (0xFFFFFFFFU)
4693#define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT (0U)
4696#define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK)
4702#define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK (0xFFFFFFFFU)
4703#define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT (0U)
4706#define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK)
4712#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK (0xFFU)
4713#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT (0U)
4716#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK)
4717
4718#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK (0x100U)
4719#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT (8U)
4722#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK)
4723
4724#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK (0x200U)
4725#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT (9U)
4728#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK)
4729
4730#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK (0x10000U)
4731#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT (16U)
4734#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK)
4740#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK (0xFFFFFFFFU)
4741#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT (0U)
4744#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK)
4750#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK (0xFFFFFFFFU)
4751#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT (0U)
4754#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK)
4760#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK (0xFFU)
4761#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT (0U)
4764#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK)
4765
4766#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK (0x100U)
4767#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT (8U)
4770#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK)
4771
4772#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK (0x200U)
4773#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT (9U)
4776#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK)
4777
4778#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK (0x10000U)
4779#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT (16U)
4782#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK)
4788#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK (0xFFFFFFFFU)
4789#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT (0U)
4792#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK)
4798#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK (0xFFFFFFFFU)
4799#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT (0U)
4802#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK)
4808#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK (0xFFU)
4809#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT (0U)
4812#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK)
4813
4814#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK (0x100U)
4815#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT (8U)
4818#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK)
4819
4820#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK (0x200U)
4821#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT (9U)
4824#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK)
4825
4826#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK (0x10000U)
4827#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT (16U)
4830#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK)
4836#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK (0xFFFFFFFFU)
4837#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT (0U)
4840#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK)
4846#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK (0xFFFFFFFFU)
4847#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT (0U)
4850#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK)
4856#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK (0xFFU)
4857#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT (0U)
4860#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK)
4861
4862#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK (0x10000U)
4863#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT (16U)
4866#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK)
4872#define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK (0xFFFFFFFFU)
4873#define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT (0U)
4876#define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK)
4882#define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK (0xFFFFFFFFU)
4883#define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT (0U)
4886#define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK)
4892#define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK (0xFFFFFFFFU)
4893#define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT (0U)
4896#define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK)
4902#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK (0xFFU)
4903#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT (0U)
4906#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK)
4907
4908#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK (0x100U)
4909#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT (8U)
4912#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK)
4913
4914#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK (0x200U)
4915#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT (9U)
4918#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK)
4919
4920#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK (0x10000U)
4921#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT (16U)
4924#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK)
4930#define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK (0xFFFFFFFFU)
4931#define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT (0U)
4934#define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK)
4940#define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK (0xFFFFFFFFU)
4941#define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT (0U)
4944#define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK) /* end of group ANADIG_MISC_Register_Masks */
4951
4952
4953/* ANADIG_MISC - Peripheral instance base addresses */
4955#define ANADIG_MISC_BASE (0x40C84000u)
4957#define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE)
4959#define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE }
4961#define ANADIG_MISC_BASE_PTRS { ANADIG_MISC }
4962 /* end of group ANADIG_MISC_Peripheral_Access_Layer */
4966
4967
4968/* ----------------------------------------------------------------------------
4969 -- ANADIG_OSC Peripheral Access Layer
4970 ---------------------------------------------------------------------------- */
4971
4978typedef struct {
4979 uint8_t RESERVED_0[16];
4980 __IO uint32_t OSC_48M_CTRL;
4981 uint8_t RESERVED_1[12];
4982 __IO uint32_t OSC_24M_CTRL;
4983 uint8_t RESERVED_2[28];
4984 __I uint32_t OSC_400M_CTRL0;
4985 uint8_t RESERVED_3[12];
4986 __IO uint32_t OSC_400M_CTRL1;
4987 uint8_t RESERVED_4[12];
4988 __IO uint32_t OSC_400M_CTRL2;
4989 uint8_t RESERVED_5[92];
4990 __IO uint32_t OSC_16M_CTRL;
4992
4993/* ----------------------------------------------------------------------------
4994 -- ANADIG_OSC Register Masks
4995 ---------------------------------------------------------------------------- */
4996
5005#define ANADIG_OSC_OSC_48M_CTRL_TEN_MASK (0x2U)
5006#define ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT (1U)
5011#define ANADIG_OSC_OSC_48M_CTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TEN_MASK)
5012
5013#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK (0x1000000U)
5014#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT (24U)
5019#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK)
5020
5021#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK (0x40000000U)
5022#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT (30U)
5027#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)
5028
5029#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK (0x80000000U)
5030#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT (31U)
5035#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)
5041#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK (0x1U)
5042#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT (0U)
5045#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK)
5046
5047#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK (0x2U)
5048#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT (1U)
5053#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK)
5054
5055#define ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK (0x4U)
5056#define ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT (2U)
5061#define ANADIG_OSC_OSC_24M_CTRL_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK)
5062
5063#define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK (0x8U)
5064#define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT (3U)
5069#define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK)
5070
5071#define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK (0x10U)
5072#define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT (4U)
5077#define ANADIG_OSC_OSC_24M_CTRL_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)
5078
5079#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK (0x80U)
5080#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT (7U)
5085#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK)
5086
5087#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK (0x40000000U)
5088#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT (30U)
5093#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)
5094
5095#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK (0x80000000U)
5096#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT (31U)
5101#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)
5107#define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK (0x80000000U)
5108#define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT (31U)
5111#define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK)
5117#define ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK (0x1U)
5118#define ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT (0U)
5123#define ANADIG_OSC_OSC_400M_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK)
5124
5125#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK (0x2U)
5126#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT (1U)
5131#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK)
5132
5133#define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK (0x80000000U)
5134#define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT (31U)
5139#define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)
5145#define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK (0x1U)
5146#define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT (0U)
5151#define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK)
5152
5153#define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK (0x400U)
5154#define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT (10U)
5159#define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK)
5160
5161#define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U)
5162#define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U)
5165#define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK)
5171#define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK (0x2U)
5172#define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT (1U)
5177#define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK)
5178
5179#define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK (0x8U)
5180#define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT (3U)
5185#define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK)
5186
5187#define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK (0x100U)
5188#define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT (8U)
5193#define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK)
5194
5195#define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK (0x80000000U)
5196#define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT (31U)
5201#define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK) /* end of group ANADIG_OSC_Register_Masks */
5208
5209
5210/* ANADIG_OSC - Peripheral instance base addresses */
5212#define ANADIG_OSC_BASE (0x40C84000u)
5214#define ANADIG_OSC ((ANADIG_OSC_Type *)ANADIG_OSC_BASE)
5216#define ANADIG_OSC_BASE_ADDRS { ANADIG_OSC_BASE }
5218#define ANADIG_OSC_BASE_PTRS { ANADIG_OSC }
5219 /* end of group ANADIG_OSC_Peripheral_Access_Layer */
5223
5224
5225/* ----------------------------------------------------------------------------
5226 -- ANADIG_PLL Peripheral Access Layer
5227 ---------------------------------------------------------------------------- */
5228
5235typedef struct {
5236 uint8_t RESERVED_0[512];
5237 __IO uint32_t ARM_PLL_CTRL;
5238 uint8_t RESERVED_1[12];
5239 __IO uint32_t SYS_PLL3_CTRL;
5240 uint8_t RESERVED_2[12];
5241 __IO uint32_t SYS_PLL3_UPDATE;
5242 uint8_t RESERVED_3[12];
5243 __IO uint32_t SYS_PLL3_PFD;
5244 uint8_t RESERVED_4[12];
5245 __IO uint32_t SYS_PLL2_CTRL;
5246 uint8_t RESERVED_5[12];
5247 __IO uint32_t SYS_PLL2_UPDATE;
5248 uint8_t RESERVED_6[12];
5249 __IO uint32_t SYS_PLL2_SS;
5250 uint8_t RESERVED_7[12];
5251 __IO uint32_t SYS_PLL2_PFD;
5252 uint8_t RESERVED_8[44];
5253 __IO uint32_t SYS_PLL2_MFD;
5254 uint8_t RESERVED_9[12];
5255 __IO uint32_t SYS_PLL1_SS;
5256 uint8_t RESERVED_10[12];
5257 __IO uint32_t SYS_PLL1_CTRL;
5258 uint8_t RESERVED_11[12];
5259 __IO uint32_t SYS_PLL1_DENOMINATOR;
5260 uint8_t RESERVED_12[12];
5261 __IO uint32_t SYS_PLL1_NUMERATOR;
5262 uint8_t RESERVED_13[12];
5263 __IO uint32_t SYS_PLL1_DIV_SELECT;
5264 uint8_t RESERVED_14[12];
5265 __IO uint32_t PLL_AUDIO_CTRL;
5266 uint8_t RESERVED_15[12];
5267 __IO uint32_t PLL_AUDIO_SS;
5268 uint8_t RESERVED_16[12];
5269 __IO uint32_t PLL_AUDIO_DENOMINATOR;
5270 uint8_t RESERVED_17[12];
5271 __IO uint32_t PLL_AUDIO_NUMERATOR;
5272 uint8_t RESERVED_18[12];
5273 __IO uint32_t PLL_AUDIO_DIV_SELECT;
5274 uint8_t RESERVED_19[12];
5275 __IO uint32_t PLL_VIDEO_CTRL;
5276 uint8_t RESERVED_20[12];
5277 __IO uint32_t PLL_VIDEO_SS;
5278 uint8_t RESERVED_21[12];
5279 __IO uint32_t PLL_VIDEO_DENOMINATOR;
5280 uint8_t RESERVED_22[12];
5281 __IO uint32_t PLL_VIDEO_NUMERATOR;
5282 uint8_t RESERVED_23[12];
5283 __IO uint32_t PLL_VIDEO_DIV_SELECT;
5285
5286/* ----------------------------------------------------------------------------
5287 -- ANADIG_PLL Register Masks
5288 ---------------------------------------------------------------------------- */
5289
5298#define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK (0xFFU)
5299#define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT (0U)
5302#define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK)
5303
5304#define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK (0x1000U)
5305#define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT (12U)
5310#define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK)
5311
5312#define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK (0x2000U)
5313#define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT (13U)
5318#define ANADIG_PLL_ARM_PLL_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK)
5319
5320#define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK (0x4000U)
5321#define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT (14U)
5326#define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK)
5327
5328#define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK (0x18000U)
5329#define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT (15U)
5336#define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK)
5337
5338#define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK (0x20000U)
5339#define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT (17U)
5344#define ANADIG_PLL_ARM_PLL_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK)
5345
5346#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK (0x20000000U)
5347#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT (29U)
5352#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK)
5353
5354#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK (0x40000000U)
5355#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT (30U)
5360#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK)
5361
5362#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK (0x80000000U)
5363#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT (31U)
5368#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK)
5374#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK (0x8U)
5375#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT (3U)
5378#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK)
5379
5380#define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK (0x10U)
5381#define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT (4U)
5384#define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK)
5385
5386#define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK (0x800U)
5387#define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT (11U)
5392#define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK)
5393
5394#define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK (0x2000U)
5395#define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT (13U)
5400#define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK)
5401
5402#define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK (0x10000U)
5403#define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT (16U)
5408#define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK)
5409
5410#define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK (0x200000U)
5411#define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT (21U)
5416#define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK)
5417
5418#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK (0x10000000U)
5419#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT (28U)
5424#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK)
5425
5426#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK (0x20000000U)
5427#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT (29U)
5430#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK)
5431
5432#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK (0x40000000U)
5433#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT (30U)
5438#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK)
5439
5440#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK (0x80000000U)
5441#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT (31U)
5446#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK)
5452#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK (0x2U)
5453#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT (1U)
5456#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK)
5457
5458#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK (0x4U)
5459#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT (2U)
5462#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK)
5463
5464#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK (0x8U)
5465#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT (3U)
5468#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK)
5469
5470#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK (0x10U)
5471#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT (4U)
5474#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK)
5475
5476#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
5477#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
5482#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK)
5483
5484#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
5485#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
5490#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK)
5491
5492#define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK (0x80U)
5493#define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT (7U)
5498#define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK)
5499
5500#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
5501#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
5506#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK)
5512#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK (0x3FU)
5513#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT (0U)
5516#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK)
5517
5518#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK (0x40U)
5519#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT (6U)
5522#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK)
5523
5524#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
5525#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
5530#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK)
5531
5532#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK (0x3F00U)
5533#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT (8U)
5536#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK)
5537
5538#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK (0x4000U)
5539#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT (14U)
5542#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK)
5543
5544#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
5545#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
5550#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK)
5551
5552#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK (0x3F0000U)
5553#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT (16U)
5556#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK)
5557
5558#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK (0x400000U)
5559#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT (22U)
5562#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK)
5563
5564#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
5565#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
5570#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK)
5571
5572#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK (0x3F000000U)
5573#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT (24U)
5576#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK)
5577
5578#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK (0x40000000U)
5579#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT (30U)
5582#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK)
5583
5584#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
5585#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
5590#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK)
5596#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK (0x8U)
5597#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT (3U)
5600#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK)
5601
5602#define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK (0x800U)
5603#define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT (11U)
5608#define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK)
5609
5610#define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK (0x2000U)
5611#define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT (13U)
5616#define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)
5617
5618#define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK (0x10000U)
5619#define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT (16U)
5624#define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK)
5625
5626#define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK (0x20000U)
5627#define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT (17U)
5632#define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK)
5633
5634#define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK (0x40000U)
5635#define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT (18U)
5638#define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK)
5639
5640#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK (0x80000U)
5641#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT (19U)
5644#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK)
5645
5646#define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK (0x800000U)
5647#define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT (23U)
5652#define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK)
5653
5654#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK (0x20000000U)
5655#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT (29U)
5658#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK)
5659
5660#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK (0x40000000U)
5661#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT (30U)
5666#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK)
5667
5668#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK (0x80000000U)
5669#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT (31U)
5674#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK)
5680#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK (0x2U)
5681#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT (1U)
5684#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK)
5685
5686#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK (0x4U)
5687#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT (2U)
5690#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK)
5691
5692#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK (0x8U)
5693#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT (3U)
5696#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK)
5697
5698#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK (0x10U)
5699#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT (4U)
5702#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK)
5703
5704#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
5705#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
5710#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK)
5711
5712#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
5713#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
5718#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK)
5719
5720#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK (0x80U)
5721#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT (7U)
5726#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK)
5727
5728#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
5729#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
5734#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK)
5740#define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU)
5741#define ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT (0U)
5744#define ANADIG_PLL_SYS_PLL2_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
5745
5746#define ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK (0x8000U)
5747#define ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT (15U)
5752#define ANADIG_PLL_SYS_PLL2_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK)
5753
5754#define ANADIG_PLL_SYS_PLL2_SS_STOP_MASK (0xFFFF0000U)
5755#define ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT (16U)
5758#define ANADIG_PLL_SYS_PLL2_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STOP_MASK)
5764#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK (0x3FU)
5765#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT (0U)
5768#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK)
5769
5770#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK (0x40U)
5771#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT (6U)
5774#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK)
5775
5776#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
5777#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
5780#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK)
5781
5782#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK (0x3F00U)
5783#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT (8U)
5786#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK)
5787
5788#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK (0x4000U)
5789#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT (14U)
5792#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK)
5793
5794#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
5795#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
5798#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK)
5799
5800#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK (0x3F0000U)
5801#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT (16U)
5804#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK)
5805
5806#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK (0x400000U)
5807#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT (22U)
5810#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK)
5811
5812#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
5813#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
5816#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK)
5817
5818#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK (0x3F000000U)
5819#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT (24U)
5822#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK)
5823
5824#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK (0x40000000U)
5825#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT (30U)
5828#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK)
5829
5830#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
5831#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
5834#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK)
5840#define ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK (0x3FFFFFFFU)
5841#define ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT (0U)
5844#define ANADIG_PLL_SYS_PLL2_MFD_MFD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT)) & ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK)
5850#define ANADIG_PLL_SYS_PLL1_SS_STEP_MASK (0x7FFFU)
5851#define ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT (0U)
5854#define ANADIG_PLL_SYS_PLL1_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STEP_MASK)
5855
5856#define ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK (0x8000U)
5857#define ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT (15U)
5862#define ANADIG_PLL_SYS_PLL1_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK)
5863
5864#define ANADIG_PLL_SYS_PLL1_SS_STOP_MASK (0xFFFF0000U)
5865#define ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT (16U)
5868#define ANADIG_PLL_SYS_PLL1_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STOP_MASK)
5874#define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK (0x2000U)
5875#define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT (13U)
5878#define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK)
5879
5880#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK (0x4000U)
5881#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT (14U)
5886#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK)
5887
5888#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK (0x2000000U)
5889#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT (25U)
5892#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK)
5893
5894#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK (0x4000000U)
5895#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT (26U)
5898#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK)
5899
5900#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK (0x8000000U)
5901#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT (27U)
5906#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK)
5907
5908#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK (0x10000000U)
5909#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT (28U)
5914#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK)
5915
5916#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK (0x20000000U)
5917#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT (29U)
5920#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK)
5921
5922#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK (0x40000000U)
5923#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT (30U)
5926#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK)
5927
5928#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK (0x80000000U)
5929#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT (31U)
5934#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK)
5940#define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
5941#define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT (0U)
5944#define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK)
5950#define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
5951#define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT (0U)
5954#define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK)
5960#define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
5961#define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT (0U)
5964#define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK)
5970#define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK (0x2000U)
5971#define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT (13U)
5974#define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK)
5975
5976#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK (0x4000U)
5977#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT (14U)
5982#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK)
5983
5984#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK (0x20000000U)
5985#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT (29U)
5988#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK)
5989
5990#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK (0x40000000U)
5991#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT (30U)
5994#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK)
5995
5996#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK (0x80000000U)
5997#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT (31U)
6002#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK)
6008#define ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK (0x7FFFU)
6009#define ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT (0U)
6012#define ANADIG_PLL_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK)
6013
6014#define ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK (0x8000U)
6015#define ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT (15U)
6020#define ANADIG_PLL_PLL_AUDIO_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK)
6021
6022#define ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK (0xFFFF0000U)
6023#define ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT (16U)
6026#define ANADIG_PLL_PLL_AUDIO_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK)
6032#define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
6033#define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT (0U)
6036#define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK)
6042#define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
6043#define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT (0U)
6046#define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK)
6052#define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
6053#define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
6056#define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK)
6062#define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK (0x2000U)
6063#define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT (13U)
6066#define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK)
6067
6068#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK (0x4000U)
6069#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT (14U)
6074#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK)
6075
6076#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK (0x1000000U)
6077#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT (24U)
6080#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK)
6081
6082#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK (0x20000000U)
6083#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT (29U)
6086#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK)
6087
6088#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK (0x40000000U)
6089#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT (30U)
6092#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK)
6093
6094#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK (0x80000000U)
6095#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT (31U)
6100#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK)
6106#define ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK (0x7FFFU)
6107#define ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT (0U)
6110#define ANADIG_PLL_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK)
6111
6112#define ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK (0x8000U)
6113#define ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT (15U)
6118#define ANADIG_PLL_PLL_VIDEO_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK)
6119
6120#define ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK (0xFFFF0000U)
6121#define ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT (16U)
6124#define ANADIG_PLL_PLL_VIDEO_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK)
6130#define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
6131#define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT (0U)
6134#define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK)
6140#define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
6141#define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT (0U)
6144#define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK)
6150#define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
6151#define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT (0U)
6154#define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK) /* end of group ANADIG_PLL_Register_Masks */
6161
6162
6163/* ANADIG_PLL - Peripheral instance base addresses */
6165#define ANADIG_PLL_BASE (0x40C84000u)
6167#define ANADIG_PLL ((ANADIG_PLL_Type *)ANADIG_PLL_BASE)
6169#define ANADIG_PLL_BASE_ADDRS { ANADIG_PLL_BASE }
6171#define ANADIG_PLL_BASE_PTRS { ANADIG_PLL }
6172 /* end of group ANADIG_PLL_Peripheral_Access_Layer */
6176
6177
6178/* ----------------------------------------------------------------------------
6179 -- ANADIG_PMU Peripheral Access Layer
6180 ---------------------------------------------------------------------------- */
6181
6188typedef struct {
6189 uint8_t RESERVED_0[1280];
6190 __IO uint32_t PMU_LDO_PLL;
6191 uint8_t RESERVED_1[76];
6192 __IO uint32_t PMU_BIAS_CTRL;
6193 uint8_t RESERVED_2[12];
6194 __IO uint32_t PMU_BIAS_CTRL2;
6195 uint8_t RESERVED_3[12];
6196 __IO uint32_t PMU_REF_CTRL;
6197 uint8_t RESERVED_4[12];
6198 __IO uint32_t PMU_POWER_DETECT_CTRL;
6199 uint8_t RESERVED_5[124];
6200 __IO uint32_t LDO_PLL_ENABLE_SP;
6201 uint8_t RESERVED_6[12];
6202 __IO uint32_t LDO_LPSR_ANA_ENABLE_SP;
6203 uint8_t RESERVED_7[12];
6204 __IO uint32_t LDO_LPSR_ANA_LP_MODE_SP;
6205 uint8_t RESERVED_8[12];
6206 __IO uint32_t LDO_LPSR_ANA_TRACKING_EN_SP;
6207 uint8_t RESERVED_9[12];
6208 __IO uint32_t LDO_LPSR_ANA_BYPASS_EN_SP;
6209 uint8_t RESERVED_10[12];
6210 __IO uint32_t LDO_LPSR_ANA_STBY_EN_SP;
6211 uint8_t RESERVED_11[12];
6212 __IO uint32_t LDO_LPSR_DIG_ENABLE_SP;
6213 uint8_t RESERVED_12[12];
6214 __IO uint32_t LDO_LPSR_DIG_TRG_SP0;
6215 uint8_t RESERVED_13[12];
6216 __IO uint32_t LDO_LPSR_DIG_TRG_SP1;
6217 uint8_t RESERVED_14[12];
6218 __IO uint32_t LDO_LPSR_DIG_TRG_SP2;
6219 uint8_t RESERVED_15[12];
6220 __IO uint32_t LDO_LPSR_DIG_TRG_SP3;
6221 uint8_t RESERVED_16[12];
6222 __IO uint32_t LDO_LPSR_DIG_LP_MODE_SP;
6223 uint8_t RESERVED_17[12];
6224 __IO uint32_t LDO_LPSR_DIG_TRACKING_EN_SP;
6225 uint8_t RESERVED_18[12];
6226 __IO uint32_t LDO_LPSR_DIG_BYPASS_EN_SP;
6227 uint8_t RESERVED_19[12];
6228 __IO uint32_t LDO_LPSR_DIG_STBY_EN_SP;
6229 uint8_t RESERVED_20[12];
6230 __IO uint32_t BANDGAP_ENABLE_SP;
6231 uint8_t RESERVED_21[28];
6232 __IO uint32_t RBB_SOC_ENABLE_SP;
6233 uint8_t RESERVED_22[12];
6234 __IO uint32_t RBB_LPSR_ENABLE_SP;
6235 uint8_t RESERVED_23[12];
6236 __IO uint32_t BANDGAP_STBY_EN_SP;
6237 uint8_t RESERVED_24[12];
6238 __IO uint32_t PLL_LDO_STBY_EN_SP;
6239 uint8_t RESERVED_25[28];
6240 __IO uint32_t RBB_SOC_STBY_EN_SP;
6241 uint8_t RESERVED_26[12];
6242 __IO uint32_t RBB_LPSR_STBY_EN_SP;
6243 uint8_t RESERVED_27[28];
6244 __IO uint32_t RBB_LPSR_CONFIGURE;
6245 uint8_t RESERVED_28[12];
6246 __IO uint32_t RBB_SOC_CONFIGURE;
6247 uint8_t RESERVED_29[12];
6248 __I uint32_t REFTOP_OTP_TRIM_VALUE;
6249 uint8_t RESERVED_30[28];
6250 __I uint32_t LPSR_1P8_LDO_OTP_TRIM_VALUE;
6252
6253/* ----------------------------------------------------------------------------
6254 -- ANADIG_PMU Register Masks
6255 ---------------------------------------------------------------------------- */
6256
6265#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK (0x1U)
6266#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT (0U)
6269#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK)
6270
6271#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK (0x2U)
6272#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT (1U)
6277#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK)
6278
6279#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK (0x10000U)
6280#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT (16U)
6283#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK)
6284
6285#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK (0x40000000U)
6286#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT (30U)
6289#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK)
6295#define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK (0x1FFFU)
6296#define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT (0U)
6299#define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK)
6300
6301#define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK (0x4000U)
6302#define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT (14U)
6307#define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK)
6313#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK (0x3FEU)
6314#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT (1U)
6317#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK)
6318
6319#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK (0x1C00U)
6320#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT (10U)
6325#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK)
6326
6327#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK (0x1FE000U)
6328#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT (13U)
6347#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK)
6348
6349#define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK (0x400000U)
6350#define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT (22U)
6355#define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK)
6356
6357#define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK (0x800000U)
6358#define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT (23U)
6363#define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK)
6364
6365#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK (0x1000000U)
6366#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT (24U)
6369#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK)
6370
6371#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK (0x2000000U)
6372#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT (25U)
6375#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK)
6376
6377#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK (0x4000000U)
6378#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT (26U)
6381#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK)
6387#define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK (0x1U)
6388#define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT (0U)
6391#define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK)
6392
6393#define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK (0x2U)
6394#define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT (1U)
6397#define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK)
6398
6399#define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK (0x4U)
6400#define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT (2U)
6403#define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK)
6404
6405#define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK (0x8U)
6406#define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT (3U)
6411#define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK)
6412
6413#define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK (0x10U)
6414#define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT (4U)
6417#define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK)
6423#define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK (0x100U)
6424#define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT (8U)
6427#define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT)) & ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK)
6433#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
6434#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
6439#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
6440
6441#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
6442#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
6447#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
6448
6449#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
6450#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
6455#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
6456
6457#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
6458#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
6463#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
6464
6465#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
6466#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
6471#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
6472
6473#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
6474#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
6479#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
6480
6481#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
6482#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
6487#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
6488
6489#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
6490#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
6495#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
6496
6497#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
6498#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
6503#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
6504
6505#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
6506#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
6511#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
6512
6513#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
6514#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
6519#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
6520
6521#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
6522#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
6527#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
6528
6529#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
6530#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
6535#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
6536
6537#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
6538#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
6543#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
6544
6545#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
6546#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
6551#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
6552
6553#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
6554#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
6559#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
6565#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
6566#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
6571#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
6572
6573#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
6574#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
6579#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
6580
6581#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
6582#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
6587#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
6588
6589#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
6590#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
6595#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
6596
6597#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
6598#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
6603#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
6604
6605#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
6606#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
6611#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
6612
6613#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
6614#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
6619#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
6620
6621#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
6622#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
6627#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
6628
6629#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
6630#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
6635#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
6636
6637#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
6638#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
6643#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
6644
6645#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
6646#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
6651#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
6652
6653#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
6654#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
6659#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
6660
6661#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
6662#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
6667#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
6668
6669#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
6670#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
6675#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
6676
6677#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
6678#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
6683#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
6684
6685#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
6686#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
6691#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
6697#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U)
6698#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U)
6703#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK)
6704
6705#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U)
6706#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U)
6711#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK)
6712
6713#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK (0x4U)
6714#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT (2U)
6719#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK)
6720
6721#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK (0x8U)
6722#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT (3U)
6727#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK)
6728
6729#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK (0x10U)
6730#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT (4U)
6735#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK)
6736
6737#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK (0x20U)
6738#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT (5U)
6743#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK)
6744
6745#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK (0x40U)
6746#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT (6U)
6751#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK)
6752
6753#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK (0x80U)
6754#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT (7U)
6759#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK)
6760
6761#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK (0x100U)
6762#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT (8U)
6767#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK)
6768
6769#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK (0x200U)
6770#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT (9U)
6775#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK)
6776
6777#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK (0x400U)
6778#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT (10U)
6783#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK)
6784
6785#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK (0x800U)
6786#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT (11U)
6791#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK)
6792
6793#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK (0x1000U)
6794#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT (12U)
6799#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK)
6800
6801#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK (0x2000U)
6802#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT (13U)
6807#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK)
6808
6809#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK (0x4000U)
6810#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT (14U)
6815#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK)
6816
6817#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK (0x8000U)
6818#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT (15U)
6823#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK)
6829#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U)
6830#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U)
6835#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK)
6836
6837#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U)
6838#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U)
6843#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK)
6844
6845#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U)
6846#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U)
6851#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK)
6852
6853#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U)
6854#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U)
6859#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK)
6860
6861#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U)
6862#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U)
6867#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK)
6868
6869#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U)
6870#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U)
6875#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK)
6876
6877#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U)
6878#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U)
6883#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK)
6884
6885#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U)
6886#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U)
6891#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK)
6892
6893#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U)
6894#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U)
6899#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK)
6900
6901#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U)
6902#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U)
6907#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK)
6908
6909#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U)
6910#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U)
6915#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK)
6916
6917#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U)
6918#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U)
6923#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK)
6924
6925#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U)
6926#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U)
6931#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK)
6932
6933#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U)
6934#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U)
6939#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK)
6940
6941#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U)
6942#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U)
6947#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK)
6948
6949#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U)
6950#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U)
6955#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK)
6961#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U)
6962#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U)
6967#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK)
6968
6969#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U)
6970#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U)
6975#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK)
6976
6977#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U)
6978#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U)
6983#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK)
6984
6985#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U)
6986#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U)
6991#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK)
6992
6993#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U)
6994#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U)
6999#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK)
7000
7001#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U)
7002#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U)
7007#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK)
7008
7009#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U)
7010#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U)
7015#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK)
7016
7017#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U)
7018#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U)
7023#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK)
7024
7025#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U)
7026#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U)
7031#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK)
7032
7033#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U)
7034#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U)
7039#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK)
7040
7041#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U)
7042#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U)
7047#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK)
7048
7049#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U)
7050#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U)
7055#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK)
7056
7057#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U)
7058#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U)
7063#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK)
7064
7065#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U)
7066#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U)
7071#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK)
7072
7073#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U)
7074#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U)
7079#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK)
7080
7081#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U)
7082#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U)
7087#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK)
7093#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
7094#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
7099#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
7100
7101#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
7102#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
7107#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
7108
7109#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
7110#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
7115#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
7116
7117#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
7118#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
7123#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
7124
7125#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
7126#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
7131#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
7132
7133#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
7134#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
7139#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
7140
7141#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
7142#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
7147#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
7148
7149#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
7150#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
7155#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
7156
7157#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
7158#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
7163#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
7164
7165#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
7166#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
7171#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
7172
7173#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
7174#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
7179#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
7180
7181#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
7182#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
7187#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
7188
7189#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
7190#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
7195#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
7196
7197#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
7198#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
7203#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
7204
7205#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
7206#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
7211#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
7212
7213#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
7214#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
7219#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
7225#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
7226#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
7231#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
7232
7233#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
7234#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
7239#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
7240
7241#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
7242#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
7247#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
7248
7249#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
7250#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
7255#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
7256
7257#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
7258#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
7263#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
7264
7265#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
7266#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
7271#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
7272
7273#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
7274#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
7279#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
7280
7281#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
7282#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
7287#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
7288
7289#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
7290#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
7295#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
7296
7297#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
7298#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
7303#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
7304
7305#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
7306#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
7311#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
7312
7313#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
7314#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
7319#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
7320
7321#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
7322#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
7327#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
7328
7329#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
7330#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
7335#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
7336
7337#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
7338#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
7343#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
7344
7345#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
7346#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
7351#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
7357#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK (0xFFU)
7358#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT (0U)
7361#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK)
7362
7363#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK (0xFF00U)
7364#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT (8U)
7367#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK)
7368
7369#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK (0xFF0000U)
7370#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT (16U)
7373#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK)
7374
7375#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK (0xFF000000U)
7376#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT (24U)
7379#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK)
7385#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK (0xFFU)
7386#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT (0U)
7389#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK)
7390
7391#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK (0xFF00U)
7392#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT (8U)
7395#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK)
7396
7397#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK (0xFF0000U)
7398#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT (16U)
7401#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK)
7402
7403#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK (0xFF000000U)
7404#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT (24U)
7407#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK)
7413#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK (0xFFU)
7414#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT (0U)
7417#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK)
7418
7419#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK (0xFF00U)
7420#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT (8U)
7423#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK)
7424
7425#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK (0xFF0000U)
7426#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT (16U)
7429#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK)
7430
7431#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK (0xFF000000U)
7432#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT (24U)
7435#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK)
7441#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK (0xFFU)
7442#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT (0U)
7445#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK)
7446
7447#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK (0xFF00U)
7448#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT (8U)
7451#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK)
7452
7453#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK (0xFF0000U)
7454#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT (16U)
7457#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK)
7458
7459#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK (0xFF000000U)
7460#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT (24U)
7463#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK)
7469#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U)
7470#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U)
7475#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK)
7476
7477#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U)
7478#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U)
7483#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK)
7484
7485#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK (0x4U)
7486#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT (2U)
7491#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK)
7492
7493#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK (0x8U)
7494#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT (3U)
7499#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK)
7500
7501#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK (0x10U)
7502#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT (4U)
7507#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK)
7508
7509#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK (0x20U)
7510#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT (5U)
7515#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK)
7516
7517#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK (0x40U)
7518#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT (6U)
7523#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK)
7524
7525#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK (0x80U)
7526#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT (7U)
7531#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK)
7532
7533#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK (0x100U)
7534#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT (8U)
7539#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK)
7540
7541#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK (0x200U)
7542#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT (9U)
7547#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK)
7548
7549#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK (0x400U)
7550#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT (10U)
7555#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK)
7556
7557#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK (0x800U)
7558#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT (11U)
7563#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK)
7564
7565#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK (0x1000U)
7566#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT (12U)
7571#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK)
7572
7573#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK (0x2000U)
7574#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT (13U)
7579#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK)
7580
7581#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK (0x4000U)
7582#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT (14U)
7587#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK)
7588
7589#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK (0x8000U)
7590#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT (15U)
7595#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK)
7601#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U)
7602#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U)
7607#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK)
7608
7609#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U)
7610#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U)
7615#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK)
7616
7617#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U)
7618#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U)
7623#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK)
7624
7625#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U)
7626#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U)
7631#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK)
7632
7633#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U)
7634#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U)
7639#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK)
7640
7641#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U)
7642#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U)
7647#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK)
7648
7649#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U)
7650#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U)
7655#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK)
7656
7657#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U)
7658#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U)
7663#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK)
7664
7665#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U)
7666#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U)
7671#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK)
7672
7673#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U)
7674#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U)
7679#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK)
7680
7681#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U)
7682#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U)
7687#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK)
7688
7689#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U)
7690#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U)
7695#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK)
7696
7697#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U)
7698#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U)
7703#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK)
7704
7705#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U)
7706#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U)
7711#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK)
7712
7713#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U)
7714#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U)
7719#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK)
7720
7721#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U)
7722#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U)
7727#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK)
7733#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U)
7734#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U)
7739#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK)
7740
7741#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U)
7742#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U)
7747#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK)
7748
7749#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U)
7750#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U)
7755#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK)
7756
7757#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U)
7758#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U)
7763#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK)
7764
7765#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U)
7766#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U)
7771#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK)
7772
7773#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U)
7774#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U)
7779#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK)
7780
7781#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U)
7782#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U)
7787#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK)
7788
7789#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U)
7790#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U)
7795#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK)
7796
7797#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U)
7798#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U)
7803#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK)
7804
7805#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U)
7806#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U)
7811#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK)
7812
7813#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U)
7814#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U)
7819#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK)
7820
7821#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U)
7822#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U)
7827#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK)
7828
7829#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U)
7830#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U)
7835#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK)
7836
7837#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U)
7838#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U)
7843#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK)
7844
7845#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U)
7846#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U)
7851#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK)
7852
7853#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U)
7854#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U)
7859#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK)
7865#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
7866#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
7871#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
7872
7873#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
7874#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
7879#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
7880
7881#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
7882#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
7887#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
7888
7889#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
7890#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
7895#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
7896
7897#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
7898#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
7903#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
7904
7905#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
7906#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
7911#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
7912
7913#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
7914#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
7919#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
7920
7921#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
7922#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
7927#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
7928
7929#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
7930#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
7935#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
7936
7937#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
7938#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
7943#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
7944
7945#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
7946#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
7951#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
7952
7953#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
7954#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
7959#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
7960
7961#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
7962#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
7967#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
7968
7969#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
7970#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
7975#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
7976
7977#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
7978#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
7983#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
7984
7985#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
7986#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
7991#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
7997#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
7998#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8003#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8004
8005#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8006#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8011#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8012
8013#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8014#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8019#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8020
8021#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8022#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8027#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8028
8029#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8030#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8035#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8036
8037#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8038#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8043#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8044
8045#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8046#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8051#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8052
8053#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8054#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8059#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8060
8061#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8062#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8067#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8068
8069#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8070#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8075#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8076
8077#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8078#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8083#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8084
8085#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8086#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8091#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8092
8093#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8094#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8099#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8100
8101#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8102#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8107#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8108
8109#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8110#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8115#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8116
8117#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8118#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8123#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8129#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
8130#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8135#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8136
8137#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8138#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8143#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8144
8145#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8146#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8151#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8152
8153#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8154#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8159#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8160
8161#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8162#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8167#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8168
8169#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8170#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8175#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8176
8177#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8178#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8183#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8184
8185#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8186#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8191#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8192
8193#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8194#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8199#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8200
8201#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8202#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8207#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8208
8209#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8210#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8215#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8216
8217#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8218#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8223#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8224
8225#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8226#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8231#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8232
8233#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8234#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8239#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8240
8241#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8242#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8247#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8248
8249#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8250#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8255#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8261#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
8262#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8267#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8268
8269#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8270#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8275#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8276
8277#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8278#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8283#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8284
8285#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8286#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8291#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8292
8293#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8294#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8299#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8300
8301#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8302#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8307#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8308
8309#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8310#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8315#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8316
8317#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8318#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8323#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8324
8325#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8326#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8331#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8332
8333#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8334#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8339#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8340
8341#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8342#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8347#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8348
8349#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8350#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8355#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8356
8357#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8358#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8363#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8364
8365#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8366#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8371#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8372
8373#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8374#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8379#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8380
8381#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8382#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8387#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8393#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8394#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8399#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8400
8401#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8402#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8407#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8408
8409#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8410#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8415#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8416
8417#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8418#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8423#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8424
8425#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8426#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8431#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8432
8433#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8434#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8439#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8440
8441#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8442#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8447#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8448
8449#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8450#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8455#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8456
8457#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8458#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8463#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8464
8465#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8466#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8471#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8472
8473#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8474#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8479#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8480
8481#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8482#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8487#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8488
8489#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8490#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8495#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8496
8497#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8498#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8503#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8504
8505#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8506#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8511#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8512
8513#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8514#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8519#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8525#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8526#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8531#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8532
8533#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8534#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8539#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8540
8541#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8542#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8547#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8548
8549#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8550#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8555#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8556
8557#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8558#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8563#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8564
8565#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8566#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8571#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8572
8573#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8574#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8579#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8580
8581#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8582#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8587#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8588
8589#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8590#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8595#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8596
8597#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8598#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8603#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8604
8605#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8606#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8611#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8612
8613#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8614#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8619#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8620
8621#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8622#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8627#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8628
8629#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8630#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8635#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8636
8637#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8638#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8643#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8644
8645#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8646#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8651#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8657#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8658#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8663#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8664
8665#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8666#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8671#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8672
8673#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8674#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8679#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8680
8681#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8682#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8687#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8688
8689#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8690#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8695#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8696
8697#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8698#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8703#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8704
8705#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8706#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8711#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8712
8713#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8714#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8719#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8720
8721#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8722#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8727#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8728
8729#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8730#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8735#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8736
8737#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8738#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8743#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8744
8745#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8746#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8751#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8752
8753#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8754#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8759#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8760
8761#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8762#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8767#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8768
8769#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8770#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8775#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8776
8777#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8778#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8783#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8789#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8790#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8795#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8796
8797#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8798#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8803#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8804
8805#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8806#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8811#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8812
8813#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8814#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8819#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8820
8821#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8822#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8827#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8828
8829#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8830#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8835#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8836
8837#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8838#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8843#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8844
8845#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8846#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8851#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8852
8853#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8854#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8859#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8860
8861#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8862#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8867#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8868
8869#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8870#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8875#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8876
8877#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8878#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8883#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8884
8885#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8886#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8891#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8892
8893#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8894#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8899#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8900
8901#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8902#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8907#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8908
8909#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8910#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8915#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8921#define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK (0xFU)
8922#define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT (0U)
8925#define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK)
8926
8927#define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
8928#define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT (4U)
8931#define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK)
8932
8933#define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
8934#define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
8937#define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK)
8938
8939#define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
8940#define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
8943#define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK)
8949#define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK (0xFU)
8950#define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT (0U)
8953#define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK)
8954
8955#define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
8956#define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT (4U)
8959#define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK)
8960
8961#define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
8962#define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
8965#define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK)
8966
8967#define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
8968#define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
8971#define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK)
8977#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK (0x7U)
8978#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT (0U)
8981#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK)
8982
8983#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK (0x38U)
8984#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT (3U)
8987#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK)
8988
8989#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK (0x40U)
8990#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT (6U)
8993#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK)
8999#define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK (0x3U)
9000#define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT (0U)
9003#define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK)
9004
9005#define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK (0x4U)
9006#define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT (2U)
9009#define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK) /* end of group ANADIG_PMU_Register_Masks */
9016
9017
9018/* ANADIG_PMU - Peripheral instance base addresses */
9020#define ANADIG_PMU_BASE (0x40C84000u)
9022#define ANADIG_PMU ((ANADIG_PMU_Type *)ANADIG_PMU_BASE)
9024#define ANADIG_PMU_BASE_ADDRS { ANADIG_PMU_BASE }
9026#define ANADIG_PMU_BASE_PTRS { ANADIG_PMU }
9027 /* end of group ANADIG_PMU_Peripheral_Access_Layer */
9031
9032
9033/* ----------------------------------------------------------------------------
9034 -- ANADIG_TEMPSENSOR Peripheral Access Layer
9035 ---------------------------------------------------------------------------- */
9036
9043typedef struct {
9044 uint8_t RESERVED_0[1024];
9045 __IO uint32_t TEMPSENSOR;
9046 uint8_t RESERVED_1[44];
9047 __I uint32_t TEMPSNS_OTP_TRIM_VALUE;
9049
9050/* ----------------------------------------------------------------------------
9051 -- ANADIG_TEMPSENSOR Register Masks
9052 ---------------------------------------------------------------------------- */
9053
9062#define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK (0x8000U)
9063#define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT (15U)
9066#define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK)
9067
9068#define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK (0x10000U)
9069#define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT (16U)
9072#define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK)
9078#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK (0x3FFC00U)
9079#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT (10U)
9082#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK) /* end of group ANADIG_TEMPSENSOR_Register_Masks */
9089
9090
9091/* ANADIG_TEMPSENSOR - Peripheral instance base addresses */
9093#define ANADIG_TEMPSENSOR_BASE (0x40C84000u)
9095#define ANADIG_TEMPSENSOR ((ANADIG_TEMPSENSOR_Type *)ANADIG_TEMPSENSOR_BASE)
9097#define ANADIG_TEMPSENSOR_BASE_ADDRS { ANADIG_TEMPSENSOR_BASE }
9099#define ANADIG_TEMPSENSOR_BASE_PTRS { ANADIG_TEMPSENSOR }
9100 /* end of group ANADIG_TEMPSENSOR_Peripheral_Access_Layer */
9104
9105
9106/* ----------------------------------------------------------------------------
9107 -- AOI Peripheral Access Layer
9108 ---------------------------------------------------------------------------- */
9109
9116typedef struct {
9117 struct { /* offset: 0x0, array step: 0x4 */
9118 __IO uint16_t BFCRT01;
9119 __IO uint16_t BFCRT23;
9120 } BFCRT[4];
9121} AOI_Type;
9122
9123/* ----------------------------------------------------------------------------
9124 -- AOI Register Masks
9125 ---------------------------------------------------------------------------- */
9126
9135#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
9136#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
9143#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
9144
9145#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
9146#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
9153#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
9154
9155#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
9156#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
9163#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
9164
9165#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
9166#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
9173#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
9174
9175#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
9176#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
9183#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
9184
9185#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
9186#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
9193#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
9194
9195#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
9196#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
9203#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
9204
9205#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
9206#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
9213#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
9216/* The count of AOI_BFCRT01 */
9217#define AOI_BFCRT01_COUNT (4U)
9218
9222#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
9223#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
9230#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
9231
9232#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
9233#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
9240#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
9241
9242#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
9243#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
9250#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
9251
9252#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
9253#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
9260#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
9261
9262#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
9263#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
9270#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
9271
9272#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
9273#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
9280#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
9281
9282#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
9283#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
9290#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
9291
9292#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
9293#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
9300#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
9303/* The count of AOI_BFCRT23 */
9304#define AOI_BFCRT23_COUNT (4U)
9305
9306 /* end of group AOI_Register_Masks */
9310
9311
9312/* AOI - Peripheral instance base addresses */
9314#define AOI1_BASE (0x400B8000u)
9316#define AOI1 ((AOI_Type *)AOI1_BASE)
9318#define AOI2_BASE (0x400BC000u)
9320#define AOI2 ((AOI_Type *)AOI2_BASE)
9322#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }
9324#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }
9325 /* end of group AOI_Peripheral_Access_Layer */
9329
9330
9331/* ----------------------------------------------------------------------------
9332 -- ASRC Peripheral Access Layer
9333 ---------------------------------------------------------------------------- */
9334
9341typedef struct {
9342 __IO uint32_t ASRCTR;
9343 __IO uint32_t ASRIER;
9344 uint8_t RESERVED_0[4];
9345 __IO uint32_t ASRCNCR;
9346 __IO uint32_t ASRCFG;
9347 __IO uint32_t ASRCSR;
9348 __IO uint32_t ASRCDR1;
9349 __IO uint32_t ASRCDR2;
9350 __I uint32_t ASRSTR;
9351 uint8_t RESERVED_1[28];
9352 __IO uint32_t ASRPM[5];
9353 __IO uint32_t ASRTFR1;
9354 uint8_t RESERVED_2[4];
9355 __IO uint32_t ASRCCR;
9356 __O uint32_t ASRDIA;
9357 __I uint32_t ASRDOA;
9358 __O uint32_t ASRDIB;
9359 __I uint32_t ASRDOB;
9360 __O uint32_t ASRDIC;
9361 __I uint32_t ASRDOC;
9362 uint8_t RESERVED_3[8];
9363 __IO uint32_t ASRIDRHA;
9364 __IO uint32_t ASRIDRLA;
9365 __IO uint32_t ASRIDRHB;
9366 __IO uint32_t ASRIDRLB;
9367 __IO uint32_t ASRIDRHC;
9368 __IO uint32_t ASRIDRLC;
9369 __IO uint32_t ASR76K;
9370 __IO uint32_t ASR56K;
9371 __IO uint32_t ASRMCRA;
9372 __I uint32_t ASRFSTA;
9373 __IO uint32_t ASRMCRB;
9374 __I uint32_t ASRFSTB;
9375 __IO uint32_t ASRMCRC;
9376 __I uint32_t ASRFSTC;
9377 uint8_t RESERVED_4[8];
9378 __IO uint32_t ASRMCR1[3];
9379} ASRC_Type;
9380
9381/* ----------------------------------------------------------------------------
9382 -- ASRC Register Masks
9383 ---------------------------------------------------------------------------- */
9384
9393#define ASRC_ASRCTR_ASRCEN_MASK (0x1U)
9394#define ASRC_ASRCTR_ASRCEN_SHIFT (0U)
9399#define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
9400
9401#define ASRC_ASRCTR_ASREA_MASK (0x2U)
9402#define ASRC_ASRCTR_ASREA_SHIFT (1U)
9407#define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
9408
9409#define ASRC_ASRCTR_ASREB_MASK (0x4U)
9410#define ASRC_ASRCTR_ASREB_SHIFT (2U)
9415#define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
9416
9417#define ASRC_ASRCTR_ASREC_MASK (0x8U)
9418#define ASRC_ASRCTR_ASREC_SHIFT (3U)
9423#define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
9424
9425#define ASRC_ASRCTR_SRST_MASK (0x10U)
9426#define ASRC_ASRCTR_SRST_SHIFT (4U)
9431#define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
9432
9433#define ASRC_ASRCTR_IDRA_MASK (0x2000U)
9434#define ASRC_ASRCTR_IDRA_SHIFT (13U)
9439#define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
9440
9441#define ASRC_ASRCTR_USRA_MASK (0x4000U)
9442#define ASRC_ASRCTR_USRA_SHIFT (14U)
9447#define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
9448
9449#define ASRC_ASRCTR_IDRB_MASK (0x8000U)
9450#define ASRC_ASRCTR_IDRB_SHIFT (15U)
9455#define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
9456
9457#define ASRC_ASRCTR_USRB_MASK (0x10000U)
9458#define ASRC_ASRCTR_USRB_SHIFT (16U)
9463#define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
9464
9465#define ASRC_ASRCTR_IDRC_MASK (0x20000U)
9466#define ASRC_ASRCTR_IDRC_SHIFT (17U)
9471#define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
9472
9473#define ASRC_ASRCTR_USRC_MASK (0x40000U)
9474#define ASRC_ASRCTR_USRC_SHIFT (18U)
9479#define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
9480
9481#define ASRC_ASRCTR_ATSA_MASK (0x100000U)
9482#define ASRC_ASRCTR_ATSA_SHIFT (20U)
9487#define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
9488
9489#define ASRC_ASRCTR_ATSB_MASK (0x200000U)
9490#define ASRC_ASRCTR_ATSB_SHIFT (21U)
9495#define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
9496
9497#define ASRC_ASRCTR_ATSC_MASK (0x400000U)
9498#define ASRC_ASRCTR_ATSC_SHIFT (22U)
9503#define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
9509#define ASRC_ASRIER_ADIEA_MASK (0x1U)
9510#define ASRC_ASRIER_ADIEA_SHIFT (0U)
9515#define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
9516
9517#define ASRC_ASRIER_ADIEB_MASK (0x2U)
9518#define ASRC_ASRIER_ADIEB_SHIFT (1U)
9523#define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
9524
9525#define ASRC_ASRIER_ADIEC_MASK (0x4U)
9526#define ASRC_ASRIER_ADIEC_SHIFT (2U)
9531#define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
9532
9533#define ASRC_ASRIER_ADOEA_MASK (0x8U)
9534#define ASRC_ASRIER_ADOEA_SHIFT (3U)
9539#define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
9540
9541#define ASRC_ASRIER_ADOEB_MASK (0x10U)
9542#define ASRC_ASRIER_ADOEB_SHIFT (4U)
9547#define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
9548
9549#define ASRC_ASRIER_ADOEC_MASK (0x20U)
9550#define ASRC_ASRIER_ADOEC_SHIFT (5U)
9555#define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
9556
9557#define ASRC_ASRIER_AOLIE_MASK (0x40U)
9558#define ASRC_ASRIER_AOLIE_SHIFT (6U)
9563#define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
9564
9565#define ASRC_ASRIER_AFPWE_MASK (0x80U)
9566#define ASRC_ASRIER_AFPWE_SHIFT (7U)
9571#define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
9577#define ASRC_ASRCNCR_ANCA_MASK (0xFU)
9578#define ASRC_ASRCNCR_ANCA_SHIFT (0U)
9593#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
9594
9595#define ASRC_ASRCNCR_ANCB_MASK (0xF0U)
9596#define ASRC_ASRCNCR_ANCB_SHIFT (4U)
9611#define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
9612
9613#define ASRC_ASRCNCR_ANCC_MASK (0xF00U)
9614#define ASRC_ASRCNCR_ANCC_SHIFT (8U)
9629#define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
9635#define ASRC_ASRCFG_PREMODA_MASK (0xC0U)
9636#define ASRC_ASRCFG_PREMODA_SHIFT (6U)
9643#define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
9644
9645#define ASRC_ASRCFG_POSTMODA_MASK (0x300U)
9646#define ASRC_ASRCFG_POSTMODA_SHIFT (8U)
9653#define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
9654
9655#define ASRC_ASRCFG_PREMODB_MASK (0xC00U)
9656#define ASRC_ASRCFG_PREMODB_SHIFT (10U)
9663#define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
9664
9665#define ASRC_ASRCFG_POSTMODB_MASK (0x3000U)
9666#define ASRC_ASRCFG_POSTMODB_SHIFT (12U)
9673#define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
9674
9675#define ASRC_ASRCFG_PREMODC_MASK (0xC000U)
9676#define ASRC_ASRCFG_PREMODC_SHIFT (14U)
9683#define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
9684
9685#define ASRC_ASRCFG_POSTMODC_MASK (0x30000U)
9686#define ASRC_ASRCFG_POSTMODC_SHIFT (16U)
9693#define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
9694
9695#define ASRC_ASRCFG_NDPRA_MASK (0x40000U)
9696#define ASRC_ASRCFG_NDPRA_SHIFT (18U)
9701#define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
9702
9703#define ASRC_ASRCFG_NDPRB_MASK (0x80000U)
9704#define ASRC_ASRCFG_NDPRB_SHIFT (19U)
9709#define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
9710
9711#define ASRC_ASRCFG_NDPRC_MASK (0x100000U)
9712#define ASRC_ASRCFG_NDPRC_SHIFT (20U)
9717#define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
9718
9719#define ASRC_ASRCFG_INIRQA_MASK (0x200000U)
9720#define ASRC_ASRCFG_INIRQA_SHIFT (21U)
9725#define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
9726
9727#define ASRC_ASRCFG_INIRQB_MASK (0x400000U)
9728#define ASRC_ASRCFG_INIRQB_SHIFT (22U)
9733#define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
9734
9735#define ASRC_ASRCFG_INIRQC_MASK (0x800000U)
9736#define ASRC_ASRCFG_INIRQC_SHIFT (23U)
9741#define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
9747#define ASRC_ASRCSR_AICSA_MASK (0xFU)
9748#define ASRC_ASRCSR_AICSA_SHIFT (0U)
9767#define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
9768
9769#define ASRC_ASRCSR_AICSB_MASK (0xF0U)
9770#define ASRC_ASRCSR_AICSB_SHIFT (4U)
9789#define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
9790
9791#define ASRC_ASRCSR_AICSC_MASK (0xF00U)
9792#define ASRC_ASRCSR_AICSC_SHIFT (8U)
9811#define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
9812
9813#define ASRC_ASRCSR_AOCSA_MASK (0xF000U)
9814#define ASRC_ASRCSR_AOCSA_SHIFT (12U)
9833#define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
9834
9835#define ASRC_ASRCSR_AOCSB_MASK (0xF0000U)
9836#define ASRC_ASRCSR_AOCSB_SHIFT (16U)
9855#define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
9856
9857#define ASRC_ASRCSR_AOCSC_MASK (0xF00000U)
9858#define ASRC_ASRCSR_AOCSC_SHIFT (20U)
9877#define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
9883#define ASRC_ASRCDR1_AICPA_MASK (0x7U)
9884#define ASRC_ASRCDR1_AICPA_SHIFT (0U)
9887#define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
9888
9889#define ASRC_ASRCDR1_AICDA_MASK (0x38U)
9890#define ASRC_ASRCDR1_AICDA_SHIFT (3U)
9893#define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
9894
9895#define ASRC_ASRCDR1_AICPB_MASK (0x1C0U)
9896#define ASRC_ASRCDR1_AICPB_SHIFT (6U)
9899#define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
9900
9901#define ASRC_ASRCDR1_AICDB_MASK (0xE00U)
9902#define ASRC_ASRCDR1_AICDB_SHIFT (9U)
9905#define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
9906
9907#define ASRC_ASRCDR1_AOCPA_MASK (0x7000U)
9908#define ASRC_ASRCDR1_AOCPA_SHIFT (12U)
9911#define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
9912
9913#define ASRC_ASRCDR1_AOCDA_MASK (0x38000U)
9914#define ASRC_ASRCDR1_AOCDA_SHIFT (15U)
9917#define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
9918
9919#define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U)
9920#define ASRC_ASRCDR1_AOCPB_SHIFT (18U)
9923#define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
9924
9925#define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U)
9926#define ASRC_ASRCDR1_AOCDB_SHIFT (21U)
9929#define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
9935#define ASRC_ASRCDR2_AICPC_MASK (0x7U)
9936#define ASRC_ASRCDR2_AICPC_SHIFT (0U)
9939#define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
9940
9941#define ASRC_ASRCDR2_AICDC_MASK (0x38U)
9942#define ASRC_ASRCDR2_AICDC_SHIFT (3U)
9945#define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
9946
9947#define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U)
9948#define ASRC_ASRCDR2_AOCPC_SHIFT (6U)
9951#define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
9952
9953#define ASRC_ASRCDR2_AOCDC_MASK (0xE00U)
9954#define ASRC_ASRCDR2_AOCDC_SHIFT (9U)
9957#define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
9963#define ASRC_ASRSTR_AIDEA_MASK (0x1U)
9964#define ASRC_ASRSTR_AIDEA_SHIFT (0U)
9969#define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
9970
9971#define ASRC_ASRSTR_AIDEB_MASK (0x2U)
9972#define ASRC_ASRSTR_AIDEB_SHIFT (1U)
9977#define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
9978
9979#define ASRC_ASRSTR_AIDEC_MASK (0x4U)
9980#define ASRC_ASRSTR_AIDEC_SHIFT (2U)
9985#define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
9986
9987#define ASRC_ASRSTR_AODFA_MASK (0x8U)
9988#define ASRC_ASRSTR_AODFA_SHIFT (3U)
9993#define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
9994
9995#define ASRC_ASRSTR_AODFB_MASK (0x10U)
9996#define ASRC_ASRSTR_AODFB_SHIFT (4U)
10001#define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
10002
10003#define ASRC_ASRSTR_AODFC_MASK (0x20U)
10004#define ASRC_ASRSTR_AODFC_SHIFT (5U)
10009#define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
10010
10011#define ASRC_ASRSTR_AOLE_MASK (0x40U)
10012#define ASRC_ASRSTR_AOLE_SHIFT (6U)
10017#define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
10018
10019#define ASRC_ASRSTR_FPWT_MASK (0x80U)
10020#define ASRC_ASRSTR_FPWT_SHIFT (7U)
10025#define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
10026
10027#define ASRC_ASRSTR_AIDUA_MASK (0x100U)
10028#define ASRC_ASRSTR_AIDUA_SHIFT (8U)
10033#define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
10034
10035#define ASRC_ASRSTR_AIDUB_MASK (0x200U)
10036#define ASRC_ASRSTR_AIDUB_SHIFT (9U)
10041#define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
10042
10043#define ASRC_ASRSTR_AIDUC_MASK (0x400U)
10044#define ASRC_ASRSTR_AIDUC_SHIFT (10U)
10049#define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
10050
10051#define ASRC_ASRSTR_AODOA_MASK (0x800U)
10052#define ASRC_ASRSTR_AODOA_SHIFT (11U)
10057#define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
10058
10059#define ASRC_ASRSTR_AODOB_MASK (0x1000U)
10060#define ASRC_ASRSTR_AODOB_SHIFT (12U)
10065#define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
10066
10067#define ASRC_ASRSTR_AODOC_MASK (0x2000U)
10068#define ASRC_ASRSTR_AODOC_SHIFT (13U)
10073#define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
10074
10075#define ASRC_ASRSTR_AIOLA_MASK (0x4000U)
10076#define ASRC_ASRSTR_AIOLA_SHIFT (14U)
10081#define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
10082
10083#define ASRC_ASRSTR_AIOLB_MASK (0x8000U)
10084#define ASRC_ASRSTR_AIOLB_SHIFT (15U)
10089#define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
10090
10091#define ASRC_ASRSTR_AIOLC_MASK (0x10000U)
10092#define ASRC_ASRSTR_AIOLC_SHIFT (16U)
10097#define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
10098
10099#define ASRC_ASRSTR_AOOLA_MASK (0x20000U)
10100#define ASRC_ASRSTR_AOOLA_SHIFT (17U)
10105#define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
10106
10107#define ASRC_ASRSTR_AOOLB_MASK (0x40000U)
10108#define ASRC_ASRSTR_AOOLB_SHIFT (18U)
10113#define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
10114
10115#define ASRC_ASRSTR_AOOLC_MASK (0x80000U)
10116#define ASRC_ASRSTR_AOOLC_SHIFT (19U)
10121#define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
10122
10123#define ASRC_ASRSTR_ATQOL_MASK (0x100000U)
10124#define ASRC_ASRSTR_ATQOL_SHIFT (20U)
10129#define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
10130
10131#define ASRC_ASRSTR_DSLCNT_MASK (0x200000U)
10132#define ASRC_ASRSTR_DSLCNT_SHIFT (21U)
10137#define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
10143#define ASRC_ASRPM_PARAMETER_VALUE_MASK (0xFFFFFFU)
10144#define ASRC_ASRPM_PARAMETER_VALUE_SHIFT (0U)
10147#define ASRC_ASRPM_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
10150/* The count of ASRC_ASRPM */
10151#define ASRC_ASRPM_COUNT (5U)
10152
10156#define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U)
10157#define ASRC_ASRTFR1_TF_BASE_SHIFT (6U)
10160#define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
10161
10162#define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U)
10163#define ASRC_ASRTFR1_TF_FILL_SHIFT (13U)
10166#define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
10172#define ASRC_ASRCCR_ACIA_MASK (0xFU)
10173#define ASRC_ASRCCR_ACIA_SHIFT (0U)
10176#define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
10177
10178#define ASRC_ASRCCR_ACIB_MASK (0xF0U)
10179#define ASRC_ASRCCR_ACIB_SHIFT (4U)
10182#define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
10183
10184#define ASRC_ASRCCR_ACIC_MASK (0xF00U)
10185#define ASRC_ASRCCR_ACIC_SHIFT (8U)
10188#define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
10189
10190#define ASRC_ASRCCR_ACOA_MASK (0xF000U)
10191#define ASRC_ASRCCR_ACOA_SHIFT (12U)
10194#define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
10195
10196#define ASRC_ASRCCR_ACOB_MASK (0xF0000U)
10197#define ASRC_ASRCCR_ACOB_SHIFT (16U)
10200#define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
10201
10202#define ASRC_ASRCCR_ACOC_MASK (0xF00000U)
10203#define ASRC_ASRCCR_ACOC_SHIFT (20U)
10206#define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
10212#define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU)
10213#define ASRC_ASRDIA_DATA_SHIFT (0U)
10216#define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
10222#define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU)
10223#define ASRC_ASRDOA_DATA_SHIFT (0U)
10226#define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
10232#define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU)
10233#define ASRC_ASRDIB_DATA_SHIFT (0U)
10236#define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
10242#define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU)
10243#define ASRC_ASRDOB_DATA_SHIFT (0U)
10246#define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
10252#define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU)
10253#define ASRC_ASRDIC_DATA_SHIFT (0U)
10256#define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
10262#define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU)
10263#define ASRC_ASRDOC_DATA_SHIFT (0U)
10266#define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
10272#define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU)
10273#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U)
10276#define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
10282#define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU)
10283#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U)
10286#define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
10292#define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU)
10293#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U)
10296#define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
10302#define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU)
10303#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U)
10306#define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
10312#define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU)
10313#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U)
10316#define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
10322#define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU)
10323#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U)
10326#define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
10332#define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU)
10333#define ASRC_ASR76K_ASR76K_SHIFT (0U)
10336#define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
10342#define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU)
10343#define ASRC_ASR56K_ASR56K_SHIFT (0U)
10346#define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
10352#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU)
10353#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U)
10356#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
10357
10358#define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U)
10359#define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U)
10364#define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
10365
10366#define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U)
10367#define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U)
10372#define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
10373
10374#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U)
10375#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U)
10378#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
10379
10380#define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U)
10381#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U)
10386#define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
10387
10388#define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U)
10389#define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U)
10394#define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
10395
10396#define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U)
10397#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U)
10402#define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
10403
10404#define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U)
10405#define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U)
10410#define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
10416#define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU)
10417#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U)
10420#define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
10421
10422#define ASRC_ASRFSTA_IAEA_MASK (0x800U)
10423#define ASRC_ASRFSTA_IAEA_SHIFT (11U)
10428#define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
10429
10430#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U)
10431#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U)
10434#define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
10435
10436#define ASRC_ASRFSTA_OAFA_MASK (0x800000U)
10437#define ASRC_ASRFSTA_OAFA_SHIFT (23U)
10442#define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
10448#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU)
10449#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U)
10452#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
10453
10454#define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U)
10455#define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U)
10460#define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
10461
10462#define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U)
10463#define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U)
10468#define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
10469
10470#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U)
10471#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U)
10474#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
10475
10476#define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U)
10477#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U)
10482#define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
10483
10484#define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U)
10485#define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U)
10490#define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
10491
10492#define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U)
10493#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U)
10498#define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
10499
10500#define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U)
10501#define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U)
10506#define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
10512#define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU)
10513#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U)
10516#define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
10517
10518#define ASRC_ASRFSTB_IAEB_MASK (0x800U)
10519#define ASRC_ASRFSTB_IAEB_SHIFT (11U)
10524#define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
10525
10526#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U)
10527#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U)
10530#define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
10531
10532#define ASRC_ASRFSTB_OAFB_MASK (0x800000U)
10533#define ASRC_ASRFSTB_OAFB_SHIFT (23U)
10538#define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
10544#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU)
10545#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U)
10548#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
10549
10550#define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U)
10551#define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U)
10556#define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
10557
10558#define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U)
10559#define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U)
10564#define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
10565
10566#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U)
10567#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U)
10570#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
10571
10572#define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U)
10573#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U)
10578#define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
10579
10580#define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U)
10581#define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U)
10586#define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
10587
10588#define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U)
10589#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U)
10594#define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
10595
10596#define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U)
10597#define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U)
10602#define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
10608#define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU)
10609#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U)
10612#define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
10613
10614#define ASRC_ASRFSTC_IAEC_MASK (0x800U)
10615#define ASRC_ASRFSTC_IAEC_SHIFT (11U)
10620#define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
10621
10622#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U)
10623#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U)
10626#define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
10627
10628#define ASRC_ASRFSTC_OAFC_MASK (0x800000U)
10629#define ASRC_ASRFSTC_OAFC_SHIFT (23U)
10634#define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
10640#define ASRC_ASRMCR1_OW16_MASK (0x1U)
10641#define ASRC_ASRMCR1_OW16_SHIFT (0U)
10646#define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
10647
10648#define ASRC_ASRMCR1_OSGN_MASK (0x2U)
10649#define ASRC_ASRMCR1_OSGN_SHIFT (1U)
10654#define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
10655
10656#define ASRC_ASRMCR1_OMSB_MASK (0x4U)
10657#define ASRC_ASRMCR1_OMSB_SHIFT (2U)
10662#define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
10663
10664#define ASRC_ASRMCR1_IMSB_MASK (0x100U)
10665#define ASRC_ASRMCR1_IMSB_SHIFT (8U)
10670#define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
10671
10672#define ASRC_ASRMCR1_IWD_MASK (0x600U)
10673#define ASRC_ASRMCR1_IWD_SHIFT (9U)
10680#define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
10683/* The count of ASRC_ASRMCR1 */
10684#define ASRC_ASRMCR1_COUNT (3U)
10685
10686 /* end of group ASRC_Register_Masks */
10690
10691
10692/* ASRC - Peripheral instance base addresses */
10694#define ASRC_BASE (0x40414000u)
10696#define ASRC ((ASRC_Type *)ASRC_BASE)
10698#define ASRC_BASE_ADDRS { ASRC_BASE }
10700#define ASRC_BASE_PTRS { ASRC }
10702#define ASRC_IRQS { ASRC_IRQn }
10703 /* end of group ASRC_Peripheral_Access_Layer */
10707
10708
10709/* ----------------------------------------------------------------------------
10710 -- AUDIO_PLL Peripheral Access Layer
10711 ---------------------------------------------------------------------------- */
10712
10719typedef struct {
10720 struct { /* offset: 0x0 */
10721 __IO uint32_t RW;
10722 __IO uint32_t SET;
10723 __IO uint32_t CLR;
10724 __IO uint32_t TOG;
10725 } CTRL0;
10726 struct { /* offset: 0x10 */
10727 __IO uint32_t RW;
10728 __IO uint32_t SET;
10729 __IO uint32_t CLR;
10730 __IO uint32_t TOG;
10731 } SPREAD_SPECTRUM;
10732 struct { /* offset: 0x20 */
10733 __IO uint32_t RW;
10734 __IO uint32_t SET;
10735 __IO uint32_t CLR;
10736 __IO uint32_t TOG;
10737 } NUMERATOR;
10738 struct { /* offset: 0x30 */
10739 __IO uint32_t RW;
10740 __IO uint32_t SET;
10741 __IO uint32_t CLR;
10742 __IO uint32_t TOG;
10743 } DENOMINATOR;
10745
10746/* ----------------------------------------------------------------------------
10747 -- AUDIO_PLL Register Masks
10748 ---------------------------------------------------------------------------- */
10749
10758#define AUDIO_PLL_CTRL0_DIV_SELECT_MASK (0x7FU)
10759#define AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT (0U)
10762#define AUDIO_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_DIV_SELECT_MASK)
10763
10764#define AUDIO_PLL_CTRL0_ENABLE_ALT_MASK (0x100U)
10765#define AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT (8U)
10770#define AUDIO_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_ALT_MASK)
10771
10772#define AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U)
10773#define AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U)
10778#define AUDIO_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK)
10779
10780#define AUDIO_PLL_CTRL0_POWERUP_MASK (0x4000U)
10781#define AUDIO_PLL_CTRL0_POWERUP_SHIFT (14U)
10786#define AUDIO_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POWERUP_SHIFT)) & AUDIO_PLL_CTRL0_POWERUP_MASK)
10787
10788#define AUDIO_PLL_CTRL0_ENABLE_MASK (0x8000U)
10789#define AUDIO_PLL_CTRL0_ENABLE_SHIFT (15U)
10794#define AUDIO_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_MASK)
10795
10796#define AUDIO_PLL_CTRL0_BYPASS_MASK (0x10000U)
10797#define AUDIO_PLL_CTRL0_BYPASS_SHIFT (16U)
10802#define AUDIO_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BYPASS_SHIFT)) & AUDIO_PLL_CTRL0_BYPASS_MASK)
10803
10804#define AUDIO_PLL_CTRL0_DITHER_EN_MASK (0x20000U)
10805#define AUDIO_PLL_CTRL0_DITHER_EN_SHIFT (17U)
10810#define AUDIO_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DITHER_EN_SHIFT)) & AUDIO_PLL_CTRL0_DITHER_EN_MASK)
10811
10812#define AUDIO_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U)
10813#define AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT (19U)
10816#define AUDIO_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_TRIM_MASK)
10817
10818#define AUDIO_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U)
10819#define AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT (22U)
10822#define AUDIO_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & AUDIO_PLL_CTRL0_PLL_REG_EN_MASK)
10823
10824#define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U)
10825#define AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U)
10834#define AUDIO_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
10835
10836#define AUDIO_PLL_CTRL0_BIAS_SELECT_MASK (0x20000000U)
10837#define AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT (29U)
10842#define AUDIO_PLL_CTRL0_BIAS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_SELECT_MASK)
10848#define AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU)
10849#define AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U)
10852#define AUDIO_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK)
10853
10854#define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U)
10855#define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U)
10858#define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
10859
10860#define AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U)
10861#define AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U)
10864#define AUDIO_PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK)
10870#define AUDIO_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
10871#define AUDIO_PLL_NUMERATOR_NUM_SHIFT (0U)
10874#define AUDIO_PLL_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_NUMERATOR_NUM_SHIFT)) & AUDIO_PLL_NUMERATOR_NUM_MASK)
10880#define AUDIO_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
10881#define AUDIO_PLL_DENOMINATOR_DENOM_SHIFT (0U)
10884#define AUDIO_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_DENOMINATOR_DENOM_SHIFT)) & AUDIO_PLL_DENOMINATOR_DENOM_MASK) /* end of group AUDIO_PLL_Register_Masks */
10891
10892
10893/* AUDIO_PLL - Peripheral instance base addresses */
10895#define AUDIO_PLL_BASE (0u)
10897#define AUDIO_PLL ((AUDIO_PLL_Type *)AUDIO_PLL_BASE)
10899#define AUDIO_PLL_BASE_ADDRS { AUDIO_PLL_BASE }
10901#define AUDIO_PLL_BASE_PTRS { AUDIO_PLL }
10902 /* end of group AUDIO_PLL_Peripheral_Access_Layer */
10906
10907
10908/* ----------------------------------------------------------------------------
10909 -- CAAM Peripheral Access Layer
10910 ---------------------------------------------------------------------------- */
10911
10918typedef struct {
10919 uint8_t RESERVED_0[4];
10920 __IO uint32_t MCFGR;
10921 __IO uint32_t PAGE0_SDID;
10922 __IO uint32_t SCFGR;
10923 struct { /* offset: 0x10, array step: 0x8 */
10924 __IO uint32_t JRDID_MS;
10925 __IO uint32_t JRDID_LS;
10926 } JRADID[4];
10927 uint8_t RESERVED_1[40];
10928 __IO uint32_t DEBUGCTL;
10929 __IO uint32_t JRSTARTR;
10930 __IO uint32_t RTIC_OWN;
10931 struct { /* offset: 0x64, array step: 0x8 */
10932 __IO uint32_t RTIC_DID;
10933 uint8_t RESERVED_0[4];
10934 } RTICADID[4];
10935 uint8_t RESERVED_2[16];
10936 __IO uint32_t DECORSR;
10937 uint8_t RESERVED_3[4];
10938 __IO uint32_t DECORR;
10939 struct { /* offset: 0xA0, array step: 0x8 */
10940 __IO uint32_t DECODID_MS;
10941 __IO uint32_t DECODID_LS;
10942 } DECONDID[1];
10943 uint8_t RESERVED_4[120];
10944 __IO uint32_t DAR;
10945 __O uint32_t DRR;
10946 uint8_t RESERVED_5[92];
10947 struct { /* offset: 0x184, array step: 0x8 */
10948 __IO uint32_t JRSMVBAR;
10949 uint8_t RESERVED_0[4];
10950 } JRNSMVBAR[4];
10951 uint8_t RESERVED_6[124];
10952 __IO uint32_t PBSL;
10953 uint8_t RESERVED_7[28];
10954 struct { /* offset: 0x240, array step: 0x10 */
10959 } AID_CNTS[1];
10960 __I uint32_t DMA0_AID_ENB;
10961 uint8_t RESERVED_8[12];
10962 __IO uint64_t DMA0_ARD_TC;
10963 uint8_t RESERVED_9[4];
10964 __IO uint32_t DMA0_ARD_LAT;
10965 __IO uint64_t DMA0_AWR_TC;
10966 uint8_t RESERVED_10[4];
10967 __IO uint32_t DMA0_AWR_LAT;
10968 uint8_t RESERVED_11[128];
10969 __IO uint8_t MPPKR[64];
10970 uint8_t RESERVED_12[64];
10971 __IO uint8_t MPMR[32];
10972 uint8_t RESERVED_13[32];
10973 __I uint8_t MPTESTR[32];
10974 uint8_t RESERVED_14[24];
10975 __I uint32_t MPECC;
10976 uint8_t RESERVED_15[4];
10977 __IO uint32_t JDKEKR[8];
10978 __IO uint32_t TDKEKR[8];
10979 __IO uint32_t TDSKR[8];
10980 uint8_t RESERVED_16[128];
10981 __IO uint64_t SKNR;
10982 uint8_t RESERVED_17[36];
10983 __I uint32_t DMA_STA;
10984 __I uint32_t DMA_X_AID_7_4_MAP;
10985 __I uint32_t DMA_X_AID_3_0_MAP;
10986 __I uint32_t DMA_X_AID_15_12_MAP;
10987 __I uint32_t DMA_X_AID_11_8_MAP;
10988 uint8_t RESERVED_18[4];
10989 __I uint32_t DMA_X_AID_15_0_EN;
10990 uint8_t RESERVED_19[8];
10991 __IO uint32_t DMA_X_ARTC_CTL;
10992 __IO uint32_t DMA_X_ARTC_LC;
10993 __IO uint32_t DMA_X_ARTC_SC;
10994 __IO uint32_t DMA_X_ARTC_LAT;
10995 __IO uint32_t DMA_X_AWTC_CTL;
10996 __IO uint32_t DMA_X_AWTC_LC;
10997 __IO uint32_t DMA_X_AWTC_SC;
10998 __IO uint32_t DMA_X_AWTC_LAT;
10999 uint8_t RESERVED_20[176];
11000 __IO uint32_t RTMCTL;
11001 __IO uint32_t RTSCMISC;
11002 __IO uint32_t RTPKRRNG;
11003 union { /* offset: 0x60C */
11004 __IO uint32_t RTPKRMAX;
11005 __I uint32_t RTPKRSQ;
11006 };
11007 __IO uint32_t RTSDCTL;
11008 union { /* offset: 0x614 */
11009 __IO uint32_t RTSBLIM;
11010 __I uint32_t RTTOTSAM;
11011 };
11012 __IO uint32_t RTFRQMIN;
11013 union { /* offset: 0x61C */
11014 struct { /* offset: 0x61C */
11015 __I uint32_t RTFRQCNT;
11016 __I uint32_t RTSCMC;
11017 __I uint32_t RTSCR1C;
11018 __I uint32_t RTSCR2C;
11019 __I uint32_t RTSCR3C;
11020 __I uint32_t RTSCR4C;
11021 __I uint32_t RTSCR5C;
11022 __I uint32_t RTSCR6PC;
11023 } COUNT;
11024 struct { /* offset: 0x61C */
11025 __IO uint32_t RTFRQMAX;
11026 __IO uint32_t RTSCML;
11027 __IO uint32_t RTSCR1L;
11028 __IO uint32_t RTSCR2L;
11029 __IO uint32_t RTSCR3L;
11030 __IO uint32_t RTSCR4L;
11031 __IO uint32_t RTSCR5L;
11032 __IO uint32_t RTSCR6PL;
11033 } LIMIT;
11034 };
11035 __I uint32_t RTSTATUS;
11036 __I uint32_t RTENT[16];
11037 __I uint32_t RTPKRCNT10;
11038 __I uint32_t RTPKRCNT32;
11039 __I uint32_t RTPKRCNT54;
11040 __I uint32_t RTPKRCNT76;
11041 __I uint32_t RTPKRCNT98;
11042 __I uint32_t RTPKRCNTBA;
11043 __I uint32_t RTPKRCNTDC;
11044 __I uint32_t RTPKRCNTFE;
11045 uint8_t RESERVED_21[32];
11046 __I uint32_t RDSTA;
11047 uint8_t RESERVED_22[12];
11048 __I uint32_t RDINT0;
11049 __I uint32_t RDINT1;
11050 uint8_t RESERVED_23[8];
11051 __IO uint32_t RDHCNTL;
11052 __I uint32_t RDHDIG;
11053 __O uint32_t RDHBUF;
11054 uint8_t RESERVED_24[788];
11055 struct { /* offset: 0xA00, array step: 0x10 */
11056 __I uint32_t PX_SDID_PG0;
11060 } PX_PG0[16];
11061 __IO uint32_t REIS;
11062 __IO uint32_t REIE;
11063 __I uint32_t REIF;
11064 __IO uint32_t REIH;
11065 uint8_t RESERVED_25[192];
11066 __IO uint32_t SMWPJRR[4];
11067 uint8_t RESERVED_26[4];
11068 __O uint32_t SMCR_PG0;
11069 uint8_t RESERVED_27[4];
11070 __I uint32_t SMCSR_PG0;
11071 uint8_t RESERVED_28[8];
11072 __I uint32_t CAAMVID_MS_TRAD;
11073 __I uint32_t CAAMVID_LS_TRAD;
11074 struct { /* offset: 0xC00, array step: 0x20 */
11075 __I uint64_t HT_JD_ADDR;
11076 __I uint64_t HT_SD_ADDR;
11079 uint8_t RESERVED_0[4];
11080 __I uint32_t HT_STATUS;
11081 } HTA[1];
11082 uint8_t RESERVED_29[4];
11083 __IO uint32_t JQ_DEBUG_SEL;
11084 uint8_t RESERVED_30[404];
11085 __I uint32_t JRJIDU_LS;
11086 __I uint32_t JRJDJIFBC;
11087 __I uint32_t JRJDJIF;
11088 uint8_t RESERVED_31[28];
11089 __I uint32_t JRJDS1;
11090 uint8_t RESERVED_32[24];
11091 __I uint64_t JRJDDA[1];
11092 uint8_t RESERVED_33[408];
11093 __I uint32_t CRNR_MS;
11094 __I uint32_t CRNR_LS;
11095 __I uint32_t CTPR_MS;
11096 __I uint32_t CTPR_LS;
11097 uint8_t RESERVED_34[4];
11098 __I uint32_t SMSTA;
11099 uint8_t RESERVED_35[4];
11100 __I uint32_t SMPO;
11101 __I uint64_t FAR;
11102 __I uint32_t FADID;
11103 __I uint32_t FADR;
11104 uint8_t RESERVED_36[4];
11105 __I uint32_t CSTA;
11106 __I uint32_t SMVID_MS;
11107 __I uint32_t SMVID_LS;
11108 __I uint32_t RVID;
11109 __I uint32_t CCBVID;
11110 __I uint32_t CHAVID_MS;
11111 __I uint32_t CHAVID_LS;
11112 __I uint32_t CHANUM_MS;
11113 __I uint32_t CHANUM_LS;
11114 __I uint32_t CAAMVID_MS;
11115 __I uint32_t CAAMVID_LS;
11116 uint8_t RESERVED_37[61440];
11117 struct { /* offset: 0x10000, array step: 0x10000 */
11118 __IO uint64_t IRBAR_JR;
11119 uint8_t RESERVED_0[4];
11120 __IO uint32_t IRSR_JR;
11121 uint8_t RESERVED_1[4];
11122 __IO uint32_t IRSAR_JR;
11123 uint8_t RESERVED_2[4];
11124 __IO uint32_t IRJAR_JR;
11125 __IO uint64_t ORBAR_JR;
11126 uint8_t RESERVED_3[4];
11127 __IO uint32_t ORSR_JR;
11128 uint8_t RESERVED_4[4];
11129 __IO uint32_t ORJRR_JR;
11130 uint8_t RESERVED_5[4];
11131 __IO uint32_t ORSFR_JR;
11132 uint8_t RESERVED_6[4];
11133 __I uint32_t JRSTAR_JR;
11134 uint8_t RESERVED_7[4];
11135 __IO uint32_t JRINTR_JR;
11138 uint8_t RESERVED_8[4];
11139 __IO uint32_t IRRIR_JR;
11140 uint8_t RESERVED_9[4];
11141 __IO uint32_t ORWIR_JR;
11142 uint8_t RESERVED_10[4];
11143 __O uint32_t JRCR_JR;
11144 uint8_t RESERVED_11[1684];
11145 __I uint32_t JRAAV;
11146 uint8_t RESERVED_12[248];
11147 __I uint64_t JRAAA[4];
11148 uint8_t RESERVED_13[480];
11149 struct { /* offset: 0x10A00, array step: index*0x10000, index2*0x10 */
11150 __I uint32_t PX_SDID_JR;
11154 } PX_JR[16];
11155 uint8_t RESERVED_14[228];
11156 __O uint32_t SMCR_JR;
11157 uint8_t RESERVED_15[4];
11158 __I uint32_t SMCSR_JR;
11159 uint8_t RESERVED_16[528];
11160 __I uint32_t REIR0JR;
11161 uint8_t RESERVED_17[4];
11162 __I uint64_t REIR2JR;
11163 __I uint32_t REIR4JR;
11164 __I uint32_t REIR5JR;
11165 uint8_t RESERVED_18[392];
11166 __I uint32_t CRNR_MS_JR;
11167 __I uint32_t CRNR_LS_JR;
11168 __I uint32_t CTPR_MS_JR;
11169 __I uint32_t CTPR_LS_JR;
11170 uint8_t RESERVED_19[4];
11171 __I uint32_t SMSTA_JR;
11172 uint8_t RESERVED_20[4];
11173 __I uint32_t SMPO_JR;
11174 __I uint64_t FAR_JR;
11175 __I uint32_t FADID_JR;
11176 __I uint32_t FADR_JR;
11177 uint8_t RESERVED_21[4];
11178 __I uint32_t CSTA_JR;
11179 __I uint32_t SMVID_MS_JR;
11180 __I uint32_t SMVID_LS_JR;
11181 __I uint32_t RVID_JR;
11182 __I uint32_t CCBVID_JR;
11189 uint8_t RESERVED_22[61440];
11190 } JOBRING[4];
11191 uint8_t RESERVED_38[65540];
11192 __I uint32_t RSTA;
11193 uint8_t RESERVED_39[4];
11194 __IO uint32_t RCMD;
11195 uint8_t RESERVED_40[4];
11196 __IO uint32_t RCTL;
11197 uint8_t RESERVED_41[4];
11198 __IO uint32_t RTHR;
11199 uint8_t RESERVED_42[8];
11200 __IO uint64_t RWDOG;
11201 uint8_t RESERVED_43[4];
11202 __IO uint32_t REND;
11203 uint8_t RESERVED_44[200];
11204 struct { /* offset: 0x60100, array step: index*0x20, index2*0x10 */
11205 __IO uint64_t RMA;
11206 uint8_t RESERVED_0[4];
11207 __IO uint32_t RML;
11208 } RM[4][2];
11209 uint8_t RESERVED_45[128];
11210 __IO uint32_t RMD[4][2][32];
11211 uint8_t RESERVED_46[2048];
11212 __I uint32_t REIR0RTIC;
11213 uint8_t RESERVED_47[4];
11214 __I uint64_t REIR2RTIC;
11215 __I uint32_t REIR4RTIC;
11216 __I uint32_t REIR5RTIC;
11217 uint8_t RESERVED_48[392];
11218 __I uint32_t CRNR_MS_RTIC;
11219 __I uint32_t CRNR_LS_RTIC;
11220 __I uint32_t CTPR_MS_RTIC;
11221 __I uint32_t CTPR_LS_RTIC;
11222 uint8_t RESERVED_49[4];
11223 __I uint32_t SMSTA_RTIC;
11224 uint8_t RESERVED_50[8];
11225 __I uint64_t FAR_RTIC;
11226 __I uint32_t FADID_RTIC;
11227 __I uint32_t FADR_RTIC;
11228 uint8_t RESERVED_51[4];
11229 __I uint32_t CSTA_RTIC;
11230 __I uint32_t SMVID_MS_RTIC;
11231 __I uint32_t SMVID_LS_RTIC;
11232 __I uint32_t RVID_RTIC;
11233 __I uint32_t CCBVID_RTIC;
11234 __I uint32_t CHAVID_MS_RTIC;
11235 __I uint32_t CHAVID_LS_RTIC;
11236 __I uint32_t CHANUM_MS_RTIC;
11237 __I uint32_t CHANUM_LS_RTIC;
11238 __I uint32_t CAAMVID_MS_RTIC;
11239 __I uint32_t CAAMVID_LS_RTIC;
11240 uint8_t RESERVED_52[126976];
11241 struct { /* offset: 0x80000, array step: 0xE3C */
11242 uint8_t RESERVED_0[4];
11243 union { /* offset: 0x80004, array step: 0xE3C */
11244 __IO uint32_t CC1MR;
11245 __IO uint32_t CC1MR_PK;
11246 __IO uint32_t CC1MR_RNG;
11247 };
11248 uint8_t RESERVED_1[4];
11249 __IO uint32_t CC1KSR;
11250 __IO uint64_t CC1DSR;
11251 uint8_t RESERVED_2[4];
11252 __IO uint32_t CC1ICVSR;
11253 uint8_t RESERVED_3[20];
11254 __O uint32_t CCCTRL;
11255 uint8_t RESERVED_4[4];
11256 __IO uint32_t CICTL;
11257 uint8_t RESERVED_5[4];
11258 __O uint32_t CCWR;
11259 __I uint32_t CCSTA_MS;
11260 __I uint32_t CCSTA_LS;
11261 uint8_t RESERVED_6[12];
11262 __IO uint32_t CC1AADSZR;
11263 uint8_t RESERVED_7[4];
11264 __IO uint32_t CC1IVSZR;
11265 uint8_t RESERVED_8[28];
11266 __IO uint32_t CPKASZR;
11267 uint8_t RESERVED_9[4];
11268 __IO uint32_t CPKBSZR;
11269 uint8_t RESERVED_10[4];
11270 __IO uint32_t CPKNSZR;
11271 uint8_t RESERVED_11[4];
11272 __IO uint32_t CPKESZR;
11273 uint8_t RESERVED_12[96];
11274 __IO uint32_t CC1CTXR[16];
11275 uint8_t RESERVED_13[192];
11276 __IO uint32_t CC1KR[8];
11277 uint8_t RESERVED_14[484];
11278 __IO uint32_t CC2MR;
11279 uint8_t RESERVED_15[4];
11280 __IO uint32_t CC2KSR;
11281 __IO uint64_t CC2DSR;
11282 uint8_t RESERVED_16[4];
11283 __IO uint32_t CC2ICVSZR;
11284 uint8_t RESERVED_17[224];
11285 __IO uint32_t CC2CTXR[18];
11286 uint8_t RESERVED_18[184];
11287 __IO uint32_t CC2KEYR[32];
11288 uint8_t RESERVED_19[320];
11289 __I uint32_t CFIFOSTA;
11290 uint8_t RESERVED_20[12];
11291 union { /* offset: 0x807D0, array step: 0xE3C */
11292 __O uint32_t CNFIFO;
11293 __O uint32_t CNFIFO_2;
11294 };
11295 uint8_t RESERVED_21[12];
11296 __O uint32_t CIFIFO;
11297 uint8_t RESERVED_22[12];
11298 __I uint64_t COFIFO;
11299 uint8_t RESERVED_23[8];
11300 __IO uint32_t DJQCR_MS;
11301 __I uint32_t DJQCR_LS;
11302 __I uint64_t DDAR;
11303 __I uint32_t DOPSTA_MS;
11304 __I uint32_t DOPSTA_LS;
11305 uint8_t RESERVED_24[8];
11306 __I uint32_t DPDIDSR;
11307 __I uint32_t DODIDSR;
11308 uint8_t RESERVED_25[24];
11309 struct { /* offset: 0x80840, array step: index*0xE3C, index2*0x8 */
11310 __IO uint32_t DMTH_MS;
11311 __IO uint32_t DMTH_LS;
11312 } DDMTHB[4];
11313 uint8_t RESERVED_26[32];
11314 struct { /* offset: 0x80880, array step: index*0xE3C, index2*0x10 */
11315 __IO uint32_t DGTR_0;
11316 __IO uint32_t DGTR_1;
11317 __IO uint32_t DGTR_2;
11318 __IO uint32_t DGTR_3;
11319 } DDGTR[1];
11320 uint8_t RESERVED_27[112];
11321 struct { /* offset: 0x80900, array step: index*0xE3C, index2*0x10 */
11322 __IO uint32_t DSTR_0;
11323 __IO uint32_t DSTR_1;
11324 __IO uint32_t DSTR_2;
11325 __IO uint32_t DSTR_3;
11326 } DDSTR[1];
11327 uint8_t RESERVED_28[240];
11328 __IO uint32_t DDESB[64];
11329 uint8_t RESERVED_29[768];
11330 __I uint32_t DDJR;
11331 __I uint32_t DDDR;
11332 __I uint64_t DDJP;
11333 __I uint64_t DSDP;
11334 __I uint32_t DDDR_MS;
11335 __I uint32_t DDDR_LS;
11336 __IO uint32_t SOL;
11337 __IO uint32_t VSOL;
11338 __IO uint32_t SIL;
11339 __IO uint32_t VSIL;
11340 __IO uint32_t DPOVRD;
11341 __IO uint32_t UVSOL;
11342 __IO uint32_t UVSIL;
11343 } DC[1];
11344 uint8_t RESERVED_53[356];
11345 __I uint32_t CRNR_MS_DC01;
11346 __I uint32_t CRNR_LS_DC01;
11347 __I uint32_t CTPR_MS_DC01;
11348 __I uint32_t CTPR_LS_DC01;
11349 uint8_t RESERVED_54[4];
11350 __I uint32_t SMSTA_DC01;
11351 uint8_t RESERVED_55[8];
11352 __I uint64_t FAR_DC01;
11353 __I uint32_t FADID_DC01;
11354 __I uint32_t FADR_DC01;
11355 uint8_t RESERVED_56[4];
11356 __I uint32_t CSTA_DC01;
11357 __I uint32_t SMVID_MS_DC01;
11358 __I uint32_t SMVID_LS_DC01;
11359 __I uint32_t RVID_DC01;
11360 __I uint32_t CCBVID_DC01;
11361 __I uint32_t CHAVID_MS_DC01;
11362 __I uint32_t CHAVID_LS_DC01;
11363 __I uint32_t CHANUM_MS_DC01;
11364 __I uint32_t CHANUM_LS_DC01;
11365 __I uint32_t CAAMVID_MS_DC01;
11366 __I uint32_t CAAMVID_LS_DC01;
11367} CAAM_Type;
11368
11369/* ----------------------------------------------------------------------------
11370 -- CAAM Register Masks
11371 ---------------------------------------------------------------------------- */
11372
11381#define CAAM_MCFGR_NORMAL_BURST_MASK (0x1U)
11382#define CAAM_MCFGR_NORMAL_BURST_SHIFT (0U)
11387#define CAAM_MCFGR_NORMAL_BURST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_NORMAL_BURST_SHIFT)) & CAAM_MCFGR_NORMAL_BURST_MASK)
11388
11389#define CAAM_MCFGR_LARGE_BURST_MASK (0x4U)
11390#define CAAM_MCFGR_LARGE_BURST_SHIFT (2U)
11391#define CAAM_MCFGR_LARGE_BURST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_LARGE_BURST_SHIFT)) & CAAM_MCFGR_LARGE_BURST_MASK)
11392
11393#define CAAM_MCFGR_AXIPIPE_MASK (0xF0U)
11394#define CAAM_MCFGR_AXIPIPE_SHIFT (4U)
11395#define CAAM_MCFGR_AXIPIPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AXIPIPE_SHIFT)) & CAAM_MCFGR_AXIPIPE_MASK)
11396
11397#define CAAM_MCFGR_AWCACHE_MASK (0xF00U)
11398#define CAAM_MCFGR_AWCACHE_SHIFT (8U)
11399#define CAAM_MCFGR_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AWCACHE_SHIFT)) & CAAM_MCFGR_AWCACHE_MASK)
11400
11401#define CAAM_MCFGR_ARCACHE_MASK (0xF000U)
11402#define CAAM_MCFGR_ARCACHE_SHIFT (12U)
11403#define CAAM_MCFGR_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_ARCACHE_SHIFT)) & CAAM_MCFGR_ARCACHE_MASK)
11404
11405#define CAAM_MCFGR_PS_MASK (0x10000U)
11406#define CAAM_MCFGR_PS_SHIFT (16U)
11411#define CAAM_MCFGR_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_PS_SHIFT)) & CAAM_MCFGR_PS_MASK)
11412
11413#define CAAM_MCFGR_DWT_MASK (0x80000U)
11414#define CAAM_MCFGR_DWT_SHIFT (19U)
11415#define CAAM_MCFGR_DWT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DWT_SHIFT)) & CAAM_MCFGR_DWT_MASK)
11416
11417#define CAAM_MCFGR_WRHD_MASK (0x8000000U)
11418#define CAAM_MCFGR_WRHD_SHIFT (27U)
11419#define CAAM_MCFGR_WRHD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WRHD_SHIFT)) & CAAM_MCFGR_WRHD_MASK)
11420
11421#define CAAM_MCFGR_DMA_RST_MASK (0x10000000U)
11422#define CAAM_MCFGR_DMA_RST_SHIFT (28U)
11423#define CAAM_MCFGR_DMA_RST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DMA_RST_SHIFT)) & CAAM_MCFGR_DMA_RST_MASK)
11424
11425#define CAAM_MCFGR_WDF_MASK (0x20000000U)
11426#define CAAM_MCFGR_WDF_SHIFT (29U)
11427#define CAAM_MCFGR_WDF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDF_SHIFT)) & CAAM_MCFGR_WDF_MASK)
11428
11429#define CAAM_MCFGR_WDE_MASK (0x40000000U)
11430#define CAAM_MCFGR_WDE_SHIFT (30U)
11431#define CAAM_MCFGR_WDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDE_SHIFT)) & CAAM_MCFGR_WDE_MASK)
11432
11433#define CAAM_MCFGR_SWRST_MASK (0x80000000U)
11434#define CAAM_MCFGR_SWRST_SHIFT (31U)
11435#define CAAM_MCFGR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_SWRST_SHIFT)) & CAAM_MCFGR_SWRST_MASK)
11441#define CAAM_PAGE0_SDID_SDID_MASK (0x7FFFU)
11442#define CAAM_PAGE0_SDID_SDID_SHIFT (0U)
11443#define CAAM_PAGE0_SDID_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PAGE0_SDID_SDID_SHIFT)) & CAAM_PAGE0_SDID_SDID_MASK)
11449#define CAAM_SCFGR_PRIBLOB_MASK (0x3U)
11450#define CAAM_SCFGR_PRIBLOB_SHIFT (0U)
11457#define CAAM_SCFGR_PRIBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_PRIBLOB_SHIFT)) & CAAM_SCFGR_PRIBLOB_MASK)
11458
11459#define CAAM_SCFGR_RNGSH0_MASK (0x200U)
11460#define CAAM_SCFGR_RNGSH0_SHIFT (9U)
11468#define CAAM_SCFGR_RNGSH0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_RNGSH0_SHIFT)) & CAAM_SCFGR_RNGSH0_MASK)
11469
11470#define CAAM_SCFGR_LCK_TRNG_MASK (0x800U)
11471#define CAAM_SCFGR_LCK_TRNG_SHIFT (11U)
11472#define CAAM_SCFGR_LCK_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_LCK_TRNG_SHIFT)) & CAAM_SCFGR_LCK_TRNG_MASK)
11473
11474#define CAAM_SCFGR_VIRT_EN_MASK (0x8000U)
11475#define CAAM_SCFGR_VIRT_EN_SHIFT (15U)
11480#define CAAM_SCFGR_VIRT_EN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_VIRT_EN_SHIFT)) & CAAM_SCFGR_VIRT_EN_MASK)
11481
11482#define CAAM_SCFGR_MPMRL_MASK (0x4000000U)
11483#define CAAM_SCFGR_MPMRL_SHIFT (26U)
11484#define CAAM_SCFGR_MPMRL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPMRL_SHIFT)) & CAAM_SCFGR_MPMRL_MASK)
11485
11486#define CAAM_SCFGR_MPPKRC_MASK (0x8000000U)
11487#define CAAM_SCFGR_MPPKRC_SHIFT (27U)
11488#define CAAM_SCFGR_MPPKRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPPKRC_SHIFT)) & CAAM_SCFGR_MPPKRC_MASK)
11489
11490#define CAAM_SCFGR_MPCURVE_MASK (0xF0000000U)
11491#define CAAM_SCFGR_MPCURVE_SHIFT (28U)
11492#define CAAM_SCFGR_MPCURVE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPCURVE_SHIFT)) & CAAM_SCFGR_MPCURVE_MASK)
11498#define CAAM_JRDID_MS_PRIM_DID_MASK (0xFU)
11499#define CAAM_JRDID_MS_PRIM_DID_SHIFT (0U)
11500#define CAAM_JRDID_MS_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_DID_SHIFT)) & CAAM_JRDID_MS_PRIM_DID_MASK)
11501
11502#define CAAM_JRDID_MS_PRIM_TZ_MASK (0x10U)
11503#define CAAM_JRDID_MS_PRIM_TZ_SHIFT (4U)
11504#define CAAM_JRDID_MS_PRIM_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_TZ_SHIFT)) & CAAM_JRDID_MS_PRIM_TZ_MASK)
11505
11506#define CAAM_JRDID_MS_SDID_MS_MASK (0x7FE0U)
11507#define CAAM_JRDID_MS_SDID_MS_SHIFT (5U)
11508#define CAAM_JRDID_MS_SDID_MS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_SDID_MS_SHIFT)) & CAAM_JRDID_MS_SDID_MS_MASK)
11509
11510#define CAAM_JRDID_MS_TZ_OWN_MASK (0x8000U)
11511#define CAAM_JRDID_MS_TZ_OWN_SHIFT (15U)
11512#define CAAM_JRDID_MS_TZ_OWN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_TZ_OWN_SHIFT)) & CAAM_JRDID_MS_TZ_OWN_MASK)
11513
11514#define CAAM_JRDID_MS_AMTD_MASK (0x10000U)
11515#define CAAM_JRDID_MS_AMTD_SHIFT (16U)
11516#define CAAM_JRDID_MS_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_AMTD_SHIFT)) & CAAM_JRDID_MS_AMTD_MASK)
11517
11518#define CAAM_JRDID_MS_LAMTD_MASK (0x20000U)
11519#define CAAM_JRDID_MS_LAMTD_SHIFT (17U)
11520#define CAAM_JRDID_MS_LAMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LAMTD_SHIFT)) & CAAM_JRDID_MS_LAMTD_MASK)
11521
11522#define CAAM_JRDID_MS_PRIM_ICID_MASK (0x3FF80000U)
11523#define CAAM_JRDID_MS_PRIM_ICID_SHIFT (19U)
11524#define CAAM_JRDID_MS_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_ICID_SHIFT)) & CAAM_JRDID_MS_PRIM_ICID_MASK)
11525
11526#define CAAM_JRDID_MS_USE_OUT_MASK (0x40000000U)
11527#define CAAM_JRDID_MS_USE_OUT_SHIFT (30U)
11528#define CAAM_JRDID_MS_USE_OUT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_USE_OUT_SHIFT)) & CAAM_JRDID_MS_USE_OUT_MASK)
11529
11530#define CAAM_JRDID_MS_LDID_MASK (0x80000000U)
11531#define CAAM_JRDID_MS_LDID_SHIFT (31U)
11532#define CAAM_JRDID_MS_LDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LDID_SHIFT)) & CAAM_JRDID_MS_LDID_MASK)
11535/* The count of CAAM_JRDID_MS */
11536#define CAAM_JRDID_MS_COUNT (4U)
11537
11541#define CAAM_JRDID_LS_OUT_DID_MASK (0xFU)
11542#define CAAM_JRDID_LS_OUT_DID_SHIFT (0U)
11543#define CAAM_JRDID_LS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_DID_SHIFT)) & CAAM_JRDID_LS_OUT_DID_MASK)
11544
11545#define CAAM_JRDID_LS_OUT_ICID_MASK (0x3FF80000U)
11546#define CAAM_JRDID_LS_OUT_ICID_SHIFT (19U)
11547#define CAAM_JRDID_LS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_ICID_SHIFT)) & CAAM_JRDID_LS_OUT_ICID_MASK)
11550/* The count of CAAM_JRDID_LS */
11551#define CAAM_JRDID_LS_COUNT (4U)
11552
11556#define CAAM_DEBUGCTL_STOP_MASK (0x10000U)
11557#define CAAM_DEBUGCTL_STOP_SHIFT (16U)
11558#define CAAM_DEBUGCTL_STOP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_SHIFT)) & CAAM_DEBUGCTL_STOP_MASK)
11559
11560#define CAAM_DEBUGCTL_STOP_ACK_MASK (0x20000U)
11561#define CAAM_DEBUGCTL_STOP_ACK_SHIFT (17U)
11562#define CAAM_DEBUGCTL_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_ACK_SHIFT)) & CAAM_DEBUGCTL_STOP_ACK_MASK)
11568#define CAAM_JRSTARTR_Start_JR0_MASK (0x1U)
11569#define CAAM_JRSTARTR_Start_JR0_SHIFT (0U)
11580#define CAAM_JRSTARTR_Start_JR0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR0_SHIFT)) & CAAM_JRSTARTR_Start_JR0_MASK)
11581
11582#define CAAM_JRSTARTR_Start_JR1_MASK (0x2U)
11583#define CAAM_JRSTARTR_Start_JR1_SHIFT (1U)
11594#define CAAM_JRSTARTR_Start_JR1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR1_SHIFT)) & CAAM_JRSTARTR_Start_JR1_MASK)
11595
11596#define CAAM_JRSTARTR_Start_JR2_MASK (0x4U)
11597#define CAAM_JRSTARTR_Start_JR2_SHIFT (2U)
11608#define CAAM_JRSTARTR_Start_JR2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR2_SHIFT)) & CAAM_JRSTARTR_Start_JR2_MASK)
11609
11610#define CAAM_JRSTARTR_Start_JR3_MASK (0x8U)
11611#define CAAM_JRSTARTR_Start_JR3_SHIFT (3U)
11622#define CAAM_JRSTARTR_Start_JR3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR3_SHIFT)) & CAAM_JRSTARTR_Start_JR3_MASK)
11628#define CAAM_RTIC_OWN_ROWN_DID_MASK (0xFU)
11629#define CAAM_RTIC_OWN_ROWN_DID_SHIFT (0U)
11632#define CAAM_RTIC_OWN_ROWN_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_DID_SHIFT)) & CAAM_RTIC_OWN_ROWN_DID_MASK)
11633
11634#define CAAM_RTIC_OWN_ROWN_TZ_MASK (0x10U)
11635#define CAAM_RTIC_OWN_ROWN_TZ_SHIFT (4U)
11636#define CAAM_RTIC_OWN_ROWN_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_TZ_SHIFT)) & CAAM_RTIC_OWN_ROWN_TZ_MASK)
11637
11638#define CAAM_RTIC_OWN_LCK_MASK (0x80000000U)
11639#define CAAM_RTIC_OWN_LCK_SHIFT (31U)
11640#define CAAM_RTIC_OWN_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_LCK_SHIFT)) & CAAM_RTIC_OWN_LCK_MASK)
11646#define CAAM_RTIC_DID_RTIC_DID_MASK (0xFU)
11647#define CAAM_RTIC_DID_RTIC_DID_SHIFT (0U)
11648#define CAAM_RTIC_DID_RTIC_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_DID_SHIFT)) & CAAM_RTIC_DID_RTIC_DID_MASK)
11649
11650#define CAAM_RTIC_DID_RTIC_TZ_MASK (0x10U)
11651#define CAAM_RTIC_DID_RTIC_TZ_SHIFT (4U)
11652#define CAAM_RTIC_DID_RTIC_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_TZ_SHIFT)) & CAAM_RTIC_DID_RTIC_TZ_MASK)
11653
11654#define CAAM_RTIC_DID_RTIC_ICID_MASK (0x3FF80000U)
11655#define CAAM_RTIC_DID_RTIC_ICID_SHIFT (19U)
11656#define CAAM_RTIC_DID_RTIC_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_ICID_SHIFT)) & CAAM_RTIC_DID_RTIC_ICID_MASK)
11659/* The count of CAAM_RTIC_DID */
11660#define CAAM_RTIC_DID_COUNT (4U)
11661
11665#define CAAM_DECORSR_JR_MASK (0x3U)
11666#define CAAM_DECORSR_JR_SHIFT (0U)
11667#define CAAM_DECORSR_JR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_JR_SHIFT)) & CAAM_DECORSR_JR_MASK)
11668
11669#define CAAM_DECORSR_VALID_MASK (0x80000000U)
11670#define CAAM_DECORSR_VALID_SHIFT (31U)
11671#define CAAM_DECORSR_VALID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_VALID_SHIFT)) & CAAM_DECORSR_VALID_MASK)
11677#define CAAM_DECORR_RQD0_MASK (0x1U)
11678#define CAAM_DECORR_RQD0_SHIFT (0U)
11679#define CAAM_DECORR_RQD0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_RQD0_SHIFT)) & CAAM_DECORR_RQD0_MASK)
11680
11681#define CAAM_DECORR_DEN0_MASK (0x10000U)
11682#define CAAM_DECORR_DEN0_SHIFT (16U)
11683#define CAAM_DECORR_DEN0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_DEN0_SHIFT)) & CAAM_DECORR_DEN0_MASK)
11689#define CAAM_DECODID_MS_DPRIM_DID_MASK (0xFU)
11690#define CAAM_DECODID_MS_DPRIM_DID_SHIFT (0U)
11693#define CAAM_DECODID_MS_DPRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_DPRIM_DID_SHIFT)) & CAAM_DECODID_MS_DPRIM_DID_MASK)
11694
11695#define CAAM_DECODID_MS_D_NS_MASK (0x10U)
11696#define CAAM_DECODID_MS_D_NS_SHIFT (4U)
11697#define CAAM_DECODID_MS_D_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_D_NS_SHIFT)) & CAAM_DECODID_MS_D_NS_MASK)
11698
11699#define CAAM_DECODID_MS_LCK_MASK (0x80000000U)
11700#define CAAM_DECODID_MS_LCK_SHIFT (31U)
11701#define CAAM_DECODID_MS_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_LCK_SHIFT)) & CAAM_DECODID_MS_LCK_MASK)
11704/* The count of CAAM_DECODID_MS */
11705#define CAAM_DECODID_MS_COUNT (1U)
11706
11710#define CAAM_DECODID_LS_DSEQ_DID_MASK (0xFU)
11711#define CAAM_DECODID_LS_DSEQ_DID_SHIFT (0U)
11712#define CAAM_DECODID_LS_DSEQ_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DSEQ_DID_MASK)
11713
11714#define CAAM_DECODID_LS_DSEQ_NS_MASK (0x10U)
11715#define CAAM_DECODID_LS_DSEQ_NS_SHIFT (4U)
11716#define CAAM_DECODID_LS_DSEQ_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DSEQ_NS_MASK)
11717
11718#define CAAM_DECODID_LS_DNSEQ_DID_MASK (0xF0000U)
11719#define CAAM_DECODID_LS_DNSEQ_DID_SHIFT (16U)
11720#define CAAM_DECODID_LS_DNSEQ_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DNSEQ_DID_MASK)
11721
11722#define CAAM_DECODID_LS_DNONSEQ_NS_MASK (0x100000U)
11723#define CAAM_DECODID_LS_DNONSEQ_NS_SHIFT (20U)
11724#define CAAM_DECODID_LS_DNONSEQ_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNONSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DNONSEQ_NS_MASK)
11727/* The count of CAAM_DECODID_LS */
11728#define CAAM_DECODID_LS_COUNT (1U)
11729
11733#define CAAM_DAR_NYA0_MASK (0x1U)
11734#define CAAM_DAR_NYA0_SHIFT (0U)
11735#define CAAM_DAR_NYA0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DAR_NYA0_SHIFT)) & CAAM_DAR_NYA0_MASK)
11741#define CAAM_DRR_RST0_MASK (0x1U)
11742#define CAAM_DRR_RST0_SHIFT (0U)
11743#define CAAM_DRR_RST0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DRR_RST0_SHIFT)) & CAAM_DRR_RST0_MASK)
11749#define CAAM_JRSMVBAR_SMVBA_MASK (0xFFFFFFFFU)
11750#define CAAM_JRSMVBAR_SMVBA_SHIFT (0U)
11751#define CAAM_JRSMVBAR_SMVBA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSMVBAR_SMVBA_SHIFT)) & CAAM_JRSMVBAR_SMVBA_MASK)
11754/* The count of CAAM_JRSMVBAR */
11755#define CAAM_JRSMVBAR_COUNT (4U)
11756
11760#define CAAM_PBSL_PBSL_MASK (0x7FU)
11761#define CAAM_PBSL_PBSL_SHIFT (0U)
11762#define CAAM_PBSL_PBSL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PBSL_PBSL_SHIFT)) & CAAM_PBSL_PBSL_MASK)
11768#define CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK (0xFFU)
11769#define CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT (0U)
11770#define CAAM_DMA_AIDL_MAP_MS_AID4_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK)
11771
11772#define CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK (0xFF00U)
11773#define CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT (8U)
11774#define CAAM_DMA_AIDL_MAP_MS_AID5_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK)
11775
11776#define CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK (0xFF0000U)
11777#define CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT (16U)
11778#define CAAM_DMA_AIDL_MAP_MS_AID6_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK)
11779
11780#define CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK (0xFF000000U)
11781#define CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT (24U)
11782#define CAAM_DMA_AIDL_MAP_MS_AID7_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK)
11785/* The count of CAAM_DMA_AIDL_MAP_MS */
11786#define CAAM_DMA_AIDL_MAP_MS_COUNT (1U)
11787
11791#define CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK (0xFFU)
11792#define CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT (0U)
11793#define CAAM_DMA_AIDL_MAP_LS_AID0_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK)
11794
11795#define CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK (0xFF00U)
11796#define CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT (8U)
11797#define CAAM_DMA_AIDL_MAP_LS_AID1_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK)
11798
11799#define CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK (0xFF0000U)
11800#define CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT (16U)
11801#define CAAM_DMA_AIDL_MAP_LS_AID2_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK)
11802
11803#define CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK (0xFF000000U)
11804#define CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT (24U)
11805#define CAAM_DMA_AIDL_MAP_LS_AID3_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK)
11808/* The count of CAAM_DMA_AIDL_MAP_LS */
11809#define CAAM_DMA_AIDL_MAP_LS_COUNT (1U)
11810
11814#define CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK (0xFFU)
11815#define CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT (0U)
11816#define CAAM_DMA_AIDM_MAP_MS_AID12_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK)
11817
11818#define CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK (0xFF00U)
11819#define CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT (8U)
11820#define CAAM_DMA_AIDM_MAP_MS_AID13_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK)
11821
11822#define CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK (0xFF0000U)
11823#define CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT (16U)
11824#define CAAM_DMA_AIDM_MAP_MS_AID14_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK)
11825
11826#define CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK (0xFF000000U)
11827#define CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT (24U)
11828#define CAAM_DMA_AIDM_MAP_MS_AID15_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK)
11831/* The count of CAAM_DMA_AIDM_MAP_MS */
11832#define CAAM_DMA_AIDM_MAP_MS_COUNT (1U)
11833
11837#define CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK (0xFFU)
11838#define CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT (0U)
11839#define CAAM_DMA_AIDM_MAP_LS_AID8_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK)
11840
11841#define CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK (0xFF00U)
11842#define CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT (8U)
11843#define CAAM_DMA_AIDM_MAP_LS_AID9_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK)
11844
11845#define CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK (0xFF0000U)
11846#define CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT (16U)
11847#define CAAM_DMA_AIDM_MAP_LS_AID10_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK)
11848
11849#define CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK (0xFF000000U)
11850#define CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT (24U)
11851#define CAAM_DMA_AIDM_MAP_LS_AID11_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK)
11854/* The count of CAAM_DMA_AIDM_MAP_LS */
11855#define CAAM_DMA_AIDM_MAP_LS_COUNT (1U)
11856
11860#define CAAM_DMA0_AID_ENB_AID0E_MASK (0x1U)
11861#define CAAM_DMA0_AID_ENB_AID0E_SHIFT (0U)
11862#define CAAM_DMA0_AID_ENB_AID0E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID0E_SHIFT)) & CAAM_DMA0_AID_ENB_AID0E_MASK)
11863
11864#define CAAM_DMA0_AID_ENB_AID1E_MASK (0x2U)
11865#define CAAM_DMA0_AID_ENB_AID1E_SHIFT (1U)
11866#define CAAM_DMA0_AID_ENB_AID1E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID1E_SHIFT)) & CAAM_DMA0_AID_ENB_AID1E_MASK)
11867
11868#define CAAM_DMA0_AID_ENB_AID2E_MASK (0x4U)
11869#define CAAM_DMA0_AID_ENB_AID2E_SHIFT (2U)
11870#define CAAM_DMA0_AID_ENB_AID2E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID2E_SHIFT)) & CAAM_DMA0_AID_ENB_AID2E_MASK)
11871
11872#define CAAM_DMA0_AID_ENB_AID3E_MASK (0x8U)
11873#define CAAM_DMA0_AID_ENB_AID3E_SHIFT (3U)
11874#define CAAM_DMA0_AID_ENB_AID3E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID3E_SHIFT)) & CAAM_DMA0_AID_ENB_AID3E_MASK)
11875
11876#define CAAM_DMA0_AID_ENB_AID4E_MASK (0x10U)
11877#define CAAM_DMA0_AID_ENB_AID4E_SHIFT (4U)
11878#define CAAM_DMA0_AID_ENB_AID4E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID4E_SHIFT)) & CAAM_DMA0_AID_ENB_AID4E_MASK)
11879
11880#define CAAM_DMA0_AID_ENB_AID5E_MASK (0x20U)
11881#define CAAM_DMA0_AID_ENB_AID5E_SHIFT (5U)
11882#define CAAM_DMA0_AID_ENB_AID5E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID5E_SHIFT)) & CAAM_DMA0_AID_ENB_AID5E_MASK)
11883
11884#define CAAM_DMA0_AID_ENB_AID6E_MASK (0x40U)
11885#define CAAM_DMA0_AID_ENB_AID6E_SHIFT (6U)
11886#define CAAM_DMA0_AID_ENB_AID6E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID6E_SHIFT)) & CAAM_DMA0_AID_ENB_AID6E_MASK)
11887
11888#define CAAM_DMA0_AID_ENB_AID7E_MASK (0x80U)
11889#define CAAM_DMA0_AID_ENB_AID7E_SHIFT (7U)
11890#define CAAM_DMA0_AID_ENB_AID7E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID7E_SHIFT)) & CAAM_DMA0_AID_ENB_AID7E_MASK)
11891
11892#define CAAM_DMA0_AID_ENB_AID8E_MASK (0x100U)
11893#define CAAM_DMA0_AID_ENB_AID8E_SHIFT (8U)
11894#define CAAM_DMA0_AID_ENB_AID8E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID8E_SHIFT)) & CAAM_DMA0_AID_ENB_AID8E_MASK)
11895
11896#define CAAM_DMA0_AID_ENB_AID9E_MASK (0x200U)
11897#define CAAM_DMA0_AID_ENB_AID9E_SHIFT (9U)
11898#define CAAM_DMA0_AID_ENB_AID9E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID9E_SHIFT)) & CAAM_DMA0_AID_ENB_AID9E_MASK)
11899
11900#define CAAM_DMA0_AID_ENB_AID10E_MASK (0x400U)
11901#define CAAM_DMA0_AID_ENB_AID10E_SHIFT (10U)
11902#define CAAM_DMA0_AID_ENB_AID10E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID10E_SHIFT)) & CAAM_DMA0_AID_ENB_AID10E_MASK)
11903
11904#define CAAM_DMA0_AID_ENB_AID11E_MASK (0x800U)
11905#define CAAM_DMA0_AID_ENB_AID11E_SHIFT (11U)
11906#define CAAM_DMA0_AID_ENB_AID11E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID11E_SHIFT)) & CAAM_DMA0_AID_ENB_AID11E_MASK)
11907
11908#define CAAM_DMA0_AID_ENB_AID12E_MASK (0x1000U)
11909#define CAAM_DMA0_AID_ENB_AID12E_SHIFT (12U)
11910#define CAAM_DMA0_AID_ENB_AID12E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID12E_SHIFT)) & CAAM_DMA0_AID_ENB_AID12E_MASK)
11911
11912#define CAAM_DMA0_AID_ENB_AID13E_MASK (0x2000U)
11913#define CAAM_DMA0_AID_ENB_AID13E_SHIFT (13U)
11914#define CAAM_DMA0_AID_ENB_AID13E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID13E_SHIFT)) & CAAM_DMA0_AID_ENB_AID13E_MASK)
11915
11916#define CAAM_DMA0_AID_ENB_AID14E_MASK (0x4000U)
11917#define CAAM_DMA0_AID_ENB_AID14E_SHIFT (14U)
11918#define CAAM_DMA0_AID_ENB_AID14E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID14E_SHIFT)) & CAAM_DMA0_AID_ENB_AID14E_MASK)
11919
11920#define CAAM_DMA0_AID_ENB_AID15E_MASK (0x8000U)
11921#define CAAM_DMA0_AID_ENB_AID15E_SHIFT (15U)
11922#define CAAM_DMA0_AID_ENB_AID15E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID15E_SHIFT)) & CAAM_DMA0_AID_ENB_AID15E_MASK)
11928#define CAAM_DMA0_ARD_TC_ARSC_MASK (0xFFFFFU)
11929#define CAAM_DMA0_ARD_TC_ARSC_SHIFT (0U)
11930#define CAAM_DMA0_ARD_TC_ARSC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARSC_SHIFT)) & CAAM_DMA0_ARD_TC_ARSC_MASK)
11931
11932#define CAAM_DMA0_ARD_TC_ARLC_MASK (0xFFFFF000000U)
11933#define CAAM_DMA0_ARD_TC_ARLC_SHIFT (24U)
11934#define CAAM_DMA0_ARD_TC_ARLC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARLC_SHIFT)) & CAAM_DMA0_ARD_TC_ARLC_MASK)
11935
11936#define CAAM_DMA0_ARD_TC_ARL_MASK (0xFFF000000000000U)
11937#define CAAM_DMA0_ARD_TC_ARL_SHIFT (48U)
11938#define CAAM_DMA0_ARD_TC_ARL(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARL_SHIFT)) & CAAM_DMA0_ARD_TC_ARL_MASK)
11939
11940#define CAAM_DMA0_ARD_TC_ARTL_MASK (0x1000000000000000U)
11941#define CAAM_DMA0_ARD_TC_ARTL_SHIFT (60U)
11942#define CAAM_DMA0_ARD_TC_ARTL(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTL_SHIFT)) & CAAM_DMA0_ARD_TC_ARTL_MASK)
11943
11944#define CAAM_DMA0_ARD_TC_ARTT_MASK (0x2000000000000000U)
11945#define CAAM_DMA0_ARD_TC_ARTT_SHIFT (61U)
11946#define CAAM_DMA0_ARD_TC_ARTT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTT_SHIFT)) & CAAM_DMA0_ARD_TC_ARTT_MASK)
11947
11948#define CAAM_DMA0_ARD_TC_ARCT_MASK (0x4000000000000000U)
11949#define CAAM_DMA0_ARD_TC_ARCT_SHIFT (62U)
11950#define CAAM_DMA0_ARD_TC_ARCT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARCT_SHIFT)) & CAAM_DMA0_ARD_TC_ARCT_MASK)
11951
11952#define CAAM_DMA0_ARD_TC_ARTCE_MASK (0x8000000000000000U)
11953#define CAAM_DMA0_ARD_TC_ARTCE_SHIFT (63U)
11954#define CAAM_DMA0_ARD_TC_ARTCE(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTCE_SHIFT)) & CAAM_DMA0_ARD_TC_ARTCE_MASK)
11960#define CAAM_DMA0_ARD_LAT_SARL_MASK (0xFFFFFFFFU)
11961#define CAAM_DMA0_ARD_LAT_SARL_SHIFT (0U)
11962#define CAAM_DMA0_ARD_LAT_SARL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_ARD_LAT_SARL_SHIFT)) & CAAM_DMA0_ARD_LAT_SARL_MASK)
11968#define CAAM_DMA0_AWR_TC_AWSC_MASK (0xFFFFFU)
11969#define CAAM_DMA0_AWR_TC_AWSC_SHIFT (0U)
11970#define CAAM_DMA0_AWR_TC_AWSC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWSC_SHIFT)) & CAAM_DMA0_AWR_TC_AWSC_MASK)
11971
11972#define CAAM_DMA0_AWR_TC_AWLC_MASK (0xFFFFF000000U)
11973#define CAAM_DMA0_AWR_TC_AWLC_SHIFT (24U)
11974#define CAAM_DMA0_AWR_TC_AWLC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWLC_SHIFT)) & CAAM_DMA0_AWR_TC_AWLC_MASK)
11975
11976#define CAAM_DMA0_AWR_TC_AWL_MASK (0xFFF000000000000U)
11977#define CAAM_DMA0_AWR_TC_AWL_SHIFT (48U)
11978#define CAAM_DMA0_AWR_TC_AWL(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWL_SHIFT)) & CAAM_DMA0_AWR_TC_AWL_MASK)
11979
11980#define CAAM_DMA0_AWR_TC_AWTT_MASK (0x2000000000000000U)
11981#define CAAM_DMA0_AWR_TC_AWTT_SHIFT (61U)
11982#define CAAM_DMA0_AWR_TC_AWTT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTT_SHIFT)) & CAAM_DMA0_AWR_TC_AWTT_MASK)
11983
11984#define CAAM_DMA0_AWR_TC_AWCT_MASK (0x4000000000000000U)
11985#define CAAM_DMA0_AWR_TC_AWCT_SHIFT (62U)
11986#define CAAM_DMA0_AWR_TC_AWCT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWCT_SHIFT)) & CAAM_DMA0_AWR_TC_AWCT_MASK)
11987
11988#define CAAM_DMA0_AWR_TC_AWTCE_MASK (0x8000000000000000U)
11989#define CAAM_DMA0_AWR_TC_AWTCE_SHIFT (63U)
11990#define CAAM_DMA0_AWR_TC_AWTCE(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTCE_SHIFT)) & CAAM_DMA0_AWR_TC_AWTCE_MASK)
11996#define CAAM_DMA0_AWR_LAT_SAWL_MASK (0xFFFFFFFFU)
11997#define CAAM_DMA0_AWR_LAT_SAWL_SHIFT (0U)
11998#define CAAM_DMA0_AWR_LAT_SAWL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AWR_LAT_SAWL_SHIFT)) & CAAM_DMA0_AWR_LAT_SAWL_MASK)
12004#define CAAM_MPPKR_MPPrivK_MASK (0xFFU)
12005#define CAAM_MPPKR_MPPrivK_SHIFT (0U)
12006#define CAAM_MPPKR_MPPrivK(x) (((uint8_t)(((uint8_t)(x)) << CAAM_MPPKR_MPPrivK_SHIFT)) & CAAM_MPPKR_MPPrivK_MASK)
12009/* The count of CAAM_MPPKR */
12010#define CAAM_MPPKR_COUNT (64U)
12011
12015#define CAAM_MPMR_MPMSG_MASK (0xFFU)
12016#define CAAM_MPMR_MPMSG_SHIFT (0U)
12017#define CAAM_MPMR_MPMSG(x) (((uint8_t)(((uint8_t)(x)) << CAAM_MPMR_MPMSG_SHIFT)) & CAAM_MPMR_MPMSG_MASK)
12020/* The count of CAAM_MPMR */
12021#define CAAM_MPMR_COUNT (32U)
12022
12026#define CAAM_MPTESTR_TEST_VALUE_MASK (0xFFU)
12027#define CAAM_MPTESTR_TEST_VALUE_SHIFT (0U)
12028#define CAAM_MPTESTR_TEST_VALUE(x) (((uint8_t)(((uint8_t)(x)) << CAAM_MPTESTR_TEST_VALUE_SHIFT)) & CAAM_MPTESTR_TEST_VALUE_MASK)
12031/* The count of CAAM_MPTESTR */
12032#define CAAM_MPTESTR_COUNT (32U)
12033
12037#define CAAM_MPECC_MP_SYNDROME_MASK (0x1FF0000U)
12038#define CAAM_MPECC_MP_SYNDROME_SHIFT (16U)
12043#define CAAM_MPECC_MP_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_SYNDROME_SHIFT)) & CAAM_MPECC_MP_SYNDROME_MASK)
12044
12045#define CAAM_MPECC_MP_ZERO_MASK (0x8000000U)
12046#define CAAM_MPECC_MP_ZERO_SHIFT (27U)
12051#define CAAM_MPECC_MP_ZERO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_ZERO_SHIFT)) & CAAM_MPECC_MP_ZERO_MASK)
12057#define CAAM_JDKEKR_JDKEK_MASK (0xFFFFFFFFU)
12058#define CAAM_JDKEKR_JDKEK_SHIFT (0U)
12059#define CAAM_JDKEKR_JDKEK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JDKEKR_JDKEK_SHIFT)) & CAAM_JDKEKR_JDKEK_MASK)
12062/* The count of CAAM_JDKEKR */
12063#define CAAM_JDKEKR_COUNT (8U)
12064
12068#define CAAM_TDKEKR_TDKEK_MASK (0xFFFFFFFFU)
12069#define CAAM_TDKEKR_TDKEK_SHIFT (0U)
12070#define CAAM_TDKEKR_TDKEK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_TDKEKR_TDKEK_SHIFT)) & CAAM_TDKEKR_TDKEK_MASK)
12073/* The count of CAAM_TDKEKR */
12074#define CAAM_TDKEKR_COUNT (8U)
12075
12079#define CAAM_TDSKR_TDSK_MASK (0xFFFFFFFFU)
12080#define CAAM_TDSKR_TDSK_SHIFT (0U)
12081#define CAAM_TDSKR_TDSK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_TDSKR_TDSK_SHIFT)) & CAAM_TDSKR_TDSK_MASK)
12084/* The count of CAAM_TDSKR */
12085#define CAAM_TDSKR_COUNT (8U)
12086
12090#define CAAM_SKNR_SK_NONCE_LS_MASK (0xFFFFFFFFU)
12091#define CAAM_SKNR_SK_NONCE_LS_SHIFT (0U)
12092#define CAAM_SKNR_SK_NONCE_LS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_LS_SHIFT)) & CAAM_SKNR_SK_NONCE_LS_MASK)
12093
12094#define CAAM_SKNR_SK_NONCE_MS_MASK (0x7FFF00000000U)
12095#define CAAM_SKNR_SK_NONCE_MS_SHIFT (32U)
12096#define CAAM_SKNR_SK_NONCE_MS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_MS_SHIFT)) & CAAM_SKNR_SK_NONCE_MS_MASK)
12102#define CAAM_DMA_STA_DMA0_ETIF_MASK (0x1FU)
12103#define CAAM_DMA_STA_DMA0_ETIF_SHIFT (0U)
12104#define CAAM_DMA_STA_DMA0_ETIF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ETIF_SHIFT)) & CAAM_DMA_STA_DMA0_ETIF_MASK)
12105
12106#define CAAM_DMA_STA_DMA0_ITIF_MASK (0x20U)
12107#define CAAM_DMA_STA_DMA0_ITIF_SHIFT (5U)
12108#define CAAM_DMA_STA_DMA0_ITIF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ITIF_SHIFT)) & CAAM_DMA_STA_DMA0_ITIF_MASK)
12109
12110#define CAAM_DMA_STA_DMA0_IDLE_MASK (0x80U)
12111#define CAAM_DMA_STA_DMA0_IDLE_SHIFT (7U)
12112#define CAAM_DMA_STA_DMA0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_IDLE_SHIFT)) & CAAM_DMA_STA_DMA0_IDLE_MASK)
12118#define CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK (0xFFU)
12119#define CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT (0U)
12120#define CAAM_DMA_X_AID_7_4_MAP_AID4_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK)
12121
12122#define CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK (0xFF00U)
12123#define CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT (8U)
12124#define CAAM_DMA_X_AID_7_4_MAP_AID5_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK)
12125
12126#define CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK (0xFF0000U)
12127#define CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT (16U)
12128#define CAAM_DMA_X_AID_7_4_MAP_AID6_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK)
12129
12130#define CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK (0xFF000000U)
12131#define CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT (24U)
12132#define CAAM_DMA_X_AID_7_4_MAP_AID7_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK)
12138#define CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK (0xFFU)
12139#define CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT (0U)
12140#define CAAM_DMA_X_AID_3_0_MAP_AID0_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK)
12141
12142#define CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK (0xFF00U)
12143#define CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT (8U)
12144#define CAAM_DMA_X_AID_3_0_MAP_AID1_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK)
12145
12146#define CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK (0xFF0000U)
12147#define CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT (16U)
12148#define CAAM_DMA_X_AID_3_0_MAP_AID2_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK)
12149
12150#define CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK (0xFF000000U)
12151#define CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT (24U)
12152#define CAAM_DMA_X_AID_3_0_MAP_AID3_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK)
12158#define CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK (0xFFU)
12159#define CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT (0U)
12160#define CAAM_DMA_X_AID_15_12_MAP_AID12_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK)
12161
12162#define CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK (0xFF00U)
12163#define CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT (8U)
12164#define CAAM_DMA_X_AID_15_12_MAP_AID13_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK)
12165
12166#define CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK (0xFF0000U)
12167#define CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT (16U)
12168#define CAAM_DMA_X_AID_15_12_MAP_AID14_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK)
12169
12170#define CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK (0xFF000000U)
12171#define CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT (24U)
12172#define CAAM_DMA_X_AID_15_12_MAP_AID15_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK)
12178#define CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK (0xFFU)
12179#define CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT (0U)
12180#define CAAM_DMA_X_AID_11_8_MAP_AID8_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK)
12181
12182#define CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK (0xFF00U)
12183#define CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT (8U)
12184#define CAAM_DMA_X_AID_11_8_MAP_AID9_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK)
12185
12186#define CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK (0xFF0000U)
12187#define CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT (16U)
12188#define CAAM_DMA_X_AID_11_8_MAP_AID10_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK)
12189
12190#define CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK (0xFF000000U)
12191#define CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT (24U)
12192#define CAAM_DMA_X_AID_11_8_MAP_AID11_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK)
12198#define CAAM_DMA_X_AID_15_0_EN_AID0E_MASK (0x1U)
12199#define CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT (0U)
12200#define CAAM_DMA_X_AID_15_0_EN_AID0E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID0E_MASK)
12201
12202#define CAAM_DMA_X_AID_15_0_EN_AID1E_MASK (0x2U)
12203#define CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT (1U)
12204#define CAAM_DMA_X_AID_15_0_EN_AID1E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID1E_MASK)
12205
12206#define CAAM_DMA_X_AID_15_0_EN_AID2E_MASK (0x4U)
12207#define CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT (2U)
12208#define CAAM_DMA_X_AID_15_0_EN_AID2E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID2E_MASK)
12209
12210#define CAAM_DMA_X_AID_15_0_EN_AID3E_MASK (0x8U)
12211#define CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT (3U)
12212#define CAAM_DMA_X_AID_15_0_EN_AID3E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID3E_MASK)
12213
12214#define CAAM_DMA_X_AID_15_0_EN_AID4E_MASK (0x10U)
12215#define CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT (4U)
12216#define CAAM_DMA_X_AID_15_0_EN_AID4E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID4E_MASK)
12217
12218#define CAAM_DMA_X_AID_15_0_EN_AID5E_MASK (0x20U)
12219#define CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT (5U)
12220#define CAAM_DMA_X_AID_15_0_EN_AID5E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID5E_MASK)
12221
12222#define CAAM_DMA_X_AID_15_0_EN_AID6E_MASK (0x40U)
12223#define CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT (6U)
12224#define CAAM_DMA_X_AID_15_0_EN_AID6E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID6E_MASK)
12225
12226#define CAAM_DMA_X_AID_15_0_EN_AID7E_MASK (0x80U)
12227#define CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT (7U)
12228#define CAAM_DMA_X_AID_15_0_EN_AID7E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID7E_MASK)
12229
12230#define CAAM_DMA_X_AID_15_0_EN_AID8E_MASK (0x100U)
12231#define CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT (8U)
12232#define CAAM_DMA_X_AID_15_0_EN_AID8E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID8E_MASK)
12233
12234#define CAAM_DMA_X_AID_15_0_EN_AID9E_MASK (0x200U)
12235#define CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT (9U)
12236#define CAAM_DMA_X_AID_15_0_EN_AID9E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID9E_MASK)
12237
12238#define CAAM_DMA_X_AID_15_0_EN_AID10E_MASK (0x400U)
12239#define CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT (10U)
12240#define CAAM_DMA_X_AID_15_0_EN_AID10E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID10E_MASK)
12241
12242#define CAAM_DMA_X_AID_15_0_EN_AID11E_MASK (0x800U)
12243#define CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT (11U)
12244#define CAAM_DMA_X_AID_15_0_EN_AID11E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID11E_MASK)
12245
12246#define CAAM_DMA_X_AID_15_0_EN_AID12E_MASK (0x1000U)
12247#define CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT (12U)
12248#define CAAM_DMA_X_AID_15_0_EN_AID12E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID12E_MASK)
12249
12250#define CAAM_DMA_X_AID_15_0_EN_AID13E_MASK (0x2000U)
12251#define CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT (13U)
12252#define CAAM_DMA_X_AID_15_0_EN_AID13E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID13E_MASK)
12253
12254#define CAAM_DMA_X_AID_15_0_EN_AID14E_MASK (0x4000U)
12255#define CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT (14U)
12256#define CAAM_DMA_X_AID_15_0_EN_AID14E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID14E_MASK)
12257
12258#define CAAM_DMA_X_AID_15_0_EN_AID15E_MASK (0x8000U)
12259#define CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT (15U)
12260#define CAAM_DMA_X_AID_15_0_EN_AID15E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID15E_MASK)
12266#define CAAM_DMA_X_ARTC_CTL_ART_MASK (0xFFFU)
12267#define CAAM_DMA_X_ARTC_CTL_ART_SHIFT (0U)
12268#define CAAM_DMA_X_ARTC_CTL_ART(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ART_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ART_MASK)
12269
12270#define CAAM_DMA_X_ARTC_CTL_ARL_MASK (0xFFF0000U)
12271#define CAAM_DMA_X_ARTC_CTL_ARL_SHIFT (16U)
12272#define CAAM_DMA_X_ARTC_CTL_ARL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARL_MASK)
12273
12274#define CAAM_DMA_X_ARTC_CTL_ARTL_MASK (0x10000000U)
12275#define CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT (28U)
12276#define CAAM_DMA_X_ARTC_CTL_ARTL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTL_MASK)
12277
12278#define CAAM_DMA_X_ARTC_CTL_ARTT_MASK (0x20000000U)
12279#define CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT (29U)
12280#define CAAM_DMA_X_ARTC_CTL_ARTT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTT_MASK)
12281
12282#define CAAM_DMA_X_ARTC_CTL_ARCT_MASK (0x40000000U)
12283#define CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT (30U)
12284#define CAAM_DMA_X_ARTC_CTL_ARCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARCT_MASK)
12285
12286#define CAAM_DMA_X_ARTC_CTL_ARTCE_MASK (0x80000000U)
12287#define CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT (31U)
12288#define CAAM_DMA_X_ARTC_CTL_ARTCE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTCE_MASK)
12294#define CAAM_DMA_X_ARTC_LC_ARLC_MASK (0xFFFFFU)
12295#define CAAM_DMA_X_ARTC_LC_ARLC_SHIFT (0U)
12296#define CAAM_DMA_X_ARTC_LC_ARLC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LC_ARLC_SHIFT)) & CAAM_DMA_X_ARTC_LC_ARLC_MASK)
12302#define CAAM_DMA_X_ARTC_SC_ARSC_MASK (0xFFFFFU)
12303#define CAAM_DMA_X_ARTC_SC_ARSC_SHIFT (0U)
12304#define CAAM_DMA_X_ARTC_SC_ARSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_SC_ARSC_SHIFT)) & CAAM_DMA_X_ARTC_SC_ARSC_MASK)
12310#define CAAM_DMA_X_ARTC_LAT_SARL_MASK (0xFFFFFFFFU)
12311#define CAAM_DMA_X_ARTC_LAT_SARL_SHIFT (0U)
12312#define CAAM_DMA_X_ARTC_LAT_SARL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LAT_SARL_SHIFT)) & CAAM_DMA_X_ARTC_LAT_SARL_MASK)
12318#define CAAM_DMA_X_AWTC_CTL_AWT_MASK (0xFFFU)
12319#define CAAM_DMA_X_AWTC_CTL_AWT_SHIFT (0U)
12320#define CAAM_DMA_X_AWTC_CTL_AWT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWT_MASK)
12321
12322#define CAAM_DMA_X_AWTC_CTL_AWL_MASK (0xFFF0000U)
12323#define CAAM_DMA_X_AWTC_CTL_AWL_SHIFT (16U)
12324#define CAAM_DMA_X_AWTC_CTL_AWL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWL_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWL_MASK)
12325
12326#define CAAM_DMA_X_AWTC_CTL_AWTT_MASK (0x20000000U)
12327#define CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT (29U)
12328#define CAAM_DMA_X_AWTC_CTL_AWTT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTT_MASK)
12329
12330#define CAAM_DMA_X_AWTC_CTL_AWCT_MASK (0x40000000U)
12331#define CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT (30U)
12332#define CAAM_DMA_X_AWTC_CTL_AWCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWCT_MASK)
12333
12334#define CAAM_DMA_X_AWTC_CTL_AWTCE_MASK (0x80000000U)
12335#define CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT (31U)
12336#define CAAM_DMA_X_AWTC_CTL_AWTCE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTCE_MASK)
12342#define CAAM_DMA_X_AWTC_LC_AWLC_MASK (0xFFFFFU)
12343#define CAAM_DMA_X_AWTC_LC_AWLC_SHIFT (0U)
12344#define CAAM_DMA_X_AWTC_LC_AWLC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LC_AWLC_SHIFT)) & CAAM_DMA_X_AWTC_LC_AWLC_MASK)
12350#define CAAM_DMA_X_AWTC_SC_AWSC_MASK (0xFFFFFU)
12351#define CAAM_DMA_X_AWTC_SC_AWSC_SHIFT (0U)
12352#define CAAM_DMA_X_AWTC_SC_AWSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_SC_AWSC_SHIFT)) & CAAM_DMA_X_AWTC_SC_AWSC_MASK)
12358#define CAAM_DMA_X_AWTC_LAT_SAWL_MASK (0xFFFFFFFFU)
12359#define CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT (0U)
12360#define CAAM_DMA_X_AWTC_LAT_SAWL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT)) & CAAM_DMA_X_AWTC_LAT_SAWL_MASK)
12366#define CAAM_RTMCTL_SAMP_MODE_MASK (0x3U)
12367#define CAAM_RTMCTL_SAMP_MODE_SHIFT (0U)
12374#define CAAM_RTMCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_SAMP_MODE_SHIFT)) & CAAM_RTMCTL_SAMP_MODE_MASK)
12375
12376#define CAAM_RTMCTL_OSC_DIV_MASK (0xCU)
12377#define CAAM_RTMCTL_OSC_DIV_SHIFT (2U)
12384#define CAAM_RTMCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_OSC_DIV_SHIFT)) & CAAM_RTMCTL_OSC_DIV_MASK)
12385
12386#define CAAM_RTMCTL_CLK_OUT_EN_MASK (0x10U)
12387#define CAAM_RTMCTL_CLK_OUT_EN_SHIFT (4U)
12388#define CAAM_RTMCTL_CLK_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_CLK_OUT_EN_SHIFT)) & CAAM_RTMCTL_CLK_OUT_EN_MASK)
12389
12390#define CAAM_RTMCTL_TRNG_ACC_MASK (0x20U)
12391#define CAAM_RTMCTL_TRNG_ACC_SHIFT (5U)
12392#define CAAM_RTMCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TRNG_ACC_SHIFT)) & CAAM_RTMCTL_TRNG_ACC_MASK)
12393
12394#define CAAM_RTMCTL_RST_DEF_MASK (0x40U)
12395#define CAAM_RTMCTL_RST_DEF_SHIFT (6U)
12396#define CAAM_RTMCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_RST_DEF_SHIFT)) & CAAM_RTMCTL_RST_DEF_MASK)
12397
12398#define CAAM_RTMCTL_FORCE_SYSCLK_MASK (0x80U)
12399#define CAAM_RTMCTL_FORCE_SYSCLK_SHIFT (7U)
12400#define CAAM_RTMCTL_FORCE_SYSCLK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FORCE_SYSCLK_SHIFT)) & CAAM_RTMCTL_FORCE_SYSCLK_MASK)
12401
12402#define CAAM_RTMCTL_FCT_FAIL_MASK (0x100U)
12403#define CAAM_RTMCTL_FCT_FAIL_SHIFT (8U)
12404#define CAAM_RTMCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_FAIL_SHIFT)) & CAAM_RTMCTL_FCT_FAIL_MASK)
12405
12406#define CAAM_RTMCTL_FCT_VAL_MASK (0x200U)
12407#define CAAM_RTMCTL_FCT_VAL_SHIFT (9U)
12408#define CAAM_RTMCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_VAL_SHIFT)) & CAAM_RTMCTL_FCT_VAL_MASK)
12409
12410#define CAAM_RTMCTL_ENT_VAL_MASK (0x400U)
12411#define CAAM_RTMCTL_ENT_VAL_SHIFT (10U)
12412#define CAAM_RTMCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ENT_VAL_SHIFT)) & CAAM_RTMCTL_ENT_VAL_MASK)
12413
12414#define CAAM_RTMCTL_TST_OUT_MASK (0x800U)
12415#define CAAM_RTMCTL_TST_OUT_SHIFT (11U)
12416#define CAAM_RTMCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TST_OUT_SHIFT)) & CAAM_RTMCTL_TST_OUT_MASK)
12417
12418#define CAAM_RTMCTL_ERR_MASK (0x1000U)
12419#define CAAM_RTMCTL_ERR_SHIFT (12U)
12420#define CAAM_RTMCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ERR_SHIFT)) & CAAM_RTMCTL_ERR_MASK)
12421
12422#define CAAM_RTMCTL_TSTOP_OK_MASK (0x2000U)
12423#define CAAM_RTMCTL_TSTOP_OK_SHIFT (13U)
12424#define CAAM_RTMCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TSTOP_OK_SHIFT)) & CAAM_RTMCTL_TSTOP_OK_MASK)
12425
12426#define CAAM_RTMCTL_PRGM_MASK (0x10000U)
12427#define CAAM_RTMCTL_PRGM_SHIFT (16U)
12428#define CAAM_RTMCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_PRGM_SHIFT)) & CAAM_RTMCTL_PRGM_MASK)
12434#define CAAM_RTSCMISC_LRUN_MAX_MASK (0xFFU)
12435#define CAAM_RTSCMISC_LRUN_MAX_SHIFT (0U)
12436#define CAAM_RTSCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_LRUN_MAX_SHIFT)) & CAAM_RTSCMISC_LRUN_MAX_MASK)
12437
12438#define CAAM_RTSCMISC_RTY_CNT_MASK (0xF0000U)
12439#define CAAM_RTSCMISC_RTY_CNT_SHIFT (16U)
12440#define CAAM_RTSCMISC_RTY_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_RTY_CNT_SHIFT)) & CAAM_RTSCMISC_RTY_CNT_MASK)
12446#define CAAM_RTPKRRNG_PKR_RNG_MASK (0xFFFFU)
12447#define CAAM_RTPKRRNG_PKR_RNG_SHIFT (0U)
12448#define CAAM_RTPKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRRNG_PKR_RNG_SHIFT)) & CAAM_RTPKRRNG_PKR_RNG_MASK)
12454#define CAAM_RTPKRMAX_PKR_MAX_MASK (0xFFFFFFU)
12455#define CAAM_RTPKRMAX_PKR_MAX_SHIFT (0U)
12456#define CAAM_RTPKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRMAX_PKR_MAX_SHIFT)) & CAAM_RTPKRMAX_PKR_MAX_MASK)
12462#define CAAM_RTPKRSQ_PKR_SQ_MASK (0xFFFFFFU)
12463#define CAAM_RTPKRSQ_PKR_SQ_SHIFT (0U)
12464#define CAAM_RTPKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRSQ_PKR_SQ_SHIFT)) & CAAM_RTPKRSQ_PKR_SQ_MASK)
12470#define CAAM_RTSDCTL_SAMP_SIZE_MASK (0xFFFFU)
12471#define CAAM_RTSDCTL_SAMP_SIZE_SHIFT (0U)
12472#define CAAM_RTSDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_SAMP_SIZE_SHIFT)) & CAAM_RTSDCTL_SAMP_SIZE_MASK)
12473
12474#define CAAM_RTSDCTL_ENT_DLY_MASK (0xFFFF0000U)
12475#define CAAM_RTSDCTL_ENT_DLY_SHIFT (16U)
12476#define CAAM_RTSDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_ENT_DLY_SHIFT)) & CAAM_RTSDCTL_ENT_DLY_MASK)
12482#define CAAM_RTSBLIM_SB_LIM_MASK (0x3FFU)
12483#define CAAM_RTSBLIM_SB_LIM_SHIFT (0U)
12484#define CAAM_RTSBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSBLIM_SB_LIM_SHIFT)) & CAAM_RTSBLIM_SB_LIM_MASK)
12490#define CAAM_RTTOTSAM_TOT_SAM_MASK (0xFFFFFU)
12491#define CAAM_RTTOTSAM_TOT_SAM_SHIFT (0U)
12492#define CAAM_RTTOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTTOTSAM_TOT_SAM_SHIFT)) & CAAM_RTTOTSAM_TOT_SAM_MASK)
12498#define CAAM_RTFRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
12499#define CAAM_RTFRQMIN_FRQ_MIN_SHIFT (0U)
12500#define CAAM_RTFRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMIN_FRQ_MIN_SHIFT)) & CAAM_RTFRQMIN_FRQ_MIN_MASK)
12506#define CAAM_RTFRQCNT_FRQ_CNT_MASK (0x3FFFFFU)
12507#define CAAM_RTFRQCNT_FRQ_CNT_SHIFT (0U)
12508#define CAAM_RTFRQCNT_FRQ_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQCNT_FRQ_CNT_SHIFT)) & CAAM_RTFRQCNT_FRQ_CNT_MASK)
12514#define CAAM_RTSCMC_MONO_CNT_MASK (0xFFFFU)
12515#define CAAM_RTSCMC_MONO_CNT_SHIFT (0U)
12516#define CAAM_RTSCMC_MONO_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMC_MONO_CNT_SHIFT)) & CAAM_RTSCMC_MONO_CNT_MASK)
12522#define CAAM_RTSCR1C_R1_0_COUNT_MASK (0x7FFFU)
12523#define CAAM_RTSCR1C_R1_0_COUNT_SHIFT (0U)
12524#define CAAM_RTSCR1C_R1_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_0_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_0_COUNT_MASK)
12525
12526#define CAAM_RTSCR1C_R1_1_COUNT_MASK (0x7FFF0000U)
12527#define CAAM_RTSCR1C_R1_1_COUNT_SHIFT (16U)
12528#define CAAM_RTSCR1C_R1_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_1_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_1_COUNT_MASK)
12534#define CAAM_RTSCR2C_R2_0_COUNT_MASK (0x3FFFU)
12535#define CAAM_RTSCR2C_R2_0_COUNT_SHIFT (0U)
12536#define CAAM_RTSCR2C_R2_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_0_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_0_COUNT_MASK)
12537
12538#define CAAM_RTSCR2C_R2_1_COUNT_MASK (0x3FFF0000U)
12539#define CAAM_RTSCR2C_R2_1_COUNT_SHIFT (16U)
12540#define CAAM_RTSCR2C_R2_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_1_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_1_COUNT_MASK)
12546#define CAAM_RTSCR3C_R3_0_COUNT_MASK (0x1FFFU)
12547#define CAAM_RTSCR3C_R3_0_COUNT_SHIFT (0U)
12548#define CAAM_RTSCR3C_R3_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_0_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_0_COUNT_MASK)
12549
12550#define CAAM_RTSCR3C_R3_1_COUNT_MASK (0x1FFF0000U)
12551#define CAAM_RTSCR3C_R3_1_COUNT_SHIFT (16U)
12552#define CAAM_RTSCR3C_R3_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_1_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_1_COUNT_MASK)
12558#define CAAM_RTSCR4C_R4_0_COUNT_MASK (0xFFFU)
12559#define CAAM_RTSCR4C_R4_0_COUNT_SHIFT (0U)
12560#define CAAM_RTSCR4C_R4_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_0_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_0_COUNT_MASK)
12561
12562#define CAAM_RTSCR4C_R4_1_COUNT_MASK (0xFFF0000U)
12563#define CAAM_RTSCR4C_R4_1_COUNT_SHIFT (16U)
12564#define CAAM_RTSCR4C_R4_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_1_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_1_COUNT_MASK)
12570#define CAAM_RTSCR5C_R5_0_COUNT_MASK (0x7FFU)
12571#define CAAM_RTSCR5C_R5_0_COUNT_SHIFT (0U)
12572#define CAAM_RTSCR5C_R5_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_0_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_0_COUNT_MASK)
12573
12574#define CAAM_RTSCR5C_R5_1_COUNT_MASK (0x7FF0000U)
12575#define CAAM_RTSCR5C_R5_1_COUNT_SHIFT (16U)
12576#define CAAM_RTSCR5C_R5_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_1_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_1_COUNT_MASK)
12582#define CAAM_RTSCR6PC_R6P_0_COUNT_MASK (0x7FFU)
12583#define CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT (0U)
12584#define CAAM_RTSCR6PC_R6P_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_0_COUNT_MASK)
12585
12586#define CAAM_RTSCR6PC_R6P_1_COUNT_MASK (0x7FF0000U)
12587#define CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT (16U)
12588#define CAAM_RTSCR6PC_R6P_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_1_COUNT_MASK)
12594#define CAAM_RTFRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
12595#define CAAM_RTFRQMAX_FRQ_MAX_SHIFT (0U)
12596#define CAAM_RTFRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMAX_FRQ_MAX_SHIFT)) & CAAM_RTFRQMAX_FRQ_MAX_MASK)
12602#define CAAM_RTSCML_MONO_MAX_MASK (0xFFFFU)
12603#define CAAM_RTSCML_MONO_MAX_SHIFT (0U)
12604#define CAAM_RTSCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_MAX_SHIFT)) & CAAM_RTSCML_MONO_MAX_MASK)
12605
12606#define CAAM_RTSCML_MONO_RNG_MASK (0xFFFF0000U)
12607#define CAAM_RTSCML_MONO_RNG_SHIFT (16U)
12608#define CAAM_RTSCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_RNG_SHIFT)) & CAAM_RTSCML_MONO_RNG_MASK)
12614#define CAAM_RTSCR1L_RUN1_MAX_MASK (0x7FFFU)
12615#define CAAM_RTSCR1L_RUN1_MAX_SHIFT (0U)
12616#define CAAM_RTSCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_MAX_SHIFT)) & CAAM_RTSCR1L_RUN1_MAX_MASK)
12617
12618#define CAAM_RTSCR1L_RUN1_RNG_MASK (0x7FFF0000U)
12619#define CAAM_RTSCR1L_RUN1_RNG_SHIFT (16U)
12620#define CAAM_RTSCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_RNG_SHIFT)) & CAAM_RTSCR1L_RUN1_RNG_MASK)
12626#define CAAM_RTSCR2L_RUN2_MAX_MASK (0x3FFFU)
12627#define CAAM_RTSCR2L_RUN2_MAX_SHIFT (0U)
12628#define CAAM_RTSCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_MAX_SHIFT)) & CAAM_RTSCR2L_RUN2_MAX_MASK)
12629
12630#define CAAM_RTSCR2L_RUN2_RNG_MASK (0x3FFF0000U)
12631#define CAAM_RTSCR2L_RUN2_RNG_SHIFT (16U)
12632#define CAAM_RTSCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_RNG_SHIFT)) & CAAM_RTSCR2L_RUN2_RNG_MASK)
12638#define CAAM_RTSCR3L_RUN3_MAX_MASK (0x1FFFU)
12639#define CAAM_RTSCR3L_RUN3_MAX_SHIFT (0U)
12640#define CAAM_RTSCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_MAX_SHIFT)) & CAAM_RTSCR3L_RUN3_MAX_MASK)
12641
12642#define CAAM_RTSCR3L_RUN3_RNG_MASK (0x1FFF0000U)
12643#define CAAM_RTSCR3L_RUN3_RNG_SHIFT (16U)
12644#define CAAM_RTSCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_RNG_SHIFT)) & CAAM_RTSCR3L_RUN3_RNG_MASK)
12650#define CAAM_RTSCR4L_RUN4_MAX_MASK (0xFFFU)
12651#define CAAM_RTSCR4L_RUN4_MAX_SHIFT (0U)
12652#define CAAM_RTSCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_MAX_SHIFT)) & CAAM_RTSCR4L_RUN4_MAX_MASK)
12653
12654#define CAAM_RTSCR4L_RUN4_RNG_MASK (0xFFF0000U)
12655#define CAAM_RTSCR4L_RUN4_RNG_SHIFT (16U)
12656#define CAAM_RTSCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_RNG_SHIFT)) & CAAM_RTSCR4L_RUN4_RNG_MASK)
12662#define CAAM_RTSCR5L_RUN5_MAX_MASK (0x7FFU)
12663#define CAAM_RTSCR5L_RUN5_MAX_SHIFT (0U)
12664#define CAAM_RTSCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_MAX_SHIFT)) & CAAM_RTSCR5L_RUN5_MAX_MASK)
12665
12666#define CAAM_RTSCR5L_RUN5_RNG_MASK (0x7FF0000U)
12667#define CAAM_RTSCR5L_RUN5_RNG_SHIFT (16U)
12668#define CAAM_RTSCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_RNG_SHIFT)) & CAAM_RTSCR5L_RUN5_RNG_MASK)
12674#define CAAM_RTSCR6PL_RUN6P_MAX_MASK (0x7FFU)
12675#define CAAM_RTSCR6PL_RUN6P_MAX_SHIFT (0U)
12676#define CAAM_RTSCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_MAX_SHIFT)) & CAAM_RTSCR6PL_RUN6P_MAX_MASK)
12677
12678#define CAAM_RTSCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
12679#define CAAM_RTSCR6PL_RUN6P_RNG_SHIFT (16U)
12680#define CAAM_RTSCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_RNG_SHIFT)) & CAAM_RTSCR6PL_RUN6P_RNG_MASK)
12686#define CAAM_RTSTATUS_F1BR0TF_MASK (0x1U)
12687#define CAAM_RTSTATUS_F1BR0TF_SHIFT (0U)
12688#define CAAM_RTSTATUS_F1BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR0TF_SHIFT)) & CAAM_RTSTATUS_F1BR0TF_MASK)
12689
12690#define CAAM_RTSTATUS_F1BR1TF_MASK (0x2U)
12691#define CAAM_RTSTATUS_F1BR1TF_SHIFT (1U)
12692#define CAAM_RTSTATUS_F1BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR1TF_SHIFT)) & CAAM_RTSTATUS_F1BR1TF_MASK)
12693
12694#define CAAM_RTSTATUS_F2BR0TF_MASK (0x4U)
12695#define CAAM_RTSTATUS_F2BR0TF_SHIFT (2U)
12696#define CAAM_RTSTATUS_F2BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR0TF_SHIFT)) & CAAM_RTSTATUS_F2BR0TF_MASK)
12697
12698#define CAAM_RTSTATUS_F2BR1TF_MASK (0x8U)
12699#define CAAM_RTSTATUS_F2BR1TF_SHIFT (3U)
12700#define CAAM_RTSTATUS_F2BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR1TF_SHIFT)) & CAAM_RTSTATUS_F2BR1TF_MASK)
12701
12702#define CAAM_RTSTATUS_F3BR01TF_MASK (0x10U)
12703#define CAAM_RTSTATUS_F3BR01TF_SHIFT (4U)
12704#define CAAM_RTSTATUS_F3BR01TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR01TF_SHIFT)) & CAAM_RTSTATUS_F3BR01TF_MASK)
12705
12706#define CAAM_RTSTATUS_F3BR1TF_MASK (0x20U)
12707#define CAAM_RTSTATUS_F3BR1TF_SHIFT (5U)
12708#define CAAM_RTSTATUS_F3BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR1TF_SHIFT)) & CAAM_RTSTATUS_F3BR1TF_MASK)
12709
12710#define CAAM_RTSTATUS_F4BR0TF_MASK (0x40U)
12711#define CAAM_RTSTATUS_F4BR0TF_SHIFT (6U)
12712#define CAAM_RTSTATUS_F4BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR0TF_SHIFT)) & CAAM_RTSTATUS_F4BR0TF_MASK)
12713
12714#define CAAM_RTSTATUS_F4BR1TF_MASK (0x80U)
12715#define CAAM_RTSTATUS_F4BR1TF_SHIFT (7U)
12716#define CAAM_RTSTATUS_F4BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR1TF_SHIFT)) & CAAM_RTSTATUS_F4BR1TF_MASK)
12717
12718#define CAAM_RTSTATUS_F5BR0TF_MASK (0x100U)
12719#define CAAM_RTSTATUS_F5BR0TF_SHIFT (8U)
12720#define CAAM_RTSTATUS_F5BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR0TF_SHIFT)) & CAAM_RTSTATUS_F5BR0TF_MASK)
12721
12722#define CAAM_RTSTATUS_F5BR1TF_MASK (0x200U)
12723#define CAAM_RTSTATUS_F5BR1TF_SHIFT (9U)
12724#define CAAM_RTSTATUS_F5BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR1TF_SHIFT)) & CAAM_RTSTATUS_F5BR1TF_MASK)
12725
12726#define CAAM_RTSTATUS_F6PBR0TF_MASK (0x400U)
12727#define CAAM_RTSTATUS_F6PBR0TF_SHIFT (10U)
12728#define CAAM_RTSTATUS_F6PBR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR0TF_SHIFT)) & CAAM_RTSTATUS_F6PBR0TF_MASK)
12729
12730#define CAAM_RTSTATUS_F6PBR1TF_MASK (0x800U)
12731#define CAAM_RTSTATUS_F6PBR1TF_SHIFT (11U)
12732#define CAAM_RTSTATUS_F6PBR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR1TF_SHIFT)) & CAAM_RTSTATUS_F6PBR1TF_MASK)
12733
12734#define CAAM_RTSTATUS_FSBTF_MASK (0x1000U)
12735#define CAAM_RTSTATUS_FSBTF_SHIFT (12U)
12736#define CAAM_RTSTATUS_FSBTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FSBTF_SHIFT)) & CAAM_RTSTATUS_FSBTF_MASK)
12737
12738#define CAAM_RTSTATUS_FLRTF_MASK (0x2000U)
12739#define CAAM_RTSTATUS_FLRTF_SHIFT (13U)
12740#define CAAM_RTSTATUS_FLRTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FLRTF_SHIFT)) & CAAM_RTSTATUS_FLRTF_MASK)
12741
12742#define CAAM_RTSTATUS_FPTF_MASK (0x4000U)
12743#define CAAM_RTSTATUS_FPTF_SHIFT (14U)
12744#define CAAM_RTSTATUS_FPTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FPTF_SHIFT)) & CAAM_RTSTATUS_FPTF_MASK)
12745
12746#define CAAM_RTSTATUS_FMBTF_MASK (0x8000U)
12747#define CAAM_RTSTATUS_FMBTF_SHIFT (15U)
12748#define CAAM_RTSTATUS_FMBTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FMBTF_SHIFT)) & CAAM_RTSTATUS_FMBTF_MASK)
12749
12750#define CAAM_RTSTATUS_RETRY_COUNT_MASK (0xF0000U)
12751#define CAAM_RTSTATUS_RETRY_COUNT_SHIFT (16U)
12752#define CAAM_RTSTATUS_RETRY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_RETRY_COUNT_SHIFT)) & CAAM_RTSTATUS_RETRY_COUNT_MASK)
12758#define CAAM_RTENT_ENT_MASK (0xFFFFFFFFU)
12759#define CAAM_RTENT_ENT_SHIFT (0U)
12760#define CAAM_RTENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTENT_ENT_SHIFT)) & CAAM_RTENT_ENT_MASK)
12763/* The count of CAAM_RTENT */
12764#define CAAM_RTENT_COUNT (16U)
12765
12769#define CAAM_RTPKRCNT10_PKR_0_CNT_MASK (0xFFFFU)
12770#define CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT (0U)
12771#define CAAM_RTPKRCNT10_PKR_0_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_0_CNT_MASK)
12772
12773#define CAAM_RTPKRCNT10_PKR_1_CNT_MASK (0xFFFF0000U)
12774#define CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT (16U)
12775#define CAAM_RTPKRCNT10_PKR_1_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_1_CNT_MASK)
12781#define CAAM_RTPKRCNT32_PKR_2_CNT_MASK (0xFFFFU)
12782#define CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT (0U)
12783#define CAAM_RTPKRCNT32_PKR_2_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_2_CNT_MASK)
12784
12785#define CAAM_RTPKRCNT32_PKR_3_CNT_MASK (0xFFFF0000U)
12786#define CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT (16U)
12787#define CAAM_RTPKRCNT32_PKR_3_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_3_CNT_MASK)
12793#define CAAM_RTPKRCNT54_PKR_4_CNT_MASK (0xFFFFU)
12794#define CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT (0U)
12795#define CAAM_RTPKRCNT54_PKR_4_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_4_CNT_MASK)
12796
12797#define CAAM_RTPKRCNT54_PKR_5_CNT_MASK (0xFFFF0000U)
12798#define CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT (16U)
12799#define CAAM_RTPKRCNT54_PKR_5_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_5_CNT_MASK)
12805#define CAAM_RTPKRCNT76_PKR_6_CNT_MASK (0xFFFFU)
12806#define CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT (0U)
12807#define CAAM_RTPKRCNT76_PKR_6_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_6_CNT_MASK)
12808
12809#define CAAM_RTPKRCNT76_PKR_7_CNT_MASK (0xFFFF0000U)
12810#define CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT (16U)
12811#define CAAM_RTPKRCNT76_PKR_7_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_7_CNT_MASK)
12817#define CAAM_RTPKRCNT98_PKR_8_CNT_MASK (0xFFFFU)
12818#define CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT (0U)
12819#define CAAM_RTPKRCNT98_PKR_8_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_8_CNT_MASK)
12820
12821#define CAAM_RTPKRCNT98_PKR_9_CNT_MASK (0xFFFF0000U)
12822#define CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT (16U)
12823#define CAAM_RTPKRCNT98_PKR_9_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_9_CNT_MASK)
12829#define CAAM_RTPKRCNTBA_PKR_A_CNT_MASK (0xFFFFU)
12830#define CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT (0U)
12831#define CAAM_RTPKRCNTBA_PKR_A_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_A_CNT_MASK)
12832
12833#define CAAM_RTPKRCNTBA_PKR_B_CNT_MASK (0xFFFF0000U)
12834#define CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT (16U)
12835#define CAAM_RTPKRCNTBA_PKR_B_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_B_CNT_MASK)
12841#define CAAM_RTPKRCNTDC_PKR_C_CNT_MASK (0xFFFFU)
12842#define CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT (0U)
12843#define CAAM_RTPKRCNTDC_PKR_C_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_C_CNT_MASK)
12844
12845#define CAAM_RTPKRCNTDC_PKR_D_CNT_MASK (0xFFFF0000U)
12846#define CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT (16U)
12847#define CAAM_RTPKRCNTDC_PKR_D_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_D_CNT_MASK)
12853#define CAAM_RTPKRCNTFE_PKR_E_CNT_MASK (0xFFFFU)
12854#define CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT (0U)
12855#define CAAM_RTPKRCNTFE_PKR_E_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_E_CNT_MASK)
12856
12857#define CAAM_RTPKRCNTFE_PKR_F_CNT_MASK (0xFFFF0000U)
12858#define CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT (16U)
12859#define CAAM_RTPKRCNTFE_PKR_F_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_F_CNT_MASK)
12865#define CAAM_RDSTA_IF0_MASK (0x1U)
12866#define CAAM_RDSTA_IF0_SHIFT (0U)
12867#define CAAM_RDSTA_IF0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF0_SHIFT)) & CAAM_RDSTA_IF0_MASK)
12868
12869#define CAAM_RDSTA_IF1_MASK (0x2U)
12870#define CAAM_RDSTA_IF1_SHIFT (1U)
12871#define CAAM_RDSTA_IF1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF1_SHIFT)) & CAAM_RDSTA_IF1_MASK)
12872
12873#define CAAM_RDSTA_PR0_MASK (0x10U)
12874#define CAAM_RDSTA_PR0_SHIFT (4U)
12875#define CAAM_RDSTA_PR0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR0_SHIFT)) & CAAM_RDSTA_PR0_MASK)
12876
12877#define CAAM_RDSTA_PR1_MASK (0x20U)
12878#define CAAM_RDSTA_PR1_SHIFT (5U)
12879#define CAAM_RDSTA_PR1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR1_SHIFT)) & CAAM_RDSTA_PR1_MASK)
12880
12881#define CAAM_RDSTA_TF0_MASK (0x100U)
12882#define CAAM_RDSTA_TF0_SHIFT (8U)
12883#define CAAM_RDSTA_TF0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF0_SHIFT)) & CAAM_RDSTA_TF0_MASK)
12884
12885#define CAAM_RDSTA_TF1_MASK (0x200U)
12886#define CAAM_RDSTA_TF1_SHIFT (9U)
12887#define CAAM_RDSTA_TF1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF1_SHIFT)) & CAAM_RDSTA_TF1_MASK)
12888
12889#define CAAM_RDSTA_ERRCODE_MASK (0xF0000U)
12890#define CAAM_RDSTA_ERRCODE_SHIFT (16U)
12891#define CAAM_RDSTA_ERRCODE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_ERRCODE_SHIFT)) & CAAM_RDSTA_ERRCODE_MASK)
12892
12893#define CAAM_RDSTA_CE_MASK (0x100000U)
12894#define CAAM_RDSTA_CE_SHIFT (20U)
12895#define CAAM_RDSTA_CE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_CE_SHIFT)) & CAAM_RDSTA_CE_MASK)
12896
12897#define CAAM_RDSTA_SKVN_MASK (0x40000000U)
12898#define CAAM_RDSTA_SKVN_SHIFT (30U)
12899#define CAAM_RDSTA_SKVN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVN_SHIFT)) & CAAM_RDSTA_SKVN_MASK)
12900
12901#define CAAM_RDSTA_SKVT_MASK (0x80000000U)
12902#define CAAM_RDSTA_SKVT_SHIFT (31U)
12903#define CAAM_RDSTA_SKVT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVT_SHIFT)) & CAAM_RDSTA_SKVT_MASK)
12909#define CAAM_RDINT0_RESINT0_MASK (0xFFFFFFFFU)
12910#define CAAM_RDINT0_RESINT0_SHIFT (0U)
12911#define CAAM_RDINT0_RESINT0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT0_RESINT0_SHIFT)) & CAAM_RDINT0_RESINT0_MASK)
12917#define CAAM_RDINT1_RESINT1_MASK (0xFFFFFFFFU)
12918#define CAAM_RDINT1_RESINT1_SHIFT (0U)
12919#define CAAM_RDINT1_RESINT1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT1_RESINT1_SHIFT)) & CAAM_RDINT1_RESINT1_MASK)
12925#define CAAM_RDHCNTL_HD_MASK (0x1U)
12926#define CAAM_RDHCNTL_HD_SHIFT (0U)
12927#define CAAM_RDHCNTL_HD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HD_SHIFT)) & CAAM_RDHCNTL_HD_MASK)
12928
12929#define CAAM_RDHCNTL_HB_MASK (0x2U)
12930#define CAAM_RDHCNTL_HB_SHIFT (1U)
12931#define CAAM_RDHCNTL_HB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HB_SHIFT)) & CAAM_RDHCNTL_HB_MASK)
12932
12933#define CAAM_RDHCNTL_HI_MASK (0x4U)
12934#define CAAM_RDHCNTL_HI_SHIFT (2U)
12935#define CAAM_RDHCNTL_HI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HI_SHIFT)) & CAAM_RDHCNTL_HI_MASK)
12936
12937#define CAAM_RDHCNTL_HTM_MASK (0x8U)
12938#define CAAM_RDHCNTL_HTM_SHIFT (3U)
12939#define CAAM_RDHCNTL_HTM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTM_SHIFT)) & CAAM_RDHCNTL_HTM_MASK)
12940
12941#define CAAM_RDHCNTL_HTC_MASK (0x10U)
12942#define CAAM_RDHCNTL_HTC_SHIFT (4U)
12943#define CAAM_RDHCNTL_HTC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTC_SHIFT)) & CAAM_RDHCNTL_HTC_MASK)
12949#define CAAM_RDHDIG_HASHMD_MASK (0xFFFFFFFFU)
12950#define CAAM_RDHDIG_HASHMD_SHIFT (0U)
12951#define CAAM_RDHDIG_HASHMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHDIG_HASHMD_SHIFT)) & CAAM_RDHDIG_HASHMD_MASK)
12957#define CAAM_RDHBUF_HASHBUF_MASK (0xFFFFFFFFU)
12958#define CAAM_RDHBUF_HASHBUF_SHIFT (0U)
12959#define CAAM_RDHBUF_HASHBUF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHBUF_HASHBUF_SHIFT)) & CAAM_RDHBUF_HASHBUF_MASK)
12965#define CAAM_PX_SDID_PG0_SDID_MASK (0xFFFFU)
12966#define CAAM_PX_SDID_PG0_SDID_SHIFT (0U)
12967#define CAAM_PX_SDID_PG0_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_PG0_SDID_SHIFT)) & CAAM_PX_SDID_PG0_SDID_MASK)
12970/* The count of CAAM_PX_SDID_PG0 */
12971#define CAAM_PX_SDID_PG0_COUNT (16U)
12972
12976#define CAAM_PX_SMAPR_PG0_G1_READ_MASK (0x1U)
12977#define CAAM_PX_SMAPR_PG0_G1_READ_SHIFT (0U)
12985#define CAAM_PX_SMAPR_PG0_G1_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_READ_MASK)
12986
12987#define CAAM_PX_SMAPR_PG0_G1_WRITE_MASK (0x2U)
12988#define CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT (1U)
12995#define CAAM_PX_SMAPR_PG0_G1_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_WRITE_MASK)
12996
12997#define CAAM_PX_SMAPR_PG0_G1_TDO_MASK (0x4U)
12998#define CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT (2U)
13005#define CAAM_PX_SMAPR_PG0_G1_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_TDO_MASK)
13006
13007#define CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK (0x8U)
13008#define CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT (3U)
13013#define CAAM_PX_SMAPR_PG0_G1_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK)
13014
13015#define CAAM_PX_SMAPR_PG0_G2_READ_MASK (0x10U)
13016#define CAAM_PX_SMAPR_PG0_G2_READ_SHIFT (4U)
13024#define CAAM_PX_SMAPR_PG0_G2_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_READ_MASK)
13025
13026#define CAAM_PX_SMAPR_PG0_G2_WRITE_MASK (0x20U)
13027#define CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT (5U)
13034#define CAAM_PX_SMAPR_PG0_G2_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_WRITE_MASK)
13035
13036#define CAAM_PX_SMAPR_PG0_G2_TDO_MASK (0x40U)
13037#define CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT (6U)
13044#define CAAM_PX_SMAPR_PG0_G2_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_TDO_MASK)
13045
13046#define CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK (0x80U)
13047#define CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT (7U)
13052#define CAAM_PX_SMAPR_PG0_G2_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK)
13053
13054#define CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK (0x1000U)
13055#define CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT (12U)
13061#define CAAM_PX_SMAPR_PG0_SMAG_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK)
13062
13063#define CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK (0x2000U)
13064#define CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT (13U)
13071#define CAAM_PX_SMAPR_PG0_SMAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK)
13072
13073#define CAAM_PX_SMAPR_PG0_PSP_MASK (0x4000U)
13074#define CAAM_PX_SMAPR_PG0_PSP_SHIFT (14U)
13079#define CAAM_PX_SMAPR_PG0_PSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PSP_SHIFT)) & CAAM_PX_SMAPR_PG0_PSP_MASK)
13080
13081#define CAAM_PX_SMAPR_PG0_CSP_MASK (0x8000U)
13082#define CAAM_PX_SMAPR_PG0_CSP_SHIFT (15U)
13089#define CAAM_PX_SMAPR_PG0_CSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_CSP_SHIFT)) & CAAM_PX_SMAPR_PG0_CSP_MASK)
13090
13091#define CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK (0xFFFF0000U)
13092#define CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT (16U)
13093#define CAAM_PX_SMAPR_PG0_PARTITION_KMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK)
13096/* The count of CAAM_PX_SMAPR_PG0 */
13097#define CAAM_PX_SMAPR_PG0_COUNT (16U)
13098
13102#define CAAM_PX_SMAG2_PG0_Gx_ID00_MASK (0x1U)
13103#define CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT (0U)
13104#define CAAM_PX_SMAG2_PG0_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID00_MASK)
13105
13106#define CAAM_PX_SMAG2_PG0_Gx_ID01_MASK (0x2U)
13107#define CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT (1U)
13108#define CAAM_PX_SMAG2_PG0_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID01_MASK)
13109
13110#define CAAM_PX_SMAG2_PG0_Gx_ID02_MASK (0x4U)
13111#define CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT (2U)
13112#define CAAM_PX_SMAG2_PG0_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID02_MASK)
13113
13114#define CAAM_PX_SMAG2_PG0_Gx_ID03_MASK (0x8U)
13115#define CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT (3U)
13116#define CAAM_PX_SMAG2_PG0_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID03_MASK)
13117
13118#define CAAM_PX_SMAG2_PG0_Gx_ID04_MASK (0x10U)
13119#define CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT (4U)
13120#define CAAM_PX_SMAG2_PG0_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID04_MASK)
13121
13122#define CAAM_PX_SMAG2_PG0_Gx_ID05_MASK (0x20U)
13123#define CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT (5U)
13124#define CAAM_PX_SMAG2_PG0_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID05_MASK)
13125
13126#define CAAM_PX_SMAG2_PG0_Gx_ID06_MASK (0x40U)
13127#define CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT (6U)
13128#define CAAM_PX_SMAG2_PG0_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID06_MASK)
13129
13130#define CAAM_PX_SMAG2_PG0_Gx_ID07_MASK (0x80U)
13131#define CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT (7U)
13132#define CAAM_PX_SMAG2_PG0_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID07_MASK)
13133
13134#define CAAM_PX_SMAG2_PG0_Gx_ID08_MASK (0x100U)
13135#define CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT (8U)
13136#define CAAM_PX_SMAG2_PG0_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID08_MASK)
13137
13138#define CAAM_PX_SMAG2_PG0_Gx_ID09_MASK (0x200U)
13139#define CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT (9U)
13140#define CAAM_PX_SMAG2_PG0_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID09_MASK)
13141
13142#define CAAM_PX_SMAG2_PG0_Gx_ID10_MASK (0x400U)
13143#define CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT (10U)
13144#define CAAM_PX_SMAG2_PG0_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID10_MASK)
13145
13146#define CAAM_PX_SMAG2_PG0_Gx_ID11_MASK (0x800U)
13147#define CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT (11U)
13148#define CAAM_PX_SMAG2_PG0_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID11_MASK)
13149
13150#define CAAM_PX_SMAG2_PG0_Gx_ID12_MASK (0x1000U)
13151#define CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT (12U)
13152#define CAAM_PX_SMAG2_PG0_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID12_MASK)
13153
13154#define CAAM_PX_SMAG2_PG0_Gx_ID13_MASK (0x2000U)
13155#define CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT (13U)
13156#define CAAM_PX_SMAG2_PG0_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID13_MASK)
13157
13158#define CAAM_PX_SMAG2_PG0_Gx_ID14_MASK (0x4000U)
13159#define CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT (14U)
13160#define CAAM_PX_SMAG2_PG0_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID14_MASK)
13161
13162#define CAAM_PX_SMAG2_PG0_Gx_ID15_MASK (0x8000U)
13163#define CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT (15U)
13164#define CAAM_PX_SMAG2_PG0_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID15_MASK)
13165
13166#define CAAM_PX_SMAG2_PG0_Gx_ID16_MASK (0x10000U)
13167#define CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT (16U)
13168#define CAAM_PX_SMAG2_PG0_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID16_MASK)
13169
13170#define CAAM_PX_SMAG2_PG0_Gx_ID17_MASK (0x20000U)
13171#define CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT (17U)
13172#define CAAM_PX_SMAG2_PG0_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID17_MASK)
13173
13174#define CAAM_PX_SMAG2_PG0_Gx_ID18_MASK (0x40000U)
13175#define CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT (18U)
13176#define CAAM_PX_SMAG2_PG0_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID18_MASK)
13177
13178#define CAAM_PX_SMAG2_PG0_Gx_ID19_MASK (0x80000U)
13179#define CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT (19U)
13180#define CAAM_PX_SMAG2_PG0_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID19_MASK)
13181
13182#define CAAM_PX_SMAG2_PG0_Gx_ID20_MASK (0x100000U)
13183#define CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT (20U)
13184#define CAAM_PX_SMAG2_PG0_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID20_MASK)
13185
13186#define CAAM_PX_SMAG2_PG0_Gx_ID21_MASK (0x200000U)
13187#define CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT (21U)
13188#define CAAM_PX_SMAG2_PG0_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID21_MASK)
13189
13190#define CAAM_PX_SMAG2_PG0_Gx_ID22_MASK (0x400000U)
13191#define CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT (22U)
13192#define CAAM_PX_SMAG2_PG0_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID22_MASK)
13193
13194#define CAAM_PX_SMAG2_PG0_Gx_ID23_MASK (0x800000U)
13195#define CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT (23U)
13196#define CAAM_PX_SMAG2_PG0_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID23_MASK)
13197
13198#define CAAM_PX_SMAG2_PG0_Gx_ID24_MASK (0x1000000U)
13199#define CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT (24U)
13200#define CAAM_PX_SMAG2_PG0_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID24_MASK)
13201
13202#define CAAM_PX_SMAG2_PG0_Gx_ID25_MASK (0x2000000U)
13203#define CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT (25U)
13204#define CAAM_PX_SMAG2_PG0_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID25_MASK)
13205
13206#define CAAM_PX_SMAG2_PG0_Gx_ID26_MASK (0x4000000U)
13207#define CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT (26U)
13208#define CAAM_PX_SMAG2_PG0_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID26_MASK)
13209
13210#define CAAM_PX_SMAG2_PG0_Gx_ID27_MASK (0x8000000U)
13211#define CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT (27U)
13212#define CAAM_PX_SMAG2_PG0_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID27_MASK)
13213
13214#define CAAM_PX_SMAG2_PG0_Gx_ID28_MASK (0x10000000U)
13215#define CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT (28U)
13216#define CAAM_PX_SMAG2_PG0_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID28_MASK)
13217
13218#define CAAM_PX_SMAG2_PG0_Gx_ID29_MASK (0x20000000U)
13219#define CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT (29U)
13220#define CAAM_PX_SMAG2_PG0_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID29_MASK)
13221
13222#define CAAM_PX_SMAG2_PG0_Gx_ID30_MASK (0x40000000U)
13223#define CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT (30U)
13224#define CAAM_PX_SMAG2_PG0_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID30_MASK)
13225
13226#define CAAM_PX_SMAG2_PG0_Gx_ID31_MASK (0x80000000U)
13227#define CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT (31U)
13228#define CAAM_PX_SMAG2_PG0_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID31_MASK)
13231/* The count of CAAM_PX_SMAG2_PG0 */
13232#define CAAM_PX_SMAG2_PG0_COUNT (16U)
13233
13237#define CAAM_PX_SMAG1_PG0_Gx_ID00_MASK (0x1U)
13238#define CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT (0U)
13239#define CAAM_PX_SMAG1_PG0_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID00_MASK)
13240
13241#define CAAM_PX_SMAG1_PG0_Gx_ID01_MASK (0x2U)
13242#define CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT (1U)
13243#define CAAM_PX_SMAG1_PG0_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID01_MASK)
13244
13245#define CAAM_PX_SMAG1_PG0_Gx_ID02_MASK (0x4U)
13246#define CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT (2U)
13247#define CAAM_PX_SMAG1_PG0_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID02_MASK)
13248
13249#define CAAM_PX_SMAG1_PG0_Gx_ID03_MASK (0x8U)
13250#define CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT (3U)
13251#define CAAM_PX_SMAG1_PG0_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID03_MASK)
13252
13253#define CAAM_PX_SMAG1_PG0_Gx_ID04_MASK (0x10U)
13254#define CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT (4U)
13255#define CAAM_PX_SMAG1_PG0_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID04_MASK)
13256
13257#define CAAM_PX_SMAG1_PG0_Gx_ID05_MASK (0x20U)
13258#define CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT (5U)
13259#define CAAM_PX_SMAG1_PG0_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID05_MASK)
13260
13261#define CAAM_PX_SMAG1_PG0_Gx_ID06_MASK (0x40U)
13262#define CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT (6U)
13263#define CAAM_PX_SMAG1_PG0_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID06_MASK)
13264
13265#define CAAM_PX_SMAG1_PG0_Gx_ID07_MASK (0x80U)
13266#define CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT (7U)
13267#define CAAM_PX_SMAG1_PG0_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID07_MASK)
13268
13269#define CAAM_PX_SMAG1_PG0_Gx_ID08_MASK (0x100U)
13270#define CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT (8U)
13271#define CAAM_PX_SMAG1_PG0_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID08_MASK)
13272
13273#define CAAM_PX_SMAG1_PG0_Gx_ID09_MASK (0x200U)
13274#define CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT (9U)
13275#define CAAM_PX_SMAG1_PG0_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID09_MASK)
13276
13277#define CAAM_PX_SMAG1_PG0_Gx_ID10_MASK (0x400U)
13278#define CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT (10U)
13279#define CAAM_PX_SMAG1_PG0_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID10_MASK)
13280
13281#define CAAM_PX_SMAG1_PG0_Gx_ID11_MASK (0x800U)
13282#define CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT (11U)
13283#define CAAM_PX_SMAG1_PG0_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID11_MASK)
13284
13285#define CAAM_PX_SMAG1_PG0_Gx_ID12_MASK (0x1000U)
13286#define CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT (12U)
13287#define CAAM_PX_SMAG1_PG0_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID12_MASK)
13288
13289#define CAAM_PX_SMAG1_PG0_Gx_ID13_MASK (0x2000U)
13290#define CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT (13U)
13291#define CAAM_PX_SMAG1_PG0_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID13_MASK)
13292
13293#define CAAM_PX_SMAG1_PG0_Gx_ID14_MASK (0x4000U)
13294#define CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT (14U)
13295#define CAAM_PX_SMAG1_PG0_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID14_MASK)
13296
13297#define CAAM_PX_SMAG1_PG0_Gx_ID15_MASK (0x8000U)
13298#define CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT (15U)
13299#define CAAM_PX_SMAG1_PG0_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID15_MASK)
13300
13301#define CAAM_PX_SMAG1_PG0_Gx_ID16_MASK (0x10000U)
13302#define CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT (16U)
13303#define CAAM_PX_SMAG1_PG0_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID16_MASK)
13304
13305#define CAAM_PX_SMAG1_PG0_Gx_ID17_MASK (0x20000U)
13306#define CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT (17U)
13307#define CAAM_PX_SMAG1_PG0_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID17_MASK)
13308
13309#define CAAM_PX_SMAG1_PG0_Gx_ID18_MASK (0x40000U)
13310#define CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT (18U)
13311#define CAAM_PX_SMAG1_PG0_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID18_MASK)
13312
13313#define CAAM_PX_SMAG1_PG0_Gx_ID19_MASK (0x80000U)
13314#define CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT (19U)
13315#define CAAM_PX_SMAG1_PG0_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID19_MASK)
13316
13317#define CAAM_PX_SMAG1_PG0_Gx_ID20_MASK (0x100000U)
13318#define CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT (20U)
13319#define CAAM_PX_SMAG1_PG0_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID20_MASK)
13320
13321#define CAAM_PX_SMAG1_PG0_Gx_ID21_MASK (0x200000U)
13322#define CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT (21U)
13323#define CAAM_PX_SMAG1_PG0_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID21_MASK)
13324
13325#define CAAM_PX_SMAG1_PG0_Gx_ID22_MASK (0x400000U)
13326#define CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT (22U)
13327#define CAAM_PX_SMAG1_PG0_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID22_MASK)
13328
13329#define CAAM_PX_SMAG1_PG0_Gx_ID23_MASK (0x800000U)
13330#define CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT (23U)
13331#define CAAM_PX_SMAG1_PG0_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID23_MASK)
13332
13333#define CAAM_PX_SMAG1_PG0_Gx_ID24_MASK (0x1000000U)
13334#define CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT (24U)
13335#define CAAM_PX_SMAG1_PG0_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID24_MASK)
13336
13337#define CAAM_PX_SMAG1_PG0_Gx_ID25_MASK (0x2000000U)
13338#define CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT (25U)
13339#define CAAM_PX_SMAG1_PG0_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID25_MASK)
13340
13341#define CAAM_PX_SMAG1_PG0_Gx_ID26_MASK (0x4000000U)
13342#define CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT (26U)
13343#define CAAM_PX_SMAG1_PG0_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID26_MASK)
13344
13345#define CAAM_PX_SMAG1_PG0_Gx_ID27_MASK (0x8000000U)
13346#define CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT (27U)
13347#define CAAM_PX_SMAG1_PG0_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID27_MASK)
13348
13349#define CAAM_PX_SMAG1_PG0_Gx_ID28_MASK (0x10000000U)
13350#define CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT (28U)
13351#define CAAM_PX_SMAG1_PG0_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID28_MASK)
13352
13353#define CAAM_PX_SMAG1_PG0_Gx_ID29_MASK (0x20000000U)
13354#define CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT (29U)
13355#define CAAM_PX_SMAG1_PG0_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID29_MASK)
13356
13357#define CAAM_PX_SMAG1_PG0_Gx_ID30_MASK (0x40000000U)
13358#define CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT (30U)
13359#define CAAM_PX_SMAG1_PG0_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID30_MASK)
13360
13361#define CAAM_PX_SMAG1_PG0_Gx_ID31_MASK (0x80000000U)
13362#define CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT (31U)
13363#define CAAM_PX_SMAG1_PG0_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID31_MASK)
13366/* The count of CAAM_PX_SMAG1_PG0 */
13367#define CAAM_PX_SMAG1_PG0_COUNT (16U)
13368
13372#define CAAM_REIS_CWDE_MASK (0x1U)
13373#define CAAM_REIS_CWDE_SHIFT (0U)
13374#define CAAM_REIS_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_CWDE_SHIFT)) & CAAM_REIS_CWDE_MASK)
13375
13376#define CAAM_REIS_RBAE_MASK (0x10000U)
13377#define CAAM_REIS_RBAE_SHIFT (16U)
13378#define CAAM_REIS_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_RBAE_SHIFT)) & CAAM_REIS_RBAE_MASK)
13379
13380#define CAAM_REIS_JBAE0_MASK (0x1000000U)
13381#define CAAM_REIS_JBAE0_SHIFT (24U)
13382#define CAAM_REIS_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE0_SHIFT)) & CAAM_REIS_JBAE0_MASK)
13383
13384#define CAAM_REIS_JBAE1_MASK (0x2000000U)
13385#define CAAM_REIS_JBAE1_SHIFT (25U)
13386#define CAAM_REIS_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE1_SHIFT)) & CAAM_REIS_JBAE1_MASK)
13387
13388#define CAAM_REIS_JBAE2_MASK (0x4000000U)
13389#define CAAM_REIS_JBAE2_SHIFT (26U)
13390#define CAAM_REIS_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE2_SHIFT)) & CAAM_REIS_JBAE2_MASK)
13391
13392#define CAAM_REIS_JBAE3_MASK (0x8000000U)
13393#define CAAM_REIS_JBAE3_SHIFT (27U)
13394#define CAAM_REIS_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE3_SHIFT)) & CAAM_REIS_JBAE3_MASK)
13400#define CAAM_REIE_CWDE_MASK (0x1U)
13401#define CAAM_REIE_CWDE_SHIFT (0U)
13402#define CAAM_REIE_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_CWDE_SHIFT)) & CAAM_REIE_CWDE_MASK)
13403
13404#define CAAM_REIE_RBAE_MASK (0x10000U)
13405#define CAAM_REIE_RBAE_SHIFT (16U)
13406#define CAAM_REIE_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_RBAE_SHIFT)) & CAAM_REIE_RBAE_MASK)
13407
13408#define CAAM_REIE_JBAE0_MASK (0x1000000U)
13409#define CAAM_REIE_JBAE0_SHIFT (24U)
13410#define CAAM_REIE_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE0_SHIFT)) & CAAM_REIE_JBAE0_MASK)
13411
13412#define CAAM_REIE_JBAE1_MASK (0x2000000U)
13413#define CAAM_REIE_JBAE1_SHIFT (25U)
13414#define CAAM_REIE_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE1_SHIFT)) & CAAM_REIE_JBAE1_MASK)
13415
13416#define CAAM_REIE_JBAE2_MASK (0x4000000U)
13417#define CAAM_REIE_JBAE2_SHIFT (26U)
13418#define CAAM_REIE_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE2_SHIFT)) & CAAM_REIE_JBAE2_MASK)
13419
13420#define CAAM_REIE_JBAE3_MASK (0x8000000U)
13421#define CAAM_REIE_JBAE3_SHIFT (27U)
13422#define CAAM_REIE_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE3_SHIFT)) & CAAM_REIE_JBAE3_MASK)
13428#define CAAM_REIF_CWDE_MASK (0x1U)
13429#define CAAM_REIF_CWDE_SHIFT (0U)
13430#define CAAM_REIF_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_CWDE_SHIFT)) & CAAM_REIF_CWDE_MASK)
13431
13432#define CAAM_REIF_RBAE_MASK (0x10000U)
13433#define CAAM_REIF_RBAE_SHIFT (16U)
13434#define CAAM_REIF_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_RBAE_SHIFT)) & CAAM_REIF_RBAE_MASK)
13435
13436#define CAAM_REIF_JBAE0_MASK (0x1000000U)
13437#define CAAM_REIF_JBAE0_SHIFT (24U)
13438#define CAAM_REIF_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE0_SHIFT)) & CAAM_REIF_JBAE0_MASK)
13439
13440#define CAAM_REIF_JBAE1_MASK (0x2000000U)
13441#define CAAM_REIF_JBAE1_SHIFT (25U)
13442#define CAAM_REIF_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE1_SHIFT)) & CAAM_REIF_JBAE1_MASK)
13443
13444#define CAAM_REIF_JBAE2_MASK (0x4000000U)
13445#define CAAM_REIF_JBAE2_SHIFT (26U)
13446#define CAAM_REIF_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE2_SHIFT)) & CAAM_REIF_JBAE2_MASK)
13447
13448#define CAAM_REIF_JBAE3_MASK (0x8000000U)
13449#define CAAM_REIF_JBAE3_SHIFT (27U)
13450#define CAAM_REIF_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE3_SHIFT)) & CAAM_REIF_JBAE3_MASK)
13456#define CAAM_REIH_CWDE_MASK (0x1U)
13457#define CAAM_REIH_CWDE_SHIFT (0U)
13462#define CAAM_REIH_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_CWDE_SHIFT)) & CAAM_REIH_CWDE_MASK)
13463
13464#define CAAM_REIH_RBAE_MASK (0x10000U)
13465#define CAAM_REIH_RBAE_SHIFT (16U)
13470#define CAAM_REIH_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_RBAE_SHIFT)) & CAAM_REIH_RBAE_MASK)
13471
13472#define CAAM_REIH_JBAE0_MASK (0x1000000U)
13473#define CAAM_REIH_JBAE0_SHIFT (24U)
13478#define CAAM_REIH_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE0_SHIFT)) & CAAM_REIH_JBAE0_MASK)
13479
13480#define CAAM_REIH_JBAE1_MASK (0x2000000U)
13481#define CAAM_REIH_JBAE1_SHIFT (25U)
13486#define CAAM_REIH_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE1_SHIFT)) & CAAM_REIH_JBAE1_MASK)
13487
13488#define CAAM_REIH_JBAE2_MASK (0x4000000U)
13489#define CAAM_REIH_JBAE2_SHIFT (26U)
13494#define CAAM_REIH_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE2_SHIFT)) & CAAM_REIH_JBAE2_MASK)
13495
13496#define CAAM_REIH_JBAE3_MASK (0x8000000U)
13497#define CAAM_REIH_JBAE3_SHIFT (27U)
13502#define CAAM_REIH_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE3_SHIFT)) & CAAM_REIH_JBAE3_MASK)
13508#define CAAM_SMWPJRR_SMR_WP_JRa_MASK (0x1U)
13509#define CAAM_SMWPJRR_SMR_WP_JRa_SHIFT (0U)
13510#define CAAM_SMWPJRR_SMR_WP_JRa(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMWPJRR_SMR_WP_JRa_SHIFT)) & CAAM_SMWPJRR_SMR_WP_JRa_MASK)
13513/* The count of CAAM_SMWPJRR */
13514#define CAAM_SMWPJRR_COUNT (4U)
13515
13519#define CAAM_SMCR_PG0_CMD_MASK (0xFU)
13520#define CAAM_SMCR_PG0_CMD_SHIFT (0U)
13521#define CAAM_SMCR_PG0_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_CMD_SHIFT)) & CAAM_SMCR_PG0_CMD_MASK)
13522
13523#define CAAM_SMCR_PG0_PRTN_MASK (0xF00U)
13524#define CAAM_SMCR_PG0_PRTN_SHIFT (8U)
13525#define CAAM_SMCR_PG0_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PRTN_SHIFT)) & CAAM_SMCR_PG0_PRTN_MASK)
13526
13527#define CAAM_SMCR_PG0_PAGE_MASK (0xFFFF0000U)
13528#define CAAM_SMCR_PG0_PAGE_SHIFT (16U)
13529#define CAAM_SMCR_PG0_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PAGE_SHIFT)) & CAAM_SMCR_PG0_PAGE_MASK)
13535#define CAAM_SMCSR_PG0_PRTN_MASK (0xFU)
13536#define CAAM_SMCSR_PG0_PRTN_SHIFT (0U)
13537#define CAAM_SMCSR_PG0_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PRTN_SHIFT)) & CAAM_SMCSR_PG0_PRTN_MASK)
13538
13539#define CAAM_SMCSR_PG0_PO_MASK (0xC0U)
13540#define CAAM_SMCSR_PG0_PO_SHIFT (6U)
13550#define CAAM_SMCSR_PG0_PO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PO_SHIFT)) & CAAM_SMCSR_PG0_PO_MASK)
13551
13552#define CAAM_SMCSR_PG0_AERR_MASK (0x3000U)
13553#define CAAM_SMCSR_PG0_AERR_SHIFT (12U)
13554#define CAAM_SMCSR_PG0_AERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_AERR_SHIFT)) & CAAM_SMCSR_PG0_AERR_MASK)
13555
13556#define CAAM_SMCSR_PG0_CERR_MASK (0xC000U)
13557#define CAAM_SMCSR_PG0_CERR_SHIFT (14U)
13565#define CAAM_SMCSR_PG0_CERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_CERR_SHIFT)) & CAAM_SMCSR_PG0_CERR_MASK)
13566
13567#define CAAM_SMCSR_PG0_PAGE_MASK (0xFFF0000U)
13568#define CAAM_SMCSR_PG0_PAGE_SHIFT (16U)
13569#define CAAM_SMCSR_PG0_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PAGE_SHIFT)) & CAAM_SMCSR_PG0_PAGE_MASK)
13575#define CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK (0xFFU)
13576#define CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT (0U)
13577#define CAAM_CAAMVID_MS_TRAD_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK)
13578
13579#define CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK (0xFF00U)
13580#define CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT (8U)
13581#define CAAM_CAAMVID_MS_TRAD_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK)
13582
13583#define CAAM_CAAMVID_MS_TRAD_IP_ID_MASK (0xFFFF0000U)
13584#define CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT (16U)
13585#define CAAM_CAAMVID_MS_TRAD_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT)) & CAAM_CAAMVID_MS_TRAD_IP_ID_MASK)
13591#define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK (0xFFU)
13592#define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT (0U)
13593#define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK)
13594
13595#define CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK (0xFF00U)
13596#define CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT (8U)
13597#define CAAM_CAAMVID_LS_TRAD_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT)) & CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK)
13598
13599#define CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK (0xFF0000U)
13600#define CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT (16U)
13601#define CAAM_CAAMVID_LS_TRAD_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK)
13602
13603#define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK (0xFF000000U)
13604#define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT (24U)
13605#define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK)
13611#define CAAM_HT_JD_ADDR_JD_ADDR_MASK (0xFFFFFFFFFU)
13612#define CAAM_HT_JD_ADDR_JD_ADDR_SHIFT (0U)
13613#define CAAM_HT_JD_ADDR_JD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_HT_JD_ADDR_JD_ADDR_SHIFT)) & CAAM_HT_JD_ADDR_JD_ADDR_MASK)
13616/* The count of CAAM_HT_JD_ADDR */
13617#define CAAM_HT_JD_ADDR_COUNT (1U)
13618
13622#define CAAM_HT_SD_ADDR_SD_ADDR_MASK (0xFFFFFFFFFU)
13623#define CAAM_HT_SD_ADDR_SD_ADDR_SHIFT (0U)
13624#define CAAM_HT_SD_ADDR_SD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_HT_SD_ADDR_SD_ADDR_SHIFT)) & CAAM_HT_SD_ADDR_SD_ADDR_MASK)
13627/* The count of CAAM_HT_SD_ADDR */
13628#define CAAM_HT_SD_ADDR_COUNT (1U)
13629
13633#define CAAM_HT_JQ_CTRL_MS_ID_MASK (0x7U)
13634#define CAAM_HT_JQ_CTRL_MS_ID_SHIFT (0U)
13635#define CAAM_HT_JQ_CTRL_MS_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ID_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ID_MASK)
13636
13637#define CAAM_HT_JQ_CTRL_MS_SRC_MASK (0x700U)
13638#define CAAM_HT_JQ_CTRL_MS_SRC_SHIFT (8U)
13649#define CAAM_HT_JQ_CTRL_MS_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SRC_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SRC_MASK)
13650
13651#define CAAM_HT_JQ_CTRL_MS_JDDS_MASK (0x4000U)
13652#define CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT (14U)
13657#define CAAM_HT_JQ_CTRL_MS_JDDS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT)) & CAAM_HT_JQ_CTRL_MS_JDDS_MASK)
13658
13659#define CAAM_HT_JQ_CTRL_MS_AMTD_MASK (0x8000U)
13660#define CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT (15U)
13661#define CAAM_HT_JQ_CTRL_MS_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT)) & CAAM_HT_JQ_CTRL_MS_AMTD_MASK)
13662
13663#define CAAM_HT_JQ_CTRL_MS_SOB_MASK (0x10000U)
13664#define CAAM_HT_JQ_CTRL_MS_SOB_SHIFT (16U)
13665#define CAAM_HT_JQ_CTRL_MS_SOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SOB_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SOB_MASK)
13666
13667#define CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK (0x60000U)
13668#define CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT (17U)
13675#define CAAM_HT_JQ_CTRL_MS_HT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK)
13676
13677#define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK (0x80000U)
13678#define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT (19U)
13683#define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT)) & CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK)
13684
13685#define CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK (0x7C00000U)
13686#define CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT (22U)
13687#define CAAM_HT_JQ_CTRL_MS_SHR_FROM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK)
13688
13689#define CAAM_HT_JQ_CTRL_MS_ILE_MASK (0x8000000U)
13690#define CAAM_HT_JQ_CTRL_MS_ILE_SHIFT (27U)
13695#define CAAM_HT_JQ_CTRL_MS_ILE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ILE_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ILE_MASK)
13696
13697#define CAAM_HT_JQ_CTRL_MS_FOUR_MASK (0x10000000U)
13698#define CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT (28U)
13699#define CAAM_HT_JQ_CTRL_MS_FOUR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_FOUR_MASK)
13700
13701#define CAAM_HT_JQ_CTRL_MS_WHL_MASK (0x20000000U)
13702#define CAAM_HT_JQ_CTRL_MS_WHL_SHIFT (29U)
13703#define CAAM_HT_JQ_CTRL_MS_WHL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_WHL_SHIFT)) & CAAM_HT_JQ_CTRL_MS_WHL_MASK)
13706/* The count of CAAM_HT_JQ_CTRL_MS */
13707#define CAAM_HT_JQ_CTRL_MS_COUNT (1U)
13708
13712#define CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK (0xFU)
13713#define CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT (0U)
13714#define CAAM_HT_JQ_CTRL_LS_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK)
13715
13716#define CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK (0x10U)
13717#define CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT (4U)
13722#define CAAM_HT_JQ_CTRL_LS_PRIM_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK)
13723
13724#define CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK (0xFFE0U)
13725#define CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT (5U)
13726#define CAAM_HT_JQ_CTRL_LS_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK)
13727
13728#define CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK (0xF0000U)
13729#define CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT (16U)
13730#define CAAM_HT_JQ_CTRL_LS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK)
13731
13732#define CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK (0xFFE00000U)
13733#define CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT (21U)
13734#define CAAM_HT_JQ_CTRL_LS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK)
13737/* The count of CAAM_HT_JQ_CTRL_LS */
13738#define CAAM_HT_JQ_CTRL_LS_COUNT (1U)
13739
13743#define CAAM_HT_STATUS_PEND_0_MASK (0x1U)
13744#define CAAM_HT_STATUS_PEND_0_SHIFT (0U)
13745#define CAAM_HT_STATUS_PEND_0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_PEND_0_SHIFT)) & CAAM_HT_STATUS_PEND_0_MASK)
13746
13747#define CAAM_HT_STATUS_IN_USE_MASK (0x40000000U)
13748#define CAAM_HT_STATUS_IN_USE_SHIFT (30U)
13749#define CAAM_HT_STATUS_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_IN_USE_SHIFT)) & CAAM_HT_STATUS_IN_USE_MASK)
13750
13751#define CAAM_HT_STATUS_BC_MASK (0x80000000U)
13752#define CAAM_HT_STATUS_BC_SHIFT (31U)
13753#define CAAM_HT_STATUS_BC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_BC_SHIFT)) & CAAM_HT_STATUS_BC_MASK)
13756/* The count of CAAM_HT_STATUS */
13757#define CAAM_HT_STATUS_COUNT (1U)
13758
13762#define CAAM_JQ_DEBUG_SEL_HT_SEL_MASK (0x1U)
13763#define CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT (0U)
13764#define CAAM_JQ_DEBUG_SEL_HT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT)) & CAAM_JQ_DEBUG_SEL_HT_SEL_MASK)
13765
13766#define CAAM_JQ_DEBUG_SEL_JOB_ID_MASK (0x70000U)
13767#define CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT (16U)
13768#define CAAM_JQ_DEBUG_SEL_JOB_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT)) & CAAM_JQ_DEBUG_SEL_JOB_ID_MASK)
13774#define CAAM_JRJIDU_LS_JID00_MASK (0x1U)
13775#define CAAM_JRJIDU_LS_JID00_SHIFT (0U)
13776#define CAAM_JRJIDU_LS_JID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID00_SHIFT)) & CAAM_JRJIDU_LS_JID00_MASK)
13777
13778#define CAAM_JRJIDU_LS_JID01_MASK (0x2U)
13779#define CAAM_JRJIDU_LS_JID01_SHIFT (1U)
13780#define CAAM_JRJIDU_LS_JID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID01_SHIFT)) & CAAM_JRJIDU_LS_JID01_MASK)
13781
13782#define CAAM_JRJIDU_LS_JID02_MASK (0x4U)
13783#define CAAM_JRJIDU_LS_JID02_SHIFT (2U)
13784#define CAAM_JRJIDU_LS_JID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID02_SHIFT)) & CAAM_JRJIDU_LS_JID02_MASK)
13785
13786#define CAAM_JRJIDU_LS_JID03_MASK (0x8U)
13787#define CAAM_JRJIDU_LS_JID03_SHIFT (3U)
13788#define CAAM_JRJIDU_LS_JID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID03_SHIFT)) & CAAM_JRJIDU_LS_JID03_MASK)
13794#define CAAM_JRJDJIFBC_BC_MASK (0x80000000U)
13795#define CAAM_JRJDJIFBC_BC_SHIFT (31U)
13796#define CAAM_JRJDJIFBC_BC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIFBC_BC_SHIFT)) & CAAM_JRJDJIFBC_BC_MASK)
13802#define CAAM_JRJDJIF_JOB_ID_ENTRY_MASK (0x7U)
13803#define CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT (0U)
13804#define CAAM_JRJDJIF_JOB_ID_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT)) & CAAM_JRJDJIF_JOB_ID_ENTRY_MASK)
13810#define CAAM_JRJDS1_SRC_MASK (0x3U)
13811#define CAAM_JRJDS1_SRC_SHIFT (0U)
13812#define CAAM_JRJDS1_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_SRC_SHIFT)) & CAAM_JRJDS1_SRC_MASK)
13813
13814#define CAAM_JRJDS1_VALID_MASK (0x80000000U)
13815#define CAAM_JRJDS1_VALID_SHIFT (31U)
13816#define CAAM_JRJDS1_VALID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_VALID_SHIFT)) & CAAM_JRJDS1_VALID_MASK)
13822#define CAAM_JRJDDA_JD_ADDR_MASK (0xFFFFFFFFFU)
13823#define CAAM_JRJDDA_JD_ADDR_SHIFT (0U)
13824#define CAAM_JRJDDA_JD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_JRJDDA_JD_ADDR_SHIFT)) & CAAM_JRJDDA_JD_ADDR_MASK)
13827/* The count of CAAM_JRJDDA */
13828#define CAAM_JRJDDA_COUNT (1U)
13829
13833#define CAAM_CRNR_MS_CRCRN_MASK (0xFU)
13834#define CAAM_CRNR_MS_CRCRN_SHIFT (0U)
13835#define CAAM_CRNR_MS_CRCRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_CRCRN_SHIFT)) & CAAM_CRNR_MS_CRCRN_MASK)
13836
13837#define CAAM_CRNR_MS_SNW9RN_MASK (0xF0U)
13838#define CAAM_CRNR_MS_SNW9RN_SHIFT (4U)
13839#define CAAM_CRNR_MS_SNW9RN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_SNW9RN_SHIFT)) & CAAM_CRNR_MS_SNW9RN_MASK)
13840
13841#define CAAM_CRNR_MS_ZERN_MASK (0xF00U)
13842#define CAAM_CRNR_MS_ZERN_SHIFT (8U)
13843#define CAAM_CRNR_MS_ZERN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZERN_SHIFT)) & CAAM_CRNR_MS_ZERN_MASK)
13844
13845#define CAAM_CRNR_MS_ZARN_MASK (0xF000U)
13846#define CAAM_CRNR_MS_ZARN_SHIFT (12U)
13847#define CAAM_CRNR_MS_ZARN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZARN_SHIFT)) & CAAM_CRNR_MS_ZARN_MASK)
13848
13849#define CAAM_CRNR_MS_DECORN_MASK (0xF000000U)
13850#define CAAM_CRNR_MS_DECORN_SHIFT (24U)
13851#define CAAM_CRNR_MS_DECORN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_DECORN_SHIFT)) & CAAM_CRNR_MS_DECORN_MASK)
13852
13853#define CAAM_CRNR_MS_JRRN_MASK (0xF0000000U)
13854#define CAAM_CRNR_MS_JRRN_SHIFT (28U)
13855#define CAAM_CRNR_MS_JRRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_JRRN_SHIFT)) & CAAM_CRNR_MS_JRRN_MASK)
13861#define CAAM_CRNR_LS_AESRN_MASK (0xFU)
13862#define CAAM_CRNR_LS_AESRN_SHIFT (0U)
13863#define CAAM_CRNR_LS_AESRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_AESRN_SHIFT)) & CAAM_CRNR_LS_AESRN_MASK)
13864
13865#define CAAM_CRNR_LS_DESRN_MASK (0xF0U)
13866#define CAAM_CRNR_LS_DESRN_SHIFT (4U)
13867#define CAAM_CRNR_LS_DESRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_DESRN_SHIFT)) & CAAM_CRNR_LS_DESRN_MASK)
13868
13869#define CAAM_CRNR_LS_MDRN_MASK (0xF000U)
13870#define CAAM_CRNR_LS_MDRN_SHIFT (12U)
13871#define CAAM_CRNR_LS_MDRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_MDRN_SHIFT)) & CAAM_CRNR_LS_MDRN_MASK)
13872
13873#define CAAM_CRNR_LS_RNGRN_MASK (0xF0000U)
13874#define CAAM_CRNR_LS_RNGRN_SHIFT (16U)
13875#define CAAM_CRNR_LS_RNGRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_RNGRN_SHIFT)) & CAAM_CRNR_LS_RNGRN_MASK)
13876
13877#define CAAM_CRNR_LS_SNW8RN_MASK (0xF00000U)
13878#define CAAM_CRNR_LS_SNW8RN_SHIFT (20U)
13879#define CAAM_CRNR_LS_SNW8RN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_SNW8RN_SHIFT)) & CAAM_CRNR_LS_SNW8RN_MASK)
13880
13881#define CAAM_CRNR_LS_KASRN_MASK (0xF000000U)
13882#define CAAM_CRNR_LS_KASRN_SHIFT (24U)
13883#define CAAM_CRNR_LS_KASRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_KASRN_SHIFT)) & CAAM_CRNR_LS_KASRN_MASK)
13884
13885#define CAAM_CRNR_LS_PKRN_MASK (0xF0000000U)
13886#define CAAM_CRNR_LS_PKRN_SHIFT (28U)
13893#define CAAM_CRNR_LS_PKRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_PKRN_SHIFT)) & CAAM_CRNR_LS_PKRN_MASK)
13899#define CAAM_CTPR_MS_VIRT_EN_INCL_MASK (0x1U)
13900#define CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT (0U)
13901#define CAAM_CTPR_MS_VIRT_EN_INCL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_INCL_MASK)
13902
13903#define CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK (0x2U)
13904#define CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT (1U)
13905#define CAAM_CTPR_MS_VIRT_EN_POR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK)
13906
13907#define CAAM_CTPR_MS_REG_PG_SIZE_MASK (0x10U)
13908#define CAAM_CTPR_MS_REG_PG_SIZE_SHIFT (4U)
13909#define CAAM_CTPR_MS_REG_PG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_REG_PG_SIZE_SHIFT)) & CAAM_CTPR_MS_REG_PG_SIZE_MASK)
13910
13911#define CAAM_CTPR_MS_RNG_I_MASK (0x700U)
13912#define CAAM_CTPR_MS_RNG_I_SHIFT (8U)
13913#define CAAM_CTPR_MS_RNG_I(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_RNG_I_SHIFT)) & CAAM_CTPR_MS_RNG_I_MASK)
13914
13915#define CAAM_CTPR_MS_AI_INCL_MASK (0x800U)
13916#define CAAM_CTPR_MS_AI_INCL_SHIFT (11U)
13917#define CAAM_CTPR_MS_AI_INCL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AI_INCL_SHIFT)) & CAAM_CTPR_MS_AI_INCL_MASK)
13918
13919#define CAAM_CTPR_MS_DPAA2_MASK (0x2000U)
13920#define CAAM_CTPR_MS_DPAA2_SHIFT (13U)
13921#define CAAM_CTPR_MS_DPAA2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DPAA2_SHIFT)) & CAAM_CTPR_MS_DPAA2_MASK)
13922
13923#define CAAM_CTPR_MS_IP_CLK_MASK (0x4000U)
13924#define CAAM_CTPR_MS_IP_CLK_SHIFT (14U)
13925#define CAAM_CTPR_MS_IP_CLK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_IP_CLK_SHIFT)) & CAAM_CTPR_MS_IP_CLK_MASK)
13926
13927#define CAAM_CTPR_MS_MCFG_BURST_MASK (0x10000U)
13928#define CAAM_CTPR_MS_MCFG_BURST_SHIFT (16U)
13929#define CAAM_CTPR_MS_MCFG_BURST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_BURST_SHIFT)) & CAAM_CTPR_MS_MCFG_BURST_MASK)
13930
13931#define CAAM_CTPR_MS_MCFG_PS_MASK (0x20000U)
13932#define CAAM_CTPR_MS_MCFG_PS_SHIFT (17U)
13933#define CAAM_CTPR_MS_MCFG_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_PS_SHIFT)) & CAAM_CTPR_MS_MCFG_PS_MASK)
13934
13935#define CAAM_CTPR_MS_SG8_MASK (0x40000U)
13936#define CAAM_CTPR_MS_SG8_SHIFT (18U)
13937#define CAAM_CTPR_MS_SG8(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_SG8_SHIFT)) & CAAM_CTPR_MS_SG8_MASK)
13938
13939#define CAAM_CTPR_MS_PM_EVT_BUS_MASK (0x80000U)
13940#define CAAM_CTPR_MS_PM_EVT_BUS_SHIFT (19U)
13941#define CAAM_CTPR_MS_PM_EVT_BUS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PM_EVT_BUS_SHIFT)) & CAAM_CTPR_MS_PM_EVT_BUS_MASK)
13942
13943#define CAAM_CTPR_MS_DECO_WD_MASK (0x100000U)
13944#define CAAM_CTPR_MS_DECO_WD_SHIFT (20U)
13945#define CAAM_CTPR_MS_DECO_WD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DECO_WD_SHIFT)) & CAAM_CTPR_MS_DECO_WD_MASK)
13946
13947#define CAAM_CTPR_MS_PC_MASK (0x200000U)
13948#define CAAM_CTPR_MS_PC_SHIFT (21U)
13949#define CAAM_CTPR_MS_PC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PC_SHIFT)) & CAAM_CTPR_MS_PC_MASK)
13950
13951#define CAAM_CTPR_MS_C1C2_MASK (0x800000U)
13952#define CAAM_CTPR_MS_C1C2_SHIFT (23U)
13953#define CAAM_CTPR_MS_C1C2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_C1C2_SHIFT)) & CAAM_CTPR_MS_C1C2_MASK)
13954
13955#define CAAM_CTPR_MS_ACC_CTL_MASK (0x1000000U)
13956#define CAAM_CTPR_MS_ACC_CTL_SHIFT (24U)
13957#define CAAM_CTPR_MS_ACC_CTL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_ACC_CTL_SHIFT)) & CAAM_CTPR_MS_ACC_CTL_MASK)
13958
13959#define CAAM_CTPR_MS_QI_MASK (0x2000000U)
13960#define CAAM_CTPR_MS_QI_SHIFT (25U)
13961#define CAAM_CTPR_MS_QI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_QI_SHIFT)) & CAAM_CTPR_MS_QI_MASK)
13962
13963#define CAAM_CTPR_MS_AXI_PRI_MASK (0x4000000U)
13964#define CAAM_CTPR_MS_AXI_PRI_SHIFT (26U)
13965#define CAAM_CTPR_MS_AXI_PRI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PRI_SHIFT)) & CAAM_CTPR_MS_AXI_PRI_MASK)
13966
13967#define CAAM_CTPR_MS_AXI_LIODN_MASK (0x8000000U)
13968#define CAAM_CTPR_MS_AXI_LIODN_SHIFT (27U)
13969#define CAAM_CTPR_MS_AXI_LIODN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_LIODN_SHIFT)) & CAAM_CTPR_MS_AXI_LIODN_MASK)
13970
13971#define CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK (0xF0000000U)
13972#define CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT (28U)
13973#define CAAM_CTPR_MS_AXI_PIPE_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT)) & CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK)
13979#define CAAM_CTPR_LS_KG_DS_MASK (0x1U)
13980#define CAAM_CTPR_LS_KG_DS_SHIFT (0U)
13985#define CAAM_CTPR_LS_KG_DS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_KG_DS_SHIFT)) & CAAM_CTPR_LS_KG_DS_MASK)
13986
13987#define CAAM_CTPR_LS_BLOB_MASK (0x2U)
13988#define CAAM_CTPR_LS_BLOB_SHIFT (1U)
13993#define CAAM_CTPR_LS_BLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_BLOB_SHIFT)) & CAAM_CTPR_LS_BLOB_MASK)
13994
13995#define CAAM_CTPR_LS_WIFI_MASK (0x4U)
13996#define CAAM_CTPR_LS_WIFI_SHIFT (2U)
14001#define CAAM_CTPR_LS_WIFI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIFI_SHIFT)) & CAAM_CTPR_LS_WIFI_MASK)
14002
14003#define CAAM_CTPR_LS_WIMAX_MASK (0x8U)
14004#define CAAM_CTPR_LS_WIMAX_SHIFT (3U)
14009#define CAAM_CTPR_LS_WIMAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIMAX_SHIFT)) & CAAM_CTPR_LS_WIMAX_MASK)
14010
14011#define CAAM_CTPR_LS_SRTP_MASK (0x10U)
14012#define CAAM_CTPR_LS_SRTP_SHIFT (4U)
14017#define CAAM_CTPR_LS_SRTP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SRTP_SHIFT)) & CAAM_CTPR_LS_SRTP_MASK)
14018
14019#define CAAM_CTPR_LS_IPSEC_MASK (0x20U)
14020#define CAAM_CTPR_LS_IPSEC_SHIFT (5U)
14025#define CAAM_CTPR_LS_IPSEC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IPSEC_SHIFT)) & CAAM_CTPR_LS_IPSEC_MASK)
14026
14027#define CAAM_CTPR_LS_IKE_MASK (0x40U)
14028#define CAAM_CTPR_LS_IKE_SHIFT (6U)
14033#define CAAM_CTPR_LS_IKE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IKE_SHIFT)) & CAAM_CTPR_LS_IKE_MASK)
14034
14035#define CAAM_CTPR_LS_SSL_TLS_MASK (0x80U)
14036#define CAAM_CTPR_LS_SSL_TLS_SHIFT (7U)
14041#define CAAM_CTPR_LS_SSL_TLS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SSL_TLS_SHIFT)) & CAAM_CTPR_LS_SSL_TLS_MASK)
14042
14043#define CAAM_CTPR_LS_TLS_PRF_MASK (0x100U)
14044#define CAAM_CTPR_LS_TLS_PRF_SHIFT (8U)
14049#define CAAM_CTPR_LS_TLS_PRF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_TLS_PRF_SHIFT)) & CAAM_CTPR_LS_TLS_PRF_MASK)
14050
14051#define CAAM_CTPR_LS_MACSEC_MASK (0x200U)
14052#define CAAM_CTPR_LS_MACSEC_SHIFT (9U)
14057#define CAAM_CTPR_LS_MACSEC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MACSEC_SHIFT)) & CAAM_CTPR_LS_MACSEC_MASK)
14058
14059#define CAAM_CTPR_LS_RSA_MASK (0x400U)
14060#define CAAM_CTPR_LS_RSA_SHIFT (10U)
14065#define CAAM_CTPR_LS_RSA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_RSA_SHIFT)) & CAAM_CTPR_LS_RSA_MASK)
14066
14067#define CAAM_CTPR_LS_P3G_LTE_MASK (0x800U)
14068#define CAAM_CTPR_LS_P3G_LTE_SHIFT (11U)
14073#define CAAM_CTPR_LS_P3G_LTE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_P3G_LTE_SHIFT)) & CAAM_CTPR_LS_P3G_LTE_MASK)
14074
14075#define CAAM_CTPR_LS_DBL_CRC_MASK (0x1000U)
14076#define CAAM_CTPR_LS_DBL_CRC_SHIFT (12U)
14081#define CAAM_CTPR_LS_DBL_CRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DBL_CRC_SHIFT)) & CAAM_CTPR_LS_DBL_CRC_MASK)
14082
14083#define CAAM_CTPR_LS_MAN_PROT_MASK (0x2000U)
14084#define CAAM_CTPR_LS_MAN_PROT_SHIFT (13U)
14089#define CAAM_CTPR_LS_MAN_PROT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MAN_PROT_SHIFT)) & CAAM_CTPR_LS_MAN_PROT_MASK)
14090
14091#define CAAM_CTPR_LS_DKP_MASK (0x4000U)
14092#define CAAM_CTPR_LS_DKP_SHIFT (14U)
14097#define CAAM_CTPR_LS_DKP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DKP_SHIFT)) & CAAM_CTPR_LS_DKP_MASK)
14103#define CAAM_SMSTA_STATE_MASK (0xFU)
14104#define CAAM_SMSTA_STATE_SHIFT (0U)
14111#define CAAM_SMSTA_STATE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_STATE_SHIFT)) & CAAM_SMSTA_STATE_MASK)
14112
14113#define CAAM_SMSTA_ACCERR_MASK (0xF0U)
14114#define CAAM_SMSTA_ACCERR_SHIFT (4U)
14131#define CAAM_SMSTA_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_ACCERR_SHIFT)) & CAAM_SMSTA_ACCERR_MASK)
14132
14133#define CAAM_SMSTA_DID_MASK (0xF00U)
14134#define CAAM_SMSTA_DID_SHIFT (8U)
14135#define CAAM_SMSTA_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_DID_SHIFT)) & CAAM_SMSTA_DID_MASK)
14136
14137#define CAAM_SMSTA_NS_MASK (0x1000U)
14138#define CAAM_SMSTA_NS_SHIFT (12U)
14139#define CAAM_SMSTA_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_NS_SHIFT)) & CAAM_SMSTA_NS_MASK)
14140
14141#define CAAM_SMSTA_SMR_WP_MASK (0x8000U)
14142#define CAAM_SMSTA_SMR_WP_SHIFT (15U)
14143#define CAAM_SMSTA_SMR_WP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_SMR_WP_SHIFT)) & CAAM_SMSTA_SMR_WP_MASK)
14144
14145#define CAAM_SMSTA_PAGE_MASK (0x7FF0000U)
14146#define CAAM_SMSTA_PAGE_SHIFT (16U)
14147#define CAAM_SMSTA_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PAGE_SHIFT)) & CAAM_SMSTA_PAGE_MASK)
14148
14149#define CAAM_SMSTA_PART_MASK (0xF0000000U)
14150#define CAAM_SMSTA_PART_SHIFT (28U)
14151#define CAAM_SMSTA_PART(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PART_SHIFT)) & CAAM_SMSTA_PART_MASK)
14157#define CAAM_SMPO_PO0_MASK (0x3U)
14158#define CAAM_SMPO_PO0_SHIFT (0U)
14172#define CAAM_SMPO_PO0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO0_SHIFT)) & CAAM_SMPO_PO0_MASK)
14173
14174#define CAAM_SMPO_PO1_MASK (0xCU)
14175#define CAAM_SMPO_PO1_SHIFT (2U)
14176#define CAAM_SMPO_PO1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO1_SHIFT)) & CAAM_SMPO_PO1_MASK)
14177
14178#define CAAM_SMPO_PO2_MASK (0x30U)
14179#define CAAM_SMPO_PO2_SHIFT (4U)
14180#define CAAM_SMPO_PO2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO2_SHIFT)) & CAAM_SMPO_PO2_MASK)
14181
14182#define CAAM_SMPO_PO3_MASK (0xC0U)
14183#define CAAM_SMPO_PO3_SHIFT (6U)
14184#define CAAM_SMPO_PO3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO3_SHIFT)) & CAAM_SMPO_PO3_MASK)
14185
14186#define CAAM_SMPO_PO4_MASK (0x300U)
14187#define CAAM_SMPO_PO4_SHIFT (8U)
14188#define CAAM_SMPO_PO4(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO4_SHIFT)) & CAAM_SMPO_PO4_MASK)
14189
14190#define CAAM_SMPO_PO5_MASK (0xC00U)
14191#define CAAM_SMPO_PO5_SHIFT (10U)
14192#define CAAM_SMPO_PO5(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO5_SHIFT)) & CAAM_SMPO_PO5_MASK)
14193
14194#define CAAM_SMPO_PO6_MASK (0x3000U)
14195#define CAAM_SMPO_PO6_SHIFT (12U)
14196#define CAAM_SMPO_PO6(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO6_SHIFT)) & CAAM_SMPO_PO6_MASK)
14197
14198#define CAAM_SMPO_PO7_MASK (0xC000U)
14199#define CAAM_SMPO_PO7_SHIFT (14U)
14200#define CAAM_SMPO_PO7(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO7_SHIFT)) & CAAM_SMPO_PO7_MASK)
14201
14202#define CAAM_SMPO_PO8_MASK (0x30000U)
14203#define CAAM_SMPO_PO8_SHIFT (16U)
14204#define CAAM_SMPO_PO8(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO8_SHIFT)) & CAAM_SMPO_PO8_MASK)
14205
14206#define CAAM_SMPO_PO9_MASK (0xC0000U)
14207#define CAAM_SMPO_PO9_SHIFT (18U)
14208#define CAAM_SMPO_PO9(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO9_SHIFT)) & CAAM_SMPO_PO9_MASK)
14209
14210#define CAAM_SMPO_PO10_MASK (0x300000U)
14211#define CAAM_SMPO_PO10_SHIFT (20U)
14212#define CAAM_SMPO_PO10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO10_SHIFT)) & CAAM_SMPO_PO10_MASK)
14213
14214#define CAAM_SMPO_PO11_MASK (0xC00000U)
14215#define CAAM_SMPO_PO11_SHIFT (22U)
14216#define CAAM_SMPO_PO11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO11_SHIFT)) & CAAM_SMPO_PO11_MASK)
14217
14218#define CAAM_SMPO_PO12_MASK (0x3000000U)
14219#define CAAM_SMPO_PO12_SHIFT (24U)
14220#define CAAM_SMPO_PO12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO12_SHIFT)) & CAAM_SMPO_PO12_MASK)
14221
14222#define CAAM_SMPO_PO13_MASK (0xC000000U)
14223#define CAAM_SMPO_PO13_SHIFT (26U)
14224#define CAAM_SMPO_PO13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO13_SHIFT)) & CAAM_SMPO_PO13_MASK)
14225
14226#define CAAM_SMPO_PO14_MASK (0x30000000U)
14227#define CAAM_SMPO_PO14_SHIFT (28U)
14228#define CAAM_SMPO_PO14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO14_SHIFT)) & CAAM_SMPO_PO14_MASK)
14229
14230#define CAAM_SMPO_PO15_MASK (0xC0000000U)
14231#define CAAM_SMPO_PO15_SHIFT (30U)
14232#define CAAM_SMPO_PO15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO15_SHIFT)) & CAAM_SMPO_PO15_MASK)
14238#define CAAM_FAR_FAR_MASK (0xFFFFFFFFFU)
14239#define CAAM_FAR_FAR_SHIFT (0U)
14240#define CAAM_FAR_FAR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_FAR_FAR_SHIFT)) & CAAM_FAR_FAR_MASK)
14246#define CAAM_FADID_FDID_MASK (0xFU)
14247#define CAAM_FADID_FDID_SHIFT (0U)
14248#define CAAM_FADID_FDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FDID_SHIFT)) & CAAM_FADID_FDID_MASK)
14249
14250#define CAAM_FADID_FNS_MASK (0x10U)
14251#define CAAM_FADID_FNS_SHIFT (4U)
14252#define CAAM_FADID_FNS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FNS_SHIFT)) & CAAM_FADID_FNS_MASK)
14253
14254#define CAAM_FADID_FICID_MASK (0xFFE0U)
14255#define CAAM_FADID_FICID_SHIFT (5U)
14256#define CAAM_FADID_FICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FICID_SHIFT)) & CAAM_FADID_FICID_MASK)
14262#define CAAM_FADR_FSZ_MASK (0x7FU)
14263#define CAAM_FADR_FSZ_SHIFT (0U)
14264#define CAAM_FADR_FSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_SHIFT)) & CAAM_FADR_FSZ_MASK)
14265
14266#define CAAM_FADR_TYP_MASK (0x80U)
14267#define CAAM_FADR_TYP_SHIFT (7U)
14272#define CAAM_FADR_TYP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_TYP_SHIFT)) & CAAM_FADR_TYP_MASK)
14273
14274#define CAAM_FADR_BLKID_MASK (0xF00U)
14275#define CAAM_FADR_BLKID_SHIFT (8U)
14281#define CAAM_FADR_BLKID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_BLKID_SHIFT)) & CAAM_FADR_BLKID_MASK)
14282
14283#define CAAM_FADR_JSRC_MASK (0x7000U)
14284#define CAAM_FADR_JSRC_SHIFT (12U)
14295#define CAAM_FADR_JSRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_JSRC_SHIFT)) & CAAM_FADR_JSRC_MASK)
14296
14297#define CAAM_FADR_DTYP_MASK (0x8000U)
14298#define CAAM_FADR_DTYP_SHIFT (15U)
14303#define CAAM_FADR_DTYP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_DTYP_SHIFT)) & CAAM_FADR_DTYP_MASK)
14304
14305#define CAAM_FADR_FSZ_EXT_MASK (0x70000U)
14306#define CAAM_FADR_FSZ_EXT_SHIFT (16U)
14307#define CAAM_FADR_FSZ_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_EXT_SHIFT)) & CAAM_FADR_FSZ_EXT_MASK)
14308
14309#define CAAM_FADR_FKMOD_MASK (0x1000000U)
14310#define CAAM_FADR_FKMOD_SHIFT (24U)
14315#define CAAM_FADR_FKMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKMOD_SHIFT)) & CAAM_FADR_FKMOD_MASK)
14316
14317#define CAAM_FADR_FKEY_MASK (0x2000000U)
14318#define CAAM_FADR_FKEY_SHIFT (25U)
14323#define CAAM_FADR_FKEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKEY_SHIFT)) & CAAM_FADR_FKEY_MASK)
14324
14325#define CAAM_FADR_FTDSC_MASK (0x4000000U)
14326#define CAAM_FADR_FTDSC_SHIFT (26U)
14331#define CAAM_FADR_FTDSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FTDSC_SHIFT)) & CAAM_FADR_FTDSC_MASK)
14332
14333#define CAAM_FADR_FBNDG_MASK (0x8000000U)
14334#define CAAM_FADR_FBNDG_SHIFT (27U)
14339#define CAAM_FADR_FBNDG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FBNDG_SHIFT)) & CAAM_FADR_FBNDG_MASK)
14340
14341#define CAAM_FADR_FNS_MASK (0x10000000U)
14342#define CAAM_FADR_FNS_SHIFT (28U)
14347#define CAAM_FADR_FNS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FNS_SHIFT)) & CAAM_FADR_FNS_MASK)
14348
14349#define CAAM_FADR_FERR_MASK (0xC0000000U)
14350#define CAAM_FADR_FERR_SHIFT (30U)
14357#define CAAM_FADR_FERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FERR_SHIFT)) & CAAM_FADR_FERR_MASK)
14363#define CAAM_CSTA_BSY_MASK (0x1U)
14364#define CAAM_CSTA_BSY_SHIFT (0U)
14365#define CAAM_CSTA_BSY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_BSY_SHIFT)) & CAAM_CSTA_BSY_MASK)
14366
14367#define CAAM_CSTA_IDLE_MASK (0x2U)
14368#define CAAM_CSTA_IDLE_SHIFT (1U)
14369#define CAAM_CSTA_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_IDLE_SHIFT)) & CAAM_CSTA_IDLE_MASK)
14370
14371#define CAAM_CSTA_TRNG_IDLE_MASK (0x4U)
14372#define CAAM_CSTA_TRNG_IDLE_SHIFT (2U)
14373#define CAAM_CSTA_TRNG_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_TRNG_IDLE_SHIFT)) & CAAM_CSTA_TRNG_IDLE_MASK)
14374
14375#define CAAM_CSTA_MOO_MASK (0x300U)
14376#define CAAM_CSTA_MOO_SHIFT (8U)
14383#define CAAM_CSTA_MOO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_MOO_SHIFT)) & CAAM_CSTA_MOO_MASK)
14384
14385#define CAAM_CSTA_PLEND_MASK (0x400U)
14386#define CAAM_CSTA_PLEND_SHIFT (10U)
14391#define CAAM_CSTA_PLEND(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_PLEND_SHIFT)) & CAAM_CSTA_PLEND_MASK)
14397#define CAAM_SMVID_MS_NPAG_MASK (0x3FFU)
14398#define CAAM_SMVID_MS_NPAG_SHIFT (0U)
14399#define CAAM_SMVID_MS_NPAG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPAG_SHIFT)) & CAAM_SMVID_MS_NPAG_MASK)
14400
14401#define CAAM_SMVID_MS_NPRT_MASK (0xF000U)
14402#define CAAM_SMVID_MS_NPRT_SHIFT (12U)
14403#define CAAM_SMVID_MS_NPRT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPRT_SHIFT)) & CAAM_SMVID_MS_NPRT_MASK)
14404
14405#define CAAM_SMVID_MS_MAX_NPAG_MASK (0x3FF0000U)
14406#define CAAM_SMVID_MS_MAX_NPAG_SHIFT (16U)
14407#define CAAM_SMVID_MS_MAX_NPAG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_MAX_NPAG_SHIFT)) & CAAM_SMVID_MS_MAX_NPAG_MASK)
14413#define CAAM_SMVID_LS_SMNV_MASK (0xFFU)
14414#define CAAM_SMVID_LS_SMNV_SHIFT (0U)
14415#define CAAM_SMVID_LS_SMNV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMNV_SHIFT)) & CAAM_SMVID_LS_SMNV_MASK)
14416
14417#define CAAM_SMVID_LS_SMJV_MASK (0xFF00U)
14418#define CAAM_SMVID_LS_SMJV_SHIFT (8U)
14419#define CAAM_SMVID_LS_SMJV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMJV_SHIFT)) & CAAM_SMVID_LS_SMJV_MASK)
14420
14421#define CAAM_SMVID_LS_PSIZ_MASK (0x70000U)
14422#define CAAM_SMVID_LS_PSIZ_SHIFT (16U)
14423#define CAAM_SMVID_LS_PSIZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_PSIZ_SHIFT)) & CAAM_SMVID_LS_PSIZ_MASK)
14429#define CAAM_RVID_RMNV_MASK (0xFFU)
14430#define CAAM_RVID_RMNV_SHIFT (0U)
14431#define CAAM_RVID_RMNV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMNV_SHIFT)) & CAAM_RVID_RMNV_MASK)
14432
14433#define CAAM_RVID_RMJV_MASK (0xFF00U)
14434#define CAAM_RVID_RMJV_SHIFT (8U)
14435#define CAAM_RVID_RMJV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMJV_SHIFT)) & CAAM_RVID_RMJV_MASK)
14436
14437#define CAAM_RVID_SHA_256_MASK (0x20000U)
14438#define CAAM_RVID_SHA_256_SHIFT (17U)
14443#define CAAM_RVID_SHA_256(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_256_SHIFT)) & CAAM_RVID_SHA_256_MASK)
14444
14445#define CAAM_RVID_SHA_512_MASK (0x80000U)
14446#define CAAM_RVID_SHA_512_SHIFT (19U)
14451#define CAAM_RVID_SHA_512(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_512_SHIFT)) & CAAM_RVID_SHA_512_MASK)
14452
14453#define CAAM_RVID_MA_MASK (0x1000000U)
14454#define CAAM_RVID_MA_SHIFT (24U)
14455#define CAAM_RVID_MA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MA_SHIFT)) & CAAM_RVID_MA_MASK)
14456
14457#define CAAM_RVID_MB_MASK (0x2000000U)
14458#define CAAM_RVID_MB_SHIFT (25U)
14459#define CAAM_RVID_MB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MB_SHIFT)) & CAAM_RVID_MB_MASK)
14460
14461#define CAAM_RVID_MC_MASK (0x4000000U)
14462#define CAAM_RVID_MC_SHIFT (26U)
14463#define CAAM_RVID_MC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MC_SHIFT)) & CAAM_RVID_MC_MASK)
14464
14465#define CAAM_RVID_MD_MASK (0x8000000U)
14466#define CAAM_RVID_MD_SHIFT (27U)
14467#define CAAM_RVID_MD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MD_SHIFT)) & CAAM_RVID_MD_MASK)
14473#define CAAM_CCBVID_AMNV_MASK (0xFFU)
14474#define CAAM_CCBVID_AMNV_SHIFT (0U)
14475#define CAAM_CCBVID_AMNV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMNV_SHIFT)) & CAAM_CCBVID_AMNV_MASK)
14476
14477#define CAAM_CCBVID_AMJV_MASK (0xFF00U)
14478#define CAAM_CCBVID_AMJV_SHIFT (8U)
14479#define CAAM_CCBVID_AMJV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMJV_SHIFT)) & CAAM_CCBVID_AMJV_MASK)
14480
14481#define CAAM_CCBVID_CAAM_ERA_MASK (0xFF000000U)
14482#define CAAM_CCBVID_CAAM_ERA_SHIFT (24U)
14483#define CAAM_CCBVID_CAAM_ERA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_CAAM_ERA_SHIFT)) & CAAM_CCBVID_CAAM_ERA_MASK)
14489#define CAAM_CHAVID_MS_CRCVID_MASK (0xFU)
14490#define CAAM_CHAVID_MS_CRCVID_SHIFT (0U)
14491#define CAAM_CHAVID_MS_CRCVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_CRCVID_SHIFT)) & CAAM_CHAVID_MS_CRCVID_MASK)
14492
14493#define CAAM_CHAVID_MS_SNW9VID_MASK (0xF0U)
14494#define CAAM_CHAVID_MS_SNW9VID_SHIFT (4U)
14495#define CAAM_CHAVID_MS_SNW9VID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_SNW9VID_SHIFT)) & CAAM_CHAVID_MS_SNW9VID_MASK)
14496
14497#define CAAM_CHAVID_MS_ZEVID_MASK (0xF00U)
14498#define CAAM_CHAVID_MS_ZEVID_SHIFT (8U)
14499#define CAAM_CHAVID_MS_ZEVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZEVID_SHIFT)) & CAAM_CHAVID_MS_ZEVID_MASK)
14500
14501#define CAAM_CHAVID_MS_ZAVID_MASK (0xF000U)
14502#define CAAM_CHAVID_MS_ZAVID_SHIFT (12U)
14503#define CAAM_CHAVID_MS_ZAVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZAVID_SHIFT)) & CAAM_CHAVID_MS_ZAVID_MASK)
14504
14505#define CAAM_CHAVID_MS_DECOVID_MASK (0xF000000U)
14506#define CAAM_CHAVID_MS_DECOVID_SHIFT (24U)
14507#define CAAM_CHAVID_MS_DECOVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_DECOVID_SHIFT)) & CAAM_CHAVID_MS_DECOVID_MASK)
14508
14509#define CAAM_CHAVID_MS_JRVID_MASK (0xF0000000U)
14510#define CAAM_CHAVID_MS_JRVID_SHIFT (28U)
14511#define CAAM_CHAVID_MS_JRVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_JRVID_SHIFT)) & CAAM_CHAVID_MS_JRVID_MASK)
14517#define CAAM_CHAVID_LS_AESVID_MASK (0xFU)
14518#define CAAM_CHAVID_LS_AESVID_SHIFT (0U)
14523#define CAAM_CHAVID_LS_AESVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_AESVID_SHIFT)) & CAAM_CHAVID_LS_AESVID_MASK)
14524
14525#define CAAM_CHAVID_LS_DESVID_MASK (0xF0U)
14526#define CAAM_CHAVID_LS_DESVID_SHIFT (4U)
14527#define CAAM_CHAVID_LS_DESVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_DESVID_SHIFT)) & CAAM_CHAVID_LS_DESVID_MASK)
14528
14529#define CAAM_CHAVID_LS_MDVID_MASK (0xF000U)
14530#define CAAM_CHAVID_LS_MDVID_SHIFT (12U)
14537#define CAAM_CHAVID_LS_MDVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_MDVID_SHIFT)) & CAAM_CHAVID_LS_MDVID_MASK)
14538
14539#define CAAM_CHAVID_LS_RNGVID_MASK (0xF0000U)
14540#define CAAM_CHAVID_LS_RNGVID_SHIFT (16U)
14545#define CAAM_CHAVID_LS_RNGVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_RNGVID_SHIFT)) & CAAM_CHAVID_LS_RNGVID_MASK)
14546
14547#define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U)
14548#define CAAM_CHAVID_LS_SNW8VID_SHIFT (20U)
14549#define CAAM_CHAVID_LS_SNW8VID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
14550
14551#define CAAM_CHAVID_LS_KASVID_MASK (0xF000000U)
14552#define CAAM_CHAVID_LS_KASVID_SHIFT (24U)
14553#define CAAM_CHAVID_LS_KASVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_KASVID_SHIFT)) & CAAM_CHAVID_LS_KASVID_MASK)
14554
14555#define CAAM_CHAVID_LS_PKVID_MASK (0xF0000000U)
14556#define CAAM_CHAVID_LS_PKVID_SHIFT (28U)
14563#define CAAM_CHAVID_LS_PKVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_PKVID_SHIFT)) & CAAM_CHAVID_LS_PKVID_MASK)
14569#define CAAM_CHANUM_MS_CRCNUM_MASK (0xFU)
14570#define CAAM_CHANUM_MS_CRCNUM_SHIFT (0U)
14571#define CAAM_CHANUM_MS_CRCNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_CRCNUM_SHIFT)) & CAAM_CHANUM_MS_CRCNUM_MASK)
14572
14573#define CAAM_CHANUM_MS_SNW9NUM_MASK (0xF0U)
14574#define CAAM_CHANUM_MS_SNW9NUM_SHIFT (4U)
14575#define CAAM_CHANUM_MS_SNW9NUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_SNW9NUM_SHIFT)) & CAAM_CHANUM_MS_SNW9NUM_MASK)
14576
14577#define CAAM_CHANUM_MS_ZENUM_MASK (0xF00U)
14578#define CAAM_CHANUM_MS_ZENUM_SHIFT (8U)
14579#define CAAM_CHANUM_MS_ZENUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZENUM_SHIFT)) & CAAM_CHANUM_MS_ZENUM_MASK)
14580
14581#define CAAM_CHANUM_MS_ZANUM_MASK (0xF000U)
14582#define CAAM_CHANUM_MS_ZANUM_SHIFT (12U)
14583#define CAAM_CHANUM_MS_ZANUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZANUM_SHIFT)) & CAAM_CHANUM_MS_ZANUM_MASK)
14584
14585#define CAAM_CHANUM_MS_DECONUM_MASK (0xF000000U)
14586#define CAAM_CHANUM_MS_DECONUM_SHIFT (24U)
14587#define CAAM_CHANUM_MS_DECONUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_DECONUM_SHIFT)) & CAAM_CHANUM_MS_DECONUM_MASK)
14588
14589#define CAAM_CHANUM_MS_JRNUM_MASK (0xF0000000U)
14590#define CAAM_CHANUM_MS_JRNUM_SHIFT (28U)
14591#define CAAM_CHANUM_MS_JRNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_JRNUM_SHIFT)) & CAAM_CHANUM_MS_JRNUM_MASK)
14597#define CAAM_CHANUM_LS_AESNUM_MASK (0xFU)
14598#define CAAM_CHANUM_LS_AESNUM_SHIFT (0U)
14599#define CAAM_CHANUM_LS_AESNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_AESNUM_SHIFT)) & CAAM_CHANUM_LS_AESNUM_MASK)
14600
14601#define CAAM_CHANUM_LS_DESNUM_MASK (0xF0U)
14602#define CAAM_CHANUM_LS_DESNUM_SHIFT (4U)
14603#define CAAM_CHANUM_LS_DESNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_DESNUM_SHIFT)) & CAAM_CHANUM_LS_DESNUM_MASK)
14604
14605#define CAAM_CHANUM_LS_ARC4NUM_MASK (0xF00U)
14606#define CAAM_CHANUM_LS_ARC4NUM_SHIFT (8U)
14607#define CAAM_CHANUM_LS_ARC4NUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_ARC4NUM_SHIFT)) & CAAM_CHANUM_LS_ARC4NUM_MASK)
14608
14609#define CAAM_CHANUM_LS_MDNUM_MASK (0xF000U)
14610#define CAAM_CHANUM_LS_MDNUM_SHIFT (12U)
14611#define CAAM_CHANUM_LS_MDNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_MDNUM_SHIFT)) & CAAM_CHANUM_LS_MDNUM_MASK)
14612
14613#define CAAM_CHANUM_LS_RNGNUM_MASK (0xF0000U)
14614#define CAAM_CHANUM_LS_RNGNUM_SHIFT (16U)
14615#define CAAM_CHANUM_LS_RNGNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_RNGNUM_SHIFT)) & CAAM_CHANUM_LS_RNGNUM_MASK)
14616
14617#define CAAM_CHANUM_LS_SNW8NUM_MASK (0xF00000U)
14618#define CAAM_CHANUM_LS_SNW8NUM_SHIFT (20U)
14619#define CAAM_CHANUM_LS_SNW8NUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_SNW8NUM_SHIFT)) & CAAM_CHANUM_LS_SNW8NUM_MASK)
14620
14621#define CAAM_CHANUM_LS_KASNUM_MASK (0xF000000U)
14622#define CAAM_CHANUM_LS_KASNUM_SHIFT (24U)
14623#define CAAM_CHANUM_LS_KASNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_KASNUM_SHIFT)) & CAAM_CHANUM_LS_KASNUM_MASK)
14624
14625#define CAAM_CHANUM_LS_PKNUM_MASK (0xF0000000U)
14626#define CAAM_CHANUM_LS_PKNUM_SHIFT (28U)
14627#define CAAM_CHANUM_LS_PKNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_PKNUM_SHIFT)) & CAAM_CHANUM_LS_PKNUM_MASK)
14633#define CAAM_IRBAR_JR_IRBA_MASK (0xFFFFFFFFFU)
14634#define CAAM_IRBAR_JR_IRBA_SHIFT (0U)
14635#define CAAM_IRBAR_JR_IRBA(x) (((uint64_t)(((uint64_t)(x)) << CAAM_IRBAR_JR_IRBA_SHIFT)) & CAAM_IRBAR_JR_IRBA_MASK)
14638/* The count of CAAM_IRBAR_JR */
14639#define CAAM_IRBAR_JR_COUNT (4U)
14640
14644#define CAAM_IRSR_JR_IRS_MASK (0x3FFU)
14645#define CAAM_IRSR_JR_IRS_SHIFT (0U)
14646#define CAAM_IRSR_JR_IRS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRSR_JR_IRS_SHIFT)) & CAAM_IRSR_JR_IRS_MASK)
14649/* The count of CAAM_IRSR_JR */
14650#define CAAM_IRSR_JR_COUNT (4U)
14651
14655#define CAAM_IRSAR_JR_IRSA_MASK (0x3FFU)
14656#define CAAM_IRSAR_JR_IRSA_SHIFT (0U)
14657#define CAAM_IRSAR_JR_IRSA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRSAR_JR_IRSA_SHIFT)) & CAAM_IRSAR_JR_IRSA_MASK)
14660/* The count of CAAM_IRSAR_JR */
14661#define CAAM_IRSAR_JR_COUNT (4U)
14662
14666#define CAAM_IRJAR_JR_IRJA_MASK (0x3FFU)
14667#define CAAM_IRJAR_JR_IRJA_SHIFT (0U)
14668#define CAAM_IRJAR_JR_IRJA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRJAR_JR_IRJA_SHIFT)) & CAAM_IRJAR_JR_IRJA_MASK)
14671/* The count of CAAM_IRJAR_JR */
14672#define CAAM_IRJAR_JR_COUNT (4U)
14673
14677#define CAAM_ORBAR_JR_ORBA_MASK (0xFFFFFFFFFU)
14678#define CAAM_ORBAR_JR_ORBA_SHIFT (0U)
14679#define CAAM_ORBAR_JR_ORBA(x) (((uint64_t)(((uint64_t)(x)) << CAAM_ORBAR_JR_ORBA_SHIFT)) & CAAM_ORBAR_JR_ORBA_MASK)
14682/* The count of CAAM_ORBAR_JR */
14683#define CAAM_ORBAR_JR_COUNT (4U)
14684
14688#define CAAM_ORSR_JR_ORS_MASK (0x3FFU)
14689#define CAAM_ORSR_JR_ORS_SHIFT (0U)
14690#define CAAM_ORSR_JR_ORS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORSR_JR_ORS_SHIFT)) & CAAM_ORSR_JR_ORS_MASK)
14693/* The count of CAAM_ORSR_JR */
14694#define CAAM_ORSR_JR_COUNT (4U)
14695
14699#define CAAM_ORJRR_JR_ORJR_MASK (0x3FFU)
14700#define CAAM_ORJRR_JR_ORJR_SHIFT (0U)
14701#define CAAM_ORJRR_JR_ORJR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORJRR_JR_ORJR_SHIFT)) & CAAM_ORJRR_JR_ORJR_MASK)
14704/* The count of CAAM_ORJRR_JR */
14705#define CAAM_ORJRR_JR_COUNT (4U)
14706
14710#define CAAM_ORSFR_JR_ORSF_MASK (0x3FFU)
14711#define CAAM_ORSFR_JR_ORSF_SHIFT (0U)
14712#define CAAM_ORSFR_JR_ORSF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORSFR_JR_ORSF_SHIFT)) & CAAM_ORSFR_JR_ORSF_MASK)
14715/* The count of CAAM_ORSFR_JR */
14716#define CAAM_ORSFR_JR_COUNT (4U)
14717
14721#define CAAM_JRSTAR_JR_SSED_MASK (0xFFFFFFFU)
14722#define CAAM_JRSTAR_JR_SSED_SHIFT (0U)
14723#define CAAM_JRSTAR_JR_SSED(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSED_SHIFT)) & CAAM_JRSTAR_JR_SSED_MASK)
14724
14725#define CAAM_JRSTAR_JR_SSRC_MASK (0xF0000000U)
14726#define CAAM_JRSTAR_JR_SSRC_SHIFT (28U)
14737#define CAAM_JRSTAR_JR_SSRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSRC_SHIFT)) & CAAM_JRSTAR_JR_SSRC_MASK)
14740/* The count of CAAM_JRSTAR_JR */
14741#define CAAM_JRSTAR_JR_COUNT (4U)
14742
14746#define CAAM_JRINTR_JR_JRI_MASK (0x1U)
14747#define CAAM_JRINTR_JR_JRI_SHIFT (0U)
14748#define CAAM_JRINTR_JR_JRI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRI_SHIFT)) & CAAM_JRINTR_JR_JRI_MASK)
14749
14750#define CAAM_JRINTR_JR_JRE_MASK (0x2U)
14751#define CAAM_JRINTR_JR_JRE_SHIFT (1U)
14752#define CAAM_JRINTR_JR_JRE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRE_SHIFT)) & CAAM_JRINTR_JR_JRE_MASK)
14753
14754#define CAAM_JRINTR_JR_HALT_MASK (0xCU)
14755#define CAAM_JRINTR_JR_HALT_SHIFT (2U)
14756#define CAAM_JRINTR_JR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_HALT_SHIFT)) & CAAM_JRINTR_JR_HALT_MASK)
14757
14758#define CAAM_JRINTR_JR_ENTER_FAIL_MASK (0x10U)
14759#define CAAM_JRINTR_JR_ENTER_FAIL_SHIFT (4U)
14760#define CAAM_JRINTR_JR_ENTER_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ENTER_FAIL_SHIFT)) & CAAM_JRINTR_JR_ENTER_FAIL_MASK)
14761
14762#define CAAM_JRINTR_JR_EXIT_FAIL_MASK (0x20U)
14763#define CAAM_JRINTR_JR_EXIT_FAIL_SHIFT (5U)
14764#define CAAM_JRINTR_JR_EXIT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_EXIT_FAIL_SHIFT)) & CAAM_JRINTR_JR_EXIT_FAIL_MASK)
14765
14766#define CAAM_JRINTR_JR_ERR_TYPE_MASK (0x1F00U)
14767#define CAAM_JRINTR_JR_ERR_TYPE_SHIFT (8U)
14792#define CAAM_JRINTR_JR_ERR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_TYPE_SHIFT)) & CAAM_JRINTR_JR_ERR_TYPE_MASK)
14793
14794#define CAAM_JRINTR_JR_ERR_ORWI_MASK (0x3FFF0000U)
14795#define CAAM_JRINTR_JR_ERR_ORWI_SHIFT (16U)
14796#define CAAM_JRINTR_JR_ERR_ORWI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_ORWI_SHIFT)) & CAAM_JRINTR_JR_ERR_ORWI_MASK)
14799/* The count of CAAM_JRINTR_JR */
14800#define CAAM_JRINTR_JR_COUNT (4U)
14801
14805#define CAAM_JRCFGR_JR_MS_MBSI_MASK (0x1U)
14806#define CAAM_JRCFGR_JR_MS_MBSI_SHIFT (0U)
14807#define CAAM_JRCFGR_JR_MS_MBSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSI_MASK)
14808
14809#define CAAM_JRCFGR_JR_MS_MHWSI_MASK (0x2U)
14810#define CAAM_JRCFGR_JR_MS_MHWSI_SHIFT (1U)
14811#define CAAM_JRCFGR_JR_MS_MHWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSI_MASK)
14812
14813#define CAAM_JRCFGR_JR_MS_MWSI_MASK (0x4U)
14814#define CAAM_JRCFGR_JR_MS_MWSI_SHIFT (2U)
14815#define CAAM_JRCFGR_JR_MS_MWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSI_MASK)
14816
14817#define CAAM_JRCFGR_JR_MS_CBSI_MASK (0x10U)
14818#define CAAM_JRCFGR_JR_MS_CBSI_SHIFT (4U)
14819#define CAAM_JRCFGR_JR_MS_CBSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSI_MASK)
14820
14821#define CAAM_JRCFGR_JR_MS_CHWSI_MASK (0x20U)
14822#define CAAM_JRCFGR_JR_MS_CHWSI_SHIFT (5U)
14823#define CAAM_JRCFGR_JR_MS_CHWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSI_MASK)
14824
14825#define CAAM_JRCFGR_JR_MS_CWSI_MASK (0x40U)
14826#define CAAM_JRCFGR_JR_MS_CWSI_SHIFT (6U)
14827#define CAAM_JRCFGR_JR_MS_CWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSI_MASK)
14828
14829#define CAAM_JRCFGR_JR_MS_MBSO_MASK (0x100U)
14830#define CAAM_JRCFGR_JR_MS_MBSO_SHIFT (8U)
14831#define CAAM_JRCFGR_JR_MS_MBSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSO_MASK)
14832
14833#define CAAM_JRCFGR_JR_MS_MHWSO_MASK (0x200U)
14834#define CAAM_JRCFGR_JR_MS_MHWSO_SHIFT (9U)
14835#define CAAM_JRCFGR_JR_MS_MHWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSO_MASK)
14836
14837#define CAAM_JRCFGR_JR_MS_MWSO_MASK (0x400U)
14838#define CAAM_JRCFGR_JR_MS_MWSO_SHIFT (10U)
14839#define CAAM_JRCFGR_JR_MS_MWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSO_MASK)
14840
14841#define CAAM_JRCFGR_JR_MS_CBSO_MASK (0x1000U)
14842#define CAAM_JRCFGR_JR_MS_CBSO_SHIFT (12U)
14843#define CAAM_JRCFGR_JR_MS_CBSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSO_MASK)
14844
14845#define CAAM_JRCFGR_JR_MS_CHWSO_MASK (0x2000U)
14846#define CAAM_JRCFGR_JR_MS_CHWSO_SHIFT (13U)
14847#define CAAM_JRCFGR_JR_MS_CHWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSO_MASK)
14848
14849#define CAAM_JRCFGR_JR_MS_CWSO_MASK (0x4000U)
14850#define CAAM_JRCFGR_JR_MS_CWSO_SHIFT (14U)
14851#define CAAM_JRCFGR_JR_MS_CWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSO_MASK)
14852
14853#define CAAM_JRCFGR_JR_MS_DMBS_MASK (0x10000U)
14854#define CAAM_JRCFGR_JR_MS_DMBS_SHIFT (16U)
14855#define CAAM_JRCFGR_JR_MS_DMBS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DMBS_SHIFT)) & CAAM_JRCFGR_JR_MS_DMBS_MASK)
14856
14857#define CAAM_JRCFGR_JR_MS_PEO_MASK (0x20000U)
14858#define CAAM_JRCFGR_JR_MS_PEO_SHIFT (17U)
14859#define CAAM_JRCFGR_JR_MS_PEO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_PEO_SHIFT)) & CAAM_JRCFGR_JR_MS_PEO_MASK)
14860
14861#define CAAM_JRCFGR_JR_MS_DWSO_MASK (0x40000U)
14862#define CAAM_JRCFGR_JR_MS_DWSO_SHIFT (18U)
14863#define CAAM_JRCFGR_JR_MS_DWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_DWSO_MASK)
14864
14865#define CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK (0x20000000U)
14866#define CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT (29U)
14867#define CAAM_JRCFGR_JR_MS_FAIL_MODE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT)) & CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK)
14868
14869#define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK (0x40000000U)
14870#define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT (30U)
14871#define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT)) & CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK)
14874/* The count of CAAM_JRCFGR_JR_MS */
14875#define CAAM_JRCFGR_JR_MS_COUNT (4U)
14876
14880#define CAAM_JRCFGR_JR_LS_IMSK_MASK (0x1U)
14881#define CAAM_JRCFGR_JR_LS_IMSK_SHIFT (0U)
14886#define CAAM_JRCFGR_JR_LS_IMSK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_IMSK_SHIFT)) & CAAM_JRCFGR_JR_LS_IMSK_MASK)
14887
14888#define CAAM_JRCFGR_JR_LS_ICEN_MASK (0x2U)
14889#define CAAM_JRCFGR_JR_LS_ICEN_SHIFT (1U)
14900#define CAAM_JRCFGR_JR_LS_ICEN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICEN_SHIFT)) & CAAM_JRCFGR_JR_LS_ICEN_MASK)
14901
14902#define CAAM_JRCFGR_JR_LS_ICDCT_MASK (0xFF00U)
14903#define CAAM_JRCFGR_JR_LS_ICDCT_SHIFT (8U)
14904#define CAAM_JRCFGR_JR_LS_ICDCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICDCT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICDCT_MASK)
14905
14906#define CAAM_JRCFGR_JR_LS_ICTT_MASK (0xFFFF0000U)
14907#define CAAM_JRCFGR_JR_LS_ICTT_SHIFT (16U)
14908#define CAAM_JRCFGR_JR_LS_ICTT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICTT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICTT_MASK)
14911/* The count of CAAM_JRCFGR_JR_LS */
14912#define CAAM_JRCFGR_JR_LS_COUNT (4U)
14913
14917#define CAAM_IRRIR_JR_IRRI_MASK (0x1FFFU)
14918#define CAAM_IRRIR_JR_IRRI_SHIFT (0U)
14919#define CAAM_IRRIR_JR_IRRI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRRIR_JR_IRRI_SHIFT)) & CAAM_IRRIR_JR_IRRI_MASK)
14922/* The count of CAAM_IRRIR_JR */
14923#define CAAM_IRRIR_JR_COUNT (4U)
14924
14928#define CAAM_ORWIR_JR_ORWI_MASK (0x3FFFU)
14929#define CAAM_ORWIR_JR_ORWI_SHIFT (0U)
14930#define CAAM_ORWIR_JR_ORWI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORWIR_JR_ORWI_SHIFT)) & CAAM_ORWIR_JR_ORWI_MASK)
14933/* The count of CAAM_ORWIR_JR */
14934#define CAAM_ORWIR_JR_COUNT (4U)
14935
14939#define CAAM_JRCR_JR_RESET_MASK (0x1U)
14940#define CAAM_JRCR_JR_RESET_SHIFT (0U)
14941#define CAAM_JRCR_JR_RESET(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_RESET_SHIFT)) & CAAM_JRCR_JR_RESET_MASK)
14942
14943#define CAAM_JRCR_JR_PARK_MASK (0x2U)
14944#define CAAM_JRCR_JR_PARK_SHIFT (1U)
14945#define CAAM_JRCR_JR_PARK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_PARK_SHIFT)) & CAAM_JRCR_JR_PARK_MASK)
14948/* The count of CAAM_JRCR_JR */
14949#define CAAM_JRCR_JR_COUNT (4U)
14950
14954#define CAAM_JRAAV_V0_MASK (0x1U)
14955#define CAAM_JRAAV_V0_SHIFT (0U)
14956#define CAAM_JRAAV_V0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V0_SHIFT)) & CAAM_JRAAV_V0_MASK)
14957
14958#define CAAM_JRAAV_V1_MASK (0x2U)
14959#define CAAM_JRAAV_V1_SHIFT (1U)
14960#define CAAM_JRAAV_V1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V1_SHIFT)) & CAAM_JRAAV_V1_MASK)
14961
14962#define CAAM_JRAAV_V2_MASK (0x4U)
14963#define CAAM_JRAAV_V2_SHIFT (2U)
14964#define CAAM_JRAAV_V2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V2_SHIFT)) & CAAM_JRAAV_V2_MASK)
14965
14966#define CAAM_JRAAV_V3_MASK (0x8U)
14967#define CAAM_JRAAV_V3_SHIFT (3U)
14968#define CAAM_JRAAV_V3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V3_SHIFT)) & CAAM_JRAAV_V3_MASK)
14969
14970#define CAAM_JRAAV_BC_MASK (0x80000000U)
14971#define CAAM_JRAAV_BC_SHIFT (31U)
14972#define CAAM_JRAAV_BC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_BC_SHIFT)) & CAAM_JRAAV_BC_MASK)
14975/* The count of CAAM_JRAAV */
14976#define CAAM_JRAAV_COUNT (4U)
14977
14981#define CAAM_JRAAA_JD_ADDR_MASK (0xFFFFFFFFFU)
14982#define CAAM_JRAAA_JD_ADDR_SHIFT (0U)
14983#define CAAM_JRAAA_JD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_JRAAA_JD_ADDR_SHIFT)) & CAAM_JRAAA_JD_ADDR_MASK)
14986/* The count of CAAM_JRAAA */
14987#define CAAM_JRAAA_COUNT (4U)
14988
14989/* The count of CAAM_JRAAA */
14990#define CAAM_JRAAA_COUNT2 (4U)
14991
14995#define CAAM_PX_SDID_JR_SDID_MASK (0xFFFFU)
14996#define CAAM_PX_SDID_JR_SDID_SHIFT (0U)
14997#define CAAM_PX_SDID_JR_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_JR_SDID_SHIFT)) & CAAM_PX_SDID_JR_SDID_MASK)
15000/* The count of CAAM_PX_SDID_JR */
15001#define CAAM_PX_SDID_JR_COUNT (4U)
15002
15003/* The count of CAAM_PX_SDID_JR */
15004#define CAAM_PX_SDID_JR_COUNT2 (16U)
15005
15009#define CAAM_PX_SMAPR_JR_G1_READ_MASK (0x1U)
15010#define CAAM_PX_SMAPR_JR_G1_READ_SHIFT (0U)
15018#define CAAM_PX_SMAPR_JR_G1_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G1_READ_MASK)
15019
15020#define CAAM_PX_SMAPR_JR_G1_WRITE_MASK (0x2U)
15021#define CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT (1U)
15028#define CAAM_PX_SMAPR_JR_G1_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G1_WRITE_MASK)
15029
15030#define CAAM_PX_SMAPR_JR_G1_TDO_MASK (0x4U)
15031#define CAAM_PX_SMAPR_JR_G1_TDO_SHIFT (2U)
15038#define CAAM_PX_SMAPR_JR_G1_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G1_TDO_MASK)
15039
15040#define CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK (0x8U)
15041#define CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT (3U)
15046#define CAAM_PX_SMAPR_JR_G1_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK)
15047
15048#define CAAM_PX_SMAPR_JR_G2_READ_MASK (0x10U)
15049#define CAAM_PX_SMAPR_JR_G2_READ_SHIFT (4U)
15057#define CAAM_PX_SMAPR_JR_G2_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G2_READ_MASK)
15058
15059#define CAAM_PX_SMAPR_JR_G2_WRITE_MASK (0x20U)
15060#define CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT (5U)
15067#define CAAM_PX_SMAPR_JR_G2_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G2_WRITE_MASK)
15068
15069#define CAAM_PX_SMAPR_JR_G2_TDO_MASK (0x40U)
15070#define CAAM_PX_SMAPR_JR_G2_TDO_SHIFT (6U)
15077#define CAAM_PX_SMAPR_JR_G2_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G2_TDO_MASK)
15078
15079#define CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK (0x80U)
15080#define CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT (7U)
15085#define CAAM_PX_SMAPR_JR_G2_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK)
15086
15087#define CAAM_PX_SMAPR_JR_SMAG_LCK_MASK (0x1000U)
15088#define CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT (12U)
15094#define CAAM_PX_SMAPR_JR_SMAG_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAG_LCK_MASK)
15095
15096#define CAAM_PX_SMAPR_JR_SMAP_LCK_MASK (0x2000U)
15097#define CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT (13U)
15104#define CAAM_PX_SMAPR_JR_SMAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAP_LCK_MASK)
15105
15106#define CAAM_PX_SMAPR_JR_PSP_MASK (0x4000U)
15107#define CAAM_PX_SMAPR_JR_PSP_SHIFT (14U)
15112#define CAAM_PX_SMAPR_JR_PSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PSP_SHIFT)) & CAAM_PX_SMAPR_JR_PSP_MASK)
15113
15114#define CAAM_PX_SMAPR_JR_CSP_MASK (0x8000U)
15115#define CAAM_PX_SMAPR_JR_CSP_SHIFT (15U)
15122#define CAAM_PX_SMAPR_JR_CSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_CSP_SHIFT)) & CAAM_PX_SMAPR_JR_CSP_MASK)
15123
15124#define CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK (0xFFFF0000U)
15125#define CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT (16U)
15126#define CAAM_PX_SMAPR_JR_PARTITION_KMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK)
15129/* The count of CAAM_PX_SMAPR_JR */
15130#define CAAM_PX_SMAPR_JR_COUNT (4U)
15131
15132/* The count of CAAM_PX_SMAPR_JR */
15133#define CAAM_PX_SMAPR_JR_COUNT2 (16U)
15134
15138#define CAAM_PX_SMAG2_JR_Gx_ID00_MASK (0x1U)
15139#define CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT (0U)
15140#define CAAM_PX_SMAG2_JR_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID00_MASK)
15141
15142#define CAAM_PX_SMAG2_JR_Gx_ID01_MASK (0x2U)
15143#define CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT (1U)
15144#define CAAM_PX_SMAG2_JR_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID01_MASK)
15145
15146#define CAAM_PX_SMAG2_JR_Gx_ID02_MASK (0x4U)
15147#define CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT (2U)
15148#define CAAM_PX_SMAG2_JR_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID02_MASK)
15149
15150#define CAAM_PX_SMAG2_JR_Gx_ID03_MASK (0x8U)
15151#define CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT (3U)
15152#define CAAM_PX_SMAG2_JR_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID03_MASK)
15153
15154#define CAAM_PX_SMAG2_JR_Gx_ID04_MASK (0x10U)
15155#define CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT (4U)
15156#define CAAM_PX_SMAG2_JR_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID04_MASK)
15157
15158#define CAAM_PX_SMAG2_JR_Gx_ID05_MASK (0x20U)
15159#define CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT (5U)
15160#define CAAM_PX_SMAG2_JR_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID05_MASK)
15161
15162#define CAAM_PX_SMAG2_JR_Gx_ID06_MASK (0x40U)
15163#define CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT (6U)
15164#define CAAM_PX_SMAG2_JR_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID06_MASK)
15165
15166#define CAAM_PX_SMAG2_JR_Gx_ID07_MASK (0x80U)
15167#define CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT (7U)
15168#define CAAM_PX_SMAG2_JR_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID07_MASK)
15169
15170#define CAAM_PX_SMAG2_JR_Gx_ID08_MASK (0x100U)
15171#define CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT (8U)
15172#define CAAM_PX_SMAG2_JR_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID08_MASK)
15173
15174#define CAAM_PX_SMAG2_JR_Gx_ID09_MASK (0x200U)
15175#define CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT (9U)
15176#define CAAM_PX_SMAG2_JR_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID09_MASK)
15177
15178#define CAAM_PX_SMAG2_JR_Gx_ID10_MASK (0x400U)
15179#define CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT (10U)
15180#define CAAM_PX_SMAG2_JR_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID10_MASK)
15181
15182#define CAAM_PX_SMAG2_JR_Gx_ID11_MASK (0x800U)
15183#define CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT (11U)
15184#define CAAM_PX_SMAG2_JR_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID11_MASK)
15185
15186#define CAAM_PX_SMAG2_JR_Gx_ID12_MASK (0x1000U)
15187#define CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT (12U)
15188#define CAAM_PX_SMAG2_JR_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID12_MASK)
15189
15190#define CAAM_PX_SMAG2_JR_Gx_ID13_MASK (0x2000U)
15191#define CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT (13U)
15192#define CAAM_PX_SMAG2_JR_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID13_MASK)
15193
15194#define CAAM_PX_SMAG2_JR_Gx_ID14_MASK (0x4000U)
15195#define CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT (14U)
15196#define CAAM_PX_SMAG2_JR_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID14_MASK)
15197
15198#define CAAM_PX_SMAG2_JR_Gx_ID15_MASK (0x8000U)
15199#define CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT (15U)
15200#define CAAM_PX_SMAG2_JR_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID15_MASK)
15201
15202#define CAAM_PX_SMAG2_JR_Gx_ID16_MASK (0x10000U)
15203#define CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT (16U)
15204#define CAAM_PX_SMAG2_JR_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID16_MASK)
15205
15206#define CAAM_PX_SMAG2_JR_Gx_ID17_MASK (0x20000U)
15207#define CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT (17U)
15208#define CAAM_PX_SMAG2_JR_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID17_MASK)
15209
15210#define CAAM_PX_SMAG2_JR_Gx_ID18_MASK (0x40000U)
15211#define CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT (18U)
15212#define CAAM_PX_SMAG2_JR_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID18_MASK)
15213
15214#define CAAM_PX_SMAG2_JR_Gx_ID19_MASK (0x80000U)
15215#define CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT (19U)
15216#define CAAM_PX_SMAG2_JR_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID19_MASK)
15217
15218#define CAAM_PX_SMAG2_JR_Gx_ID20_MASK (0x100000U)
15219#define CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT (20U)
15220#define CAAM_PX_SMAG2_JR_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID20_MASK)
15221
15222#define CAAM_PX_SMAG2_JR_Gx_ID21_MASK (0x200000U)
15223#define CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT (21U)
15224#define CAAM_PX_SMAG2_JR_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID21_MASK)
15225
15226#define CAAM_PX_SMAG2_JR_Gx_ID22_MASK (0x400000U)
15227#define CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT (22U)
15228#define CAAM_PX_SMAG2_JR_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID22_MASK)
15229
15230#define CAAM_PX_SMAG2_JR_Gx_ID23_MASK (0x800000U)
15231#define CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT (23U)
15232#define CAAM_PX_SMAG2_JR_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID23_MASK)
15233
15234#define CAAM_PX_SMAG2_JR_Gx_ID24_MASK (0x1000000U)
15235#define CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT (24U)
15236#define CAAM_PX_SMAG2_JR_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID24_MASK)
15237
15238#define CAAM_PX_SMAG2_JR_Gx_ID25_MASK (0x2000000U)
15239#define CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT (25U)
15240#define CAAM_PX_SMAG2_JR_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID25_MASK)
15241
15242#define CAAM_PX_SMAG2_JR_Gx_ID26_MASK (0x4000000U)
15243#define CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT (26U)
15244#define CAAM_PX_SMAG2_JR_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID26_MASK)
15245
15246#define CAAM_PX_SMAG2_JR_Gx_ID27_MASK (0x8000000U)
15247#define CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT (27U)
15248#define CAAM_PX_SMAG2_JR_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID27_MASK)
15249
15250#define CAAM_PX_SMAG2_JR_Gx_ID28_MASK (0x10000000U)
15251#define CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT (28U)
15252#define CAAM_PX_SMAG2_JR_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID28_MASK)
15253
15254#define CAAM_PX_SMAG2_JR_Gx_ID29_MASK (0x20000000U)
15255#define CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT (29U)
15256#define CAAM_PX_SMAG2_JR_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID29_MASK)
15257
15258#define CAAM_PX_SMAG2_JR_Gx_ID30_MASK (0x40000000U)
15259#define CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT (30U)
15260#define CAAM_PX_SMAG2_JR_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID30_MASK)
15261
15262#define CAAM_PX_SMAG2_JR_Gx_ID31_MASK (0x80000000U)
15263#define CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT (31U)
15264#define CAAM_PX_SMAG2_JR_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID31_MASK)
15267/* The count of CAAM_PX_SMAG2_JR */
15268#define CAAM_PX_SMAG2_JR_COUNT (4U)
15269
15270/* The count of CAAM_PX_SMAG2_JR */
15271#define CAAM_PX_SMAG2_JR_COUNT2 (16U)
15272
15276#define CAAM_PX_SMAG1_JR_Gx_ID00_MASK (0x1U)
15277#define CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT (0U)
15278#define CAAM_PX_SMAG1_JR_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID00_MASK)
15279
15280#define CAAM_PX_SMAG1_JR_Gx_ID01_MASK (0x2U)
15281#define CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT (1U)
15282#define CAAM_PX_SMAG1_JR_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID01_MASK)
15283
15284#define CAAM_PX_SMAG1_JR_Gx_ID02_MASK (0x4U)
15285#define CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT (2U)
15286#define CAAM_PX_SMAG1_JR_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID02_MASK)
15287
15288#define CAAM_PX_SMAG1_JR_Gx_ID03_MASK (0x8U)
15289#define CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT (3U)
15290#define CAAM_PX_SMAG1_JR_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID03_MASK)
15291
15292#define CAAM_PX_SMAG1_JR_Gx_ID04_MASK (0x10U)
15293#define CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT (4U)
15294#define CAAM_PX_SMAG1_JR_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID04_MASK)
15295
15296#define CAAM_PX_SMAG1_JR_Gx_ID05_MASK (0x20U)
15297#define CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT (5U)
15298#define CAAM_PX_SMAG1_JR_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID05_MASK)
15299
15300#define CAAM_PX_SMAG1_JR_Gx_ID06_MASK (0x40U)
15301#define CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT (6U)
15302#define CAAM_PX_SMAG1_JR_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID06_MASK)
15303
15304#define CAAM_PX_SMAG1_JR_Gx_ID07_MASK (0x80U)
15305#define CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT (7U)
15306#define CAAM_PX_SMAG1_JR_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID07_MASK)
15307
15308#define CAAM_PX_SMAG1_JR_Gx_ID08_MASK (0x100U)
15309#define CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT (8U)
15310#define CAAM_PX_SMAG1_JR_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID08_MASK)
15311
15312#define CAAM_PX_SMAG1_JR_Gx_ID09_MASK (0x200U)
15313#define CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT (9U)
15314#define CAAM_PX_SMAG1_JR_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID09_MASK)
15315
15316#define CAAM_PX_SMAG1_JR_Gx_ID10_MASK (0x400U)
15317#define CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT (10U)
15318#define CAAM_PX_SMAG1_JR_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID10_MASK)
15319
15320#define CAAM_PX_SMAG1_JR_Gx_ID11_MASK (0x800U)
15321#define CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT (11U)
15322#define CAAM_PX_SMAG1_JR_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID11_MASK)
15323
15324#define CAAM_PX_SMAG1_JR_Gx_ID12_MASK (0x1000U)
15325#define CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT (12U)
15326#define CAAM_PX_SMAG1_JR_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID12_MASK)
15327
15328#define CAAM_PX_SMAG1_JR_Gx_ID13_MASK (0x2000U)
15329#define CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT (13U)
15330#define CAAM_PX_SMAG1_JR_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID13_MASK)
15331
15332#define CAAM_PX_SMAG1_JR_Gx_ID14_MASK (0x4000U)
15333#define CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT (14U)
15334#define CAAM_PX_SMAG1_JR_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID14_MASK)
15335
15336#define CAAM_PX_SMAG1_JR_Gx_ID15_MASK (0x8000U)
15337#define CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT (15U)
15338#define CAAM_PX_SMAG1_JR_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID15_MASK)
15339
15340#define CAAM_PX_SMAG1_JR_Gx_ID16_MASK (0x10000U)
15341#define CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT (16U)
15342#define CAAM_PX_SMAG1_JR_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID16_MASK)
15343
15344#define CAAM_PX_SMAG1_JR_Gx_ID17_MASK (0x20000U)
15345#define CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT (17U)
15346#define CAAM_PX_SMAG1_JR_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID17_MASK)
15347
15348#define CAAM_PX_SMAG1_JR_Gx_ID18_MASK (0x40000U)
15349#define CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT (18U)
15350#define CAAM_PX_SMAG1_JR_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID18_MASK)
15351
15352#define CAAM_PX_SMAG1_JR_Gx_ID19_MASK (0x80000U)
15353#define CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT (19U)
15354#define CAAM_PX_SMAG1_JR_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID19_MASK)
15355
15356#define CAAM_PX_SMAG1_JR_Gx_ID20_MASK (0x100000U)
15357#define CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT (20U)
15358#define CAAM_PX_SMAG1_JR_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID20_MASK)
15359
15360#define CAAM_PX_SMAG1_JR_Gx_ID21_MASK (0x200000U)
15361#define CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT (21U)
15362#define CAAM_PX_SMAG1_JR_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID21_MASK)
15363
15364#define CAAM_PX_SMAG1_JR_Gx_ID22_MASK (0x400000U)
15365#define CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT (22U)
15366#define CAAM_PX_SMAG1_JR_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID22_MASK)
15367
15368#define CAAM_PX_SMAG1_JR_Gx_ID23_MASK (0x800000U)
15369#define CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT (23U)
15370#define CAAM_PX_SMAG1_JR_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID23_MASK)
15371
15372#define CAAM_PX_SMAG1_JR_Gx_ID24_MASK (0x1000000U)
15373#define CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT (24U)
15374#define CAAM_PX_SMAG1_JR_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID24_MASK)
15375
15376#define CAAM_PX_SMAG1_JR_Gx_ID25_MASK (0x2000000U)
15377#define CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT (25U)
15378#define CAAM_PX_SMAG1_JR_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID25_MASK)
15379
15380#define CAAM_PX_SMAG1_JR_Gx_ID26_MASK (0x4000000U)
15381#define CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT (26U)
15382#define CAAM_PX_SMAG1_JR_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID26_MASK)
15383
15384#define CAAM_PX_SMAG1_JR_Gx_ID27_MASK (0x8000000U)
15385#define CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT (27U)
15386#define CAAM_PX_SMAG1_JR_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID27_MASK)
15387
15388#define CAAM_PX_SMAG1_JR_Gx_ID28_MASK (0x10000000U)
15389#define CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT (28U)
15390#define CAAM_PX_SMAG1_JR_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID28_MASK)
15391
15392#define CAAM_PX_SMAG1_JR_Gx_ID29_MASK (0x20000000U)
15393#define CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT (29U)
15394#define CAAM_PX_SMAG1_JR_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID29_MASK)
15395
15396#define CAAM_PX_SMAG1_JR_Gx_ID30_MASK (0x40000000U)
15397#define CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT (30U)
15398#define CAAM_PX_SMAG1_JR_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID30_MASK)
15399
15400#define CAAM_PX_SMAG1_JR_Gx_ID31_MASK (0x80000000U)
15401#define CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT (31U)
15402#define CAAM_PX_SMAG1_JR_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID31_MASK)
15405/* The count of CAAM_PX_SMAG1_JR */
15406#define CAAM_PX_SMAG1_JR_COUNT (4U)
15407
15408/* The count of CAAM_PX_SMAG1_JR */
15409#define CAAM_PX_SMAG1_JR_COUNT2 (16U)
15410
15414#define CAAM_SMCR_JR_CMD_MASK (0xFU)
15415#define CAAM_SMCR_JR_CMD_SHIFT (0U)
15416#define CAAM_SMCR_JR_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_CMD_SHIFT)) & CAAM_SMCR_JR_CMD_MASK)
15417
15418#define CAAM_SMCR_JR_PRTN_MASK (0xF00U)
15419#define CAAM_SMCR_JR_PRTN_SHIFT (8U)
15420#define CAAM_SMCR_JR_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PRTN_SHIFT)) & CAAM_SMCR_JR_PRTN_MASK)
15421
15422#define CAAM_SMCR_JR_PAGE_MASK (0xFFFF0000U)
15423#define CAAM_SMCR_JR_PAGE_SHIFT (16U)
15424#define CAAM_SMCR_JR_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PAGE_SHIFT)) & CAAM_SMCR_JR_PAGE_MASK)
15427/* The count of CAAM_SMCR_JR */
15428#define CAAM_SMCR_JR_COUNT (4U)
15429
15433#define CAAM_SMCSR_JR_PRTN_MASK (0xFU)
15434#define CAAM_SMCSR_JR_PRTN_SHIFT (0U)
15435#define CAAM_SMCSR_JR_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PRTN_SHIFT)) & CAAM_SMCSR_JR_PRTN_MASK)
15436
15437#define CAAM_SMCSR_JR_PO_MASK (0xC0U)
15438#define CAAM_SMCSR_JR_PO_SHIFT (6U)
15448#define CAAM_SMCSR_JR_PO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PO_SHIFT)) & CAAM_SMCSR_JR_PO_MASK)
15449
15450#define CAAM_SMCSR_JR_AERR_MASK (0x3000U)
15451#define CAAM_SMCSR_JR_AERR_SHIFT (12U)
15452#define CAAM_SMCSR_JR_AERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_AERR_SHIFT)) & CAAM_SMCSR_JR_AERR_MASK)
15453
15454#define CAAM_SMCSR_JR_CERR_MASK (0xC000U)
15455#define CAAM_SMCSR_JR_CERR_SHIFT (14U)
15463#define CAAM_SMCSR_JR_CERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_CERR_SHIFT)) & CAAM_SMCSR_JR_CERR_MASK)
15464
15465#define CAAM_SMCSR_JR_PAGE_MASK (0xFFF0000U)
15466#define CAAM_SMCSR_JR_PAGE_SHIFT (16U)
15467#define CAAM_SMCSR_JR_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PAGE_SHIFT)) & CAAM_SMCSR_JR_PAGE_MASK)
15470/* The count of CAAM_SMCSR_JR */
15471#define CAAM_SMCSR_JR_COUNT (4U)
15472
15476#define CAAM_REIR0JR_TYPE_MASK (0x3000000U)
15477#define CAAM_REIR0JR_TYPE_SHIFT (24U)
15478#define CAAM_REIR0JR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_TYPE_SHIFT)) & CAAM_REIR0JR_TYPE_MASK)
15479
15480#define CAAM_REIR0JR_MISS_MASK (0x80000000U)
15481#define CAAM_REIR0JR_MISS_SHIFT (31U)
15482#define CAAM_REIR0JR_MISS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_MISS_SHIFT)) & CAAM_REIR0JR_MISS_MASK)
15485/* The count of CAAM_REIR0JR */
15486#define CAAM_REIR0JR_COUNT (4U)
15487
15491#define CAAM_REIR2JR_ADDR_MASK (0xFFFFFFFFFU)
15492#define CAAM_REIR2JR_ADDR_SHIFT (0U)
15493#define CAAM_REIR2JR_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2JR_ADDR_SHIFT)) & CAAM_REIR2JR_ADDR_MASK)
15496/* The count of CAAM_REIR2JR */
15497#define CAAM_REIR2JR_COUNT (4U)
15498
15502#define CAAM_REIR4JR_ICID_MASK (0x7FFU)
15503#define CAAM_REIR4JR_ICID_SHIFT (0U)
15504#define CAAM_REIR4JR_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ICID_SHIFT)) & CAAM_REIR4JR_ICID_MASK)
15505
15506#define CAAM_REIR4JR_DID_MASK (0x7800U)
15507#define CAAM_REIR4JR_DID_SHIFT (11U)
15508#define CAAM_REIR4JR_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_DID_SHIFT)) & CAAM_REIR4JR_DID_MASK)
15509
15510#define CAAM_REIR4JR_AXCACHE_MASK (0xF0000U)
15511#define CAAM_REIR4JR_AXCACHE_SHIFT (16U)
15512#define CAAM_REIR4JR_AXCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXCACHE_SHIFT)) & CAAM_REIR4JR_AXCACHE_MASK)
15513
15514#define CAAM_REIR4JR_AXPROT_MASK (0x700000U)
15515#define CAAM_REIR4JR_AXPROT_SHIFT (20U)
15516#define CAAM_REIR4JR_AXPROT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXPROT_SHIFT)) & CAAM_REIR4JR_AXPROT_MASK)
15517
15518#define CAAM_REIR4JR_RWB_MASK (0x800000U)
15519#define CAAM_REIR4JR_RWB_SHIFT (23U)
15520#define CAAM_REIR4JR_RWB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_RWB_SHIFT)) & CAAM_REIR4JR_RWB_MASK)
15521
15522#define CAAM_REIR4JR_ERR_MASK (0x30000000U)
15523#define CAAM_REIR4JR_ERR_SHIFT (28U)
15524#define CAAM_REIR4JR_ERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ERR_SHIFT)) & CAAM_REIR4JR_ERR_MASK)
15525
15526#define CAAM_REIR4JR_MIX_MASK (0xC0000000U)
15527#define CAAM_REIR4JR_MIX_SHIFT (30U)
15528#define CAAM_REIR4JR_MIX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_MIX_SHIFT)) & CAAM_REIR4JR_MIX_MASK)
15531/* The count of CAAM_REIR4JR */
15532#define CAAM_REIR4JR_COUNT (4U)
15533
15537#define CAAM_REIR5JR_BID_MASK (0xF0000U)
15538#define CAAM_REIR5JR_BID_SHIFT (16U)
15539#define CAAM_REIR5JR_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BID_SHIFT)) & CAAM_REIR5JR_BID_MASK)
15540
15541#define CAAM_REIR5JR_BNDG_MASK (0x2000000U)
15542#define CAAM_REIR5JR_BNDG_SHIFT (25U)
15543#define CAAM_REIR5JR_BNDG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BNDG_SHIFT)) & CAAM_REIR5JR_BNDG_MASK)
15544
15545#define CAAM_REIR5JR_TDSC_MASK (0x4000000U)
15546#define CAAM_REIR5JR_TDSC_SHIFT (26U)
15547#define CAAM_REIR5JR_TDSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_TDSC_SHIFT)) & CAAM_REIR5JR_TDSC_MASK)
15548
15549#define CAAM_REIR5JR_KMOD_MASK (0x8000000U)
15550#define CAAM_REIR5JR_KMOD_SHIFT (27U)
15551#define CAAM_REIR5JR_KMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KMOD_SHIFT)) & CAAM_REIR5JR_KMOD_MASK)
15552
15553#define CAAM_REIR5JR_KEY_MASK (0x10000000U)
15554#define CAAM_REIR5JR_KEY_SHIFT (28U)
15555#define CAAM_REIR5JR_KEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KEY_SHIFT)) & CAAM_REIR5JR_KEY_MASK)
15556
15557#define CAAM_REIR5JR_SMA_MASK (0x20000000U)
15558#define CAAM_REIR5JR_SMA_SHIFT (29U)
15559#define CAAM_REIR5JR_SMA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_SMA_SHIFT)) & CAAM_REIR5JR_SMA_MASK)
15562/* The count of CAAM_REIR5JR */
15563#define CAAM_REIR5JR_COUNT (4U)
15564
15568#define CAAM_RSTA_BSY_MASK (0x1U)
15569#define CAAM_RSTA_BSY_SHIFT (0U)
15574#define CAAM_RSTA_BSY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_BSY_SHIFT)) & CAAM_RSTA_BSY_MASK)
15575
15576#define CAAM_RSTA_HD_MASK (0x2U)
15577#define CAAM_RSTA_HD_SHIFT (1U)
15582#define CAAM_RSTA_HD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HD_SHIFT)) & CAAM_RSTA_HD_MASK)
15583
15584#define CAAM_RSTA_SV_MASK (0x4U)
15585#define CAAM_RSTA_SV_SHIFT (2U)
15590#define CAAM_RSTA_SV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_SV_SHIFT)) & CAAM_RSTA_SV_MASK)
15591
15592#define CAAM_RSTA_HE_MASK (0x8U)
15593#define CAAM_RSTA_HE_SHIFT (3U)
15598#define CAAM_RSTA_HE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HE_SHIFT)) & CAAM_RSTA_HE_MASK)
15599
15600#define CAAM_RSTA_MIS_MASK (0xF0U)
15601#define CAAM_RSTA_MIS_SHIFT (4U)
15606#define CAAM_RSTA_MIS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_MIS_SHIFT)) & CAAM_RSTA_MIS_MASK)
15607
15608#define CAAM_RSTA_AE_MASK (0xF00U)
15609#define CAAM_RSTA_AE_SHIFT (8U)
15614#define CAAM_RSTA_AE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_AE_SHIFT)) & CAAM_RSTA_AE_MASK)
15615
15616#define CAAM_RSTA_WE_MASK (0x10000U)
15617#define CAAM_RSTA_WE_SHIFT (16U)
15622#define CAAM_RSTA_WE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_WE_SHIFT)) & CAAM_RSTA_WE_MASK)
15623
15624#define CAAM_RSTA_ABH_MASK (0x20000U)
15625#define CAAM_RSTA_ABH_SHIFT (17U)
15626#define CAAM_RSTA_ABH(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_ABH_SHIFT)) & CAAM_RSTA_ABH_MASK)
15627
15628#define CAAM_RSTA_HOD_MASK (0x40000U)
15629#define CAAM_RSTA_HOD_SHIFT (18U)
15630#define CAAM_RSTA_HOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HOD_SHIFT)) & CAAM_RSTA_HOD_MASK)
15631
15632#define CAAM_RSTA_RTD_MASK (0x80000U)
15633#define CAAM_RSTA_RTD_SHIFT (19U)
15634#define CAAM_RSTA_RTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_RTD_SHIFT)) & CAAM_RSTA_RTD_MASK)
15635
15636#define CAAM_RSTA_CS_MASK (0x6000000U)
15637#define CAAM_RSTA_CS_SHIFT (25U)
15644#define CAAM_RSTA_CS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_CS_SHIFT)) & CAAM_RSTA_CS_MASK)
15650#define CAAM_RCMD_CINT_MASK (0x1U)
15651#define CAAM_RCMD_CINT_SHIFT (0U)
15656#define CAAM_RCMD_CINT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_CINT_SHIFT)) & CAAM_RCMD_CINT_MASK)
15657
15658#define CAAM_RCMD_HO_MASK (0x2U)
15659#define CAAM_RCMD_HO_SHIFT (1U)
15664#define CAAM_RCMD_HO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_HO_SHIFT)) & CAAM_RCMD_HO_MASK)
15665
15666#define CAAM_RCMD_RTC_MASK (0x4U)
15667#define CAAM_RCMD_RTC_SHIFT (2U)
15672#define CAAM_RCMD_RTC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTC_SHIFT)) & CAAM_RCMD_RTC_MASK)
15673
15674#define CAAM_RCMD_RTD_MASK (0x8U)
15675#define CAAM_RCMD_RTD_SHIFT (3U)
15680#define CAAM_RCMD_RTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTD_SHIFT)) & CAAM_RCMD_RTD_MASK)
15686#define CAAM_RCTL_IE_MASK (0x1U)
15687#define CAAM_RCTL_IE_SHIFT (0U)
15692#define CAAM_RCTL_IE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_IE_SHIFT)) & CAAM_RCTL_IE_MASK)
15693
15694#define CAAM_RCTL_RREQS_MASK (0xEU)
15695#define CAAM_RCTL_RREQS_SHIFT (1U)
15696#define CAAM_RCTL_RREQS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RREQS_SHIFT)) & CAAM_RCTL_RREQS_MASK)
15697
15698#define CAAM_RCTL_HOME_MASK (0xF0U)
15699#define CAAM_RCTL_HOME_SHIFT (4U)
15700#define CAAM_RCTL_HOME(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_HOME_SHIFT)) & CAAM_RCTL_HOME_MASK)
15701
15702#define CAAM_RCTL_RTME_MASK (0xF00U)
15703#define CAAM_RCTL_RTME_SHIFT (8U)
15704#define CAAM_RCTL_RTME(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTME_SHIFT)) & CAAM_RCTL_RTME_MASK)
15705
15706#define CAAM_RCTL_RTMU_MASK (0xF000U)
15707#define CAAM_RCTL_RTMU_SHIFT (12U)
15708#define CAAM_RCTL_RTMU(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTMU_SHIFT)) & CAAM_RCTL_RTMU_MASK)
15709
15710#define CAAM_RCTL_RALG_MASK (0xF0000U)
15711#define CAAM_RCTL_RALG_SHIFT (16U)
15712#define CAAM_RCTL_RALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RALG_SHIFT)) & CAAM_RCTL_RALG_MASK)
15713
15714#define CAAM_RCTL_RIDLE_MASK (0x100000U)
15715#define CAAM_RCTL_RIDLE_SHIFT (20U)
15716#define CAAM_RCTL_RIDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RIDLE_SHIFT)) & CAAM_RCTL_RIDLE_MASK)
15722#define CAAM_RTHR_RTHR_MASK (0xFFFFU)
15723#define CAAM_RTHR_RTHR_SHIFT (0U)
15724#define CAAM_RTHR_RTHR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTHR_RTHR_SHIFT)) & CAAM_RTHR_RTHR_MASK)
15730#define CAAM_RWDOG_RWDOG_MASK (0xFFFFFFFFU)
15731#define CAAM_RWDOG_RWDOG_SHIFT (0U)
15732#define CAAM_RWDOG_RWDOG(x) (((uint64_t)(((uint64_t)(x)) << CAAM_RWDOG_RWDOG_SHIFT)) & CAAM_RWDOG_RWDOG_MASK)
15738#define CAAM_REND_REPO_MASK (0xFU)
15739#define CAAM_REND_REPO_SHIFT (0U)
15746#define CAAM_REND_REPO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_REPO_SHIFT)) & CAAM_REND_REPO_MASK)
15747
15748#define CAAM_REND_RBS_MASK (0xF0U)
15749#define CAAM_REND_RBS_SHIFT (4U)
15756#define CAAM_REND_RBS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RBS_SHIFT)) & CAAM_REND_RBS_MASK)
15757
15758#define CAAM_REND_RHWS_MASK (0xF00U)
15759#define CAAM_REND_RHWS_SHIFT (8U)
15766#define CAAM_REND_RHWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RHWS_SHIFT)) & CAAM_REND_RHWS_MASK)
15767
15768#define CAAM_REND_RWS_MASK (0xF000U)
15769#define CAAM_REND_RWS_SHIFT (12U)
15776#define CAAM_REND_RWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RWS_SHIFT)) & CAAM_REND_RWS_MASK)
15782#define CAAM_RMA_MEMBLKADDR_MASK (0xFFFFFFFFFU)
15783#define CAAM_RMA_MEMBLKADDR_SHIFT (0U)
15784#define CAAM_RMA_MEMBLKADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_RMA_MEMBLKADDR_SHIFT)) & CAAM_RMA_MEMBLKADDR_MASK)
15787/* The count of CAAM_RMA */
15788#define CAAM_RMA_COUNT (4U)
15789
15790/* The count of CAAM_RMA */
15791#define CAAM_RMA_COUNT2 (2U)
15792
15796#define CAAM_RML_MEMBLKLEN_MASK (0xFFFFFFFFU)
15797#define CAAM_RML_MEMBLKLEN_SHIFT (0U)
15798#define CAAM_RML_MEMBLKLEN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RML_MEMBLKLEN_SHIFT)) & CAAM_RML_MEMBLKLEN_MASK)
15801/* The count of CAAM_RML */
15802#define CAAM_RML_COUNT (4U)
15803
15804/* The count of CAAM_RML */
15805#define CAAM_RML_COUNT2 (2U)
15806
15810#define CAAM_RMD_RTIC_Hash_Result_MASK (0xFFFFFFFFU)
15811#define CAAM_RMD_RTIC_Hash_Result_SHIFT (0U)
15812#define CAAM_RMD_RTIC_Hash_Result(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RMD_RTIC_Hash_Result_SHIFT)) & CAAM_RMD_RTIC_Hash_Result_MASK)
15815/* The count of CAAM_RMD */
15816#define CAAM_RMD_COUNT (4U)
15817
15818/* The count of CAAM_RMD */
15819#define CAAM_RMD_COUNT2 (2U)
15820
15821/* The count of CAAM_RMD */
15822#define CAAM_RMD_COUNT3 (32U)
15823
15827#define CAAM_REIR0RTIC_TYPE_MASK (0x3000000U)
15828#define CAAM_REIR0RTIC_TYPE_SHIFT (24U)
15829#define CAAM_REIR0RTIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_TYPE_SHIFT)) & CAAM_REIR0RTIC_TYPE_MASK)
15830
15831#define CAAM_REIR0RTIC_MISS_MASK (0x80000000U)
15832#define CAAM_REIR0RTIC_MISS_SHIFT (31U)
15833#define CAAM_REIR0RTIC_MISS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_MISS_SHIFT)) & CAAM_REIR0RTIC_MISS_MASK)
15839#define CAAM_REIR2RTIC_ADDR_MASK (0xFFFFFFFFFFFFFFFFU)
15840#define CAAM_REIR2RTIC_ADDR_SHIFT (0U)
15841#define CAAM_REIR2RTIC_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2RTIC_ADDR_SHIFT)) & CAAM_REIR2RTIC_ADDR_MASK)
15847#define CAAM_REIR4RTIC_ICID_MASK (0x7FFU)
15848#define CAAM_REIR4RTIC_ICID_SHIFT (0U)
15849#define CAAM_REIR4RTIC_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ICID_SHIFT)) & CAAM_REIR4RTIC_ICID_MASK)
15850
15851#define CAAM_REIR4RTIC_DID_MASK (0x7800U)
15852#define CAAM_REIR4RTIC_DID_SHIFT (11U)
15853#define CAAM_REIR4RTIC_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_DID_SHIFT)) & CAAM_REIR4RTIC_DID_MASK)
15854
15855#define CAAM_REIR4RTIC_AXCACHE_MASK (0xF0000U)
15856#define CAAM_REIR4RTIC_AXCACHE_SHIFT (16U)
15857#define CAAM_REIR4RTIC_AXCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXCACHE_SHIFT)) & CAAM_REIR4RTIC_AXCACHE_MASK)
15858
15859#define CAAM_REIR4RTIC_AXPROT_MASK (0x700000U)
15860#define CAAM_REIR4RTIC_AXPROT_SHIFT (20U)
15861#define CAAM_REIR4RTIC_AXPROT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXPROT_SHIFT)) & CAAM_REIR4RTIC_AXPROT_MASK)
15862
15863#define CAAM_REIR4RTIC_RWB_MASK (0x800000U)
15864#define CAAM_REIR4RTIC_RWB_SHIFT (23U)
15865#define CAAM_REIR4RTIC_RWB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_RWB_SHIFT)) & CAAM_REIR4RTIC_RWB_MASK)
15866
15867#define CAAM_REIR4RTIC_ERR_MASK (0x30000000U)
15868#define CAAM_REIR4RTIC_ERR_SHIFT (28U)
15869#define CAAM_REIR4RTIC_ERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ERR_SHIFT)) & CAAM_REIR4RTIC_ERR_MASK)
15870
15871#define CAAM_REIR4RTIC_MIX_MASK (0xC0000000U)
15872#define CAAM_REIR4RTIC_MIX_SHIFT (30U)
15873#define CAAM_REIR4RTIC_MIX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_MIX_SHIFT)) & CAAM_REIR4RTIC_MIX_MASK)
15879#define CAAM_REIR5RTIC_BID_MASK (0xF0000U)
15880#define CAAM_REIR5RTIC_BID_SHIFT (16U)
15881#define CAAM_REIR5RTIC_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_BID_SHIFT)) & CAAM_REIR5RTIC_BID_MASK)
15882
15883#define CAAM_REIR5RTIC_SAFE_MASK (0x1000000U)
15884#define CAAM_REIR5RTIC_SAFE_SHIFT (24U)
15885#define CAAM_REIR5RTIC_SAFE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SAFE_SHIFT)) & CAAM_REIR5RTIC_SAFE_MASK)
15886
15887#define CAAM_REIR5RTIC_SMA_MASK (0x2000000U)
15888#define CAAM_REIR5RTIC_SMA_SHIFT (25U)
15889#define CAAM_REIR5RTIC_SMA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SMA_SHIFT)) & CAAM_REIR5RTIC_SMA_MASK)
15895#define CAAM_CC1MR_ENC_MASK (0x1U)
15896#define CAAM_CC1MR_ENC_SHIFT (0U)
15901#define CAAM_CC1MR_ENC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ENC_SHIFT)) & CAAM_CC1MR_ENC_MASK)
15902
15903#define CAAM_CC1MR_ICV_TEST_MASK (0x2U)
15904#define CAAM_CC1MR_ICV_TEST_SHIFT (1U)
15905#define CAAM_CC1MR_ICV_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ICV_TEST_SHIFT)) & CAAM_CC1MR_ICV_TEST_MASK)
15906
15907#define CAAM_CC1MR_AS_MASK (0xCU)
15908#define CAAM_CC1MR_AS_SHIFT (2U)
15915#define CAAM_CC1MR_AS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AS_SHIFT)) & CAAM_CC1MR_AS_MASK)
15916
15917#define CAAM_CC1MR_AAI_MASK (0x1FF0U)
15918#define CAAM_CC1MR_AAI_SHIFT (4U)
15919#define CAAM_CC1MR_AAI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AAI_SHIFT)) & CAAM_CC1MR_AAI_MASK)
15920
15921#define CAAM_CC1MR_ALG_MASK (0xFF0000U)
15922#define CAAM_CC1MR_ALG_SHIFT (16U)
15929#define CAAM_CC1MR_ALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ALG_SHIFT)) & CAAM_CC1MR_ALG_MASK)
15932/* The count of CAAM_CC1MR */
15933#define CAAM_CC1MR_COUNT (1U)
15934
15938#define CAAM_CC1MR_PK_PKHA_MODE_LS_MASK (0xFFFU)
15939#define CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT (0U)
15940#define CAAM_CC1MR_PK_PKHA_MODE_LS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_LS_MASK)
15941
15942#define CAAM_CC1MR_PK_PKHA_MODE_MS_MASK (0xF0000U)
15943#define CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT (16U)
15944#define CAAM_CC1MR_PK_PKHA_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_MS_MASK)
15947/* The count of CAAM_CC1MR_PK */
15948#define CAAM_CC1MR_PK_COUNT (1U)
15949
15953#define CAAM_CC1MR_RNG_TST_MASK (0x1U)
15954#define CAAM_CC1MR_RNG_TST_SHIFT (0U)
15955#define CAAM_CC1MR_RNG_TST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_TST_SHIFT)) & CAAM_CC1MR_RNG_TST_MASK)
15956
15957#define CAAM_CC1MR_RNG_PR_MASK (0x2U)
15958#define CAAM_CC1MR_RNG_PR_SHIFT (1U)
15959#define CAAM_CC1MR_RNG_PR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PR_SHIFT)) & CAAM_CC1MR_RNG_PR_MASK)
15960
15961#define CAAM_CC1MR_RNG_AS_MASK (0xCU)
15962#define CAAM_CC1MR_RNG_AS_SHIFT (2U)
15963#define CAAM_CC1MR_RNG_AS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AS_SHIFT)) & CAAM_CC1MR_RNG_AS_MASK)
15964
15965#define CAAM_CC1MR_RNG_SH_MASK (0x30U)
15966#define CAAM_CC1MR_RNG_SH_SHIFT (4U)
15973#define CAAM_CC1MR_RNG_SH(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SH_SHIFT)) & CAAM_CC1MR_RNG_SH_MASK)
15974
15975#define CAAM_CC1MR_RNG_NZB_MASK (0x100U)
15976#define CAAM_CC1MR_RNG_NZB_SHIFT (8U)
15981#define CAAM_CC1MR_RNG_NZB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_NZB_SHIFT)) & CAAM_CC1MR_RNG_NZB_MASK)
15982
15983#define CAAM_CC1MR_RNG_OBP_MASK (0x200U)
15984#define CAAM_CC1MR_RNG_OBP_SHIFT (9U)
15989#define CAAM_CC1MR_RNG_OBP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_OBP_SHIFT)) & CAAM_CC1MR_RNG_OBP_MASK)
15990
15991#define CAAM_CC1MR_RNG_PS_MASK (0x400U)
15992#define CAAM_CC1MR_RNG_PS_SHIFT (10U)
15997#define CAAM_CC1MR_RNG_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PS_SHIFT)) & CAAM_CC1MR_RNG_PS_MASK)
15998
15999#define CAAM_CC1MR_RNG_AI_MASK (0x800U)
16000#define CAAM_CC1MR_RNG_AI_SHIFT (11U)
16005#define CAAM_CC1MR_RNG_AI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AI_SHIFT)) & CAAM_CC1MR_RNG_AI_MASK)
16006
16007#define CAAM_CC1MR_RNG_SK_MASK (0x1000U)
16008#define CAAM_CC1MR_RNG_SK_SHIFT (12U)
16013#define CAAM_CC1MR_RNG_SK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SK_SHIFT)) & CAAM_CC1MR_RNG_SK_MASK)
16014
16015#define CAAM_CC1MR_RNG_ALG_MASK (0xFF0000U)
16016#define CAAM_CC1MR_RNG_ALG_SHIFT (16U)
16020#define CAAM_CC1MR_RNG_ALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_ALG_SHIFT)) & CAAM_CC1MR_RNG_ALG_MASK)
16023/* The count of CAAM_CC1MR_RNG */
16024#define CAAM_CC1MR_RNG_COUNT (1U)
16025
16029#define CAAM_CC1KSR_C1KS_MASK (0x7FU)
16030#define CAAM_CC1KSR_C1KS_SHIFT (0U)
16031#define CAAM_CC1KSR_C1KS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KSR_C1KS_SHIFT)) & CAAM_CC1KSR_C1KS_MASK)
16034/* The count of CAAM_CC1KSR */
16035#define CAAM_CC1KSR_COUNT (1U)
16036
16040#define CAAM_CC1DSR_C1DS_MASK (0xFFFFFFFFU)
16041#define CAAM_CC1DSR_C1DS_SHIFT (0U)
16042#define CAAM_CC1DSR_C1DS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1DS_SHIFT)) & CAAM_CC1DSR_C1DS_MASK)
16043
16044#define CAAM_CC1DSR_C1CY_MASK (0x100000000U)
16045#define CAAM_CC1DSR_C1CY_SHIFT (32U)
16050#define CAAM_CC1DSR_C1CY(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1CY_SHIFT)) & CAAM_CC1DSR_C1CY_MASK)
16051
16052#define CAAM_CC1DSR_NUMBITS_MASK (0xE000000000000000U)
16053#define CAAM_CC1DSR_NUMBITS_SHIFT (61U)
16054#define CAAM_CC1DSR_NUMBITS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_NUMBITS_SHIFT)) & CAAM_CC1DSR_NUMBITS_MASK)
16057/* The count of CAAM_CC1DSR */
16058#define CAAM_CC1DSR_COUNT (1U)
16059
16063#define CAAM_CC1ICVSR_C1ICVS_MASK (0x1FU)
16064#define CAAM_CC1ICVSR_C1ICVS_SHIFT (0U)
16065#define CAAM_CC1ICVSR_C1ICVS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1ICVSR_C1ICVS_SHIFT)) & CAAM_CC1ICVSR_C1ICVS_MASK)
16068/* The count of CAAM_CC1ICVSR */
16069#define CAAM_CC1ICVSR_COUNT (1U)
16070
16074#define CAAM_CCCTRL_CCB_MASK (0x1U)
16075#define CAAM_CCCTRL_CCB_SHIFT (0U)
16080#define CAAM_CCCTRL_CCB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CCB_SHIFT)) & CAAM_CCCTRL_CCB_MASK)
16081
16082#define CAAM_CCCTRL_AES_MASK (0x2U)
16083#define CAAM_CCCTRL_AES_SHIFT (1U)
16088#define CAAM_CCCTRL_AES(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_AES_SHIFT)) & CAAM_CCCTRL_AES_MASK)
16089
16090#define CAAM_CCCTRL_DES_MASK (0x4U)
16091#define CAAM_CCCTRL_DES_SHIFT (2U)
16096#define CAAM_CCCTRL_DES(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_DES_SHIFT)) & CAAM_CCCTRL_DES_MASK)
16097
16098#define CAAM_CCCTRL_PK_MASK (0x40U)
16099#define CAAM_CCCTRL_PK_SHIFT (6U)
16104#define CAAM_CCCTRL_PK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_PK_SHIFT)) & CAAM_CCCTRL_PK_MASK)
16105
16106#define CAAM_CCCTRL_MD_MASK (0x80U)
16107#define CAAM_CCCTRL_MD_SHIFT (7U)
16112#define CAAM_CCCTRL_MD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_MD_SHIFT)) & CAAM_CCCTRL_MD_MASK)
16113
16114#define CAAM_CCCTRL_CRC_MASK (0x100U)
16115#define CAAM_CCCTRL_CRC_SHIFT (8U)
16120#define CAAM_CCCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CRC_SHIFT)) & CAAM_CCCTRL_CRC_MASK)
16121
16122#define CAAM_CCCTRL_RNG_MASK (0x200U)
16123#define CAAM_CCCTRL_RNG_SHIFT (9U)
16128#define CAAM_CCCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_RNG_SHIFT)) & CAAM_CCCTRL_RNG_MASK)
16129
16130#define CAAM_CCCTRL_UA0_MASK (0x10000U)
16131#define CAAM_CCCTRL_UA0_SHIFT (16U)
16136#define CAAM_CCCTRL_UA0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA0_SHIFT)) & CAAM_CCCTRL_UA0_MASK)
16137
16138#define CAAM_CCCTRL_UA1_MASK (0x20000U)
16139#define CAAM_CCCTRL_UA1_SHIFT (17U)
16144#define CAAM_CCCTRL_UA1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA1_SHIFT)) & CAAM_CCCTRL_UA1_MASK)
16145
16146#define CAAM_CCCTRL_UA2_MASK (0x40000U)
16147#define CAAM_CCCTRL_UA2_SHIFT (18U)
16152#define CAAM_CCCTRL_UA2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA2_SHIFT)) & CAAM_CCCTRL_UA2_MASK)
16153
16154#define CAAM_CCCTRL_UA3_MASK (0x80000U)
16155#define CAAM_CCCTRL_UA3_SHIFT (19U)
16160#define CAAM_CCCTRL_UA3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA3_SHIFT)) & CAAM_CCCTRL_UA3_MASK)
16161
16162#define CAAM_CCCTRL_UB0_MASK (0x100000U)
16163#define CAAM_CCCTRL_UB0_SHIFT (20U)
16168#define CAAM_CCCTRL_UB0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB0_SHIFT)) & CAAM_CCCTRL_UB0_MASK)
16169
16170#define CAAM_CCCTRL_UB1_MASK (0x200000U)
16171#define CAAM_CCCTRL_UB1_SHIFT (21U)
16176#define CAAM_CCCTRL_UB1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB1_SHIFT)) & CAAM_CCCTRL_UB1_MASK)
16177
16178#define CAAM_CCCTRL_UB2_MASK (0x400000U)
16179#define CAAM_CCCTRL_UB2_SHIFT (22U)
16184#define CAAM_CCCTRL_UB2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB2_SHIFT)) & CAAM_CCCTRL_UB2_MASK)
16185
16186#define CAAM_CCCTRL_UB3_MASK (0x800000U)
16187#define CAAM_CCCTRL_UB3_SHIFT (23U)
16192#define CAAM_CCCTRL_UB3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB3_SHIFT)) & CAAM_CCCTRL_UB3_MASK)
16193
16194#define CAAM_CCCTRL_UN_MASK (0x1000000U)
16195#define CAAM_CCCTRL_UN_SHIFT (24U)
16200#define CAAM_CCCTRL_UN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UN_SHIFT)) & CAAM_CCCTRL_UN_MASK)
16201
16202#define CAAM_CCCTRL_UA_MASK (0x4000000U)
16203#define CAAM_CCCTRL_UA_SHIFT (26U)
16208#define CAAM_CCCTRL_UA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA_SHIFT)) & CAAM_CCCTRL_UA_MASK)
16209
16210#define CAAM_CCCTRL_UB_MASK (0x8000000U)
16211#define CAAM_CCCTRL_UB_SHIFT (27U)
16216#define CAAM_CCCTRL_UB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB_SHIFT)) & CAAM_CCCTRL_UB_MASK)
16219/* The count of CAAM_CCCTRL */
16220#define CAAM_CCCTRL_COUNT (1U)
16221
16225#define CAAM_CICTL_ADI_MASK (0x2U)
16226#define CAAM_CICTL_ADI_SHIFT (1U)
16227#define CAAM_CICTL_ADI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_ADI_SHIFT)) & CAAM_CICTL_ADI_MASK)
16228
16229#define CAAM_CICTL_DDI_MASK (0x4U)
16230#define CAAM_CICTL_DDI_SHIFT (2U)
16231#define CAAM_CICTL_DDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DDI_SHIFT)) & CAAM_CICTL_DDI_MASK)
16232
16233#define CAAM_CICTL_PDI_MASK (0x40U)
16234#define CAAM_CICTL_PDI_SHIFT (6U)
16235#define CAAM_CICTL_PDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PDI_SHIFT)) & CAAM_CICTL_PDI_MASK)
16236
16237#define CAAM_CICTL_MDI_MASK (0x80U)
16238#define CAAM_CICTL_MDI_SHIFT (7U)
16239#define CAAM_CICTL_MDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MDI_SHIFT)) & CAAM_CICTL_MDI_MASK)
16240
16241#define CAAM_CICTL_CDI_MASK (0x100U)
16242#define CAAM_CICTL_CDI_SHIFT (8U)
16243#define CAAM_CICTL_CDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CDI_SHIFT)) & CAAM_CICTL_CDI_MASK)
16244
16245#define CAAM_CICTL_RNDI_MASK (0x200U)
16246#define CAAM_CICTL_RNDI_SHIFT (9U)
16247#define CAAM_CICTL_RNDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNDI_SHIFT)) & CAAM_CICTL_RNDI_MASK)
16248
16249#define CAAM_CICTL_AEI_MASK (0x20000U)
16250#define CAAM_CICTL_AEI_SHIFT (17U)
16255#define CAAM_CICTL_AEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_AEI_SHIFT)) & CAAM_CICTL_AEI_MASK)
16256
16257#define CAAM_CICTL_DEI_MASK (0x40000U)
16258#define CAAM_CICTL_DEI_SHIFT (18U)
16263#define CAAM_CICTL_DEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DEI_SHIFT)) & CAAM_CICTL_DEI_MASK)
16264
16265#define CAAM_CICTL_PEI_MASK (0x400000U)
16266#define CAAM_CICTL_PEI_SHIFT (22U)
16271#define CAAM_CICTL_PEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PEI_SHIFT)) & CAAM_CICTL_PEI_MASK)
16272
16273#define CAAM_CICTL_MEI_MASK (0x800000U)
16274#define CAAM_CICTL_MEI_SHIFT (23U)
16279#define CAAM_CICTL_MEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MEI_SHIFT)) & CAAM_CICTL_MEI_MASK)
16280
16281#define CAAM_CICTL_CEI_MASK (0x1000000U)
16282#define CAAM_CICTL_CEI_SHIFT (24U)
16287#define CAAM_CICTL_CEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CEI_SHIFT)) & CAAM_CICTL_CEI_MASK)
16288
16289#define CAAM_CICTL_RNEI_MASK (0x2000000U)
16290#define CAAM_CICTL_RNEI_SHIFT (25U)
16295#define CAAM_CICTL_RNEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNEI_SHIFT)) & CAAM_CICTL_RNEI_MASK)
16298/* The count of CAAM_CICTL */
16299#define CAAM_CICTL_COUNT (1U)
16300
16304#define CAAM_CCWR_C1M_MASK (0x1U)
16305#define CAAM_CCWR_C1M_SHIFT (0U)
16310#define CAAM_CCWR_C1M(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1M_SHIFT)) & CAAM_CCWR_C1M_MASK)
16311
16312#define CAAM_CCWR_C1DS_MASK (0x4U)
16313#define CAAM_CCWR_C1DS_SHIFT (2U)
16318#define CAAM_CCWR_C1DS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1DS_SHIFT)) & CAAM_CCWR_C1DS_MASK)
16319
16320#define CAAM_CCWR_C1ICV_MASK (0x8U)
16321#define CAAM_CCWR_C1ICV_SHIFT (3U)
16326#define CAAM_CCWR_C1ICV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1ICV_SHIFT)) & CAAM_CCWR_C1ICV_MASK)
16327
16328#define CAAM_CCWR_C1C_MASK (0x20U)
16329#define CAAM_CCWR_C1C_SHIFT (5U)
16334#define CAAM_CCWR_C1C(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1C_SHIFT)) & CAAM_CCWR_C1C_MASK)
16335
16336#define CAAM_CCWR_C1K_MASK (0x40U)
16337#define CAAM_CCWR_C1K_SHIFT (6U)
16342#define CAAM_CCWR_C1K(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1K_SHIFT)) & CAAM_CCWR_C1K_MASK)
16343
16344#define CAAM_CCWR_CPKA_MASK (0x1000U)
16345#define CAAM_CCWR_CPKA_SHIFT (12U)
16350#define CAAM_CCWR_CPKA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKA_SHIFT)) & CAAM_CCWR_CPKA_MASK)
16351
16352#define CAAM_CCWR_CPKB_MASK (0x2000U)
16353#define CAAM_CCWR_CPKB_SHIFT (13U)
16358#define CAAM_CCWR_CPKB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKB_SHIFT)) & CAAM_CCWR_CPKB_MASK)
16359
16360#define CAAM_CCWR_CPKN_MASK (0x4000U)
16361#define CAAM_CCWR_CPKN_SHIFT (14U)
16366#define CAAM_CCWR_CPKN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKN_SHIFT)) & CAAM_CCWR_CPKN_MASK)
16367
16368#define CAAM_CCWR_CPKE_MASK (0x8000U)
16369#define CAAM_CCWR_CPKE_SHIFT (15U)
16374#define CAAM_CCWR_CPKE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKE_SHIFT)) & CAAM_CCWR_CPKE_MASK)
16375
16376#define CAAM_CCWR_C2M_MASK (0x10000U)
16377#define CAAM_CCWR_C2M_SHIFT (16U)
16382#define CAAM_CCWR_C2M(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2M_SHIFT)) & CAAM_CCWR_C2M_MASK)
16383
16384#define CAAM_CCWR_C2DS_MASK (0x40000U)
16385#define CAAM_CCWR_C2DS_SHIFT (18U)
16390#define CAAM_CCWR_C2DS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2DS_SHIFT)) & CAAM_CCWR_C2DS_MASK)
16391
16392#define CAAM_CCWR_C2C_MASK (0x200000U)
16393#define CAAM_CCWR_C2C_SHIFT (21U)
16398#define CAAM_CCWR_C2C(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2C_SHIFT)) & CAAM_CCWR_C2C_MASK)
16399
16400#define CAAM_CCWR_C2K_MASK (0x400000U)
16401#define CAAM_CCWR_C2K_SHIFT (22U)
16406#define CAAM_CCWR_C2K(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2K_SHIFT)) & CAAM_CCWR_C2K_MASK)
16407
16408#define CAAM_CCWR_CDS_MASK (0x2000000U)
16409#define CAAM_CCWR_CDS_SHIFT (25U)
16414#define CAAM_CCWR_CDS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CDS_SHIFT)) & CAAM_CCWR_CDS_MASK)
16415
16416#define CAAM_CCWR_C2D_MASK (0x4000000U)
16417#define CAAM_CCWR_C2D_SHIFT (26U)
16422#define CAAM_CCWR_C2D(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2D_SHIFT)) & CAAM_CCWR_C2D_MASK)
16423
16424#define CAAM_CCWR_C1D_MASK (0x8000000U)
16425#define CAAM_CCWR_C1D_SHIFT (27U)
16430#define CAAM_CCWR_C1D(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1D_SHIFT)) & CAAM_CCWR_C1D_MASK)
16431
16432#define CAAM_CCWR_C2RST_MASK (0x10000000U)
16433#define CAAM_CCWR_C2RST_SHIFT (28U)
16438#define CAAM_CCWR_C2RST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2RST_SHIFT)) & CAAM_CCWR_C2RST_MASK)
16439
16440#define CAAM_CCWR_C1RST_MASK (0x20000000U)
16441#define CAAM_CCWR_C1RST_SHIFT (29U)
16446#define CAAM_CCWR_C1RST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1RST_SHIFT)) & CAAM_CCWR_C1RST_MASK)
16447
16448#define CAAM_CCWR_COF_MASK (0x40000000U)
16449#define CAAM_CCWR_COF_SHIFT (30U)
16454#define CAAM_CCWR_COF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_COF_SHIFT)) & CAAM_CCWR_COF_MASK)
16455
16456#define CAAM_CCWR_CIF_MASK (0x80000000U)
16457#define CAAM_CCWR_CIF_SHIFT (31U)
16462#define CAAM_CCWR_CIF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CIF_SHIFT)) & CAAM_CCWR_CIF_MASK)
16465/* The count of CAAM_CCWR */
16466#define CAAM_CCWR_COUNT (1U)
16467
16471#define CAAM_CCSTA_MS_ERRID1_MASK (0xFU)
16472#define CAAM_CCSTA_MS_ERRID1_SHIFT (0U)
16491#define CAAM_CCSTA_MS_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID1_SHIFT)) & CAAM_CCSTA_MS_ERRID1_MASK)
16492
16493#define CAAM_CCSTA_MS_CL1_MASK (0xF000U)
16494#define CAAM_CCSTA_MS_CL1_SHIFT (12U)
16501#define CAAM_CCSTA_MS_CL1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL1_SHIFT)) & CAAM_CCSTA_MS_CL1_MASK)
16502
16503#define CAAM_CCSTA_MS_ERRID2_MASK (0xF0000U)
16504#define CAAM_CCSTA_MS_ERRID2_SHIFT (16U)
16515#define CAAM_CCSTA_MS_ERRID2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID2_SHIFT)) & CAAM_CCSTA_MS_ERRID2_MASK)
16516
16517#define CAAM_CCSTA_MS_CL2_MASK (0xF0000000U)
16518#define CAAM_CCSTA_MS_CL2_SHIFT (28U)
16523#define CAAM_CCSTA_MS_CL2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL2_SHIFT)) & CAAM_CCSTA_MS_CL2_MASK)
16526/* The count of CAAM_CCSTA_MS */
16527#define CAAM_CCSTA_MS_COUNT (1U)
16528
16532#define CAAM_CCSTA_LS_AB_MASK (0x2U)
16533#define CAAM_CCSTA_LS_AB_SHIFT (1U)
16538#define CAAM_CCSTA_LS_AB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_AB_SHIFT)) & CAAM_CCSTA_LS_AB_MASK)
16539
16540#define CAAM_CCSTA_LS_DB_MASK (0x4U)
16541#define CAAM_CCSTA_LS_DB_SHIFT (2U)
16546#define CAAM_CCSTA_LS_DB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_DB_SHIFT)) & CAAM_CCSTA_LS_DB_MASK)
16547
16548#define CAAM_CCSTA_LS_PB_MASK (0x40U)
16549#define CAAM_CCSTA_LS_PB_SHIFT (6U)
16554#define CAAM_CCSTA_LS_PB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PB_SHIFT)) & CAAM_CCSTA_LS_PB_MASK)
16555
16556#define CAAM_CCSTA_LS_MB_MASK (0x80U)
16557#define CAAM_CCSTA_LS_MB_SHIFT (7U)
16562#define CAAM_CCSTA_LS_MB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_MB_SHIFT)) & CAAM_CCSTA_LS_MB_MASK)
16563
16564#define CAAM_CCSTA_LS_CB_MASK (0x100U)
16565#define CAAM_CCSTA_LS_CB_SHIFT (8U)
16570#define CAAM_CCSTA_LS_CB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_CB_SHIFT)) & CAAM_CCSTA_LS_CB_MASK)
16571
16572#define CAAM_CCSTA_LS_RNB_MASK (0x200U)
16573#define CAAM_CCSTA_LS_RNB_SHIFT (9U)
16578#define CAAM_CCSTA_LS_RNB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_RNB_SHIFT)) & CAAM_CCSTA_LS_RNB_MASK)
16579
16580#define CAAM_CCSTA_LS_PDI_MASK (0x10000U)
16581#define CAAM_CCSTA_LS_PDI_SHIFT (16U)
16586#define CAAM_CCSTA_LS_PDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PDI_SHIFT)) & CAAM_CCSTA_LS_PDI_MASK)
16587
16588#define CAAM_CCSTA_LS_SDI_MASK (0x20000U)
16589#define CAAM_CCSTA_LS_SDI_SHIFT (17U)
16594#define CAAM_CCSTA_LS_SDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SDI_SHIFT)) & CAAM_CCSTA_LS_SDI_MASK)
16595
16596#define CAAM_CCSTA_LS_PEI_MASK (0x100000U)
16597#define CAAM_CCSTA_LS_PEI_SHIFT (20U)
16602#define CAAM_CCSTA_LS_PEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PEI_SHIFT)) & CAAM_CCSTA_LS_PEI_MASK)
16603
16604#define CAAM_CCSTA_LS_SEI_MASK (0x200000U)
16605#define CAAM_CCSTA_LS_SEI_SHIFT (21U)
16610#define CAAM_CCSTA_LS_SEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SEI_SHIFT)) & CAAM_CCSTA_LS_SEI_MASK)
16611
16612#define CAAM_CCSTA_LS_PRM_MASK (0x10000000U)
16613#define CAAM_CCSTA_LS_PRM_SHIFT (28U)
16618#define CAAM_CCSTA_LS_PRM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PRM_SHIFT)) & CAAM_CCSTA_LS_PRM_MASK)
16619
16620#define CAAM_CCSTA_LS_GCD_MASK (0x20000000U)
16621#define CAAM_CCSTA_LS_GCD_SHIFT (29U)
16626#define CAAM_CCSTA_LS_GCD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_GCD_SHIFT)) & CAAM_CCSTA_LS_GCD_MASK)
16627
16628#define CAAM_CCSTA_LS_PIZ_MASK (0x40000000U)
16629#define CAAM_CCSTA_LS_PIZ_SHIFT (30U)
16634#define CAAM_CCSTA_LS_PIZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PIZ_SHIFT)) & CAAM_CCSTA_LS_PIZ_MASK)
16637/* The count of CAAM_CCSTA_LS */
16638#define CAAM_CCSTA_LS_COUNT (1U)
16639
16643#define CAAM_CC1AADSZR_AASZ_MASK (0xFU)
16644#define CAAM_CC1AADSZR_AASZ_SHIFT (0U)
16645#define CAAM_CC1AADSZR_AASZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1AADSZR_AASZ_SHIFT)) & CAAM_CC1AADSZR_AASZ_MASK)
16648/* The count of CAAM_CC1AADSZR */
16649#define CAAM_CC1AADSZR_COUNT (1U)
16650
16654#define CAAM_CC1IVSZR_IVSZ_MASK (0xFU)
16655#define CAAM_CC1IVSZR_IVSZ_SHIFT (0U)
16656#define CAAM_CC1IVSZR_IVSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1IVSZR_IVSZ_SHIFT)) & CAAM_CC1IVSZR_IVSZ_MASK)
16659/* The count of CAAM_CC1IVSZR */
16660#define CAAM_CC1IVSZR_COUNT (1U)
16661
16665#define CAAM_CPKASZR_PKASZ_MASK (0x3FFU)
16666#define CAAM_CPKASZR_PKASZ_SHIFT (0U)
16667#define CAAM_CPKASZR_PKASZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKASZR_PKASZ_SHIFT)) & CAAM_CPKASZR_PKASZ_MASK)
16670/* The count of CAAM_CPKASZR */
16671#define CAAM_CPKASZR_COUNT (1U)
16672
16676#define CAAM_CPKBSZR_PKBSZ_MASK (0x3FFU)
16677#define CAAM_CPKBSZR_PKBSZ_SHIFT (0U)
16678#define CAAM_CPKBSZR_PKBSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKBSZR_PKBSZ_SHIFT)) & CAAM_CPKBSZR_PKBSZ_MASK)
16681/* The count of CAAM_CPKBSZR */
16682#define CAAM_CPKBSZR_COUNT (1U)
16683
16687#define CAAM_CPKNSZR_PKNSZ_MASK (0x3FFU)
16688#define CAAM_CPKNSZR_PKNSZ_SHIFT (0U)
16689#define CAAM_CPKNSZR_PKNSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKNSZR_PKNSZ_SHIFT)) & CAAM_CPKNSZR_PKNSZ_MASK)
16692/* The count of CAAM_CPKNSZR */
16693#define CAAM_CPKNSZR_COUNT (1U)
16694
16698#define CAAM_CPKESZR_PKESZ_MASK (0x3FFU)
16699#define CAAM_CPKESZR_PKESZ_SHIFT (0U)
16700#define CAAM_CPKESZR_PKESZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKESZR_PKESZ_SHIFT)) & CAAM_CPKESZR_PKESZ_MASK)
16703/* The count of CAAM_CPKESZR */
16704#define CAAM_CPKESZR_COUNT (1U)
16705
16709#define CAAM_CC1CTXR_C1CTX_MASK (0xFFFFFFFFU)
16710#define CAAM_CC1CTXR_C1CTX_SHIFT (0U)
16711#define CAAM_CC1CTXR_C1CTX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1CTXR_C1CTX_SHIFT)) & CAAM_CC1CTXR_C1CTX_MASK)
16714/* The count of CAAM_CC1CTXR */
16715#define CAAM_CC1CTXR_COUNT (1U)
16716
16717/* The count of CAAM_CC1CTXR */
16718#define CAAM_CC1CTXR_COUNT2 (16U)
16719
16723#define CAAM_CC1KR_C1KEY_MASK (0xFFFFFFFFU)
16724#define CAAM_CC1KR_C1KEY_SHIFT (0U)
16725#define CAAM_CC1KR_C1KEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KR_C1KEY_SHIFT)) & CAAM_CC1KR_C1KEY_MASK)
16728/* The count of CAAM_CC1KR */
16729#define CAAM_CC1KR_COUNT (1U)
16730
16731/* The count of CAAM_CC1KR */
16732#define CAAM_CC1KR_COUNT2 (8U)
16733
16737#define CAAM_CC2MR_AP_MASK (0x1U)
16738#define CAAM_CC2MR_AP_SHIFT (0U)
16743#define CAAM_CC2MR_AP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AP_SHIFT)) & CAAM_CC2MR_AP_MASK)
16744
16745#define CAAM_CC2MR_ICV_MASK (0x2U)
16746#define CAAM_CC2MR_ICV_SHIFT (1U)
16751#define CAAM_CC2MR_ICV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ICV_SHIFT)) & CAAM_CC2MR_ICV_MASK)
16752
16753#define CAAM_CC2MR_AS_MASK (0xCU)
16754#define CAAM_CC2MR_AS_SHIFT (2U)
16761#define CAAM_CC2MR_AS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AS_SHIFT)) & CAAM_CC2MR_AS_MASK)
16762
16763#define CAAM_CC2MR_AAI_MASK (0x1FF0U)
16764#define CAAM_CC2MR_AAI_SHIFT (4U)
16765#define CAAM_CC2MR_AAI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AAI_SHIFT)) & CAAM_CC2MR_AAI_MASK)
16766
16767#define CAAM_CC2MR_ALG_MASK (0xFF0000U)
16768#define CAAM_CC2MR_ALG_SHIFT (16U)
16780#define CAAM_CC2MR_ALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ALG_SHIFT)) & CAAM_CC2MR_ALG_MASK)
16783/* The count of CAAM_CC2MR */
16784#define CAAM_CC2MR_COUNT (1U)
16785
16789#define CAAM_CC2KSR_C2KS_MASK (0xFFU)
16790#define CAAM_CC2KSR_C2KS_SHIFT (0U)
16791#define CAAM_CC2KSR_C2KS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KSR_C2KS_SHIFT)) & CAAM_CC2KSR_C2KS_MASK)
16794/* The count of CAAM_CC2KSR */
16795#define CAAM_CC2KSR_COUNT (1U)
16796
16800#define CAAM_CC2DSR_C2DS_MASK (0xFFFFFFFFU)
16801#define CAAM_CC2DSR_C2DS_SHIFT (0U)
16802#define CAAM_CC2DSR_C2DS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2DS_SHIFT)) & CAAM_CC2DSR_C2DS_MASK)
16803
16804#define CAAM_CC2DSR_C2CY_MASK (0x100000000U)
16805#define CAAM_CC2DSR_C2CY_SHIFT (32U)
16810#define CAAM_CC2DSR_C2CY(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2CY_SHIFT)) & CAAM_CC2DSR_C2CY_MASK)
16811
16812#define CAAM_CC2DSR_NUMBITS_MASK (0xE000000000000000U)
16813#define CAAM_CC2DSR_NUMBITS_SHIFT (61U)
16814#define CAAM_CC2DSR_NUMBITS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_NUMBITS_SHIFT)) & CAAM_CC2DSR_NUMBITS_MASK)
16817/* The count of CAAM_CC2DSR */
16818#define CAAM_CC2DSR_COUNT (1U)
16819
16823#define CAAM_CC2ICVSZR_ICVSZ_MASK (0xFU)
16824#define CAAM_CC2ICVSZR_ICVSZ_SHIFT (0U)
16825#define CAAM_CC2ICVSZR_ICVSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2ICVSZR_ICVSZ_SHIFT)) & CAAM_CC2ICVSZR_ICVSZ_MASK)
16828/* The count of CAAM_CC2ICVSZR */
16829#define CAAM_CC2ICVSZR_COUNT (1U)
16830
16834#define CAAM_CC2CTXR_C2CTXR_MASK (0xFFFFFFFFU)
16835#define CAAM_CC2CTXR_C2CTXR_SHIFT (0U)
16836#define CAAM_CC2CTXR_C2CTXR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2CTXR_C2CTXR_SHIFT)) & CAAM_CC2CTXR_C2CTXR_MASK)
16839/* The count of CAAM_CC2CTXR */
16840#define CAAM_CC2CTXR_COUNT (1U)
16841
16842/* The count of CAAM_CC2CTXR */
16843#define CAAM_CC2CTXR_COUNT2 (18U)
16844
16848#define CAAM_CC2KEYR_C2KEY_MASK (0xFFFFFFFFU)
16849#define CAAM_CC2KEYR_C2KEY_SHIFT (0U)
16850#define CAAM_CC2KEYR_C2KEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KEYR_C2KEY_SHIFT)) & CAAM_CC2KEYR_C2KEY_MASK)
16853/* The count of CAAM_CC2KEYR */
16854#define CAAM_CC2KEYR_COUNT (1U)
16855
16856/* The count of CAAM_CC2KEYR */
16857#define CAAM_CC2KEYR_COUNT2 (32U)
16858
16862#define CAAM_CFIFOSTA_DECOOQHEAD_MASK (0xFFU)
16863#define CAAM_CFIFOSTA_DECOOQHEAD_SHIFT (0U)
16864#define CAAM_CFIFOSTA_DECOOQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DECOOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DECOOQHEAD_MASK)
16865
16866#define CAAM_CFIFOSTA_DMAOQHEAD_MASK (0xFF00U)
16867#define CAAM_CFIFOSTA_DMAOQHEAD_SHIFT (8U)
16868#define CAAM_CFIFOSTA_DMAOQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DMAOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DMAOQHEAD_MASK)
16869
16870#define CAAM_CFIFOSTA_C2IQHEAD_MASK (0xFF0000U)
16871#define CAAM_CFIFOSTA_C2IQHEAD_SHIFT (16U)
16872#define CAAM_CFIFOSTA_C2IQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C2IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C2IQHEAD_MASK)
16873
16874#define CAAM_CFIFOSTA_C1IQHEAD_MASK (0xFF000000U)
16875#define CAAM_CFIFOSTA_C1IQHEAD_SHIFT (24U)
16876#define CAAM_CFIFOSTA_C1IQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C1IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C1IQHEAD_MASK)
16879/* The count of CAAM_CFIFOSTA */
16880#define CAAM_CFIFOSTA_COUNT (1U)
16881
16885#define CAAM_CNFIFO_DL_MASK (0xFFFU)
16886#define CAAM_CNFIFO_DL_SHIFT (0U)
16887#define CAAM_CNFIFO_DL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DL_SHIFT)) & CAAM_CNFIFO_DL_MASK)
16888
16889#define CAAM_CNFIFO_AST_MASK (0x4000U)
16890#define CAAM_CNFIFO_AST_SHIFT (14U)
16891#define CAAM_CNFIFO_AST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_AST_SHIFT)) & CAAM_CNFIFO_AST_MASK)
16892
16893#define CAAM_CNFIFO_OC_MASK (0x8000U)
16894#define CAAM_CNFIFO_OC_SHIFT (15U)
16899#define CAAM_CNFIFO_OC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_OC_SHIFT)) & CAAM_CNFIFO_OC_MASK)
16900
16901#define CAAM_CNFIFO_PTYPE_MASK (0x70000U)
16902#define CAAM_CNFIFO_PTYPE_SHIFT (16U)
16903#define CAAM_CNFIFO_PTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_PTYPE_SHIFT)) & CAAM_CNFIFO_PTYPE_MASK)
16904
16905#define CAAM_CNFIFO_BND_MASK (0x80000U)
16906#define CAAM_CNFIFO_BND_SHIFT (19U)
16911#define CAAM_CNFIFO_BND(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_BND_SHIFT)) & CAAM_CNFIFO_BND_MASK)
16912
16913#define CAAM_CNFIFO_DTYPE_MASK (0xF00000U)
16914#define CAAM_CNFIFO_DTYPE_SHIFT (20U)
16915#define CAAM_CNFIFO_DTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DTYPE_SHIFT)) & CAAM_CNFIFO_DTYPE_MASK)
16916
16917#define CAAM_CNFIFO_STYPE_MASK (0x3000000U)
16918#define CAAM_CNFIFO_STYPE_SHIFT (24U)
16919#define CAAM_CNFIFO_STYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_STYPE_SHIFT)) & CAAM_CNFIFO_STYPE_MASK)
16920
16921#define CAAM_CNFIFO_FC1_MASK (0x4000000U)
16922#define CAAM_CNFIFO_FC1_SHIFT (26U)
16927#define CAAM_CNFIFO_FC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC1_SHIFT)) & CAAM_CNFIFO_FC1_MASK)
16928
16929#define CAAM_CNFIFO_FC2_MASK (0x8000000U)
16930#define CAAM_CNFIFO_FC2_SHIFT (27U)
16935#define CAAM_CNFIFO_FC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC2_SHIFT)) & CAAM_CNFIFO_FC2_MASK)
16936
16937#define CAAM_CNFIFO_LC1_MASK (0x10000000U)
16938#define CAAM_CNFIFO_LC1_SHIFT (28U)
16943#define CAAM_CNFIFO_LC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC1_SHIFT)) & CAAM_CNFIFO_LC1_MASK)
16944
16945#define CAAM_CNFIFO_LC2_MASK (0x20000000U)
16946#define CAAM_CNFIFO_LC2_SHIFT (29U)
16951#define CAAM_CNFIFO_LC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC2_SHIFT)) & CAAM_CNFIFO_LC2_MASK)
16952
16953#define CAAM_CNFIFO_DEST_MASK (0xC0000000U)
16954#define CAAM_CNFIFO_DEST_SHIFT (30U)
16963#define CAAM_CNFIFO_DEST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DEST_SHIFT)) & CAAM_CNFIFO_DEST_MASK)
16966/* The count of CAAM_CNFIFO */
16967#define CAAM_CNFIFO_COUNT (1U)
16968
16972#define CAAM_CNFIFO_2_PL_MASK (0x7FU)
16973#define CAAM_CNFIFO_2_PL_SHIFT (0U)
16974#define CAAM_CNFIFO_2_PL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PL_SHIFT)) & CAAM_CNFIFO_2_PL_MASK)
16975
16976#define CAAM_CNFIFO_2_PS_MASK (0x400U)
16977#define CAAM_CNFIFO_2_PS_SHIFT (10U)
16982#define CAAM_CNFIFO_2_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PS_SHIFT)) & CAAM_CNFIFO_2_PS_MASK)
16983
16984#define CAAM_CNFIFO_2_BM_MASK (0x800U)
16985#define CAAM_CNFIFO_2_BM_SHIFT (11U)
16990#define CAAM_CNFIFO_2_BM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BM_SHIFT)) & CAAM_CNFIFO_2_BM_MASK)
16991
16992#define CAAM_CNFIFO_2_PR_MASK (0x8000U)
16993#define CAAM_CNFIFO_2_PR_SHIFT (15U)
16998#define CAAM_CNFIFO_2_PR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PR_SHIFT)) & CAAM_CNFIFO_2_PR_MASK)
16999
17000#define CAAM_CNFIFO_2_PTYPE_MASK (0x70000U)
17001#define CAAM_CNFIFO_2_PTYPE_SHIFT (16U)
17012#define CAAM_CNFIFO_2_PTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PTYPE_SHIFT)) & CAAM_CNFIFO_2_PTYPE_MASK)
17013
17014#define CAAM_CNFIFO_2_BND_MASK (0x80000U)
17015#define CAAM_CNFIFO_2_BND_SHIFT (19U)
17020#define CAAM_CNFIFO_2_BND(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BND_SHIFT)) & CAAM_CNFIFO_2_BND_MASK)
17021
17022#define CAAM_CNFIFO_2_DTYPE_MASK (0xF00000U)
17023#define CAAM_CNFIFO_2_DTYPE_SHIFT (20U)
17024#define CAAM_CNFIFO_2_DTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DTYPE_SHIFT)) & CAAM_CNFIFO_2_DTYPE_MASK)
17025
17026#define CAAM_CNFIFO_2_STYPE_MASK (0x3000000U)
17027#define CAAM_CNFIFO_2_STYPE_SHIFT (24U)
17028#define CAAM_CNFIFO_2_STYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_STYPE_SHIFT)) & CAAM_CNFIFO_2_STYPE_MASK)
17029
17030#define CAAM_CNFIFO_2_FC1_MASK (0x4000000U)
17031#define CAAM_CNFIFO_2_FC1_SHIFT (26U)
17036#define CAAM_CNFIFO_2_FC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC1_SHIFT)) & CAAM_CNFIFO_2_FC1_MASK)
17037
17038#define CAAM_CNFIFO_2_FC2_MASK (0x8000000U)
17039#define CAAM_CNFIFO_2_FC2_SHIFT (27U)
17044#define CAAM_CNFIFO_2_FC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC2_SHIFT)) & CAAM_CNFIFO_2_FC2_MASK)
17045
17046#define CAAM_CNFIFO_2_LC1_MASK (0x10000000U)
17047#define CAAM_CNFIFO_2_LC1_SHIFT (28U)
17052#define CAAM_CNFIFO_2_LC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC1_SHIFT)) & CAAM_CNFIFO_2_LC1_MASK)
17053
17054#define CAAM_CNFIFO_2_LC2_MASK (0x20000000U)
17055#define CAAM_CNFIFO_2_LC2_SHIFT (29U)
17060#define CAAM_CNFIFO_2_LC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC2_SHIFT)) & CAAM_CNFIFO_2_LC2_MASK)
17061
17062#define CAAM_CNFIFO_2_DEST_MASK (0xC0000000U)
17063#define CAAM_CNFIFO_2_DEST_SHIFT (30U)
17072#define CAAM_CNFIFO_2_DEST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DEST_SHIFT)) & CAAM_CNFIFO_2_DEST_MASK)
17075/* The count of CAAM_CNFIFO_2 */
17076#define CAAM_CNFIFO_2_COUNT (1U)
17077
17081#define CAAM_CIFIFO_IFIFO_MASK (0xFFFFFFFFU)
17082#define CAAM_CIFIFO_IFIFO_SHIFT (0U)
17083#define CAAM_CIFIFO_IFIFO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CIFIFO_IFIFO_SHIFT)) & CAAM_CIFIFO_IFIFO_MASK)
17086/* The count of CAAM_CIFIFO */
17087#define CAAM_CIFIFO_COUNT (1U)
17088
17092#define CAAM_COFIFO_OFIFO_MASK (0xFFFFFFFFFFFFFFFFU)
17093#define CAAM_COFIFO_OFIFO_SHIFT (0U)
17094#define CAAM_COFIFO_OFIFO(x) (((uint64_t)(((uint64_t)(x)) << CAAM_COFIFO_OFIFO_SHIFT)) & CAAM_COFIFO_OFIFO_MASK)
17097/* The count of CAAM_COFIFO */
17098#define CAAM_COFIFO_COUNT (1U)
17099
17103#define CAAM_DJQCR_MS_ID_MASK (0x7U)
17104#define CAAM_DJQCR_MS_ID_SHIFT (0U)
17105#define CAAM_DJQCR_MS_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ID_SHIFT)) & CAAM_DJQCR_MS_ID_MASK)
17106
17107#define CAAM_DJQCR_MS_SRC_MASK (0x700U)
17108#define CAAM_DJQCR_MS_SRC_SHIFT (8U)
17119#define CAAM_DJQCR_MS_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SRC_SHIFT)) & CAAM_DJQCR_MS_SRC_MASK)
17120
17121#define CAAM_DJQCR_MS_AMTD_MASK (0x8000U)
17122#define CAAM_DJQCR_MS_AMTD_SHIFT (15U)
17127#define CAAM_DJQCR_MS_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_AMTD_SHIFT)) & CAAM_DJQCR_MS_AMTD_MASK)
17128
17129#define CAAM_DJQCR_MS_SOB_MASK (0x10000U)
17130#define CAAM_DJQCR_MS_SOB_SHIFT (16U)
17135#define CAAM_DJQCR_MS_SOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SOB_SHIFT)) & CAAM_DJQCR_MS_SOB_MASK)
17136
17137#define CAAM_DJQCR_MS_DWS_MASK (0x80000U)
17138#define CAAM_DJQCR_MS_DWS_SHIFT (19U)
17143#define CAAM_DJQCR_MS_DWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_DWS_SHIFT)) & CAAM_DJQCR_MS_DWS_MASK)
17144
17145#define CAAM_DJQCR_MS_SHR_FROM_MASK (0x7000000U)
17146#define CAAM_DJQCR_MS_SHR_FROM_SHIFT (24U)
17147#define CAAM_DJQCR_MS_SHR_FROM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SHR_FROM_SHIFT)) & CAAM_DJQCR_MS_SHR_FROM_MASK)
17148
17149#define CAAM_DJQCR_MS_ILE_MASK (0x8000000U)
17150#define CAAM_DJQCR_MS_ILE_SHIFT (27U)
17155#define CAAM_DJQCR_MS_ILE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ILE_SHIFT)) & CAAM_DJQCR_MS_ILE_MASK)
17156
17157#define CAAM_DJQCR_MS_FOUR_MASK (0x10000000U)
17158#define CAAM_DJQCR_MS_FOUR_SHIFT (28U)
17163#define CAAM_DJQCR_MS_FOUR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_FOUR_SHIFT)) & CAAM_DJQCR_MS_FOUR_MASK)
17164
17165#define CAAM_DJQCR_MS_WHL_MASK (0x20000000U)
17166#define CAAM_DJQCR_MS_WHL_SHIFT (29U)
17171#define CAAM_DJQCR_MS_WHL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_WHL_SHIFT)) & CAAM_DJQCR_MS_WHL_MASK)
17172
17173#define CAAM_DJQCR_MS_SING_MASK (0x40000000U)
17174#define CAAM_DJQCR_MS_SING_SHIFT (30U)
17179#define CAAM_DJQCR_MS_SING(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SING_SHIFT)) & CAAM_DJQCR_MS_SING_MASK)
17180
17181#define CAAM_DJQCR_MS_STEP_MASK (0x80000000U)
17182#define CAAM_DJQCR_MS_STEP_SHIFT (31U)
17187#define CAAM_DJQCR_MS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_STEP_SHIFT)) & CAAM_DJQCR_MS_STEP_MASK)
17190/* The count of CAAM_DJQCR_MS */
17191#define CAAM_DJQCR_MS_COUNT (1U)
17192
17196#define CAAM_DJQCR_LS_CMD_MASK (0xFFFFFFFFU)
17197#define CAAM_DJQCR_LS_CMD_SHIFT (0U)
17198#define CAAM_DJQCR_LS_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_LS_CMD_SHIFT)) & CAAM_DJQCR_LS_CMD_MASK)
17201/* The count of CAAM_DJQCR_LS */
17202#define CAAM_DJQCR_LS_COUNT (1U)
17203
17207#define CAAM_DDAR_DPTR_MASK (0xFFFFFFFFFU)
17208#define CAAM_DDAR_DPTR_SHIFT (0U)
17209#define CAAM_DDAR_DPTR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DDAR_DPTR_SHIFT)) & CAAM_DDAR_DPTR_MASK)
17212/* The count of CAAM_DDAR */
17213#define CAAM_DDAR_COUNT (1U)
17214
17218#define CAAM_DOPSTA_MS_STATUS_MASK (0xFFU)
17219#define CAAM_DOPSTA_MS_STATUS_SHIFT (0U)
17220#define CAAM_DOPSTA_MS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_SHIFT)) & CAAM_DOPSTA_MS_STATUS_MASK)
17221
17222#define CAAM_DOPSTA_MS_COMMAND_INDEX_MASK (0x7F00U)
17223#define CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT (8U)
17224#define CAAM_DOPSTA_MS_COMMAND_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT)) & CAAM_DOPSTA_MS_COMMAND_INDEX_MASK)
17225
17226#define CAAM_DOPSTA_MS_NLJ_MASK (0x8000000U)
17227#define CAAM_DOPSTA_MS_NLJ_SHIFT (27U)
17232#define CAAM_DOPSTA_MS_NLJ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_NLJ_SHIFT)) & CAAM_DOPSTA_MS_NLJ_MASK)
17233
17234#define CAAM_DOPSTA_MS_STATUS_TYPE_MASK (0xF0000000U)
17235#define CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT (28U)
17245#define CAAM_DOPSTA_MS_STATUS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT)) & CAAM_DOPSTA_MS_STATUS_TYPE_MASK)
17248/* The count of CAAM_DOPSTA_MS */
17249#define CAAM_DOPSTA_MS_COUNT (1U)
17250
17254#define CAAM_DOPSTA_LS_OUT_CT_MASK (0xFFFFFFFFU)
17255#define CAAM_DOPSTA_LS_OUT_CT_SHIFT (0U)
17256#define CAAM_DOPSTA_LS_OUT_CT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_LS_OUT_CT_SHIFT)) & CAAM_DOPSTA_LS_OUT_CT_MASK)
17259/* The count of CAAM_DOPSTA_LS */
17260#define CAAM_DOPSTA_LS_COUNT (1U)
17261
17265#define CAAM_DPDIDSR_PRIM_DID_MASK (0xFU)
17266#define CAAM_DPDIDSR_PRIM_DID_SHIFT (0U)
17267#define CAAM_DPDIDSR_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_DID_SHIFT)) & CAAM_DPDIDSR_PRIM_DID_MASK)
17268
17269#define CAAM_DPDIDSR_PRIM_ICID_MASK (0x3FF80000U)
17270#define CAAM_DPDIDSR_PRIM_ICID_SHIFT (19U)
17271#define CAAM_DPDIDSR_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_ICID_SHIFT)) & CAAM_DPDIDSR_PRIM_ICID_MASK)
17274/* The count of CAAM_DPDIDSR */
17275#define CAAM_DPDIDSR_COUNT (1U)
17276
17280#define CAAM_DODIDSR_OUT_DID_MASK (0xFU)
17281#define CAAM_DODIDSR_OUT_DID_SHIFT (0U)
17282#define CAAM_DODIDSR_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_DID_SHIFT)) & CAAM_DODIDSR_OUT_DID_MASK)
17283
17284#define CAAM_DODIDSR_OUT_ICID_MASK (0x3FF80000U)
17285#define CAAM_DODIDSR_OUT_ICID_SHIFT (19U)
17286#define CAAM_DODIDSR_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_ICID_SHIFT)) & CAAM_DODIDSR_OUT_ICID_MASK)
17289/* The count of CAAM_DODIDSR */
17290#define CAAM_DODIDSR_COUNT (1U)
17291
17295#define CAAM_DMTH_MS_MATH_MS_MASK (0xFFFFFFFFU)
17296#define CAAM_DMTH_MS_MATH_MS_SHIFT (0U)
17297#define CAAM_DMTH_MS_MATH_MS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_MS_MATH_MS_SHIFT)) & CAAM_DMTH_MS_MATH_MS_MASK)
17300/* The count of CAAM_DMTH_MS */
17301#define CAAM_DMTH_MS_COUNT (1U)
17302
17303/* The count of CAAM_DMTH_MS */
17304#define CAAM_DMTH_MS_COUNT2 (4U)
17305
17309#define CAAM_DMTH_LS_MATH_LS_MASK (0xFFFFFFFFU)
17310#define CAAM_DMTH_LS_MATH_LS_SHIFT (0U)
17311#define CAAM_DMTH_LS_MATH_LS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_LS_MATH_LS_SHIFT)) & CAAM_DMTH_LS_MATH_LS_MASK)
17314/* The count of CAAM_DMTH_LS */
17315#define CAAM_DMTH_LS_COUNT (1U)
17316
17317/* The count of CAAM_DMTH_LS */
17318#define CAAM_DMTH_LS_COUNT2 (4U)
17319
17323#define CAAM_DGTR_0_ADDRESS_POINTER_MASK (0xFU)
17324#define CAAM_DGTR_0_ADDRESS_POINTER_SHIFT (0U)
17327#define CAAM_DGTR_0_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_0_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_0_ADDRESS_POINTER_MASK)
17330/* The count of CAAM_DGTR_0 */
17331#define CAAM_DGTR_0_COUNT (1U)
17332
17333/* The count of CAAM_DGTR_0 */
17334#define CAAM_DGTR_0_COUNT2 (1U)
17335
17339#define CAAM_DGTR_1_ADDRESS_POINTER_MASK (0xFFFFFFFFU)
17340#define CAAM_DGTR_1_ADDRESS_POINTER_SHIFT (0U)
17341#define CAAM_DGTR_1_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_1_ADDRESS_POINTER_MASK)
17344/* The count of CAAM_DGTR_1 */
17345#define CAAM_DGTR_1_COUNT (1U)
17346
17347/* The count of CAAM_DGTR_1 */
17348#define CAAM_DGTR_1_COUNT2 (1U)
17349
17353#define CAAM_DGTR_2_Length_MASK (0x3FFFFFFFU)
17354#define CAAM_DGTR_2_Length_SHIFT (0U)
17355#define CAAM_DGTR_2_Length(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_Length_SHIFT)) & CAAM_DGTR_2_Length_MASK)
17356
17357#define CAAM_DGTR_2_F_MASK (0x40000000U)
17358#define CAAM_DGTR_2_F_SHIFT (30U)
17363#define CAAM_DGTR_2_F(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_F_SHIFT)) & CAAM_DGTR_2_F_MASK)
17364
17365#define CAAM_DGTR_2_E_MASK (0x80000000U)
17366#define CAAM_DGTR_2_E_SHIFT (31U)
17371#define CAAM_DGTR_2_E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_E_SHIFT)) & CAAM_DGTR_2_E_MASK)
17374/* The count of CAAM_DGTR_2 */
17375#define CAAM_DGTR_2_COUNT (1U)
17376
17377/* The count of CAAM_DGTR_2 */
17378#define CAAM_DGTR_2_COUNT2 (1U)
17379
17383#define CAAM_DGTR_3_Offset_MASK (0x1FFFU)
17384#define CAAM_DGTR_3_Offset_SHIFT (0U)
17385#define CAAM_DGTR_3_Offset(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_3_Offset_SHIFT)) & CAAM_DGTR_3_Offset_MASK)
17388/* The count of CAAM_DGTR_3 */
17389#define CAAM_DGTR_3_COUNT (1U)
17390
17391/* The count of CAAM_DGTR_3 */
17392#define CAAM_DGTR_3_COUNT2 (1U)
17393
17397#define CAAM_DSTR_0_ADDRESS_POINTER_MASK (0xFU)
17398#define CAAM_DSTR_0_ADDRESS_POINTER_SHIFT (0U)
17401#define CAAM_DSTR_0_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_0_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_0_ADDRESS_POINTER_MASK)
17404/* The count of CAAM_DSTR_0 */
17405#define CAAM_DSTR_0_COUNT (1U)
17406
17407/* The count of CAAM_DSTR_0 */
17408#define CAAM_DSTR_0_COUNT2 (1U)
17409
17413#define CAAM_DSTR_1_ADDRESS_POINTER_MASK (0xFFFFFFFFU)
17414#define CAAM_DSTR_1_ADDRESS_POINTER_SHIFT (0U)
17415#define CAAM_DSTR_1_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_1_ADDRESS_POINTER_MASK)
17418/* The count of CAAM_DSTR_1 */
17419#define CAAM_DSTR_1_COUNT (1U)
17420
17421/* The count of CAAM_DSTR_1 */
17422#define CAAM_DSTR_1_COUNT2 (1U)
17423
17427#define CAAM_DSTR_2_Length_MASK (0x3FFFFFFFU)
17428#define CAAM_DSTR_2_Length_SHIFT (0U)
17429#define CAAM_DSTR_2_Length(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_Length_SHIFT)) & CAAM_DSTR_2_Length_MASK)
17430
17431#define CAAM_DSTR_2_F_MASK (0x40000000U)
17432#define CAAM_DSTR_2_F_SHIFT (30U)
17437#define CAAM_DSTR_2_F(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_F_SHIFT)) & CAAM_DSTR_2_F_MASK)
17438
17439#define CAAM_DSTR_2_E_MASK (0x80000000U)
17440#define CAAM_DSTR_2_E_SHIFT (31U)
17445#define CAAM_DSTR_2_E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_E_SHIFT)) & CAAM_DSTR_2_E_MASK)
17448/* The count of CAAM_DSTR_2 */
17449#define CAAM_DSTR_2_COUNT (1U)
17450
17451/* The count of CAAM_DSTR_2 */
17452#define CAAM_DSTR_2_COUNT2 (1U)
17453
17457#define CAAM_DSTR_3_Offset_MASK (0x1FFFU)
17458#define CAAM_DSTR_3_Offset_SHIFT (0U)
17459#define CAAM_DSTR_3_Offset(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_3_Offset_SHIFT)) & CAAM_DSTR_3_Offset_MASK)
17462/* The count of CAAM_DSTR_3 */
17463#define CAAM_DSTR_3_COUNT (1U)
17464
17465/* The count of CAAM_DSTR_3 */
17466#define CAAM_DSTR_3_COUNT2 (1U)
17467
17471#define CAAM_DDESB_DESBW_MASK (0xFFFFFFFFU)
17472#define CAAM_DDESB_DESBW_SHIFT (0U)
17473#define CAAM_DDESB_DESBW(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDESB_DESBW_SHIFT)) & CAAM_DDESB_DESBW_MASK)
17476/* The count of CAAM_DDESB */
17477#define CAAM_DDESB_COUNT (1U)
17478
17479/* The count of CAAM_DDESB */
17480#define CAAM_DDESB_COUNT2 (64U)
17481
17485#define CAAM_DDJR_ID_MASK (0x7U)
17486#define CAAM_DDJR_ID_SHIFT (0U)
17487#define CAAM_DDJR_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ID_SHIFT)) & CAAM_DDJR_ID_MASK)
17488
17489#define CAAM_DDJR_SRC_MASK (0x700U)
17490#define CAAM_DDJR_SRC_SHIFT (8U)
17499#define CAAM_DDJR_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SRC_SHIFT)) & CAAM_DDJR_SRC_MASK)
17500
17501#define CAAM_DDJR_JDDS_MASK (0x4000U)
17502#define CAAM_DDJR_JDDS_SHIFT (14U)
17507#define CAAM_DDJR_JDDS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_JDDS_SHIFT)) & CAAM_DDJR_JDDS_MASK)
17508
17509#define CAAM_DDJR_AMTD_MASK (0x8000U)
17510#define CAAM_DDJR_AMTD_SHIFT (15U)
17515#define CAAM_DDJR_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_AMTD_SHIFT)) & CAAM_DDJR_AMTD_MASK)
17516
17517#define CAAM_DDJR_GSD_MASK (0x10000U)
17518#define CAAM_DDJR_GSD_SHIFT (16U)
17523#define CAAM_DDJR_GSD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_GSD_SHIFT)) & CAAM_DDJR_GSD_MASK)
17524
17525#define CAAM_DDJR_DWS_MASK (0x80000U)
17526#define CAAM_DDJR_DWS_SHIFT (19U)
17531#define CAAM_DDJR_DWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_DWS_SHIFT)) & CAAM_DDJR_DWS_MASK)
17532
17533#define CAAM_DDJR_SHR_FROM_MASK (0x7000000U)
17534#define CAAM_DDJR_SHR_FROM_SHIFT (24U)
17535#define CAAM_DDJR_SHR_FROM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SHR_FROM_SHIFT)) & CAAM_DDJR_SHR_FROM_MASK)
17536
17537#define CAAM_DDJR_ILE_MASK (0x8000000U)
17538#define CAAM_DDJR_ILE_SHIFT (27U)
17543#define CAAM_DDJR_ILE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ILE_SHIFT)) & CAAM_DDJR_ILE_MASK)
17544
17545#define CAAM_DDJR_FOUR_MASK (0x10000000U)
17546#define CAAM_DDJR_FOUR_SHIFT (28U)
17551#define CAAM_DDJR_FOUR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_FOUR_SHIFT)) & CAAM_DDJR_FOUR_MASK)
17552
17553#define CAAM_DDJR_WHL_MASK (0x20000000U)
17554#define CAAM_DDJR_WHL_SHIFT (29U)
17559#define CAAM_DDJR_WHL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_WHL_SHIFT)) & CAAM_DDJR_WHL_MASK)
17560
17561#define CAAM_DDJR_SING_MASK (0x40000000U)
17562#define CAAM_DDJR_SING_SHIFT (30U)
17567#define CAAM_DDJR_SING(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SING_SHIFT)) & CAAM_DDJR_SING_MASK)
17568
17569#define CAAM_DDJR_STEP_MASK (0x80000000U)
17570#define CAAM_DDJR_STEP_SHIFT (31U)
17575#define CAAM_DDJR_STEP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_STEP_SHIFT)) & CAAM_DDJR_STEP_MASK)
17578/* The count of CAAM_DDJR */
17579#define CAAM_DDJR_COUNT (1U)
17580
17584#define CAAM_DDDR_CT_MASK (0x1U)
17585#define CAAM_DDDR_CT_SHIFT (0U)
17590#define CAAM_DDDR_CT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CT_SHIFT)) & CAAM_DDDR_CT_MASK)
17591
17592#define CAAM_DDDR_BRB_MASK (0x2U)
17593#define CAAM_DDDR_BRB_SHIFT (1U)
17598#define CAAM_DDDR_BRB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BRB_SHIFT)) & CAAM_DDDR_BRB_MASK)
17599
17600#define CAAM_DDDR_BWB_MASK (0x4U)
17601#define CAAM_DDDR_BWB_SHIFT (2U)
17606#define CAAM_DDDR_BWB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BWB_SHIFT)) & CAAM_DDDR_BWB_MASK)
17607
17608#define CAAM_DDDR_NC_MASK (0x8U)
17609#define CAAM_DDDR_NC_SHIFT (3U)
17614#define CAAM_DDDR_NC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NC_SHIFT)) & CAAM_DDDR_NC_MASK)
17615
17616#define CAAM_DDDR_CSA_MASK (0x10U)
17617#define CAAM_DDDR_CSA_SHIFT (4U)
17618#define CAAM_DDDR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CSA_SHIFT)) & CAAM_DDDR_CSA_MASK)
17619
17620#define CAAM_DDDR_CMD_STAGE_MASK (0xE0U)
17621#define CAAM_DDDR_CMD_STAGE_SHIFT (5U)
17622#define CAAM_DDDR_CMD_STAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_STAGE_SHIFT)) & CAAM_DDDR_CMD_STAGE_MASK)
17623
17624#define CAAM_DDDR_CMD_INDEX_MASK (0x3F00U)
17625#define CAAM_DDDR_CMD_INDEX_SHIFT (8U)
17626#define CAAM_DDDR_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_INDEX_SHIFT)) & CAAM_DDDR_CMD_INDEX_MASK)
17627
17628#define CAAM_DDDR_NLJ_MASK (0x4000U)
17629#define CAAM_DDDR_NLJ_SHIFT (14U)
17634#define CAAM_DDDR_NLJ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NLJ_SHIFT)) & CAAM_DDDR_NLJ_MASK)
17635
17636#define CAAM_DDDR_PTCL_RUN_MASK (0x8000U)
17637#define CAAM_DDDR_PTCL_RUN_SHIFT (15U)
17642#define CAAM_DDDR_PTCL_RUN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PTCL_RUN_SHIFT)) & CAAM_DDDR_PTCL_RUN_MASK)
17643
17644#define CAAM_DDDR_PDB_STALL_MASK (0x30000U)
17645#define CAAM_DDDR_PDB_STALL_SHIFT (16U)
17646#define CAAM_DDDR_PDB_STALL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_STALL_SHIFT)) & CAAM_DDDR_PDB_STALL_MASK)
17647
17648#define CAAM_DDDR_PDB_WB_ST_MASK (0xC0000U)
17649#define CAAM_DDDR_PDB_WB_ST_SHIFT (18U)
17650#define CAAM_DDDR_PDB_WB_ST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_WB_ST_SHIFT)) & CAAM_DDDR_PDB_WB_ST_MASK)
17651
17652#define CAAM_DDDR_DECO_STATE_MASK (0xF00000U)
17653#define CAAM_DDDR_DECO_STATE_SHIFT (20U)
17654#define CAAM_DDDR_DECO_STATE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_DECO_STATE_SHIFT)) & CAAM_DDDR_DECO_STATE_MASK)
17655
17656#define CAAM_DDDR_NSEQLSEL_MASK (0x3000000U)
17657#define CAAM_DDDR_NSEQLSEL_SHIFT (24U)
17663#define CAAM_DDDR_NSEQLSEL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NSEQLSEL_SHIFT)) & CAAM_DDDR_NSEQLSEL_MASK)
17664
17665#define CAAM_DDDR_SEQLSEL_MASK (0xC000000U)
17666#define CAAM_DDDR_SEQLSEL_SHIFT (26U)
17672#define CAAM_DDDR_SEQLSEL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SEQLSEL_SHIFT)) & CAAM_DDDR_SEQLSEL_MASK)
17673
17674#define CAAM_DDDR_TRCT_MASK (0x30000000U)
17675#define CAAM_DDDR_TRCT_SHIFT (28U)
17676#define CAAM_DDDR_TRCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_TRCT_SHIFT)) & CAAM_DDDR_TRCT_MASK)
17677
17678#define CAAM_DDDR_SD_MASK (0x40000000U)
17679#define CAAM_DDDR_SD_SHIFT (30U)
17684#define CAAM_DDDR_SD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SD_SHIFT)) & CAAM_DDDR_SD_MASK)
17685
17686#define CAAM_DDDR_VALID_MASK (0x80000000U)
17687#define CAAM_DDDR_VALID_SHIFT (31U)
17692#define CAAM_DDDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_VALID_SHIFT)) & CAAM_DDDR_VALID_MASK)
17695/* The count of CAAM_DDDR */
17696#define CAAM_DDDR_COUNT (1U)
17697
17701#define CAAM_DDJP_JDPTR_MASK (0xFFFFFFFFFU)
17702#define CAAM_DDJP_JDPTR_SHIFT (0U)
17703#define CAAM_DDJP_JDPTR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DDJP_JDPTR_SHIFT)) & CAAM_DDJP_JDPTR_MASK)
17706/* The count of CAAM_DDJP */
17707#define CAAM_DDJP_COUNT (1U)
17708
17712#define CAAM_DSDP_SDPTR_MASK (0xFFFFFFFFFU)
17713#define CAAM_DSDP_SDPTR_SHIFT (0U)
17714#define CAAM_DSDP_SDPTR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DSDP_SDPTR_SHIFT)) & CAAM_DSDP_SDPTR_MASK)
17717/* The count of CAAM_DSDP */
17718#define CAAM_DSDP_COUNT (1U)
17719
17723#define CAAM_DDDR_MS_PRIM_DID_MASK (0xFU)
17724#define CAAM_DDDR_MS_PRIM_DID_SHIFT (0U)
17725#define CAAM_DDDR_MS_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_DID_SHIFT)) & CAAM_DDDR_MS_PRIM_DID_MASK)
17726
17727#define CAAM_DDDR_MS_PRIM_TZ_MASK (0x10U)
17728#define CAAM_DDDR_MS_PRIM_TZ_SHIFT (4U)
17733#define CAAM_DDDR_MS_PRIM_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_TZ_SHIFT)) & CAAM_DDDR_MS_PRIM_TZ_MASK)
17734
17735#define CAAM_DDDR_MS_PRIM_ICID_MASK (0xFFE0U)
17736#define CAAM_DDDR_MS_PRIM_ICID_SHIFT (5U)
17737#define CAAM_DDDR_MS_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_ICID_SHIFT)) & CAAM_DDDR_MS_PRIM_ICID_MASK)
17738
17739#define CAAM_DDDR_MS_OUT_DID_MASK (0xF0000U)
17740#define CAAM_DDDR_MS_OUT_DID_SHIFT (16U)
17741#define CAAM_DDDR_MS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_DID_SHIFT)) & CAAM_DDDR_MS_OUT_DID_MASK)
17742
17743#define CAAM_DDDR_MS_OUT_ICID_MASK (0xFFE00000U)
17744#define CAAM_DDDR_MS_OUT_ICID_SHIFT (21U)
17745#define CAAM_DDDR_MS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_ICID_SHIFT)) & CAAM_DDDR_MS_OUT_ICID_MASK)
17748/* The count of CAAM_DDDR_MS */
17749#define CAAM_DDDR_MS_COUNT (1U)
17750
17754#define CAAM_DDDR_LS_OUT_DID_MASK (0xFU)
17755#define CAAM_DDDR_LS_OUT_DID_SHIFT (0U)
17756#define CAAM_DDDR_LS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_DID_SHIFT)) & CAAM_DDDR_LS_OUT_DID_MASK)
17757
17758#define CAAM_DDDR_LS_OUT_ICID_MASK (0x3FF80000U)
17759#define CAAM_DDDR_LS_OUT_ICID_SHIFT (19U)
17760#define CAAM_DDDR_LS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_ICID_SHIFT)) & CAAM_DDDR_LS_OUT_ICID_MASK)
17763/* The count of CAAM_DDDR_LS */
17764#define CAAM_DDDR_LS_COUNT (1U)
17765
17769#define CAAM_SOL_SOL_MASK (0xFFFFFFFFU)
17770#define CAAM_SOL_SOL_SHIFT (0U)
17771#define CAAM_SOL_SOL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SOL_SOL_SHIFT)) & CAAM_SOL_SOL_MASK)
17774/* The count of CAAM_SOL */
17775#define CAAM_SOL_COUNT (1U)
17776
17780#define CAAM_VSOL_VSOL_MASK (0xFFFFFFFFU)
17781#define CAAM_VSOL_VSOL_SHIFT (0U)
17782#define CAAM_VSOL_VSOL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_VSOL_VSOL_SHIFT)) & CAAM_VSOL_VSOL_MASK)
17785/* The count of CAAM_VSOL */
17786#define CAAM_VSOL_COUNT (1U)
17787
17791#define CAAM_SIL_SIL_MASK (0xFFFFFFFFU)
17792#define CAAM_SIL_SIL_SHIFT (0U)
17793#define CAAM_SIL_SIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SIL_SIL_SHIFT)) & CAAM_SIL_SIL_MASK)
17796/* The count of CAAM_SIL */
17797#define CAAM_SIL_COUNT (1U)
17798
17802#define CAAM_VSIL_VSIL_MASK (0xFFFFFFFFU)
17803#define CAAM_VSIL_VSIL_SHIFT (0U)
17804#define CAAM_VSIL_VSIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_VSIL_VSIL_SHIFT)) & CAAM_VSIL_VSIL_MASK)
17807/* The count of CAAM_VSIL */
17808#define CAAM_VSIL_COUNT (1U)
17809
17813#define CAAM_DPOVRD_DPOVRD_MASK (0xFFFFFFFFU)
17814#define CAAM_DPOVRD_DPOVRD_SHIFT (0U)
17815#define CAAM_DPOVRD_DPOVRD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DPOVRD_DPOVRD_SHIFT)) & CAAM_DPOVRD_DPOVRD_MASK)
17818/* The count of CAAM_DPOVRD */
17819#define CAAM_DPOVRD_COUNT (1U)
17820
17824#define CAAM_UVSOL_UVSOL_MASK (0xFFFFFFFFU)
17825#define CAAM_UVSOL_UVSOL_SHIFT (0U)
17826#define CAAM_UVSOL_UVSOL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_UVSOL_UVSOL_SHIFT)) & CAAM_UVSOL_UVSOL_MASK)
17829/* The count of CAAM_UVSOL */
17830#define CAAM_UVSOL_COUNT (1U)
17831
17835#define CAAM_UVSIL_UVSIL_MASK (0xFFFFFFFFU)
17836#define CAAM_UVSIL_UVSIL_SHIFT (0U)
17837#define CAAM_UVSIL_UVSIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_UVSIL_UVSIL_SHIFT)) & CAAM_UVSIL_UVSIL_MASK)
17840/* The count of CAAM_UVSIL */
17841#define CAAM_UVSIL_COUNT (1U)
17842
17843 /* end of group CAAM_Register_Masks */
17847
17848
17849/* CAAM - Peripheral instance base addresses */
17851#define CAAM_BASE (0x40440000u)
17853#define CAAM ((CAAM_Type *)CAAM_BASE)
17855#define CAAM_BASE_ADDRS { CAAM_BASE }
17857#define CAAM_BASE_PTRS { CAAM }
17858 /* end of group CAAM_Peripheral_Access_Layer */
17862
17863
17864/* ----------------------------------------------------------------------------
17865 -- CAN Peripheral Access Layer
17866 ---------------------------------------------------------------------------- */
17867
17874typedef struct {
17875 __IO uint32_t MCR;
17876 __IO uint32_t CTRL1;
17877 __IO uint32_t TIMER;
17878 uint8_t RESERVED_0[4];
17879 __IO uint32_t RXMGMASK;
17880 __IO uint32_t RX14MASK;
17881 __IO uint32_t RX15MASK;
17882 __IO uint32_t ECR;
17883 __IO uint32_t ESR1;
17884 __IO uint32_t IMASK2;
17885 __IO uint32_t IMASK1;
17886 __IO uint32_t IFLAG2;
17887 __IO uint32_t IFLAG1;
17888 __IO uint32_t CTRL2;
17889 __I uint32_t ESR2;
17890 uint8_t RESERVED_1[8];
17891 __I uint32_t CRCR;
17892 __IO uint32_t RXFGMASK;
17893 __I uint32_t RXFIR;
17894 __IO uint32_t CBT;
17895 uint8_t RESERVED_2[44];
17896 union { /* offset: 0x80 */
17897 struct { /* offset: 0x80, array step: 0x10 */
17898 __IO uint32_t CS;
17899 __IO uint32_t ID;
17900 __IO uint32_t WORD[2];
17901 } MB_8B[64];
17902 struct { /* offset: 0x80 */
17903 struct { /* offset: 0x80, array step: 0x18 */
17904 __IO uint32_t CS;
17905 __IO uint32_t ID;
17906 __IO uint32_t WORD[4];
17907 } MB_16B_L[21];
17908 uint8_t RESERVED_0[8];
17909 struct { /* offset: 0x280, array step: 0x18 */
17910 __IO uint32_t CS;
17911 __IO uint32_t ID;
17912 __IO uint32_t WORD[4];
17913 } MB_16B_H[21];
17914 } MB_16B;
17915 struct { /* offset: 0x80 */
17916 struct { /* offset: 0x80, array step: 0x28 */
17917 __IO uint32_t CS;
17918 __IO uint32_t ID;
17919 __IO uint32_t WORD[8];
17920 } MB_32B_L[12];
17921 uint8_t RESERVED_0[32];
17922 struct { /* offset: 0x280, array step: 0x28 */
17923 __IO uint32_t CS;
17924 __IO uint32_t ID;
17925 __IO uint32_t WORD[8];
17926 } MB_32B_H[12];
17927 } MB_32B;
17928 struct { /* offset: 0x80 */
17929 struct { /* offset: 0x80, array step: 0x48 */
17930 __IO uint32_t CS;
17931 __IO uint32_t ID;
17932 __IO uint32_t WORD[16];
17933 } MB_64B_L[7];
17934 uint8_t RESERVED_0[8];
17935 struct { /* offset: 0x280, array step: 0x48 */
17936 __IO uint32_t CS;
17937 __IO uint32_t ID;
17938 __IO uint32_t WORD[16];
17939 } MB_64B_H[7];
17940 } MB_64B;
17941 struct { /* offset: 0x80, array step: 0x10 */
17942 __IO uint32_t CS;
17943 __IO uint32_t ID;
17944 __IO uint32_t WORD0;
17945 __IO uint32_t WORD1;
17946 } MB[64];
17947 };
17948 uint8_t RESERVED_3[1024];
17949 __IO uint32_t RXIMR[64];
17950 uint8_t RESERVED_4[352];
17951 __IO uint32_t MECR;
17952 __IO uint32_t ERRIAR;
17953 __IO uint32_t ERRIDPR;
17954 __IO uint32_t ERRIPPR;
17955 __I uint32_t RERRAR;
17956 __I uint32_t RERRDR;
17957 __I uint32_t RERRSYNR;
17958 __IO uint32_t ERRSR;
17959 uint8_t RESERVED_5[256];
17960 __IO uint32_t FDCTRL;
17961 __IO uint32_t FDCBT;
17962 __I uint32_t FDCRC;
17963} CAN_Type;
17964
17965/* ----------------------------------------------------------------------------
17966 -- CAN Register Masks
17967 ---------------------------------------------------------------------------- */
17968
17977#define CAN_MCR_MAXMB_MASK (0x7FU)
17978#define CAN_MCR_MAXMB_SHIFT (0U)
17981#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
17982
17983#define CAN_MCR_IDAM_MASK (0x300U)
17984#define CAN_MCR_IDAM_SHIFT (8U)
17991#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
17992
17993#define CAN_MCR_FDEN_MASK (0x800U)
17994#define CAN_MCR_FDEN_SHIFT (11U)
17999#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
18000
18001#define CAN_MCR_AEN_MASK (0x1000U)
18002#define CAN_MCR_AEN_SHIFT (12U)
18007#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
18008
18009#define CAN_MCR_LPRIOEN_MASK (0x2000U)
18010#define CAN_MCR_LPRIOEN_SHIFT (13U)
18015#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
18016
18017#define CAN_MCR_DMA_MASK (0x8000U)
18018#define CAN_MCR_DMA_SHIFT (15U)
18023#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
18024
18025#define CAN_MCR_IRMQ_MASK (0x10000U)
18026#define CAN_MCR_IRMQ_SHIFT (16U)
18032#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
18033
18034#define CAN_MCR_SRXDIS_MASK (0x20000U)
18035#define CAN_MCR_SRXDIS_SHIFT (17U)
18040#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
18041
18042#define CAN_MCR_DOZE_MASK (0x40000U)
18043#define CAN_MCR_DOZE_SHIFT (18U)
18048#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
18049
18050#define CAN_MCR_WAKSRC_MASK (0x80000U)
18051#define CAN_MCR_WAKSRC_SHIFT (19U)
18056#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
18057
18058#define CAN_MCR_LPMACK_MASK (0x100000U)
18059#define CAN_MCR_LPMACK_SHIFT (20U)
18064#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
18065
18066#define CAN_MCR_WRNEN_MASK (0x200000U)
18067#define CAN_MCR_WRNEN_SHIFT (21U)
18072#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
18073
18074#define CAN_MCR_SLFWAK_MASK (0x400000U)
18075#define CAN_MCR_SLFWAK_SHIFT (22U)
18080#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
18081
18082#define CAN_MCR_SUPV_MASK (0x800000U)
18083#define CAN_MCR_SUPV_SHIFT (23U)
18089#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
18090
18091#define CAN_MCR_FRZACK_MASK (0x1000000U)
18092#define CAN_MCR_FRZACK_SHIFT (24U)
18097#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
18098
18099#define CAN_MCR_SOFTRST_MASK (0x2000000U)
18100#define CAN_MCR_SOFTRST_SHIFT (25U)
18105#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
18106
18107#define CAN_MCR_WAKMSK_MASK (0x4000000U)
18108#define CAN_MCR_WAKMSK_SHIFT (26U)
18113#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
18114
18115#define CAN_MCR_NOTRDY_MASK (0x8000000U)
18116#define CAN_MCR_NOTRDY_SHIFT (27U)
18121#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
18122
18123#define CAN_MCR_HALT_MASK (0x10000000U)
18124#define CAN_MCR_HALT_SHIFT (28U)
18129#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
18130
18131#define CAN_MCR_RFEN_MASK (0x20000000U)
18132#define CAN_MCR_RFEN_SHIFT (29U)
18137#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
18138
18139#define CAN_MCR_FRZ_MASK (0x40000000U)
18140#define CAN_MCR_FRZ_SHIFT (30U)
18145#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
18146
18147#define CAN_MCR_MDIS_MASK (0x80000000U)
18148#define CAN_MCR_MDIS_SHIFT (31U)
18153#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
18159#define CAN_CTRL1_PROPSEG_MASK (0x7U)
18160#define CAN_CTRL1_PROPSEG_SHIFT (0U)
18163#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
18164
18165#define CAN_CTRL1_LOM_MASK (0x8U)
18166#define CAN_CTRL1_LOM_SHIFT (3U)
18171#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
18172
18173#define CAN_CTRL1_LBUF_MASK (0x10U)
18174#define CAN_CTRL1_LBUF_SHIFT (4U)
18179#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
18180
18181#define CAN_CTRL1_TSYN_MASK (0x20U)
18182#define CAN_CTRL1_TSYN_SHIFT (5U)
18187#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
18188
18189#define CAN_CTRL1_BOFFREC_MASK (0x40U)
18190#define CAN_CTRL1_BOFFREC_SHIFT (6U)
18195#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
18196
18197#define CAN_CTRL1_SMP_MASK (0x80U)
18198#define CAN_CTRL1_SMP_SHIFT (7U)
18204#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
18205
18206#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
18207#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
18212#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
18213
18214#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
18215#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
18220#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
18221
18222#define CAN_CTRL1_LPB_MASK (0x1000U)
18223#define CAN_CTRL1_LPB_SHIFT (12U)
18228#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
18229
18230#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
18231#define CAN_CTRL1_CLKSRC_SHIFT (13U)
18236#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
18237
18238#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
18239#define CAN_CTRL1_ERRMSK_SHIFT (14U)
18244#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
18245
18246#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
18247#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
18252#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
18253
18254#define CAN_CTRL1_PSEG2_MASK (0x70000U)
18255#define CAN_CTRL1_PSEG2_SHIFT (16U)
18258#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
18259
18260#define CAN_CTRL1_PSEG1_MASK (0x380000U)
18261#define CAN_CTRL1_PSEG1_SHIFT (19U)
18264#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
18265
18266#define CAN_CTRL1_RJW_MASK (0xC00000U)
18267#define CAN_CTRL1_RJW_SHIFT (22U)
18270#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
18271
18272#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
18273#define CAN_CTRL1_PRESDIV_SHIFT (24U)
18276#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
18282#define CAN_TIMER_TIMER_MASK (0xFFFFU)
18283#define CAN_TIMER_TIMER_SHIFT (0U)
18286#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
18292#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
18293#define CAN_RXMGMASK_MG_SHIFT (0U)
18296#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
18302#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
18303#define CAN_RX14MASK_RX14M_SHIFT (0U)
18306#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
18312#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
18313#define CAN_RX15MASK_RX15M_SHIFT (0U)
18316#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
18322#define CAN_ECR_TXERRCNT_MASK (0xFFU)
18323#define CAN_ECR_TXERRCNT_SHIFT (0U)
18326#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
18327
18328#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
18329#define CAN_ECR_RXERRCNT_SHIFT (8U)
18332#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
18333
18334#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)
18335#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U)
18338#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
18339
18340#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)
18341#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U)
18344#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
18350#define CAN_ESR1_WAKINT_MASK (0x1U)
18351#define CAN_ESR1_WAKINT_SHIFT (0U)
18356#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
18357
18358#define CAN_ESR1_ERRINT_MASK (0x2U)
18359#define CAN_ESR1_ERRINT_SHIFT (1U)
18364#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
18365
18366#define CAN_ESR1_BOFFINT_MASK (0x4U)
18367#define CAN_ESR1_BOFFINT_SHIFT (2U)
18372#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
18373
18374#define CAN_ESR1_RX_MASK (0x8U)
18375#define CAN_ESR1_RX_SHIFT (3U)
18380#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
18381
18382#define CAN_ESR1_FLTCONF_MASK (0x30U)
18383#define CAN_ESR1_FLTCONF_SHIFT (4U)
18389#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
18390
18391#define CAN_ESR1_TX_MASK (0x40U)
18392#define CAN_ESR1_TX_SHIFT (6U)
18397#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
18398
18399#define CAN_ESR1_IDLE_MASK (0x80U)
18400#define CAN_ESR1_IDLE_SHIFT (7U)
18405#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
18406
18407#define CAN_ESR1_RXWRN_MASK (0x100U)
18408#define CAN_ESR1_RXWRN_SHIFT (8U)
18413#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
18414
18415#define CAN_ESR1_TXWRN_MASK (0x200U)
18416#define CAN_ESR1_TXWRN_SHIFT (9U)
18421#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
18422
18423#define CAN_ESR1_STFERR_MASK (0x400U)
18424#define CAN_ESR1_STFERR_SHIFT (10U)
18429#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
18430
18431#define CAN_ESR1_FRMERR_MASK (0x800U)
18432#define CAN_ESR1_FRMERR_SHIFT (11U)
18437#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
18438
18439#define CAN_ESR1_CRCERR_MASK (0x1000U)
18440#define CAN_ESR1_CRCERR_SHIFT (12U)
18445#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
18446
18447#define CAN_ESR1_ACKERR_MASK (0x2000U)
18448#define CAN_ESR1_ACKERR_SHIFT (13U)
18453#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
18454
18455#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
18456#define CAN_ESR1_BIT0ERR_SHIFT (14U)
18461#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
18462
18463#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
18464#define CAN_ESR1_BIT1ERR_SHIFT (15U)
18469#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
18470
18471#define CAN_ESR1_RWRNINT_MASK (0x10000U)
18472#define CAN_ESR1_RWRNINT_SHIFT (16U)
18477#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
18478
18479#define CAN_ESR1_TWRNINT_MASK (0x20000U)
18480#define CAN_ESR1_TWRNINT_SHIFT (17U)
18485#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
18486
18487#define CAN_ESR1_SYNCH_MASK (0x40000U)
18488#define CAN_ESR1_SYNCH_SHIFT (18U)
18493#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
18494
18495#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U)
18496#define CAN_ESR1_BOFFDONEINT_SHIFT (19U)
18501#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
18502
18503#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U)
18504#define CAN_ESR1_ERRINT_FAST_SHIFT (20U)
18509#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
18510
18511#define CAN_ESR1_ERROVR_MASK (0x200000U)
18512#define CAN_ESR1_ERROVR_SHIFT (21U)
18517#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
18518
18519#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U)
18520#define CAN_ESR1_STFERR_FAST_SHIFT (26U)
18525#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
18526
18527#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)
18528#define CAN_ESR1_FRMERR_FAST_SHIFT (27U)
18533#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
18534
18535#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)
18536#define CAN_ESR1_CRCERR_FAST_SHIFT (28U)
18541#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
18542
18543#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)
18544#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)
18549#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
18550
18551#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)
18552#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)
18557#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
18563#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)
18564#define CAN_IMASK2_BUF63TO32M_SHIFT (0U)
18567#define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
18573#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)
18574#define CAN_IMASK1_BUF31TO0M_SHIFT (0U)
18577#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
18583#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)
18584#define CAN_IFLAG2_BUF63TO32I_SHIFT (0U)
18587#define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
18593#define CAN_IFLAG1_BUF0I_MASK (0x1U)
18594#define CAN_IFLAG1_BUF0I_SHIFT (0U)
18599#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
18600
18601#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
18602#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
18605#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
18606
18607#define CAN_IFLAG1_BUF5I_MASK (0x20U)
18608#define CAN_IFLAG1_BUF5I_SHIFT (5U)
18614#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
18615
18616#define CAN_IFLAG1_BUF6I_MASK (0x40U)
18617#define CAN_IFLAG1_BUF6I_SHIFT (6U)
18622#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
18623
18624#define CAN_IFLAG1_BUF7I_MASK (0x80U)
18625#define CAN_IFLAG1_BUF7I_SHIFT (7U)
18630#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
18631
18632#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
18633#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
18636#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
18642#define CAN_CTRL2_EDFLTDIS_MASK (0x800U)
18643#define CAN_CTRL2_EDFLTDIS_SHIFT (11U)
18648#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
18649
18650#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)
18651#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U)
18656#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
18657
18658#define CAN_CTRL2_PREXCEN_MASK (0x4000U)
18659#define CAN_CTRL2_PREXCEN_SHIFT (14U)
18664#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
18665
18666#define CAN_CTRL2_TIMER_SRC_MASK (0x8000U)
18667#define CAN_CTRL2_TIMER_SRC_SHIFT (15U)
18674#define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)
18675
18676#define CAN_CTRL2_EACEN_MASK (0x10000U)
18677#define CAN_CTRL2_EACEN_SHIFT (16U)
18683#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
18684
18685#define CAN_CTRL2_RRS_MASK (0x20000U)
18686#define CAN_CTRL2_RRS_SHIFT (17U)
18691#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
18692
18693#define CAN_CTRL2_MRP_MASK (0x40000U)
18694#define CAN_CTRL2_MRP_SHIFT (18U)
18699#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
18700
18701#define CAN_CTRL2_TASD_MASK (0xF80000U)
18702#define CAN_CTRL2_TASD_SHIFT (19U)
18705#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
18706
18707#define CAN_CTRL2_RFFN_MASK (0xF000000U)
18708#define CAN_CTRL2_RFFN_SHIFT (24U)
18711#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
18712
18713#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
18714#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
18719#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
18720
18721#define CAN_CTRL2_ECRWRE_MASK (0x20000000U)
18722#define CAN_CTRL2_ECRWRE_SHIFT (29U)
18727#define CAN_CTRL2_ECRWRE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK)
18728
18729#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)
18730#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)
18735#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
18736
18737#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)
18738#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)
18743#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
18749#define CAN_ESR2_IMB_MASK (0x2000U)
18750#define CAN_ESR2_IMB_SHIFT (13U)
18755#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
18756
18757#define CAN_ESR2_VPS_MASK (0x4000U)
18758#define CAN_ESR2_VPS_SHIFT (14U)
18763#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
18764
18765#define CAN_ESR2_LPTM_MASK (0x7F0000U)
18766#define CAN_ESR2_LPTM_SHIFT (16U)
18769#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
18775#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
18776#define CAN_CRCR_TXCRC_SHIFT (0U)
18779#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
18780
18781#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
18782#define CAN_CRCR_MBCRC_SHIFT (16U)
18785#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
18791#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
18792#define CAN_RXFGMASK_FGM_SHIFT (0U)
18795#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
18801#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
18802#define CAN_RXFIR_IDHIT_SHIFT (0U)
18805#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
18811#define CAN_CBT_EPSEG2_MASK (0x1FU)
18812#define CAN_CBT_EPSEG2_SHIFT (0U)
18815#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
18816
18817#define CAN_CBT_EPSEG1_MASK (0x3E0U)
18818#define CAN_CBT_EPSEG1_SHIFT (5U)
18821#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
18822
18823#define CAN_CBT_EPROPSEG_MASK (0xFC00U)
18824#define CAN_CBT_EPROPSEG_SHIFT (10U)
18827#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
18828
18829#define CAN_CBT_ERJW_MASK (0x1F0000U)
18830#define CAN_CBT_ERJW_SHIFT (16U)
18833#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
18834
18835#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U)
18836#define CAN_CBT_EPRESDIV_SHIFT (21U)
18839#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
18840
18841#define CAN_CBT_BTF_MASK (0x80000000U)
18842#define CAN_CBT_BTF_SHIFT (31U)
18847#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
18850/* The count of CAN_CS */
18851#define CAN_CS_COUNT_MB8B (64U)
18852
18853/* The count of CAN_ID */
18854#define CAN_ID_COUNT_MB8B (64U)
18855
18856/* The count of CAN_WORD */
18857#define CAN_WORD_COUNT_MB8B (64U)
18858
18859/* The count of CAN_WORD */
18860#define CAN_WORD_COUNT_MB8B2 (2U)
18861
18862/* The count of CAN_CS */
18863#define CAN_CS_COUNT_MB16B_L (21U)
18864
18865/* The count of CAN_ID */
18866#define CAN_ID_COUNT_MB16B_L (21U)
18867
18868/* The count of CAN_WORD */
18869#define CAN_WORD_COUNT_MB16B_L (21U)
18870
18871/* The count of CAN_WORD */
18872#define CAN_WORD_COUNT_MB16B_L2 (4U)
18873
18874/* The count of CAN_CS */
18875#define CAN_CS_COUNT_MB16B_H (21U)
18876
18877/* The count of CAN_ID */
18878#define CAN_ID_COUNT_MB16B_H (21U)
18879
18880/* The count of CAN_WORD */
18881#define CAN_WORD_COUNT_MB16B_H (21U)
18882
18883/* The count of CAN_WORD */
18884#define CAN_WORD_COUNT_MB16B_H2 (4U)
18885
18886/* The count of CAN_CS */
18887#define CAN_CS_COUNT_MB32B_L (12U)
18888
18889/* The count of CAN_ID */
18890#define CAN_ID_COUNT_MB32B_L (12U)
18891
18892/* The count of CAN_WORD */
18893#define CAN_WORD_COUNT_MB32B_L (12U)
18894
18895/* The count of CAN_WORD */
18896#define CAN_WORD_COUNT_MB32B_L2 (8U)
18897
18898/* The count of CAN_CS */
18899#define CAN_CS_COUNT_MB32B_H (12U)
18900
18901/* The count of CAN_ID */
18902#define CAN_ID_COUNT_MB32B_H (12U)
18903
18904/* The count of CAN_WORD */
18905#define CAN_WORD_COUNT_MB32B_H (12U)
18906
18907/* The count of CAN_WORD */
18908#define CAN_WORD_COUNT_MB32B_H2 (8U)
18909
18913#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
18914#define CAN_CS_TIME_STAMP_SHIFT (0U)
18919#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
18920
18921#define CAN_CS_DLC_MASK (0xF0000U)
18922#define CAN_CS_DLC_SHIFT (16U)
18925#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
18926
18927#define CAN_CS_RTR_MASK (0x100000U)
18928#define CAN_CS_RTR_SHIFT (20U)
18931#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
18932
18933#define CAN_CS_IDE_MASK (0x200000U)
18934#define CAN_CS_IDE_SHIFT (21U)
18937#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
18938
18939#define CAN_CS_SRR_MASK (0x400000U)
18940#define CAN_CS_SRR_SHIFT (22U)
18943#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
18944
18945#define CAN_CS_CODE_MASK (0xF000000U)
18946#define CAN_CS_CODE_SHIFT (24U)
18950#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
18951
18952#define CAN_CS_ESI_MASK (0x20000000U)
18953#define CAN_CS_ESI_SHIFT (29U)
18956#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
18957
18958#define CAN_CS_BRS_MASK (0x40000000U)
18959#define CAN_CS_BRS_SHIFT (30U)
18962#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
18963
18964#define CAN_CS_EDL_MASK (0x80000000U)
18965#define CAN_CS_EDL_SHIFT (31U)
18969#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
18972/* The count of CAN_CS */
18973#define CAN_CS_COUNT_MB64B_L (7U)
18974
18978#define CAN_ID_EXT_MASK (0x3FFFFU)
18979#define CAN_ID_EXT_SHIFT (0U)
18982#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
18983
18984#define CAN_ID_STD_MASK (0x1FFC0000U)
18985#define CAN_ID_STD_SHIFT (18U)
18988#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
18989
18990#define CAN_ID_PRIO_MASK (0xE0000000U)
18991#define CAN_ID_PRIO_SHIFT (29U)
18996#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
18999/* The count of CAN_ID */
19000#define CAN_ID_COUNT_MB64B_L (7U)
19001
19005#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU)
19006#define CAN_WORD_DATA_BYTE_3_SHIFT (0U)
19009#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
19010
19011#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU)
19012#define CAN_WORD_DATA_BYTE_7_SHIFT (0U)
19015#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
19016
19017#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU)
19018#define CAN_WORD_DATA_BYTE_11_SHIFT (0U)
19021#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
19022
19023#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU)
19024#define CAN_WORD_DATA_BYTE_15_SHIFT (0U)
19027#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
19028
19029#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU)
19030#define CAN_WORD_DATA_BYTE_19_SHIFT (0U)
19033#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
19034
19035#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU)
19036#define CAN_WORD_DATA_BYTE_23_SHIFT (0U)
19039#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
19040
19041#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU)
19042#define CAN_WORD_DATA_BYTE_27_SHIFT (0U)
19045#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
19046
19047#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU)
19048#define CAN_WORD_DATA_BYTE_31_SHIFT (0U)
19051#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
19052
19053#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU)
19054#define CAN_WORD_DATA_BYTE_35_SHIFT (0U)
19057#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
19058
19059#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU)
19060#define CAN_WORD_DATA_BYTE_39_SHIFT (0U)
19063#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
19064
19065#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU)
19066#define CAN_WORD_DATA_BYTE_43_SHIFT (0U)
19069#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
19070
19071#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU)
19072#define CAN_WORD_DATA_BYTE_47_SHIFT (0U)
19075#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
19076
19077#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU)
19078#define CAN_WORD_DATA_BYTE_51_SHIFT (0U)
19081#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
19082
19083#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU)
19084#define CAN_WORD_DATA_BYTE_55_SHIFT (0U)
19087#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
19088
19089#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU)
19090#define CAN_WORD_DATA_BYTE_59_SHIFT (0U)
19093#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
19094
19095#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU)
19096#define CAN_WORD_DATA_BYTE_63_SHIFT (0U)
19099#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
19100
19101#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U)
19102#define CAN_WORD_DATA_BYTE_2_SHIFT (8U)
19105#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
19106
19107#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U)
19108#define CAN_WORD_DATA_BYTE_6_SHIFT (8U)
19111#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
19112
19113#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U)
19114#define CAN_WORD_DATA_BYTE_10_SHIFT (8U)
19117#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
19118
19119#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U)
19120#define CAN_WORD_DATA_BYTE_14_SHIFT (8U)
19123#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
19124
19125#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U)
19126#define CAN_WORD_DATA_BYTE_18_SHIFT (8U)
19129#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
19130
19131#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U)
19132#define CAN_WORD_DATA_BYTE_22_SHIFT (8U)
19135#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
19136
19137#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U)
19138#define CAN_WORD_DATA_BYTE_26_SHIFT (8U)
19141#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
19142
19143#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U)
19144#define CAN_WORD_DATA_BYTE_30_SHIFT (8U)
19147#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
19148
19149#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U)
19150#define CAN_WORD_DATA_BYTE_34_SHIFT (8U)
19153#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
19154
19155#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U)
19156#define CAN_WORD_DATA_BYTE_38_SHIFT (8U)
19159#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
19160
19161#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U)
19162#define CAN_WORD_DATA_BYTE_42_SHIFT (8U)
19165#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
19166
19167#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U)
19168#define CAN_WORD_DATA_BYTE_46_SHIFT (8U)
19171#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
19172
19173#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U)
19174#define CAN_WORD_DATA_BYTE_50_SHIFT (8U)
19177#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
19178
19179#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U)
19180#define CAN_WORD_DATA_BYTE_54_SHIFT (8U)
19183#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
19184
19185#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U)
19186#define CAN_WORD_DATA_BYTE_58_SHIFT (8U)
19189#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
19190
19191#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U)
19192#define CAN_WORD_DATA_BYTE_62_SHIFT (8U)
19195#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
19196
19197#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U)
19198#define CAN_WORD_DATA_BYTE_1_SHIFT (16U)
19201#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
19202
19203#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U)
19204#define CAN_WORD_DATA_BYTE_5_SHIFT (16U)
19207#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
19208
19209#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U)
19210#define CAN_WORD_DATA_BYTE_9_SHIFT (16U)
19213#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
19214
19215#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U)
19216#define CAN_WORD_DATA_BYTE_13_SHIFT (16U)
19219#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
19220
19221#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U)
19222#define CAN_WORD_DATA_BYTE_17_SHIFT (16U)
19225#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
19226
19227#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U)
19228#define CAN_WORD_DATA_BYTE_21_SHIFT (16U)
19231#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
19232
19233#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U)
19234#define CAN_WORD_DATA_BYTE_25_SHIFT (16U)
19237#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
19238
19239#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U)
19240#define CAN_WORD_DATA_BYTE_29_SHIFT (16U)
19243#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
19244
19245#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U)
19246#define CAN_WORD_DATA_BYTE_33_SHIFT (16U)
19249#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
19250
19251#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U)
19252#define CAN_WORD_DATA_BYTE_37_SHIFT (16U)
19255#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
19256
19257#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U)
19258#define CAN_WORD_DATA_BYTE_41_SHIFT (16U)
19261#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
19262
19263#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U)
19264#define CAN_WORD_DATA_BYTE_45_SHIFT (16U)
19267#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
19268
19269#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U)
19270#define CAN_WORD_DATA_BYTE_49_SHIFT (16U)
19273#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
19274
19275#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U)
19276#define CAN_WORD_DATA_BYTE_53_SHIFT (16U)
19279#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
19280
19281#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U)
19282#define CAN_WORD_DATA_BYTE_57_SHIFT (16U)
19285#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
19286
19287#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U)
19288#define CAN_WORD_DATA_BYTE_61_SHIFT (16U)
19291#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
19292
19293#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U)
19294#define CAN_WORD_DATA_BYTE_0_SHIFT (24U)
19297#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
19298
19299#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U)
19300#define CAN_WORD_DATA_BYTE_4_SHIFT (24U)
19303#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
19304
19305#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U)
19306#define CAN_WORD_DATA_BYTE_8_SHIFT (24U)
19309#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
19310
19311#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U)
19312#define CAN_WORD_DATA_BYTE_12_SHIFT (24U)
19315#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
19316
19317#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U)
19318#define CAN_WORD_DATA_BYTE_16_SHIFT (24U)
19321#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
19322
19323#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U)
19324#define CAN_WORD_DATA_BYTE_20_SHIFT (24U)
19327#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
19328
19329#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U)
19330#define CAN_WORD_DATA_BYTE_24_SHIFT (24U)
19333#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
19334
19335#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U)
19336#define CAN_WORD_DATA_BYTE_28_SHIFT (24U)
19339#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
19340
19341#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U)
19342#define CAN_WORD_DATA_BYTE_32_SHIFT (24U)
19345#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
19346
19347#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U)
19348#define CAN_WORD_DATA_BYTE_36_SHIFT (24U)
19351#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
19352
19353#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U)
19354#define CAN_WORD_DATA_BYTE_40_SHIFT (24U)
19357#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
19358
19359#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U)
19360#define CAN_WORD_DATA_BYTE_44_SHIFT (24U)
19363#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
19364
19365#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U)
19366#define CAN_WORD_DATA_BYTE_48_SHIFT (24U)
19369#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
19370
19371#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U)
19372#define CAN_WORD_DATA_BYTE_52_SHIFT (24U)
19375#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
19376
19377#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U)
19378#define CAN_WORD_DATA_BYTE_56_SHIFT (24U)
19381#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
19382
19383#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U)
19384#define CAN_WORD_DATA_BYTE_60_SHIFT (24U)
19387#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
19390/* The count of CAN_WORD */
19391#define CAN_WORD_COUNT_MB64B_L (7U)
19392
19393/* The count of CAN_WORD */
19394#define CAN_WORD_COUNT_MB64B_L2 (16U)
19395
19399#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
19400#define CAN_CS_TIME_STAMP_SHIFT (0U)
19405#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
19406
19407#define CAN_CS_DLC_MASK (0xF0000U)
19408#define CAN_CS_DLC_SHIFT (16U)
19411#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
19412
19413#define CAN_CS_RTR_MASK (0x100000U)
19414#define CAN_CS_RTR_SHIFT (20U)
19417#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
19418
19419#define CAN_CS_IDE_MASK (0x200000U)
19420#define CAN_CS_IDE_SHIFT (21U)
19423#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
19424
19425#define CAN_CS_SRR_MASK (0x400000U)
19426#define CAN_CS_SRR_SHIFT (22U)
19429#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
19430
19431#define CAN_CS_CODE_MASK (0xF000000U)
19432#define CAN_CS_CODE_SHIFT (24U)
19436#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
19437
19438#define CAN_CS_ESI_MASK (0x20000000U)
19439#define CAN_CS_ESI_SHIFT (29U)
19442#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
19443
19444#define CAN_CS_BRS_MASK (0x40000000U)
19445#define CAN_CS_BRS_SHIFT (30U)
19448#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
19449
19450#define CAN_CS_EDL_MASK (0x80000000U)
19451#define CAN_CS_EDL_SHIFT (31U)
19455#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
19458/* The count of CAN_CS */
19459#define CAN_CS_COUNT_MB64B_H (7U)
19460
19464#define CAN_ID_EXT_MASK (0x3FFFFU)
19465#define CAN_ID_EXT_SHIFT (0U)
19468#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
19469
19470#define CAN_ID_STD_MASK (0x1FFC0000U)
19471#define CAN_ID_STD_SHIFT (18U)
19474#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
19475
19476#define CAN_ID_PRIO_MASK (0xE0000000U)
19477#define CAN_ID_PRIO_SHIFT (29U)
19482#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
19485/* The count of CAN_ID */
19486#define CAN_ID_COUNT_MB64B_H (7U)
19487
19491#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU)
19492#define CAN_WORD_DATA_BYTE_3_SHIFT (0U)
19495#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
19496
19497#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU)
19498#define CAN_WORD_DATA_BYTE_7_SHIFT (0U)
19501#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
19502
19503#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU)
19504#define CAN_WORD_DATA_BYTE_11_SHIFT (0U)
19507#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
19508
19509#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU)
19510#define CAN_WORD_DATA_BYTE_15_SHIFT (0U)
19513#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
19514
19515#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU)
19516#define CAN_WORD_DATA_BYTE_19_SHIFT (0U)
19519#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
19520
19521#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU)
19522#define CAN_WORD_DATA_BYTE_23_SHIFT (0U)
19525#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
19526
19527#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU)
19528#define CAN_WORD_DATA_BYTE_27_SHIFT (0U)
19531#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
19532
19533#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU)
19534#define CAN_WORD_DATA_BYTE_31_SHIFT (0U)
19537#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
19538
19539#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU)
19540#define CAN_WORD_DATA_BYTE_35_SHIFT (0U)
19543#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
19544
19545#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU)
19546#define CAN_WORD_DATA_BYTE_39_SHIFT (0U)
19549#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
19550
19551#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU)
19552#define CAN_WORD_DATA_BYTE_43_SHIFT (0U)
19555#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
19556
19557#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU)
19558#define CAN_WORD_DATA_BYTE_47_SHIFT (0U)
19561#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
19562
19563#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU)
19564#define CAN_WORD_DATA_BYTE_51_SHIFT (0U)
19567#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
19568
19569#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU)
19570#define CAN_WORD_DATA_BYTE_55_SHIFT (0U)
19573#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
19574
19575#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU)
19576#define CAN_WORD_DATA_BYTE_59_SHIFT (0U)
19579#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
19580
19581#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU)
19582#define CAN_WORD_DATA_BYTE_63_SHIFT (0U)
19585#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
19586
19587#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U)
19588#define CAN_WORD_DATA_BYTE_2_SHIFT (8U)
19591#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
19592
19593#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U)
19594#define CAN_WORD_DATA_BYTE_6_SHIFT (8U)
19597#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
19598
19599#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U)
19600#define CAN_WORD_DATA_BYTE_10_SHIFT (8U)
19603#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
19604
19605#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U)
19606#define CAN_WORD_DATA_BYTE_14_SHIFT (8U)
19609#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
19610
19611#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U)
19612#define CAN_WORD_DATA_BYTE_18_SHIFT (8U)
19615#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
19616
19617#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U)
19618#define CAN_WORD_DATA_BYTE_22_SHIFT (8U)
19621#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
19622
19623#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U)
19624#define CAN_WORD_DATA_BYTE_26_SHIFT (8U)
19627#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
19628
19629#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U)
19630#define CAN_WORD_DATA_BYTE_30_SHIFT (8U)
19633#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
19634
19635#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U)
19636#define CAN_WORD_DATA_BYTE_34_SHIFT (8U)
19639#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
19640
19641#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U)
19642#define CAN_WORD_DATA_BYTE_38_SHIFT (8U)
19645#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
19646
19647#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U)
19648#define CAN_WORD_DATA_BYTE_42_SHIFT (8U)
19651#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
19652
19653#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U)
19654#define CAN_WORD_DATA_BYTE_46_SHIFT (8U)
19657#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
19658
19659#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U)
19660#define CAN_WORD_DATA_BYTE_50_SHIFT (8U)
19663#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
19664
19665#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U)
19666#define CAN_WORD_DATA_BYTE_54_SHIFT (8U)
19669#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
19670
19671#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U)
19672#define CAN_WORD_DATA_BYTE_58_SHIFT (8U)
19675#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
19676
19677#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U)
19678#define CAN_WORD_DATA_BYTE_62_SHIFT (8U)
19681#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
19682
19683#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U)
19684#define CAN_WORD_DATA_BYTE_1_SHIFT (16U)
19687#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
19688
19689#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U)
19690#define CAN_WORD_DATA_BYTE_5_SHIFT (16U)
19693#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
19694
19695#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U)
19696#define CAN_WORD_DATA_BYTE_9_SHIFT (16U)
19699#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
19700
19701#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U)
19702#define CAN_WORD_DATA_BYTE_13_SHIFT (16U)
19705#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
19706
19707#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U)
19708#define CAN_WORD_DATA_BYTE_17_SHIFT (16U)
19711#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
19712
19713#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U)
19714#define CAN_WORD_DATA_BYTE_21_SHIFT (16U)
19717#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
19718
19719#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U)
19720#define CAN_WORD_DATA_BYTE_25_SHIFT (16U)
19723#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
19724
19725#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U)
19726#define CAN_WORD_DATA_BYTE_29_SHIFT (16U)
19729#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
19730
19731#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U)
19732#define CAN_WORD_DATA_BYTE_33_SHIFT (16U)
19735#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
19736
19737#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U)
19738#define CAN_WORD_DATA_BYTE_37_SHIFT (16U)
19741#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
19742
19743#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U)
19744#define CAN_WORD_DATA_BYTE_41_SHIFT (16U)
19747#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
19748
19749#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U)
19750#define CAN_WORD_DATA_BYTE_45_SHIFT (16U)
19753#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
19754
19755#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U)
19756#define CAN_WORD_DATA_BYTE_49_SHIFT (16U)
19759#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
19760
19761#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U)
19762#define CAN_WORD_DATA_BYTE_53_SHIFT (16U)
19765#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
19766
19767#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U)
19768#define CAN_WORD_DATA_BYTE_57_SHIFT (16U)
19771#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
19772
19773#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U)
19774#define CAN_WORD_DATA_BYTE_61_SHIFT (16U)
19777#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
19778
19779#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U)
19780#define CAN_WORD_DATA_BYTE_0_SHIFT (24U)
19783#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
19784
19785#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U)
19786#define CAN_WORD_DATA_BYTE_4_SHIFT (24U)
19789#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
19790
19791#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U)
19792#define CAN_WORD_DATA_BYTE_8_SHIFT (24U)
19795#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
19796
19797#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U)
19798#define CAN_WORD_DATA_BYTE_12_SHIFT (24U)
19801#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
19802
19803#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U)
19804#define CAN_WORD_DATA_BYTE_16_SHIFT (24U)
19807#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
19808
19809#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U)
19810#define CAN_WORD_DATA_BYTE_20_SHIFT (24U)
19813#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
19814
19815#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U)
19816#define CAN_WORD_DATA_BYTE_24_SHIFT (24U)
19819#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
19820
19821#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U)
19822#define CAN_WORD_DATA_BYTE_28_SHIFT (24U)
19825#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
19826
19827#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U)
19828#define CAN_WORD_DATA_BYTE_32_SHIFT (24U)
19831#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
19832
19833#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U)
19834#define CAN_WORD_DATA_BYTE_36_SHIFT (24U)
19837#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
19838
19839#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U)
19840#define CAN_WORD_DATA_BYTE_40_SHIFT (24U)
19843#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
19844
19845#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U)
19846#define CAN_WORD_DATA_BYTE_44_SHIFT (24U)
19849#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
19850
19851#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U)
19852#define CAN_WORD_DATA_BYTE_48_SHIFT (24U)
19855#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
19856
19857#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U)
19858#define CAN_WORD_DATA_BYTE_52_SHIFT (24U)
19861#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
19862
19863#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U)
19864#define CAN_WORD_DATA_BYTE_56_SHIFT (24U)
19867#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
19868
19869#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U)
19870#define CAN_WORD_DATA_BYTE_60_SHIFT (24U)
19873#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
19876/* The count of CAN_WORD */
19877#define CAN_WORD_COUNT_MB64B_H (7U)
19878
19879/* The count of CAN_WORD */
19880#define CAN_WORD_COUNT_MB64B_H2 (16U)
19881
19882/* The count of CAN_CS */
19883#define CAN_CS_COUNT (64U)
19884
19885/* The count of CAN_ID */
19886#define CAN_ID_COUNT (64U)
19887
19891#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
19892#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
19895#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
19896
19897#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
19898#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
19901#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
19902
19903#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
19904#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
19907#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
19908
19909#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
19910#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
19913#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
19916/* The count of CAN_WORD0 */
19917#define CAN_WORD0_COUNT (64U)
19918
19922#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
19923#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
19926#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
19927
19928#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
19929#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
19932#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
19933
19934#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
19935#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
19938#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
19939
19940#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
19941#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
19944#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
19947/* The count of CAN_WORD1 */
19948#define CAN_WORD1_COUNT (64U)
19949
19953#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
19954#define CAN_RXIMR_MI_SHIFT (0U)
19957#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
19960/* The count of CAN_RXIMR */
19961#define CAN_RXIMR_COUNT (64U)
19962
19966#define CAN_MECR_NCEFAFRZ_MASK (0x80U)
19967#define CAN_MECR_NCEFAFRZ_SHIFT (7U)
19972#define CAN_MECR_NCEFAFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK)
19973
19974#define CAN_MECR_ECCDIS_MASK (0x100U)
19975#define CAN_MECR_ECCDIS_SHIFT (8U)
19980#define CAN_MECR_ECCDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK)
19981
19982#define CAN_MECR_RERRDIS_MASK (0x200U)
19983#define CAN_MECR_RERRDIS_SHIFT (9U)
19988#define CAN_MECR_RERRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK)
19989
19990#define CAN_MECR_EXTERRIE_MASK (0x2000U)
19991#define CAN_MECR_EXTERRIE_SHIFT (13U)
19996#define CAN_MECR_EXTERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK)
19997
19998#define CAN_MECR_FAERRIE_MASK (0x4000U)
19999#define CAN_MECR_FAERRIE_SHIFT (14U)
20004#define CAN_MECR_FAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK)
20005
20006#define CAN_MECR_HAERRIE_MASK (0x8000U)
20007#define CAN_MECR_HAERRIE_SHIFT (15U)
20012#define CAN_MECR_HAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK)
20013
20014#define CAN_MECR_CEI_MSK_MASK (0x10000U)
20015#define CAN_MECR_CEI_MSK_SHIFT (16U)
20020#define CAN_MECR_CEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK)
20021
20022#define CAN_MECR_FANCEI_MSK_MASK (0x40000U)
20023#define CAN_MECR_FANCEI_MSK_SHIFT (18U)
20028#define CAN_MECR_FANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK)
20029
20030#define CAN_MECR_HANCEI_MSK_MASK (0x80000U)
20031#define CAN_MECR_HANCEI_MSK_SHIFT (19U)
20036#define CAN_MECR_HANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK)
20037
20038#define CAN_MECR_ECRWRDIS_MASK (0x80000000U)
20039#define CAN_MECR_ECRWRDIS_SHIFT (31U)
20044#define CAN_MECR_ECRWRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK)
20050#define CAN_ERRIAR_INJADDR_L_MASK (0x3U)
20051#define CAN_ERRIAR_INJADDR_L_SHIFT (0U)
20054#define CAN_ERRIAR_INJADDR_L(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK)
20055
20056#define CAN_ERRIAR_INJADDR_H_MASK (0x3FFCU)
20057#define CAN_ERRIAR_INJADDR_H_SHIFT (2U)
20060#define CAN_ERRIAR_INJADDR_H(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK)
20066#define CAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFFU)
20067#define CAN_ERRIDPR_DFLIP_SHIFT (0U)
20070#define CAN_ERRIDPR_DFLIP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK)
20076#define CAN_ERRIPPR_PFLIP0_MASK (0x1FU)
20077#define CAN_ERRIPPR_PFLIP0_SHIFT (0U)
20080#define CAN_ERRIPPR_PFLIP0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK)
20081
20082#define CAN_ERRIPPR_PFLIP1_MASK (0x1F00U)
20083#define CAN_ERRIPPR_PFLIP1_SHIFT (8U)
20086#define CAN_ERRIPPR_PFLIP1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK)
20087
20088#define CAN_ERRIPPR_PFLIP2_MASK (0x1F0000U)
20089#define CAN_ERRIPPR_PFLIP2_SHIFT (16U)
20092#define CAN_ERRIPPR_PFLIP2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK)
20093
20094#define CAN_ERRIPPR_PFLIP3_MASK (0x1F000000U)
20095#define CAN_ERRIPPR_PFLIP3_SHIFT (24U)
20098#define CAN_ERRIPPR_PFLIP3(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK)
20104#define CAN_RERRAR_ERRADDR_MASK (0x3FFFU)
20105#define CAN_RERRAR_ERRADDR_SHIFT (0U)
20108#define CAN_RERRAR_ERRADDR(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK)
20109
20110#define CAN_RERRAR_SAID_MASK (0x70000U)
20111#define CAN_RERRAR_SAID_SHIFT (16U)
20114#define CAN_RERRAR_SAID(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK)
20115
20116#define CAN_RERRAR_NCE_MASK (0x1000000U)
20117#define CAN_RERRAR_NCE_SHIFT (24U)
20122#define CAN_RERRAR_NCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK)
20128#define CAN_RERRDR_RDATA_MASK (0xFFFFFFFFU)
20129#define CAN_RERRDR_RDATA_SHIFT (0U)
20132#define CAN_RERRDR_RDATA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK)
20138#define CAN_RERRSYNR_SYND0_MASK (0x1FU)
20139#define CAN_RERRSYNR_SYND0_SHIFT (0U)
20142#define CAN_RERRSYNR_SYND0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK)
20143
20144#define CAN_RERRSYNR_BE0_MASK (0x80U)
20145#define CAN_RERRSYNR_BE0_SHIFT (7U)
20150#define CAN_RERRSYNR_BE0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK)
20151
20152#define CAN_RERRSYNR_SYND1_MASK (0x1F00U)
20153#define CAN_RERRSYNR_SYND1_SHIFT (8U)
20156#define CAN_RERRSYNR_SYND1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK)
20157
20158#define CAN_RERRSYNR_BE1_MASK (0x8000U)
20159#define CAN_RERRSYNR_BE1_SHIFT (15U)
20164#define CAN_RERRSYNR_BE1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK)
20165
20166#define CAN_RERRSYNR_SYND2_MASK (0x1F0000U)
20167#define CAN_RERRSYNR_SYND2_SHIFT (16U)
20170#define CAN_RERRSYNR_SYND2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK)
20171
20172#define CAN_RERRSYNR_BE2_MASK (0x800000U)
20173#define CAN_RERRSYNR_BE2_SHIFT (23U)
20178#define CAN_RERRSYNR_BE2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK)
20179
20180#define CAN_RERRSYNR_SYND3_MASK (0x1F000000U)
20181#define CAN_RERRSYNR_SYND3_SHIFT (24U)
20184#define CAN_RERRSYNR_SYND3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK)
20185
20186#define CAN_RERRSYNR_BE3_MASK (0x80000000U)
20187#define CAN_RERRSYNR_BE3_SHIFT (31U)
20192#define CAN_RERRSYNR_BE3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK)
20198#define CAN_ERRSR_CEIOF_MASK (0x1U)
20199#define CAN_ERRSR_CEIOF_SHIFT (0U)
20204#define CAN_ERRSR_CEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK)
20205
20206#define CAN_ERRSR_FANCEIOF_MASK (0x4U)
20207#define CAN_ERRSR_FANCEIOF_SHIFT (2U)
20212#define CAN_ERRSR_FANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK)
20213
20214#define CAN_ERRSR_HANCEIOF_MASK (0x8U)
20215#define CAN_ERRSR_HANCEIOF_SHIFT (3U)
20220#define CAN_ERRSR_HANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK)
20221
20222#define CAN_ERRSR_CEIF_MASK (0x10000U)
20223#define CAN_ERRSR_CEIF_SHIFT (16U)
20228#define CAN_ERRSR_CEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK)
20229
20230#define CAN_ERRSR_FANCEIF_MASK (0x40000U)
20231#define CAN_ERRSR_FANCEIF_SHIFT (18U)
20236#define CAN_ERRSR_FANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK)
20237
20238#define CAN_ERRSR_HANCEIF_MASK (0x80000U)
20239#define CAN_ERRSR_HANCEIF_SHIFT (19U)
20244#define CAN_ERRSR_HANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK)
20250#define CAN_FDCTRL_TDCVAL_MASK (0x3FU)
20251#define CAN_FDCTRL_TDCVAL_SHIFT (0U)
20254#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
20255
20256#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U)
20257#define CAN_FDCTRL_TDCOFF_SHIFT (8U)
20260#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
20261
20262#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U)
20263#define CAN_FDCTRL_TDCFAIL_SHIFT (14U)
20268#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
20269
20270#define CAN_FDCTRL_TDCEN_MASK (0x8000U)
20271#define CAN_FDCTRL_TDCEN_SHIFT (15U)
20276#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
20277
20278#define CAN_FDCTRL_MBDSR0_MASK (0x30000U)
20279#define CAN_FDCTRL_MBDSR0_SHIFT (16U)
20286#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
20287
20288#define CAN_FDCTRL_MBDSR1_MASK (0x180000U)
20289#define CAN_FDCTRL_MBDSR1_SHIFT (19U)
20296#define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
20297
20298#define CAN_FDCTRL_FDRATE_MASK (0x80000000U)
20299#define CAN_FDCTRL_FDRATE_SHIFT (31U)
20304#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
20310#define CAN_FDCBT_FPSEG2_MASK (0x7U)
20311#define CAN_FDCBT_FPSEG2_SHIFT (0U)
20314#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
20315
20316#define CAN_FDCBT_FPSEG1_MASK (0xE0U)
20317#define CAN_FDCBT_FPSEG1_SHIFT (5U)
20320#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
20321
20322#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U)
20323#define CAN_FDCBT_FPROPSEG_SHIFT (10U)
20326#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
20327
20328#define CAN_FDCBT_FRJW_MASK (0x70000U)
20329#define CAN_FDCBT_FRJW_SHIFT (16U)
20332#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
20333
20334#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)
20335#define CAN_FDCBT_FPRESDIV_SHIFT (20U)
20338#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
20344#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)
20345#define CAN_FDCRC_FD_TXCRC_SHIFT (0U)
20348#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
20349
20350#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)
20351#define CAN_FDCRC_FD_MBCRC_SHIFT (24U)
20354#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) /* end of group CAN_Register_Masks */
20361
20362
20363/* CAN - Peripheral instance base addresses */
20365#define CAN1_BASE (0x400C4000u)
20367#define CAN1 ((CAN_Type *)CAN1_BASE)
20369#define CAN2_BASE (0x400C8000u)
20371#define CAN2 ((CAN_Type *)CAN2_BASE)
20373#define CAN3_BASE (0x40C3C000u)
20375#define CAN3 ((CAN_Type *)CAN3_BASE)
20377#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }
20379#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2, CAN3 }
20381#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20382#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20383#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20384#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20385#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20386#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20387 /* end of group CAN_Peripheral_Access_Layer */
20391
20392
20393/* ----------------------------------------------------------------------------
20394 -- CAN_WRAPPER Peripheral Access Layer
20395 ---------------------------------------------------------------------------- */
20396
20403typedef struct {
20404 uint8_t RESERVED_0[2528];
20405 __IO uint32_t GFWR;
20407
20408/* ----------------------------------------------------------------------------
20409 -- CAN_WRAPPER Register Masks
20410 ---------------------------------------------------------------------------- */
20411
20420#define CAN_WRAPPER_GFWR_GFWR_MASK (0xFFU)
20421#define CAN_WRAPPER_GFWR_GFWR_SHIFT (0U)
20424#define CAN_WRAPPER_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WRAPPER_GFWR_GFWR_SHIFT)) & CAN_WRAPPER_GFWR_GFWR_MASK) /* end of group CAN_WRAPPER_Register_Masks */
20431
20432
20433/* CAN_WRAPPER - Peripheral instance base addresses */
20435#define CAN1_WRAPPER_BASE (0x400C4000u)
20437#define CAN1_WRAPPER ((CAN_WRAPPER_Type *)CAN1_WRAPPER_BASE)
20439#define CAN2_WRAPPER_BASE (0x400C8000u)
20441#define CAN2_WRAPPER ((CAN_WRAPPER_Type *)CAN2_WRAPPER_BASE)
20443#define CAN3_WRAPPER_BASE (0x40C3C000u)
20445#define CAN3_WRAPPER ((CAN_WRAPPER_Type *)CAN3_WRAPPER_BASE)
20447#define CAN_WRAPPER_BASE_ADDRS { 0u, CAN1_WRAPPER_BASE, CAN2_WRAPPER_BASE, CAN3_WRAPPER_BASE }
20449#define CAN_WRAPPER_BASE_PTRS { (CAN_WRAPPER_Type *)0u, CAN1_WRAPPER, CAN2_WRAPPER, CAN3_WRAPPER }
20450 /* end of group CAN_WRAPPER_Peripheral_Access_Layer */
20454
20455
20456/* ----------------------------------------------------------------------------
20457 -- CCM Peripheral Access Layer
20458 ---------------------------------------------------------------------------- */
20459
20466typedef struct {
20467 struct { /* offset: 0x0, array step: 0x80 */
20468 __IO uint32_t CONTROL;
20472 uint8_t RESERVED_0[16];
20473 __I uint32_t STATUS0;
20474 __I uint32_t STATUS1;
20475 uint8_t RESERVED_1[4];
20476 __I uint32_t CONFIG;
20477 __IO uint32_t AUTHEN;
20478 __IO uint32_t AUTHEN_SET;
20479 __IO uint32_t AUTHEN_CLR;
20480 __IO uint32_t AUTHEN_TOG;
20481 __IO uint32_t SETPOINT[16];
20482 } CLOCK_ROOT[79];
20483 uint8_t RESERVED_0[6272];
20484 struct { /* offset: 0x4000, array step: 0x80 */
20485 __IO uint32_t CONTROL;
20489 uint8_t RESERVED_0[16];
20490 __IO uint32_t STATUS0;
20491 __I uint32_t STATUS1;
20492 uint8_t RESERVED_1[4];
20493 __I uint32_t CONFIG;
20494 __IO uint32_t AUTHEN;
20495 __IO uint32_t AUTHEN_SET;
20496 __IO uint32_t AUTHEN_CLR;
20497 __IO uint32_t AUTHEN_TOG;
20498 __IO uint32_t SETPOINT[16];
20499 } CLOCK_GROUP[2];
20500 uint8_t RESERVED_1[1792];
20501 struct { /* offset: 0x4800, array step: 0x20 */
20502 __IO uint32_t GPR_SHARED;
20503 __IO uint32_t SET;
20504 __IO uint32_t CLR;
20505 __IO uint32_t TOG;
20506 __IO uint32_t AUTHEN;
20507 __IO uint32_t AUTHEN_SET;
20508 __IO uint32_t AUTHEN_CLR;
20509 __IO uint32_t AUTHEN_TOG;
20510 } GPR_SHARED[8];
20511 uint8_t RESERVED_2[800];
20512 __IO uint32_t GPR_PRIVATE1;
20513 __IO uint32_t GPR_PRIVATE1_SET;
20514 __IO uint32_t GPR_PRIVATE1_CLR;
20515 __IO uint32_t GPR_PRIVATE1_TOG;
20516 __IO uint32_t GPR_PRIVATE1_AUTHEN;
20517 __IO uint32_t GPR_PRIVATE1_AUTHEN_SET;
20518 __IO uint32_t GPR_PRIVATE1_AUTHEN_CLR;
20519 __IO uint32_t GPR_PRIVATE1_AUTHEN_TOG;
20520 __IO uint32_t GPR_PRIVATE2;
20521 __IO uint32_t GPR_PRIVATE2_SET;
20522 __IO uint32_t GPR_PRIVATE2_CLR;
20523 __IO uint32_t GPR_PRIVATE2_TOG;
20524 __IO uint32_t GPR_PRIVATE2_AUTHEN;
20525 __IO uint32_t GPR_PRIVATE2_AUTHEN_SET;
20526 __IO uint32_t GPR_PRIVATE2_AUTHEN_CLR;
20527 __IO uint32_t GPR_PRIVATE2_AUTHEN_TOG;
20528 __IO uint32_t GPR_PRIVATE3;
20529 __IO uint32_t GPR_PRIVATE3_SET;
20530 __IO uint32_t GPR_PRIVATE3_CLR;
20531 __IO uint32_t GPR_PRIVATE3_TOG;
20532 __IO uint32_t GPR_PRIVATE3_AUTHEN;
20533 __IO uint32_t GPR_PRIVATE3_AUTHEN_SET;
20534 __IO uint32_t GPR_PRIVATE3_AUTHEN_CLR;
20535 __IO uint32_t GPR_PRIVATE3_AUTHEN_TOG;
20536 __IO uint32_t GPR_PRIVATE4;
20537 __IO uint32_t GPR_PRIVATE4_SET;
20538 __IO uint32_t GPR_PRIVATE4_CLR;
20539 __IO uint32_t GPR_PRIVATE4_TOG;
20540 __IO uint32_t GPR_PRIVATE4_AUTHEN;
20541 __IO uint32_t GPR_PRIVATE4_AUTHEN_SET;
20542 __IO uint32_t GPR_PRIVATE4_AUTHEN_CLR;
20543 __IO uint32_t GPR_PRIVATE4_AUTHEN_TOG;
20544 __IO uint32_t GPR_PRIVATE5;
20545 __IO uint32_t GPR_PRIVATE5_SET;
20546 __IO uint32_t GPR_PRIVATE5_CLR;
20547 __IO uint32_t GPR_PRIVATE5_TOG;
20548 __IO uint32_t GPR_PRIVATE5_AUTHEN;
20549 __IO uint32_t GPR_PRIVATE5_AUTHEN_SET;
20550 __IO uint32_t GPR_PRIVATE5_AUTHEN_CLR;
20551 __IO uint32_t GPR_PRIVATE5_AUTHEN_TOG;
20552 __IO uint32_t GPR_PRIVATE6;
20553 __IO uint32_t GPR_PRIVATE6_SET;
20554 __IO uint32_t GPR_PRIVATE6_CLR;
20555 __IO uint32_t GPR_PRIVATE6_TOG;
20556 __IO uint32_t GPR_PRIVATE6_AUTHEN;
20557 __IO uint32_t GPR_PRIVATE6_AUTHEN_SET;
20558 __IO uint32_t GPR_PRIVATE6_AUTHEN_CLR;
20559 __IO uint32_t GPR_PRIVATE6_AUTHEN_TOG;
20560 __IO uint32_t GPR_PRIVATE7;
20561 __IO uint32_t GPR_PRIVATE7_SET;
20562 __IO uint32_t GPR_PRIVATE7_CLR;
20563 __IO uint32_t GPR_PRIVATE7_TOG;
20564 __IO uint32_t GPR_PRIVATE7_AUTHEN;
20565 __IO uint32_t GPR_PRIVATE7_AUTHEN_SET;
20566 __IO uint32_t GPR_PRIVATE7_AUTHEN_CLR;
20567 __IO uint32_t GPR_PRIVATE7_AUTHEN_TOG;
20568 uint8_t RESERVED_3[768];
20569 struct { /* offset: 0x5000, array step: 0x20 */
20570 __IO uint32_t DIRECT;
20571 __IO uint32_t DOMAINr;
20572 __IO uint32_t SETPOINT;
20573 uint8_t RESERVED_0[4];
20574 __I uint32_t STATUS0;
20575 __I uint32_t STATUS1;
20576 __I uint32_t CONFIG;
20577 __IO uint32_t AUTHEN;
20578 } OSCPLL[29];
20579 uint8_t RESERVED_4[3168];
20580 struct { /* offset: 0x6000, array step: 0x20 */
20581 __IO uint32_t DIRECT;
20582 __IO uint32_t DOMAINr;
20583 __IO uint32_t SETPOINT;
20584 uint8_t RESERVED_0[4];
20585 __I uint32_t STATUS0;
20586 __I uint32_t STATUS1;
20587 __I uint32_t CONFIG;
20588 __IO uint32_t AUTHEN;
20589 } LPCG[138];
20590} CCM_Type;
20591
20592/* ----------------------------------------------------------------------------
20593 -- CCM Register Masks
20594 ---------------------------------------------------------------------------- */
20595
20604#define CCM_CLOCK_ROOT_CONTROL_DIV_MASK (0xFFU)
20605#define CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT (0U)
20608#define CCM_CLOCK_ROOT_CONTROL_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_DIV_MASK)
20609
20610#define CCM_CLOCK_ROOT_CONTROL_MUX_MASK (0x700U)
20611#define CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT (8U)
20614#define CCM_CLOCK_ROOT_CONTROL_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_MUX_MASK)
20615
20616#define CCM_CLOCK_ROOT_CONTROL_OFF_MASK (0x1000000U)
20617#define CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT (24U)
20622#define CCM_CLOCK_ROOT_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_OFF_MASK)
20625/* The count of CCM_CLOCK_ROOT_CONTROL */
20626#define CCM_CLOCK_ROOT_CONTROL_COUNT (79U)
20627
20631#define CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK (0xFFU)
20632#define CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT (0U)
20635#define CCM_CLOCK_ROOT_CONTROL_SET_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK)
20636
20637#define CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK (0x700U)
20638#define CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT (8U)
20641#define CCM_CLOCK_ROOT_CONTROL_SET_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK)
20642
20643#define CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK (0x1000000U)
20644#define CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT (24U)
20647#define CCM_CLOCK_ROOT_CONTROL_SET_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK)
20650/* The count of CCM_CLOCK_ROOT_CONTROL_SET */
20651#define CCM_CLOCK_ROOT_CONTROL_SET_COUNT (79U)
20652
20656#define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK (0xFFU)
20657#define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT (0U)
20660#define CCM_CLOCK_ROOT_CONTROL_CLR_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK)
20661
20662#define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK (0x700U)
20663#define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT (8U)
20666#define CCM_CLOCK_ROOT_CONTROL_CLR_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK)
20667
20668#define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK (0x1000000U)
20669#define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT (24U)
20672#define CCM_CLOCK_ROOT_CONTROL_CLR_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK)
20675/* The count of CCM_CLOCK_ROOT_CONTROL_CLR */
20676#define CCM_CLOCK_ROOT_CONTROL_CLR_COUNT (79U)
20677
20681#define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK (0xFFU)
20682#define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT (0U)
20685#define CCM_CLOCK_ROOT_CONTROL_TOG_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK)
20686
20687#define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK (0x700U)
20688#define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT (8U)
20691#define CCM_CLOCK_ROOT_CONTROL_TOG_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK)
20692
20693#define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK (0x1000000U)
20694#define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT (24U)
20697#define CCM_CLOCK_ROOT_CONTROL_TOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK)
20700/* The count of CCM_CLOCK_ROOT_CONTROL_TOG */
20701#define CCM_CLOCK_ROOT_CONTROL_TOG_COUNT (79U)
20702
20706#define CCM_CLOCK_ROOT_STATUS0_DIV_MASK (0xFFU)
20707#define CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT (0U)
20710#define CCM_CLOCK_ROOT_STATUS0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_DIV_MASK)
20711
20712#define CCM_CLOCK_ROOT_STATUS0_MUX_MASK (0x700U)
20713#define CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT (8U)
20716#define CCM_CLOCK_ROOT_STATUS0_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MUX_MASK)
20717
20718#define CCM_CLOCK_ROOT_STATUS0_OFF_MASK (0x1000000U)
20719#define CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT (24U)
20724#define CCM_CLOCK_ROOT_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_OFF_MASK)
20725
20726#define CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK (0x8000000U)
20727#define CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT (27U)
20732#define CCM_CLOCK_ROOT_STATUS0_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK)
20733
20734#define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK (0x10000000U)
20735#define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT (28U)
20740#define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK)
20741
20742#define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK (0x20000000U)
20743#define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT (29U)
20748#define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK)
20749
20750#define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK (0x40000000U)
20751#define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT (30U)
20756#define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK)
20757
20758#define CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK (0x80000000U)
20759#define CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT (31U)
20764#define CCM_CLOCK_ROOT_STATUS0_CHANGING(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK)
20767/* The count of CCM_CLOCK_ROOT_STATUS0 */
20768#define CCM_CLOCK_ROOT_STATUS0_COUNT (79U)
20769
20773#define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
20774#define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT (16U)
20777#define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK)
20778
20779#define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
20780#define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
20783#define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK)
20784
20785#define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK (0x1000000U)
20786#define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT (24U)
20791#define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK)
20792
20793#define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK (0x2000000U)
20794#define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT (25U)
20799#define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK)
20800
20801#define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK (0x4000000U)
20802#define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT (26U)
20807#define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK)
20808
20809#define CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK (0x8000000U)
20810#define CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT (27U)
20815#define CCM_CLOCK_ROOT_STATUS1_UP_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK)
20818/* The count of CCM_CLOCK_ROOT_STATUS1 */
20819#define CCM_CLOCK_ROOT_STATUS1_COUNT (79U)
20820
20824#define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
20825#define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
20830#define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK)
20833/* The count of CCM_CLOCK_ROOT_CONFIG */
20834#define CCM_CLOCK_ROOT_CONFIG_COUNT (79U)
20835
20839#define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK (0x1U)
20840#define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT (0U)
20845#define CCM_CLOCK_ROOT_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK)
20846
20847#define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK (0x2U)
20848#define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT (1U)
20853#define CCM_CLOCK_ROOT_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK)
20854
20855#define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK (0x10U)
20856#define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT (4U)
20861#define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK)
20862
20863#define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK (0xF00U)
20864#define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT (8U)
20869#define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK)
20870
20871#define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK (0x1000U)
20872#define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT (12U)
20877#define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK)
20878
20879#define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
20880#define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT (16U)
20885#define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK)
20886
20887#define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
20888#define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT (17U)
20893#define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK)
20894
20895#define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK (0x100000U)
20896#define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT (20U)
20901#define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK)
20904/* The count of CCM_CLOCK_ROOT_AUTHEN */
20905#define CCM_CLOCK_ROOT_AUTHEN_COUNT (79U)
20906
20910#define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK (0x1U)
20911#define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT (0U)
20914#define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK)
20915
20916#define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK (0x2U)
20917#define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT (1U)
20920#define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK)
20921
20922#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
20923#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
20926#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK)
20927
20928#define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
20929#define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
20932#define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK)
20933
20934#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
20935#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
20938#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK)
20939
20940#define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
20941#define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
20944#define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK)
20945
20946#define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U)
20947#define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U)
20950#define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK)
20951
20952#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
20953#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
20956#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK)
20959/* The count of CCM_CLOCK_ROOT_AUTHEN_SET */
20960#define CCM_CLOCK_ROOT_AUTHEN_SET_COUNT (79U)
20961
20965#define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK (0x1U)
20966#define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT (0U)
20969#define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK)
20970
20971#define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK (0x2U)
20972#define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT (1U)
20975#define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK)
20976
20977#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
20978#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
20981#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK)
20982
20983#define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
20984#define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
20987#define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK)
20988
20989#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
20990#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
20993#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK)
20994
20995#define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
20996#define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
20999#define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK)
21000
21001#define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U)
21002#define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U)
21005#define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK)
21006
21007#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
21008#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
21011#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK)
21014/* The count of CCM_CLOCK_ROOT_AUTHEN_CLR */
21015#define CCM_CLOCK_ROOT_AUTHEN_CLR_COUNT (79U)
21016
21020#define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK (0x1U)
21021#define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT (0U)
21024#define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK)
21025
21026#define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK (0x2U)
21027#define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT (1U)
21030#define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK)
21031
21032#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
21033#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
21036#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK)
21037
21038#define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
21039#define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
21042#define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK)
21043
21044#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
21045#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
21048#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK)
21049
21050#define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
21051#define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
21054#define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK)
21055
21056#define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U)
21057#define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U)
21060#define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK)
21061
21062#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
21063#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
21066#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK)
21069/* The count of CCM_CLOCK_ROOT_AUTHEN_TOG */
21070#define CCM_CLOCK_ROOT_AUTHEN_TOG_COUNT (79U)
21071
21075#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK (0xFFU)
21076#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT (0U)
21079#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK)
21080
21081#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK (0x700U)
21082#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT (8U)
21085#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK)
21086
21087#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK (0x1000000U)
21088#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT (24U)
21093#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK)
21094
21095#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U)
21096#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT (28U)
21099#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK)
21102/* The count of CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT */
21103#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT (79U)
21104
21105/* The count of CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT */
21106#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT2 (16U)
21107
21111#define CCM_CLOCK_GROUP_CONTROL_DIV0_MASK (0xFU)
21112#define CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT (0U)
21115#define CCM_CLOCK_GROUP_CONTROL_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_DIV0_MASK)
21116
21117#define CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK (0xFF0000U)
21118#define CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT (16U)
21121#define CCM_CLOCK_GROUP_CONTROL_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK)
21122
21123#define CCM_CLOCK_GROUP_CONTROL_OFF_MASK (0x1000000U)
21124#define CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT (24U)
21129#define CCM_CLOCK_GROUP_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_OFF_MASK)
21132/* The count of CCM_CLOCK_GROUP_CONTROL */
21133#define CCM_CLOCK_GROUP_CONTROL_COUNT (2U)
21134
21138#define CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK (0xFU)
21139#define CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT (0U)
21142#define CCM_CLOCK_GROUP_CONTROL_SET_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK)
21143
21144#define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK (0xFF0000U)
21145#define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT (16U)
21148#define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK)
21149
21150#define CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK (0x1000000U)
21151#define CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT (24U)
21154#define CCM_CLOCK_GROUP_CONTROL_SET_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK)
21157/* The count of CCM_CLOCK_GROUP_CONTROL_SET */
21158#define CCM_CLOCK_GROUP_CONTROL_SET_COUNT (2U)
21159
21163#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK (0xFU)
21164#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT (0U)
21167#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK)
21168
21169#define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK (0xFF0000U)
21170#define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT (16U)
21173#define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK)
21174
21175#define CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK (0x1000000U)
21176#define CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT (24U)
21179#define CCM_CLOCK_GROUP_CONTROL_CLR_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK)
21182/* The count of CCM_CLOCK_GROUP_CONTROL_CLR */
21183#define CCM_CLOCK_GROUP_CONTROL_CLR_COUNT (2U)
21184
21188#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK (0xFU)
21189#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT (0U)
21192#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK)
21193
21194#define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK (0xFF0000U)
21195#define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT (16U)
21198#define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK)
21199
21200#define CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK (0x1000000U)
21201#define CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT (24U)
21204#define CCM_CLOCK_GROUP_CONTROL_TOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK)
21207/* The count of CCM_CLOCK_GROUP_CONTROL_TOG */
21208#define CCM_CLOCK_GROUP_CONTROL_TOG_COUNT (2U)
21209
21213#define CCM_CLOCK_GROUP_STATUS0_DIV0_MASK (0xFU)
21214#define CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT (0U)
21217#define CCM_CLOCK_GROUP_STATUS0_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_DIV0_MASK)
21218
21219#define CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK (0xFF0000U)
21220#define CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT (16U)
21223#define CCM_CLOCK_GROUP_STATUS0_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK)
21224
21225#define CCM_CLOCK_GROUP_STATUS0_OFF_MASK (0x1000000U)
21226#define CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT (24U)
21231#define CCM_CLOCK_GROUP_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_OFF_MASK)
21232
21233#define CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK (0x8000000U)
21234#define CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT (27U)
21239#define CCM_CLOCK_GROUP_STATUS0_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK)
21240
21241#define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK (0x10000000U)
21242#define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT (28U)
21247#define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK)
21248
21249#define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK (0x20000000U)
21250#define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT (29U)
21255#define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK)
21256
21257#define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK (0x40000000U)
21258#define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT (30U)
21263#define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK)
21264
21265#define CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK (0x80000000U)
21266#define CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT (31U)
21271#define CCM_CLOCK_GROUP_STATUS0_CHANGING(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK)
21274/* The count of CCM_CLOCK_GROUP_STATUS0 */
21275#define CCM_CLOCK_GROUP_STATUS0_COUNT (2U)
21276
21280#define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
21281#define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT (16U)
21284#define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK)
21285
21286#define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
21287#define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
21290#define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK)
21291
21292#define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK (0x1000000U)
21293#define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT (24U)
21298#define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK)
21299
21300#define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK (0x2000000U)
21301#define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT (25U)
21306#define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK)
21307
21308#define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK (0x4000000U)
21309#define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT (26U)
21314#define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK)
21315
21316#define CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK (0x8000000U)
21317#define CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT (27U)
21322#define CCM_CLOCK_GROUP_STATUS1_UP_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK)
21325/* The count of CCM_CLOCK_GROUP_STATUS1 */
21326#define CCM_CLOCK_GROUP_STATUS1_COUNT (2U)
21327
21331#define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
21332#define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
21337#define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK)
21340/* The count of CCM_CLOCK_GROUP_CONFIG */
21341#define CCM_CLOCK_GROUP_CONFIG_COUNT (2U)
21342
21346#define CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK (0x1U)
21347#define CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT (0U)
21352#define CCM_CLOCK_GROUP_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK)
21353
21354#define CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK (0x2U)
21355#define CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT (1U)
21360#define CCM_CLOCK_GROUP_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK)
21361
21362#define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK (0x10U)
21363#define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT (4U)
21368#define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK)
21369
21370#define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK (0xF00U)
21371#define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT (8U)
21374#define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK)
21375
21376#define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK (0x1000U)
21377#define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT (12U)
21382#define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK)
21383
21384#define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
21385#define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT (16U)
21390#define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK)
21391
21392#define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
21393#define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT (17U)
21396#define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK)
21397
21398#define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK (0x100000U)
21399#define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT (20U)
21404#define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK)
21407/* The count of CCM_CLOCK_GROUP_AUTHEN */
21408#define CCM_CLOCK_GROUP_AUTHEN_COUNT (2U)
21409
21413#define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK (0x1U)
21414#define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT (0U)
21417#define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK)
21418
21419#define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK (0x2U)
21420#define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT (1U)
21423#define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK)
21424
21425#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
21426#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
21429#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK)
21430
21431#define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
21432#define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
21435#define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK)
21436
21437#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
21438#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
21441#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK)
21442
21443#define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
21444#define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
21447#define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK)
21448
21449#define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U)
21450#define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U)
21453#define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK)
21454
21455#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
21456#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
21459#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK)
21462/* The count of CCM_CLOCK_GROUP_AUTHEN_SET */
21463#define CCM_CLOCK_GROUP_AUTHEN_SET_COUNT (2U)
21464
21468#define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK (0x1U)
21469#define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT (0U)
21472#define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK)
21473
21474#define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK (0x2U)
21475#define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT (1U)
21478#define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK)
21479
21480#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
21481#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
21484#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK)
21485
21486#define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
21487#define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
21490#define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK)
21491
21492#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
21493#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
21496#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK)
21497
21498#define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
21499#define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
21502#define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK)
21503
21504#define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U)
21505#define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U)
21508#define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK)
21509
21510#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
21511#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
21514#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK)
21517/* The count of CCM_CLOCK_GROUP_AUTHEN_CLR */
21518#define CCM_CLOCK_GROUP_AUTHEN_CLR_COUNT (2U)
21519
21523#define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK (0x1U)
21524#define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT (0U)
21527#define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK)
21528
21529#define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK (0x2U)
21530#define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT (1U)
21533#define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK)
21534
21535#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
21536#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
21539#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK)
21540
21541#define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
21542#define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
21545#define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK)
21546
21547#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
21548#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
21551#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK)
21552
21553#define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
21554#define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
21557#define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK)
21558
21559#define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U)
21560#define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U)
21563#define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK)
21564
21565#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
21566#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
21569#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK)
21572/* The count of CCM_CLOCK_GROUP_AUTHEN_TOG */
21573#define CCM_CLOCK_GROUP_AUTHEN_TOG_COUNT (2U)
21574
21578#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK (0xFU)
21579#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT (0U)
21587#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK)
21588
21589#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK (0xFF0000U)
21590#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT (16U)
21593#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK)
21594
21595#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK (0x1000000U)
21596#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT (24U)
21601#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK)
21602
21603#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U)
21604#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT (28U)
21607#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK)
21610/* The count of CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT */
21611#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT (2U)
21612
21613/* The count of CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT */
21614#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT2 (16U)
21615
21619#define CCM_GPR_SHARED_GPR_MASK (0xFFFFFFFFU)
21620#define CCM_GPR_SHARED_GPR_SHIFT (0U)
21623#define CCM_GPR_SHARED_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_GPR_SHIFT)) & CCM_GPR_SHARED_GPR_MASK)
21626/* The count of CCM_GPR_SHARED */
21627#define CCM_GPR_SHARED_COUNT (8U)
21628
21632#define CCM_GPR_SHARED_SET_GPR_MASK (0xFFFFFFFFU)
21633#define CCM_GPR_SHARED_SET_GPR_SHIFT (0U)
21636#define CCM_GPR_SHARED_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_SET_GPR_SHIFT)) & CCM_GPR_SHARED_SET_GPR_MASK)
21639/* The count of CCM_GPR_SHARED_SET */
21640#define CCM_GPR_SHARED_SET_COUNT (8U)
21641
21645#define CCM_GPR_SHARED_CLR_GPR_MASK (0xFFFFFFFFU)
21646#define CCM_GPR_SHARED_CLR_GPR_SHIFT (0U)
21649#define CCM_GPR_SHARED_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_CLR_GPR_SHIFT)) & CCM_GPR_SHARED_CLR_GPR_MASK)
21652/* The count of CCM_GPR_SHARED_CLR */
21653#define CCM_GPR_SHARED_CLR_COUNT (8U)
21654
21658#define CCM_GPR_SHARED_TOG_GPR_MASK (0xFFFFFFFFU)
21659#define CCM_GPR_SHARED_TOG_GPR_SHIFT (0U)
21662#define CCM_GPR_SHARED_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TOG_GPR_SHIFT)) & CCM_GPR_SHARED_TOG_GPR_MASK)
21665/* The count of CCM_GPR_SHARED_TOG */
21666#define CCM_GPR_SHARED_TOG_COUNT (8U)
21667
21671#define CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK (0x1U)
21672#define CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT (0U)
21677#define CCM_GPR_SHARED_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK)
21678
21679#define CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK (0x2U)
21680#define CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT (1U)
21685#define CCM_GPR_SHARED_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK)
21686
21687#define CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK (0x10U)
21688#define CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT (4U)
21693#define CCM_GPR_SHARED_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK)
21694
21695#define CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK (0xF00U)
21696#define CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT (8U)
21701#define CCM_GPR_SHARED_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK)
21702
21703#define CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK (0x1000U)
21704#define CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT (12U)
21709#define CCM_GPR_SHARED_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK)
21710
21711#define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
21712#define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT (16U)
21717#define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK)
21718
21719#define CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK (0x100000U)
21720#define CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT (20U)
21725#define CCM_GPR_SHARED_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK)
21728/* The count of CCM_GPR_SHARED_AUTHEN */
21729#define CCM_GPR_SHARED_AUTHEN_COUNT (8U)
21730
21734#define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK (0x1U)
21735#define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT (0U)
21738#define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK)
21739
21740#define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK (0x2U)
21741#define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT (1U)
21744#define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK)
21745
21746#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
21747#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
21750#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK)
21751
21752#define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
21753#define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
21756#define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK)
21757
21758#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
21759#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
21762#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK)
21763
21764#define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
21765#define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
21768#define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK)
21769
21770#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
21771#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
21774#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK)
21777/* The count of CCM_GPR_SHARED_AUTHEN_SET */
21778#define CCM_GPR_SHARED_AUTHEN_SET_COUNT (8U)
21779
21783#define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK (0x1U)
21784#define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT (0U)
21787#define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK)
21788
21789#define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK (0x2U)
21790#define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT (1U)
21793#define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK)
21794
21795#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
21796#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
21799#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK)
21800
21801#define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
21802#define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
21805#define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK)
21806
21807#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
21808#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
21811#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK)
21812
21813#define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
21814#define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
21817#define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK)
21818
21819#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
21820#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
21823#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK)
21826/* The count of CCM_GPR_SHARED_AUTHEN_CLR */
21827#define CCM_GPR_SHARED_AUTHEN_CLR_COUNT (8U)
21828
21832#define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK (0x1U)
21833#define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT (0U)
21836#define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK)
21837
21838#define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK (0x2U)
21839#define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT (1U)
21842#define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK)
21843
21844#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
21845#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
21848#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK)
21849
21850#define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
21851#define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
21854#define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK)
21855
21856#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
21857#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
21860#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK)
21861
21862#define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
21863#define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
21866#define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK)
21867
21868#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
21869#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
21872#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK)
21875/* The count of CCM_GPR_SHARED_AUTHEN_TOG */
21876#define CCM_GPR_SHARED_AUTHEN_TOG_COUNT (8U)
21877
21881#define CCM_GPR_PRIVATE1_GPR_MASK (0xFFFFFFFFU)
21882#define CCM_GPR_PRIVATE1_GPR_SHIFT (0U)
21885#define CCM_GPR_PRIVATE1_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_GPR_SHIFT)) & CCM_GPR_PRIVATE1_GPR_MASK)
21891#define CCM_GPR_PRIVATE1_SET_GPR_MASK (0xFFFFFFFFU)
21892#define CCM_GPR_PRIVATE1_SET_GPR_SHIFT (0U)
21895#define CCM_GPR_PRIVATE1_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE1_SET_GPR_MASK)
21901#define CCM_GPR_PRIVATE1_CLR_GPR_MASK (0xFFFFFFFFU)
21902#define CCM_GPR_PRIVATE1_CLR_GPR_SHIFT (0U)
21905#define CCM_GPR_PRIVATE1_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE1_CLR_GPR_MASK)
21911#define CCM_GPR_PRIVATE1_TOG_GPR_MASK (0xFFFFFFFFU)
21912#define CCM_GPR_PRIVATE1_TOG_GPR_SHIFT (0U)
21915#define CCM_GPR_PRIVATE1_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE1_TOG_GPR_MASK)
21921#define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK (0x1U)
21922#define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT (0U)
21927#define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK)
21928
21929#define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK (0x2U)
21930#define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT (1U)
21935#define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK)
21936
21937#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK (0x10U)
21938#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT (4U)
21943#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK)
21944
21945#define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK (0xF00U)
21946#define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT (8U)
21951#define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK)
21952
21953#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK (0x1000U)
21954#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT (12U)
21959#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK)
21960
21961#define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
21962#define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT (16U)
21967#define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK)
21968
21969#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK (0x100000U)
21970#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT (20U)
21975#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK)
21981#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK (0x1U)
21982#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT (0U)
21985#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK)
21986
21987#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK (0x2U)
21988#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT (1U)
21991#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK)
21992
21993#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
21994#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
21997#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK)
21998
21999#define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22000#define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22003#define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK)
22004
22005#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22006#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22009#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK)
22010
22011#define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22012#define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22015#define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK)
22016
22017#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22018#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22021#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK)
22027#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22028#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22031#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK)
22032
22033#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK (0x2U)
22034#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT (1U)
22037#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK)
22038
22039#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22040#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22043#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK)
22044
22045#define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22046#define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22049#define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK)
22050
22051#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22052#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22055#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK)
22056
22057#define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22058#define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22061#define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK)
22062
22063#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22064#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22067#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK)
22073#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22074#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22077#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK)
22078
22079#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK (0x2U)
22080#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT (1U)
22083#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK)
22084
22085#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22086#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22089#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK)
22090
22091#define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22092#define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22095#define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK)
22096
22097#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22098#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22101#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK)
22102
22103#define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22104#define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22107#define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK)
22108
22109#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22110#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22113#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK)
22119#define CCM_GPR_PRIVATE2_GPR_MASK (0xFFFFFFFFU)
22120#define CCM_GPR_PRIVATE2_GPR_SHIFT (0U)
22123#define CCM_GPR_PRIVATE2_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_GPR_SHIFT)) & CCM_GPR_PRIVATE2_GPR_MASK)
22129#define CCM_GPR_PRIVATE2_SET_GPR_MASK (0xFFFFFFFFU)
22130#define CCM_GPR_PRIVATE2_SET_GPR_SHIFT (0U)
22133#define CCM_GPR_PRIVATE2_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE2_SET_GPR_MASK)
22139#define CCM_GPR_PRIVATE2_CLR_GPR_MASK (0xFFFFFFFFU)
22140#define CCM_GPR_PRIVATE2_CLR_GPR_SHIFT (0U)
22143#define CCM_GPR_PRIVATE2_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE2_CLR_GPR_MASK)
22149#define CCM_GPR_PRIVATE2_TOG_GPR_MASK (0xFFFFFFFFU)
22150#define CCM_GPR_PRIVATE2_TOG_GPR_SHIFT (0U)
22153#define CCM_GPR_PRIVATE2_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE2_TOG_GPR_MASK)
22159#define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK (0x1U)
22160#define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT (0U)
22165#define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK)
22166
22167#define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK (0x2U)
22168#define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT (1U)
22173#define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK)
22174
22175#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK (0x10U)
22176#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT (4U)
22181#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK)
22182
22183#define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK (0xF00U)
22184#define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT (8U)
22189#define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK)
22190
22191#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK (0x1000U)
22192#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT (12U)
22197#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK)
22198
22199#define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22200#define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22205#define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK)
22206
22207#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK (0x100000U)
22208#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT (20U)
22213#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK)
22219#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK (0x1U)
22220#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT (0U)
22223#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK)
22224
22225#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK (0x2U)
22226#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT (1U)
22229#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK)
22230
22231#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22232#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22235#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK)
22236
22237#define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22238#define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22241#define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK)
22242
22243#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22244#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22247#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK)
22248
22249#define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22250#define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22253#define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK)
22254
22255#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22256#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22259#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK)
22265#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22266#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22269#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK)
22270
22271#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK (0x2U)
22272#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT (1U)
22275#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK)
22276
22277#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22278#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22281#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK)
22282
22283#define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22284#define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22287#define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK)
22288
22289#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22290#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22293#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK)
22294
22295#define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22296#define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22299#define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK)
22300
22301#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22302#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22305#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK)
22311#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22312#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22315#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK)
22316
22317#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK (0x2U)
22318#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT (1U)
22321#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK)
22322
22323#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22324#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22327#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK)
22328
22329#define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22330#define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22333#define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK)
22334
22335#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22336#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22339#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK)
22340
22341#define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22342#define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22345#define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK)
22346
22347#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22348#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22351#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK)
22357#define CCM_GPR_PRIVATE3_GPR_MASK (0xFFFFFFFFU)
22358#define CCM_GPR_PRIVATE3_GPR_SHIFT (0U)
22361#define CCM_GPR_PRIVATE3_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_GPR_SHIFT)) & CCM_GPR_PRIVATE3_GPR_MASK)
22367#define CCM_GPR_PRIVATE3_SET_GPR_MASK (0xFFFFFFFFU)
22368#define CCM_GPR_PRIVATE3_SET_GPR_SHIFT (0U)
22371#define CCM_GPR_PRIVATE3_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE3_SET_GPR_MASK)
22377#define CCM_GPR_PRIVATE3_CLR_GPR_MASK (0xFFFFFFFFU)
22378#define CCM_GPR_PRIVATE3_CLR_GPR_SHIFT (0U)
22381#define CCM_GPR_PRIVATE3_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE3_CLR_GPR_MASK)
22387#define CCM_GPR_PRIVATE3_TOG_GPR_MASK (0xFFFFFFFFU)
22388#define CCM_GPR_PRIVATE3_TOG_GPR_SHIFT (0U)
22391#define CCM_GPR_PRIVATE3_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE3_TOG_GPR_MASK)
22397#define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK (0x1U)
22398#define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT (0U)
22403#define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK)
22404
22405#define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK (0x2U)
22406#define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT (1U)
22411#define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK)
22412
22413#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK (0x10U)
22414#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT (4U)
22419#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK)
22420
22421#define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK (0xF00U)
22422#define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT (8U)
22427#define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK)
22428
22429#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK (0x1000U)
22430#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT (12U)
22435#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK)
22436
22437#define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22438#define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22443#define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK)
22444
22445#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK (0x100000U)
22446#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT (20U)
22451#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK)
22457#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK (0x1U)
22458#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT (0U)
22461#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK)
22462
22463#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK (0x2U)
22464#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT (1U)
22467#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK)
22468
22469#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22470#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22473#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK)
22474
22475#define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22476#define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22479#define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK)
22480
22481#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22482#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22485#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK)
22486
22487#define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22488#define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22491#define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK)
22492
22493#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22494#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22497#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK)
22503#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22504#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22507#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK)
22508
22509#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK (0x2U)
22510#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT (1U)
22513#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK)
22514
22515#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22516#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22519#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK)
22520
22521#define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22522#define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22525#define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK)
22526
22527#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22528#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22531#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK)
22532
22533#define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22534#define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22537#define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK)
22538
22539#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22540#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22543#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK)
22549#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22550#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22553#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK)
22554
22555#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK (0x2U)
22556#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT (1U)
22559#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK)
22560
22561#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22562#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22565#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK)
22566
22567#define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22568#define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22571#define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK)
22572
22573#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22574#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22577#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK)
22578
22579#define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22580#define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22583#define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK)
22584
22585#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22586#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22589#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK)
22595#define CCM_GPR_PRIVATE4_GPR_MASK (0xFFFFFFFFU)
22596#define CCM_GPR_PRIVATE4_GPR_SHIFT (0U)
22599#define CCM_GPR_PRIVATE4_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_GPR_SHIFT)) & CCM_GPR_PRIVATE4_GPR_MASK)
22605#define CCM_GPR_PRIVATE4_SET_GPR_MASK (0xFFFFFFFFU)
22606#define CCM_GPR_PRIVATE4_SET_GPR_SHIFT (0U)
22609#define CCM_GPR_PRIVATE4_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE4_SET_GPR_MASK)
22615#define CCM_GPR_PRIVATE4_CLR_GPR_MASK (0xFFFFFFFFU)
22616#define CCM_GPR_PRIVATE4_CLR_GPR_SHIFT (0U)
22619#define CCM_GPR_PRIVATE4_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE4_CLR_GPR_MASK)
22625#define CCM_GPR_PRIVATE4_TOG_GPR_MASK (0xFFFFFFFFU)
22626#define CCM_GPR_PRIVATE4_TOG_GPR_SHIFT (0U)
22629#define CCM_GPR_PRIVATE4_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE4_TOG_GPR_MASK)
22635#define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK (0x1U)
22636#define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT (0U)
22641#define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK)
22642
22643#define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK (0x2U)
22644#define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT (1U)
22649#define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK)
22650
22651#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK (0x10U)
22652#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT (4U)
22657#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK)
22658
22659#define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK (0xF00U)
22660#define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT (8U)
22665#define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK)
22666
22667#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK (0x1000U)
22668#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT (12U)
22673#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK)
22674
22675#define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22676#define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22681#define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK)
22682
22683#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK (0x100000U)
22684#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT (20U)
22689#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK)
22695#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK (0x1U)
22696#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT (0U)
22699#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK)
22700
22701#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK (0x2U)
22702#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT (1U)
22705#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK)
22706
22707#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22708#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22711#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK)
22712
22713#define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22714#define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22717#define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK)
22718
22719#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22720#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22723#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK)
22724
22725#define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22726#define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22729#define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK)
22730
22731#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22732#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22735#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK)
22741#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22742#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22745#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK)
22746
22747#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK (0x2U)
22748#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT (1U)
22751#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK)
22752
22753#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22754#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22757#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK)
22758
22759#define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22760#define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22763#define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK)
22764
22765#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22766#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22769#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK)
22770
22771#define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22772#define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22775#define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK)
22776
22777#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22778#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22781#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK)
22787#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22788#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22791#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK)
22792
22793#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK (0x2U)
22794#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT (1U)
22797#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK)
22798
22799#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22800#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22803#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK)
22804
22805#define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22806#define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22809#define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK)
22810
22811#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22812#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22815#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK)
22816
22817#define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22818#define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22821#define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK)
22822
22823#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22824#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22827#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK)
22833#define CCM_GPR_PRIVATE5_GPR_MASK (0xFFFFFFFFU)
22834#define CCM_GPR_PRIVATE5_GPR_SHIFT (0U)
22837#define CCM_GPR_PRIVATE5_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_GPR_SHIFT)) & CCM_GPR_PRIVATE5_GPR_MASK)
22843#define CCM_GPR_PRIVATE5_SET_GPR_MASK (0xFFFFFFFFU)
22844#define CCM_GPR_PRIVATE5_SET_GPR_SHIFT (0U)
22847#define CCM_GPR_PRIVATE5_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE5_SET_GPR_MASK)
22853#define CCM_GPR_PRIVATE5_CLR_GPR_MASK (0xFFFFFFFFU)
22854#define CCM_GPR_PRIVATE5_CLR_GPR_SHIFT (0U)
22857#define CCM_GPR_PRIVATE5_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE5_CLR_GPR_MASK)
22863#define CCM_GPR_PRIVATE5_TOG_GPR_MASK (0xFFFFFFFFU)
22864#define CCM_GPR_PRIVATE5_TOG_GPR_SHIFT (0U)
22867#define CCM_GPR_PRIVATE5_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE5_TOG_GPR_MASK)
22873#define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK (0x1U)
22874#define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT (0U)
22879#define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK)
22880
22881#define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK (0x2U)
22882#define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT (1U)
22887#define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK)
22888
22889#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK (0x10U)
22890#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT (4U)
22895#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK)
22896
22897#define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK (0xF00U)
22898#define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT (8U)
22903#define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK)
22904
22905#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK (0x1000U)
22906#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT (12U)
22911#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK)
22912
22913#define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22914#define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22919#define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK)
22920
22921#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK (0x100000U)
22922#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT (20U)
22927#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK)
22933#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK (0x1U)
22934#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT (0U)
22937#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK)
22938
22939#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK (0x2U)
22940#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT (1U)
22943#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK)
22944
22945#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22946#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22949#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK)
22950
22951#define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22952#define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22955#define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK)
22956
22957#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22958#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22961#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK)
22962
22963#define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22964#define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22967#define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK)
22968
22969#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22970#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22973#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK)
22979#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22980#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22983#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK)
22984
22985#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK (0x2U)
22986#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT (1U)
22989#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK)
22990
22991#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22992#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22995#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK)
22996
22997#define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22998#define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
23001#define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK)
23002
23003#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
23004#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
23007#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK)
23008
23009#define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
23010#define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
23013#define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK)
23014
23015#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
23016#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
23019#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK)
23025#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK (0x1U)
23026#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT (0U)
23029#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK)
23030
23031#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK (0x2U)
23032#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT (1U)
23035#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK)
23036
23037#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
23038#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
23041#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK)
23042
23043#define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
23044#define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
23047#define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK)
23048
23049#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
23050#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
23053#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK)
23054
23055#define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
23056#define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
23059#define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK)
23060
23061#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
23062#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
23065#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK)
23071#define CCM_GPR_PRIVATE6_GPR_MASK (0xFFFFFFFFU)
23072#define CCM_GPR_PRIVATE6_GPR_SHIFT (0U)
23075#define CCM_GPR_PRIVATE6_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_GPR_SHIFT)) & CCM_GPR_PRIVATE6_GPR_MASK)
23081#define CCM_GPR_PRIVATE6_SET_GPR_MASK (0xFFFFFFFFU)
23082#define CCM_GPR_PRIVATE6_SET_GPR_SHIFT (0U)
23085#define CCM_GPR_PRIVATE6_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE6_SET_GPR_MASK)
23091#define CCM_GPR_PRIVATE6_CLR_GPR_MASK (0xFFFFFFFFU)
23092#define CCM_GPR_PRIVATE6_CLR_GPR_SHIFT (0U)
23095#define CCM_GPR_PRIVATE6_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE6_CLR_GPR_MASK)
23101#define CCM_GPR_PRIVATE6_TOG_GPR_MASK (0xFFFFFFFFU)
23102#define CCM_GPR_PRIVATE6_TOG_GPR_SHIFT (0U)
23105#define CCM_GPR_PRIVATE6_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE6_TOG_GPR_MASK)
23111#define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK (0x1U)
23112#define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT (0U)
23117#define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK)
23118
23119#define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK (0x2U)
23120#define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT (1U)
23125#define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK)
23126
23127#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK (0x10U)
23128#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT (4U)
23133#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK)
23134
23135#define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK (0xF00U)
23136#define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT (8U)
23141#define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK)
23142
23143#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK (0x1000U)
23144#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT (12U)
23149#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK)
23150
23151#define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
23152#define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT (16U)
23157#define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK)
23158
23159#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK (0x100000U)
23160#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT (20U)
23165#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK)
23171#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK (0x1U)
23172#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT (0U)
23175#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK)
23176
23177#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK (0x2U)
23178#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT (1U)
23181#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK)
23182
23183#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
23184#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
23187#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK)
23188
23189#define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
23190#define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
23193#define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK)
23194
23195#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
23196#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
23199#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK)
23200
23201#define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
23202#define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
23205#define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK)
23206
23207#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
23208#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
23211#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK)
23217#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK (0x1U)
23218#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT (0U)
23221#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK)
23222
23223#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK (0x2U)
23224#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT (1U)
23227#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK)
23228
23229#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
23230#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
23233#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK)
23234
23235#define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
23236#define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
23239#define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK)
23240
23241#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
23242#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
23245#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK)
23246
23247#define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
23248#define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
23251#define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK)
23252
23253#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
23254#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
23257#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK)
23263#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK (0x1U)
23264#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT (0U)
23267#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK)
23268
23269#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK (0x2U)
23270#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT (1U)
23273#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK)
23274
23275#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
23276#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
23279#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK)
23280
23281#define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
23282#define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
23285#define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK)
23286
23287#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
23288#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
23291#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK)
23292
23293#define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
23294#define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
23297#define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK)
23298
23299#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
23300#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
23303#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK)
23309#define CCM_GPR_PRIVATE7_GPR_MASK (0xFFFFFFFFU)
23310#define CCM_GPR_PRIVATE7_GPR_SHIFT (0U)
23313#define CCM_GPR_PRIVATE7_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_GPR_SHIFT)) & CCM_GPR_PRIVATE7_GPR_MASK)
23319#define CCM_GPR_PRIVATE7_SET_GPR_MASK (0xFFFFFFFFU)
23320#define CCM_GPR_PRIVATE7_SET_GPR_SHIFT (0U)
23323#define CCM_GPR_PRIVATE7_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE7_SET_GPR_MASK)
23329#define CCM_GPR_PRIVATE7_CLR_GPR_MASK (0xFFFFFFFFU)
23330#define CCM_GPR_PRIVATE7_CLR_GPR_SHIFT (0U)
23333#define CCM_GPR_PRIVATE7_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE7_CLR_GPR_MASK)
23339#define CCM_GPR_PRIVATE7_TOG_GPR_MASK (0xFFFFFFFFU)
23340#define CCM_GPR_PRIVATE7_TOG_GPR_SHIFT (0U)
23343#define CCM_GPR_PRIVATE7_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE7_TOG_GPR_MASK)
23349#define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK (0x1U)
23350#define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT (0U)
23355#define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK)
23356
23357#define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK (0x2U)
23358#define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT (1U)
23363#define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK)
23364
23365#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK (0x10U)
23366#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT (4U)
23371#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK)
23372
23373#define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK (0xF00U)
23374#define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT (8U)
23379#define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK)
23380
23381#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK (0x1000U)
23382#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT (12U)
23387#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK)
23388
23389#define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
23390#define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT (16U)
23395#define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK)
23396
23397#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK (0x100000U)
23398#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT (20U)
23403#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK)
23409#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK (0x1U)
23410#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT (0U)
23413#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK)
23414
23415#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK (0x2U)
23416#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT (1U)
23419#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK)
23420
23421#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
23422#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
23425#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK)
23426
23427#define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
23428#define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
23431#define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK)
23432
23433#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
23434#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
23437#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK)
23438
23439#define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
23440#define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
23443#define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK)
23444
23445#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
23446#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
23449#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK)
23455#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK (0x1U)
23456#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT (0U)
23459#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK)
23460
23461#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK (0x2U)
23462#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT (1U)
23465#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK)
23466
23467#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
23468#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
23471#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK)
23472
23473#define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
23474#define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
23477#define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK)
23478
23479#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
23480#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
23483#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK)
23484
23485#define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
23486#define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
23489#define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK)
23490
23491#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
23492#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
23495#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK)
23501#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK (0x1U)
23502#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT (0U)
23505#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK)
23506
23507#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK (0x2U)
23508#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT (1U)
23511#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK)
23512
23513#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
23514#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
23517#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK)
23518
23519#define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
23520#define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
23523#define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK)
23524
23525#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
23526#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
23529#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK)
23530
23531#define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
23532#define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
23535#define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK)
23536
23537#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
23538#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
23541#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK)
23547#define CCM_OSCPLL_DIRECT_ON_MASK (0x1U)
23548#define CCM_OSCPLL_DIRECT_ON_SHIFT (0U)
23553#define CCM_OSCPLL_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DIRECT_ON_SHIFT)) & CCM_OSCPLL_DIRECT_ON_MASK)
23556/* The count of CCM_OSCPLL_DIRECT */
23557#define CCM_OSCPLL_DIRECT_COUNT (29U)
23558
23562#define CCM_OSCPLL_DOMAIN_LEVEL_MASK (0x7U)
23563#define CCM_OSCPLL_DOMAIN_LEVEL_SHIFT (0U)
23572#define CCM_OSCPLL_DOMAIN_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL_MASK)
23573
23574#define CCM_OSCPLL_DOMAIN_LEVEL0_MASK (0x70000U)
23575#define CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT (16U)
23584#define CCM_OSCPLL_DOMAIN_LEVEL0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL0_MASK)
23585
23586#define CCM_OSCPLL_DOMAIN_LEVEL1_MASK (0x700000U)
23587#define CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT (20U)
23596#define CCM_OSCPLL_DOMAIN_LEVEL1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL1_MASK)
23597
23598#define CCM_OSCPLL_DOMAIN_LEVEL2_MASK (0x7000000U)
23599#define CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT (24U)
23608#define CCM_OSCPLL_DOMAIN_LEVEL2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL2_MASK)
23609
23610#define CCM_OSCPLL_DOMAIN_LEVEL3_MASK (0x70000000U)
23611#define CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT (28U)
23620#define CCM_OSCPLL_DOMAIN_LEVEL3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL3_MASK)
23623/* The count of CCM_OSCPLL_DOMAIN */
23624#define CCM_OSCPLL_DOMAIN_COUNT (29U)
23625
23629#define CCM_OSCPLL_SETPOINT_SETPOINT_MASK (0xFFFFU)
23630#define CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT (0U)
23633#define CCM_OSCPLL_SETPOINT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT)) & CCM_OSCPLL_SETPOINT_SETPOINT_MASK)
23634
23635#define CCM_OSCPLL_SETPOINT_STANDBY_MASK (0xFFFF0000U)
23636#define CCM_OSCPLL_SETPOINT_STANDBY_SHIFT (16U)
23639#define CCM_OSCPLL_SETPOINT_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_STANDBY_SHIFT)) & CCM_OSCPLL_SETPOINT_STANDBY_MASK)
23642/* The count of CCM_OSCPLL_SETPOINT */
23643#define CCM_OSCPLL_SETPOINT_COUNT (29U)
23644
23648#define CCM_OSCPLL_STATUS0_ON_MASK (0x1U)
23649#define CCM_OSCPLL_STATUS0_ON_SHIFT (0U)
23654#define CCM_OSCPLL_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ON_SHIFT)) & CCM_OSCPLL_STATUS0_ON_MASK)
23655
23656#define CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK (0x10U)
23657#define CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT (4U)
23662#define CCM_OSCPLL_STATUS0_STATUS_EARLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK)
23663
23664#define CCM_OSCPLL_STATUS0_STATUS_LATE_MASK (0x20U)
23665#define CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT (5U)
23670#define CCM_OSCPLL_STATUS0_STATUS_LATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_LATE_MASK)
23671
23672#define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK (0xF00U)
23673#define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT (8U)
23692#define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK)
23693
23694#define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK (0xF000U)
23695#define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT (12U)
23714#define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK)
23715
23716#define CCM_OSCPLL_STATUS0_IN_USE_MASK (0x10000000U)
23717#define CCM_OSCPLL_STATUS0_IN_USE_SHIFT (28U)
23722#define CCM_OSCPLL_STATUS0_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_IN_USE_SHIFT)) & CCM_OSCPLL_STATUS0_IN_USE_MASK)
23725/* The count of CCM_OSCPLL_STATUS0 */
23726#define CCM_OSCPLL_STATUS0_COUNT (29U)
23727
23731#define CCM_OSCPLL_STATUS1_CPU0_MODE_MASK (0x3U)
23732#define CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT (0U)
23739#define CCM_OSCPLL_STATUS1_CPU0_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_MASK)
23740
23741#define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U)
23742#define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U)
23747#define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK)
23748
23749#define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK (0x8U)
23750#define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT (3U)
23755#define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK)
23756
23757#define CCM_OSCPLL_STATUS1_CPU1_MODE_MASK (0x30U)
23758#define CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT (4U)
23765#define CCM_OSCPLL_STATUS1_CPU1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_MASK)
23766
23767#define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U)
23768#define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U)
23773#define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK)
23774
23775#define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK (0x80U)
23776#define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT (7U)
23781#define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK)
23782
23783#define CCM_OSCPLL_STATUS1_CPU2_MODE_MASK (0x300U)
23784#define CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT (8U)
23791#define CCM_OSCPLL_STATUS1_CPU2_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_MASK)
23792
23793#define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U)
23794#define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U)
23799#define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK)
23800
23801#define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK (0x800U)
23802#define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT (11U)
23807#define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK)
23808
23809#define CCM_OSCPLL_STATUS1_CPU3_MODE_MASK (0x3000U)
23810#define CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT (12U)
23817#define CCM_OSCPLL_STATUS1_CPU3_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_MASK)
23818
23819#define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U)
23820#define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U)
23825#define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK)
23826
23827#define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK (0x8000U)
23828#define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT (15U)
23833#define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK)
23834
23835#define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
23836#define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT (16U)
23839#define CCM_OSCPLL_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK)
23840
23841#define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
23842#define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
23845#define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK)
23846
23847#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U)
23848#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U)
23853#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK)
23854
23855#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U)
23856#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U)
23861#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK)
23862
23863#define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U)
23864#define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U)
23869#define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK)
23870
23871#define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U)
23872#define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT (27U)
23877#define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK)
23878
23879#define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK (0x10000000U)
23880#define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT (28U)
23885#define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK)
23886
23887#define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK (0x20000000U)
23888#define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT (29U)
23893#define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK)
23894
23895#define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK (0x40000000U)
23896#define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT (30U)
23901#define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK)
23902
23903#define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK (0x80000000U)
23904#define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT (31U)
23909#define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK)
23912/* The count of CCM_OSCPLL_STATUS1 */
23913#define CCM_OSCPLL_STATUS1_COUNT (29U)
23914
23918#define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK (0x2U)
23919#define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT (1U)
23924#define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK)
23925
23926#define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
23927#define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
23932#define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK)
23935/* The count of CCM_OSCPLL_CONFIG */
23936#define CCM_OSCPLL_CONFIG_COUNT (29U)
23937
23941#define CCM_OSCPLL_AUTHEN_TZ_USER_MASK (0x1U)
23942#define CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT (0U)
23947#define CCM_OSCPLL_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK)
23948
23949#define CCM_OSCPLL_AUTHEN_TZ_NS_MASK (0x2U)
23950#define CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT (1U)
23955#define CCM_OSCPLL_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_NS_MASK)
23956
23957#define CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK (0x10U)
23958#define CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT (4U)
23963#define CCM_OSCPLL_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK)
23964
23965#define CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK (0xF00U)
23966#define CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT (8U)
23969#define CCM_OSCPLL_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK)
23970
23971#define CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK (0x1000U)
23972#define CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT (12U)
23977#define CCM_OSCPLL_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK)
23978
23979#define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
23980#define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT (16U)
23985#define CCM_OSCPLL_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK)
23986
23987#define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
23988#define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT (17U)
23991#define CCM_OSCPLL_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK)
23992
23993#define CCM_OSCPLL_AUTHEN_CPULPM_MASK (0x40000U)
23994#define CCM_OSCPLL_AUTHEN_CPULPM_SHIFT (18U)
23999#define CCM_OSCPLL_AUTHEN_CPULPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_CPULPM_SHIFT)) & CCM_OSCPLL_AUTHEN_CPULPM_MASK)
24000
24001#define CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK (0x100000U)
24002#define CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT (20U)
24007#define CCM_OSCPLL_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK)
24010/* The count of CCM_OSCPLL_AUTHEN */
24011#define CCM_OSCPLL_AUTHEN_COUNT (29U)
24012
24016#define CCM_LPCG_DIRECT_ON_MASK (0x1U)
24017#define CCM_LPCG_DIRECT_ON_SHIFT (0U)
24022#define CCM_LPCG_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_ON_SHIFT)) & CCM_LPCG_DIRECT_ON_MASK)
24025/* The count of CCM_LPCG_DIRECT */
24026#define CCM_LPCG_DIRECT_COUNT (138U)
24027
24031#define CCM_LPCG_DOMAIN_LEVEL_MASK (0x7U)
24032#define CCM_LPCG_DOMAIN_LEVEL_SHIFT (0U)
24041#define CCM_LPCG_DOMAIN_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL_MASK)
24042
24043#define CCM_LPCG_DOMAIN_LEVEL0_MASK (0x70000U)
24044#define CCM_LPCG_DOMAIN_LEVEL0_SHIFT (16U)
24053#define CCM_LPCG_DOMAIN_LEVEL0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL0_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL0_MASK)
24054
24055#define CCM_LPCG_DOMAIN_LEVEL1_MASK (0x700000U)
24056#define CCM_LPCG_DOMAIN_LEVEL1_SHIFT (20U)
24065#define CCM_LPCG_DOMAIN_LEVEL1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL1_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL1_MASK)
24066
24067#define CCM_LPCG_DOMAIN_LEVEL2_MASK (0x7000000U)
24068#define CCM_LPCG_DOMAIN_LEVEL2_SHIFT (24U)
24077#define CCM_LPCG_DOMAIN_LEVEL2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL2_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL2_MASK)
24078
24079#define CCM_LPCG_DOMAIN_LEVEL3_MASK (0x70000000U)
24080#define CCM_LPCG_DOMAIN_LEVEL3_SHIFT (28U)
24089#define CCM_LPCG_DOMAIN_LEVEL3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL3_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL3_MASK)
24092/* The count of CCM_LPCG_DOMAIN */
24093#define CCM_LPCG_DOMAIN_COUNT (138U)
24094
24098#define CCM_LPCG_SETPOINT_SETPOINT_MASK (0xFFFFU)
24099#define CCM_LPCG_SETPOINT_SETPOINT_SHIFT (0U)
24102#define CCM_LPCG_SETPOINT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_SETPOINT_SHIFT)) & CCM_LPCG_SETPOINT_SETPOINT_MASK)
24103
24104#define CCM_LPCG_SETPOINT_STANDBY_MASK (0xFFFF0000U)
24105#define CCM_LPCG_SETPOINT_STANDBY_SHIFT (16U)
24108#define CCM_LPCG_SETPOINT_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_STANDBY_SHIFT)) & CCM_LPCG_SETPOINT_STANDBY_MASK)
24111/* The count of CCM_LPCG_SETPOINT */
24112#define CCM_LPCG_SETPOINT_COUNT (138U)
24113
24117#define CCM_LPCG_STATUS0_ON_MASK (0x1U)
24118#define CCM_LPCG_STATUS0_ON_SHIFT (0U)
24123#define CCM_LPCG_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ON_SHIFT)) & CCM_LPCG_STATUS0_ON_MASK)
24124
24125#define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK (0xF00U)
24126#define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT (8U)
24145#define CCM_LPCG_STATUS0_ACTIVE_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK)
24146
24147#define CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK (0xF000U)
24148#define CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT (12U)
24167#define CCM_LPCG_STATUS0_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK)
24170/* The count of CCM_LPCG_STATUS0 */
24171#define CCM_LPCG_STATUS0_COUNT (138U)
24172
24176#define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U)
24177#define CCM_LPCG_STATUS1_CPU0_MODE_SHIFT (0U)
24184#define CCM_LPCG_STATUS1_CPU0_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
24185
24186#define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U)
24187#define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U)
24192#define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK)
24193
24194#define CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK (0x8U)
24195#define CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT (3U)
24200#define CCM_LPCG_STATUS1_CPU0_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK)
24201
24202#define CCM_LPCG_STATUS1_CPU1_MODE_MASK (0x30U)
24203#define CCM_LPCG_STATUS1_CPU1_MODE_SHIFT (4U)
24210#define CCM_LPCG_STATUS1_CPU1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_MASK)
24211
24212#define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U)
24213#define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U)
24218#define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK)
24219
24220#define CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK (0x80U)
24221#define CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT (7U)
24226#define CCM_LPCG_STATUS1_CPU1_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK)
24227
24228#define CCM_LPCG_STATUS1_CPU2_MODE_MASK (0x300U)
24229#define CCM_LPCG_STATUS1_CPU2_MODE_SHIFT (8U)
24236#define CCM_LPCG_STATUS1_CPU2_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_MASK)
24237
24238#define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U)
24239#define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U)
24244#define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK)
24245
24246#define CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK (0x800U)
24247#define CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT (11U)
24252#define CCM_LPCG_STATUS1_CPU2_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK)
24253
24254#define CCM_LPCG_STATUS1_CPU3_MODE_MASK (0x3000U)
24255#define CCM_LPCG_STATUS1_CPU3_MODE_SHIFT (12U)
24262#define CCM_LPCG_STATUS1_CPU3_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_MASK)
24263
24264#define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U)
24265#define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U)
24270#define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK)
24271
24272#define CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK (0x8000U)
24273#define CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT (15U)
24278#define CCM_LPCG_STATUS1_CPU3_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK)
24279
24280#define CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
24281#define CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT (16U)
24284#define CCM_LPCG_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK)
24285
24286#define CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
24287#define CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
24290#define CCM_LPCG_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK)
24291
24292#define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U)
24293#define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U)
24298#define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK)
24299
24300#define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U)
24301#define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U)
24306#define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK)
24307
24308#define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U)
24309#define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U)
24314#define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK)
24315
24316#define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U)
24317#define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT (27U)
24322#define CCM_LPCG_STATUS1_SETPOINT_ON_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK)
24325/* The count of CCM_LPCG_STATUS1 */
24326#define CCM_LPCG_STATUS1_COUNT (138U)
24327
24331#define CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
24332#define CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
24337#define CCM_LPCG_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK)
24340/* The count of CCM_LPCG_CONFIG */
24341#define CCM_LPCG_CONFIG_COUNT (138U)
24342
24346#define CCM_LPCG_AUTHEN_TZ_USER_MASK (0x1U)
24347#define CCM_LPCG_AUTHEN_TZ_USER_SHIFT (0U)
24352#define CCM_LPCG_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK)
24353
24354#define CCM_LPCG_AUTHEN_TZ_NS_MASK (0x2U)
24355#define CCM_LPCG_AUTHEN_TZ_NS_SHIFT (1U)
24360#define CCM_LPCG_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_NS_SHIFT)) & CCM_LPCG_AUTHEN_TZ_NS_MASK)
24361
24362#define CCM_LPCG_AUTHEN_LOCK_TZ_MASK (0x10U)
24363#define CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT (4U)
24368#define CCM_LPCG_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_TZ_MASK)
24369
24370#define CCM_LPCG_AUTHEN_WHITE_LIST_MASK (0xF00U)
24371#define CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT (8U)
24374#define CCM_LPCG_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT)) & CCM_LPCG_AUTHEN_WHITE_LIST_MASK)
24375
24376#define CCM_LPCG_AUTHEN_LOCK_LIST_MASK (0x1000U)
24377#define CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT (12U)
24382#define CCM_LPCG_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_LIST_MASK)
24383
24384#define CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
24385#define CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT (16U)
24390#define CCM_LPCG_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK)
24391
24392#define CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
24393#define CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT (17U)
24398#define CCM_LPCG_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK)
24399
24400#define CCM_LPCG_AUTHEN_CPULPM_MASK (0x40000U)
24401#define CCM_LPCG_AUTHEN_CPULPM_SHIFT (18U)
24406#define CCM_LPCG_AUTHEN_CPULPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_CPULPM_SHIFT)) & CCM_LPCG_AUTHEN_CPULPM_MASK)
24407
24408#define CCM_LPCG_AUTHEN_LOCK_MODE_MASK (0x100000U)
24409#define CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT (20U)
24414#define CCM_LPCG_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_MODE_MASK)
24417/* The count of CCM_LPCG_AUTHEN */
24418#define CCM_LPCG_AUTHEN_COUNT (138U)
24419
24420 /* end of group CCM_Register_Masks */
24424
24425
24426/* CCM - Peripheral instance base addresses */
24428#define CCM_BASE (0x40CC0000u)
24430#define CCM ((CCM_Type *)CCM_BASE)
24432#define CCM_BASE_ADDRS { CCM_BASE }
24434#define CCM_BASE_PTRS { CCM }
24435 /* end of group CCM_Peripheral_Access_Layer */
24439
24440
24441/* ----------------------------------------------------------------------------
24442 -- CCM_OBS Peripheral Access Layer
24443 ---------------------------------------------------------------------------- */
24444
24451typedef struct {
24452 struct { /* offset: 0x0, array step: 0x80 */
24453 __IO uint32_t CONTROL;
24457 uint8_t RESERVED_0[16];
24458 __I uint32_t STATUS0;
24459 uint8_t RESERVED_1[12];
24460 __IO uint32_t AUTHEN;
24461 __IO uint32_t AUTHEN_SET;
24462 __IO uint32_t AUTHEN_CLR;
24463 __IO uint32_t AUTHEN_TOG;
24467 uint8_t RESERVED_2[52];
24468 } OBSERVE[6];
24469} CCM_OBS_Type;
24470
24471/* ----------------------------------------------------------------------------
24472 -- CCM_OBS Register Masks
24473 ---------------------------------------------------------------------------- */
24474
24483#define CCM_OBS_OBSERVE_CONTROL_SELECT_MASK (0x1FFU)
24484#define CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT (0U)
24487#define CCM_OBS_OBSERVE_CONTROL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SELECT_MASK)
24488
24489#define CCM_OBS_OBSERVE_CONTROL_RAW_MASK (0x1000U)
24490#define CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT (12U)
24495#define CCM_OBS_OBSERVE_CONTROL_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RAW_MASK)
24496
24497#define CCM_OBS_OBSERVE_CONTROL_INV_MASK (0x2000U)
24498#define CCM_OBS_OBSERVE_CONTROL_INV_SHIFT (13U)
24503#define CCM_OBS_OBSERVE_CONTROL_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_INV_MASK)
24504
24505#define CCM_OBS_OBSERVE_CONTROL_RESET_MASK (0x8000U)
24506#define CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT (15U)
24511#define CCM_OBS_OBSERVE_CONTROL_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RESET_MASK)
24512
24513#define CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK (0xFF0000U)
24514#define CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT (16U)
24517#define CCM_OBS_OBSERVE_CONTROL_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK)
24518
24519#define CCM_OBS_OBSERVE_CONTROL_OFF_MASK (0x1000000U)
24520#define CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT (24U)
24525#define CCM_OBS_OBSERVE_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_OFF_MASK)
24528/* The count of CCM_OBS_OBSERVE_CONTROL */
24529#define CCM_OBS_OBSERVE_CONTROL_COUNT (6U)
24530
24534#define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK (0x1FFU)
24535#define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT (0U)
24538#define CCM_OBS_OBSERVE_CONTROL_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK)
24539
24540#define CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK (0x1000U)
24541#define CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT (12U)
24544#define CCM_OBS_OBSERVE_CONTROL_SET_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK)
24545
24546#define CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK (0x2000U)
24547#define CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT (13U)
24550#define CCM_OBS_OBSERVE_CONTROL_SET_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK)
24551
24552#define CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK (0x8000U)
24553#define CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT (15U)
24556#define CCM_OBS_OBSERVE_CONTROL_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK)
24557
24558#define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK (0xFF0000U)
24559#define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT (16U)
24562#define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK)
24563
24564#define CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK (0x1000000U)
24565#define CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT (24U)
24568#define CCM_OBS_OBSERVE_CONTROL_SET_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK)
24571/* The count of CCM_OBS_OBSERVE_CONTROL_SET */
24572#define CCM_OBS_OBSERVE_CONTROL_SET_COUNT (6U)
24573
24577#define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK (0x1FFU)
24578#define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT (0U)
24581#define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK)
24582
24583#define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK (0x1000U)
24584#define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT (12U)
24587#define CCM_OBS_OBSERVE_CONTROL_CLR_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK)
24588
24589#define CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK (0x2000U)
24590#define CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT (13U)
24593#define CCM_OBS_OBSERVE_CONTROL_CLR_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK)
24594
24595#define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK (0x8000U)
24596#define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT (15U)
24599#define CCM_OBS_OBSERVE_CONTROL_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK)
24600
24601#define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK (0xFF0000U)
24602#define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT (16U)
24605#define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK)
24606
24607#define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK (0x1000000U)
24608#define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT (24U)
24611#define CCM_OBS_OBSERVE_CONTROL_CLR_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK)
24614/* The count of CCM_OBS_OBSERVE_CONTROL_CLR */
24615#define CCM_OBS_OBSERVE_CONTROL_CLR_COUNT (6U)
24616
24620#define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK (0x1FFU)
24621#define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT (0U)
24624#define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK)
24625
24626#define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK (0x1000U)
24627#define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT (12U)
24630#define CCM_OBS_OBSERVE_CONTROL_TOG_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK)
24631
24632#define CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK (0x2000U)
24633#define CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT (13U)
24636#define CCM_OBS_OBSERVE_CONTROL_TOG_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK)
24637
24638#define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK (0x8000U)
24639#define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT (15U)
24642#define CCM_OBS_OBSERVE_CONTROL_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK)
24643
24644#define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK (0xFF0000U)
24645#define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT (16U)
24648#define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK)
24649
24650#define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK (0x1000000U)
24651#define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT (24U)
24654#define CCM_OBS_OBSERVE_CONTROL_TOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK)
24657/* The count of CCM_OBS_OBSERVE_CONTROL_TOG */
24658#define CCM_OBS_OBSERVE_CONTROL_TOG_COUNT (6U)
24659
24663#define CCM_OBS_OBSERVE_STATUS0_SELECT_MASK (0x1FFU)
24664#define CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT (0U)
24667#define CCM_OBS_OBSERVE_STATUS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_SELECT_MASK)
24668
24669#define CCM_OBS_OBSERVE_STATUS0_RAW_MASK (0x1000U)
24670#define CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT (12U)
24675#define CCM_OBS_OBSERVE_STATUS0_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RAW_MASK)
24676
24677#define CCM_OBS_OBSERVE_STATUS0_INV_MASK (0x2000U)
24678#define CCM_OBS_OBSERVE_STATUS0_INV_SHIFT (13U)
24683#define CCM_OBS_OBSERVE_STATUS0_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_INV_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_INV_MASK)
24684
24685#define CCM_OBS_OBSERVE_STATUS0_RESET_MASK (0x8000U)
24686#define CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT (15U)
24691#define CCM_OBS_OBSERVE_STATUS0_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RESET_MASK)
24692
24693#define CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK (0xFF0000U)
24694#define CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT (16U)
24697#define CCM_OBS_OBSERVE_STATUS0_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK)
24698
24699#define CCM_OBS_OBSERVE_STATUS0_OFF_MASK (0x1000000U)
24700#define CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT (24U)
24705#define CCM_OBS_OBSERVE_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_OFF_MASK)
24708/* The count of CCM_OBS_OBSERVE_STATUS0 */
24709#define CCM_OBS_OBSERVE_STATUS0_COUNT (6U)
24710
24714#define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK (0x1U)
24715#define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT (0U)
24720#define CCM_OBS_OBSERVE_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK)
24721
24722#define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK (0x2U)
24723#define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT (1U)
24728#define CCM_OBS_OBSERVE_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK)
24729
24730#define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK (0x10U)
24731#define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT (4U)
24736#define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK)
24737
24738#define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK (0xF00U)
24739#define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT (8U)
24748#define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK)
24749
24750#define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK (0x1000U)
24751#define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT (12U)
24756#define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK)
24757
24758#define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
24759#define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT (16U)
24764#define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK)
24765
24766#define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK (0x100000U)
24767#define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT (20U)
24772#define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK)
24775/* The count of CCM_OBS_OBSERVE_AUTHEN */
24776#define CCM_OBS_OBSERVE_AUTHEN_COUNT (6U)
24777
24781#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK (0x1U)
24782#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT (0U)
24785#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK)
24786
24787#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK (0x2U)
24788#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT (1U)
24791#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK)
24792
24793#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
24794#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
24797#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK)
24798
24799#define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
24800#define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
24803#define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK)
24804
24805#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
24806#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
24809#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK)
24810
24811#define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
24812#define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
24815#define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK)
24816
24817#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
24818#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
24821#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK)
24824/* The count of CCM_OBS_OBSERVE_AUTHEN_SET */
24825#define CCM_OBS_OBSERVE_AUTHEN_SET_COUNT (6U)
24826
24830#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK (0x1U)
24831#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT (0U)
24834#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK)
24835
24836#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK (0x2U)
24837#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT (1U)
24840#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK)
24841
24842#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
24843#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
24846#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK)
24847
24848#define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
24849#define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
24852#define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK)
24853
24854#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
24855#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
24858#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK)
24859
24860#define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
24861#define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
24864#define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK)
24865
24866#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
24867#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
24870#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK)
24873/* The count of CCM_OBS_OBSERVE_AUTHEN_CLR */
24874#define CCM_OBS_OBSERVE_AUTHEN_CLR_COUNT (6U)
24875
24879#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK (0x1U)
24880#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT (0U)
24883#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK)
24884
24885#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK (0x2U)
24886#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT (1U)
24889#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK)
24890
24891#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
24892#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
24895#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK)
24896
24897#define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
24898#define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
24901#define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK)
24902
24903#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
24904#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
24907#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK)
24908
24909#define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
24910#define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
24913#define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK)
24914
24915#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
24916#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
24919#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK)
24922/* The count of CCM_OBS_OBSERVE_AUTHEN_TOG */
24923#define CCM_OBS_OBSERVE_AUTHEN_TOG_COUNT (6U)
24924
24928#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK (0xFFFFFFFFU)
24929#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT (0U)
24932#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK)
24935/* The count of CCM_OBS_OBSERVE_FREQUENCY_CURRENT */
24936#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_COUNT (6U)
24937
24941#define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK (0xFFFFFFFFU)
24942#define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT (0U)
24945#define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK)
24948/* The count of CCM_OBS_OBSERVE_FREQUENCY_MIN */
24949#define CCM_OBS_OBSERVE_FREQUENCY_MIN_COUNT (6U)
24950
24954#define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK (0xFFFFFFFFU)
24955#define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT (0U)
24958#define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK)
24961/* The count of CCM_OBS_OBSERVE_FREQUENCY_MAX */
24962#define CCM_OBS_OBSERVE_FREQUENCY_MAX_COUNT (6U)
24963
24964 /* end of group CCM_OBS_Register_Masks */
24968
24969
24970/* CCM_OBS - Peripheral instance base addresses */
24972#define CCM_OBS_BASE (0x40150000u)
24974#define CCM_OBS ((CCM_OBS_Type *)CCM_OBS_BASE)
24976#define CCM_OBS_BASE_ADDRS { CCM_OBS_BASE }
24978#define CCM_OBS_BASE_PTRS { CCM_OBS }
24979 /* end of group CCM_OBS_Peripheral_Access_Layer */
24983
24984
24985/* ----------------------------------------------------------------------------
24986 -- CDOG Peripheral Access Layer
24987 ---------------------------------------------------------------------------- */
24988
24995typedef struct {
24996 __IO uint32_t CONTROL;
24997 __IO uint32_t RELOAD;
24998 __IO uint32_t INSTRUCTION_TIMER;
24999 __O uint32_t SECURE_COUNTER;
25000 __I uint32_t STATUS;
25001 __I uint32_t STATUS2;
25002 __IO uint32_t FLAGS;
25003 __IO uint32_t PERSISTENT;
25004 __O uint32_t START;
25005 __O uint32_t STOP;
25006 __O uint32_t RESTART;
25007 __O uint32_t ADD;
25008 __O uint32_t ADD1;
25009 __O uint32_t ADD16;
25010 __O uint32_t ADD256;
25011 __O uint32_t SUB;
25012 __O uint32_t SUB1;
25013 __O uint32_t SUB16;
25014 __O uint32_t SUB256;
25015} CDOG_Type;
25016
25017/* ----------------------------------------------------------------------------
25018 -- CDOG Register Masks
25019 ---------------------------------------------------------------------------- */
25020
25029#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U)
25030#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U)
25035#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK)
25036
25037#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU)
25038#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U)
25044#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK)
25045
25046#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U)
25047#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U)
25053#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK)
25054
25055#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U)
25056#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U)
25062#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK)
25063
25064#define CDOG_CONTROL_CONTROL_CTRL_MASK (0x3800U)
25065#define CDOG_CONTROL_CONTROL_CTRL_SHIFT (11U)
25070#define CDOG_CONTROL_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK)
25071
25072#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U)
25073#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U)
25079#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK)
25080
25081#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U)
25082#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U)
25088#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK)
25089
25090#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U)
25091#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U)
25096#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK)
25097
25098#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U)
25099#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U)
25104#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK)
25110#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU)
25111#define CDOG_RELOAD_RLOAD_SHIFT (0U)
25114#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK)
25120#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU)
25121#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U)
25124#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK)
25130#define CDOG_SECURE_COUNTER_SECCNT_MASK (0xFFFFFFFFU)
25131#define CDOG_SECURE_COUNTER_SECCNT_SHIFT (0U)
25134#define CDOG_SECURE_COUNTER_SECCNT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK)
25140#define CDOG_STATUS_NUMTOF_MASK (0xFFU)
25141#define CDOG_STATUS_NUMTOF_SHIFT (0U)
25144#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK)
25145
25146#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U)
25147#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U)
25150#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK)
25151
25152#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U)
25153#define CDOG_STATUS_NUMILSEQF_SHIFT (16U)
25156#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK)
25157
25158#define CDOG_STATUS_CURST_MASK (0xF0000000U)
25159#define CDOG_STATUS_CURST_SHIFT (28U)
25162#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK)
25168#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU)
25169#define CDOG_STATUS2_NUMCNTF_SHIFT (0U)
25172#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK)
25173
25174#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U)
25175#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U)
25178#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK)
25179
25180#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U)
25181#define CDOG_STATUS2_NUMILLA_SHIFT (16U)
25184#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK)
25190#define CDOG_FLAGS_TO_FLAG_MASK (0x1U)
25191#define CDOG_FLAGS_TO_FLAG_SHIFT (0U)
25196#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK)
25197
25198#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U)
25199#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U)
25204#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK)
25205
25206#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U)
25207#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U)
25212#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK)
25213
25214#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U)
25215#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U)
25220#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK)
25221
25222#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U)
25223#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U)
25228#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK)
25229
25230#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U)
25231#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U)
25236#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK)
25237
25238#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U)
25239#define CDOG_FLAGS_POR_FLAG_SHIFT (16U)
25244#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK)
25250#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU)
25251#define CDOG_PERSISTENT_PERSIS_SHIFT (0U)
25254#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK)
25260#define CDOG_START_STRT_MASK (0xFFFFFFFFU)
25261#define CDOG_START_STRT_SHIFT (0U)
25264#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK)
25270#define CDOG_STOP_STP_MASK (0xFFFFFFFFU)
25271#define CDOG_STOP_STP_SHIFT (0U)
25274#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK)
25280#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU)
25281#define CDOG_RESTART_RSTRT_SHIFT (0U)
25284#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK)
25290#define CDOG_ADD_AD_MASK (0xFFFFFFFFU)
25291#define CDOG_ADD_AD_SHIFT (0U)
25294#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK)
25300#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU)
25301#define CDOG_ADD1_AD1_SHIFT (0U)
25304#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK)
25310#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU)
25311#define CDOG_ADD16_AD16_SHIFT (0U)
25314#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK)
25320#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU)
25321#define CDOG_ADD256_AD256_SHIFT (0U)
25324#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK)
25330#define CDOG_SUB_S0B_MASK (0xFFFFFFFFU)
25331#define CDOG_SUB_S0B_SHIFT (0U)
25334#define CDOG_SUB_S0B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
25340#define CDOG_SUB1_S1B_MASK (0xFFFFFFFFU)
25341#define CDOG_SUB1_S1B_SHIFT (0U)
25344#define CDOG_SUB1_S1B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK)
25350#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU)
25351#define CDOG_SUB16_SB16_SHIFT (0U)
25354#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK)
25360#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU)
25361#define CDOG_SUB256_SB256_SHIFT (0U)
25364#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) /* end of group CDOG_Register_Masks */
25371
25372
25373/* CDOG - Peripheral instance base addresses */
25375#define CDOG_BASE (0x41900000u)
25377#define CDOG ((CDOG_Type *)CDOG_BASE)
25379#define CDOG_BASE_ADDRS { CDOG_BASE }
25381#define CDOG_BASE_PTRS { CDOG }
25382 /* end of group CDOG_Peripheral_Access_Layer */
25386
25387
25388/* ----------------------------------------------------------------------------
25389 -- CMP Peripheral Access Layer
25390 ---------------------------------------------------------------------------- */
25391
25398typedef struct {
25399 __I uint32_t VERID;
25400 __I uint32_t PARAM;
25401 __IO uint32_t C0;
25402 __IO uint32_t C1;
25403 __IO uint32_t C2;
25404 __IO uint32_t C3;
25405} CMP_Type;
25406
25407/* ----------------------------------------------------------------------------
25408 -- CMP Register Masks
25409 ---------------------------------------------------------------------------- */
25410
25419#define CMP_VERID_FEATURE_MASK (0xFFFFU)
25420#define CMP_VERID_FEATURE_SHIFT (0U)
25423#define CMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)
25424
25425#define CMP_VERID_MINOR_MASK (0xFF0000U)
25426#define CMP_VERID_MINOR_SHIFT (16U)
25429#define CMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)
25430
25431#define CMP_VERID_MAJOR_MASK (0xFF000000U)
25432#define CMP_VERID_MAJOR_SHIFT (24U)
25435#define CMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)
25441#define CMP_PARAM_PARAM_MASK (0xFFFFFFFFU)
25442#define CMP_PARAM_PARAM_SHIFT (0U)
25445#define CMP_PARAM_PARAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)
25451#define CMP_C0_HYSTCTR_MASK (0x3U)
25452#define CMP_C0_HYSTCTR_SHIFT (0U)
25459#define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)
25460
25461#define CMP_C0_FILTER_CNT_MASK (0x70U)
25462#define CMP_C0_FILTER_CNT_SHIFT (4U)
25473#define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)
25474
25475#define CMP_C0_EN_MASK (0x100U)
25476#define CMP_C0_EN_SHIFT (8U)
25481#define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)
25482
25483#define CMP_C0_OPE_MASK (0x200U)
25484#define CMP_C0_OPE_SHIFT (9U)
25489#define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)
25490
25491#define CMP_C0_COS_MASK (0x400U)
25492#define CMP_C0_COS_SHIFT (10U)
25497#define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)
25498
25499#define CMP_C0_INVT_MASK (0x800U)
25500#define CMP_C0_INVT_SHIFT (11U)
25505#define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)
25506
25507#define CMP_C0_PMODE_MASK (0x1000U)
25508#define CMP_C0_PMODE_SHIFT (12U)
25513#define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)
25514
25515#define CMP_C0_WE_MASK (0x4000U)
25516#define CMP_C0_WE_SHIFT (14U)
25521#define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)
25522
25523#define CMP_C0_SE_MASK (0x8000U)
25524#define CMP_C0_SE_SHIFT (15U)
25529#define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)
25530
25531#define CMP_C0_FPR_MASK (0xFF0000U)
25532#define CMP_C0_FPR_SHIFT (16U)
25535#define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)
25536
25537#define CMP_C0_COUT_MASK (0x1000000U)
25538#define CMP_C0_COUT_SHIFT (24U)
25541#define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)
25542
25543#define CMP_C0_CFF_MASK (0x2000000U)
25544#define CMP_C0_CFF_SHIFT (25U)
25549#define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)
25550
25551#define CMP_C0_CFR_MASK (0x4000000U)
25552#define CMP_C0_CFR_SHIFT (26U)
25557#define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
25558
25559#define CMP_C0_IEF_MASK (0x8000000U)
25560#define CMP_C0_IEF_SHIFT (27U)
25565#define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)
25566
25567#define CMP_C0_IER_MASK (0x10000000U)
25568#define CMP_C0_IER_SHIFT (28U)
25573#define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)
25574
25575#define CMP_C0_DMAEN_MASK (0x40000000U)
25576#define CMP_C0_DMAEN_SHIFT (30U)
25581#define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)
25582
25583#define CMP_C0_LINKEN_MASK (0x80000000U)
25584#define CMP_C0_LINKEN_SHIFT (31U)
25589#define CMP_C0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)
25595#define CMP_C1_VOSEL_MASK (0xFFU)
25596#define CMP_C1_VOSEL_SHIFT (0U)
25599#define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)
25600
25601#define CMP_C1_DMODE_MASK (0x100U)
25602#define CMP_C1_DMODE_SHIFT (8U)
25607#define CMP_C1_DMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)
25608
25609#define CMP_C1_VRSEL_MASK (0x200U)
25610#define CMP_C1_VRSEL_SHIFT (9U)
25615#define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)
25616
25617#define CMP_C1_DACEN_MASK (0x400U)
25618#define CMP_C1_DACEN_SHIFT (10U)
25623#define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)
25624
25625#define CMP_C1_CHN0_MASK (0x10000U)
25626#define CMP_C1_CHN0_SHIFT (16U)
25629#define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)
25630
25631#define CMP_C1_CHN1_MASK (0x20000U)
25632#define CMP_C1_CHN1_SHIFT (17U)
25635#define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)
25636
25637#define CMP_C1_CHN2_MASK (0x40000U)
25638#define CMP_C1_CHN2_SHIFT (18U)
25641#define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)
25642
25643#define CMP_C1_CHN3_MASK (0x80000U)
25644#define CMP_C1_CHN3_SHIFT (19U)
25647#define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)
25648
25649#define CMP_C1_CHN4_MASK (0x100000U)
25650#define CMP_C1_CHN4_SHIFT (20U)
25653#define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)
25654
25655#define CMP_C1_CHN5_MASK (0x200000U)
25656#define CMP_C1_CHN5_SHIFT (21U)
25659#define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)
25660
25661#define CMP_C1_MSEL_MASK (0x7000000U)
25662#define CMP_C1_MSEL_SHIFT (24U)
25673#define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)
25674
25675#define CMP_C1_PSEL_MASK (0x70000000U)
25676#define CMP_C1_PSEL_SHIFT (28U)
25687#define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)
25693#define CMP_C2_ACOn_MASK (0x3FU)
25694#define CMP_C2_ACOn_SHIFT (0U)
25697#define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)
25698
25699#define CMP_C2_INITMOD_MASK (0x3F00U)
25700#define CMP_C2_INITMOD_SHIFT (8U)
25703#define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)
25704
25705#define CMP_C2_NSAM_MASK (0xC000U)
25706#define CMP_C2_NSAM_SHIFT (14U)
25713#define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)
25714
25715#define CMP_C2_CH0F_MASK (0x10000U)
25716#define CMP_C2_CH0F_SHIFT (16U)
25719#define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)
25720
25721#define CMP_C2_CH1F_MASK (0x20000U)
25722#define CMP_C2_CH1F_SHIFT (17U)
25725#define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)
25726
25727#define CMP_C2_CH2F_MASK (0x40000U)
25728#define CMP_C2_CH2F_SHIFT (18U)
25731#define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)
25732
25733#define CMP_C2_CH3F_MASK (0x80000U)
25734#define CMP_C2_CH3F_SHIFT (19U)
25737#define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)
25738
25739#define CMP_C2_CH4F_MASK (0x100000U)
25740#define CMP_C2_CH4F_SHIFT (20U)
25743#define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)
25744
25745#define CMP_C2_CH5F_MASK (0x200000U)
25746#define CMP_C2_CH5F_SHIFT (21U)
25749#define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)
25750
25751#define CMP_C2_FXMXCH_MASK (0xE000000U)
25752#define CMP_C2_FXMXCH_SHIFT (25U)
25763#define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)
25764
25765#define CMP_C2_FXMP_MASK (0x20000000U)
25766#define CMP_C2_FXMP_SHIFT (29U)
25771#define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)
25772
25773#define CMP_C2_RRIE_MASK (0x40000000U)
25774#define CMP_C2_RRIE_SHIFT (30U)
25779#define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)
25785#define CMP_C3_ACPH2TC_MASK (0x70U)
25786#define CMP_C3_ACPH2TC_SHIFT (4U)
25797#define CMP_C3_ACPH2TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)
25798
25799#define CMP_C3_ACPH1TC_MASK (0x700U)
25800#define CMP_C3_ACPH1TC_SHIFT (8U)
25811#define CMP_C3_ACPH1TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)
25812
25813#define CMP_C3_ACSAT_MASK (0x7000U)
25814#define CMP_C3_ACSAT_SHIFT (12U)
25825#define CMP_C3_ACSAT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)
25826
25827#define CMP_C3_DMCS_MASK (0x10000U)
25828#define CMP_C3_DMCS_SHIFT (16U)
25833#define CMP_C3_DMCS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)
25834
25835#define CMP_C3_RDIVE_MASK (0x100000U)
25836#define CMP_C3_RDIVE_SHIFT (20U)
25841#define CMP_C3_RDIVE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)
25842
25843#define CMP_C3_NCHCTEN_MASK (0x1000000U)
25844#define CMP_C3_NCHCTEN_SHIFT (24U)
25849#define CMP_C3_NCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)
25850
25851#define CMP_C3_PCHCTEN_MASK (0x10000000U)
25852#define CMP_C3_PCHCTEN_SHIFT (28U)
25857#define CMP_C3_PCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK) /* end of group CMP_Register_Masks */
25864
25865
25866/* CMP - Peripheral instance base addresses */
25868#define CMP1_BASE (0x401A4000u)
25870#define CMP1 ((CMP_Type *)CMP1_BASE)
25872#define CMP2_BASE (0x401A8000u)
25874#define CMP2 ((CMP_Type *)CMP2_BASE)
25876#define CMP3_BASE (0x401AC000u)
25878#define CMP3 ((CMP_Type *)CMP3_BASE)
25880#define CMP4_BASE (0x401B0000u)
25882#define CMP4 ((CMP_Type *)CMP4_BASE)
25884#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
25886#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
25888#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
25889 /* end of group CMP_Peripheral_Access_Layer */
25893
25894
25895/* ----------------------------------------------------------------------------
25896 -- CSI Peripheral Access Layer
25897 ---------------------------------------------------------------------------- */
25898
25905typedef struct {
25906 __IO uint32_t CR1;
25907 __IO uint32_t CR2;
25908 __IO uint32_t CR3;
25909 __I uint32_t STATFIFO;
25910 __I uint32_t RFIFO;
25911 __IO uint32_t RXCNT;
25912 __IO uint32_t SR;
25913 uint8_t RESERVED_0[4];
25914 __IO uint32_t DMASA_STATFIFO;
25915 __IO uint32_t DMATS_STATFIFO;
25916 __IO uint32_t DMASA_FB1;
25917 __IO uint32_t DMASA_FB2;
25918 __IO uint32_t FBUF_PARA;
25919 __IO uint32_t IMAG_PARA;
25920 uint8_t RESERVED_1[16];
25921 __IO uint32_t CR18;
25922 __IO uint32_t CR19;
25923 __IO uint32_t CR20;
25924 __IO uint32_t CR[256];
25925} CSI_Type;
25926
25927/* ----------------------------------------------------------------------------
25928 -- CSI Register Masks
25929 ---------------------------------------------------------------------------- */
25930
25939#define CSI_CR1_PIXEL_BIT_MASK (0x1U)
25940#define CSI_CR1_PIXEL_BIT_SHIFT (0U)
25945#define CSI_CR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PIXEL_BIT_SHIFT)) & CSI_CR1_PIXEL_BIT_MASK)
25946
25947#define CSI_CR1_REDGE_MASK (0x2U)
25948#define CSI_CR1_REDGE_SHIFT (1U)
25953#define CSI_CR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_REDGE_SHIFT)) & CSI_CR1_REDGE_MASK)
25954
25955#define CSI_CR1_INV_PCLK_MASK (0x4U)
25956#define CSI_CR1_INV_PCLK_SHIFT (2U)
25961#define CSI_CR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_PCLK_SHIFT)) & CSI_CR1_INV_PCLK_MASK)
25962
25963#define CSI_CR1_INV_DATA_MASK (0x8U)
25964#define CSI_CR1_INV_DATA_SHIFT (3U)
25969#define CSI_CR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_DATA_SHIFT)) & CSI_CR1_INV_DATA_MASK)
25970
25971#define CSI_CR1_GCLK_MODE_MASK (0x10U)
25972#define CSI_CR1_GCLK_MODE_SHIFT (4U)
25977#define CSI_CR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_GCLK_MODE_SHIFT)) & CSI_CR1_GCLK_MODE_MASK)
25978
25979#define CSI_CR1_CLR_RXFIFO_MASK (0x20U)
25980#define CSI_CR1_CLR_RXFIFO_SHIFT (5U)
25981#define CSI_CR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_RXFIFO_SHIFT)) & CSI_CR1_CLR_RXFIFO_MASK)
25982
25983#define CSI_CR1_CLR_STATFIFO_MASK (0x40U)
25984#define CSI_CR1_CLR_STATFIFO_SHIFT (6U)
25985#define CSI_CR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_STATFIFO_SHIFT)) & CSI_CR1_CLR_STATFIFO_MASK)
25986
25987#define CSI_CR1_PACK_DIR_MASK (0x80U)
25988#define CSI_CR1_PACK_DIR_SHIFT (7U)
25995#define CSI_CR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PACK_DIR_SHIFT)) & CSI_CR1_PACK_DIR_MASK)
25996
25997#define CSI_CR1_FCC_MASK (0x100U)
25998#define CSI_CR1_FCC_SHIFT (8U)
26003#define CSI_CR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FCC_SHIFT)) & CSI_CR1_FCC_MASK)
26004
26005#define CSI_CR1_CCIR_EN_MASK (0x400U)
26006#define CSI_CR1_CCIR_EN_SHIFT (10U)
26011#define CSI_CR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CCIR_EN_SHIFT)) & CSI_CR1_CCIR_EN_MASK)
26012
26013#define CSI_CR1_HSYNC_POL_MASK (0x800U)
26014#define CSI_CR1_HSYNC_POL_SHIFT (11U)
26019#define CSI_CR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HSYNC_POL_SHIFT)) & CSI_CR1_HSYNC_POL_MASK)
26020
26021#define CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK (0x1000U)
26022#define CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT (12U)
26027#define CSI_CR1_HISTOGRAM_CALC_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT)) & CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK)
26028
26029#define CSI_CR1_SOF_INTEN_MASK (0x10000U)
26030#define CSI_CR1_SOF_INTEN_SHIFT (16U)
26035#define CSI_CR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_INTEN_SHIFT)) & CSI_CR1_SOF_INTEN_MASK)
26036
26037#define CSI_CR1_SOF_POL_MASK (0x20000U)
26038#define CSI_CR1_SOF_POL_SHIFT (17U)
26043#define CSI_CR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_POL_SHIFT)) & CSI_CR1_SOF_POL_MASK)
26044
26045#define CSI_CR1_RXFF_INTEN_MASK (0x40000U)
26046#define CSI_CR1_RXFF_INTEN_SHIFT (18U)
26051#define CSI_CR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RXFF_INTEN_SHIFT)) & CSI_CR1_RXFF_INTEN_MASK)
26052
26053#define CSI_CR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)
26054#define CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT (19U)
26059#define CSI_CR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB1_DMA_DONE_INTEN_MASK)
26060
26061#define CSI_CR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)
26062#define CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT (20U)
26067#define CSI_CR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB2_DMA_DONE_INTEN_MASK)
26068
26069#define CSI_CR1_STATFF_INTEN_MASK (0x200000U)
26070#define CSI_CR1_STATFF_INTEN_SHIFT (21U)
26075#define CSI_CR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_STATFF_INTEN_SHIFT)) & CSI_CR1_STATFF_INTEN_MASK)
26076
26077#define CSI_CR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)
26078#define CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT (22U)
26083#define CSI_CR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_SFF_DMA_DONE_INTEN_MASK)
26084
26085#define CSI_CR1_RF_OR_INTEN_MASK (0x1000000U)
26086#define CSI_CR1_RF_OR_INTEN_SHIFT (24U)
26091#define CSI_CR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RF_OR_INTEN_SHIFT)) & CSI_CR1_RF_OR_INTEN_MASK)
26092
26093#define CSI_CR1_SF_OR_INTEN_MASK (0x2000000U)
26094#define CSI_CR1_SF_OR_INTEN_SHIFT (25U)
26099#define CSI_CR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SF_OR_INTEN_SHIFT)) & CSI_CR1_SF_OR_INTEN_MASK)
26100
26101#define CSI_CR1_COF_INT_EN_MASK (0x4000000U)
26102#define CSI_CR1_COF_INT_EN_SHIFT (26U)
26107#define CSI_CR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_COF_INT_EN_SHIFT)) & CSI_CR1_COF_INT_EN_MASK)
26108
26109#define CSI_CR1_VIDEO_MODE_MASK (0x8000000U)
26110#define CSI_CR1_VIDEO_MODE_SHIFT (27U)
26115#define CSI_CR1_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_VIDEO_MODE_SHIFT)) & CSI_CR1_VIDEO_MODE_MASK)
26116
26117#define CSI_CR1_EOF_INT_EN_MASK (0x20000000U)
26118#define CSI_CR1_EOF_INT_EN_SHIFT (29U)
26123#define CSI_CR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EOF_INT_EN_SHIFT)) & CSI_CR1_EOF_INT_EN_MASK)
26124
26125#define CSI_CR1_EXT_VSYNC_MASK (0x40000000U)
26126#define CSI_CR1_EXT_VSYNC_SHIFT (30U)
26131#define CSI_CR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EXT_VSYNC_SHIFT)) & CSI_CR1_EXT_VSYNC_MASK)
26132
26133#define CSI_CR1_SWAP16_EN_MASK (0x80000000U)
26134#define CSI_CR1_SWAP16_EN_SHIFT (31U)
26139#define CSI_CR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SWAP16_EN_SHIFT)) & CSI_CR1_SWAP16_EN_MASK)
26145#define CSI_CR2_HSC_MASK (0xFFU)
26146#define CSI_CR2_HSC_SHIFT (0U)
26150#define CSI_CR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_HSC_SHIFT)) & CSI_CR2_HSC_MASK)
26151
26152#define CSI_CR2_VSC_MASK (0xFF00U)
26153#define CSI_CR2_VSC_SHIFT (8U)
26157#define CSI_CR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_VSC_SHIFT)) & CSI_CR2_VSC_MASK)
26158
26159#define CSI_CR2_LVRM_MASK (0x70000U)
26160#define CSI_CR2_LVRM_SHIFT (16U)
26170#define CSI_CR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_LVRM_SHIFT)) & CSI_CR2_LVRM_MASK)
26171
26172#define CSI_CR2_BTS_MASK (0x180000U)
26173#define CSI_CR2_BTS_SHIFT (19U)
26180#define CSI_CR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_BTS_SHIFT)) & CSI_CR2_BTS_MASK)
26181
26182#define CSI_CR2_SCE_MASK (0x800000U)
26183#define CSI_CR2_SCE_SHIFT (23U)
26188#define CSI_CR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_SCE_SHIFT)) & CSI_CR2_SCE_MASK)
26189
26190#define CSI_CR2_AFS_MASK (0x3000000U)
26191#define CSI_CR2_AFS_SHIFT (24U)
26197#define CSI_CR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_AFS_SHIFT)) & CSI_CR2_AFS_MASK)
26198
26199#define CSI_CR2_DRM_MASK (0x4000000U)
26200#define CSI_CR2_DRM_SHIFT (26U)
26205#define CSI_CR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DRM_SHIFT)) & CSI_CR2_DRM_MASK)
26206
26207#define CSI_CR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)
26208#define CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT (28U)
26214#define CSI_CR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_SFF_MASK)
26215
26216#define CSI_CR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)
26217#define CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT (30U)
26223#define CSI_CR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_RFF_MASK)
26229#define CSI_CR3_ECC_AUTO_EN_MASK (0x1U)
26230#define CSI_CR3_ECC_AUTO_EN_SHIFT (0U)
26235#define CSI_CR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_AUTO_EN_SHIFT)) & CSI_CR3_ECC_AUTO_EN_MASK)
26236
26237#define CSI_CR3_ECC_INT_EN_MASK (0x2U)
26238#define CSI_CR3_ECC_INT_EN_SHIFT (1U)
26243#define CSI_CR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_INT_EN_SHIFT)) & CSI_CR3_ECC_INT_EN_MASK)
26244
26245#define CSI_CR3_ZERO_PACK_EN_MASK (0x4U)
26246#define CSI_CR3_ZERO_PACK_EN_SHIFT (2U)
26251#define CSI_CR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ZERO_PACK_EN_SHIFT)) & CSI_CR3_ZERO_PACK_EN_MASK)
26252
26253#define CSI_CR3_SENSOR_16BITS_MASK (0x8U)
26254#define CSI_CR3_SENSOR_16BITS_SHIFT (3U)
26259#define CSI_CR3_SENSOR_16BITS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_SENSOR_16BITS_SHIFT)) & CSI_CR3_SENSOR_16BITS_MASK)
26260
26261#define CSI_CR3_RxFF_LEVEL_MASK (0x70U)
26262#define CSI_CR3_RxFF_LEVEL_SHIFT (4U)
26273#define CSI_CR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_RxFF_LEVEL_SHIFT)) & CSI_CR3_RxFF_LEVEL_MASK)
26274
26275#define CSI_CR3_HRESP_ERR_EN_MASK (0x80U)
26276#define CSI_CR3_HRESP_ERR_EN_SHIFT (7U)
26281#define CSI_CR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_HRESP_ERR_EN_SHIFT)) & CSI_CR3_HRESP_ERR_EN_MASK)
26282
26283#define CSI_CR3_STATFF_LEVEL_MASK (0x700U)
26284#define CSI_CR3_STATFF_LEVEL_SHIFT (8U)
26295#define CSI_CR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_STATFF_LEVEL_SHIFT)) & CSI_CR3_STATFF_LEVEL_MASK)
26296
26297#define CSI_CR3_DMA_REQ_EN_SFF_MASK (0x800U)
26298#define CSI_CR3_DMA_REQ_EN_SFF_SHIFT (11U)
26303#define CSI_CR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_SFF_MASK)
26304
26305#define CSI_CR3_DMA_REQ_EN_RFF_MASK (0x1000U)
26306#define CSI_CR3_DMA_REQ_EN_RFF_SHIFT (12U)
26311#define CSI_CR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_RFF_MASK)
26312
26313#define CSI_CR3_DMA_REFLASH_SFF_MASK (0x2000U)
26314#define CSI_CR3_DMA_REFLASH_SFF_SHIFT (13U)
26319#define CSI_CR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CR3_DMA_REFLASH_SFF_MASK)
26320
26321#define CSI_CR3_DMA_REFLASH_RFF_MASK (0x4000U)
26322#define CSI_CR3_DMA_REFLASH_RFF_SHIFT (14U)
26327#define CSI_CR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CR3_DMA_REFLASH_RFF_MASK)
26328
26329#define CSI_CR3_FRMCNT_RST_MASK (0x8000U)
26330#define CSI_CR3_FRMCNT_RST_SHIFT (15U)
26335#define CSI_CR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_RST_SHIFT)) & CSI_CR3_FRMCNT_RST_MASK)
26336
26337#define CSI_CR3_FRMCNT_MASK (0xFFFF0000U)
26338#define CSI_CR3_FRMCNT_SHIFT (16U)
26339#define CSI_CR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_SHIFT)) & CSI_CR3_FRMCNT_MASK)
26345#define CSI_STATFIFO_STAT_MASK (0xFFFFFFFFU)
26346#define CSI_STATFIFO_STAT_SHIFT (0U)
26347#define CSI_STATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_STATFIFO_STAT_SHIFT)) & CSI_STATFIFO_STAT_MASK)
26353#define CSI_RFIFO_IMAGE_MASK (0xFFFFFFFFU)
26354#define CSI_RFIFO_IMAGE_SHIFT (0U)
26355#define CSI_RFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_RFIFO_IMAGE_SHIFT)) & CSI_RFIFO_IMAGE_MASK)
26361#define CSI_RXCNT_RXCNT_MASK (0x3FFFFFU)
26362#define CSI_RXCNT_RXCNT_SHIFT (0U)
26363#define CSI_RXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_RXCNT_RXCNT_SHIFT)) & CSI_RXCNT_RXCNT_MASK)
26369#define CSI_SR_DRDY_MASK (0x1U)
26370#define CSI_SR_DRDY_SHIFT (0U)
26375#define CSI_SR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DRDY_SHIFT)) & CSI_SR_DRDY_MASK)
26376
26377#define CSI_SR_ECC_INT_MASK (0x2U)
26378#define CSI_SR_ECC_INT_SHIFT (1U)
26383#define CSI_SR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_ECC_INT_SHIFT)) & CSI_SR_ECC_INT_MASK)
26384
26385#define CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK (0x4U)
26386#define CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT (2U)
26391#define CSI_SR_HISTOGRAM_CALC_DONE_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT)) & CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK)
26392
26393#define CSI_SR_HRESP_ERR_INT_MASK (0x80U)
26394#define CSI_SR_HRESP_ERR_INT_SHIFT (7U)
26399#define CSI_SR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_HRESP_ERR_INT_SHIFT)) & CSI_SR_HRESP_ERR_INT_MASK)
26400
26401#define CSI_SR_COF_INT_MASK (0x2000U)
26402#define CSI_SR_COF_INT_SHIFT (13U)
26407#define CSI_SR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_COF_INT_SHIFT)) & CSI_SR_COF_INT_MASK)
26408
26409#define CSI_SR_F1_INT_MASK (0x4000U)
26410#define CSI_SR_F1_INT_SHIFT (14U)
26415#define CSI_SR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_F1_INT_SHIFT)) & CSI_SR_F1_INT_MASK)
26416
26417#define CSI_SR_F2_INT_MASK (0x8000U)
26418#define CSI_SR_F2_INT_SHIFT (15U)
26423#define CSI_SR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_F2_INT_SHIFT)) & CSI_SR_F2_INT_MASK)
26424
26425#define CSI_SR_SOF_INT_MASK (0x10000U)
26426#define CSI_SR_SOF_INT_SHIFT (16U)
26431#define CSI_SR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_SOF_INT_SHIFT)) & CSI_SR_SOF_INT_MASK)
26432
26433#define CSI_SR_EOF_INT_MASK (0x20000U)
26434#define CSI_SR_EOF_INT_SHIFT (17U)
26439#define CSI_SR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_EOF_INT_SHIFT)) & CSI_SR_EOF_INT_MASK)
26440
26441#define CSI_SR_RxFF_INT_MASK (0x40000U)
26442#define CSI_SR_RxFF_INT_SHIFT (18U)
26447#define CSI_SR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_RxFF_INT_SHIFT)) & CSI_SR_RxFF_INT_MASK)
26448
26449#define CSI_SR_DMA_TSF_DONE_FB1_MASK (0x80000U)
26450#define CSI_SR_DMA_TSF_DONE_FB1_SHIFT (19U)
26455#define CSI_SR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB1_MASK)
26456
26457#define CSI_SR_DMA_TSF_DONE_FB2_MASK (0x100000U)
26458#define CSI_SR_DMA_TSF_DONE_FB2_SHIFT (20U)
26463#define CSI_SR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB2_MASK)
26464
26465#define CSI_SR_STATFF_INT_MASK (0x200000U)
26466#define CSI_SR_STATFF_INT_SHIFT (21U)
26471#define CSI_SR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_STATFF_INT_SHIFT)) & CSI_SR_STATFF_INT_MASK)
26472
26473#define CSI_SR_DMA_TSF_DONE_SFF_MASK (0x400000U)
26474#define CSI_SR_DMA_TSF_DONE_SFF_SHIFT (22U)
26479#define CSI_SR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_SR_DMA_TSF_DONE_SFF_MASK)
26480
26481#define CSI_SR_RF_OR_INT_MASK (0x1000000U)
26482#define CSI_SR_RF_OR_INT_SHIFT (24U)
26487#define CSI_SR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_RF_OR_INT_SHIFT)) & CSI_SR_RF_OR_INT_MASK)
26488
26489#define CSI_SR_SF_OR_INT_MASK (0x2000000U)
26490#define CSI_SR_SF_OR_INT_SHIFT (25U)
26495#define CSI_SR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_SF_OR_INT_SHIFT)) & CSI_SR_SF_OR_INT_MASK)
26496
26497#define CSI_SR_DMA_FIELD1_DONE_MASK (0x4000000U)
26498#define CSI_SR_DMA_FIELD1_DONE_SHIFT (26U)
26499#define CSI_SR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD1_DONE_SHIFT)) & CSI_SR_DMA_FIELD1_DONE_MASK)
26500
26501#define CSI_SR_DMA_FIELD0_DONE_MASK (0x8000000U)
26502#define CSI_SR_DMA_FIELD0_DONE_SHIFT (27U)
26503#define CSI_SR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD0_DONE_SHIFT)) & CSI_SR_DMA_FIELD0_DONE_MASK)
26504
26505#define CSI_SR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)
26506#define CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)
26507#define CSI_SR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_SR_BASEADDR_CHHANGE_ERROR_MASK)
26513#define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
26514#define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
26515#define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
26521#define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
26522#define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
26523#define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
26529#define CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
26530#define CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
26531#define CSI_DMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK)
26537#define CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
26538#define CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
26539#define CSI_DMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK)
26545#define CSI_FBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)
26546#define CSI_FBUF_PARA_FBUF_STRIDE_SHIFT (0U)
26547#define CSI_FBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_FBUF_PARA_FBUF_STRIDE_MASK)
26548
26549#define CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
26550#define CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
26551#define CSI_FBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK)
26557#define CSI_IMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)
26558#define CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)
26559#define CSI_IMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_IMAG_PARA_IMAGE_HEIGHT_MASK)
26560
26561#define CSI_IMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)
26562#define CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT (16U)
26563#define CSI_IMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_IMAG_PARA_IMAGE_WIDTH_MASK)
26569#define CSI_CR18_NTSC_EN_MASK (0x1U)
26570#define CSI_CR18_NTSC_EN_SHIFT (0U)
26575#define CSI_CR18_NTSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_NTSC_EN_SHIFT)) & CSI_CR18_NTSC_EN_MASK)
26576
26577#define CSI_CR18_TVDECODER_IN_EN_MASK (0x2U)
26578#define CSI_CR18_TVDECODER_IN_EN_SHIFT (1U)
26579#define CSI_CR18_TVDECODER_IN_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_TVDECODER_IN_EN_SHIFT)) & CSI_CR18_TVDECODER_IN_EN_MASK)
26580
26581#define CSI_CR18_DEINTERLACE_EN_MASK (0x4U)
26582#define CSI_CR18_DEINTERLACE_EN_SHIFT (2U)
26587#define CSI_CR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DEINTERLACE_EN_SHIFT)) & CSI_CR18_DEINTERLACE_EN_MASK)
26588
26589#define CSI_CR18_PARALLEL24_EN_MASK (0x8U)
26590#define CSI_CR18_PARALLEL24_EN_SHIFT (3U)
26595#define CSI_CR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_PARALLEL24_EN_SHIFT)) & CSI_CR18_PARALLEL24_EN_MASK)
26596
26597#define CSI_CR18_BASEADDR_SWITCH_EN_MASK (0x10U)
26598#define CSI_CR18_BASEADDR_SWITCH_EN_SHIFT (4U)
26599#define CSI_CR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_EN_MASK)
26600
26601#define CSI_CR18_BASEADDR_SWITCH_SEL_MASK (0x20U)
26602#define CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT (5U)
26607#define CSI_CR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_SEL_MASK)
26608
26609#define CSI_CR18_FIELD0_DONE_IE_MASK (0x40U)
26610#define CSI_CR18_FIELD0_DONE_IE_SHIFT (6U)
26615#define CSI_CR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_FIELD0_DONE_IE_SHIFT)) & CSI_CR18_FIELD0_DONE_IE_MASK)
26616
26617#define CSI_CR18_DMA_FIELD1_DONE_IE_MASK (0x80U)
26618#define CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT (7U)
26623#define CSI_CR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CR18_DMA_FIELD1_DONE_IE_MASK)
26624
26625#define CSI_CR18_LAST_DMA_REQ_SEL_MASK (0x100U)
26626#define CSI_CR18_LAST_DMA_REQ_SEL_SHIFT (8U)
26631#define CSI_CR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CR18_LAST_DMA_REQ_SEL_MASK)
26632
26633#define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
26634#define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
26639#define CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK)
26640
26641#define CSI_CR18_RGB888A_FORMAT_SEL_MASK (0x400U)
26642#define CSI_CR18_RGB888A_FORMAT_SEL_SHIFT (10U)
26647#define CSI_CR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CR18_RGB888A_FORMAT_SEL_MASK)
26648
26649#define CSI_CR18_AHB_HPROT_MASK (0xF000U)
26650#define CSI_CR18_AHB_HPROT_SHIFT (12U)
26651#define CSI_CR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_AHB_HPROT_SHIFT)) & CSI_CR18_AHB_HPROT_MASK)
26652
26653#define CSI_CR18_MASK_OPTION_MASK (0xC0000U)
26654#define CSI_CR18_MASK_OPTION_SHIFT (18U)
26661#define CSI_CR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MASK_OPTION_SHIFT)) & CSI_CR18_MASK_OPTION_MASK)
26662
26663#define CSI_CR18_MIPI_DOUBLE_CMPNT_MASK (0x100000U)
26664#define CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT (20U)
26669#define CSI_CR18_MIPI_DOUBLE_CMPNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT)) & CSI_CR18_MIPI_DOUBLE_CMPNT_MASK)
26670
26671#define CSI_CR18_MIPI_YU_SWAP_MASK (0x200000U)
26672#define CSI_CR18_MIPI_YU_SWAP_SHIFT (21U)
26675#define CSI_CR18_MIPI_YU_SWAP(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_YU_SWAP_SHIFT)) & CSI_CR18_MIPI_YU_SWAP_MASK)
26676
26677#define CSI_CR18_DATA_FROM_MIPI_MASK (0x400000U)
26678#define CSI_CR18_DATA_FROM_MIPI_SHIFT (22U)
26683#define CSI_CR18_DATA_FROM_MIPI(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DATA_FROM_MIPI_SHIFT)) & CSI_CR18_DATA_FROM_MIPI_MASK)
26684
26685#define CSI_CR18_LINE_STRIDE_EN_MASK (0x1000000U)
26686#define CSI_CR18_LINE_STRIDE_EN_SHIFT (24U)
26687#define CSI_CR18_LINE_STRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LINE_STRIDE_EN_SHIFT)) & CSI_CR18_LINE_STRIDE_EN_MASK)
26688
26689#define CSI_CR18_MIPI_DATA_FORMAT_MASK (0x7E000000U)
26690#define CSI_CR18_MIPI_DATA_FORMAT_SHIFT (25U)
26693#define CSI_CR18_MIPI_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DATA_FORMAT_SHIFT)) & CSI_CR18_MIPI_DATA_FORMAT_MASK)
26694
26695#define CSI_CR18_CSI_ENABLE_MASK (0x80000000U)
26696#define CSI_CR18_CSI_ENABLE_SHIFT (31U)
26697#define CSI_CR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_CSI_ENABLE_SHIFT)) & CSI_CR18_CSI_ENABLE_MASK)
26703#define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
26704#define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
26705#define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
26711#define CSI_CR20_THRESHOLD_MASK (0xFFU)
26712#define CSI_CR20_THRESHOLD_SHIFT (0U)
26713#define CSI_CR20_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_THRESHOLD_SHIFT)) & CSI_CR20_THRESHOLD_MASK)
26714
26715#define CSI_CR20_BINARY_EN_MASK (0x100U)
26716#define CSI_CR20_BINARY_EN_SHIFT (8U)
26721#define CSI_CR20_BINARY_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BINARY_EN_SHIFT)) & CSI_CR20_BINARY_EN_MASK)
26722
26723#define CSI_CR20_QR_DATA_FORMAT_MASK (0xE00U)
26724#define CSI_CR20_QR_DATA_FORMAT_SHIFT (9U)
26733#define CSI_CR20_QR_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QR_DATA_FORMAT_SHIFT)) & CSI_CR20_QR_DATA_FORMAT_MASK)
26734
26735#define CSI_CR20_BIG_END_MASK (0x1000U)
26736#define CSI_CR20_BIG_END_SHIFT (12U)
26741#define CSI_CR20_BIG_END(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BIG_END_SHIFT)) & CSI_CR20_BIG_END_MASK)
26742
26743#define CSI_CR20_10BIT_NEW_EN_MASK (0x20000000U)
26744#define CSI_CR20_10BIT_NEW_EN_SHIFT (29U)
26749#define CSI_CR20_10BIT_NEW_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_10BIT_NEW_EN_SHIFT)) & CSI_CR20_10BIT_NEW_EN_MASK)
26750
26751#define CSI_CR20_HISTOGRAM_EN_MASK (0x40000000U)
26752#define CSI_CR20_HISTOGRAM_EN_SHIFT (30U)
26757#define CSI_CR20_HISTOGRAM_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_HISTOGRAM_EN_SHIFT)) & CSI_CR20_HISTOGRAM_EN_MASK)
26758
26759#define CSI_CR20_QRCODE_EN_MASK (0x80000000U)
26760#define CSI_CR20_QRCODE_EN_SHIFT (31U)
26765#define CSI_CR20_QRCODE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QRCODE_EN_SHIFT)) & CSI_CR20_QRCODE_EN_MASK)
26771#define CSI_CR_PIXEL_COUNTERS_MASK (0xFFFFFFU)
26772#define CSI_CR_PIXEL_COUNTERS_SHIFT (0U)
26773#define CSI_CR_PIXEL_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR_PIXEL_COUNTERS_SHIFT)) & CSI_CR_PIXEL_COUNTERS_MASK)
26776/* The count of CSI_CR */
26777#define CSI_CR_COUNT (256U)
26778
26779 /* end of group CSI_Register_Masks */
26783
26784
26785/* CSI - Peripheral instance base addresses */
26787#define CSI_BASE (0x40800000u)
26789#define CSI ((CSI_Type *)CSI_BASE)
26791#define CSI_BASE_ADDRS { CSI_BASE }
26793#define CSI_BASE_PTRS { CSI }
26795#define CSI_IRQS { CSI_IRQn }
26796/* Backward compatibility */
26797#define CSI_CSICR1_PIXEL_BIT_MASK CSI_CR1_PIXEL_BIT_MASK
26798#define CSI_CSICR1_PIXEL_BIT_SHIFT CSI_CR1_PIXEL_BIT_SHIFT
26799#define CSI_CSICR1_PIXEL_BIT(x) CSI_CR1_PIXEL_BIT(x)
26800#define CSI_CSICR1_REDGE_MASK CSI_CR1_REDGE_MASK
26801#define CSI_CSICR1_REDGE_SHIFT CSI_CR1_REDGE_SHIFT
26802#define CSI_CSICR1_REDGE(x) CSI_CR1_REDGE(x)
26803#define CSI_CSICR1_INV_PCLK_MASK CSI_CR1_INV_PCLK_MASK
26804#define CSI_CSICR1_INV_PCLK_SHIFT CSI_CR1_INV_PCLK_SHIFT
26805#define CSI_CSICR1_INV_PCLK(x) CSI_CR1_INV_PCLK(x)
26806#define CSI_CSICR1_INV_DATA_MASK CSI_CR1_INV_DATA_MASK
26807#define CSI_CSICR1_INV_DATA_SHIFT CSI_CR1_INV_DATA_SHIFT
26808#define CSI_CSICR1_INV_DATA(x) CSI_CR1_INV_DATA(x)
26809#define CSI_CSICR1_GCLK_MODE_MASK CSI_CR1_GCLK_MODE_MASK
26810#define CSI_CSICR1_GCLK_MODE_SHIFT CSI_CR1_GCLK_MODE_SHIFT
26811#define CSI_CSICR1_GCLK_MODE(x) CSI_CR1_GCLK_MODE(x)
26812#define CSI_CSICR1_CLR_RXFIFO_MASK CSI_CR1_CLR_RXFIFO_MASK
26813#define CSI_CSICR1_CLR_RXFIFO_SHIFT CSI_CR1_CLR_RXFIFO_SHIFT
26814#define CSI_CSICR1_CLR_RXFIFO(x) CSI_CR1_CLR_RXFIFO(x)
26815#define CSI_CSICR1_CLR_STATFIFO_MASK CSI_CR1_CLR_STATFIFO_MASK
26816#define CSI_CSICR1_CLR_STATFIFO_SHIFT CSI_CR1_CLR_STATFIFO_SHIFT
26817#define CSI_CSICR1_CLR_STATFIFO(x) CSI_CR1_CLR_STATFIFO(x)
26818#define CSI_CSICR1_PACK_DIR_MASK CSI_CR1_PACK_DIR_MASK
26819#define CSI_CSICR1_PACK_DIR_SHIFT CSI_CR1_PACK_DIR_SHIFT
26820#define CSI_CSICR1_PACK_DIR(x) CSI_CR1_PACK_DIR(x)
26821#define CSI_CSICR1_FCC_MASK CSI_CR1_FCC_MASK
26822#define CSI_CSICR1_FCC_SHIFT CSI_CR1_FCC_SHIFT
26823#define CSI_CSICR1_FCC(x) CSI_CR1_FCC(x)
26824#define CSI_CSICR1_CCIR_EN_MASK CSI_CR1_CCIR_EN_MASK
26825#define CSI_CSICR1_CCIR_EN_SHIFT CSI_CR1_CCIR_EN_SHIFT
26826#define CSI_CSICR1_CCIR_EN(x) CSI_CR1_CCIR_EN(x)
26827#define CSI_CSICR1_HSYNC_POL_MASK CSI_CR1_HSYNC_POL_MASK
26828#define CSI_CSICR1_HSYNC_POL_SHIFT CSI_CR1_HSYNC_POL_SHIFT
26829#define CSI_CSICR1_HSYNC_POL(x) CSI_CR1_HSYNC_POL(x)
26830#define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_MASK CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK
26831#define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_SHIFT CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT
26832#define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE(x) CSI_CR1_HISTOGRAM_CALC_DONE_IE(x)
26833#define CSI_CSICR1_SOF_INTEN_MASK CSI_CR1_SOF_INTEN_MASK
26834#define CSI_CSICR1_SOF_INTEN_SHIFT CSI_CR1_SOF_INTEN_SHIFT
26835#define CSI_CSICR1_SOF_INTEN(x) CSI_CR1_SOF_INTEN(x)
26836#define CSI_CSICR1_SOF_POL_MASK CSI_CR1_SOF_POL_MASK
26837#define CSI_CSICR1_SOF_POL_SHIFT CSI_CR1_SOF_POL_SHIFT
26838#define CSI_CSICR1_SOF_POL(x) CSI_CR1_SOF_POL(x)
26839#define CSI_CSICR1_RXFF_INTEN_MASK CSI_CR1_RXFF_INTEN_MASK
26840#define CSI_CSICR1_RXFF_INTEN_SHIFT CSI_CR1_RXFF_INTEN_SHIFT
26841#define CSI_CSICR1_RXFF_INTEN(x) CSI_CR1_RXFF_INTEN(x)
26842#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK CSI_CR1_FB1_DMA_DONE_INTEN_MASK
26843#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT
26844#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) CSI_CR1_FB1_DMA_DONE_INTEN(x)
26845#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK CSI_CR1_FB2_DMA_DONE_INTEN_MASK
26846#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT
26847#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) CSI_CR1_FB2_DMA_DONE_INTEN(x)
26848#define CSI_CSICR1_STATFF_INTEN_MASK CSI_CR1_STATFF_INTEN_MASK
26849#define CSI_CSICR1_STATFF_INTEN_SHIFT CSI_CR1_STATFF_INTEN_SHIFT
26850#define CSI_CSICR1_STATFF_INTEN(x) CSI_CR1_STATFF_INTEN(x)
26851#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK CSI_CR1_SFF_DMA_DONE_INTEN_MASK
26852#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT
26853#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) CSI_CR1_SFF_DMA_DONE_INTEN(x)
26854#define CSI_CSICR1_RF_OR_INTEN_MASK CSI_CR1_RF_OR_INTEN_MASK
26855#define CSI_CSICR1_RF_OR_INTEN_SHIFT CSI_CR1_RF_OR_INTEN_SHIFT
26856#define CSI_CSICR1_RF_OR_INTEN(x) CSI_CR1_RF_OR_INTEN(x)
26857#define CSI_CSICR1_SF_OR_INTEN_MASK CSI_CR1_SF_OR_INTEN_MASK
26858#define CSI_CSICR1_SF_OR_INTEN_SHIFT CSI_CR1_SF_OR_INTEN_SHIFT
26859#define CSI_CSICR1_SF_OR_INTEN(x) CSI_CR1_SF_OR_INTEN(x)
26860#define CSI_CSICR1_COF_INT_EN_MASK CSI_CR1_COF_INT_EN_MASK
26861#define CSI_CSICR1_COF_INT_EN_SHIFT CSI_CR1_COF_INT_EN_SHIFT
26862#define CSI_CSICR1_COF_INT_EN(x) CSI_CR1_COF_INT_EN(x)
26863#define CSI_CSICR1_VIDEO_MODE_MASK CSI_CR1_VIDEO_MODE_MASK
26864#define CSI_CSICR1_VIDEO_MODE_SHIFT CSI_CR1_VIDEO_MODE_SHIFT
26865#define CSI_CSICR1_VIDEO_MODE(x) CSI_CR1_VIDEO_MODE(x)
26866#define CSI_CSICR1_EOF_INT_EN_MASK CSI_CR1_EOF_INT_EN_MASK
26867#define CSI_CSICR1_EOF_INT_EN_SHIFT CSI_CR1_EOF_INT_EN_SHIFT
26868#define CSI_CSICR1_EOF_INT_EN(x) CSI_CR1_EOF_INT_EN(x)
26869#define CSI_CSICR1_EXT_VSYNC_MASK CSI_CR1_EXT_VSYNC_MASK
26870#define CSI_CSICR1_EXT_VSYNC_SHIFT CSI_CR1_EXT_VSYNC_SHIFT
26871#define CSI_CSICR1_EXT_VSYNC(x) CSI_CR1_EXT_VSYNC(x)
26872#define CSI_CSICR1_SWAP16_EN_MASK CSI_CR1_SWAP16_EN_MASK
26873#define CSI_CSICR1_SWAP16_EN_SHIFT CSI_CR1_SWAP16_EN_SHIFT
26874#define CSI_CSICR1_SWAP16_EN(x) CSI_CR1_SWAP16_EN(x)
26875#define CSI_CSICR2_HSC_MASK CSI_CR2_HSC_MASK
26876#define CSI_CSICR2_HSC_SHIFT CSI_CR2_HSC_SHIFT
26877#define CSI_CSICR2_HSC(x) CSI_CR2_HSC(x)
26878#define CSI_CSICR2_VSC_MASK CSI_CR2_VSC_MASK
26879#define CSI_CSICR2_VSC_SHIFT CSI_CR2_VSC_SHIFT
26880#define CSI_CSICR2_VSC(x) CSI_CR2_VSC(x)
26881#define CSI_CSICR2_LVRM_MASK CSI_CR2_LVRM_MASK
26882#define CSI_CSICR2_LVRM_SHIFT CSI_CR2_LVRM_SHIFT
26883#define CSI_CSICR2_LVRM(x) CSI_CR2_LVRM(x)
26884#define CSI_CSICR2_BTS_MASK CSI_CR2_BTS_MASK
26885#define CSI_CSICR2_BTS_SHIFT CSI_CR2_BTS_SHIFT
26886#define CSI_CSICR2_BTS(x) CSI_CR2_BTS(x)
26887#define CSI_CSICR2_SCE_MASK CSI_CR2_SCE_MASK
26888#define CSI_CSICR2_SCE_SHIFT CSI_CR2_SCE_SHIFT
26889#define CSI_CSICR2_SCE(x) CSI_CR2_SCE(x)
26890#define CSI_CSICR2_AFS_MASK CSI_CR2_AFS_MASK
26891#define CSI_CSICR2_AFS_SHIFT CSI_CR2_AFS_SHIFT
26892#define CSI_CSICR2_AFS(x) CSI_CR2_AFS(x)
26893#define CSI_CSICR2_DRM_MASK CSI_CR2_DRM_MASK
26894#define CSI_CSICR2_DRM_SHIFT CSI_CR2_DRM_SHIFT
26895#define CSI_CSICR2_DRM(x) CSI_CR2_DRM(x)
26896#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK CSI_CR2_DMA_BURST_TYPE_SFF_MASK
26897#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT
26898#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) CSI_CR2_DMA_BURST_TYPE_SFF(x)
26899#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK CSI_CR2_DMA_BURST_TYPE_RFF_MASK
26900#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT
26901#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) CSI_CR2_DMA_BURST_TYPE_RFF(x)
26902#define CSI_CSICR3_ECC_AUTO_EN_MASK CSI_CR3_ECC_AUTO_EN_MASK
26903#define CSI_CSICR3_ECC_AUTO_EN_SHIFT CSI_CR3_ECC_AUTO_EN_SHIFT
26904#define CSI_CSICR3_ECC_AUTO_EN(x) CSI_CR3_ECC_AUTO_EN(x)
26905#define CSI_CSICR3_ECC_INT_EN_MASK CSI_CR3_ECC_INT_EN_MASK
26906#define CSI_CSICR3_ECC_INT_EN_SHIFT CSI_CR3_ECC_INT_EN_SHIFT
26907#define CSI_CSICR3_ECC_INT_EN(x) CSI_CR3_ECC_INT_EN(x)
26908#define CSI_CSICR3_ZERO_PACK_EN_MASK CSI_CR3_ZERO_PACK_EN_MASK
26909#define CSI_CSICR3_ZERO_PACK_EN_SHIFT CSI_CR3_ZERO_PACK_EN_SHIFT
26910#define CSI_CSICR3_ZERO_PACK_EN(x) CSI_CR3_ZERO_PACK_EN(x)
26911#define CSI_CSICR3_SENSOR_16BITS_MASK CSI_CR3_SENSOR_16BITS_MASK
26912#define CSI_CSICR3_SENSOR_16BITS_SHIFT CSI_CR3_SENSOR_16BITS_SHIFT
26913#define CSI_CSICR3_SENSOR_16BITS(x) CSI_CR3_SENSOR_16BITS(x)
26914#define CSI_CSICR3_RxFF_LEVEL_MASK CSI_CR3_RxFF_LEVEL_MASK
26915#define CSI_CSICR3_RxFF_LEVEL_SHIFT CSI_CR3_RxFF_LEVEL_SHIFT
26916#define CSI_CSICR3_RxFF_LEVEL(x) CSI_CR3_RxFF_LEVEL(x)
26917#define CSI_CSICR3_HRESP_ERR_EN_MASK CSI_CR3_HRESP_ERR_EN_MASK
26918#define CSI_CSICR3_HRESP_ERR_EN_SHIFT CSI_CR3_HRESP_ERR_EN_SHIFT
26919#define CSI_CSICR3_HRESP_ERR_EN(x) CSI_CR3_HRESP_ERR_EN(x)
26920#define CSI_CSICR3_STATFF_LEVEL_MASK CSI_CR3_STATFF_LEVEL_MASK
26921#define CSI_CSICR3_STATFF_LEVEL_SHIFT CSI_CR3_STATFF_LEVEL_SHIFT
26922#define CSI_CSICR3_STATFF_LEVEL(x) CSI_CR3_STATFF_LEVEL(x)
26923#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK CSI_CR3_DMA_REQ_EN_SFF_MASK
26924#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT CSI_CR3_DMA_REQ_EN_SFF_SHIFT
26925#define CSI_CSICR3_DMA_REQ_EN_SFF(x) CSI_CR3_DMA_REQ_EN_SFF(x)
26926#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK CSI_CR3_DMA_REQ_EN_RFF_MASK
26927#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT CSI_CR3_DMA_REQ_EN_RFF_SHIFT
26928#define CSI_CSICR3_DMA_REQ_EN_RFF(x) CSI_CR3_DMA_REQ_EN_RFF(x)
26929#define CSI_CSICR3_DMA_REFLASH_SFF_MASK CSI_CR3_DMA_REFLASH_SFF_MASK
26930#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT CSI_CR3_DMA_REFLASH_SFF_SHIFT
26931#define CSI_CSICR3_DMA_REFLASH_SFF(x) CSI_CR3_DMA_REFLASH_SFF(x)
26932#define CSI_CSICR3_DMA_REFLASH_RFF_MASK CSI_CR3_DMA_REFLASH_RFF_MASK
26933#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT CSI_CR3_DMA_REFLASH_RFF_SHIFT
26934#define CSI_CSICR3_DMA_REFLASH_RFF(x) CSI_CR3_DMA_REFLASH_RFF(x)
26935#define CSI_CSICR3_FRMCNT_RST_MASK CSI_CR3_FRMCNT_RST_MASK
26936#define CSI_CSICR3_FRMCNT_RST_SHIFT CSI_CR3_FRMCNT_RST_SHIFT
26937#define CSI_CSICR3_FRMCNT_RST(x) CSI_CR3_FRMCNT_RST(x)
26938#define CSI_CSICR3_FRMCNT_MASK CSI_CR3_FRMCNT_MASK
26939#define CSI_CSICR3_FRMCNT_SHIFT CSI_CR3_FRMCNT_SHIFT
26940#define CSI_CSICR3_FRMCNT(x) CSI_CR3_FRMCNT(x)
26941#define CSI_CSISTATFIFO_STAT_MASK CSI_STATFIFO_STAT_MASK
26942#define CSI_CSISTATFIFO_STAT_SHIFT CSI_STATFIFO_STAT_SHIFT
26943#define CSI_CSISTATFIFO_STAT(x) CSI_STATFIFO_STAT(x)
26944#define CSI_CSIRFIFO_IMAGE_MASK CSI_RFIFO_IMAGE_MASK
26945#define CSI_CSIRFIFO_IMAGE_SHIFT CSI_RFIFO_IMAGE_SHIFT
26946#define CSI_CSIRFIFO_IMAGE(x) CSI_RFIFO_IMAGE(x)
26947#define CSI_CSIRXCNT_RXCNT_MASK CSI_RXCNT_RXCNT_MASK
26948#define CSI_CSIRXCNT_RXCNT_SHIFT CSI_RXCNT_RXCNT_SHIFT
26949#define CSI_CSIRXCNT_RXCNT(x) CSI_RXCNT_RXCNT(x)
26950#define CSI_CSISR_DRDY_MASK CSI_SR_DRDY_MASK
26951#define CSI_CSISR_DRDY_SHIFT CSI_SR_DRDY_SHIFT
26952#define CSI_CSISR_DRDY(x) CSI_SR_DRDY(x)
26953#define CSI_CSISR_ECC_INT_MASK CSI_SR_ECC_INT_MASK
26954#define CSI_CSISR_ECC_INT_SHIFT CSI_SR_ECC_INT_SHIFT
26955#define CSI_CSISR_ECC_INT(x) CSI_SR_ECC_INT(x)
26956#define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_MASK CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK
26957#define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_SHIFT CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT
26958#define CSI_CSISR_HISTOGRAM_CALC_DONE_INT(x) CSI_SR_HISTOGRAM_CALC_DONE_INT(x)
26959#define CSI_CSISR_HRESP_ERR_INT_MASK CSI_SR_HRESP_ERR_INT_MASK
26960#define CSI_CSISR_HRESP_ERR_INT_SHIFT CSI_SR_HRESP_ERR_INT_SHIFT
26961#define CSI_CSISR_HRESP_ERR_INT(x) CSI_SR_HRESP_ERR_INT(x)
26962#define CSI_CSISR_COF_INT_MASK CSI_SR_COF_INT_MASK
26963#define CSI_CSISR_COF_INT_SHIFT CSI_SR_COF_INT_SHIFT
26964#define CSI_CSISR_COF_INT(x) CSI_SR_COF_INT(x)
26965#define CSI_CSISR_F1_INT_MASK CSI_SR_F1_INT_MASK
26966#define CSI_CSISR_F1_INT_SHIFT CSI_SR_F1_INT_SHIFT
26967#define CSI_CSISR_F1_INT(x) CSI_SR_F1_INT(x)
26968#define CSI_CSISR_F2_INT_MASK CSI_SR_F2_INT_MASK
26969#define CSI_CSISR_F2_INT_SHIFT CSI_SR_F2_INT_SHIFT
26970#define CSI_CSISR_F2_INT(x) CSI_SR_F2_INT(x)
26971#define CSI_CSISR_SOF_INT_MASK CSI_SR_SOF_INT_MASK
26972#define CSI_CSISR_SOF_INT_SHIFT CSI_SR_SOF_INT_SHIFT
26973#define CSI_CSISR_SOF_INT(x) CSI_SR_SOF_INT(x)
26974#define CSI_CSISR_EOF_INT_MASK CSI_SR_EOF_INT_MASK
26975#define CSI_CSISR_EOF_INT_SHIFT CSI_SR_EOF_INT_SHIFT
26976#define CSI_CSISR_EOF_INT(x) CSI_SR_EOF_INT(x)
26977#define CSI_CSISR_RxFF_INT_MASK CSI_SR_RxFF_INT_MASK
26978#define CSI_CSISR_RxFF_INT_SHIFT CSI_SR_RxFF_INT_SHIFT
26979#define CSI_CSISR_RxFF_INT(x) CSI_SR_RxFF_INT(x)
26980#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK CSI_SR_DMA_TSF_DONE_FB1_MASK
26981#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT CSI_SR_DMA_TSF_DONE_FB1_SHIFT
26982#define CSI_CSISR_DMA_TSF_DONE_FB1(x) CSI_SR_DMA_TSF_DONE_FB1(x)
26983#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK CSI_SR_DMA_TSF_DONE_FB2_MASK
26984#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT CSI_SR_DMA_TSF_DONE_FB2_SHIFT
26985#define CSI_CSISR_DMA_TSF_DONE_FB2(x) CSI_SR_DMA_TSF_DONE_FB2(x)
26986#define CSI_CSISR_STATFF_INT_MASK CSI_SR_STATFF_INT_MASK
26987#define CSI_CSISR_STATFF_INT_SHIFT CSI_SR_STATFF_INT_SHIFT
26988#define CSI_CSISR_STATFF_INT(x) CSI_SR_STATFF_INT(x)
26989#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK CSI_SR_DMA_TSF_DONE_SFF_MASK
26990#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT CSI_SR_DMA_TSF_DONE_SFF_SHIFT
26991#define CSI_CSISR_DMA_TSF_DONE_SFF(x) CSI_SR_DMA_TSF_DONE_SFF(x)
26992#define CSI_CSISR_RF_OR_INT_MASK CSI_SR_RF_OR_INT_MASK
26993#define CSI_CSISR_RF_OR_INT_SHIFT CSI_SR_RF_OR_INT_SHIFT
26994#define CSI_CSISR_RF_OR_INT(x) CSI_SR_RF_OR_INT(x)
26995#define CSI_CSISR_SF_OR_INT_MASK CSI_SR_SF_OR_INT_MASK
26996#define CSI_CSISR_SF_OR_INT_SHIFT CSI_SR_SF_OR_INT_SHIFT
26997#define CSI_CSISR_SF_OR_INT(x) CSI_SR_SF_OR_INT(x)
26998#define CSI_CSISR_DMA_FIELD1_DONE_MASK CSI_SR_DMA_FIELD1_DONE_MASK
26999#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT CSI_SR_DMA_FIELD1_DONE_SHIFT
27000#define CSI_CSISR_DMA_FIELD1_DONE(x) CSI_SR_DMA_FIELD1_DONE(x)
27001#define CSI_CSISR_DMA_FIELD0_DONE_MASK CSI_SR_DMA_FIELD0_DONE_MASK
27002#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT CSI_SR_DMA_FIELD0_DONE_SHIFT
27003#define CSI_CSISR_DMA_FIELD0_DONE(x) CSI_SR_DMA_FIELD0_DONE(x)
27004#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK CSI_SR_BASEADDR_CHHANGE_ERROR_MASK
27005#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT
27006#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) CSI_SR_BASEADDR_CHHANGE_ERROR(x)
27007#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK
27008#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT
27009#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x)
27010#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK
27011#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT
27012#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)
27013#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK
27014#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT
27015#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) CSI_DMASA_FB1_DMA_START_ADDR_FB1(x)
27016#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK
27017#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT
27018#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) CSI_DMASA_FB2_DMA_START_ADDR_FB2(x)
27019#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK CSI_FBUF_PARA_FBUF_STRIDE_MASK
27020#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT CSI_FBUF_PARA_FBUF_STRIDE_SHIFT
27021#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) CSI_FBUF_PARA_FBUF_STRIDE(x)
27022#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK
27023#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT
27024#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) CSI_FBUF_PARA_DEINTERLACE_STRIDE(x)
27025#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK CSI_IMAG_PARA_IMAGE_HEIGHT_MASK
27026#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT
27027#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) CSI_IMAG_PARA_IMAGE_HEIGHT(x)
27028#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK CSI_IMAG_PARA_IMAGE_WIDTH_MASK
27029#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT
27030#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) CSI_IMAG_PARA_IMAGE_WIDTH(x)
27031#define CSI_CSICR18_NTSC_EN_MASK CSI_CR18_NTSC_EN_MASK
27032#define CSI_CSICR18_NTSC_EN_SHIFT CSI_CR18_NTSC_EN_SHIFT
27033#define CSI_CSICR18_NTSC_EN(x) CSI_CR18_NTSC_EN(x)
27034#define CSI_CSICR18_TVDECODER_IN_EN_MASK CSI_CR18_TVDECODER_IN_EN_MASK
27035#define CSI_CSICR18_TVDECODER_IN_EN_SHIFT CSI_CR18_TVDECODER_IN_EN_SHIFT
27036#define CSI_CSICR18_TVDECODER_IN_EN(x) CSI_CR18_TVDECODER_IN_EN(x)
27037#define CSI_CSICR18_DEINTERLACE_EN_MASK CSI_CR18_DEINTERLACE_EN_MASK
27038#define CSI_CSICR18_DEINTERLACE_EN_SHIFT CSI_CR18_DEINTERLACE_EN_SHIFT
27039#define CSI_CSICR18_DEINTERLACE_EN(x) CSI_CR18_DEINTERLACE_EN(x)
27040#define CSI_CSICR18_PARALLEL24_EN_MASK CSI_CR18_PARALLEL24_EN_MASK
27041#define CSI_CSICR18_PARALLEL24_EN_SHIFT CSI_CR18_PARALLEL24_EN_SHIFT
27042#define CSI_CSICR18_PARALLEL24_EN(x) CSI_CR18_PARALLEL24_EN(x)
27043#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK CSI_CR18_BASEADDR_SWITCH_EN_MASK
27044#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT CSI_CR18_BASEADDR_SWITCH_EN_SHIFT
27045#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) CSI_CR18_BASEADDR_SWITCH_EN(x)
27046#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK CSI_CR18_BASEADDR_SWITCH_SEL_MASK
27047#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT
27048#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) CSI_CR18_BASEADDR_SWITCH_SEL(x)
27049#define CSI_CSICR18_FIELD0_DONE_IE_MASK CSI_CR18_FIELD0_DONE_IE_MASK
27050#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT CSI_CR18_FIELD0_DONE_IE_SHIFT
27051#define CSI_CSICR18_FIELD0_DONE_IE(x) CSI_CR18_FIELD0_DONE_IE(x)
27052#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK CSI_CR18_DMA_FIELD1_DONE_IE_MASK
27053#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT
27054#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) CSI_CR18_DMA_FIELD1_DONE_IE(x)
27055#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK CSI_CR18_LAST_DMA_REQ_SEL_MASK
27056#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT CSI_CR18_LAST_DMA_REQ_SEL_SHIFT
27057#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) CSI_CR18_LAST_DMA_REQ_SEL(x)
27058#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK
27059#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT
27060#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x)
27061#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK CSI_CR18_RGB888A_FORMAT_SEL_MASK
27062#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT CSI_CR18_RGB888A_FORMAT_SEL_SHIFT
27063#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) CSI_CR18_RGB888A_FORMAT_SEL(x)
27064#define CSI_CSICR18_AHB_HPROT_MASK CSI_CR18_AHB_HPROT_MASK
27065#define CSI_CSICR18_AHB_HPROT_SHIFT CSI_CR18_AHB_HPROT_SHIFT
27066#define CSI_CSICR18_AHB_HPROT(x) CSI_CR18_AHB_HPROT(x)
27067#define CSI_CSICR18_MASK_OPTION_MASK CSI_CR18_MASK_OPTION_MASK
27068#define CSI_CSICR18_MASK_OPTION_SHIFT CSI_CR18_MASK_OPTION_SHIFT
27069#define CSI_CSICR18_MASK_OPTION(x) CSI_CR18_MASK_OPTION(x)
27070#define CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK CSI_CR18_MIPI_DOUBLE_CMPNT_MASK
27071#define CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT
27072#define CSI_CSICR18_MIPI_DOUBLE_CMPNT(x) CSI_CR18_MIPI_DOUBLE_CMPNT(x)
27073#define CSI_CSICR18_MIPI_YU_SWAP_MASK CSI_CR18_MIPI_YU_SWAP_MASK
27074#define CSI_CSICR18_MIPI_YU_SWAP_SHIFT CSI_CR18_MIPI_YU_SWAP_SHIFT
27075#define CSI_CSICR18_MIPI_YU_SWAP(x) CSI_CR18_MIPI_YU_SWAP(x)
27076#define CSI_CSICR18_DATA_FROM_MIPI_MASK CSI_CR18_DATA_FROM_MIPI_MASK
27077#define CSI_CSICR18_DATA_FROM_MIPI_SHIFT CSI_CR18_DATA_FROM_MIPI_SHIFT
27078#define CSI_CSICR18_DATA_FROM_MIPI(x) CSI_CR18_DATA_FROM_MIPI(x)
27079#define CSI_CSICR18_LINE_STRIDE_EN_MASK CSI_CR18_LINE_STRIDE_EN_MASK
27080#define CSI_CSICR18_LINE_STRIDE_EN_SHIFT CSI_CR18_LINE_STRIDE_EN_SHIFT
27081#define CSI_CSICR18_LINE_STRIDE_EN(x) CSI_CR18_LINE_STRIDE_EN(x)
27082#define CSI_CSICR18_MIPI_DATA_FORMAT_MASK CSI_CR18_MIPI_DATA_FORMAT_MASK
27083#define CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT CSI_CR18_MIPI_DATA_FORMAT_SHIFT
27084#define CSI_CSICR18_MIPI_DATA_FORMAT(x) CSI_CR18_MIPI_DATA_FORMAT(x)
27085#define CSI_CSICR18_CSI_ENABLE_MASK CSI_CR18_CSI_ENABLE_MASK
27086#define CSI_CSICR18_CSI_ENABLE_SHIFT CSI_CR18_CSI_ENABLE_SHIFT
27087#define CSI_CSICR18_CSI_ENABLE(x) CSI_CR18_CSI_ENABLE(x)
27088#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK
27089#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT
27090#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x)
27091#define CSI_CSICR20_THRESHOLD_MASK CSI_CR20_THRESHOLD_MASK
27092#define CSI_CSICR20_THRESHOLD_SHIFT CSI_CR20_THRESHOLD_SHIFT
27093#define CSI_CSICR20_THRESHOLD(x) CSI_CR20_THRESHOLD(x)
27094#define CSI_CSICR20_BINARY_EN_MASK CSI_CR20_BINARY_EN_MASK
27095#define CSI_CSICR20_BINARY_EN_SHIFT CSI_CR20_BINARY_EN_SHIFT
27096#define CSI_CSICR20_BINARY_EN(x) CSI_CR20_BINARY_EN(x)
27097#define CSI_CSICR20_QR_DATA_FORMAT_MASK CSI_CR20_QR_DATA_FORMAT_MASK
27098#define CSI_CSICR20_QR_DATA_FORMAT_SHIFT CSI_CR20_QR_DATA_FORMAT_SHIFT
27099#define CSI_CSICR20_QR_DATA_FORMAT(x) CSI_CR20_QR_DATA_FORMAT(x)
27100#define CSI_CSICR20_BIG_END_MASK CSI_CR20_BIG_END_MASK
27101#define CSI_CSICR20_BIG_END_SHIFT CSI_CR20_BIG_END_SHIFT
27102#define CSI_CSICR20_BIG_END(x) CSI_CR20_BIG_END(x)
27103#define CSI_CSICR20_10BIT_NEW_EN_MASK CSI_CR20_10BIT_NEW_EN_MASK
27104#define CSI_CSICR20_10BIT_NEW_EN_SHIFT CSI_CR20_10BIT_NEW_EN_SHIFT
27105#define CSI_CSICR20_10BIT_NEW_EN(x) CSI_CR20_10BIT_NEW_EN(x)
27106#define CSI_CSICR20_HISTOGRAM_EN_MASK CSI_CR20_HISTOGRAM_EN_MASK
27107#define CSI_CSICR20_HISTOGRAM_EN_SHIFT CSI_CR20_HISTOGRAM_EN_SHIFT
27108#define CSI_CSICR20_HISTOGRAM_EN(x) CSI_CR20_HISTOGRAM_EN(x)
27109#define CSI_CSICR20_QRCODE_EN_MASK CSI_CR20_QRCODE_EN_MASK
27110#define CSI_CSICR20_QRCODE_EN_SHIFT CSI_CR20_QRCODE_EN_SHIFT
27111#define CSI_CSICR20_QRCODE_EN(x) CSI_CR20_QRCODE_EN(x)
27112#define CSI_CSICR21_PIXEL_COUNTERS_MASK CSI_CR21_PIXEL_COUNTERS_MASK
27113#define CSI_CSICR21_PIXEL_COUNTERS_SHIFT CSI_CR21_PIXEL_COUNTERS_SHIFT
27114#define CSI_CSICR21_PIXEL_COUNTERS(x) CSI_CR21_PIXEL_COUNTERS(x)
27115#define CSI_CSICR22_PIXEL_COUNTERS_MASK CSI_CR22_PIXEL_COUNTERS_MASK
27116#define CSI_CSICR22_PIXEL_COUNTERS_SHIFT CSI_CR22_PIXEL_COUNTERS_SHIFT
27117#define CSI_CSICR22_PIXEL_COUNTERS(x) CSI_CR22_PIXEL_COUNTERS(x)
27118#define CSI_CSICR23_PIXEL_COUNTERS_MASK CSI_CR23_PIXEL_COUNTERS_MASK
27119#define CSI_CSICR23_PIXEL_COUNTERS_SHIFT CSI_CR23_PIXEL_COUNTERS_SHIFT
27120#define CSI_CSICR23_PIXEL_COUNTERS(x) CSI_CR23_PIXEL_COUNTERS(x)
27121#define CSI_CSICR24_PIXEL_COUNTERS_MASK CSI_CR24_PIXEL_COUNTERS_MASK
27122#define CSI_CSICR24_PIXEL_COUNTERS_SHIFT CSI_CR24_PIXEL_COUNTERS_SHIFT
27123#define CSI_CSICR24_PIXEL_COUNTERS(x) CSI_CR24_PIXEL_COUNTERS(x)
27124#define CSI_CSICR25_PIXEL_COUNTERS_MASK CSI_CR25_PIXEL_COUNTERS_MASK
27125#define CSI_CSICR25_PIXEL_COUNTERS_SHIFT CSI_CR25_PIXEL_COUNTERS_SHIFT
27126#define CSI_CSICR25_PIXEL_COUNTERS(x) CSI_CR25_PIXEL_COUNTERS(x)
27127#define CSI_CSICR26_PIXEL_COUNTERS_MASK CSI_CR26_PIXEL_COUNTERS_MASK
27128#define CSI_CSICR26_PIXEL_COUNTERS_SHIFT CSI_CR26_PIXEL_COUNTERS_SHIFT
27129#define CSI_CSICR26_PIXEL_COUNTERS(x) CSI_CR26_PIXEL_COUNTERS(x)
27130#define CSI_CSICR27_PIXEL_COUNTERS_MASK CSI_CR27_PIXEL_COUNTERS_MASK
27131#define CSI_CSICR27_PIXEL_COUNTERS_SHIFT CSI_CR27_PIXEL_COUNTERS_SHIFT
27132#define CSI_CSICR27_PIXEL_COUNTERS(x) CSI_CR27_PIXEL_COUNTERS(x)
27133#define CSI_CSICR28_PIXEL_COUNTERS_MASK CSI_CR28_PIXEL_COUNTERS_MASK
27134#define CSI_CSICR28_PIXEL_COUNTERS_SHIFT CSI_CR28_PIXEL_COUNTERS_SHIFT
27135#define CSI_CSICR28_PIXEL_COUNTERS(x) CSI_CR28_PIXEL_COUNTERS(x)
27136#define CSI_CSICR29_PIXEL_COUNTERS_MASK CSI_CR29_PIXEL_COUNTERS_MASK
27137#define CSI_CSICR29_PIXEL_COUNTERS_SHIFT CSI_CR29_PIXEL_COUNTERS_SHIFT
27138#define CSI_CSICR29_PIXEL_COUNTERS(x) CSI_CR29_PIXEL_COUNTERS(x)
27139#define CSI_CSICR30_PIXEL_COUNTERS_MASK CSI_CR30_PIXEL_COUNTERS_MASK
27140#define CSI_CSICR30_PIXEL_COUNTERS_SHIFT CSI_CR30_PIXEL_COUNTERS_SHIFT
27141#define CSI_CSICR30_PIXEL_COUNTERS(x) CSI_CR30_PIXEL_COUNTERS(x)
27142#define CSI_CSICR31_PIXEL_COUNTERS_MASK CSI_CR31_PIXEL_COUNTERS_MASK
27143#define CSI_CSICR31_PIXEL_COUNTERS_SHIFT CSI_CR31_PIXEL_COUNTERS_SHIFT
27144#define CSI_CSICR31_PIXEL_COUNTERS(x) CSI_CR31_PIXEL_COUNTERS(x)
27145#define CSI_CSICR32_PIXEL_COUNTERS_MASK CSI_CR32_PIXEL_COUNTERS_MASK
27146#define CSI_CSICR32_PIXEL_COUNTERS_SHIFT CSI_CR32_PIXEL_COUNTERS_SHIFT
27147#define CSI_CSICR32_PIXEL_COUNTERS(x) CSI_CR32_PIXEL_COUNTERS(x)
27148#define CSI_CSICR33_PIXEL_COUNTERS_MASK CSI_CR33_PIXEL_COUNTERS_MASK
27149#define CSI_CSICR33_PIXEL_COUNTERS_SHIFT CSI_CR33_PIXEL_COUNTERS_SHIFT
27150#define CSI_CSICR33_PIXEL_COUNTERS(x) CSI_CR33_PIXEL_COUNTERS(x)
27151#define CSI_CSICR34_PIXEL_COUNTERS_MASK CSI_CR34_PIXEL_COUNTERS_MASK
27152#define CSI_CSICR34_PIXEL_COUNTERS_SHIFT CSI_CR34_PIXEL_COUNTERS_SHIFT
27153#define CSI_CSICR34_PIXEL_COUNTERS(x) CSI_CR34_PIXEL_COUNTERS(x)
27154#define CSI_CSICR35_PIXEL_COUNTERS_MASK CSI_CR35_PIXEL_COUNTERS_MASK
27155#define CSI_CSICR35_PIXEL_COUNTERS_SHIFT CSI_CR35_PIXEL_COUNTERS_SHIFT
27156#define CSI_CSICR35_PIXEL_COUNTERS(x) CSI_CR35_PIXEL_COUNTERS(x)
27157#define CSI_CSICR36_PIXEL_COUNTERS_MASK CSI_CR36_PIXEL_COUNTERS_MASK
27158#define CSI_CSICR36_PIXEL_COUNTERS_SHIFT CSI_CR36_PIXEL_COUNTERS_SHIFT
27159#define CSI_CSICR36_PIXEL_COUNTERS(x) CSI_CR36_PIXEL_COUNTERS(x)
27160#define CSI_CSICR37_PIXEL_COUNTERS_MASK CSI_CR37_PIXEL_COUNTERS_MASK
27161#define CSI_CSICR37_PIXEL_COUNTERS_SHIFT CSI_CR37_PIXEL_COUNTERS_SHIFT
27162#define CSI_CSICR37_PIXEL_COUNTERS(x) CSI_CR37_PIXEL_COUNTERS(x)
27163#define CSI_CSICR38_PIXEL_COUNTERS_MASK CSI_CR38_PIXEL_COUNTERS_MASK
27164#define CSI_CSICR38_PIXEL_COUNTERS_SHIFT CSI_CR38_PIXEL_COUNTERS_SHIFT
27165#define CSI_CSICR38_PIXEL_COUNTERS(x) CSI_CR38_PIXEL_COUNTERS(x)
27166#define CSI_CSICR39_PIXEL_COUNTERS_MASK CSI_CR39_PIXEL_COUNTERS_MASK
27167#define CSI_CSICR39_PIXEL_COUNTERS_SHIFT CSI_CR39_PIXEL_COUNTERS_SHIFT
27168#define CSI_CSICR39_PIXEL_COUNTERS(x) CSI_CR39_PIXEL_COUNTERS(x)
27169#define CSI_CSICR40_PIXEL_COUNTERS_MASK CSI_CR40_PIXEL_COUNTERS_MASK
27170#define CSI_CSICR40_PIXEL_COUNTERS_SHIFT CSI_CR40_PIXEL_COUNTERS_SHIFT
27171#define CSI_CSICR40_PIXEL_COUNTERS(x) CSI_CR40_PIXEL_COUNTERS(x)
27172#define CSI_CSICR41_PIXEL_COUNTERS_MASK CSI_CR41_PIXEL_COUNTERS_MASK
27173#define CSI_CSICR41_PIXEL_COUNTERS_SHIFT CSI_CR41_PIXEL_COUNTERS_SHIFT
27174#define CSI_CSICR41_PIXEL_COUNTERS(x) CSI_CR41_PIXEL_COUNTERS(x)
27175#define CSI_CSICR42_PIXEL_COUNTERS_MASK CSI_CR42_PIXEL_COUNTERS_MASK
27176#define CSI_CSICR42_PIXEL_COUNTERS_SHIFT CSI_CR42_PIXEL_COUNTERS_SHIFT
27177#define CSI_CSICR42_PIXEL_COUNTERS(x) CSI_CR42_PIXEL_COUNTERS(x)
27178#define CSI_CSICR43_PIXEL_COUNTERS_MASK CSI_CR43_PIXEL_COUNTERS_MASK
27179#define CSI_CSICR43_PIXEL_COUNTERS_SHIFT CSI_CR43_PIXEL_COUNTERS_SHIFT
27180#define CSI_CSICR43_PIXEL_COUNTERS(x) CSI_CR43_PIXEL_COUNTERS(x)
27181#define CSI_CSICR44_PIXEL_COUNTERS_MASK CSI_CR44_PIXEL_COUNTERS_MASK
27182#define CSI_CSICR44_PIXEL_COUNTERS_SHIFT CSI_CR44_PIXEL_COUNTERS_SHIFT
27183#define CSI_CSICR44_PIXEL_COUNTERS(x) CSI_CR44_PIXEL_COUNTERS(x)
27184#define CSI_CSICR45_PIXEL_COUNTERS_MASK CSI_CR45_PIXEL_COUNTERS_MASK
27185#define CSI_CSICR45_PIXEL_COUNTERS_SHIFT CSI_CR45_PIXEL_COUNTERS_SHIFT
27186#define CSI_CSICR45_PIXEL_COUNTERS(x) CSI_CR45_PIXEL_COUNTERS(x)
27187#define CSI_CSICR46_PIXEL_COUNTERS_MASK CSI_CR46_PIXEL_COUNTERS_MASK
27188#define CSI_CSICR46_PIXEL_COUNTERS_SHIFT CSI_CR46_PIXEL_COUNTERS_SHIFT
27189#define CSI_CSICR46_PIXEL_COUNTERS(x) CSI_CR46_PIXEL_COUNTERS(x)
27190#define CSI_CSICR47_PIXEL_COUNTERS_MASK CSI_CR47_PIXEL_COUNTERS_MASK
27191#define CSI_CSICR47_PIXEL_COUNTERS_SHIFT CSI_CR47_PIXEL_COUNTERS_SHIFT
27192#define CSI_CSICR47_PIXEL_COUNTERS(x) CSI_CR47_PIXEL_COUNTERS(x)
27193#define CSI_CSICR48_PIXEL_COUNTERS_MASK CSI_CR48_PIXEL_COUNTERS_MASK
27194#define CSI_CSICR48_PIXEL_COUNTERS_SHIFT CSI_CR48_PIXEL_COUNTERS_SHIFT
27195#define CSI_CSICR48_PIXEL_COUNTERS(x) CSI_CR48_PIXEL_COUNTERS(x)
27196#define CSI_CSICR49_PIXEL_COUNTERS_MASK CSI_CR49_PIXEL_COUNTERS_MASK
27197#define CSI_CSICR49_PIXEL_COUNTERS_SHIFT CSI_CR49_PIXEL_COUNTERS_SHIFT
27198#define CSI_CSICR49_PIXEL_COUNTERS(x) CSI_CR49_PIXEL_COUNTERS(x)
27199#define CSI_CSICR50_PIXEL_COUNTERS_MASK CSI_CR50_PIXEL_COUNTERS_MASK
27200#define CSI_CSICR50_PIXEL_COUNTERS_SHIFT CSI_CR50_PIXEL_COUNTERS_SHIFT
27201#define CSI_CSICR50_PIXEL_COUNTERS(x) CSI_CR50_PIXEL_COUNTERS(x)
27202#define CSI_CSICR51_PIXEL_COUNTERS_MASK CSI_CR51_PIXEL_COUNTERS_MASK
27203#define CSI_CSICR51_PIXEL_COUNTERS_SHIFT CSI_CR51_PIXEL_COUNTERS_SHIFT
27204#define CSI_CSICR51_PIXEL_COUNTERS(x) CSI_CR51_PIXEL_COUNTERS(x)
27205#define CSI_CSICR52_PIXEL_COUNTERS_MASK CSI_CR52_PIXEL_COUNTERS_MASK
27206#define CSI_CSICR52_PIXEL_COUNTERS_SHIFT CSI_CR52_PIXEL_COUNTERS_SHIFT
27207#define CSI_CSICR52_PIXEL_COUNTERS(x) CSI_CR52_PIXEL_COUNTERS(x)
27208#define CSI_CSICR53_PIXEL_COUNTERS_MASK CSI_CR53_PIXEL_COUNTERS_MASK
27209#define CSI_CSICR53_PIXEL_COUNTERS_SHIFT CSI_CR53_PIXEL_COUNTERS_SHIFT
27210#define CSI_CSICR53_PIXEL_COUNTERS(x) CSI_CR53_PIXEL_COUNTERS(x)
27211#define CSI_CSICR54_PIXEL_COUNTERS_MASK CSI_CR54_PIXEL_COUNTERS_MASK
27212#define CSI_CSICR54_PIXEL_COUNTERS_SHIFT CSI_CR54_PIXEL_COUNTERS_SHIFT
27213#define CSI_CSICR54_PIXEL_COUNTERS(x) CSI_CR54_PIXEL_COUNTERS(x)
27214#define CSI_CSICR55_PIXEL_COUNTERS_MASK CSI_CR55_PIXEL_COUNTERS_MASK
27215#define CSI_CSICR55_PIXEL_COUNTERS_SHIFT CSI_CR55_PIXEL_COUNTERS_SHIFT
27216#define CSI_CSICR55_PIXEL_COUNTERS(x) CSI_CR55_PIXEL_COUNTERS(x)
27217#define CSI_CSICR56_PIXEL_COUNTERS_MASK CSI_CR56_PIXEL_COUNTERS_MASK
27218#define CSI_CSICR56_PIXEL_COUNTERS_SHIFT CSI_CR56_PIXEL_COUNTERS_SHIFT
27219#define CSI_CSICR56_PIXEL_COUNTERS(x) CSI_CR56_PIXEL_COUNTERS(x)
27220#define CSI_CSICR57_PIXEL_COUNTERS_MASK CSI_CR57_PIXEL_COUNTERS_MASK
27221#define CSI_CSICR57_PIXEL_COUNTERS_SHIFT CSI_CR57_PIXEL_COUNTERS_SHIFT
27222#define CSI_CSICR57_PIXEL_COUNTERS(x) CSI_CR57_PIXEL_COUNTERS(x)
27223#define CSI_CSICR58_PIXEL_COUNTERS_MASK CSI_CR58_PIXEL_COUNTERS_MASK
27224#define CSI_CSICR58_PIXEL_COUNTERS_SHIFT CSI_CR58_PIXEL_COUNTERS_SHIFT
27225#define CSI_CSICR58_PIXEL_COUNTERS(x) CSI_CR58_PIXEL_COUNTERS(x)
27226#define CSI_CSICR59_PIXEL_COUNTERS_MASK CSI_CR59_PIXEL_COUNTERS_MASK
27227#define CSI_CSICR59_PIXEL_COUNTERS_SHIFT CSI_CR59_PIXEL_COUNTERS_SHIFT
27228#define CSI_CSICR59_PIXEL_COUNTERS(x) CSI_CR59_PIXEL_COUNTERS(x)
27229#define CSI_CSICR60_PIXEL_COUNTERS_MASK CSI_CR60_PIXEL_COUNTERS_MASK
27230#define CSI_CSICR60_PIXEL_COUNTERS_SHIFT CSI_CR60_PIXEL_COUNTERS_SHIFT
27231#define CSI_CSICR60_PIXEL_COUNTERS(x) CSI_CR60_PIXEL_COUNTERS(x)
27232#define CSI_CSICR61_PIXEL_COUNTERS_MASK CSI_CR61_PIXEL_COUNTERS_MASK
27233#define CSI_CSICR61_PIXEL_COUNTERS_SHIFT CSI_CR61_PIXEL_COUNTERS_SHIFT
27234#define CSI_CSICR61_PIXEL_COUNTERS(x) CSI_CR61_PIXEL_COUNTERS(x)
27235#define CSI_CSICR62_PIXEL_COUNTERS_MASK CSI_CR62_PIXEL_COUNTERS_MASK
27236#define CSI_CSICR62_PIXEL_COUNTERS_SHIFT CSI_CR62_PIXEL_COUNTERS_SHIFT
27237#define CSI_CSICR62_PIXEL_COUNTERS(x) CSI_CR62_PIXEL_COUNTERS(x)
27238#define CSI_CSICR63_PIXEL_COUNTERS_MASK CSI_CR63_PIXEL_COUNTERS_MASK
27239#define CSI_CSICR63_PIXEL_COUNTERS_SHIFT CSI_CR63_PIXEL_COUNTERS_SHIFT
27240#define CSI_CSICR63_PIXEL_COUNTERS(x) CSI_CR63_PIXEL_COUNTERS(x)
27241#define CSI_CSICR64_PIXEL_COUNTERS_MASK CSI_CR64_PIXEL_COUNTERS_MASK
27242#define CSI_CSICR64_PIXEL_COUNTERS_SHIFT CSI_CR64_PIXEL_COUNTERS_SHIFT
27243#define CSI_CSICR64_PIXEL_COUNTERS(x) CSI_CR64_PIXEL_COUNTERS(x)
27244#define CSI_CSICR65_PIXEL_COUNTERS_MASK CSI_CR65_PIXEL_COUNTERS_MASK
27245#define CSI_CSICR65_PIXEL_COUNTERS_SHIFT CSI_CR65_PIXEL_COUNTERS_SHIFT
27246#define CSI_CSICR65_PIXEL_COUNTERS(x) CSI_CR65_PIXEL_COUNTERS(x)
27247#define CSI_CSICR66_PIXEL_COUNTERS_MASK CSI_CR66_PIXEL_COUNTERS_MASK
27248#define CSI_CSICR66_PIXEL_COUNTERS_SHIFT CSI_CR66_PIXEL_COUNTERS_SHIFT
27249#define CSI_CSICR66_PIXEL_COUNTERS(x) CSI_CR66_PIXEL_COUNTERS(x)
27250#define CSI_CSICR67_PIXEL_COUNTERS_MASK CSI_CR67_PIXEL_COUNTERS_MASK
27251#define CSI_CSICR67_PIXEL_COUNTERS_SHIFT CSI_CR67_PIXEL_COUNTERS_SHIFT
27252#define CSI_CSICR67_PIXEL_COUNTERS(x) CSI_CR67_PIXEL_COUNTERS(x)
27253#define CSI_CSICR68_PIXEL_COUNTERS_MASK CSI_CR68_PIXEL_COUNTERS_MASK
27254#define CSI_CSICR68_PIXEL_COUNTERS_SHIFT CSI_CR68_PIXEL_COUNTERS_SHIFT
27255#define CSI_CSICR68_PIXEL_COUNTERS(x) CSI_CR68_PIXEL_COUNTERS(x)
27256#define CSI_CSICR69_PIXEL_COUNTERS_MASK CSI_CR69_PIXEL_COUNTERS_MASK
27257#define CSI_CSICR69_PIXEL_COUNTERS_SHIFT CSI_CR69_PIXEL_COUNTERS_SHIFT
27258#define CSI_CSICR69_PIXEL_COUNTERS(x) CSI_CR69_PIXEL_COUNTERS(x)
27259#define CSI_CSICR70_PIXEL_COUNTERS_MASK CSI_CR70_PIXEL_COUNTERS_MASK
27260#define CSI_CSICR70_PIXEL_COUNTERS_SHIFT CSI_CR70_PIXEL_COUNTERS_SHIFT
27261#define CSI_CSICR70_PIXEL_COUNTERS(x) CSI_CR70_PIXEL_COUNTERS(x)
27262#define CSI_CSICR71_PIXEL_COUNTERS_MASK CSI_CR71_PIXEL_COUNTERS_MASK
27263#define CSI_CSICR71_PIXEL_COUNTERS_SHIFT CSI_CR71_PIXEL_COUNTERS_SHIFT
27264#define CSI_CSICR71_PIXEL_COUNTERS(x) CSI_CR71_PIXEL_COUNTERS(x)
27265#define CSI_CSICR72_PIXEL_COUNTERS_MASK CSI_CR72_PIXEL_COUNTERS_MASK
27266#define CSI_CSICR72_PIXEL_COUNTERS_SHIFT CSI_CR72_PIXEL_COUNTERS_SHIFT
27267#define CSI_CSICR72_PIXEL_COUNTERS(x) CSI_CR72_PIXEL_COUNTERS(x)
27268#define CSI_CSICR73_PIXEL_COUNTERS_MASK CSI_CR73_PIXEL_COUNTERS_MASK
27269#define CSI_CSICR73_PIXEL_COUNTERS_SHIFT CSI_CR73_PIXEL_COUNTERS_SHIFT
27270#define CSI_CSICR73_PIXEL_COUNTERS(x) CSI_CR73_PIXEL_COUNTERS(x)
27271#define CSI_CSICR74_PIXEL_COUNTERS_MASK CSI_CR74_PIXEL_COUNTERS_MASK
27272#define CSI_CSICR74_PIXEL_COUNTERS_SHIFT CSI_CR74_PIXEL_COUNTERS_SHIFT
27273#define CSI_CSICR74_PIXEL_COUNTERS(x) CSI_CR74_PIXEL_COUNTERS(x)
27274#define CSI_CSICR75_PIXEL_COUNTERS_MASK CSI_CR75_PIXEL_COUNTERS_MASK
27275#define CSI_CSICR75_PIXEL_COUNTERS_SHIFT CSI_CR75_PIXEL_COUNTERS_SHIFT
27276#define CSI_CSICR75_PIXEL_COUNTERS(x) CSI_CR75_PIXEL_COUNTERS(x)
27277#define CSI_CSICR76_PIXEL_COUNTERS_MASK CSI_CR76_PIXEL_COUNTERS_MASK
27278#define CSI_CSICR76_PIXEL_COUNTERS_SHIFT CSI_CR76_PIXEL_COUNTERS_SHIFT
27279#define CSI_CSICR76_PIXEL_COUNTERS(x) CSI_CR76_PIXEL_COUNTERS(x)
27280#define CSI_CSICR77_PIXEL_COUNTERS_MASK CSI_CR77_PIXEL_COUNTERS_MASK
27281#define CSI_CSICR77_PIXEL_COUNTERS_SHIFT CSI_CR77_PIXEL_COUNTERS_SHIFT
27282#define CSI_CSICR77_PIXEL_COUNTERS(x) CSI_CR77_PIXEL_COUNTERS(x)
27283#define CSI_CSICR78_PIXEL_COUNTERS_MASK CSI_CR78_PIXEL_COUNTERS_MASK
27284#define CSI_CSICR78_PIXEL_COUNTERS_SHIFT CSI_CR78_PIXEL_COUNTERS_SHIFT
27285#define CSI_CSICR78_PIXEL_COUNTERS(x) CSI_CR78_PIXEL_COUNTERS(x)
27286#define CSI_CSICR79_PIXEL_COUNTERS_MASK CSI_CR79_PIXEL_COUNTERS_MASK
27287#define CSI_CSICR79_PIXEL_COUNTERS_SHIFT CSI_CR79_PIXEL_COUNTERS_SHIFT
27288#define CSI_CSICR79_PIXEL_COUNTERS(x) CSI_CR79_PIXEL_COUNTERS(x)
27289#define CSI_CSICR80_PIXEL_COUNTERS_MASK CSI_CR80_PIXEL_COUNTERS_MASK
27290#define CSI_CSICR80_PIXEL_COUNTERS_SHIFT CSI_CR80_PIXEL_COUNTERS_SHIFT
27291#define CSI_CSICR80_PIXEL_COUNTERS(x) CSI_CR80_PIXEL_COUNTERS(x)
27292#define CSI_CSICR81_PIXEL_COUNTERS_MASK CSI_CR81_PIXEL_COUNTERS_MASK
27293#define CSI_CSICR81_PIXEL_COUNTERS_SHIFT CSI_CR81_PIXEL_COUNTERS_SHIFT
27294#define CSI_CSICR81_PIXEL_COUNTERS(x) CSI_CR81_PIXEL_COUNTERS(x)
27295#define CSI_CSICR82_PIXEL_COUNTERS_MASK CSI_CR82_PIXEL_COUNTERS_MASK
27296#define CSI_CSICR82_PIXEL_COUNTERS_SHIFT CSI_CR82_PIXEL_COUNTERS_SHIFT
27297#define CSI_CSICR82_PIXEL_COUNTERS(x) CSI_CR82_PIXEL_COUNTERS(x)
27298#define CSI_CSICR83_PIXEL_COUNTERS_MASK CSI_CR83_PIXEL_COUNTERS_MASK
27299#define CSI_CSICR83_PIXEL_COUNTERS_SHIFT CSI_CR83_PIXEL_COUNTERS_SHIFT
27300#define CSI_CSICR83_PIXEL_COUNTERS(x) CSI_CR83_PIXEL_COUNTERS(x)
27301#define CSI_CSICR84_PIXEL_COUNTERS_MASK CSI_CR84_PIXEL_COUNTERS_MASK
27302#define CSI_CSICR84_PIXEL_COUNTERS_SHIFT CSI_CR84_PIXEL_COUNTERS_SHIFT
27303#define CSI_CSICR84_PIXEL_COUNTERS(x) CSI_CR84_PIXEL_COUNTERS(x)
27304#define CSI_CSICR85_PIXEL_COUNTERS_MASK CSI_CR85_PIXEL_COUNTERS_MASK
27305#define CSI_CSICR85_PIXEL_COUNTERS_SHIFT CSI_CR85_PIXEL_COUNTERS_SHIFT
27306#define CSI_CSICR85_PIXEL_COUNTERS(x) CSI_CR85_PIXEL_COUNTERS(x)
27307#define CSI_CSICR86_PIXEL_COUNTERS_MASK CSI_CR86_PIXEL_COUNTERS_MASK
27308#define CSI_CSICR86_PIXEL_COUNTERS_SHIFT CSI_CR86_PIXEL_COUNTERS_SHIFT
27309#define CSI_CSICR86_PIXEL_COUNTERS(x) CSI_CR86_PIXEL_COUNTERS(x)
27310#define CSI_CSICR87_PIXEL_COUNTERS_MASK CSI_CR87_PIXEL_COUNTERS_MASK
27311#define CSI_CSICR87_PIXEL_COUNTERS_SHIFT CSI_CR87_PIXEL_COUNTERS_SHIFT
27312#define CSI_CSICR87_PIXEL_COUNTERS(x) CSI_CR87_PIXEL_COUNTERS(x)
27313#define CSI_CSICR88_PIXEL_COUNTERS_MASK CSI_CR88_PIXEL_COUNTERS_MASK
27314#define CSI_CSICR88_PIXEL_COUNTERS_SHIFT CSI_CR88_PIXEL_COUNTERS_SHIFT
27315#define CSI_CSICR88_PIXEL_COUNTERS(x) CSI_CR88_PIXEL_COUNTERS(x)
27316#define CSI_CSICR89_PIXEL_COUNTERS_MASK CSI_CR89_PIXEL_COUNTERS_MASK
27317#define CSI_CSICR89_PIXEL_COUNTERS_SHIFT CSI_CR89_PIXEL_COUNTERS_SHIFT
27318#define CSI_CSICR89_PIXEL_COUNTERS(x) CSI_CR89_PIXEL_COUNTERS(x)
27319#define CSI_CSICR90_PIXEL_COUNTERS_MASK CSI_CR90_PIXEL_COUNTERS_MASK
27320#define CSI_CSICR90_PIXEL_COUNTERS_SHIFT CSI_CR90_PIXEL_COUNTERS_SHIFT
27321#define CSI_CSICR90_PIXEL_COUNTERS(x) CSI_CR90_PIXEL_COUNTERS(x)
27322#define CSI_CSICR91_PIXEL_COUNTERS_MASK CSI_CR91_PIXEL_COUNTERS_MASK
27323#define CSI_CSICR91_PIXEL_COUNTERS_SHIFT CSI_CR91_PIXEL_COUNTERS_SHIFT
27324#define CSI_CSICR91_PIXEL_COUNTERS(x) CSI_CR91_PIXEL_COUNTERS(x)
27325#define CSI_CSICR92_PIXEL_COUNTERS_MASK CSI_CR92_PIXEL_COUNTERS_MASK
27326#define CSI_CSICR92_PIXEL_COUNTERS_SHIFT CSI_CR92_PIXEL_COUNTERS_SHIFT
27327#define CSI_CSICR92_PIXEL_COUNTERS(x) CSI_CR92_PIXEL_COUNTERS(x)
27328#define CSI_CSICR93_PIXEL_COUNTERS_MASK CSI_CR93_PIXEL_COUNTERS_MASK
27329#define CSI_CSICR93_PIXEL_COUNTERS_SHIFT CSI_CR93_PIXEL_COUNTERS_SHIFT
27330#define CSI_CSICR93_PIXEL_COUNTERS(x) CSI_CR93_PIXEL_COUNTERS(x)
27331#define CSI_CSICR94_PIXEL_COUNTERS_MASK CSI_CR94_PIXEL_COUNTERS_MASK
27332#define CSI_CSICR94_PIXEL_COUNTERS_SHIFT CSI_CR94_PIXEL_COUNTERS_SHIFT
27333#define CSI_CSICR94_PIXEL_COUNTERS(x) CSI_CR94_PIXEL_COUNTERS(x)
27334#define CSI_CSICR95_PIXEL_COUNTERS_MASK CSI_CR95_PIXEL_COUNTERS_MASK
27335#define CSI_CSICR95_PIXEL_COUNTERS_SHIFT CSI_CR95_PIXEL_COUNTERS_SHIFT
27336#define CSI_CSICR95_PIXEL_COUNTERS(x) CSI_CR95_PIXEL_COUNTERS(x)
27337#define CSI_CSICR96_PIXEL_COUNTERS_MASK CSI_CR96_PIXEL_COUNTERS_MASK
27338#define CSI_CSICR96_PIXEL_COUNTERS_SHIFT CSI_CR96_PIXEL_COUNTERS_SHIFT
27339#define CSI_CSICR96_PIXEL_COUNTERS(x) CSI_CR96_PIXEL_COUNTERS(x)
27340#define CSI_CSICR97_PIXEL_COUNTERS_MASK CSI_CR97_PIXEL_COUNTERS_MASK
27341#define CSI_CSICR97_PIXEL_COUNTERS_SHIFT CSI_CR97_PIXEL_COUNTERS_SHIFT
27342#define CSI_CSICR97_PIXEL_COUNTERS(x) CSI_CR97_PIXEL_COUNTERS(x)
27343#define CSI_CSICR98_PIXEL_COUNTERS_MASK CSI_CR98_PIXEL_COUNTERS_MASK
27344#define CSI_CSICR98_PIXEL_COUNTERS_SHIFT CSI_CR98_PIXEL_COUNTERS_SHIFT
27345#define CSI_CSICR98_PIXEL_COUNTERS(x) CSI_CR98_PIXEL_COUNTERS(x)
27346#define CSI_CSICR99_PIXEL_COUNTERS_MASK CSI_CR99_PIXEL_COUNTERS_MASK
27347#define CSI_CSICR99_PIXEL_COUNTERS_SHIFT CSI_CR99_PIXEL_COUNTERS_SHIFT
27348#define CSI_CSICR99_PIXEL_COUNTERS(x) CSI_CR99_PIXEL_COUNTERS(x)
27349#define CSI_CSICR100_PIXEL_COUNTERS_MASK CSI_CR100_PIXEL_COUNTERS_MASK
27350#define CSI_CSICR100_PIXEL_COUNTERS_SHIFT CSI_CR100_PIXEL_COUNTERS_SHIFT
27351#define CSI_CSICR100_PIXEL_COUNTERS(x) CSI_CR100_PIXEL_COUNTERS(x)
27352#define CSI_CSICR101_PIXEL_COUNTERS_MASK CSI_CR101_PIXEL_COUNTERS_MASK
27353#define CSI_CSICR101_PIXEL_COUNTERS_SHIFT CSI_CR101_PIXEL_COUNTERS_SHIFT
27354#define CSI_CSICR101_PIXEL_COUNTERS(x) CSI_CR101_PIXEL_COUNTERS(x)
27355#define CSI_CSICR102_PIXEL_COUNTERS_MASK CSI_CR102_PIXEL_COUNTERS_MASK
27356#define CSI_CSICR102_PIXEL_COUNTERS_SHIFT CSI_CR102_PIXEL_COUNTERS_SHIFT
27357#define CSI_CSICR102_PIXEL_COUNTERS(x) CSI_CR102_PIXEL_COUNTERS(x)
27358#define CSI_CSICR103_PIXEL_COUNTERS_MASK CSI_CR103_PIXEL_COUNTERS_MASK
27359#define CSI_CSICR103_PIXEL_COUNTERS_SHIFT CSI_CR103_PIXEL_COUNTERS_SHIFT
27360#define CSI_CSICR103_PIXEL_COUNTERS(x) CSI_CR103_PIXEL_COUNTERS(x)
27361#define CSI_CSICR104_PIXEL_COUNTERS_MASK CSI_CR104_PIXEL_COUNTERS_MASK
27362#define CSI_CSICR104_PIXEL_COUNTERS_SHIFT CSI_CR104_PIXEL_COUNTERS_SHIFT
27363#define CSI_CSICR104_PIXEL_COUNTERS(x) CSI_CR104_PIXEL_COUNTERS(x)
27364#define CSI_CSICR105_PIXEL_COUNTERS_MASK CSI_CR105_PIXEL_COUNTERS_MASK
27365#define CSI_CSICR105_PIXEL_COUNTERS_SHIFT CSI_CR105_PIXEL_COUNTERS_SHIFT
27366#define CSI_CSICR105_PIXEL_COUNTERS(x) CSI_CR105_PIXEL_COUNTERS(x)
27367#define CSI_CSICR106_PIXEL_COUNTERS_MASK CSI_CR106_PIXEL_COUNTERS_MASK
27368#define CSI_CSICR106_PIXEL_COUNTERS_SHIFT CSI_CR106_PIXEL_COUNTERS_SHIFT
27369#define CSI_CSICR106_PIXEL_COUNTERS(x) CSI_CR106_PIXEL_COUNTERS(x)
27370#define CSI_CSICR107_PIXEL_COUNTERS_MASK CSI_CR107_PIXEL_COUNTERS_MASK
27371#define CSI_CSICR107_PIXEL_COUNTERS_SHIFT CSI_CR107_PIXEL_COUNTERS_SHIFT
27372#define CSI_CSICR107_PIXEL_COUNTERS(x) CSI_CR107_PIXEL_COUNTERS(x)
27373#define CSI_CSICR108_PIXEL_COUNTERS_MASK CSI_CR108_PIXEL_COUNTERS_MASK
27374#define CSI_CSICR108_PIXEL_COUNTERS_SHIFT CSI_CR108_PIXEL_COUNTERS_SHIFT
27375#define CSI_CSICR108_PIXEL_COUNTERS(x) CSI_CR108_PIXEL_COUNTERS(x)
27376#define CSI_CSICR109_PIXEL_COUNTERS_MASK CSI_CR109_PIXEL_COUNTERS_MASK
27377#define CSI_CSICR109_PIXEL_COUNTERS_SHIFT CSI_CR109_PIXEL_COUNTERS_SHIFT
27378#define CSI_CSICR109_PIXEL_COUNTERS(x) CSI_CR109_PIXEL_COUNTERS(x)
27379#define CSI_CSICR110_PIXEL_COUNTERS_MASK CSI_CR110_PIXEL_COUNTERS_MASK
27380#define CSI_CSICR110_PIXEL_COUNTERS_SHIFT CSI_CR110_PIXEL_COUNTERS_SHIFT
27381#define CSI_CSICR110_PIXEL_COUNTERS(x) CSI_CR110_PIXEL_COUNTERS(x)
27382#define CSI_CSICR111_PIXEL_COUNTERS_MASK CSI_CR111_PIXEL_COUNTERS_MASK
27383#define CSI_CSICR111_PIXEL_COUNTERS_SHIFT CSI_CR111_PIXEL_COUNTERS_SHIFT
27384#define CSI_CSICR111_PIXEL_COUNTERS(x) CSI_CR111_PIXEL_COUNTERS(x)
27385#define CSI_CSICR112_PIXEL_COUNTERS_MASK CSI_CR112_PIXEL_COUNTERS_MASK
27386#define CSI_CSICR112_PIXEL_COUNTERS_SHIFT CSI_CR112_PIXEL_COUNTERS_SHIFT
27387#define CSI_CSICR112_PIXEL_COUNTERS(x) CSI_CR112_PIXEL_COUNTERS(x)
27388#define CSI_CSICR113_PIXEL_COUNTERS_MASK CSI_CR113_PIXEL_COUNTERS_MASK
27389#define CSI_CSICR113_PIXEL_COUNTERS_SHIFT CSI_CR113_PIXEL_COUNTERS_SHIFT
27390#define CSI_CSICR113_PIXEL_COUNTERS(x) CSI_CR113_PIXEL_COUNTERS(x)
27391#define CSI_CSICR114_PIXEL_COUNTERS_MASK CSI_CR114_PIXEL_COUNTERS_MASK
27392#define CSI_CSICR114_PIXEL_COUNTERS_SHIFT CSI_CR114_PIXEL_COUNTERS_SHIFT
27393#define CSI_CSICR114_PIXEL_COUNTERS(x) CSI_CR114_PIXEL_COUNTERS(x)
27394#define CSI_CSICR115_PIXEL_COUNTERS_MASK CSI_CR115_PIXEL_COUNTERS_MASK
27395#define CSI_CSICR115_PIXEL_COUNTERS_SHIFT CSI_CR115_PIXEL_COUNTERS_SHIFT
27396#define CSI_CSICR115_PIXEL_COUNTERS(x) CSI_CR115_PIXEL_COUNTERS(x)
27397#define CSI_CSICR116_PIXEL_COUNTERS_MASK CSI_CR116_PIXEL_COUNTERS_MASK
27398#define CSI_CSICR116_PIXEL_COUNTERS_SHIFT CSI_CR116_PIXEL_COUNTERS_SHIFT
27399#define CSI_CSICR116_PIXEL_COUNTERS(x) CSI_CR116_PIXEL_COUNTERS(x)
27400#define CSI_CSICR117_PIXEL_COUNTERS_MASK CSI_CR117_PIXEL_COUNTERS_MASK
27401#define CSI_CSICR117_PIXEL_COUNTERS_SHIFT CSI_CR117_PIXEL_COUNTERS_SHIFT
27402#define CSI_CSICR117_PIXEL_COUNTERS(x) CSI_CR117_PIXEL_COUNTERS(x)
27403#define CSI_CSICR118_PIXEL_COUNTERS_MASK CSI_CR118_PIXEL_COUNTERS_MASK
27404#define CSI_CSICR118_PIXEL_COUNTERS_SHIFT CSI_CR118_PIXEL_COUNTERS_SHIFT
27405#define CSI_CSICR118_PIXEL_COUNTERS(x) CSI_CR118_PIXEL_COUNTERS(x)
27406#define CSI_CSICR119_PIXEL_COUNTERS_MASK CSI_CR119_PIXEL_COUNTERS_MASK
27407#define CSI_CSICR119_PIXEL_COUNTERS_SHIFT CSI_CR119_PIXEL_COUNTERS_SHIFT
27408#define CSI_CSICR119_PIXEL_COUNTERS(x) CSI_CR119_PIXEL_COUNTERS(x)
27409#define CSI_CSICR120_PIXEL_COUNTERS_MASK CSI_CR120_PIXEL_COUNTERS_MASK
27410#define CSI_CSICR120_PIXEL_COUNTERS_SHIFT CSI_CR120_PIXEL_COUNTERS_SHIFT
27411#define CSI_CSICR120_PIXEL_COUNTERS(x) CSI_CR120_PIXEL_COUNTERS(x)
27412#define CSI_CSICR121_PIXEL_COUNTERS_MASK CSI_CR121_PIXEL_COUNTERS_MASK
27413#define CSI_CSICR121_PIXEL_COUNTERS_SHIFT CSI_CR121_PIXEL_COUNTERS_SHIFT
27414#define CSI_CSICR121_PIXEL_COUNTERS(x) CSI_CR121_PIXEL_COUNTERS(x)
27415#define CSI_CSICR122_PIXEL_COUNTERS_MASK CSI_CR122_PIXEL_COUNTERS_MASK
27416#define CSI_CSICR122_PIXEL_COUNTERS_SHIFT CSI_CR122_PIXEL_COUNTERS_SHIFT
27417#define CSI_CSICR122_PIXEL_COUNTERS(x) CSI_CR122_PIXEL_COUNTERS(x)
27418#define CSI_CSICR123_PIXEL_COUNTERS_MASK CSI_CR123_PIXEL_COUNTERS_MASK
27419#define CSI_CSICR123_PIXEL_COUNTERS_SHIFT CSI_CR123_PIXEL_COUNTERS_SHIFT
27420#define CSI_CSICR123_PIXEL_COUNTERS(x) CSI_CR123_PIXEL_COUNTERS(x)
27421#define CSI_CSICR124_PIXEL_COUNTERS_MASK CSI_CR124_PIXEL_COUNTERS_MASK
27422#define CSI_CSICR124_PIXEL_COUNTERS_SHIFT CSI_CR124_PIXEL_COUNTERS_SHIFT
27423#define CSI_CSICR124_PIXEL_COUNTERS(x) CSI_CR124_PIXEL_COUNTERS(x)
27424#define CSI_CSICR125_PIXEL_COUNTERS_MASK CSI_CR125_PIXEL_COUNTERS_MASK
27425#define CSI_CSICR125_PIXEL_COUNTERS_SHIFT CSI_CR125_PIXEL_COUNTERS_SHIFT
27426#define CSI_CSICR125_PIXEL_COUNTERS(x) CSI_CR125_PIXEL_COUNTERS(x)
27427#define CSI_CSICR126_PIXEL_COUNTERS_MASK CSI_CR126_PIXEL_COUNTERS_MASK
27428#define CSI_CSICR126_PIXEL_COUNTERS_SHIFT CSI_CR126_PIXEL_COUNTERS_SHIFT
27429#define CSI_CSICR126_PIXEL_COUNTERS(x) CSI_CR126_PIXEL_COUNTERS(x)
27430#define CSI_CSICR127_PIXEL_COUNTERS_MASK CSI_CR127_PIXEL_COUNTERS_MASK
27431#define CSI_CSICR127_PIXEL_COUNTERS_SHIFT CSI_CR127_PIXEL_COUNTERS_SHIFT
27432#define CSI_CSICR127_PIXEL_COUNTERS(x) CSI_CR127_PIXEL_COUNTERS(x)
27433#define CSI_CSICR128_PIXEL_COUNTERS_MASK CSI_CR128_PIXEL_COUNTERS_MASK
27434#define CSI_CSICR128_PIXEL_COUNTERS_SHIFT CSI_CR128_PIXEL_COUNTERS_SHIFT
27435#define CSI_CSICR128_PIXEL_COUNTERS(x) CSI_CR128_PIXEL_COUNTERS(x)
27436#define CSI_CSICR129_PIXEL_COUNTERS_MASK CSI_CR129_PIXEL_COUNTERS_MASK
27437#define CSI_CSICR129_PIXEL_COUNTERS_SHIFT CSI_CR129_PIXEL_COUNTERS_SHIFT
27438#define CSI_CSICR129_PIXEL_COUNTERS(x) CSI_CR129_PIXEL_COUNTERS(x)
27439#define CSI_CSICR130_PIXEL_COUNTERS_MASK CSI_CR130_PIXEL_COUNTERS_MASK
27440#define CSI_CSICR130_PIXEL_COUNTERS_SHIFT CSI_CR130_PIXEL_COUNTERS_SHIFT
27441#define CSI_CSICR130_PIXEL_COUNTERS(x) CSI_CR130_PIXEL_COUNTERS(x)
27442#define CSI_CSICR131_PIXEL_COUNTERS_MASK CSI_CR131_PIXEL_COUNTERS_MASK
27443#define CSI_CSICR131_PIXEL_COUNTERS_SHIFT CSI_CR131_PIXEL_COUNTERS_SHIFT
27444#define CSI_CSICR131_PIXEL_COUNTERS(x) CSI_CR131_PIXEL_COUNTERS(x)
27445#define CSI_CSICR132_PIXEL_COUNTERS_MASK CSI_CR132_PIXEL_COUNTERS_MASK
27446#define CSI_CSICR132_PIXEL_COUNTERS_SHIFT CSI_CR132_PIXEL_COUNTERS_SHIFT
27447#define CSI_CSICR132_PIXEL_COUNTERS(x) CSI_CR132_PIXEL_COUNTERS(x)
27448#define CSI_CSICR133_PIXEL_COUNTERS_MASK CSI_CR133_PIXEL_COUNTERS_MASK
27449#define CSI_CSICR133_PIXEL_COUNTERS_SHIFT CSI_CR133_PIXEL_COUNTERS_SHIFT
27450#define CSI_CSICR133_PIXEL_COUNTERS(x) CSI_CR133_PIXEL_COUNTERS(x)
27451#define CSI_CSICR134_PIXEL_COUNTERS_MASK CSI_CR134_PIXEL_COUNTERS_MASK
27452#define CSI_CSICR134_PIXEL_COUNTERS_SHIFT CSI_CR134_PIXEL_COUNTERS_SHIFT
27453#define CSI_CSICR134_PIXEL_COUNTERS(x) CSI_CR134_PIXEL_COUNTERS(x)
27454#define CSI_CSICR135_PIXEL_COUNTERS_MASK CSI_CR135_PIXEL_COUNTERS_MASK
27455#define CSI_CSICR135_PIXEL_COUNTERS_SHIFT CSI_CR135_PIXEL_COUNTERS_SHIFT
27456#define CSI_CSICR135_PIXEL_COUNTERS(x) CSI_CR135_PIXEL_COUNTERS(x)
27457#define CSI_CSICR136_PIXEL_COUNTERS_MASK CSI_CR136_PIXEL_COUNTERS_MASK
27458#define CSI_CSICR136_PIXEL_COUNTERS_SHIFT CSI_CR136_PIXEL_COUNTERS_SHIFT
27459#define CSI_CSICR136_PIXEL_COUNTERS(x) CSI_CR136_PIXEL_COUNTERS(x)
27460#define CSI_CSICR137_PIXEL_COUNTERS_MASK CSI_CR137_PIXEL_COUNTERS_MASK
27461#define CSI_CSICR137_PIXEL_COUNTERS_SHIFT CSI_CR137_PIXEL_COUNTERS_SHIFT
27462#define CSI_CSICR137_PIXEL_COUNTERS(x) CSI_CR137_PIXEL_COUNTERS(x)
27463#define CSI_CSICR138_PIXEL_COUNTERS_MASK CSI_CR138_PIXEL_COUNTERS_MASK
27464#define CSI_CSICR138_PIXEL_COUNTERS_SHIFT CSI_CR138_PIXEL_COUNTERS_SHIFT
27465#define CSI_CSICR138_PIXEL_COUNTERS(x) CSI_CR138_PIXEL_COUNTERS(x)
27466#define CSI_CSICR139_PIXEL_COUNTERS_MASK CSI_CR139_PIXEL_COUNTERS_MASK
27467#define CSI_CSICR139_PIXEL_COUNTERS_SHIFT CSI_CR139_PIXEL_COUNTERS_SHIFT
27468#define CSI_CSICR139_PIXEL_COUNTERS(x) CSI_CR139_PIXEL_COUNTERS(x)
27469#define CSI_CSICR140_PIXEL_COUNTERS_MASK CSI_CR140_PIXEL_COUNTERS_MASK
27470#define CSI_CSICR140_PIXEL_COUNTERS_SHIFT CSI_CR140_PIXEL_COUNTERS_SHIFT
27471#define CSI_CSICR140_PIXEL_COUNTERS(x) CSI_CR140_PIXEL_COUNTERS(x)
27472#define CSI_CSICR141_PIXEL_COUNTERS_MASK CSI_CR141_PIXEL_COUNTERS_MASK
27473#define CSI_CSICR141_PIXEL_COUNTERS_SHIFT CSI_CR141_PIXEL_COUNTERS_SHIFT
27474#define CSI_CSICR141_PIXEL_COUNTERS(x) CSI_CR141_PIXEL_COUNTERS(x)
27475#define CSI_CSICR142_PIXEL_COUNTERS_MASK CSI_CR142_PIXEL_COUNTERS_MASK
27476#define CSI_CSICR142_PIXEL_COUNTERS_SHIFT CSI_CR142_PIXEL_COUNTERS_SHIFT
27477#define CSI_CSICR142_PIXEL_COUNTERS(x) CSI_CR142_PIXEL_COUNTERS(x)
27478#define CSI_CSICR143_PIXEL_COUNTERS_MASK CSI_CR143_PIXEL_COUNTERS_MASK
27479#define CSI_CSICR143_PIXEL_COUNTERS_SHIFT CSI_CR143_PIXEL_COUNTERS_SHIFT
27480#define CSI_CSICR143_PIXEL_COUNTERS(x) CSI_CR143_PIXEL_COUNTERS(x)
27481#define CSI_CSICR144_PIXEL_COUNTERS_MASK CSI_CR144_PIXEL_COUNTERS_MASK
27482#define CSI_CSICR144_PIXEL_COUNTERS_SHIFT CSI_CR144_PIXEL_COUNTERS_SHIFT
27483#define CSI_CSICR144_PIXEL_COUNTERS(x) CSI_CR144_PIXEL_COUNTERS(x)
27484#define CSI_CSICR145_PIXEL_COUNTERS_MASK CSI_CR145_PIXEL_COUNTERS_MASK
27485#define CSI_CSICR145_PIXEL_COUNTERS_SHIFT CSI_CR145_PIXEL_COUNTERS_SHIFT
27486#define CSI_CSICR145_PIXEL_COUNTERS(x) CSI_CR145_PIXEL_COUNTERS(x)
27487#define CSI_CSICR146_PIXEL_COUNTERS_MASK CSI_CR146_PIXEL_COUNTERS_MASK
27488#define CSI_CSICR146_PIXEL_COUNTERS_SHIFT CSI_CR146_PIXEL_COUNTERS_SHIFT
27489#define CSI_CSICR146_PIXEL_COUNTERS(x) CSI_CR146_PIXEL_COUNTERS(x)
27490#define CSI_CSICR147_PIXEL_COUNTERS_MASK CSI_CR147_PIXEL_COUNTERS_MASK
27491#define CSI_CSICR147_PIXEL_COUNTERS_SHIFT CSI_CR147_PIXEL_COUNTERS_SHIFT
27492#define CSI_CSICR147_PIXEL_COUNTERS(x) CSI_CR147_PIXEL_COUNTERS(x)
27493#define CSI_CSICR148_PIXEL_COUNTERS_MASK CSI_CR148_PIXEL_COUNTERS_MASK
27494#define CSI_CSICR148_PIXEL_COUNTERS_SHIFT CSI_CR148_PIXEL_COUNTERS_SHIFT
27495#define CSI_CSICR148_PIXEL_COUNTERS(x) CSI_CR148_PIXEL_COUNTERS(x)
27496#define CSI_CSICR149_PIXEL_COUNTERS_MASK CSI_CR149_PIXEL_COUNTERS_MASK
27497#define CSI_CSICR149_PIXEL_COUNTERS_SHIFT CSI_CR149_PIXEL_COUNTERS_SHIFT
27498#define CSI_CSICR149_PIXEL_COUNTERS(x) CSI_CR149_PIXEL_COUNTERS(x)
27499#define CSI_CSICR150_PIXEL_COUNTERS_MASK CSI_CR150_PIXEL_COUNTERS_MASK
27500#define CSI_CSICR150_PIXEL_COUNTERS_SHIFT CSI_CR150_PIXEL_COUNTERS_SHIFT
27501#define CSI_CSICR150_PIXEL_COUNTERS(x) CSI_CR150_PIXEL_COUNTERS(x)
27502#define CSI_CSICR151_PIXEL_COUNTERS_MASK CSI_CR151_PIXEL_COUNTERS_MASK
27503#define CSI_CSICR151_PIXEL_COUNTERS_SHIFT CSI_CR151_PIXEL_COUNTERS_SHIFT
27504#define CSI_CSICR151_PIXEL_COUNTERS(x) CSI_CR151_PIXEL_COUNTERS(x)
27505#define CSI_CSICR152_PIXEL_COUNTERS_MASK CSI_CR152_PIXEL_COUNTERS_MASK
27506#define CSI_CSICR152_PIXEL_COUNTERS_SHIFT CSI_CR152_PIXEL_COUNTERS_SHIFT
27507#define CSI_CSICR152_PIXEL_COUNTERS(x) CSI_CR152_PIXEL_COUNTERS(x)
27508#define CSI_CSICR153_PIXEL_COUNTERS_MASK CSI_CR153_PIXEL_COUNTERS_MASK
27509#define CSI_CSICR153_PIXEL_COUNTERS_SHIFT CSI_CR153_PIXEL_COUNTERS_SHIFT
27510#define CSI_CSICR153_PIXEL_COUNTERS(x) CSI_CR153_PIXEL_COUNTERS(x)
27511#define CSI_CSICR154_PIXEL_COUNTERS_MASK CSI_CR154_PIXEL_COUNTERS_MASK
27512#define CSI_CSICR154_PIXEL_COUNTERS_SHIFT CSI_CR154_PIXEL_COUNTERS_SHIFT
27513#define CSI_CSICR154_PIXEL_COUNTERS(x) CSI_CR154_PIXEL_COUNTERS(x)
27514#define CSI_CSICR155_PIXEL_COUNTERS_MASK CSI_CR155_PIXEL_COUNTERS_MASK
27515#define CSI_CSICR155_PIXEL_COUNTERS_SHIFT CSI_CR155_PIXEL_COUNTERS_SHIFT
27516#define CSI_CSICR155_PIXEL_COUNTERS(x) CSI_CR155_PIXEL_COUNTERS(x)
27517#define CSI_CSICR156_PIXEL_COUNTERS_MASK CSI_CR156_PIXEL_COUNTERS_MASK
27518#define CSI_CSICR156_PIXEL_COUNTERS_SHIFT CSI_CR156_PIXEL_COUNTERS_SHIFT
27519#define CSI_CSICR156_PIXEL_COUNTERS(x) CSI_CR156_PIXEL_COUNTERS(x)
27520#define CSI_CSICR157_PIXEL_COUNTERS_MASK CSI_CR157_PIXEL_COUNTERS_MASK
27521#define CSI_CSICR157_PIXEL_COUNTERS_SHIFT CSI_CR157_PIXEL_COUNTERS_SHIFT
27522#define CSI_CSICR157_PIXEL_COUNTERS(x) CSI_CR157_PIXEL_COUNTERS(x)
27523#define CSI_CSICR158_PIXEL_COUNTERS_MASK CSI_CR158_PIXEL_COUNTERS_MASK
27524#define CSI_CSICR158_PIXEL_COUNTERS_SHIFT CSI_CR158_PIXEL_COUNTERS_SHIFT
27525#define CSI_CSICR158_PIXEL_COUNTERS(x) CSI_CR158_PIXEL_COUNTERS(x)
27526#define CSI_CSICR159_PIXEL_COUNTERS_MASK CSI_CR159_PIXEL_COUNTERS_MASK
27527#define CSI_CSICR159_PIXEL_COUNTERS_SHIFT CSI_CR159_PIXEL_COUNTERS_SHIFT
27528#define CSI_CSICR159_PIXEL_COUNTERS(x) CSI_CR159_PIXEL_COUNTERS(x)
27529#define CSI_CSICR160_PIXEL_COUNTERS_MASK CSI_CR160_PIXEL_COUNTERS_MASK
27530#define CSI_CSICR160_PIXEL_COUNTERS_SHIFT CSI_CR160_PIXEL_COUNTERS_SHIFT
27531#define CSI_CSICR160_PIXEL_COUNTERS(x) CSI_CR160_PIXEL_COUNTERS(x)
27532#define CSI_CSICR161_PIXEL_COUNTERS_MASK CSI_CR161_PIXEL_COUNTERS_MASK
27533#define CSI_CSICR161_PIXEL_COUNTERS_SHIFT CSI_CR161_PIXEL_COUNTERS_SHIFT
27534#define CSI_CSICR161_PIXEL_COUNTERS(x) CSI_CR161_PIXEL_COUNTERS(x)
27535#define CSI_CSICR162_PIXEL_COUNTERS_MASK CSI_CR162_PIXEL_COUNTERS_MASK
27536#define CSI_CSICR162_PIXEL_COUNTERS_SHIFT CSI_CR162_PIXEL_COUNTERS_SHIFT
27537#define CSI_CSICR162_PIXEL_COUNTERS(x) CSI_CR162_PIXEL_COUNTERS(x)
27538#define CSI_CSICR163_PIXEL_COUNTERS_MASK CSI_CR163_PIXEL_COUNTERS_MASK
27539#define CSI_CSICR163_PIXEL_COUNTERS_SHIFT CSI_CR163_PIXEL_COUNTERS_SHIFT
27540#define CSI_CSICR163_PIXEL_COUNTERS(x) CSI_CR163_PIXEL_COUNTERS(x)
27541#define CSI_CSICR164_PIXEL_COUNTERS_MASK CSI_CR164_PIXEL_COUNTERS_MASK
27542#define CSI_CSICR164_PIXEL_COUNTERS_SHIFT CSI_CR164_PIXEL_COUNTERS_SHIFT
27543#define CSI_CSICR164_PIXEL_COUNTERS(x) CSI_CR164_PIXEL_COUNTERS(x)
27544#define CSI_CSICR165_PIXEL_COUNTERS_MASK CSI_CR165_PIXEL_COUNTERS_MASK
27545#define CSI_CSICR165_PIXEL_COUNTERS_SHIFT CSI_CR165_PIXEL_COUNTERS_SHIFT
27546#define CSI_CSICR165_PIXEL_COUNTERS(x) CSI_CR165_PIXEL_COUNTERS(x)
27547#define CSI_CSICR166_PIXEL_COUNTERS_MASK CSI_CR166_PIXEL_COUNTERS_MASK
27548#define CSI_CSICR166_PIXEL_COUNTERS_SHIFT CSI_CR166_PIXEL_COUNTERS_SHIFT
27549#define CSI_CSICR166_PIXEL_COUNTERS(x) CSI_CR166_PIXEL_COUNTERS(x)
27550#define CSI_CSICR167_PIXEL_COUNTERS_MASK CSI_CR167_PIXEL_COUNTERS_MASK
27551#define CSI_CSICR167_PIXEL_COUNTERS_SHIFT CSI_CR167_PIXEL_COUNTERS_SHIFT
27552#define CSI_CSICR167_PIXEL_COUNTERS(x) CSI_CR167_PIXEL_COUNTERS(x)
27553#define CSI_CSICR168_PIXEL_COUNTERS_MASK CSI_CR168_PIXEL_COUNTERS_MASK
27554#define CSI_CSICR168_PIXEL_COUNTERS_SHIFT CSI_CR168_PIXEL_COUNTERS_SHIFT
27555#define CSI_CSICR168_PIXEL_COUNTERS(x) CSI_CR168_PIXEL_COUNTERS(x)
27556#define CSI_CSICR169_PIXEL_COUNTERS_MASK CSI_CR169_PIXEL_COUNTERS_MASK
27557#define CSI_CSICR169_PIXEL_COUNTERS_SHIFT CSI_CR169_PIXEL_COUNTERS_SHIFT
27558#define CSI_CSICR169_PIXEL_COUNTERS(x) CSI_CR169_PIXEL_COUNTERS(x)
27559#define CSI_CSICR170_PIXEL_COUNTERS_MASK CSI_CR170_PIXEL_COUNTERS_MASK
27560#define CSI_CSICR170_PIXEL_COUNTERS_SHIFT CSI_CR170_PIXEL_COUNTERS_SHIFT
27561#define CSI_CSICR170_PIXEL_COUNTERS(x) CSI_CR170_PIXEL_COUNTERS(x)
27562#define CSI_CSICR171_PIXEL_COUNTERS_MASK CSI_CR171_PIXEL_COUNTERS_MASK
27563#define CSI_CSICR171_PIXEL_COUNTERS_SHIFT CSI_CR171_PIXEL_COUNTERS_SHIFT
27564#define CSI_CSICR171_PIXEL_COUNTERS(x) CSI_CR171_PIXEL_COUNTERS(x)
27565#define CSI_CSICR172_PIXEL_COUNTERS_MASK CSI_CR172_PIXEL_COUNTERS_MASK
27566#define CSI_CSICR172_PIXEL_COUNTERS_SHIFT CSI_CR172_PIXEL_COUNTERS_SHIFT
27567#define CSI_CSICR172_PIXEL_COUNTERS(x) CSI_CR172_PIXEL_COUNTERS(x)
27568#define CSI_CSICR173_PIXEL_COUNTERS_MASK CSI_CR173_PIXEL_COUNTERS_MASK
27569#define CSI_CSICR173_PIXEL_COUNTERS_SHIFT CSI_CR173_PIXEL_COUNTERS_SHIFT
27570#define CSI_CSICR173_PIXEL_COUNTERS(x) CSI_CR173_PIXEL_COUNTERS(x)
27571#define CSI_CSICR174_PIXEL_COUNTERS_MASK CSI_CR174_PIXEL_COUNTERS_MASK
27572#define CSI_CSICR174_PIXEL_COUNTERS_SHIFT CSI_CR174_PIXEL_COUNTERS_SHIFT
27573#define CSI_CSICR174_PIXEL_COUNTERS(x) CSI_CR174_PIXEL_COUNTERS(x)
27574#define CSI_CSICR175_PIXEL_COUNTERS_MASK CSI_CR175_PIXEL_COUNTERS_MASK
27575#define CSI_CSICR175_PIXEL_COUNTERS_SHIFT CSI_CR175_PIXEL_COUNTERS_SHIFT
27576#define CSI_CSICR175_PIXEL_COUNTERS(x) CSI_CR175_PIXEL_COUNTERS(x)
27577#define CSI_CSICR176_PIXEL_COUNTERS_MASK CSI_CR176_PIXEL_COUNTERS_MASK
27578#define CSI_CSICR176_PIXEL_COUNTERS_SHIFT CSI_CR176_PIXEL_COUNTERS_SHIFT
27579#define CSI_CSICR176_PIXEL_COUNTERS(x) CSI_CR176_PIXEL_COUNTERS(x)
27580#define CSI_CSICR177_PIXEL_COUNTERS_MASK CSI_CR177_PIXEL_COUNTERS_MASK
27581#define CSI_CSICR177_PIXEL_COUNTERS_SHIFT CSI_CR177_PIXEL_COUNTERS_SHIFT
27582#define CSI_CSICR177_PIXEL_COUNTERS(x) CSI_CR177_PIXEL_COUNTERS(x)
27583#define CSI_CSICR178_PIXEL_COUNTERS_MASK CSI_CR178_PIXEL_COUNTERS_MASK
27584#define CSI_CSICR178_PIXEL_COUNTERS_SHIFT CSI_CR178_PIXEL_COUNTERS_SHIFT
27585#define CSI_CSICR178_PIXEL_COUNTERS(x) CSI_CR178_PIXEL_COUNTERS(x)
27586#define CSI_CSICR179_PIXEL_COUNTERS_MASK CSI_CR179_PIXEL_COUNTERS_MASK
27587#define CSI_CSICR179_PIXEL_COUNTERS_SHIFT CSI_CR179_PIXEL_COUNTERS_SHIFT
27588#define CSI_CSICR179_PIXEL_COUNTERS(x) CSI_CR179_PIXEL_COUNTERS(x)
27589#define CSI_CSICR180_PIXEL_COUNTERS_MASK CSI_CR180_PIXEL_COUNTERS_MASK
27590#define CSI_CSICR180_PIXEL_COUNTERS_SHIFT CSI_CR180_PIXEL_COUNTERS_SHIFT
27591#define CSI_CSICR180_PIXEL_COUNTERS(x) CSI_CR180_PIXEL_COUNTERS(x)
27592#define CSI_CSICR181_PIXEL_COUNTERS_MASK CSI_CR181_PIXEL_COUNTERS_MASK
27593#define CSI_CSICR181_PIXEL_COUNTERS_SHIFT CSI_CR181_PIXEL_COUNTERS_SHIFT
27594#define CSI_CSICR181_PIXEL_COUNTERS(x) CSI_CR181_PIXEL_COUNTERS(x)
27595#define CSI_CSICR182_PIXEL_COUNTERS_MASK CSI_CR182_PIXEL_COUNTERS_MASK
27596#define CSI_CSICR182_PIXEL_COUNTERS_SHIFT CSI_CR182_PIXEL_COUNTERS_SHIFT
27597#define CSI_CSICR182_PIXEL_COUNTERS(x) CSI_CR182_PIXEL_COUNTERS(x)
27598#define CSI_CSICR183_PIXEL_COUNTERS_MASK CSI_CR183_PIXEL_COUNTERS_MASK
27599#define CSI_CSICR183_PIXEL_COUNTERS_SHIFT CSI_CR183_PIXEL_COUNTERS_SHIFT
27600#define CSI_CSICR183_PIXEL_COUNTERS(x) CSI_CR183_PIXEL_COUNTERS(x)
27601#define CSI_CSICR184_PIXEL_COUNTERS_MASK CSI_CR184_PIXEL_COUNTERS_MASK
27602#define CSI_CSICR184_PIXEL_COUNTERS_SHIFT CSI_CR184_PIXEL_COUNTERS_SHIFT
27603#define CSI_CSICR184_PIXEL_COUNTERS(x) CSI_CR184_PIXEL_COUNTERS(x)
27604#define CSI_CSICR185_PIXEL_COUNTERS_MASK CSI_CR185_PIXEL_COUNTERS_MASK
27605#define CSI_CSICR185_PIXEL_COUNTERS_SHIFT CSI_CR185_PIXEL_COUNTERS_SHIFT
27606#define CSI_CSICR185_PIXEL_COUNTERS(x) CSI_CR185_PIXEL_COUNTERS(x)
27607#define CSI_CSICR186_PIXEL_COUNTERS_MASK CSI_CR186_PIXEL_COUNTERS_MASK
27608#define CSI_CSICR186_PIXEL_COUNTERS_SHIFT CSI_CR186_PIXEL_COUNTERS_SHIFT
27609#define CSI_CSICR186_PIXEL_COUNTERS(x) CSI_CR186_PIXEL_COUNTERS(x)
27610#define CSI_CSICR187_PIXEL_COUNTERS_MASK CSI_CR187_PIXEL_COUNTERS_MASK
27611#define CSI_CSICR187_PIXEL_COUNTERS_SHIFT CSI_CR187_PIXEL_COUNTERS_SHIFT
27612#define CSI_CSICR187_PIXEL_COUNTERS(x) CSI_CR187_PIXEL_COUNTERS(x)
27613#define CSI_CSICR188_PIXEL_COUNTERS_MASK CSI_CR188_PIXEL_COUNTERS_MASK
27614#define CSI_CSICR188_PIXEL_COUNTERS_SHIFT CSI_CR188_PIXEL_COUNTERS_SHIFT
27615#define CSI_CSICR188_PIXEL_COUNTERS(x) CSI_CR188_PIXEL_COUNTERS(x)
27616#define CSI_CSICR189_PIXEL_COUNTERS_MASK CSI_CR189_PIXEL_COUNTERS_MASK
27617#define CSI_CSICR189_PIXEL_COUNTERS_SHIFT CSI_CR189_PIXEL_COUNTERS_SHIFT
27618#define CSI_CSICR189_PIXEL_COUNTERS(x) CSI_CR189_PIXEL_COUNTERS(x)
27619#define CSI_CSICR190_PIXEL_COUNTERS_MASK CSI_CR190_PIXEL_COUNTERS_MASK
27620#define CSI_CSICR190_PIXEL_COUNTERS_SHIFT CSI_CR190_PIXEL_COUNTERS_SHIFT
27621#define CSI_CSICR190_PIXEL_COUNTERS(x) CSI_CR190_PIXEL_COUNTERS(x)
27622#define CSI_CSICR191_PIXEL_COUNTERS_MASK CSI_CR191_PIXEL_COUNTERS_MASK
27623#define CSI_CSICR191_PIXEL_COUNTERS_SHIFT CSI_CR191_PIXEL_COUNTERS_SHIFT
27624#define CSI_CSICR191_PIXEL_COUNTERS(x) CSI_CR191_PIXEL_COUNTERS(x)
27625#define CSI_CSICR192_PIXEL_COUNTERS_MASK CSI_CR192_PIXEL_COUNTERS_MASK
27626#define CSI_CSICR192_PIXEL_COUNTERS_SHIFT CSI_CR192_PIXEL_COUNTERS_SHIFT
27627#define CSI_CSICR192_PIXEL_COUNTERS(x) CSI_CR192_PIXEL_COUNTERS(x)
27628#define CSI_CSICR193_PIXEL_COUNTERS_MASK CSI_CR193_PIXEL_COUNTERS_MASK
27629#define CSI_CSICR193_PIXEL_COUNTERS_SHIFT CSI_CR193_PIXEL_COUNTERS_SHIFT
27630#define CSI_CSICR193_PIXEL_COUNTERS(x) CSI_CR193_PIXEL_COUNTERS(x)
27631#define CSI_CSICR194_PIXEL_COUNTERS_MASK CSI_CR194_PIXEL_COUNTERS_MASK
27632#define CSI_CSICR194_PIXEL_COUNTERS_SHIFT CSI_CR194_PIXEL_COUNTERS_SHIFT
27633#define CSI_CSICR194_PIXEL_COUNTERS(x) CSI_CR194_PIXEL_COUNTERS(x)
27634#define CSI_CSICR195_PIXEL_COUNTERS_MASK CSI_CR195_PIXEL_COUNTERS_MASK
27635#define CSI_CSICR195_PIXEL_COUNTERS_SHIFT CSI_CR195_PIXEL_COUNTERS_SHIFT
27636#define CSI_CSICR195_PIXEL_COUNTERS(x) CSI_CR195_PIXEL_COUNTERS(x)
27637#define CSI_CSICR196_PIXEL_COUNTERS_MASK CSI_CR196_PIXEL_COUNTERS_MASK
27638#define CSI_CSICR196_PIXEL_COUNTERS_SHIFT CSI_CR196_PIXEL_COUNTERS_SHIFT
27639#define CSI_CSICR196_PIXEL_COUNTERS(x) CSI_CR196_PIXEL_COUNTERS(x)
27640#define CSI_CSICR197_PIXEL_COUNTERS_MASK CSI_CR197_PIXEL_COUNTERS_MASK
27641#define CSI_CSICR197_PIXEL_COUNTERS_SHIFT CSI_CR197_PIXEL_COUNTERS_SHIFT
27642#define CSI_CSICR197_PIXEL_COUNTERS(x) CSI_CR197_PIXEL_COUNTERS(x)
27643#define CSI_CSICR198_PIXEL_COUNTERS_MASK CSI_CR198_PIXEL_COUNTERS_MASK
27644#define CSI_CSICR198_PIXEL_COUNTERS_SHIFT CSI_CR198_PIXEL_COUNTERS_SHIFT
27645#define CSI_CSICR198_PIXEL_COUNTERS(x) CSI_CR198_PIXEL_COUNTERS(x)
27646#define CSI_CSICR199_PIXEL_COUNTERS_MASK CSI_CR199_PIXEL_COUNTERS_MASK
27647#define CSI_CSICR199_PIXEL_COUNTERS_SHIFT CSI_CR199_PIXEL_COUNTERS_SHIFT
27648#define CSI_CSICR199_PIXEL_COUNTERS(x) CSI_CR199_PIXEL_COUNTERS(x)
27649#define CSI_CSICR200_PIXEL_COUNTERS_MASK CSI_CR200_PIXEL_COUNTERS_MASK
27650#define CSI_CSICR200_PIXEL_COUNTERS_SHIFT CSI_CR200_PIXEL_COUNTERS_SHIFT
27651#define CSI_CSICR200_PIXEL_COUNTERS(x) CSI_CR200_PIXEL_COUNTERS(x)
27652#define CSI_CSICR201_PIXEL_COUNTERS_MASK CSI_CR201_PIXEL_COUNTERS_MASK
27653#define CSI_CSICR201_PIXEL_COUNTERS_SHIFT CSI_CR201_PIXEL_COUNTERS_SHIFT
27654#define CSI_CSICR201_PIXEL_COUNTERS(x) CSI_CR201_PIXEL_COUNTERS(x)
27655#define CSI_CSICR202_PIXEL_COUNTERS_MASK CSI_CR202_PIXEL_COUNTERS_MASK
27656#define CSI_CSICR202_PIXEL_COUNTERS_SHIFT CSI_CR202_PIXEL_COUNTERS_SHIFT
27657#define CSI_CSICR202_PIXEL_COUNTERS(x) CSI_CR202_PIXEL_COUNTERS(x)
27658#define CSI_CSICR203_PIXEL_COUNTERS_MASK CSI_CR203_PIXEL_COUNTERS_MASK
27659#define CSI_CSICR203_PIXEL_COUNTERS_SHIFT CSI_CR203_PIXEL_COUNTERS_SHIFT
27660#define CSI_CSICR203_PIXEL_COUNTERS(x) CSI_CR203_PIXEL_COUNTERS(x)
27661#define CSI_CSICR204_PIXEL_COUNTERS_MASK CSI_CR204_PIXEL_COUNTERS_MASK
27662#define CSI_CSICR204_PIXEL_COUNTERS_SHIFT CSI_CR204_PIXEL_COUNTERS_SHIFT
27663#define CSI_CSICR204_PIXEL_COUNTERS(x) CSI_CR204_PIXEL_COUNTERS(x)
27664#define CSI_CSICR205_PIXEL_COUNTERS_MASK CSI_CR205_PIXEL_COUNTERS_MASK
27665#define CSI_CSICR205_PIXEL_COUNTERS_SHIFT CSI_CR205_PIXEL_COUNTERS_SHIFT
27666#define CSI_CSICR205_PIXEL_COUNTERS(x) CSI_CR205_PIXEL_COUNTERS(x)
27667#define CSI_CSICR206_PIXEL_COUNTERS_MASK CSI_CR206_PIXEL_COUNTERS_MASK
27668#define CSI_CSICR206_PIXEL_COUNTERS_SHIFT CSI_CR206_PIXEL_COUNTERS_SHIFT
27669#define CSI_CSICR206_PIXEL_COUNTERS(x) CSI_CR206_PIXEL_COUNTERS(x)
27670#define CSI_CSICR207_PIXEL_COUNTERS_MASK CSI_CR207_PIXEL_COUNTERS_MASK
27671#define CSI_CSICR207_PIXEL_COUNTERS_SHIFT CSI_CR207_PIXEL_COUNTERS_SHIFT
27672#define CSI_CSICR207_PIXEL_COUNTERS(x) CSI_CR207_PIXEL_COUNTERS(x)
27673#define CSI_CSICR208_PIXEL_COUNTERS_MASK CSI_CR208_PIXEL_COUNTERS_MASK
27674#define CSI_CSICR208_PIXEL_COUNTERS_SHIFT CSI_CR208_PIXEL_COUNTERS_SHIFT
27675#define CSI_CSICR208_PIXEL_COUNTERS(x) CSI_CR208_PIXEL_COUNTERS(x)
27676#define CSI_CSICR209_PIXEL_COUNTERS_MASK CSI_CR209_PIXEL_COUNTERS_MASK
27677#define CSI_CSICR209_PIXEL_COUNTERS_SHIFT CSI_CR209_PIXEL_COUNTERS_SHIFT
27678#define CSI_CSICR209_PIXEL_COUNTERS(x) CSI_CR209_PIXEL_COUNTERS(x)
27679#define CSI_CSICR210_PIXEL_COUNTERS_MASK CSI_CR210_PIXEL_COUNTERS_MASK
27680#define CSI_CSICR210_PIXEL_COUNTERS_SHIFT CSI_CR210_PIXEL_COUNTERS_SHIFT
27681#define CSI_CSICR210_PIXEL_COUNTERS(x) CSI_CR210_PIXEL_COUNTERS(x)
27682#define CSI_CSICR211_PIXEL_COUNTERS_MASK CSI_CR211_PIXEL_COUNTERS_MASK
27683#define CSI_CSICR211_PIXEL_COUNTERS_SHIFT CSI_CR211_PIXEL_COUNTERS_SHIFT
27684#define CSI_CSICR211_PIXEL_COUNTERS(x) CSI_CR211_PIXEL_COUNTERS(x)
27685#define CSI_CSICR212_PIXEL_COUNTERS_MASK CSI_CR212_PIXEL_COUNTERS_MASK
27686#define CSI_CSICR212_PIXEL_COUNTERS_SHIFT CSI_CR212_PIXEL_COUNTERS_SHIFT
27687#define CSI_CSICR212_PIXEL_COUNTERS(x) CSI_CR212_PIXEL_COUNTERS(x)
27688#define CSI_CSICR213_PIXEL_COUNTERS_MASK CSI_CR213_PIXEL_COUNTERS_MASK
27689#define CSI_CSICR213_PIXEL_COUNTERS_SHIFT CSI_CR213_PIXEL_COUNTERS_SHIFT
27690#define CSI_CSICR213_PIXEL_COUNTERS(x) CSI_CR213_PIXEL_COUNTERS(x)
27691#define CSI_CSICR214_PIXEL_COUNTERS_MASK CSI_CR214_PIXEL_COUNTERS_MASK
27692#define CSI_CSICR214_PIXEL_COUNTERS_SHIFT CSI_CR214_PIXEL_COUNTERS_SHIFT
27693#define CSI_CSICR214_PIXEL_COUNTERS(x) CSI_CR214_PIXEL_COUNTERS(x)
27694#define CSI_CSICR215_PIXEL_COUNTERS_MASK CSI_CR215_PIXEL_COUNTERS_MASK
27695#define CSI_CSICR215_PIXEL_COUNTERS_SHIFT CSI_CR215_PIXEL_COUNTERS_SHIFT
27696#define CSI_CSICR215_PIXEL_COUNTERS(x) CSI_CR215_PIXEL_COUNTERS(x)
27697#define CSI_CSICR216_PIXEL_COUNTERS_MASK CSI_CR216_PIXEL_COUNTERS_MASK
27698#define CSI_CSICR216_PIXEL_COUNTERS_SHIFT CSI_CR216_PIXEL_COUNTERS_SHIFT
27699#define CSI_CSICR216_PIXEL_COUNTERS(x) CSI_CR216_PIXEL_COUNTERS(x)
27700#define CSI_CSICR217_PIXEL_COUNTERS_MASK CSI_CR217_PIXEL_COUNTERS_MASK
27701#define CSI_CSICR217_PIXEL_COUNTERS_SHIFT CSI_CR217_PIXEL_COUNTERS_SHIFT
27702#define CSI_CSICR217_PIXEL_COUNTERS(x) CSI_CR217_PIXEL_COUNTERS(x)
27703#define CSI_CSICR218_PIXEL_COUNTERS_MASK CSI_CR218_PIXEL_COUNTERS_MASK
27704#define CSI_CSICR218_PIXEL_COUNTERS_SHIFT CSI_CR218_PIXEL_COUNTERS_SHIFT
27705#define CSI_CSICR218_PIXEL_COUNTERS(x) CSI_CR218_PIXEL_COUNTERS(x)
27706#define CSI_CSICR219_PIXEL_COUNTERS_MASK CSI_CR219_PIXEL_COUNTERS_MASK
27707#define CSI_CSICR219_PIXEL_COUNTERS_SHIFT CSI_CR219_PIXEL_COUNTERS_SHIFT
27708#define CSI_CSICR219_PIXEL_COUNTERS(x) CSI_CR219_PIXEL_COUNTERS(x)
27709#define CSI_CSICR220_PIXEL_COUNTERS_MASK CSI_CR220_PIXEL_COUNTERS_MASK
27710#define CSI_CSICR220_PIXEL_COUNTERS_SHIFT CSI_CR220_PIXEL_COUNTERS_SHIFT
27711#define CSI_CSICR220_PIXEL_COUNTERS(x) CSI_CR220_PIXEL_COUNTERS(x)
27712#define CSI_CSICR221_PIXEL_COUNTERS_MASK CSI_CR221_PIXEL_COUNTERS_MASK
27713#define CSI_CSICR221_PIXEL_COUNTERS_SHIFT CSI_CR221_PIXEL_COUNTERS_SHIFT
27714#define CSI_CSICR221_PIXEL_COUNTERS(x) CSI_CR221_PIXEL_COUNTERS(x)
27715#define CSI_CSICR222_PIXEL_COUNTERS_MASK CSI_CR222_PIXEL_COUNTERS_MASK
27716#define CSI_CSICR222_PIXEL_COUNTERS_SHIFT CSI_CR222_PIXEL_COUNTERS_SHIFT
27717#define CSI_CSICR222_PIXEL_COUNTERS(x) CSI_CR222_PIXEL_COUNTERS(x)
27718#define CSI_CSICR223_PIXEL_COUNTERS_MASK CSI_CR223_PIXEL_COUNTERS_MASK
27719#define CSI_CSICR223_PIXEL_COUNTERS_SHIFT CSI_CR223_PIXEL_COUNTERS_SHIFT
27720#define CSI_CSICR223_PIXEL_COUNTERS(x) CSI_CR223_PIXEL_COUNTERS(x)
27721#define CSI_CSICR224_PIXEL_COUNTERS_MASK CSI_CR224_PIXEL_COUNTERS_MASK
27722#define CSI_CSICR224_PIXEL_COUNTERS_SHIFT CSI_CR224_PIXEL_COUNTERS_SHIFT
27723#define CSI_CSICR224_PIXEL_COUNTERS(x) CSI_CR224_PIXEL_COUNTERS(x)
27724#define CSI_CSICR225_PIXEL_COUNTERS_MASK CSI_CR225_PIXEL_COUNTERS_MASK
27725#define CSI_CSICR225_PIXEL_COUNTERS_SHIFT CSI_CR225_PIXEL_COUNTERS_SHIFT
27726#define CSI_CSICR225_PIXEL_COUNTERS(x) CSI_CR225_PIXEL_COUNTERS(x)
27727#define CSI_CSICR226_PIXEL_COUNTERS_MASK CSI_CR226_PIXEL_COUNTERS_MASK
27728#define CSI_CSICR226_PIXEL_COUNTERS_SHIFT CSI_CR226_PIXEL_COUNTERS_SHIFT
27729#define CSI_CSICR226_PIXEL_COUNTERS(x) CSI_CR226_PIXEL_COUNTERS(x)
27730#define CSI_CSICR227_PIXEL_COUNTERS_MASK CSI_CR227_PIXEL_COUNTERS_MASK
27731#define CSI_CSICR227_PIXEL_COUNTERS_SHIFT CSI_CR227_PIXEL_COUNTERS_SHIFT
27732#define CSI_CSICR227_PIXEL_COUNTERS(x) CSI_CR227_PIXEL_COUNTERS(x)
27733#define CSI_CSICR228_PIXEL_COUNTERS_MASK CSI_CR228_PIXEL_COUNTERS_MASK
27734#define CSI_CSICR228_PIXEL_COUNTERS_SHIFT CSI_CR228_PIXEL_COUNTERS_SHIFT
27735#define CSI_CSICR228_PIXEL_COUNTERS(x) CSI_CR228_PIXEL_COUNTERS(x)
27736#define CSI_CSICR229_PIXEL_COUNTERS_MASK CSI_CR229_PIXEL_COUNTERS_MASK
27737#define CSI_CSICR229_PIXEL_COUNTERS_SHIFT CSI_CR229_PIXEL_COUNTERS_SHIFT
27738#define CSI_CSICR229_PIXEL_COUNTERS(x) CSI_CR229_PIXEL_COUNTERS(x)
27739#define CSI_CSICR230_PIXEL_COUNTERS_MASK CSI_CR230_PIXEL_COUNTERS_MASK
27740#define CSI_CSICR230_PIXEL_COUNTERS_SHIFT CSI_CR230_PIXEL_COUNTERS_SHIFT
27741#define CSI_CSICR230_PIXEL_COUNTERS(x) CSI_CR230_PIXEL_COUNTERS(x)
27742#define CSI_CSICR231_PIXEL_COUNTERS_MASK CSI_CR231_PIXEL_COUNTERS_MASK
27743#define CSI_CSICR231_PIXEL_COUNTERS_SHIFT CSI_CR231_PIXEL_COUNTERS_SHIFT
27744#define CSI_CSICR231_PIXEL_COUNTERS(x) CSI_CR231_PIXEL_COUNTERS(x)
27745#define CSI_CSICR232_PIXEL_COUNTERS_MASK CSI_CR232_PIXEL_COUNTERS_MASK
27746#define CSI_CSICR232_PIXEL_COUNTERS_SHIFT CSI_CR232_PIXEL_COUNTERS_SHIFT
27747#define CSI_CSICR232_PIXEL_COUNTERS(x) CSI_CR232_PIXEL_COUNTERS(x)
27748#define CSI_CSICR233_PIXEL_COUNTERS_MASK CSI_CR233_PIXEL_COUNTERS_MASK
27749#define CSI_CSICR233_PIXEL_COUNTERS_SHIFT CSI_CR233_PIXEL_COUNTERS_SHIFT
27750#define CSI_CSICR233_PIXEL_COUNTERS(x) CSI_CR233_PIXEL_COUNTERS(x)
27751#define CSI_CSICR234_PIXEL_COUNTERS_MASK CSI_CR234_PIXEL_COUNTERS_MASK
27752#define CSI_CSICR234_PIXEL_COUNTERS_SHIFT CSI_CR234_PIXEL_COUNTERS_SHIFT
27753#define CSI_CSICR234_PIXEL_COUNTERS(x) CSI_CR234_PIXEL_COUNTERS(x)
27754#define CSI_CSICR235_PIXEL_COUNTERS_MASK CSI_CR235_PIXEL_COUNTERS_MASK
27755#define CSI_CSICR235_PIXEL_COUNTERS_SHIFT CSI_CR235_PIXEL_COUNTERS_SHIFT
27756#define CSI_CSICR235_PIXEL_COUNTERS(x) CSI_CR235_PIXEL_COUNTERS(x)
27757#define CSI_CSICR236_PIXEL_COUNTERS_MASK CSI_CR236_PIXEL_COUNTERS_MASK
27758#define CSI_CSICR236_PIXEL_COUNTERS_SHIFT CSI_CR236_PIXEL_COUNTERS_SHIFT
27759#define CSI_CSICR236_PIXEL_COUNTERS(x) CSI_CR236_PIXEL_COUNTERS(x)
27760#define CSI_CSICR237_PIXEL_COUNTERS_MASK CSI_CR237_PIXEL_COUNTERS_MASK
27761#define CSI_CSICR237_PIXEL_COUNTERS_SHIFT CSI_CR237_PIXEL_COUNTERS_SHIFT
27762#define CSI_CSICR237_PIXEL_COUNTERS(x) CSI_CR237_PIXEL_COUNTERS(x)
27763#define CSI_CSICR238_PIXEL_COUNTERS_MASK CSI_CR238_PIXEL_COUNTERS_MASK
27764#define CSI_CSICR238_PIXEL_COUNTERS_SHIFT CSI_CR238_PIXEL_COUNTERS_SHIFT
27765#define CSI_CSICR238_PIXEL_COUNTERS(x) CSI_CR238_PIXEL_COUNTERS(x)
27766#define CSI_CSICR239_PIXEL_COUNTERS_MASK CSI_CR239_PIXEL_COUNTERS_MASK
27767#define CSI_CSICR239_PIXEL_COUNTERS_SHIFT CSI_CR239_PIXEL_COUNTERS_SHIFT
27768#define CSI_CSICR239_PIXEL_COUNTERS(x) CSI_CR239_PIXEL_COUNTERS(x)
27769#define CSI_CSICR240_PIXEL_COUNTERS_MASK CSI_CR240_PIXEL_COUNTERS_MASK
27770#define CSI_CSICR240_PIXEL_COUNTERS_SHIFT CSI_CR240_PIXEL_COUNTERS_SHIFT
27771#define CSI_CSICR240_PIXEL_COUNTERS(x) CSI_CR240_PIXEL_COUNTERS(x)
27772#define CSI_CSICR241_PIXEL_COUNTERS_MASK CSI_CR241_PIXEL_COUNTERS_MASK
27773#define CSI_CSICR241_PIXEL_COUNTERS_SHIFT CSI_CR241_PIXEL_COUNTERS_SHIFT
27774#define CSI_CSICR241_PIXEL_COUNTERS(x) CSI_CR241_PIXEL_COUNTERS(x)
27775#define CSI_CSICR242_PIXEL_COUNTERS_MASK CSI_CR242_PIXEL_COUNTERS_MASK
27776#define CSI_CSICR242_PIXEL_COUNTERS_SHIFT CSI_CR242_PIXEL_COUNTERS_SHIFT
27777#define CSI_CSICR242_PIXEL_COUNTERS(x) CSI_CR242_PIXEL_COUNTERS(x)
27778#define CSI_CSICR243_PIXEL_COUNTERS_MASK CSI_CR243_PIXEL_COUNTERS_MASK
27779#define CSI_CSICR243_PIXEL_COUNTERS_SHIFT CSI_CR243_PIXEL_COUNTERS_SHIFT
27780#define CSI_CSICR243_PIXEL_COUNTERS(x) CSI_CR243_PIXEL_COUNTERS(x)
27781#define CSI_CSICR244_PIXEL_COUNTERS_MASK CSI_CR244_PIXEL_COUNTERS_MASK
27782#define CSI_CSICR244_PIXEL_COUNTERS_SHIFT CSI_CR244_PIXEL_COUNTERS_SHIFT
27783#define CSI_CSICR244_PIXEL_COUNTERS(x) CSI_CR244_PIXEL_COUNTERS(x)
27784#define CSI_CSICR245_PIXEL_COUNTERS_MASK CSI_CR245_PIXEL_COUNTERS_MASK
27785#define CSI_CSICR245_PIXEL_COUNTERS_SHIFT CSI_CR245_PIXEL_COUNTERS_SHIFT
27786#define CSI_CSICR245_PIXEL_COUNTERS(x) CSI_CR245_PIXEL_COUNTERS(x)
27787#define CSI_CSICR246_PIXEL_COUNTERS_MASK CSI_CR246_PIXEL_COUNTERS_MASK
27788#define CSI_CSICR246_PIXEL_COUNTERS_SHIFT CSI_CR246_PIXEL_COUNTERS_SHIFT
27789#define CSI_CSICR246_PIXEL_COUNTERS(x) CSI_CR246_PIXEL_COUNTERS(x)
27790#define CSI_CSICR247_PIXEL_COUNTERS_MASK CSI_CR247_PIXEL_COUNTERS_MASK
27791#define CSI_CSICR247_PIXEL_COUNTERS_SHIFT CSI_CR247_PIXEL_COUNTERS_SHIFT
27792#define CSI_CSICR247_PIXEL_COUNTERS(x) CSI_CR247_PIXEL_COUNTERS(x)
27793#define CSI_CSICR248_PIXEL_COUNTERS_MASK CSI_CR248_PIXEL_COUNTERS_MASK
27794#define CSI_CSICR248_PIXEL_COUNTERS_SHIFT CSI_CR248_PIXEL_COUNTERS_SHIFT
27795#define CSI_CSICR248_PIXEL_COUNTERS(x) CSI_CR248_PIXEL_COUNTERS(x)
27796#define CSI_CSICR249_PIXEL_COUNTERS_MASK CSI_CR249_PIXEL_COUNTERS_MASK
27797#define CSI_CSICR249_PIXEL_COUNTERS_SHIFT CSI_CR249_PIXEL_COUNTERS_SHIFT
27798#define CSI_CSICR249_PIXEL_COUNTERS(x) CSI_CR249_PIXEL_COUNTERS(x)
27799#define CSI_CSICR250_PIXEL_COUNTERS_MASK CSI_CR250_PIXEL_COUNTERS_MASK
27800#define CSI_CSICR250_PIXEL_COUNTERS_SHIFT CSI_CR250_PIXEL_COUNTERS_SHIFT
27801#define CSI_CSICR250_PIXEL_COUNTERS(x) CSI_CR250_PIXEL_COUNTERS(x)
27802#define CSI_CSICR251_PIXEL_COUNTERS_MASK CSI_CR251_PIXEL_COUNTERS_MASK
27803#define CSI_CSICR251_PIXEL_COUNTERS_SHIFT CSI_CR251_PIXEL_COUNTERS_SHIFT
27804#define CSI_CSICR251_PIXEL_COUNTERS(x) CSI_CR251_PIXEL_COUNTERS(x)
27805#define CSI_CSICR252_PIXEL_COUNTERS_MASK CSI_CR252_PIXEL_COUNTERS_MASK
27806#define CSI_CSICR252_PIXEL_COUNTERS_SHIFT CSI_CR252_PIXEL_COUNTERS_SHIFT
27807#define CSI_CSICR252_PIXEL_COUNTERS(x) CSI_CR252_PIXEL_COUNTERS(x)
27808#define CSI_CSICR253_PIXEL_COUNTERS_MASK CSI_CR253_PIXEL_COUNTERS_MASK
27809#define CSI_CSICR253_PIXEL_COUNTERS_SHIFT CSI_CR253_PIXEL_COUNTERS_SHIFT
27810#define CSI_CSICR253_PIXEL_COUNTERS(x) CSI_CR253_PIXEL_COUNTERS(x)
27811#define CSI_CSICR254_PIXEL_COUNTERS_MASK CSI_CR254_PIXEL_COUNTERS_MASK
27812#define CSI_CSICR254_PIXEL_COUNTERS_SHIFT CSI_CR254_PIXEL_COUNTERS_SHIFT
27813#define CSI_CSICR254_PIXEL_COUNTERS(x) CSI_CR254_PIXEL_COUNTERS(x)
27814#define CSI_CSICR255_PIXEL_COUNTERS_MASK CSI_CR255_PIXEL_COUNTERS_MASK
27815#define CSI_CSICR255_PIXEL_COUNTERS_SHIFT CSI_CR255_PIXEL_COUNTERS_SHIFT
27816#define CSI_CSICR255_PIXEL_COUNTERS(x) CSI_CR255_PIXEL_COUNTERS(x)
27817#define CSI_CSICR256_PIXEL_COUNTERS_MASK CSI_CR256_PIXEL_COUNTERS_MASK
27818#define CSI_CSICR256_PIXEL_COUNTERS_SHIFT CSI_CR256_PIXEL_COUNTERS_SHIFT
27819#define CSI_CSICR256_PIXEL_COUNTERS(x) CSI_CR256_PIXEL_COUNTERS(x)
27820#define CSI_CSICR257_PIXEL_COUNTERS_MASK CSI_CR257_PIXEL_COUNTERS_MASK
27821#define CSI_CSICR257_PIXEL_COUNTERS_SHIFT CSI_CR257_PIXEL_COUNTERS_SHIFT
27822#define CSI_CSICR257_PIXEL_COUNTERS(x) CSI_CR257_PIXEL_COUNTERS(x)
27823#define CSI_CSICR258_PIXEL_COUNTERS_MASK CSI_CR258_PIXEL_COUNTERS_MASK
27824#define CSI_CSICR258_PIXEL_COUNTERS_SHIFT CSI_CR258_PIXEL_COUNTERS_SHIFT
27825#define CSI_CSICR258_PIXEL_COUNTERS(x) CSI_CR258_PIXEL_COUNTERS(x)
27826#define CSI_CSICR259_PIXEL_COUNTERS_MASK CSI_CR259_PIXEL_COUNTERS_MASK
27827#define CSI_CSICR259_PIXEL_COUNTERS_SHIFT CSI_CR259_PIXEL_COUNTERS_SHIFT
27828#define CSI_CSICR259_PIXEL_COUNTERS(x) CSI_CR259_PIXEL_COUNTERS(x)
27829#define CSI_CSICR260_PIXEL_COUNTERS_MASK CSI_CR260_PIXEL_COUNTERS_MASK
27830#define CSI_CSICR260_PIXEL_COUNTERS_SHIFT CSI_CR260_PIXEL_COUNTERS_SHIFT
27831#define CSI_CSICR260_PIXEL_COUNTERS(x) CSI_CR260_PIXEL_COUNTERS(x)
27832#define CSI_CSICR261_PIXEL_COUNTERS_MASK CSI_CR261_PIXEL_COUNTERS_MASK
27833#define CSI_CSICR261_PIXEL_COUNTERS_SHIFT CSI_CR261_PIXEL_COUNTERS_SHIFT
27834#define CSI_CSICR261_PIXEL_COUNTERS(x) CSI_CR261_PIXEL_COUNTERS(x)
27835#define CSI_CSICR262_PIXEL_COUNTERS_MASK CSI_CR262_PIXEL_COUNTERS_MASK
27836#define CSI_CSICR262_PIXEL_COUNTERS_SHIFT CSI_CR262_PIXEL_COUNTERS_SHIFT
27837#define CSI_CSICR262_PIXEL_COUNTERS(x) CSI_CR262_PIXEL_COUNTERS(x)
27838#define CSI_CSICR263_PIXEL_COUNTERS_MASK CSI_CR263_PIXEL_COUNTERS_MASK
27839#define CSI_CSICR263_PIXEL_COUNTERS_SHIFT CSI_CR263_PIXEL_COUNTERS_SHIFT
27840#define CSI_CSICR263_PIXEL_COUNTERS(x) CSI_CR263_PIXEL_COUNTERS(x)
27841#define CSI_CSICR264_PIXEL_COUNTERS_MASK CSI_CR264_PIXEL_COUNTERS_MASK
27842#define CSI_CSICR264_PIXEL_COUNTERS_SHIFT CSI_CR264_PIXEL_COUNTERS_SHIFT
27843#define CSI_CSICR264_PIXEL_COUNTERS(x) CSI_CR264_PIXEL_COUNTERS(x)
27844#define CSI_CSICR265_PIXEL_COUNTERS_MASK CSI_CR265_PIXEL_COUNTERS_MASK
27845#define CSI_CSICR265_PIXEL_COUNTERS_SHIFT CSI_CR265_PIXEL_COUNTERS_SHIFT
27846#define CSI_CSICR265_PIXEL_COUNTERS(x) CSI_CR265_PIXEL_COUNTERS(x)
27847#define CSI_CSICR266_PIXEL_COUNTERS_MASK CSI_CR266_PIXEL_COUNTERS_MASK
27848#define CSI_CSICR266_PIXEL_COUNTERS_SHIFT CSI_CR266_PIXEL_COUNTERS_SHIFT
27849#define CSI_CSICR266_PIXEL_COUNTERS(x) CSI_CR266_PIXEL_COUNTERS(x)
27850#define CSI_CSICR267_PIXEL_COUNTERS_MASK CSI_CR267_PIXEL_COUNTERS_MASK
27851#define CSI_CSICR267_PIXEL_COUNTERS_SHIFT CSI_CR267_PIXEL_COUNTERS_SHIFT
27852#define CSI_CSICR267_PIXEL_COUNTERS(x) CSI_CR267_PIXEL_COUNTERS(x)
27853#define CSI_CSICR268_PIXEL_COUNTERS_MASK CSI_CR268_PIXEL_COUNTERS_MASK
27854#define CSI_CSICR268_PIXEL_COUNTERS_SHIFT CSI_CR268_PIXEL_COUNTERS_SHIFT
27855#define CSI_CSICR268_PIXEL_COUNTERS(x) CSI_CR268_PIXEL_COUNTERS(x)
27856#define CSI_CSICR269_PIXEL_COUNTERS_MASK CSI_CR269_PIXEL_COUNTERS_MASK
27857#define CSI_CSICR269_PIXEL_COUNTERS_SHIFT CSI_CR269_PIXEL_COUNTERS_SHIFT
27858#define CSI_CSICR269_PIXEL_COUNTERS(x) CSI_CR269_PIXEL_COUNTERS(x)
27859#define CSI_CSICR270_PIXEL_COUNTERS_MASK CSI_CR270_PIXEL_COUNTERS_MASK
27860#define CSI_CSICR270_PIXEL_COUNTERS_SHIFT CSI_CR270_PIXEL_COUNTERS_SHIFT
27861#define CSI_CSICR270_PIXEL_COUNTERS(x) CSI_CR270_PIXEL_COUNTERS(x)
27862#define CSI_CSICR271_PIXEL_COUNTERS_MASK CSI_CR271_PIXEL_COUNTERS_MASK
27863#define CSI_CSICR271_PIXEL_COUNTERS_SHIFT CSI_CR271_PIXEL_COUNTERS_SHIFT
27864#define CSI_CSICR271_PIXEL_COUNTERS(x) CSI_CR271_PIXEL_COUNTERS(x)
27865#define CSI_CSICR272_PIXEL_COUNTERS_MASK CSI_CR272_PIXEL_COUNTERS_MASK
27866#define CSI_CSICR272_PIXEL_COUNTERS_SHIFT CSI_CR272_PIXEL_COUNTERS_SHIFT
27867#define CSI_CSICR272_PIXEL_COUNTERS(x) CSI_CR272_PIXEL_COUNTERS(x)
27868#define CSI_CSICR273_PIXEL_COUNTERS_MASK CSI_CR273_PIXEL_COUNTERS_MASK
27869#define CSI_CSICR273_PIXEL_COUNTERS_SHIFT CSI_CR273_PIXEL_COUNTERS_SHIFT
27870#define CSI_CSICR273_PIXEL_COUNTERS(x) CSI_CR273_PIXEL_COUNTERS(x)
27871#define CSI_CSICR274_PIXEL_COUNTERS_MASK CSI_CR274_PIXEL_COUNTERS_MASK
27872#define CSI_CSICR274_PIXEL_COUNTERS_SHIFT CSI_CR274_PIXEL_COUNTERS_SHIFT
27873#define CSI_CSICR274_PIXEL_COUNTERS(x) CSI_CR274_PIXEL_COUNTERS(x)
27874#define CSI_CSICR275_PIXEL_COUNTERS_MASK CSI_CR275_PIXEL_COUNTERS_MASK
27875#define CSI_CSICR275_PIXEL_COUNTERS_SHIFT CSI_CR275_PIXEL_COUNTERS_SHIFT
27876#define CSI_CSICR275_PIXEL_COUNTERS(x) CSI_CR275_PIXEL_COUNTERS(x)
27877#define CSI_CSICR276_PIXEL_COUNTERS_MASK CSI_CR276_PIXEL_COUNTERS_MASK
27878#define CSI_CSICR276_PIXEL_COUNTERS_SHIFT CSI_CR276_PIXEL_COUNTERS_SHIFT
27879#define CSI_CSICR276_PIXEL_COUNTERS(x) CSI_CR276_PIXEL_COUNTERS(x)
27880
27881 /* end of group CSI_Peripheral_Access_Layer */
27885
27886
27887/* ----------------------------------------------------------------------------
27888 -- DAC Peripheral Access Layer
27889 ---------------------------------------------------------------------------- */
27890
27897typedef struct {
27898 __I uint32_t VERID;
27899 __I uint32_t PARAM;
27900 __O uint32_t DATA;
27901 __IO uint32_t CR;
27902 __I uint32_t PTR;
27903 __IO uint32_t CR2;
27904} DAC_Type;
27905
27906/* ----------------------------------------------------------------------------
27907 -- DAC Register Masks
27908 ---------------------------------------------------------------------------- */
27909
27918#define DAC_VERID_FEATURE_MASK (0xFFFFU)
27919#define DAC_VERID_FEATURE_SHIFT (0U)
27926#define DAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK)
27927
27928#define DAC_VERID_MINOR_MASK (0xFF0000U)
27929#define DAC_VERID_MINOR_SHIFT (16U)
27932#define DAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK)
27933
27934#define DAC_VERID_MAJOR_MASK (0xFF000000U)
27935#define DAC_VERID_MAJOR_SHIFT (24U)
27938#define DAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK)
27944#define DAC_PARAM_FIFOSZ_MASK (0x7U)
27945#define DAC_PARAM_FIFOSZ_SHIFT (0U)
27956#define DAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)
27962#define DAC_DATA_DATA0_MASK (0xFFFU)
27963#define DAC_DATA_DATA0_SHIFT (0U)
27966#define DAC_DATA_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK)
27972#define DAC_CR_FULLF_MASK (0x1U)
27973#define DAC_CR_FULLF_SHIFT (0U)
27978#define DAC_CR_FULLF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK)
27979
27980#define DAC_CR_NEMPTF_MASK (0x2U)
27981#define DAC_CR_NEMPTF_SHIFT (1U)
27986#define DAC_CR_NEMPTF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK)
27987
27988#define DAC_CR_WMF_MASK (0x4U)
27989#define DAC_CR_WMF_SHIFT (2U)
27994#define DAC_CR_WMF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK)
27995
27996#define DAC_CR_UDFF_MASK (0x8U)
27997#define DAC_CR_UDFF_SHIFT (3U)
28002#define DAC_CR_UDFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK)
28003
28004#define DAC_CR_OVFF_MASK (0x10U)
28005#define DAC_CR_OVFF_SHIFT (4U)
28010#define DAC_CR_OVFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK)
28011
28012#define DAC_CR_FULLIE_MASK (0x100U)
28013#define DAC_CR_FULLIE_SHIFT (8U)
28018#define DAC_CR_FULLIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK)
28019
28020#define DAC_CR_EMPTIE_MASK (0x200U)
28021#define DAC_CR_EMPTIE_SHIFT (9U)
28026#define DAC_CR_EMPTIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK)
28027
28028#define DAC_CR_WTMIE_MASK (0x400U)
28029#define DAC_CR_WTMIE_SHIFT (10U)
28034#define DAC_CR_WTMIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK)
28035
28036#define DAC_CR_SWTRG_MASK (0x1000U)
28037#define DAC_CR_SWTRG_SHIFT (12U)
28042#define DAC_CR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK)
28043
28044#define DAC_CR_TRGSEL_MASK (0x2000U)
28045#define DAC_CR_TRGSEL_SHIFT (13U)
28050#define DAC_CR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK)
28051
28052#define DAC_CR_DACRFS_MASK (0x4000U)
28053#define DAC_CR_DACRFS_SHIFT (14U)
28058#define DAC_CR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK)
28059
28060#define DAC_CR_DACEN_MASK (0x8000U)
28061#define DAC_CR_DACEN_SHIFT (15U)
28066#define DAC_CR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK)
28067
28068#define DAC_CR_FIFOEN_MASK (0x10000U)
28069#define DAC_CR_FIFOEN_SHIFT (16U)
28074#define DAC_CR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK)
28075
28076#define DAC_CR_SWMD_MASK (0x20000U)
28077#define DAC_CR_SWMD_SHIFT (17U)
28082#define DAC_CR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK)
28083
28084#define DAC_CR_UVIE_MASK (0x40000U)
28085#define DAC_CR_UVIE_SHIFT (18U)
28090#define DAC_CR_UVIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK)
28091
28092#define DAC_CR_FIFORST_MASK (0x200000U)
28093#define DAC_CR_FIFORST_SHIFT (21U)
28098#define DAC_CR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK)
28099
28100#define DAC_CR_SWRST_MASK (0x400000U)
28101#define DAC_CR_SWRST_SHIFT (22U)
28104#define DAC_CR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK)
28105
28106#define DAC_CR_DMAEN_MASK (0x800000U)
28107#define DAC_CR_DMAEN_SHIFT (23U)
28113#define DAC_CR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK)
28114
28115#define DAC_CR_WML_MASK (0xFF000000U)
28116#define DAC_CR_WML_SHIFT (24U)
28119#define DAC_CR_WML(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK)
28125#define DAC_PTR_DACWFP_MASK (0xFFU)
28126#define DAC_PTR_DACWFP_SHIFT (0U)
28129#define DAC_PTR_DACWFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK)
28130
28131#define DAC_PTR_DACRFP_MASK (0xFF0000U)
28132#define DAC_PTR_DACRFP_SHIFT (16U)
28135#define DAC_PTR_DACRFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK)
28141#define DAC_CR2_BFEN_MASK (0x1U)
28142#define DAC_CR2_BFEN_SHIFT (0U)
28147#define DAC_CR2_BFEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK)
28148
28149#define DAC_CR2_OEN_MASK (0x2U)
28150#define DAC_CR2_OEN_SHIFT (1U)
28155#define DAC_CR2_OEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK)
28156
28157#define DAC_CR2_BFMS_MASK (0x4U)
28158#define DAC_CR2_BFMS_SHIFT (2U)
28163#define DAC_CR2_BFMS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK)
28164
28165#define DAC_CR2_BFHS_MASK (0x8U)
28166#define DAC_CR2_BFHS_SHIFT (3U)
28171#define DAC_CR2_BFHS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK)
28172
28173#define DAC_CR2_IREF2_MASK (0x10U)
28174#define DAC_CR2_IREF2_SHIFT (4U)
28179#define DAC_CR2_IREF2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK)
28180
28181#define DAC_CR2_IREF1_MASK (0x20U)
28182#define DAC_CR2_IREF1_SHIFT (5U)
28187#define DAC_CR2_IREF1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK)
28188
28189#define DAC_CR2_IREF_MASK (0x40U)
28190#define DAC_CR2_IREF_SHIFT (6U)
28195#define DAC_CR2_IREF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK) /* end of group DAC_Register_Masks */
28202
28203
28204/* DAC - Peripheral instance base addresses */
28206#define DAC_BASE (0x40064000u)
28208#define DAC ((DAC_Type *)DAC_BASE)
28210#define DAC_BASE_ADDRS { DAC_BASE }
28212#define DAC_BASE_PTRS { DAC }
28214#define DAC_IRQS { DAC_IRQn }
28215 /* end of group DAC_Peripheral_Access_Layer */
28219
28220
28221/* ----------------------------------------------------------------------------
28222 -- DCDC Peripheral Access Layer
28223 ---------------------------------------------------------------------------- */
28224
28231typedef struct {
28232 __IO uint32_t CTRL0;
28233 __IO uint32_t CTRL1;
28234 __IO uint32_t REG0;
28235 __IO uint32_t REG1;
28236 __IO uint32_t REG2;
28237 __IO uint32_t REG3;
28238 __IO uint32_t REG4;
28239 __IO uint32_t REG5;
28240 __IO uint32_t REG6;
28241 __IO uint32_t REG7;
28242 __IO uint32_t REG7P;
28243 __IO uint32_t REG8;
28244 __IO uint32_t REG9;
28245 __IO uint32_t REG10;
28246 __IO uint32_t REG11;
28247 __IO uint32_t REG12;
28248 __IO uint32_t REG13;
28249 __IO uint32_t REG14;
28250 __IO uint32_t REG15;
28251 __IO uint32_t REG16;
28252 __IO uint32_t REG17;
28253 __IO uint32_t REG18;
28254 __IO uint32_t REG19;
28255 __IO uint32_t REG20;
28256 __IO uint32_t REG21;
28257 __IO uint32_t REG22;
28258 __IO uint32_t REG23;
28259 __IO uint32_t REG24;
28260} DCDC_Type;
28261
28262/* ----------------------------------------------------------------------------
28263 -- DCDC Register Masks
28264 ---------------------------------------------------------------------------- */
28265
28274#define DCDC_CTRL0_ENABLE_MASK (0x1U)
28275#define DCDC_CTRL0_ENABLE_SHIFT (0U)
28280#define DCDC_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
28281
28282#define DCDC_CTRL0_DIG_EN_MASK (0x2U)
28283#define DCDC_CTRL0_DIG_EN_SHIFT (1U)
28288#define DCDC_CTRL0_DIG_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DIG_EN_SHIFT)) & DCDC_CTRL0_DIG_EN_MASK)
28289
28290#define DCDC_CTRL0_STBY_EN_MASK (0x4U)
28291#define DCDC_CTRL0_STBY_EN_SHIFT (2U)
28295#define DCDC_CTRL0_STBY_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_EN_SHIFT)) & DCDC_CTRL0_STBY_EN_MASK)
28296
28297#define DCDC_CTRL0_LP_MODE_EN_MASK (0x8U)
28298#define DCDC_CTRL0_LP_MODE_EN_SHIFT (3U)
28302#define DCDC_CTRL0_LP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_LP_MODE_EN_MASK)
28303
28304#define DCDC_CTRL0_STBY_LP_MODE_EN_MASK (0x10U)
28305#define DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT (4U)
28310#define DCDC_CTRL0_STBY_LP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_STBY_LP_MODE_EN_MASK)
28311
28312#define DCDC_CTRL0_ENABLE_DCDC_CNT_MASK (0x20U)
28313#define DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT (5U)
28318#define DCDC_CTRL0_ENABLE_DCDC_CNT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_DCDC_CNT_MASK)
28319
28320#define DCDC_CTRL0_TRIM_HOLD_MASK (0x40U)
28321#define DCDC_CTRL0_TRIM_HOLD_SHIFT (6U)
28326#define DCDC_CTRL0_TRIM_HOLD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK)
28327
28328#define DCDC_CTRL0_DEBUG_BITS_MASK (0x7FF80000U)
28329#define DCDC_CTRL0_DEBUG_BITS_SHIFT (19U)
28332#define DCDC_CTRL0_DEBUG_BITS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DEBUG_BITS_SHIFT)) & DCDC_CTRL0_DEBUG_BITS_MASK)
28333
28334#define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U)
28335#define DCDC_CTRL0_CONTROL_MODE_SHIFT (31U)
28340#define DCDC_CTRL0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
28346#define DCDC_CTRL1_VDD1P8CTRL_TRG_MASK (0x1FU)
28347#define DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT (0U)
28353#define DCDC_CTRL1_VDD1P8CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)
28354
28355#define DCDC_CTRL1_VDD1P0CTRL_TRG_MASK (0x1F00U)
28356#define DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT (8U)
28362#define DCDC_CTRL1_VDD1P0CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)
28363
28364#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK (0x1F0000U)
28365#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT (16U)
28371#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK)
28372
28373#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK (0x1F000000U)
28374#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT (24U)
28380#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)
28386#define DCDC_REG0_PWD_ZCD_MASK (0x1U)
28387#define DCDC_REG0_PWD_ZCD_SHIFT (0U)
28392#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
28393
28394#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
28395#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
28401#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
28402
28403#define DCDC_REG0_SEL_CLK_MASK (0x4U)
28404#define DCDC_REG0_SEL_CLK_SHIFT (2U)
28409#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
28410
28411#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U)
28412#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U)
28417#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
28418
28419#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)
28420#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)
28425#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
28426
28427#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)
28428#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)
28431#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
28432
28433#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)
28434#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)
28439#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
28440
28441#define DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK (0x800U)
28442#define DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT (11U)
28447#define DCDC_REG0_PWD_CMP_DCDC_IN_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK)
28448
28449#define DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK (0x10000U)
28450#define DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT (16U)
28455#define DCDC_REG0_PWD_HIGH_VDD1P8_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK)
28456
28457#define DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK (0x20000U)
28458#define DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT (17U)
28463#define DCDC_REG0_PWD_HIGH_VDD1P0_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK)
28464
28465#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)
28466#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)
28471#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
28472
28473#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
28474#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
28479#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
28480
28481#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)
28482#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)
28487#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
28488
28489#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)
28490#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U)
28495#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
28496
28497#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U)
28498#define DCDC_REG0_STS_DC_OK_SHIFT (31U)
28503#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
28509#define DCDC_REG1_DM_CTRL_MASK (0x8U)
28510#define DCDC_REG1_DM_CTRL_SHIFT (3U)
28515#define DCDC_REG1_DM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DM_CTRL_SHIFT)) & DCDC_REG1_DM_CTRL_MASK)
28516
28517#define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U)
28518#define DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT (4U)
28523#define DCDC_REG1_RLOAD_REG_EN_LPSR(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
28524
28525#define DCDC_REG1_VBG_TRIM_MASK (0x7C0U)
28526#define DCDC_REG1_VBG_TRIM_SHIFT (6U)
28532#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
28533
28534#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x1800U)
28535#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (11U)
28542#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
28543
28544#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK (0x8000000U)
28545#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT (27U)
28548#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK)
28549
28550#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U)
28551#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT (28U)
28554#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
28555
28556#define DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK (0x20000000U)
28557#define DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT (29U)
28562#define DCDC_REG1_LOOPCTRL_EN_CM_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK)
28563
28564#define DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK (0x40000000U)
28565#define DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT (30U)
28570#define DCDC_REG1_LOOPCTRL_EN_DF_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK)
28576#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)
28577#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)
28578#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
28579
28580#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)
28581#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)
28582#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
28583
28584#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)
28585#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)
28586#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
28587
28588#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)
28589#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)
28592#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
28593
28594#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)
28595#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)
28596#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
28597
28598#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
28599#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)
28600#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
28601
28602#define DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK (0x8000U)
28603#define DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT (15U)
28604#define DCDC_REG2_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK)
28605
28606#define DCDC_REG2_BATTMONITOR_BATT_VAL_MASK (0x3FF0000U)
28607#define DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT (16U)
28608#define DCDC_REG2_BATTMONITOR_BATT_VAL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_BATTMONITOR_BATT_VAL_MASK)
28609
28610#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)
28611#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)
28614#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
28615
28616#define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK (0x40000000U)
28617#define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT (30U)
28618#define DCDC_REG2_LOOPCTRL_TOGGLE_DIF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT)) & DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK)
28624#define DCDC_REG3_IN_BROWNOUT_MASK (0x4000U)
28625#define DCDC_REG3_IN_BROWNOUT_SHIFT (14U)
28629#define DCDC_REG3_IN_BROWNOUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_SHIFT)) & DCDC_REG3_IN_BROWNOUT_MASK)
28630
28631#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK (0x8000U)
28632#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT (15U)
28636#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK)
28637
28638#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK (0x10000U)
28639#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT (16U)
28643#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK)
28644
28645#define DCDC_REG3_OVERCUR_DETECT_OUT_MASK (0x20000U)
28646#define DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT (17U)
28650#define DCDC_REG3_OVERCUR_DETECT_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT)) & DCDC_REG3_OVERCUR_DETECT_OUT_MASK)
28651
28652#define DCDC_REG3_ENABLE_FF_MASK (0x40000U)
28653#define DCDC_REG3_ENABLE_FF_SHIFT (18U)
28657#define DCDC_REG3_ENABLE_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK)
28658
28659#define DCDC_REG3_DISABLE_PULSE_SKIP_MASK (0x80000U)
28660#define DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT (19U)
28664#define DCDC_REG3_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK)
28665
28666#define DCDC_REG3_DISABLE_IDLE_SKIP_MASK (0x100000U)
28667#define DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT (20U)
28673#define DCDC_REG3_DISABLE_IDLE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK)
28674
28675#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK (0x200000U)
28676#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT (21U)
28680#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK)
28681
28682#define DCDC_REG3_REG_FBK_SEL_MASK (0xC00000U)
28683#define DCDC_REG3_REG_FBK_SEL_SHIFT (22U)
28684#define DCDC_REG3_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_REG_FBK_SEL_SHIFT)) & DCDC_REG3_REG_FBK_SEL_MASK)
28685
28686#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)
28687#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)
28692#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
28693
28694#define DCDC_REG3_MINPWR_HALF_FETS_MASK (0x4000000U)
28695#define DCDC_REG3_MINPWR_HALF_FETS_SHIFT (26U)
28696#define DCDC_REG3_MINPWR_HALF_FETS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_MINPWR_HALF_FETS_MASK)
28697
28698#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)
28699#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)
28702#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
28703
28704#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U)
28705#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT (29U)
28710#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
28711
28712#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U)
28713#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT (30U)
28718#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK)
28724#define DCDC_REG4_ENABLE_SP_MASK (0xFFFFU)
28725#define DCDC_REG4_ENABLE_SP_SHIFT (0U)
28726#define DCDC_REG4_ENABLE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_ENABLE_SP_SHIFT)) & DCDC_REG4_ENABLE_SP_MASK)
28732#define DCDC_REG5_DIG_EN_SP_MASK (0xFFFFU)
28733#define DCDC_REG5_DIG_EN_SP_SHIFT (0U)
28734#define DCDC_REG5_DIG_EN_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG5_DIG_EN_SP_SHIFT)) & DCDC_REG5_DIG_EN_SP_MASK)
28740#define DCDC_REG6_LP_MODE_SP_MASK (0xFFFFU)
28741#define DCDC_REG6_LP_MODE_SP_SHIFT (0U)
28742#define DCDC_REG6_LP_MODE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_LP_MODE_SP_SHIFT)) & DCDC_REG6_LP_MODE_SP_MASK)
28748#define DCDC_REG7_STBY_EN_SP_MASK (0xFFFFU)
28749#define DCDC_REG7_STBY_EN_SP_SHIFT (0U)
28750#define DCDC_REG7_STBY_EN_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_STBY_EN_SP_SHIFT)) & DCDC_REG7_STBY_EN_SP_MASK)
28756#define DCDC_REG7P_STBY_LP_MODE_SP_MASK (0xFFFFU)
28757#define DCDC_REG7P_STBY_LP_MODE_SP_SHIFT (0U)
28758#define DCDC_REG7P_STBY_LP_MODE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7P_STBY_LP_MODE_SP_SHIFT)) & DCDC_REG7P_STBY_LP_MODE_SP_MASK)
28764#define DCDC_REG8_ANA_TRG_SP0_MASK (0xFFFFFFFFU)
28765#define DCDC_REG8_ANA_TRG_SP0_SHIFT (0U)
28766#define DCDC_REG8_ANA_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG8_ANA_TRG_SP0_SHIFT)) & DCDC_REG8_ANA_TRG_SP0_MASK)
28772#define DCDC_REG9_ANA_TRG_SP1_MASK (0xFFFFFFFFU)
28773#define DCDC_REG9_ANA_TRG_SP1_SHIFT (0U)
28774#define DCDC_REG9_ANA_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG9_ANA_TRG_SP1_SHIFT)) & DCDC_REG9_ANA_TRG_SP1_MASK)
28780#define DCDC_REG10_ANA_TRG_SP2_MASK (0xFFFFFFFFU)
28781#define DCDC_REG10_ANA_TRG_SP2_SHIFT (0U)
28782#define DCDC_REG10_ANA_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG10_ANA_TRG_SP2_SHIFT)) & DCDC_REG10_ANA_TRG_SP2_MASK)
28788#define DCDC_REG11_ANA_TRG_SP3_MASK (0xFFFFFFFFU)
28789#define DCDC_REG11_ANA_TRG_SP3_SHIFT (0U)
28790#define DCDC_REG11_ANA_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG11_ANA_TRG_SP3_SHIFT)) & DCDC_REG11_ANA_TRG_SP3_MASK)
28796#define DCDC_REG12_DIG_TRG_SP0_MASK (0xFFFFFFFFU)
28797#define DCDC_REG12_DIG_TRG_SP0_SHIFT (0U)
28798#define DCDC_REG12_DIG_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG12_DIG_TRG_SP0_SHIFT)) & DCDC_REG12_DIG_TRG_SP0_MASK)
28804#define DCDC_REG13_DIG_TRG_SP1_MASK (0xFFFFFFFFU)
28805#define DCDC_REG13_DIG_TRG_SP1_SHIFT (0U)
28806#define DCDC_REG13_DIG_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG13_DIG_TRG_SP1_SHIFT)) & DCDC_REG13_DIG_TRG_SP1_MASK)
28812#define DCDC_REG14_DIG_TRG_SP2_MASK (0xFFFFFFFFU)
28813#define DCDC_REG14_DIG_TRG_SP2_SHIFT (0U)
28814#define DCDC_REG14_DIG_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG14_DIG_TRG_SP2_SHIFT)) & DCDC_REG14_DIG_TRG_SP2_MASK)
28820#define DCDC_REG15_DIG_TRG_SP3_MASK (0xFFFFFFFFU)
28821#define DCDC_REG15_DIG_TRG_SP3_SHIFT (0U)
28822#define DCDC_REG15_DIG_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG15_DIG_TRG_SP3_SHIFT)) & DCDC_REG15_DIG_TRG_SP3_MASK)
28828#define DCDC_REG16_ANA_STBY_TRG_SP0_MASK (0xFFFFFFFFU)
28829#define DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT (0U)
28830#define DCDC_REG16_ANA_STBY_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT)) & DCDC_REG16_ANA_STBY_TRG_SP0_MASK)
28836#define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU)
28837#define DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT (0U)
28838#define DCDC_REG17_ANA_STBY_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
28844#define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU)
28845#define DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT (0U)
28846#define DCDC_REG18_ANA_STBY_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
28852#define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU)
28853#define DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT (0U)
28854#define DCDC_REG19_ANA_STBY_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
28860#define DCDC_REG20_DIG_STBY_TRG_SP0_MASK (0xFFFFFFFFU)
28861#define DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT (0U)
28862#define DCDC_REG20_DIG_STBY_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT)) & DCDC_REG20_DIG_STBY_TRG_SP0_MASK)
28868#define DCDC_REG21_DIG_STBY_TRG_SP1_MASK (0xFFFFFFFFU)
28869#define DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT (0U)
28870#define DCDC_REG21_DIG_STBY_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT)) & DCDC_REG21_DIG_STBY_TRG_SP1_MASK)
28876#define DCDC_REG22_DIG_STBY_TRG_SP2_MASK (0xFFFFFFFFU)
28877#define DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT (0U)
28878#define DCDC_REG22_DIG_STBY_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT)) & DCDC_REG22_DIG_STBY_TRG_SP2_MASK)
28884#define DCDC_REG23_DIG_STBY_TRG_SP3_MASK (0xFFFFFFFFU)
28885#define DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT (0U)
28886#define DCDC_REG23_DIG_STBY_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT)) & DCDC_REG23_DIG_STBY_TRG_SP3_MASK)
28892#define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU)
28893#define DCDC_REG24_OK_COUNT_SHIFT (0U)
28894#define DCDC_REG24_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK) /* end of group DCDC_Register_Masks */
28901
28902
28903/* DCDC - Peripheral instance base addresses */
28905#define DCDC_BASE (0x40CA8000u)
28907#define DCDC ((DCDC_Type *)DCDC_BASE)
28909#define DCDC_BASE_ADDRS { DCDC_BASE }
28911#define DCDC_BASE_PTRS { DCDC }
28912 /* end of group DCDC_Peripheral_Access_Layer */
28916
28917
28918/* ----------------------------------------------------------------------------
28919 -- DCIC Peripheral Access Layer
28920 ---------------------------------------------------------------------------- */
28921
28928typedef struct {
28929 __IO uint32_t DCICC;
28930 __IO uint32_t DCICIC;
28931 __IO uint32_t DCICS;
28932 uint8_t RESERVED_0[4];
28933 struct { /* offset: 0x10, array step: 0x10 */
28934 __IO uint32_t DCICRC;
28935 __IO uint32_t DCICRS;
28936 __IO uint32_t DCICRRS;
28937 __I uint32_t DCICRCS;
28938 } REGION[16];
28939} DCIC_Type;
28940
28941/* ----------------------------------------------------------------------------
28942 -- DCIC Register Masks
28943 ---------------------------------------------------------------------------- */
28944
28953#define DCIC_DCICC_IC_EN_MASK (0x1U)
28954#define DCIC_DCICC_IC_EN_SHIFT (0U)
28959#define DCIC_DCICC_IC_EN(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_IC_EN_SHIFT)) & DCIC_DCICC_IC_EN_MASK)
28960
28961#define DCIC_DCICC_DE_POL_MASK (0x10U)
28962#define DCIC_DCICC_DE_POL_SHIFT (4U)
28967#define DCIC_DCICC_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_DE_POL_SHIFT)) & DCIC_DCICC_DE_POL_MASK)
28968
28969#define DCIC_DCICC_HSYNC_POL_MASK (0x20U)
28970#define DCIC_DCICC_HSYNC_POL_SHIFT (5U)
28975#define DCIC_DCICC_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_HSYNC_POL_SHIFT)) & DCIC_DCICC_HSYNC_POL_MASK)
28976
28977#define DCIC_DCICC_VSYNC_POL_MASK (0x40U)
28978#define DCIC_DCICC_VSYNC_POL_SHIFT (6U)
28983#define DCIC_DCICC_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_VSYNC_POL_SHIFT)) & DCIC_DCICC_VSYNC_POL_MASK)
28984
28985#define DCIC_DCICC_CLK_POL_MASK (0x80U)
28986#define DCIC_DCICC_CLK_POL_SHIFT (7U)
28991#define DCIC_DCICC_CLK_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_CLK_POL_SHIFT)) & DCIC_DCICC_CLK_POL_MASK)
28997#define DCIC_DCICIC_EI_MASK_MASK (0x1U)
28998#define DCIC_DCICIC_EI_MASK_SHIFT (0U)
29003#define DCIC_DCICIC_EI_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EI_MASK_SHIFT)) & DCIC_DCICIC_EI_MASK_MASK)
29004
29005#define DCIC_DCICIC_FI_MASK_MASK (0x2U)
29006#define DCIC_DCICIC_FI_MASK_SHIFT (1U)
29011#define DCIC_DCICIC_FI_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FI_MASK_SHIFT)) & DCIC_DCICIC_FI_MASK_MASK)
29012
29013#define DCIC_DCICIC_FREEZE_MASK_MASK (0x8U)
29014#define DCIC_DCICIC_FREEZE_MASK_SHIFT (3U)
29019#define DCIC_DCICIC_FREEZE_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FREEZE_MASK_SHIFT)) & DCIC_DCICIC_FREEZE_MASK_MASK)
29020
29021#define DCIC_DCICIC_EXT_SIG_EN_MASK (0x10000U)
29022#define DCIC_DCICIC_EXT_SIG_EN_SHIFT (16U)
29027#define DCIC_DCICIC_EXT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EXT_SIG_EN_SHIFT)) & DCIC_DCICIC_EXT_SIG_EN_MASK)
29033#define DCIC_DCICS_ROI_MATCH_STAT_MASK (0xFFFFU)
29034#define DCIC_DCICS_ROI_MATCH_STAT_SHIFT (0U)
29039#define DCIC_DCICS_ROI_MATCH_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_ROI_MATCH_STAT_SHIFT)) & DCIC_DCICS_ROI_MATCH_STAT_MASK)
29040
29041#define DCIC_DCICS_EI_STAT_MASK (0x10000U)
29042#define DCIC_DCICS_EI_STAT_SHIFT (16U)
29047#define DCIC_DCICS_EI_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_EI_STAT_SHIFT)) & DCIC_DCICS_EI_STAT_MASK)
29048
29049#define DCIC_DCICS_FI_STAT_MASK (0x20000U)
29050#define DCIC_DCICS_FI_STAT_SHIFT (17U)
29055#define DCIC_DCICS_FI_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_FI_STAT_SHIFT)) & DCIC_DCICS_FI_STAT_MASK)
29061#define DCIC_DCICRC_START_OFFSET_X_MASK (0x1FFFU)
29062#define DCIC_DCICRC_START_OFFSET_X_SHIFT (0U)
29063#define DCIC_DCICRC_START_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_X_SHIFT)) & DCIC_DCICRC_START_OFFSET_X_MASK)
29064
29065#define DCIC_DCICRC_START_OFFSET_Y_MASK (0xFFF0000U)
29066#define DCIC_DCICRC_START_OFFSET_Y_SHIFT (16U)
29067#define DCIC_DCICRC_START_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_Y_SHIFT)) & DCIC_DCICRC_START_OFFSET_Y_MASK)
29068
29069#define DCIC_DCICRC_ROI_FREEZE_MASK (0x40000000U)
29070#define DCIC_DCICRC_ROI_FREEZE_SHIFT (30U)
29075#define DCIC_DCICRC_ROI_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_FREEZE_SHIFT)) & DCIC_DCICRC_ROI_FREEZE_MASK)
29076
29077#define DCIC_DCICRC_ROI_EN_MASK (0x80000000U)
29078#define DCIC_DCICRC_ROI_EN_SHIFT (31U)
29083#define DCIC_DCICRC_ROI_EN(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_EN_SHIFT)) & DCIC_DCICRC_ROI_EN_MASK)
29086/* The count of DCIC_DCICRC */
29087#define DCIC_DCICRC_COUNT (16U)
29088
29092#define DCIC_DCICRS_END_OFFSET_X_MASK (0x1FFFU)
29093#define DCIC_DCICRS_END_OFFSET_X_SHIFT (0U)
29094#define DCIC_DCICRS_END_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_X_SHIFT)) & DCIC_DCICRS_END_OFFSET_X_MASK)
29095
29096#define DCIC_DCICRS_END_OFFSET_Y_MASK (0xFFF0000U)
29097#define DCIC_DCICRS_END_OFFSET_Y_SHIFT (16U)
29098#define DCIC_DCICRS_END_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_Y_SHIFT)) & DCIC_DCICRS_END_OFFSET_Y_MASK)
29101/* The count of DCIC_DCICRS */
29102#define DCIC_DCICRS_COUNT (16U)
29103
29107#define DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK (0xFFFFFFFFU)
29108#define DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT (0U)
29109#define DCIC_DCICRRS_REFERENCE_SIGNATURE(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT)) & DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK)
29112/* The count of DCIC_DCICRRS */
29113#define DCIC_DCICRRS_COUNT (16U)
29114
29118#define DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK (0xFFFFFFFFU)
29119#define DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT (0U)
29120#define DCIC_DCICRCS_CALCULATED_SIGNATURE(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT)) & DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK)
29123/* The count of DCIC_DCICRCS */
29124#define DCIC_DCICRCS_COUNT (16U)
29125
29126 /* end of group DCIC_Register_Masks */
29130
29131
29132/* DCIC - Peripheral instance base addresses */
29134#define DCIC1_BASE (0x40819000u)
29136#define DCIC1 ((DCIC_Type *)DCIC1_BASE)
29138#define DCIC2_BASE (0x4081A000u)
29140#define DCIC2 ((DCIC_Type *)DCIC2_BASE)
29142#define DCIC_BASE_ADDRS { 0u, DCIC1_BASE, DCIC2_BASE }
29144#define DCIC_BASE_PTRS { (DCIC_Type *)0u, DCIC1, DCIC2 }
29145 /* end of group DCIC_Peripheral_Access_Layer */
29149
29150
29151/* ----------------------------------------------------------------------------
29152 -- DMA Peripheral Access Layer
29153 ---------------------------------------------------------------------------- */
29154
29161typedef struct {
29162 __IO uint32_t CR;
29163 __I uint32_t ES;
29164 uint8_t RESERVED_0[4];
29165 __IO uint32_t ERQ;
29166 uint8_t RESERVED_1[4];
29167 __IO uint32_t EEI;
29168 __O uint8_t CEEI;
29169 __O uint8_t SEEI;
29170 __O uint8_t CERQ;
29171 __O uint8_t SERQ;
29172 __O uint8_t CDNE;
29173 __O uint8_t SSRT;
29174 __O uint8_t CERR;
29175 __O uint8_t CINT;
29176 uint8_t RESERVED_2[4];
29177 __IO uint32_t INT;
29178 uint8_t RESERVED_3[4];
29179 __IO uint32_t ERR;
29180 uint8_t RESERVED_4[4];
29181 __I uint32_t HRS;
29182 uint8_t RESERVED_5[12];
29183 __IO uint32_t EARS;
29184 uint8_t RESERVED_6[184];
29185 __IO uint8_t DCHPRI3;
29186 __IO uint8_t DCHPRI2;
29187 __IO uint8_t DCHPRI1;
29188 __IO uint8_t DCHPRI0;
29189 __IO uint8_t DCHPRI7;
29190 __IO uint8_t DCHPRI6;
29191 __IO uint8_t DCHPRI5;
29192 __IO uint8_t DCHPRI4;
29193 __IO uint8_t DCHPRI11;
29194 __IO uint8_t DCHPRI10;
29195 __IO uint8_t DCHPRI9;
29196 __IO uint8_t DCHPRI8;
29197 __IO uint8_t DCHPRI15;
29198 __IO uint8_t DCHPRI14;
29199 __IO uint8_t DCHPRI13;
29200 __IO uint8_t DCHPRI12;
29201 __IO uint8_t DCHPRI19;
29202 __IO uint8_t DCHPRI18;
29203 __IO uint8_t DCHPRI17;
29204 __IO uint8_t DCHPRI16;
29205 __IO uint8_t DCHPRI23;
29206 __IO uint8_t DCHPRI22;
29207 __IO uint8_t DCHPRI21;
29208 __IO uint8_t DCHPRI20;
29209 __IO uint8_t DCHPRI27;
29210 __IO uint8_t DCHPRI26;
29211 __IO uint8_t DCHPRI25;
29212 __IO uint8_t DCHPRI24;
29213 __IO uint8_t DCHPRI31;
29214 __IO uint8_t DCHPRI30;
29215 __IO uint8_t DCHPRI29;
29216 __IO uint8_t DCHPRI28;
29217 uint8_t RESERVED_7[3808];
29218 struct { /* offset: 0x1000, array step: 0x20 */
29219 __IO uint32_t SADDR;
29220 __IO uint16_t SOFF;
29221 __IO uint16_t ATTR;
29222 union { /* offset: 0x1008, array step: 0x20 */
29226 };
29227 __IO int32_t SLAST;
29228 __IO uint32_t DADDR;
29229 __IO uint16_t DOFF;
29230 union { /* offset: 0x1016, array step: 0x20 */
29233 };
29234 __IO int32_t DLAST_SGA;
29235 __IO uint16_t CSR;
29236 union { /* offset: 0x101E, array step: 0x20 */
29239 };
29240 } TCD[32];
29241} DMA_Type;
29242
29243/* ----------------------------------------------------------------------------
29244 -- DMA Register Masks
29245 ---------------------------------------------------------------------------- */
29246
29255#define DMA_CR_EDBG_MASK (0x2U)
29256#define DMA_CR_EDBG_SHIFT (1U)
29261#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
29262
29263#define DMA_CR_ERCA_MASK (0x4U)
29264#define DMA_CR_ERCA_SHIFT (2U)
29269#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
29270
29271#define DMA_CR_ERGA_MASK (0x8U)
29272#define DMA_CR_ERGA_SHIFT (3U)
29277#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
29278
29279#define DMA_CR_HOE_MASK (0x10U)
29280#define DMA_CR_HOE_SHIFT (4U)
29285#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
29286
29287#define DMA_CR_HALT_MASK (0x20U)
29288#define DMA_CR_HALT_SHIFT (5U)
29293#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
29294
29295#define DMA_CR_CLM_MASK (0x40U)
29296#define DMA_CR_CLM_SHIFT (6U)
29301#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
29302
29303#define DMA_CR_EMLM_MASK (0x80U)
29304#define DMA_CR_EMLM_SHIFT (7U)
29309#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
29310
29311#define DMA_CR_GRP0PRI_MASK (0x100U)
29312#define DMA_CR_GRP0PRI_SHIFT (8U)
29315#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
29316
29317#define DMA_CR_GRP1PRI_MASK (0x400U)
29318#define DMA_CR_GRP1PRI_SHIFT (10U)
29321#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
29322
29323#define DMA_CR_ECX_MASK (0x10000U)
29324#define DMA_CR_ECX_SHIFT (16U)
29329#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
29330
29331#define DMA_CR_CX_MASK (0x20000U)
29332#define DMA_CR_CX_SHIFT (17U)
29337#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
29338
29339#define DMA_CR_VERSION_MASK (0x7F000000U)
29340#define DMA_CR_VERSION_SHIFT (24U)
29343#define DMA_CR_VERSION(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK)
29344
29345#define DMA_CR_ACTIVE_MASK (0x80000000U)
29346#define DMA_CR_ACTIVE_SHIFT (31U)
29351#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
29357#define DMA_ES_DBE_MASK (0x1U)
29358#define DMA_ES_DBE_SHIFT (0U)
29363#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
29364
29365#define DMA_ES_SBE_MASK (0x2U)
29366#define DMA_ES_SBE_SHIFT (1U)
29371#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
29372
29373#define DMA_ES_SGE_MASK (0x4U)
29374#define DMA_ES_SGE_SHIFT (2U)
29379#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
29380
29381#define DMA_ES_NCE_MASK (0x8U)
29382#define DMA_ES_NCE_SHIFT (3U)
29389#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
29390
29391#define DMA_ES_DOE_MASK (0x10U)
29392#define DMA_ES_DOE_SHIFT (4U)
29397#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
29398
29399#define DMA_ES_DAE_MASK (0x20U)
29400#define DMA_ES_DAE_SHIFT (5U)
29406#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
29407
29408#define DMA_ES_SOE_MASK (0x40U)
29409#define DMA_ES_SOE_SHIFT (6U)
29414#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
29415
29416#define DMA_ES_SAE_MASK (0x80U)
29417#define DMA_ES_SAE_SHIFT (7U)
29423#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
29424
29425#define DMA_ES_ERRCHN_MASK (0x1F00U)
29426#define DMA_ES_ERRCHN_SHIFT (8U)
29429#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
29430
29431#define DMA_ES_CPE_MASK (0x4000U)
29432#define DMA_ES_CPE_SHIFT (14U)
29438#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
29439
29440#define DMA_ES_GPE_MASK (0x8000U)
29441#define DMA_ES_GPE_SHIFT (15U)
29446#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
29447
29448#define DMA_ES_ECX_MASK (0x10000U)
29449#define DMA_ES_ECX_SHIFT (16U)
29454#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
29455
29456#define DMA_ES_VLD_MASK (0x80000000U)
29457#define DMA_ES_VLD_SHIFT (31U)
29462#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
29468#define DMA_ERQ_ERQ0_MASK (0x1U)
29469#define DMA_ERQ_ERQ0_SHIFT (0U)
29474#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
29475
29476#define DMA_ERQ_ERQ1_MASK (0x2U)
29477#define DMA_ERQ_ERQ1_SHIFT (1U)
29482#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
29483
29484#define DMA_ERQ_ERQ2_MASK (0x4U)
29485#define DMA_ERQ_ERQ2_SHIFT (2U)
29490#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
29491
29492#define DMA_ERQ_ERQ3_MASK (0x8U)
29493#define DMA_ERQ_ERQ3_SHIFT (3U)
29498#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
29499
29500#define DMA_ERQ_ERQ4_MASK (0x10U)
29501#define DMA_ERQ_ERQ4_SHIFT (4U)
29506#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
29507
29508#define DMA_ERQ_ERQ5_MASK (0x20U)
29509#define DMA_ERQ_ERQ5_SHIFT (5U)
29514#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
29515
29516#define DMA_ERQ_ERQ6_MASK (0x40U)
29517#define DMA_ERQ_ERQ6_SHIFT (6U)
29522#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
29523
29524#define DMA_ERQ_ERQ7_MASK (0x80U)
29525#define DMA_ERQ_ERQ7_SHIFT (7U)
29530#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
29531
29532#define DMA_ERQ_ERQ8_MASK (0x100U)
29533#define DMA_ERQ_ERQ8_SHIFT (8U)
29538#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
29539
29540#define DMA_ERQ_ERQ9_MASK (0x200U)
29541#define DMA_ERQ_ERQ9_SHIFT (9U)
29546#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
29547
29548#define DMA_ERQ_ERQ10_MASK (0x400U)
29549#define DMA_ERQ_ERQ10_SHIFT (10U)
29554#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
29555
29556#define DMA_ERQ_ERQ11_MASK (0x800U)
29557#define DMA_ERQ_ERQ11_SHIFT (11U)
29562#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
29563
29564#define DMA_ERQ_ERQ12_MASK (0x1000U)
29565#define DMA_ERQ_ERQ12_SHIFT (12U)
29570#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
29571
29572#define DMA_ERQ_ERQ13_MASK (0x2000U)
29573#define DMA_ERQ_ERQ13_SHIFT (13U)
29578#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
29579
29580#define DMA_ERQ_ERQ14_MASK (0x4000U)
29581#define DMA_ERQ_ERQ14_SHIFT (14U)
29586#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
29587
29588#define DMA_ERQ_ERQ15_MASK (0x8000U)
29589#define DMA_ERQ_ERQ15_SHIFT (15U)
29594#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
29595
29596#define DMA_ERQ_ERQ16_MASK (0x10000U)
29597#define DMA_ERQ_ERQ16_SHIFT (16U)
29602#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
29603
29604#define DMA_ERQ_ERQ17_MASK (0x20000U)
29605#define DMA_ERQ_ERQ17_SHIFT (17U)
29610#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
29611
29612#define DMA_ERQ_ERQ18_MASK (0x40000U)
29613#define DMA_ERQ_ERQ18_SHIFT (18U)
29618#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
29619
29620#define DMA_ERQ_ERQ19_MASK (0x80000U)
29621#define DMA_ERQ_ERQ19_SHIFT (19U)
29626#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
29627
29628#define DMA_ERQ_ERQ20_MASK (0x100000U)
29629#define DMA_ERQ_ERQ20_SHIFT (20U)
29634#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
29635
29636#define DMA_ERQ_ERQ21_MASK (0x200000U)
29637#define DMA_ERQ_ERQ21_SHIFT (21U)
29642#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
29643
29644#define DMA_ERQ_ERQ22_MASK (0x400000U)
29645#define DMA_ERQ_ERQ22_SHIFT (22U)
29650#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
29651
29652#define DMA_ERQ_ERQ23_MASK (0x800000U)
29653#define DMA_ERQ_ERQ23_SHIFT (23U)
29658#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
29659
29660#define DMA_ERQ_ERQ24_MASK (0x1000000U)
29661#define DMA_ERQ_ERQ24_SHIFT (24U)
29666#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
29667
29668#define DMA_ERQ_ERQ25_MASK (0x2000000U)
29669#define DMA_ERQ_ERQ25_SHIFT (25U)
29674#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
29675
29676#define DMA_ERQ_ERQ26_MASK (0x4000000U)
29677#define DMA_ERQ_ERQ26_SHIFT (26U)
29682#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
29683
29684#define DMA_ERQ_ERQ27_MASK (0x8000000U)
29685#define DMA_ERQ_ERQ27_SHIFT (27U)
29690#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
29691
29692#define DMA_ERQ_ERQ28_MASK (0x10000000U)
29693#define DMA_ERQ_ERQ28_SHIFT (28U)
29698#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
29699
29700#define DMA_ERQ_ERQ29_MASK (0x20000000U)
29701#define DMA_ERQ_ERQ29_SHIFT (29U)
29706#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
29707
29708#define DMA_ERQ_ERQ30_MASK (0x40000000U)
29709#define DMA_ERQ_ERQ30_SHIFT (30U)
29714#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
29715
29716#define DMA_ERQ_ERQ31_MASK (0x80000000U)
29717#define DMA_ERQ_ERQ31_SHIFT (31U)
29722#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
29728#define DMA_EEI_EEI0_MASK (0x1U)
29729#define DMA_EEI_EEI0_SHIFT (0U)
29734#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
29735
29736#define DMA_EEI_EEI1_MASK (0x2U)
29737#define DMA_EEI_EEI1_SHIFT (1U)
29742#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
29743
29744#define DMA_EEI_EEI2_MASK (0x4U)
29745#define DMA_EEI_EEI2_SHIFT (2U)
29750#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
29751
29752#define DMA_EEI_EEI3_MASK (0x8U)
29753#define DMA_EEI_EEI3_SHIFT (3U)
29758#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
29759
29760#define DMA_EEI_EEI4_MASK (0x10U)
29761#define DMA_EEI_EEI4_SHIFT (4U)
29766#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
29767
29768#define DMA_EEI_EEI5_MASK (0x20U)
29769#define DMA_EEI_EEI5_SHIFT (5U)
29774#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
29775
29776#define DMA_EEI_EEI6_MASK (0x40U)
29777#define DMA_EEI_EEI6_SHIFT (6U)
29782#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
29783
29784#define DMA_EEI_EEI7_MASK (0x80U)
29785#define DMA_EEI_EEI7_SHIFT (7U)
29790#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
29791
29792#define DMA_EEI_EEI8_MASK (0x100U)
29793#define DMA_EEI_EEI8_SHIFT (8U)
29798#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
29799
29800#define DMA_EEI_EEI9_MASK (0x200U)
29801#define DMA_EEI_EEI9_SHIFT (9U)
29806#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
29807
29808#define DMA_EEI_EEI10_MASK (0x400U)
29809#define DMA_EEI_EEI10_SHIFT (10U)
29814#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
29815
29816#define DMA_EEI_EEI11_MASK (0x800U)
29817#define DMA_EEI_EEI11_SHIFT (11U)
29822#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
29823
29824#define DMA_EEI_EEI12_MASK (0x1000U)
29825#define DMA_EEI_EEI12_SHIFT (12U)
29830#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
29831
29832#define DMA_EEI_EEI13_MASK (0x2000U)
29833#define DMA_EEI_EEI13_SHIFT (13U)
29838#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
29839
29840#define DMA_EEI_EEI14_MASK (0x4000U)
29841#define DMA_EEI_EEI14_SHIFT (14U)
29846#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
29847
29848#define DMA_EEI_EEI15_MASK (0x8000U)
29849#define DMA_EEI_EEI15_SHIFT (15U)
29854#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
29855
29856#define DMA_EEI_EEI16_MASK (0x10000U)
29857#define DMA_EEI_EEI16_SHIFT (16U)
29862#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
29863
29864#define DMA_EEI_EEI17_MASK (0x20000U)
29865#define DMA_EEI_EEI17_SHIFT (17U)
29870#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
29871
29872#define DMA_EEI_EEI18_MASK (0x40000U)
29873#define DMA_EEI_EEI18_SHIFT (18U)
29878#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
29879
29880#define DMA_EEI_EEI19_MASK (0x80000U)
29881#define DMA_EEI_EEI19_SHIFT (19U)
29886#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
29887
29888#define DMA_EEI_EEI20_MASK (0x100000U)
29889#define DMA_EEI_EEI20_SHIFT (20U)
29894#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
29895
29896#define DMA_EEI_EEI21_MASK (0x200000U)
29897#define DMA_EEI_EEI21_SHIFT (21U)
29902#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
29903
29904#define DMA_EEI_EEI22_MASK (0x400000U)
29905#define DMA_EEI_EEI22_SHIFT (22U)
29910#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
29911
29912#define DMA_EEI_EEI23_MASK (0x800000U)
29913#define DMA_EEI_EEI23_SHIFT (23U)
29918#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
29919
29920#define DMA_EEI_EEI24_MASK (0x1000000U)
29921#define DMA_EEI_EEI24_SHIFT (24U)
29926#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
29927
29928#define DMA_EEI_EEI25_MASK (0x2000000U)
29929#define DMA_EEI_EEI25_SHIFT (25U)
29934#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
29935
29936#define DMA_EEI_EEI26_MASK (0x4000000U)
29937#define DMA_EEI_EEI26_SHIFT (26U)
29942#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
29943
29944#define DMA_EEI_EEI27_MASK (0x8000000U)
29945#define DMA_EEI_EEI27_SHIFT (27U)
29950#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
29951
29952#define DMA_EEI_EEI28_MASK (0x10000000U)
29953#define DMA_EEI_EEI28_SHIFT (28U)
29958#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
29959
29960#define DMA_EEI_EEI29_MASK (0x20000000U)
29961#define DMA_EEI_EEI29_SHIFT (29U)
29966#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
29967
29968#define DMA_EEI_EEI30_MASK (0x40000000U)
29969#define DMA_EEI_EEI30_SHIFT (30U)
29974#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
29975
29976#define DMA_EEI_EEI31_MASK (0x80000000U)
29977#define DMA_EEI_EEI31_SHIFT (31U)
29982#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
29988#define DMA_CEEI_CEEI_MASK (0x1FU)
29989#define DMA_CEEI_CEEI_SHIFT (0U)
29992#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
29993
29994#define DMA_CEEI_CAEE_MASK (0x40U)
29995#define DMA_CEEI_CAEE_SHIFT (6U)
30000#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
30001
30002#define DMA_CEEI_NOP_MASK (0x80U)
30003#define DMA_CEEI_NOP_SHIFT (7U)
30008#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
30014#define DMA_SEEI_SEEI_MASK (0x1FU)
30015#define DMA_SEEI_SEEI_SHIFT (0U)
30018#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
30019
30020#define DMA_SEEI_SAEE_MASK (0x40U)
30021#define DMA_SEEI_SAEE_SHIFT (6U)
30026#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
30027
30028#define DMA_SEEI_NOP_MASK (0x80U)
30029#define DMA_SEEI_NOP_SHIFT (7U)
30034#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
30040#define DMA_CERQ_CERQ_MASK (0x1FU)
30041#define DMA_CERQ_CERQ_SHIFT (0U)
30044#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
30045
30046#define DMA_CERQ_CAER_MASK (0x40U)
30047#define DMA_CERQ_CAER_SHIFT (6U)
30052#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
30053
30054#define DMA_CERQ_NOP_MASK (0x80U)
30055#define DMA_CERQ_NOP_SHIFT (7U)
30060#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
30066#define DMA_SERQ_SERQ_MASK (0x1FU)
30067#define DMA_SERQ_SERQ_SHIFT (0U)
30070#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
30071
30072#define DMA_SERQ_SAER_MASK (0x40U)
30073#define DMA_SERQ_SAER_SHIFT (6U)
30078#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
30079
30080#define DMA_SERQ_NOP_MASK (0x80U)
30081#define DMA_SERQ_NOP_SHIFT (7U)
30086#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
30092#define DMA_CDNE_CDNE_MASK (0x1FU)
30093#define DMA_CDNE_CDNE_SHIFT (0U)
30096#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
30097
30098#define DMA_CDNE_CADN_MASK (0x40U)
30099#define DMA_CDNE_CADN_SHIFT (6U)
30104#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
30105
30106#define DMA_CDNE_NOP_MASK (0x80U)
30107#define DMA_CDNE_NOP_SHIFT (7U)
30112#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
30118#define DMA_SSRT_SSRT_MASK (0x1FU)
30119#define DMA_SSRT_SSRT_SHIFT (0U)
30122#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
30123
30124#define DMA_SSRT_SAST_MASK (0x40U)
30125#define DMA_SSRT_SAST_SHIFT (6U)
30130#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
30131
30132#define DMA_SSRT_NOP_MASK (0x80U)
30133#define DMA_SSRT_NOP_SHIFT (7U)
30138#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
30144#define DMA_CERR_CERR_MASK (0x1FU)
30145#define DMA_CERR_CERR_SHIFT (0U)
30148#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
30149
30150#define DMA_CERR_CAEI_MASK (0x40U)
30151#define DMA_CERR_CAEI_SHIFT (6U)
30156#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
30157
30158#define DMA_CERR_NOP_MASK (0x80U)
30159#define DMA_CERR_NOP_SHIFT (7U)
30164#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
30170#define DMA_CINT_CINT_MASK (0x1FU)
30171#define DMA_CINT_CINT_SHIFT (0U)
30174#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
30175
30176#define DMA_CINT_CAIR_MASK (0x40U)
30177#define DMA_CINT_CAIR_SHIFT (6U)
30182#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
30183
30184#define DMA_CINT_NOP_MASK (0x80U)
30185#define DMA_CINT_NOP_SHIFT (7U)
30190#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
30196#define DMA_INT_INT0_MASK (0x1U)
30197#define DMA_INT_INT0_SHIFT (0U)
30202#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
30203
30204#define DMA_INT_INT1_MASK (0x2U)
30205#define DMA_INT_INT1_SHIFT (1U)
30210#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
30211
30212#define DMA_INT_INT2_MASK (0x4U)
30213#define DMA_INT_INT2_SHIFT (2U)
30218#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
30219
30220#define DMA_INT_INT3_MASK (0x8U)
30221#define DMA_INT_INT3_SHIFT (3U)
30226#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
30227
30228#define DMA_INT_INT4_MASK (0x10U)
30229#define DMA_INT_INT4_SHIFT (4U)
30234#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
30235
30236#define DMA_INT_INT5_MASK (0x20U)
30237#define DMA_INT_INT5_SHIFT (5U)
30242#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
30243
30244#define DMA_INT_INT6_MASK (0x40U)
30245#define DMA_INT_INT6_SHIFT (6U)
30250#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
30251
30252#define DMA_INT_INT7_MASK (0x80U)
30253#define DMA_INT_INT7_SHIFT (7U)
30258#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
30259
30260#define DMA_INT_INT8_MASK (0x100U)
30261#define DMA_INT_INT8_SHIFT (8U)
30266#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
30267
30268#define DMA_INT_INT9_MASK (0x200U)
30269#define DMA_INT_INT9_SHIFT (9U)
30274#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
30275
30276#define DMA_INT_INT10_MASK (0x400U)
30277#define DMA_INT_INT10_SHIFT (10U)
30282#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
30283
30284#define DMA_INT_INT11_MASK (0x800U)
30285#define DMA_INT_INT11_SHIFT (11U)
30290#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
30291
30292#define DMA_INT_INT12_MASK (0x1000U)
30293#define DMA_INT_INT12_SHIFT (12U)
30298#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
30299
30300#define DMA_INT_INT13_MASK (0x2000U)
30301#define DMA_INT_INT13_SHIFT (13U)
30306#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
30307
30308#define DMA_INT_INT14_MASK (0x4000U)
30309#define DMA_INT_INT14_SHIFT (14U)
30314#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
30315
30316#define DMA_INT_INT15_MASK (0x8000U)
30317#define DMA_INT_INT15_SHIFT (15U)
30322#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
30323
30324#define DMA_INT_INT16_MASK (0x10000U)
30325#define DMA_INT_INT16_SHIFT (16U)
30330#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
30331
30332#define DMA_INT_INT17_MASK (0x20000U)
30333#define DMA_INT_INT17_SHIFT (17U)
30338#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
30339
30340#define DMA_INT_INT18_MASK (0x40000U)
30341#define DMA_INT_INT18_SHIFT (18U)
30346#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
30347
30348#define DMA_INT_INT19_MASK (0x80000U)
30349#define DMA_INT_INT19_SHIFT (19U)
30354#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
30355
30356#define DMA_INT_INT20_MASK (0x100000U)
30357#define DMA_INT_INT20_SHIFT (20U)
30362#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
30363
30364#define DMA_INT_INT21_MASK (0x200000U)
30365#define DMA_INT_INT21_SHIFT (21U)
30370#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
30371
30372#define DMA_INT_INT22_MASK (0x400000U)
30373#define DMA_INT_INT22_SHIFT (22U)
30378#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
30379
30380#define DMA_INT_INT23_MASK (0x800000U)
30381#define DMA_INT_INT23_SHIFT (23U)
30386#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
30387
30388#define DMA_INT_INT24_MASK (0x1000000U)
30389#define DMA_INT_INT24_SHIFT (24U)
30394#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
30395
30396#define DMA_INT_INT25_MASK (0x2000000U)
30397#define DMA_INT_INT25_SHIFT (25U)
30402#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
30403
30404#define DMA_INT_INT26_MASK (0x4000000U)
30405#define DMA_INT_INT26_SHIFT (26U)
30410#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
30411
30412#define DMA_INT_INT27_MASK (0x8000000U)
30413#define DMA_INT_INT27_SHIFT (27U)
30418#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
30419
30420#define DMA_INT_INT28_MASK (0x10000000U)
30421#define DMA_INT_INT28_SHIFT (28U)
30426#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
30427
30428#define DMA_INT_INT29_MASK (0x20000000U)
30429#define DMA_INT_INT29_SHIFT (29U)
30434#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
30435
30436#define DMA_INT_INT30_MASK (0x40000000U)
30437#define DMA_INT_INT30_SHIFT (30U)
30442#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
30443
30444#define DMA_INT_INT31_MASK (0x80000000U)
30445#define DMA_INT_INT31_SHIFT (31U)
30450#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
30456#define DMA_ERR_ERR0_MASK (0x1U)
30457#define DMA_ERR_ERR0_SHIFT (0U)
30462#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
30463
30464#define DMA_ERR_ERR1_MASK (0x2U)
30465#define DMA_ERR_ERR1_SHIFT (1U)
30470#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
30471
30472#define DMA_ERR_ERR2_MASK (0x4U)
30473#define DMA_ERR_ERR2_SHIFT (2U)
30478#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
30479
30480#define DMA_ERR_ERR3_MASK (0x8U)
30481#define DMA_ERR_ERR3_SHIFT (3U)
30486#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
30487
30488#define DMA_ERR_ERR4_MASK (0x10U)
30489#define DMA_ERR_ERR4_SHIFT (4U)
30494#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
30495
30496#define DMA_ERR_ERR5_MASK (0x20U)
30497#define DMA_ERR_ERR5_SHIFT (5U)
30502#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
30503
30504#define DMA_ERR_ERR6_MASK (0x40U)
30505#define DMA_ERR_ERR6_SHIFT (6U)
30510#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
30511
30512#define DMA_ERR_ERR7_MASK (0x80U)
30513#define DMA_ERR_ERR7_SHIFT (7U)
30518#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
30519
30520#define DMA_ERR_ERR8_MASK (0x100U)
30521#define DMA_ERR_ERR8_SHIFT (8U)
30526#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
30527
30528#define DMA_ERR_ERR9_MASK (0x200U)
30529#define DMA_ERR_ERR9_SHIFT (9U)
30534#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
30535
30536#define DMA_ERR_ERR10_MASK (0x400U)
30537#define DMA_ERR_ERR10_SHIFT (10U)
30542#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
30543
30544#define DMA_ERR_ERR11_MASK (0x800U)
30545#define DMA_ERR_ERR11_SHIFT (11U)
30550#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
30551
30552#define DMA_ERR_ERR12_MASK (0x1000U)
30553#define DMA_ERR_ERR12_SHIFT (12U)
30558#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
30559
30560#define DMA_ERR_ERR13_MASK (0x2000U)
30561#define DMA_ERR_ERR13_SHIFT (13U)
30566#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
30567
30568#define DMA_ERR_ERR14_MASK (0x4000U)
30569#define DMA_ERR_ERR14_SHIFT (14U)
30574#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
30575
30576#define DMA_ERR_ERR15_MASK (0x8000U)
30577#define DMA_ERR_ERR15_SHIFT (15U)
30582#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
30583
30584#define DMA_ERR_ERR16_MASK (0x10000U)
30585#define DMA_ERR_ERR16_SHIFT (16U)
30590#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
30591
30592#define DMA_ERR_ERR17_MASK (0x20000U)
30593#define DMA_ERR_ERR17_SHIFT (17U)
30598#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
30599
30600#define DMA_ERR_ERR18_MASK (0x40000U)
30601#define DMA_ERR_ERR18_SHIFT (18U)
30606#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
30607
30608#define DMA_ERR_ERR19_MASK (0x80000U)
30609#define DMA_ERR_ERR19_SHIFT (19U)
30614#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
30615
30616#define DMA_ERR_ERR20_MASK (0x100000U)
30617#define DMA_ERR_ERR20_SHIFT (20U)
30622#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
30623
30624#define DMA_ERR_ERR21_MASK (0x200000U)
30625#define DMA_ERR_ERR21_SHIFT (21U)
30630#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
30631
30632#define DMA_ERR_ERR22_MASK (0x400000U)
30633#define DMA_ERR_ERR22_SHIFT (22U)
30638#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
30639
30640#define DMA_ERR_ERR23_MASK (0x800000U)
30641#define DMA_ERR_ERR23_SHIFT (23U)
30646#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
30647
30648#define DMA_ERR_ERR24_MASK (0x1000000U)
30649#define DMA_ERR_ERR24_SHIFT (24U)
30654#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
30655
30656#define DMA_ERR_ERR25_MASK (0x2000000U)
30657#define DMA_ERR_ERR25_SHIFT (25U)
30662#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
30663
30664#define DMA_ERR_ERR26_MASK (0x4000000U)
30665#define DMA_ERR_ERR26_SHIFT (26U)
30670#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
30671
30672#define DMA_ERR_ERR27_MASK (0x8000000U)
30673#define DMA_ERR_ERR27_SHIFT (27U)
30678#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
30679
30680#define DMA_ERR_ERR28_MASK (0x10000000U)
30681#define DMA_ERR_ERR28_SHIFT (28U)
30686#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
30687
30688#define DMA_ERR_ERR29_MASK (0x20000000U)
30689#define DMA_ERR_ERR29_SHIFT (29U)
30694#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
30695
30696#define DMA_ERR_ERR30_MASK (0x40000000U)
30697#define DMA_ERR_ERR30_SHIFT (30U)
30702#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
30703
30704#define DMA_ERR_ERR31_MASK (0x80000000U)
30705#define DMA_ERR_ERR31_SHIFT (31U)
30710#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
30716#define DMA_HRS_HRS0_MASK (0x1U)
30717#define DMA_HRS_HRS0_SHIFT (0U)
30722#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
30723
30724#define DMA_HRS_HRS1_MASK (0x2U)
30725#define DMA_HRS_HRS1_SHIFT (1U)
30730#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
30731
30732#define DMA_HRS_HRS2_MASK (0x4U)
30733#define DMA_HRS_HRS2_SHIFT (2U)
30738#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
30739
30740#define DMA_HRS_HRS3_MASK (0x8U)
30741#define DMA_HRS_HRS3_SHIFT (3U)
30746#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
30747
30748#define DMA_HRS_HRS4_MASK (0x10U)
30749#define DMA_HRS_HRS4_SHIFT (4U)
30754#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
30755
30756#define DMA_HRS_HRS5_MASK (0x20U)
30757#define DMA_HRS_HRS5_SHIFT (5U)
30762#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
30763
30764#define DMA_HRS_HRS6_MASK (0x40U)
30765#define DMA_HRS_HRS6_SHIFT (6U)
30770#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
30771
30772#define DMA_HRS_HRS7_MASK (0x80U)
30773#define DMA_HRS_HRS7_SHIFT (7U)
30778#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
30779
30780#define DMA_HRS_HRS8_MASK (0x100U)
30781#define DMA_HRS_HRS8_SHIFT (8U)
30786#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
30787
30788#define DMA_HRS_HRS9_MASK (0x200U)
30789#define DMA_HRS_HRS9_SHIFT (9U)
30794#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
30795
30796#define DMA_HRS_HRS10_MASK (0x400U)
30797#define DMA_HRS_HRS10_SHIFT (10U)
30802#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
30803
30804#define DMA_HRS_HRS11_MASK (0x800U)
30805#define DMA_HRS_HRS11_SHIFT (11U)
30810#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
30811
30812#define DMA_HRS_HRS12_MASK (0x1000U)
30813#define DMA_HRS_HRS12_SHIFT (12U)
30818#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
30819
30820#define DMA_HRS_HRS13_MASK (0x2000U)
30821#define DMA_HRS_HRS13_SHIFT (13U)
30826#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
30827
30828#define DMA_HRS_HRS14_MASK (0x4000U)
30829#define DMA_HRS_HRS14_SHIFT (14U)
30834#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
30835
30836#define DMA_HRS_HRS15_MASK (0x8000U)
30837#define DMA_HRS_HRS15_SHIFT (15U)
30842#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
30843
30844#define DMA_HRS_HRS16_MASK (0x10000U)
30845#define DMA_HRS_HRS16_SHIFT (16U)
30850#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
30851
30852#define DMA_HRS_HRS17_MASK (0x20000U)
30853#define DMA_HRS_HRS17_SHIFT (17U)
30858#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
30859
30860#define DMA_HRS_HRS18_MASK (0x40000U)
30861#define DMA_HRS_HRS18_SHIFT (18U)
30866#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
30867
30868#define DMA_HRS_HRS19_MASK (0x80000U)
30869#define DMA_HRS_HRS19_SHIFT (19U)
30874#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
30875
30876#define DMA_HRS_HRS20_MASK (0x100000U)
30877#define DMA_HRS_HRS20_SHIFT (20U)
30882#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
30883
30884#define DMA_HRS_HRS21_MASK (0x200000U)
30885#define DMA_HRS_HRS21_SHIFT (21U)
30890#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
30891
30892#define DMA_HRS_HRS22_MASK (0x400000U)
30893#define DMA_HRS_HRS22_SHIFT (22U)
30898#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
30899
30900#define DMA_HRS_HRS23_MASK (0x800000U)
30901#define DMA_HRS_HRS23_SHIFT (23U)
30906#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
30907
30908#define DMA_HRS_HRS24_MASK (0x1000000U)
30909#define DMA_HRS_HRS24_SHIFT (24U)
30914#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
30915
30916#define DMA_HRS_HRS25_MASK (0x2000000U)
30917#define DMA_HRS_HRS25_SHIFT (25U)
30922#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
30923
30924#define DMA_HRS_HRS26_MASK (0x4000000U)
30925#define DMA_HRS_HRS26_SHIFT (26U)
30930#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
30931
30932#define DMA_HRS_HRS27_MASK (0x8000000U)
30933#define DMA_HRS_HRS27_SHIFT (27U)
30938#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
30939
30940#define DMA_HRS_HRS28_MASK (0x10000000U)
30941#define DMA_HRS_HRS28_SHIFT (28U)
30946#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
30947
30948#define DMA_HRS_HRS29_MASK (0x20000000U)
30949#define DMA_HRS_HRS29_SHIFT (29U)
30954#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
30955
30956#define DMA_HRS_HRS30_MASK (0x40000000U)
30957#define DMA_HRS_HRS30_SHIFT (30U)
30962#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
30963
30964#define DMA_HRS_HRS31_MASK (0x80000000U)
30965#define DMA_HRS_HRS31_SHIFT (31U)
30970#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
30976#define DMA_EARS_EDREQ_0_MASK (0x1U)
30977#define DMA_EARS_EDREQ_0_SHIFT (0U)
30982#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
30983
30984#define DMA_EARS_EDREQ_1_MASK (0x2U)
30985#define DMA_EARS_EDREQ_1_SHIFT (1U)
30990#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
30991
30992#define DMA_EARS_EDREQ_2_MASK (0x4U)
30993#define DMA_EARS_EDREQ_2_SHIFT (2U)
30998#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
30999
31000#define DMA_EARS_EDREQ_3_MASK (0x8U)
31001#define DMA_EARS_EDREQ_3_SHIFT (3U)
31006#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
31007
31008#define DMA_EARS_EDREQ_4_MASK (0x10U)
31009#define DMA_EARS_EDREQ_4_SHIFT (4U)
31014#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
31015
31016#define DMA_EARS_EDREQ_5_MASK (0x20U)
31017#define DMA_EARS_EDREQ_5_SHIFT (5U)
31022#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
31023
31024#define DMA_EARS_EDREQ_6_MASK (0x40U)
31025#define DMA_EARS_EDREQ_6_SHIFT (6U)
31030#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
31031
31032#define DMA_EARS_EDREQ_7_MASK (0x80U)
31033#define DMA_EARS_EDREQ_7_SHIFT (7U)
31038#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
31039
31040#define DMA_EARS_EDREQ_8_MASK (0x100U)
31041#define DMA_EARS_EDREQ_8_SHIFT (8U)
31046#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
31047
31048#define DMA_EARS_EDREQ_9_MASK (0x200U)
31049#define DMA_EARS_EDREQ_9_SHIFT (9U)
31054#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
31055
31056#define DMA_EARS_EDREQ_10_MASK (0x400U)
31057#define DMA_EARS_EDREQ_10_SHIFT (10U)
31062#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
31063
31064#define DMA_EARS_EDREQ_11_MASK (0x800U)
31065#define DMA_EARS_EDREQ_11_SHIFT (11U)
31070#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
31071
31072#define DMA_EARS_EDREQ_12_MASK (0x1000U)
31073#define DMA_EARS_EDREQ_12_SHIFT (12U)
31078#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
31079
31080#define DMA_EARS_EDREQ_13_MASK (0x2000U)
31081#define DMA_EARS_EDREQ_13_SHIFT (13U)
31086#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
31087
31088#define DMA_EARS_EDREQ_14_MASK (0x4000U)
31089#define DMA_EARS_EDREQ_14_SHIFT (14U)
31094#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
31095
31096#define DMA_EARS_EDREQ_15_MASK (0x8000U)
31097#define DMA_EARS_EDREQ_15_SHIFT (15U)
31102#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
31103
31104#define DMA_EARS_EDREQ_16_MASK (0x10000U)
31105#define DMA_EARS_EDREQ_16_SHIFT (16U)
31110#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
31111
31112#define DMA_EARS_EDREQ_17_MASK (0x20000U)
31113#define DMA_EARS_EDREQ_17_SHIFT (17U)
31118#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
31119
31120#define DMA_EARS_EDREQ_18_MASK (0x40000U)
31121#define DMA_EARS_EDREQ_18_SHIFT (18U)
31126#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
31127
31128#define DMA_EARS_EDREQ_19_MASK (0x80000U)
31129#define DMA_EARS_EDREQ_19_SHIFT (19U)
31134#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
31135
31136#define DMA_EARS_EDREQ_20_MASK (0x100000U)
31137#define DMA_EARS_EDREQ_20_SHIFT (20U)
31142#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
31143
31144#define DMA_EARS_EDREQ_21_MASK (0x200000U)
31145#define DMA_EARS_EDREQ_21_SHIFT (21U)
31150#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
31151
31152#define DMA_EARS_EDREQ_22_MASK (0x400000U)
31153#define DMA_EARS_EDREQ_22_SHIFT (22U)
31158#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
31159
31160#define DMA_EARS_EDREQ_23_MASK (0x800000U)
31161#define DMA_EARS_EDREQ_23_SHIFT (23U)
31166#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
31167
31168#define DMA_EARS_EDREQ_24_MASK (0x1000000U)
31169#define DMA_EARS_EDREQ_24_SHIFT (24U)
31174#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
31175
31176#define DMA_EARS_EDREQ_25_MASK (0x2000000U)
31177#define DMA_EARS_EDREQ_25_SHIFT (25U)
31182#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
31183
31184#define DMA_EARS_EDREQ_26_MASK (0x4000000U)
31185#define DMA_EARS_EDREQ_26_SHIFT (26U)
31190#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
31191
31192#define DMA_EARS_EDREQ_27_MASK (0x8000000U)
31193#define DMA_EARS_EDREQ_27_SHIFT (27U)
31198#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
31199
31200#define DMA_EARS_EDREQ_28_MASK (0x10000000U)
31201#define DMA_EARS_EDREQ_28_SHIFT (28U)
31206#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
31207
31208#define DMA_EARS_EDREQ_29_MASK (0x20000000U)
31209#define DMA_EARS_EDREQ_29_SHIFT (29U)
31214#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
31215
31216#define DMA_EARS_EDREQ_30_MASK (0x40000000U)
31217#define DMA_EARS_EDREQ_30_SHIFT (30U)
31222#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
31223
31224#define DMA_EARS_EDREQ_31_MASK (0x80000000U)
31225#define DMA_EARS_EDREQ_31_SHIFT (31U)
31230#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
31236#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
31237#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
31240#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
31241
31242#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
31243#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
31246#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
31247
31248#define DMA_DCHPRI3_DPA_MASK (0x40U)
31249#define DMA_DCHPRI3_DPA_SHIFT (6U)
31254#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
31255
31256#define DMA_DCHPRI3_ECP_MASK (0x80U)
31257#define DMA_DCHPRI3_ECP_SHIFT (7U)
31262#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
31268#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
31269#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
31272#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
31273
31274#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
31275#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
31278#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
31279
31280#define DMA_DCHPRI2_DPA_MASK (0x40U)
31281#define DMA_DCHPRI2_DPA_SHIFT (6U)
31286#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
31287
31288#define DMA_DCHPRI2_ECP_MASK (0x80U)
31289#define DMA_DCHPRI2_ECP_SHIFT (7U)
31294#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
31300#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
31301#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
31304#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
31305
31306#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
31307#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
31310#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
31311
31312#define DMA_DCHPRI1_DPA_MASK (0x40U)
31313#define DMA_DCHPRI1_DPA_SHIFT (6U)
31318#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
31319
31320#define DMA_DCHPRI1_ECP_MASK (0x80U)
31321#define DMA_DCHPRI1_ECP_SHIFT (7U)
31326#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
31332#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
31333#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
31336#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
31337
31338#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
31339#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
31342#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
31343
31344#define DMA_DCHPRI0_DPA_MASK (0x40U)
31345#define DMA_DCHPRI0_DPA_SHIFT (6U)
31350#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
31351
31352#define DMA_DCHPRI0_ECP_MASK (0x80U)
31353#define DMA_DCHPRI0_ECP_SHIFT (7U)
31358#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
31364#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
31365#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
31368#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
31369
31370#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
31371#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
31374#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
31375
31376#define DMA_DCHPRI7_DPA_MASK (0x40U)
31377#define DMA_DCHPRI7_DPA_SHIFT (6U)
31382#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
31383
31384#define DMA_DCHPRI7_ECP_MASK (0x80U)
31385#define DMA_DCHPRI7_ECP_SHIFT (7U)
31390#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
31396#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
31397#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
31400#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
31401
31402#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
31403#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
31406#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
31407
31408#define DMA_DCHPRI6_DPA_MASK (0x40U)
31409#define DMA_DCHPRI6_DPA_SHIFT (6U)
31414#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
31415
31416#define DMA_DCHPRI6_ECP_MASK (0x80U)
31417#define DMA_DCHPRI6_ECP_SHIFT (7U)
31422#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
31428#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
31429#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
31432#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
31433
31434#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
31435#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
31438#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
31439
31440#define DMA_DCHPRI5_DPA_MASK (0x40U)
31441#define DMA_DCHPRI5_DPA_SHIFT (6U)
31446#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
31447
31448#define DMA_DCHPRI5_ECP_MASK (0x80U)
31449#define DMA_DCHPRI5_ECP_SHIFT (7U)
31454#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
31460#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
31461#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
31464#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
31465
31466#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
31467#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
31470#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
31471
31472#define DMA_DCHPRI4_DPA_MASK (0x40U)
31473#define DMA_DCHPRI4_DPA_SHIFT (6U)
31478#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
31479
31480#define DMA_DCHPRI4_ECP_MASK (0x80U)
31481#define DMA_DCHPRI4_ECP_SHIFT (7U)
31486#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
31492#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
31493#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
31496#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
31497
31498#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
31499#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
31502#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
31503
31504#define DMA_DCHPRI11_DPA_MASK (0x40U)
31505#define DMA_DCHPRI11_DPA_SHIFT (6U)
31510#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
31511
31512#define DMA_DCHPRI11_ECP_MASK (0x80U)
31513#define DMA_DCHPRI11_ECP_SHIFT (7U)
31518#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
31524#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
31525#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
31528#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
31529
31530#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
31531#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
31534#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
31535
31536#define DMA_DCHPRI10_DPA_MASK (0x40U)
31537#define DMA_DCHPRI10_DPA_SHIFT (6U)
31542#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
31543
31544#define DMA_DCHPRI10_ECP_MASK (0x80U)
31545#define DMA_DCHPRI10_ECP_SHIFT (7U)
31550#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
31556#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
31557#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
31560#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
31561
31562#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
31563#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
31566#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
31567
31568#define DMA_DCHPRI9_DPA_MASK (0x40U)
31569#define DMA_DCHPRI9_DPA_SHIFT (6U)
31574#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
31575
31576#define DMA_DCHPRI9_ECP_MASK (0x80U)
31577#define DMA_DCHPRI9_ECP_SHIFT (7U)
31582#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
31588#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
31589#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
31592#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
31593
31594#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
31595#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
31598#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
31599
31600#define DMA_DCHPRI8_DPA_MASK (0x40U)
31601#define DMA_DCHPRI8_DPA_SHIFT (6U)
31606#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
31607
31608#define DMA_DCHPRI8_ECP_MASK (0x80U)
31609#define DMA_DCHPRI8_ECP_SHIFT (7U)
31614#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
31620#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
31621#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
31624#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
31625
31626#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
31627#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
31630#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
31631
31632#define DMA_DCHPRI15_DPA_MASK (0x40U)
31633#define DMA_DCHPRI15_DPA_SHIFT (6U)
31638#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
31639
31640#define DMA_DCHPRI15_ECP_MASK (0x80U)
31641#define DMA_DCHPRI15_ECP_SHIFT (7U)
31646#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
31652#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
31653#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
31656#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
31657
31658#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
31659#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
31662#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
31663
31664#define DMA_DCHPRI14_DPA_MASK (0x40U)
31665#define DMA_DCHPRI14_DPA_SHIFT (6U)
31670#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
31671
31672#define DMA_DCHPRI14_ECP_MASK (0x80U)
31673#define DMA_DCHPRI14_ECP_SHIFT (7U)
31678#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
31684#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
31685#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
31688#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
31689
31690#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
31691#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
31694#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
31695
31696#define DMA_DCHPRI13_DPA_MASK (0x40U)
31697#define DMA_DCHPRI13_DPA_SHIFT (6U)
31702#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
31703
31704#define DMA_DCHPRI13_ECP_MASK (0x80U)
31705#define DMA_DCHPRI13_ECP_SHIFT (7U)
31710#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
31716#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
31717#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
31720#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
31721
31722#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
31723#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
31726#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
31727
31728#define DMA_DCHPRI12_DPA_MASK (0x40U)
31729#define DMA_DCHPRI12_DPA_SHIFT (6U)
31734#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
31735
31736#define DMA_DCHPRI12_ECP_MASK (0x80U)
31737#define DMA_DCHPRI12_ECP_SHIFT (7U)
31742#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
31748#define DMA_DCHPRI19_CHPRI_MASK (0xFU)
31749#define DMA_DCHPRI19_CHPRI_SHIFT (0U)
31752#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
31753
31754#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
31755#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
31758#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
31759
31760#define DMA_DCHPRI19_DPA_MASK (0x40U)
31761#define DMA_DCHPRI19_DPA_SHIFT (6U)
31766#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
31767
31768#define DMA_DCHPRI19_ECP_MASK (0x80U)
31769#define DMA_DCHPRI19_ECP_SHIFT (7U)
31774#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
31780#define DMA_DCHPRI18_CHPRI_MASK (0xFU)
31781#define DMA_DCHPRI18_CHPRI_SHIFT (0U)
31784#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
31785
31786#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
31787#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
31790#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
31791
31792#define DMA_DCHPRI18_DPA_MASK (0x40U)
31793#define DMA_DCHPRI18_DPA_SHIFT (6U)
31798#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
31799
31800#define DMA_DCHPRI18_ECP_MASK (0x80U)
31801#define DMA_DCHPRI18_ECP_SHIFT (7U)
31806#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
31812#define DMA_DCHPRI17_CHPRI_MASK (0xFU)
31813#define DMA_DCHPRI17_CHPRI_SHIFT (0U)
31816#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
31817
31818#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
31819#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
31822#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
31823
31824#define DMA_DCHPRI17_DPA_MASK (0x40U)
31825#define DMA_DCHPRI17_DPA_SHIFT (6U)
31830#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
31831
31832#define DMA_DCHPRI17_ECP_MASK (0x80U)
31833#define DMA_DCHPRI17_ECP_SHIFT (7U)
31838#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
31844#define DMA_DCHPRI16_CHPRI_MASK (0xFU)
31845#define DMA_DCHPRI16_CHPRI_SHIFT (0U)
31848#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
31849
31850#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
31851#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
31854#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
31855
31856#define DMA_DCHPRI16_DPA_MASK (0x40U)
31857#define DMA_DCHPRI16_DPA_SHIFT (6U)
31862#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
31863
31864#define DMA_DCHPRI16_ECP_MASK (0x80U)
31865#define DMA_DCHPRI16_ECP_SHIFT (7U)
31870#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
31876#define DMA_DCHPRI23_CHPRI_MASK (0xFU)
31877#define DMA_DCHPRI23_CHPRI_SHIFT (0U)
31880#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
31881
31882#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
31883#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
31886#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
31887
31888#define DMA_DCHPRI23_DPA_MASK (0x40U)
31889#define DMA_DCHPRI23_DPA_SHIFT (6U)
31894#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
31895
31896#define DMA_DCHPRI23_ECP_MASK (0x80U)
31897#define DMA_DCHPRI23_ECP_SHIFT (7U)
31902#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
31908#define DMA_DCHPRI22_CHPRI_MASK (0xFU)
31909#define DMA_DCHPRI22_CHPRI_SHIFT (0U)
31912#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
31913
31914#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
31915#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
31918#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
31919
31920#define DMA_DCHPRI22_DPA_MASK (0x40U)
31921#define DMA_DCHPRI22_DPA_SHIFT (6U)
31926#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
31927
31928#define DMA_DCHPRI22_ECP_MASK (0x80U)
31929#define DMA_DCHPRI22_ECP_SHIFT (7U)
31934#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
31940#define DMA_DCHPRI21_CHPRI_MASK (0xFU)
31941#define DMA_DCHPRI21_CHPRI_SHIFT (0U)
31944#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
31945
31946#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
31947#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
31950#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
31951
31952#define DMA_DCHPRI21_DPA_MASK (0x40U)
31953#define DMA_DCHPRI21_DPA_SHIFT (6U)
31958#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
31959
31960#define DMA_DCHPRI21_ECP_MASK (0x80U)
31961#define DMA_DCHPRI21_ECP_SHIFT (7U)
31966#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
31972#define DMA_DCHPRI20_CHPRI_MASK (0xFU)
31973#define DMA_DCHPRI20_CHPRI_SHIFT (0U)
31976#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
31977
31978#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
31979#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
31982#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
31983
31984#define DMA_DCHPRI20_DPA_MASK (0x40U)
31985#define DMA_DCHPRI20_DPA_SHIFT (6U)
31990#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
31991
31992#define DMA_DCHPRI20_ECP_MASK (0x80U)
31993#define DMA_DCHPRI20_ECP_SHIFT (7U)
31998#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
32004#define DMA_DCHPRI27_CHPRI_MASK (0xFU)
32005#define DMA_DCHPRI27_CHPRI_SHIFT (0U)
32008#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
32009
32010#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
32011#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
32014#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
32015
32016#define DMA_DCHPRI27_DPA_MASK (0x40U)
32017#define DMA_DCHPRI27_DPA_SHIFT (6U)
32022#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
32023
32024#define DMA_DCHPRI27_ECP_MASK (0x80U)
32025#define DMA_DCHPRI27_ECP_SHIFT (7U)
32030#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
32036#define DMA_DCHPRI26_CHPRI_MASK (0xFU)
32037#define DMA_DCHPRI26_CHPRI_SHIFT (0U)
32040#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
32041
32042#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
32043#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
32046#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
32047
32048#define DMA_DCHPRI26_DPA_MASK (0x40U)
32049#define DMA_DCHPRI26_DPA_SHIFT (6U)
32054#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
32055
32056#define DMA_DCHPRI26_ECP_MASK (0x80U)
32057#define DMA_DCHPRI26_ECP_SHIFT (7U)
32062#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
32068#define DMA_DCHPRI25_CHPRI_MASK (0xFU)
32069#define DMA_DCHPRI25_CHPRI_SHIFT (0U)
32072#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
32073
32074#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
32075#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
32078#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
32079
32080#define DMA_DCHPRI25_DPA_MASK (0x40U)
32081#define DMA_DCHPRI25_DPA_SHIFT (6U)
32086#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
32087
32088#define DMA_DCHPRI25_ECP_MASK (0x80U)
32089#define DMA_DCHPRI25_ECP_SHIFT (7U)
32094#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
32100#define DMA_DCHPRI24_CHPRI_MASK (0xFU)
32101#define DMA_DCHPRI24_CHPRI_SHIFT (0U)
32104#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
32105
32106#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
32107#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
32110#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
32111
32112#define DMA_DCHPRI24_DPA_MASK (0x40U)
32113#define DMA_DCHPRI24_DPA_SHIFT (6U)
32118#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
32119
32120#define DMA_DCHPRI24_ECP_MASK (0x80U)
32121#define DMA_DCHPRI24_ECP_SHIFT (7U)
32126#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
32132#define DMA_DCHPRI31_CHPRI_MASK (0xFU)
32133#define DMA_DCHPRI31_CHPRI_SHIFT (0U)
32136#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
32137
32138#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
32139#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
32142#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
32143
32144#define DMA_DCHPRI31_DPA_MASK (0x40U)
32145#define DMA_DCHPRI31_DPA_SHIFT (6U)
32150#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
32151
32152#define DMA_DCHPRI31_ECP_MASK (0x80U)
32153#define DMA_DCHPRI31_ECP_SHIFT (7U)
32158#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
32164#define DMA_DCHPRI30_CHPRI_MASK (0xFU)
32165#define DMA_DCHPRI30_CHPRI_SHIFT (0U)
32168#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
32169
32170#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
32171#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
32174#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
32175
32176#define DMA_DCHPRI30_DPA_MASK (0x40U)
32177#define DMA_DCHPRI30_DPA_SHIFT (6U)
32182#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
32183
32184#define DMA_DCHPRI30_ECP_MASK (0x80U)
32185#define DMA_DCHPRI30_ECP_SHIFT (7U)
32190#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
32196#define DMA_DCHPRI29_CHPRI_MASK (0xFU)
32197#define DMA_DCHPRI29_CHPRI_SHIFT (0U)
32200#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
32201
32202#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
32203#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
32206#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
32207
32208#define DMA_DCHPRI29_DPA_MASK (0x40U)
32209#define DMA_DCHPRI29_DPA_SHIFT (6U)
32214#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
32215
32216#define DMA_DCHPRI29_ECP_MASK (0x80U)
32217#define DMA_DCHPRI29_ECP_SHIFT (7U)
32222#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
32228#define DMA_DCHPRI28_CHPRI_MASK (0xFU)
32229#define DMA_DCHPRI28_CHPRI_SHIFT (0U)
32232#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
32233
32234#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
32235#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
32238#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
32239
32240#define DMA_DCHPRI28_DPA_MASK (0x40U)
32241#define DMA_DCHPRI28_DPA_SHIFT (6U)
32246#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
32247
32248#define DMA_DCHPRI28_ECP_MASK (0x80U)
32249#define DMA_DCHPRI28_ECP_SHIFT (7U)
32254#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
32260#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
32261#define DMA_SADDR_SADDR_SHIFT (0U)
32264#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
32267/* The count of DMA_SADDR */
32268#define DMA_SADDR_COUNT (32U)
32269
32273#define DMA_SOFF_SOFF_MASK (0xFFFFU)
32274#define DMA_SOFF_SOFF_SHIFT (0U)
32277#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
32280/* The count of DMA_SOFF */
32281#define DMA_SOFF_COUNT (32U)
32282
32286#define DMA_ATTR_DSIZE_MASK (0x7U)
32287#define DMA_ATTR_DSIZE_SHIFT (0U)
32290#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
32291
32292#define DMA_ATTR_DMOD_MASK (0xF8U)
32293#define DMA_ATTR_DMOD_SHIFT (3U)
32296#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
32297
32298#define DMA_ATTR_SSIZE_MASK (0x700U)
32299#define DMA_ATTR_SSIZE_SHIFT (8U)
32310#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
32311
32312#define DMA_ATTR_SMOD_MASK (0xF800U)
32313#define DMA_ATTR_SMOD_SHIFT (11U)
32318#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
32321/* The count of DMA_ATTR */
32322#define DMA_ATTR_COUNT (32U)
32323
32327#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
32328#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
32331#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
32334/* The count of DMA_NBYTES_MLNO */
32335#define DMA_NBYTES_MLNO_COUNT (32U)
32336
32340#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
32341#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
32344#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
32345
32346#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
32347#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
32352#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
32353
32354#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
32355#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
32360#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
32363/* The count of DMA_NBYTES_MLOFFNO */
32364#define DMA_NBYTES_MLOFFNO_COUNT (32U)
32365
32369#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
32370#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
32373#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
32374
32375#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
32376#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
32380#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
32381
32382#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
32383#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
32388#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
32389
32390#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
32391#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
32396#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
32399/* The count of DMA_NBYTES_MLOFFYES */
32400#define DMA_NBYTES_MLOFFYES_COUNT (32U)
32401
32405#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
32406#define DMA_SLAST_SLAST_SHIFT (0U)
32409#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
32412/* The count of DMA_SLAST */
32413#define DMA_SLAST_COUNT (32U)
32414
32418#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
32419#define DMA_DADDR_DADDR_SHIFT (0U)
32422#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
32425/* The count of DMA_DADDR */
32426#define DMA_DADDR_COUNT (32U)
32427
32431#define DMA_DOFF_DOFF_MASK (0xFFFFU)
32432#define DMA_DOFF_DOFF_SHIFT (0U)
32435#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
32438/* The count of DMA_DOFF */
32439#define DMA_DOFF_COUNT (32U)
32440
32444#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
32445#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
32448#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
32449
32450#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
32451#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
32456#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
32459/* The count of DMA_CITER_ELINKNO */
32460#define DMA_CITER_ELINKNO_COUNT (32U)
32461
32465#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
32466#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
32469#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
32470
32471#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
32472#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
32475#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
32476
32477#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
32478#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
32483#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
32486/* The count of DMA_CITER_ELINKYES */
32487#define DMA_CITER_ELINKYES_COUNT (32U)
32488
32492#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
32493#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
32496#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
32499/* The count of DMA_DLAST_SGA */
32500#define DMA_DLAST_SGA_COUNT (32U)
32501
32505#define DMA_CSR_START_MASK (0x1U)
32506#define DMA_CSR_START_SHIFT (0U)
32511#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
32512
32513#define DMA_CSR_INTMAJOR_MASK (0x2U)
32514#define DMA_CSR_INTMAJOR_SHIFT (1U)
32519#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
32520
32521#define DMA_CSR_INTHALF_MASK (0x4U)
32522#define DMA_CSR_INTHALF_SHIFT (2U)
32527#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
32528
32529#define DMA_CSR_DREQ_MASK (0x8U)
32530#define DMA_CSR_DREQ_SHIFT (3U)
32535#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
32536
32537#define DMA_CSR_ESG_MASK (0x10U)
32538#define DMA_CSR_ESG_SHIFT (4U)
32543#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
32544
32545#define DMA_CSR_MAJORELINK_MASK (0x20U)
32546#define DMA_CSR_MAJORELINK_SHIFT (5U)
32551#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
32552
32553#define DMA_CSR_ACTIVE_MASK (0x40U)
32554#define DMA_CSR_ACTIVE_SHIFT (6U)
32557#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
32558
32559#define DMA_CSR_DONE_MASK (0x80U)
32560#define DMA_CSR_DONE_SHIFT (7U)
32563#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
32564
32565#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
32566#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
32569#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
32570
32571#define DMA_CSR_BWC_MASK (0xC000U)
32572#define DMA_CSR_BWC_SHIFT (14U)
32579#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
32582/* The count of DMA_CSR */
32583#define DMA_CSR_COUNT (32U)
32584
32588#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
32589#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
32592#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
32593
32594#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
32595#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
32600#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
32603/* The count of DMA_BITER_ELINKNO */
32604#define DMA_BITER_ELINKNO_COUNT (32U)
32605
32609#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
32610#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
32613#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
32614
32615#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
32616#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
32619#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
32620
32621#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
32622#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
32627#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
32630/* The count of DMA_BITER_ELINKYES */
32631#define DMA_BITER_ELINKYES_COUNT (32U)
32632
32633 /* end of group DMA_Register_Masks */
32637
32638
32639/* DMA - Peripheral instance base addresses */
32641#define DMA0_BASE (0x40070000u)
32643#define DMA0 ((DMA_Type *)DMA0_BASE)
32645#define DMA_BASE_ADDRS { DMA0_BASE }
32647#define DMA_BASE_PTRS { DMA0 }
32649#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
32650#define DMA_ERROR_IRQS { DMA_ERROR_IRQn }
32651 /* end of group DMA_Peripheral_Access_Layer */
32655
32656
32657/* ----------------------------------------------------------------------------
32658 -- DMAMUX Peripheral Access Layer
32659 ---------------------------------------------------------------------------- */
32660
32667typedef struct {
32668 __IO uint32_t CHCFG[32];
32669} DMAMUX_Type;
32670
32671/* ----------------------------------------------------------------------------
32672 -- DMAMUX Register Masks
32673 ---------------------------------------------------------------------------- */
32674
32683#define DMAMUX_CHCFG_SOURCE_MASK (0xFFU)
32684#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
32687#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
32688
32689#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U)
32690#define DMAMUX_CHCFG_A_ON_SHIFT (29U)
32695#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
32696
32697#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U)
32698#define DMAMUX_CHCFG_TRIG_SHIFT (30U)
32704#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
32705
32706#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U)
32707#define DMAMUX_CHCFG_ENBL_SHIFT (31U)
32712#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
32715/* The count of DMAMUX_CHCFG */
32716#define DMAMUX_CHCFG_COUNT (32U)
32717
32718 /* end of group DMAMUX_Register_Masks */
32722
32723
32724/* DMAMUX - Peripheral instance base addresses */
32726#define DMAMUX0_BASE (0x40074000u)
32728#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
32730#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
32732#define DMAMUX_BASE_PTRS { DMAMUX0 }
32733 /* end of group DMAMUX_Peripheral_Access_Layer */
32737
32738
32739/* ----------------------------------------------------------------------------
32740 -- DSI_HOST Peripheral Access Layer
32741 ---------------------------------------------------------------------------- */
32742
32749typedef struct {
32750 __IO uint32_t CFG_NUM_LANES;
32751 __IO uint32_t CFG_NONCONTINUOUS_CLK;
32752 __IO uint32_t CFG_T_PRE;
32753 __IO uint32_t CFG_T_POST;
32754 __IO uint32_t CFG_TX_GAP;
32755 __IO uint32_t CFG_AUTOINSERT_EOTP;
32756 __IO uint32_t CFG_EXTRA_CMDS_AFTER_EOTP;
32757 __IO uint32_t CFG_HTX_TO_COUNT;
32758 __IO uint32_t CFG_LRX_H_TO_COUNT;
32759 __IO uint32_t CFG_BTA_H_TO_COUNT;
32760 __IO uint32_t CFG_TWAKEUP;
32761 __I uint32_t CFG_STATUS_OUT;
32762 __I uint32_t RX_ERROR_STATUS;
32764
32765/* ----------------------------------------------------------------------------
32766 -- DSI_HOST Register Masks
32767 ---------------------------------------------------------------------------- */
32768
32777#define DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK (0x3U)
32778#define DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT (0U)
32783#define DSI_HOST_CFG_NUM_LANES_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT)) & DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK)
32789#define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK (0x1U)
32790#define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT (0U)
32796#define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT)) & DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK)
32802#define DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK (0xFFU)
32803#define DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT (0U)
32809#define DSI_HOST_CFG_T_PRE_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK)
32815#define DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK (0xFFU)
32816#define DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT (0U)
32823#define DSI_HOST_CFG_T_POST_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK)
32829#define DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK (0xFFU)
32830#define DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT (0U)
32836#define DSI_HOST_CFG_TX_GAP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK)
32842#define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK (0x1U)
32843#define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT (0U)
32848#define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT)) & DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK)
32854#define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK (0xFFU)
32855#define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT (0U)
32859#define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT)) & DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK)
32865#define DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK (0xFFFFFFU)
32866#define DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT (0U)
32871#define DSI_HOST_CFG_HTX_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK)
32877#define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK (0xFFFFFFU)
32878#define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT (0U)
32883#define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK)
32889#define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK (0xFFFFFFU)
32890#define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT (0U)
32894#define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK)
32900#define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK (0x7FFFFU)
32901#define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT (0U)
32906#define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK)
32912#define DSI_HOST_CFG_STATUS_OUT_STATUS_MASK (0xFFFFFFFFU)
32913#define DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT (0U)
32916#define DSI_HOST_CFG_STATUS_OUT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT)) & DSI_HOST_CFG_STATUS_OUT_STATUS_MASK)
32922#define DSI_HOST_RX_ERROR_STATUS_STATUS_MASK (0x7FFU)
32923#define DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT (0U)
32926#define DSI_HOST_RX_ERROR_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT)) & DSI_HOST_RX_ERROR_STATUS_STATUS_MASK) /* end of group DSI_HOST_Register_Masks */
32933
32934
32935/* DSI_HOST - Peripheral instance base addresses */
32937#define DSI_HOST_BASE (0x4080C000u)
32939#define DSI_HOST ((DSI_HOST_Type *)DSI_HOST_BASE)
32941#define DSI_HOST_BASE_ADDRS { DSI_HOST_BASE }
32943#define DSI_HOST_BASE_PTRS { DSI_HOST }
32945#define DSI_HOST_DSI_IRQS { MIPI_DSI_IRQn }
32946 /* end of group DSI_HOST_Peripheral_Access_Layer */
32950
32951
32952/* ----------------------------------------------------------------------------
32953 -- DSI_HOST_APB_PKT_IF Peripheral Access Layer
32954 ---------------------------------------------------------------------------- */
32955
32962typedef struct {
32963 __IO uint32_t TX_PAYLOAD;
32964 __IO uint32_t PKT_CONTROL;
32965 __IO uint32_t SEND_PACKET;
32966 __I uint32_t PKT_STATUS;
32967 __I uint32_t PKT_FIFO_WR_LEVEL;
32968 __I uint32_t PKT_FIFO_RD_LEVEL;
32969 __I uint32_t PKT_RX_PAYLOAD;
32970 __I uint32_t PKT_RX_PKT_HEADER;
32971 __I uint32_t IRQ_STATUS;
32972 __I uint32_t IRQ_STATUS2;
32973 __IO uint32_t IRQ_MASK;
32974 __IO uint32_t IRQ_MASK2;
32976
32977/* ----------------------------------------------------------------------------
32978 -- DSI_HOST_APB_PKT_IF Register Masks
32979 ---------------------------------------------------------------------------- */
32980
32989#define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU)
32990#define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT (0U)
32993#define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK)
32999#define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK (0x7FFFFFFU)
33000#define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT (0U)
33003#define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK)
33009#define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK (0x1U)
33010#define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT (0U)
33015#define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT)) & DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK)
33021#define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK (0x1FFU)
33022#define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT (0U)
33025#define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK)
33031#define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK (0xFFFFU)
33032#define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT (0U)
33035#define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK)
33041#define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK (0xFFFFU)
33042#define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT (0U)
33045#define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK)
33051#define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU)
33052#define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT (0U)
33055#define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK)
33061#define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK (0xFFFFFFU)
33062#define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT (0U)
33065#define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK)
33071#define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK (0xFFFFFFFFU)
33072#define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT (0U)
33075#define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK)
33081#define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK (0x7U)
33082#define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT (0U)
33086#define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK)
33092#define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK (0xFFFFFFFFU)
33093#define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT (0U)
33096#define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK)
33102#define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK (0x7U)
33103#define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT (0U)
33106#define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK) /* end of group DSI_HOST_APB_PKT_IF_Register_Masks */
33113
33114
33115/* DSI_HOST_APB_PKT_IF - Peripheral instance base addresses */
33117#define DSI_HOST_APB_PKT_IF_BASE (0x4080C280u)
33119#define DSI_HOST_APB_PKT_IF ((DSI_HOST_APB_PKT_IF_Type *)DSI_HOST_APB_PKT_IF_BASE)
33121#define DSI_HOST_APB_PKT_IF_BASE_ADDRS { DSI_HOST_APB_PKT_IF_BASE }
33123#define DSI_HOST_APB_PKT_IF_BASE_PTRS { DSI_HOST_APB_PKT_IF }
33124 /* end of group DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer */
33128
33129
33130/* ----------------------------------------------------------------------------
33131 -- DSI_HOST_DPI_INTFC Peripheral Access Layer
33132 ---------------------------------------------------------------------------- */
33133
33140typedef struct {
33141 __IO uint32_t PIXEL_PAYLOAD_SIZE;
33142 __IO uint32_t PIXEL_FIFO_SEND_LEVEL;
33143 __IO uint32_t INTERFACE_COLOR_CODING;
33144 __IO uint32_t PIXEL_FORMAT;
33145 __IO uint32_t VSYNC_POLARITY;
33146 __IO uint32_t HSYNC_POLARITY;
33147 __IO uint32_t VIDEO_MODE;
33148 __IO uint32_t HFP;
33149 __IO uint32_t HBP;
33150 __IO uint32_t HSA;
33151 __IO uint32_t ENABLE_MULT_PKTS;
33152 __IO uint32_t VBP;
33153 __IO uint32_t VFP;
33154 __IO uint32_t BLLP_MODE;
33155 __IO uint32_t USE_NULL_PKT_BLLP;
33156 __IO uint32_t VACTIVE;
33158
33159/* ----------------------------------------------------------------------------
33160 -- DSI_HOST_DPI_INTFC Register Masks
33161 ---------------------------------------------------------------------------- */
33162
33171#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK (0xFFFFU)
33172#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT (0U)
33176#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK)
33182#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK (0xFFFFU)
33183#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT (0U)
33188#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK)
33194#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK (0x7U)
33195#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT (0U)
33205#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT)) & DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK)
33211#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK (0x3U)
33212#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT (0U)
33219#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK)
33225#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK (0x1U)
33226#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT (0U)
33231#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK)
33237#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK (0x1U)
33238#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT (0U)
33243#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK)
33249#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK (0x3U)
33250#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT (0U)
33257#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT)) & DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK)
33263#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK (0xFFFFU)
33264#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT (0U)
33267#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK)
33273#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK (0xFFFFU)
33274#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT (0U)
33277#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK)
33283#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK (0xFFFFU)
33284#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT (0U)
33287#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK)
33293#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK (0x1U)
33294#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT (0U)
33300#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT)) & DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK)
33306#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK (0xFFU)
33307#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT (0U)
33310#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK)
33316#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK (0xFFU)
33317#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT (0U)
33320#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK)
33326#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK (0x1U)
33327#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT (0U)
33332#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT)) & DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK)
33338#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK (0x1U)
33339#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT (0U)
33344#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT)) & DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK)
33350#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK (0x3FFFU)
33351#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT (0U)
33354#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK) /* end of group DSI_HOST_DPI_INTFC_Register_Masks */
33361
33362
33363/* DSI_HOST_DPI_INTFC - Peripheral instance base addresses */
33365#define DSI_HOST_DPI_INTFC_BASE (0x4080C200u)
33367#define DSI_HOST_DPI_INTFC ((DSI_HOST_DPI_INTFC_Type *)DSI_HOST_DPI_INTFC_BASE)
33369#define DSI_HOST_DPI_INTFC_BASE_ADDRS { DSI_HOST_DPI_INTFC_BASE }
33371#define DSI_HOST_DPI_INTFC_BASE_PTRS { DSI_HOST_DPI_INTFC }
33372 /* end of group DSI_HOST_DPI_INTFC_Peripheral_Access_Layer */
33376
33377
33378/* ----------------------------------------------------------------------------
33379 -- DSI_HOST_NXP_FDSOI28_DPHY_INTFC Peripheral Access Layer
33380 ---------------------------------------------------------------------------- */
33381
33388typedef struct {
33389 __IO uint32_t PD_TX;
33390 __IO uint32_t M_PRG_HS_PREPARE;
33391 __IO uint32_t MC_PRG_HS_PREPARE;
33392 __IO uint32_t M_PRG_HS_ZERO;
33393 __IO uint32_t MC_PRG_HS_ZERO;
33394 __IO uint32_t M_PRG_HS_TRAIL;
33395 __IO uint32_t MC_PRG_HS_TRAIL;
33396 __IO uint32_t PD_PLL;
33397 __IO uint32_t TST;
33398 __IO uint32_t CN;
33399 __IO uint32_t CM;
33400 __IO uint32_t CO;
33401 __I uint32_t LOCK;
33402 __IO uint32_t LOCK_BYP;
33403 __IO uint32_t TX_RCAL;
33404 __IO uint32_t AUTO_PD_EN;
33405 __IO uint32_t RXLPRP;
33406 __IO uint32_t RXCDRP;
33408
33409/* ----------------------------------------------------------------------------
33410 -- DSI_HOST_NXP_FDSOI28_DPHY_INTFC Register Masks
33411 ---------------------------------------------------------------------------- */
33412
33421#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK (0x1U)
33422#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT (0U)
33427#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK)
33433#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK (0x3U)
33434#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT (0U)
33437#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK)
33443#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK (0x1U)
33444#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT (0U)
33447#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK)
33453#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK (0x1FU)
33454#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT (0U)
33457#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK)
33463#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK (0x3FU)
33464#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT (0U)
33467#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK)
33473#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK (0xFU)
33474#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT (0U)
33477#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK)
33483#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK (0xFU)
33484#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT (0U)
33487#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK)
33493#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK (0x1U)
33494#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT (0U)
33499#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK)
33505#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK (0x3FU)
33506#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT (0U)
33509#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK)
33515#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK (0x1FU)
33516#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT (0U)
33519#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK)
33525#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK (0xFFU)
33526#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT (0U)
33529#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK)
33535#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK (0x3U)
33536#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT (0U)
33543#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK)
33549#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK (0x1U)
33550#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT (0U)
33555#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK)
33561#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK (0x1U)
33562#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT (0U)
33567#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK)
33573#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK (0x3U)
33574#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT (0U)
33581#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK)
33587#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK (0x1U)
33588#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT (0U)
33593#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK)
33599#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK (0x3U)
33600#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT (0U)
33603#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK)
33609#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK (0x3U)
33610#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT (0U)
33617#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK) /* end of group DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Register_Masks */
33624
33625
33626/* DSI_HOST_NXP_FDSOI28_DPHY_INTFC - Peripheral instance base addresses */
33628#define DSI_HOST_DPHY_INTFC_BASE (0x4080C300u)
33630#define DSI_HOST_DPHY_INTFC ((DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type *)DSI_HOST_DPHY_INTFC_BASE)
33633#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_ADDRS { DSI_HOST_DPHY_INTFC_BASE }
33636#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_PTRS { DSI_HOST_DPHY_INTFC }
33637 /* end of group DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Peripheral_Access_Layer */
33641
33642
33643/* ----------------------------------------------------------------------------
33644 -- EMVSIM Peripheral Access Layer
33645 ---------------------------------------------------------------------------- */
33646
33653typedef struct {
33654 __I uint32_t VER_ID;
33655 __I uint32_t PARAM;
33656 __IO uint32_t CLKCFG;
33657 __IO uint32_t DIVISOR;
33658 __IO uint32_t CTRL;
33659 __IO uint32_t INT_MASK;
33660 __IO uint32_t RX_THD;
33661 __IO uint32_t TX_THD;
33662 __IO uint32_t RX_STATUS;
33663 __IO uint32_t TX_STATUS;
33664 __IO uint32_t PCSR;
33665 __I uint32_t RX_BUF;
33666 __O uint32_t TX_BUF;
33667 __IO uint32_t TX_GETU;
33668 __IO uint32_t CWT_VAL;
33669 __IO uint32_t BWT_VAL;
33670 __IO uint32_t BGT_VAL;
33671 __IO uint32_t GPCNT0_VAL;
33672 __IO uint32_t GPCNT1_VAL;
33673} EMVSIM_Type;
33674
33675/* ----------------------------------------------------------------------------
33676 -- EMVSIM Register Masks
33677 ---------------------------------------------------------------------------- */
33678
33687#define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU)
33688#define EMVSIM_VER_ID_VER_SHIFT (0U)
33691#define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
33697#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU)
33698#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U)
33701#define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
33702
33703#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U)
33704#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U)
33707#define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
33713#define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU)
33714#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U)
33717#define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
33718
33719#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U)
33720#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U)
33727#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
33728
33729#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U)
33730#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U)
33737#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
33743#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU)
33744#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U)
33749#define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
33755#define EMVSIM_CTRL_IC_MASK (0x1U)
33756#define EMVSIM_CTRL_IC_SHIFT (0U)
33761#define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
33762
33763#define EMVSIM_CTRL_ICM_MASK (0x2U)
33764#define EMVSIM_CTRL_ICM_SHIFT (1U)
33769#define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
33770
33771#define EMVSIM_CTRL_ANACK_MASK (0x4U)
33772#define EMVSIM_CTRL_ANACK_SHIFT (2U)
33777#define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
33778
33779#define EMVSIM_CTRL_ONACK_MASK (0x8U)
33780#define EMVSIM_CTRL_ONACK_SHIFT (3U)
33785#define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
33786
33787#define EMVSIM_CTRL_FLSH_RX_MASK (0x100U)
33788#define EMVSIM_CTRL_FLSH_RX_SHIFT (8U)
33793#define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
33794
33795#define EMVSIM_CTRL_FLSH_TX_MASK (0x200U)
33796#define EMVSIM_CTRL_FLSH_TX_SHIFT (9U)
33801#define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
33802
33803#define EMVSIM_CTRL_SW_RST_MASK (0x400U)
33804#define EMVSIM_CTRL_SW_RST_SHIFT (10U)
33809#define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
33810
33811#define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U)
33812#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U)
33817#define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
33818
33819#define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U)
33820#define EMVSIM_CTRL_DOZE_EN_SHIFT (12U)
33825#define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
33826
33827#define EMVSIM_CTRL_STOP_EN_MASK (0x2000U)
33828#define EMVSIM_CTRL_STOP_EN_SHIFT (13U)
33833#define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
33834
33835#define EMVSIM_CTRL_RCV_EN_MASK (0x10000U)
33836#define EMVSIM_CTRL_RCV_EN_SHIFT (16U)
33841#define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
33842
33843#define EMVSIM_CTRL_XMT_EN_MASK (0x20000U)
33844#define EMVSIM_CTRL_XMT_EN_SHIFT (17U)
33849#define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
33850
33851#define EMVSIM_CTRL_RCVR_11_MASK (0x40000U)
33852#define EMVSIM_CTRL_RCVR_11_SHIFT (18U)
33857#define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
33858
33859#define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U)
33860#define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U)
33865#define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
33866
33867#define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U)
33868#define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U)
33873#define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
33874
33875#define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U)
33876#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U)
33881#define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
33882
33883#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U)
33884#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U)
33889#define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
33890
33891#define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U)
33892#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U)
33897#define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
33898
33899#define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U)
33900#define EMVSIM_CTRL_CWT_EN_SHIFT (27U)
33905#define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
33906
33907#define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U)
33908#define EMVSIM_CTRL_LRC_EN_SHIFT (28U)
33913#define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
33914
33915#define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U)
33916#define EMVSIM_CTRL_CRC_EN_SHIFT (29U)
33921#define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
33922
33923#define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U)
33924#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U)
33929#define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
33930
33931#define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U)
33932#define EMVSIM_CTRL_BWT_EN_SHIFT (31U)
33937#define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
33943#define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U)
33944#define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U)
33949#define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
33950
33951#define EMVSIM_INT_MASK_TC_IM_MASK (0x2U)
33952#define EMVSIM_INT_MASK_TC_IM_SHIFT (1U)
33957#define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
33958
33959#define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U)
33960#define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U)
33965#define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
33966
33967#define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U)
33968#define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U)
33973#define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
33974
33975#define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U)
33976#define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U)
33981#define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
33982
33983#define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U)
33984#define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U)
33989#define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
33990
33991#define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U)
33992#define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U)
33997#define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
33998
33999#define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U)
34000#define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U)
34005#define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
34006
34007#define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U)
34008#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U)
34013#define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
34014
34015#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U)
34016#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U)
34021#define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
34022
34023#define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U)
34024#define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U)
34029#define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
34030
34031#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U)
34032#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U)
34037#define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
34038
34039#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U)
34040#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U)
34045#define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
34046
34047#define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U)
34048#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U)
34053#define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
34054
34055#define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U)
34056#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U)
34061#define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
34062
34063#define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U)
34064#define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U)
34069#define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
34075#define EMVSIM_RX_THD_RDT_MASK (0xFU)
34076#define EMVSIM_RX_THD_RDT_SHIFT (0U)
34079#define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
34080
34081#define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U)
34082#define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U)
34085#define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
34091#define EMVSIM_TX_THD_TDT_MASK (0xFU)
34092#define EMVSIM_TX_THD_TDT_SHIFT (0U)
34095#define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
34096
34097#define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U)
34098#define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U)
34101#define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
34107#define EMVSIM_RX_STATUS_RFO_MASK (0x1U)
34108#define EMVSIM_RX_STATUS_RFO_SHIFT (0U)
34113#define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
34114
34115#define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U)
34116#define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U)
34121#define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
34122
34123#define EMVSIM_RX_STATUS_RDTF_MASK (0x20U)
34124#define EMVSIM_RX_STATUS_RDTF_SHIFT (5U)
34129#define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
34130
34131#define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U)
34132#define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U)
34137#define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
34138
34139#define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U)
34140#define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U)
34145#define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
34146
34147#define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U)
34148#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U)
34153#define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
34154
34155#define EMVSIM_RX_STATUS_RTE_MASK (0x200U)
34156#define EMVSIM_RX_STATUS_RTE_SHIFT (9U)
34161#define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
34162
34163#define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U)
34164#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U)
34169#define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
34170
34171#define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U)
34172#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U)
34177#define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
34178
34179#define EMVSIM_RX_STATUS_PEF_MASK (0x1000U)
34180#define EMVSIM_RX_STATUS_PEF_SHIFT (12U)
34185#define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
34186
34187#define EMVSIM_RX_STATUS_FEF_MASK (0x2000U)
34188#define EMVSIM_RX_STATUS_FEF_SHIFT (13U)
34193#define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
34194
34195#define EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U)
34196#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U)
34199#define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
34200
34201#define EMVSIM_RX_STATUS_RX_CNT_MASK (0xF000000U)
34202#define EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U)
34206#define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
34212#define EMVSIM_TX_STATUS_TNTE_MASK (0x1U)
34213#define EMVSIM_TX_STATUS_TNTE_SHIFT (0U)
34218#define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
34219
34220#define EMVSIM_TX_STATUS_TFE_MASK (0x8U)
34221#define EMVSIM_TX_STATUS_TFE_SHIFT (3U)
34226#define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
34227
34228#define EMVSIM_TX_STATUS_ETCF_MASK (0x10U)
34229#define EMVSIM_TX_STATUS_ETCF_SHIFT (4U)
34234#define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
34235
34236#define EMVSIM_TX_STATUS_TCF_MASK (0x20U)
34237#define EMVSIM_TX_STATUS_TCF_SHIFT (5U)
34242#define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
34243
34244#define EMVSIM_TX_STATUS_TFF_MASK (0x40U)
34245#define EMVSIM_TX_STATUS_TFF_SHIFT (6U)
34250#define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
34251
34252#define EMVSIM_TX_STATUS_TDTF_MASK (0x80U)
34253#define EMVSIM_TX_STATUS_TDTF_SHIFT (7U)
34258#define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
34259
34260#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U)
34261#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U)
34266#define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
34267
34268#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U)
34269#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U)
34274#define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
34275
34276#define EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U)
34277#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U)
34280#define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
34281
34282#define EMVSIM_TX_STATUS_TX_CNT_MASK (0xF000000U)
34283#define EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U)
34287#define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
34293#define EMVSIM_PCSR_SAPD_MASK (0x1U)
34294#define EMVSIM_PCSR_SAPD_SHIFT (0U)
34299#define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
34300
34301#define EMVSIM_PCSR_SVCC_EN_MASK (0x2U)
34302#define EMVSIM_PCSR_SVCC_EN_SHIFT (1U)
34307#define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
34308
34309#define EMVSIM_PCSR_VCCENP_MASK (0x4U)
34310#define EMVSIM_PCSR_VCCENP_SHIFT (2U)
34315#define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
34316
34317#define EMVSIM_PCSR_SRST_MASK (0x8U)
34318#define EMVSIM_PCSR_SRST_SHIFT (3U)
34323#define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
34324
34325#define EMVSIM_PCSR_SCEN_MASK (0x10U)
34326#define EMVSIM_PCSR_SCEN_SHIFT (4U)
34331#define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
34332
34333#define EMVSIM_PCSR_SCSP_MASK (0x20U)
34334#define EMVSIM_PCSR_SCSP_SHIFT (5U)
34339#define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
34340
34341#define EMVSIM_PCSR_SPD_MASK (0x80U)
34342#define EMVSIM_PCSR_SPD_SHIFT (7U)
34347#define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
34348
34349#define EMVSIM_PCSR_SPDIM_MASK (0x1000000U)
34350#define EMVSIM_PCSR_SPDIM_SHIFT (24U)
34355#define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
34356
34357#define EMVSIM_PCSR_SPDIF_MASK (0x2000000U)
34358#define EMVSIM_PCSR_SPDIF_SHIFT (25U)
34363#define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
34364
34365#define EMVSIM_PCSR_SPDP_MASK (0x4000000U)
34366#define EMVSIM_PCSR_SPDP_SHIFT (26U)
34371#define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
34372
34373#define EMVSIM_PCSR_SPDES_MASK (0x8000000U)
34374#define EMVSIM_PCSR_SPDES_SHIFT (27U)
34379#define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
34385#define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU)
34386#define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U)
34389#define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
34395#define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU)
34396#define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U)
34399#define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
34405#define EMVSIM_TX_GETU_GETU_MASK (0xFFU)
34406#define EMVSIM_TX_GETU_GETU_SHIFT (0U)
34409#define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
34415#define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU)
34416#define EMVSIM_CWT_VAL_CWT_SHIFT (0U)
34419#define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
34425#define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU)
34426#define EMVSIM_BWT_VAL_BWT_SHIFT (0U)
34429#define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
34435#define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU)
34436#define EMVSIM_BGT_VAL_BGT_SHIFT (0U)
34439#define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
34445#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU)
34446#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U)
34449#define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
34455#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU)
34456#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U)
34459#define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK) /* end of group EMVSIM_Register_Masks */
34466
34467
34468/* EMVSIM - Peripheral instance base addresses */
34470#define EMVSIM1_BASE (0x40154000u)
34472#define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE)
34474#define EMVSIM2_BASE (0x40158000u)
34476#define EMVSIM2 ((EMVSIM_Type *)EMVSIM2_BASE)
34478#define EMVSIM_BASE_ADDRS { 0u, EMVSIM1_BASE, EMVSIM2_BASE }
34480#define EMVSIM_BASE_PTRS { (EMVSIM_Type *)0u, EMVSIM1, EMVSIM2 }
34482#define EMVSIM_IRQS { NotAvail_IRQn, EMVSIM1_IRQn, EMVSIM2_IRQn }
34483 /* end of group EMVSIM_Peripheral_Access_Layer */
34487
34488
34489/* ----------------------------------------------------------------------------
34490 -- ENC Peripheral Access Layer
34491 ---------------------------------------------------------------------------- */
34492
34499typedef struct {
34500 __IO uint16_t CTRL;
34501 __IO uint16_t FILT;
34502 __IO uint16_t WTR;
34503 __IO uint16_t POSD;
34504 __I uint16_t POSDH;
34505 __IO uint16_t REV;
34506 __I uint16_t REVH;
34507 __IO uint16_t UPOS;
34508 __IO uint16_t LPOS;
34509 __I uint16_t UPOSH;
34510 __I uint16_t LPOSH;
34511 __IO uint16_t UINIT;
34512 __IO uint16_t LINIT;
34513 __I uint16_t IMR;
34514 __IO uint16_t TST;
34515 __IO uint16_t CTRL2;
34516 __IO uint16_t UMOD;
34517 __IO uint16_t LMOD;
34518 __IO uint16_t UCOMP;
34519 __IO uint16_t LCOMP;
34520 __I uint16_t LASTEDGE;
34521 __I uint16_t LASTEDGEH;
34522 __I uint16_t POSDPER;
34523 __I uint16_t POSDPERBFR;
34524 __I uint16_t POSDPERH;
34525 __IO uint16_t CTRL3;
34526} ENC_Type;
34527
34528/* ----------------------------------------------------------------------------
34529 -- ENC Register Masks
34530 ---------------------------------------------------------------------------- */
34531
34540#define ENC_CTRL_CMPIE_MASK (0x1U)
34541#define ENC_CTRL_CMPIE_SHIFT (0U)
34546#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
34547
34548#define ENC_CTRL_CMPIRQ_MASK (0x2U)
34549#define ENC_CTRL_CMPIRQ_SHIFT (1U)
34554#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
34555
34556#define ENC_CTRL_WDE_MASK (0x4U)
34557#define ENC_CTRL_WDE_SHIFT (2U)
34562#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
34563
34564#define ENC_CTRL_DIE_MASK (0x8U)
34565#define ENC_CTRL_DIE_SHIFT (3U)
34570#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
34571
34572#define ENC_CTRL_DIRQ_MASK (0x10U)
34573#define ENC_CTRL_DIRQ_SHIFT (4U)
34578#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
34579
34580#define ENC_CTRL_XNE_MASK (0x20U)
34581#define ENC_CTRL_XNE_SHIFT (5U)
34586#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
34587
34588#define ENC_CTRL_XIP_MASK (0x40U)
34589#define ENC_CTRL_XIP_SHIFT (6U)
34594#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
34595
34596#define ENC_CTRL_XIE_MASK (0x80U)
34597#define ENC_CTRL_XIE_SHIFT (7U)
34602#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
34603
34604#define ENC_CTRL_XIRQ_MASK (0x100U)
34605#define ENC_CTRL_XIRQ_SHIFT (8U)
34610#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
34611
34612#define ENC_CTRL_PH1_MASK (0x200U)
34613#define ENC_CTRL_PH1_SHIFT (9U)
34621#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
34622
34623#define ENC_CTRL_REV_MASK (0x400U)
34624#define ENC_CTRL_REV_SHIFT (10U)
34629#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
34630
34631#define ENC_CTRL_SWIP_MASK (0x800U)
34632#define ENC_CTRL_SWIP_SHIFT (11U)
34637#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
34638
34639#define ENC_CTRL_HNE_MASK (0x1000U)
34640#define ENC_CTRL_HNE_SHIFT (12U)
34645#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
34646
34647#define ENC_CTRL_HIP_MASK (0x2000U)
34648#define ENC_CTRL_HIP_SHIFT (13U)
34653#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
34654
34655#define ENC_CTRL_HIE_MASK (0x4000U)
34656#define ENC_CTRL_HIE_SHIFT (14U)
34661#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
34662
34663#define ENC_CTRL_HIRQ_MASK (0x8000U)
34664#define ENC_CTRL_HIRQ_SHIFT (15U)
34669#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
34675#define ENC_FILT_FILT_PER_MASK (0xFFU)
34676#define ENC_FILT_FILT_PER_SHIFT (0U)
34679#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
34680
34681#define ENC_FILT_FILT_CNT_MASK (0x700U)
34682#define ENC_FILT_FILT_CNT_SHIFT (8U)
34685#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
34686
34687#define ENC_FILT_FILT_PRSC_MASK (0xE000U)
34688#define ENC_FILT_FILT_PRSC_SHIFT (13U)
34691#define ENC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK)
34697#define ENC_WTR_WDOG_MASK (0xFFFFU)
34698#define ENC_WTR_WDOG_SHIFT (0U)
34701#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
34707#define ENC_POSD_POSD_MASK (0xFFFFU)
34708#define ENC_POSD_POSD_SHIFT (0U)
34711#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
34717#define ENC_POSDH_POSDH_MASK (0xFFFFU)
34718#define ENC_POSDH_POSDH_SHIFT (0U)
34721#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
34727#define ENC_REV_REV_MASK (0xFFFFU)
34728#define ENC_REV_REV_SHIFT (0U)
34731#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
34737#define ENC_REVH_REVH_MASK (0xFFFFU)
34738#define ENC_REVH_REVH_SHIFT (0U)
34741#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
34747#define ENC_UPOS_POS_MASK (0xFFFFU)
34748#define ENC_UPOS_POS_SHIFT (0U)
34751#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
34757#define ENC_LPOS_POS_MASK (0xFFFFU)
34758#define ENC_LPOS_POS_SHIFT (0U)
34761#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
34767#define ENC_UPOSH_POSH_MASK (0xFFFFU)
34768#define ENC_UPOSH_POSH_SHIFT (0U)
34771#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
34777#define ENC_LPOSH_POSH_MASK (0xFFFFU)
34778#define ENC_LPOSH_POSH_SHIFT (0U)
34781#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
34787#define ENC_UINIT_INIT_MASK (0xFFFFU)
34788#define ENC_UINIT_INIT_SHIFT (0U)
34791#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
34797#define ENC_LINIT_INIT_MASK (0xFFFFU)
34798#define ENC_LINIT_INIT_SHIFT (0U)
34801#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
34807#define ENC_IMR_HOME_MASK (0x1U)
34808#define ENC_IMR_HOME_SHIFT (0U)
34811#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
34812
34813#define ENC_IMR_INDEX_MASK (0x2U)
34814#define ENC_IMR_INDEX_SHIFT (1U)
34817#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
34818
34819#define ENC_IMR_PHB_MASK (0x4U)
34820#define ENC_IMR_PHB_SHIFT (2U)
34823#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
34824
34825#define ENC_IMR_PHA_MASK (0x8U)
34826#define ENC_IMR_PHA_SHIFT (3U)
34829#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
34830
34831#define ENC_IMR_FHOM_MASK (0x10U)
34832#define ENC_IMR_FHOM_SHIFT (4U)
34835#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
34836
34837#define ENC_IMR_FIND_MASK (0x20U)
34838#define ENC_IMR_FIND_SHIFT (5U)
34841#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
34842
34843#define ENC_IMR_FPHB_MASK (0x40U)
34844#define ENC_IMR_FPHB_SHIFT (6U)
34847#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
34848
34849#define ENC_IMR_FPHA_MASK (0x80U)
34850#define ENC_IMR_FPHA_SHIFT (7U)
34853#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
34859#define ENC_TST_TEST_COUNT_MASK (0xFFU)
34860#define ENC_TST_TEST_COUNT_SHIFT (0U)
34863#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
34864
34865#define ENC_TST_TEST_PERIOD_MASK (0x1F00U)
34866#define ENC_TST_TEST_PERIOD_SHIFT (8U)
34869#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
34870
34871#define ENC_TST_QDN_MASK (0x2000U)
34872#define ENC_TST_QDN_SHIFT (13U)
34877#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
34878
34879#define ENC_TST_TCE_MASK (0x4000U)
34880#define ENC_TST_TCE_SHIFT (14U)
34885#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
34886
34887#define ENC_TST_TEN_MASK (0x8000U)
34888#define ENC_TST_TEN_SHIFT (15U)
34893#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
34899#define ENC_CTRL2_UPDHLD_MASK (0x1U)
34900#define ENC_CTRL2_UPDHLD_SHIFT (0U)
34905#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
34906
34907#define ENC_CTRL2_UPDPOS_MASK (0x2U)
34908#define ENC_CTRL2_UPDPOS_SHIFT (1U)
34913#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
34914
34915#define ENC_CTRL2_MOD_MASK (0x4U)
34916#define ENC_CTRL2_MOD_SHIFT (2U)
34921#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
34922
34923#define ENC_CTRL2_DIR_MASK (0x8U)
34924#define ENC_CTRL2_DIR_SHIFT (3U)
34929#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
34930
34931#define ENC_CTRL2_RUIE_MASK (0x10U)
34932#define ENC_CTRL2_RUIE_SHIFT (4U)
34937#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
34938
34939#define ENC_CTRL2_RUIRQ_MASK (0x20U)
34940#define ENC_CTRL2_RUIRQ_SHIFT (5U)
34945#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
34946
34947#define ENC_CTRL2_ROIE_MASK (0x40U)
34948#define ENC_CTRL2_ROIE_SHIFT (6U)
34953#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
34954
34955#define ENC_CTRL2_ROIRQ_MASK (0x80U)
34956#define ENC_CTRL2_ROIRQ_SHIFT (7U)
34961#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
34962
34963#define ENC_CTRL2_REVMOD_MASK (0x100U)
34964#define ENC_CTRL2_REVMOD_SHIFT (8U)
34969#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
34970
34971#define ENC_CTRL2_OUTCTL_MASK (0x200U)
34972#define ENC_CTRL2_OUTCTL_SHIFT (9U)
34977#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
34978
34979#define ENC_CTRL2_SABIE_MASK (0x400U)
34980#define ENC_CTRL2_SABIE_SHIFT (10U)
34985#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
34986
34987#define ENC_CTRL2_SABIRQ_MASK (0x800U)
34988#define ENC_CTRL2_SABIRQ_SHIFT (11U)
34993#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
34999#define ENC_UMOD_MOD_MASK (0xFFFFU)
35000#define ENC_UMOD_MOD_SHIFT (0U)
35003#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
35009#define ENC_LMOD_MOD_MASK (0xFFFFU)
35010#define ENC_LMOD_MOD_SHIFT (0U)
35013#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
35019#define ENC_UCOMP_COMP_MASK (0xFFFFU)
35020#define ENC_UCOMP_COMP_SHIFT (0U)
35023#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
35029#define ENC_LCOMP_COMP_MASK (0xFFFFU)
35030#define ENC_LCOMP_COMP_SHIFT (0U)
35033#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
35039#define ENC_LASTEDGE_LASTEDGE_MASK (0xFFFFU)
35040#define ENC_LASTEDGE_LASTEDGE_SHIFT (0U)
35043#define ENC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK)
35049#define ENC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU)
35050#define ENC_LASTEDGEH_LASTEDGEH_SHIFT (0U)
35053#define ENC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK)
35059#define ENC_POSDPER_POSDPER_MASK (0xFFFFU)
35060#define ENC_POSDPER_POSDPER_SHIFT (0U)
35063#define ENC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK)
35069#define ENC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU)
35070#define ENC_POSDPERBFR_POSDPERBFR_SHIFT (0U)
35073#define ENC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK)
35079#define ENC_POSDPERH_POSDPERH_MASK (0xFFFFU)
35080#define ENC_POSDPERH_POSDPERH_SHIFT (0U)
35083#define ENC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK)
35089#define ENC_CTRL3_PMEN_MASK (0x1U)
35090#define ENC_CTRL3_PMEN_SHIFT (0U)
35095#define ENC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK)
35096
35097#define ENC_CTRL3_PRSC_MASK (0xF0U)
35098#define ENC_CTRL3_PRSC_SHIFT (4U)
35101#define ENC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK) /* end of group ENC_Register_Masks */
35108
35109
35110/* ENC - Peripheral instance base addresses */
35112#define ENC1_BASE (0x40174000u)
35114#define ENC1 ((ENC_Type *)ENC1_BASE)
35116#define ENC2_BASE (0x40178000u)
35118#define ENC2 ((ENC_Type *)ENC2_BASE)
35120#define ENC3_BASE (0x4017C000u)
35122#define ENC3 ((ENC_Type *)ENC3_BASE)
35124#define ENC4_BASE (0x40180000u)
35126#define ENC4 ((ENC_Type *)ENC4_BASE)
35128#define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
35130#define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
35132#define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
35133#define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
35134#define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
35135#define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
35136#define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
35137 /* end of group ENC_Peripheral_Access_Layer */
35141
35142
35143/* ----------------------------------------------------------------------------
35144 -- ENET Peripheral Access Layer
35145 ---------------------------------------------------------------------------- */
35146
35153typedef struct {
35154 uint8_t RESERVED_0[4];
35155 __IO uint32_t EIR;
35156 __IO uint32_t EIMR;
35157 uint8_t RESERVED_1[4];
35158 __IO uint32_t RDAR;
35159 __IO uint32_t TDAR;
35160 uint8_t RESERVED_2[12];
35161 __IO uint32_t ECR;
35162 uint8_t RESERVED_3[24];
35163 __IO uint32_t MMFR;
35164 __IO uint32_t MSCR;
35165 uint8_t RESERVED_4[28];
35166 __IO uint32_t MIBC;
35167 uint8_t RESERVED_5[28];
35168 __IO uint32_t RCR;
35169 uint8_t RESERVED_6[60];
35170 __IO uint32_t TCR;
35171 uint8_t RESERVED_7[28];
35172 __IO uint32_t PALR;
35173 __IO uint32_t PAUR;
35174 __IO uint32_t OPD;
35175 __IO uint32_t TXIC[3];
35176 uint8_t RESERVED_8[4];
35177 __IO uint32_t RXIC[3];
35178 uint8_t RESERVED_9[12];
35179 __IO uint32_t IAUR;
35180 __IO uint32_t IALR;
35181 __IO uint32_t GAUR;
35182 __IO uint32_t GALR;
35183 uint8_t RESERVED_10[28];
35184 __IO uint32_t TFWR;
35185 uint8_t RESERVED_11[24];
35186 __IO uint32_t RDSR1;
35187 __IO uint32_t TDSR1;
35188 __IO uint32_t MRBR1;
35189 __IO uint32_t RDSR2;
35190 __IO uint32_t TDSR2;
35191 __IO uint32_t MRBR2;
35192 uint8_t RESERVED_12[8];
35193 __IO uint32_t RDSR;
35194 __IO uint32_t TDSR;
35195 __IO uint32_t MRBR;
35196 uint8_t RESERVED_13[4];
35197 __IO uint32_t RSFL;
35198 __IO uint32_t RSEM;
35199 __IO uint32_t RAEM;
35200 __IO uint32_t RAFL;
35201 __IO uint32_t TSEM;
35202 __IO uint32_t TAEM;
35203 __IO uint32_t TAFL;
35204 __IO uint32_t TIPG;
35205 __IO uint32_t FTRL;
35206 uint8_t RESERVED_14[12];
35207 __IO uint32_t TACC;
35208 __IO uint32_t RACC;
35209 __IO uint32_t RCMR[2];
35210 uint8_t RESERVED_15[8];
35211 __IO uint32_t DMACFG[2];
35212 __IO uint32_t RDAR1;
35213 __IO uint32_t TDAR1;
35214 __IO uint32_t RDAR2;
35215 __IO uint32_t TDAR2;
35216 __IO uint32_t QOS;
35217 uint8_t RESERVED_16[16];
35218 __I uint32_t RMON_T_PACKETS;
35219 __I uint32_t RMON_T_BC_PKT;
35220 __I uint32_t RMON_T_MC_PKT;
35221 __I uint32_t RMON_T_CRC_ALIGN;
35222 __I uint32_t RMON_T_UNDERSIZE;
35223 __I uint32_t RMON_T_OVERSIZE;
35224 __I uint32_t RMON_T_FRAG;
35225 __I uint32_t RMON_T_JAB;
35226 __I uint32_t RMON_T_COL;
35227 __I uint32_t RMON_T_P64;
35228 __I uint32_t RMON_T_P65TO127;
35229 __I uint32_t RMON_T_P128TO255;
35230 __I uint32_t RMON_T_P256TO511;
35231 __I uint32_t RMON_T_P512TO1023;
35232 __I uint32_t RMON_T_P1024TO2047;
35233 __I uint32_t RMON_T_P_GTE2048;
35234 __I uint32_t RMON_T_OCTETS;
35235 uint32_t IEEE_T_DROP;
35236 __I uint32_t IEEE_T_FRAME_OK;
35237 __I uint32_t IEEE_T_1COL;
35238 __I uint32_t IEEE_T_MCOL;
35239 __I uint32_t IEEE_T_DEF;
35240 __I uint32_t IEEE_T_LCOL;
35241 __I uint32_t IEEE_T_EXCOL;
35242 __I uint32_t IEEE_T_MACERR;
35243 __I uint32_t IEEE_T_CSERR;
35244 __I uint32_t IEEE_T_SQE;
35245 __I uint32_t IEEE_T_FDXFC;
35246 __I uint32_t IEEE_T_OCTETS_OK;
35247 uint8_t RESERVED_17[12];
35248 __I uint32_t RMON_R_PACKETS;
35249 __I uint32_t RMON_R_BC_PKT;
35250 __I uint32_t RMON_R_MC_PKT;
35251 __I uint32_t RMON_R_CRC_ALIGN;
35252 __I uint32_t RMON_R_UNDERSIZE;
35253 __I uint32_t RMON_R_OVERSIZE;
35254 __I uint32_t RMON_R_FRAG;
35255 __I uint32_t RMON_R_JAB;
35256 uint8_t RESERVED_18[4];
35257 __I uint32_t RMON_R_P64;
35258 __I uint32_t RMON_R_P65TO127;
35259 __I uint32_t RMON_R_P128TO255;
35260 __I uint32_t RMON_R_P256TO511;
35261 __I uint32_t RMON_R_P512TO1023;
35262 __I uint32_t RMON_R_P1024TO2047;
35263 __I uint32_t RMON_R_P_GTE2048;
35264 __I uint32_t RMON_R_OCTETS;
35265 __I uint32_t IEEE_R_DROP;
35266 __I uint32_t IEEE_R_FRAME_OK;
35267 __I uint32_t IEEE_R_CRC;
35268 __I uint32_t IEEE_R_ALIGN;
35269 __I uint32_t IEEE_R_MACERR;
35270 __I uint32_t IEEE_R_FDXFC;
35271 __I uint32_t IEEE_R_OCTETS_OK;
35272 uint8_t RESERVED_19[284];
35273 __IO uint32_t ATCR;
35274 __IO uint32_t ATVR;
35275 __IO uint32_t ATOFF;
35276 __IO uint32_t ATPER;
35277 __IO uint32_t ATCOR;
35278 __IO uint32_t ATINC;
35279 __I uint32_t ATSTMP;
35280 uint8_t RESERVED_20[488];
35281 __IO uint32_t TGSR;
35282 struct { /* offset: 0x608, array step: 0x8 */
35283 __IO uint32_t TCSR;
35284 __IO uint32_t TCCR;
35285 } CHANNEL[4];
35286} ENET_Type;
35287
35288/* ----------------------------------------------------------------------------
35289 -- ENET Register Masks
35290 ---------------------------------------------------------------------------- */
35291
35300#define ENET_EIR_RXB1_MASK (0x1U)
35301#define ENET_EIR_RXB1_SHIFT (0U)
35304#define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)
35305
35306#define ENET_EIR_RXF1_MASK (0x2U)
35307#define ENET_EIR_RXF1_SHIFT (1U)
35310#define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)
35311
35312#define ENET_EIR_TXB1_MASK (0x4U)
35313#define ENET_EIR_TXB1_SHIFT (2U)
35316#define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)
35317
35318#define ENET_EIR_TXF1_MASK (0x8U)
35319#define ENET_EIR_TXF1_SHIFT (3U)
35322#define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)
35323
35324#define ENET_EIR_RXB2_MASK (0x10U)
35325#define ENET_EIR_RXB2_SHIFT (4U)
35328#define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)
35329
35330#define ENET_EIR_RXF2_MASK (0x20U)
35331#define ENET_EIR_RXF2_SHIFT (5U)
35334#define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)
35335
35336#define ENET_EIR_TXB2_MASK (0x40U)
35337#define ENET_EIR_TXB2_SHIFT (6U)
35340#define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)
35341
35342#define ENET_EIR_TXF2_MASK (0x80U)
35343#define ENET_EIR_TXF2_SHIFT (7U)
35346#define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)
35347
35348#define ENET_EIR_RXFLUSH_0_MASK (0x1000U)
35349#define ENET_EIR_RXFLUSH_0_SHIFT (12U)
35350#define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)
35351
35352#define ENET_EIR_RXFLUSH_1_MASK (0x2000U)
35353#define ENET_EIR_RXFLUSH_1_SHIFT (13U)
35354#define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)
35355
35356#define ENET_EIR_RXFLUSH_2_MASK (0x4000U)
35357#define ENET_EIR_RXFLUSH_2_SHIFT (14U)
35358#define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)
35359
35360#define ENET_EIR_TS_TIMER_MASK (0x8000U)
35361#define ENET_EIR_TS_TIMER_SHIFT (15U)
35364#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
35365
35366#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
35367#define ENET_EIR_TS_AVAIL_SHIFT (16U)
35370#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
35371
35372#define ENET_EIR_WAKEUP_MASK (0x20000U)
35373#define ENET_EIR_WAKEUP_SHIFT (17U)
35376#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
35377
35378#define ENET_EIR_PLR_MASK (0x40000U)
35379#define ENET_EIR_PLR_SHIFT (18U)
35382#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
35383
35384#define ENET_EIR_UN_MASK (0x80000U)
35385#define ENET_EIR_UN_SHIFT (19U)
35388#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
35389
35390#define ENET_EIR_RL_MASK (0x100000U)
35391#define ENET_EIR_RL_SHIFT (20U)
35394#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
35395
35396#define ENET_EIR_LC_MASK (0x200000U)
35397#define ENET_EIR_LC_SHIFT (21U)
35400#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
35401
35402#define ENET_EIR_EBERR_MASK (0x400000U)
35403#define ENET_EIR_EBERR_SHIFT (22U)
35406#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
35407
35408#define ENET_EIR_MII_MASK (0x800000U)
35409#define ENET_EIR_MII_SHIFT (23U)
35412#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
35413
35414#define ENET_EIR_RXB_MASK (0x1000000U)
35415#define ENET_EIR_RXB_SHIFT (24U)
35418#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
35419
35420#define ENET_EIR_RXF_MASK (0x2000000U)
35421#define ENET_EIR_RXF_SHIFT (25U)
35424#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
35425
35426#define ENET_EIR_TXB_MASK (0x4000000U)
35427#define ENET_EIR_TXB_SHIFT (26U)
35430#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
35431
35432#define ENET_EIR_TXF_MASK (0x8000000U)
35433#define ENET_EIR_TXF_SHIFT (27U)
35436#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
35437
35438#define ENET_EIR_GRA_MASK (0x10000000U)
35439#define ENET_EIR_GRA_SHIFT (28U)
35442#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
35443
35444#define ENET_EIR_BABT_MASK (0x20000000U)
35445#define ENET_EIR_BABT_SHIFT (29U)
35448#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
35449
35450#define ENET_EIR_BABR_MASK (0x40000000U)
35451#define ENET_EIR_BABR_SHIFT (30U)
35454#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
35460#define ENET_EIMR_RXB1_MASK (0x1U)
35461#define ENET_EIMR_RXB1_SHIFT (0U)
35466#define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)
35467
35468#define ENET_EIMR_RXF1_MASK (0x2U)
35469#define ENET_EIMR_RXF1_SHIFT (1U)
35474#define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)
35475
35476#define ENET_EIMR_TXB1_MASK (0x4U)
35477#define ENET_EIMR_TXB1_SHIFT (2U)
35482#define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)
35483
35484#define ENET_EIMR_TXF1_MASK (0x8U)
35485#define ENET_EIMR_TXF1_SHIFT (3U)
35490#define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)
35491
35492#define ENET_EIMR_RXB2_MASK (0x10U)
35493#define ENET_EIMR_RXB2_SHIFT (4U)
35498#define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)
35499
35500#define ENET_EIMR_RXF2_MASK (0x20U)
35501#define ENET_EIMR_RXF2_SHIFT (5U)
35506#define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)
35507
35508#define ENET_EIMR_TXB2_MASK (0x40U)
35509#define ENET_EIMR_TXB2_SHIFT (6U)
35514#define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)
35515
35516#define ENET_EIMR_TXF2_MASK (0x80U)
35517#define ENET_EIMR_TXF2_SHIFT (7U)
35522#define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)
35523
35524#define ENET_EIMR_RXFLUSH_0_MASK (0x1000U)
35525#define ENET_EIMR_RXFLUSH_0_SHIFT (12U)
35530#define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)
35531
35532#define ENET_EIMR_RXFLUSH_1_MASK (0x2000U)
35533#define ENET_EIMR_RXFLUSH_1_SHIFT (13U)
35538#define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)
35539
35540#define ENET_EIMR_RXFLUSH_2_MASK (0x4000U)
35541#define ENET_EIMR_RXFLUSH_2_SHIFT (14U)
35546#define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)
35547
35548#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
35549#define ENET_EIMR_TS_TIMER_SHIFT (15U)
35554#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
35555
35556#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
35557#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
35562#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
35563
35564#define ENET_EIMR_WAKEUP_MASK (0x20000U)
35565#define ENET_EIMR_WAKEUP_SHIFT (17U)
35570#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
35571
35572#define ENET_EIMR_PLR_MASK (0x40000U)
35573#define ENET_EIMR_PLR_SHIFT (18U)
35578#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
35579
35580#define ENET_EIMR_UN_MASK (0x80000U)
35581#define ENET_EIMR_UN_SHIFT (19U)
35586#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
35587
35588#define ENET_EIMR_RL_MASK (0x100000U)
35589#define ENET_EIMR_RL_SHIFT (20U)
35594#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
35595
35596#define ENET_EIMR_LC_MASK (0x200000U)
35597#define ENET_EIMR_LC_SHIFT (21U)
35602#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
35603
35604#define ENET_EIMR_EBERR_MASK (0x400000U)
35605#define ENET_EIMR_EBERR_SHIFT (22U)
35610#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
35611
35612#define ENET_EIMR_MII_MASK (0x800000U)
35613#define ENET_EIMR_MII_SHIFT (23U)
35618#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
35619
35620#define ENET_EIMR_RXB_MASK (0x1000000U)
35621#define ENET_EIMR_RXB_SHIFT (24U)
35626#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
35627
35628#define ENET_EIMR_RXF_MASK (0x2000000U)
35629#define ENET_EIMR_RXF_SHIFT (25U)
35634#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
35635
35636#define ENET_EIMR_TXB_MASK (0x4000000U)
35637#define ENET_EIMR_TXB_SHIFT (26U)
35642#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
35643
35644#define ENET_EIMR_TXF_MASK (0x8000000U)
35645#define ENET_EIMR_TXF_SHIFT (27U)
35650#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
35651
35652#define ENET_EIMR_GRA_MASK (0x10000000U)
35653#define ENET_EIMR_GRA_SHIFT (28U)
35658#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
35659
35660#define ENET_EIMR_BABT_MASK (0x20000000U)
35661#define ENET_EIMR_BABT_SHIFT (29U)
35666#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
35667
35668#define ENET_EIMR_BABR_MASK (0x40000000U)
35669#define ENET_EIMR_BABR_SHIFT (30U)
35674#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
35680#define ENET_RDAR_RDAR_MASK (0x1000000U)
35681#define ENET_RDAR_RDAR_SHIFT (24U)
35684#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
35690#define ENET_TDAR_TDAR_MASK (0x1000000U)
35691#define ENET_TDAR_TDAR_SHIFT (24U)
35694#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
35700#define ENET_ECR_RESET_MASK (0x1U)
35701#define ENET_ECR_RESET_SHIFT (0U)
35704#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
35705
35706#define ENET_ECR_ETHEREN_MASK (0x2U)
35707#define ENET_ECR_ETHEREN_SHIFT (1U)
35712#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
35713
35714#define ENET_ECR_MAGICEN_MASK (0x4U)
35715#define ENET_ECR_MAGICEN_SHIFT (2U)
35720#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
35721
35722#define ENET_ECR_SLEEP_MASK (0x8U)
35723#define ENET_ECR_SLEEP_SHIFT (3U)
35728#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
35729
35730#define ENET_ECR_EN1588_MASK (0x10U)
35731#define ENET_ECR_EN1588_SHIFT (4U)
35736#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
35737
35738#define ENET_ECR_SPEED_MASK (0x20U)
35739#define ENET_ECR_SPEED_SHIFT (5U)
35744#define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)
35745
35746#define ENET_ECR_DBGEN_MASK (0x40U)
35747#define ENET_ECR_DBGEN_SHIFT (6U)
35752#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
35753
35754#define ENET_ECR_DBSWP_MASK (0x100U)
35755#define ENET_ECR_DBSWP_SHIFT (8U)
35760#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
35761
35762#define ENET_ECR_SVLANEN_MASK (0x200U)
35763#define ENET_ECR_SVLANEN_SHIFT (9U)
35770#define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)
35771
35772#define ENET_ECR_VLANUSE2ND_MASK (0x400U)
35773#define ENET_ECR_VLANUSE2ND_SHIFT (10U)
35780#define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)
35781
35782#define ENET_ECR_SVLANDBL_MASK (0x800U)
35783#define ENET_ECR_SVLANDBL_SHIFT (11U)
35788#define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)
35789
35790#define ENET_ECR_TXC_DLY_MASK (0x10000U)
35791#define ENET_ECR_TXC_DLY_SHIFT (16U)
35796#define ENET_ECR_TXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)
35802#define ENET_MMFR_DATA_MASK (0xFFFFU)
35803#define ENET_MMFR_DATA_SHIFT (0U)
35806#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
35807
35808#define ENET_MMFR_TA_MASK (0x30000U)
35809#define ENET_MMFR_TA_SHIFT (16U)
35812#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
35813
35814#define ENET_MMFR_RA_MASK (0x7C0000U)
35815#define ENET_MMFR_RA_SHIFT (18U)
35818#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
35819
35820#define ENET_MMFR_PA_MASK (0xF800000U)
35821#define ENET_MMFR_PA_SHIFT (23U)
35824#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
35825
35826#define ENET_MMFR_OP_MASK (0x30000000U)
35827#define ENET_MMFR_OP_SHIFT (28U)
35830#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
35831
35832#define ENET_MMFR_ST_MASK (0xC0000000U)
35833#define ENET_MMFR_ST_SHIFT (30U)
35836#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
35842#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
35843#define ENET_MSCR_MII_SPEED_SHIFT (1U)
35846#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
35847
35848#define ENET_MSCR_DIS_PRE_MASK (0x80U)
35849#define ENET_MSCR_DIS_PRE_SHIFT (7U)
35854#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
35855
35856#define ENET_MSCR_HOLDTIME_MASK (0x700U)
35857#define ENET_MSCR_HOLDTIME_SHIFT (8U)
35864#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
35870#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
35871#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
35876#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
35877
35878#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
35879#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
35884#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
35885
35886#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
35887#define ENET_MIBC_MIB_DIS_SHIFT (31U)
35892#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
35898#define ENET_RCR_LOOP_MASK (0x1U)
35899#define ENET_RCR_LOOP_SHIFT (0U)
35904#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
35905
35906#define ENET_RCR_DRT_MASK (0x2U)
35907#define ENET_RCR_DRT_SHIFT (1U)
35912#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
35913
35914#define ENET_RCR_MII_MODE_MASK (0x4U)
35915#define ENET_RCR_MII_MODE_SHIFT (2U)
35920#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
35921
35922#define ENET_RCR_PROM_MASK (0x8U)
35923#define ENET_RCR_PROM_SHIFT (3U)
35928#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
35929
35930#define ENET_RCR_BC_REJ_MASK (0x10U)
35931#define ENET_RCR_BC_REJ_SHIFT (4U)
35936#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
35937
35938#define ENET_RCR_FCE_MASK (0x20U)
35939#define ENET_RCR_FCE_SHIFT (5U)
35944#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
35945
35946#define ENET_RCR_RGMII_EN_MASK (0x40U)
35947#define ENET_RCR_RGMII_EN_SHIFT (6U)
35953#define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)
35954
35955#define ENET_RCR_RMII_MODE_MASK (0x100U)
35956#define ENET_RCR_RMII_MODE_SHIFT (8U)
35961#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
35962
35963#define ENET_RCR_RMII_10T_MASK (0x200U)
35964#define ENET_RCR_RMII_10T_SHIFT (9U)
35969#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
35970
35971#define ENET_RCR_PADEN_MASK (0x1000U)
35972#define ENET_RCR_PADEN_SHIFT (12U)
35977#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
35978
35979#define ENET_RCR_PAUFWD_MASK (0x2000U)
35980#define ENET_RCR_PAUFWD_SHIFT (13U)
35985#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
35986
35987#define ENET_RCR_CRCFWD_MASK (0x4000U)
35988#define ENET_RCR_CRCFWD_SHIFT (14U)
35993#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
35994
35995#define ENET_RCR_CFEN_MASK (0x8000U)
35996#define ENET_RCR_CFEN_SHIFT (15U)
36001#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
36002
36003#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
36004#define ENET_RCR_MAX_FL_SHIFT (16U)
36007#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
36008
36009#define ENET_RCR_NLC_MASK (0x40000000U)
36010#define ENET_RCR_NLC_SHIFT (30U)
36015#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
36016
36017#define ENET_RCR_GRS_MASK (0x80000000U)
36018#define ENET_RCR_GRS_SHIFT (31U)
36023#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
36029#define ENET_TCR_GTS_MASK (0x1U)
36030#define ENET_TCR_GTS_SHIFT (0U)
36035#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
36036
36037#define ENET_TCR_FDEN_MASK (0x4U)
36038#define ENET_TCR_FDEN_SHIFT (2U)
36043#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
36044
36045#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
36046#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
36051#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
36052
36053#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
36054#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
36057#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
36058
36059#define ENET_TCR_ADDSEL_MASK (0xE0U)
36060#define ENET_TCR_ADDSEL_SHIFT (5U)
36067#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
36068
36069#define ENET_TCR_ADDINS_MASK (0x100U)
36070#define ENET_TCR_ADDINS_SHIFT (8U)
36075#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
36076
36077#define ENET_TCR_CRCFWD_MASK (0x200U)
36078#define ENET_TCR_CRCFWD_SHIFT (9U)
36083#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
36089#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
36090#define ENET_PALR_PADDR1_SHIFT (0U)
36093#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
36099#define ENET_PAUR_TYPE_MASK (0xFFFFU)
36100#define ENET_PAUR_TYPE_SHIFT (0U)
36103#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
36104
36105#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
36106#define ENET_PAUR_PADDR2_SHIFT (16U)
36107#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
36113#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
36114#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
36117#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
36118
36119#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
36120#define ENET_OPD_OPCODE_SHIFT (16U)
36123#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
36129#define ENET_TXIC_ICTT_MASK (0xFFFFU)
36130#define ENET_TXIC_ICTT_SHIFT (0U)
36133#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
36134
36135#define ENET_TXIC_ICFT_MASK (0xFF00000U)
36136#define ENET_TXIC_ICFT_SHIFT (20U)
36139#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
36140
36141#define ENET_TXIC_ICCS_MASK (0x40000000U)
36142#define ENET_TXIC_ICCS_SHIFT (30U)
36147#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
36148
36149#define ENET_TXIC_ICEN_MASK (0x80000000U)
36150#define ENET_TXIC_ICEN_SHIFT (31U)
36155#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
36158/* The count of ENET_TXIC */
36159#define ENET_TXIC_COUNT (3U)
36160
36164#define ENET_RXIC_ICTT_MASK (0xFFFFU)
36165#define ENET_RXIC_ICTT_SHIFT (0U)
36168#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
36169
36170#define ENET_RXIC_ICFT_MASK (0xFF00000U)
36171#define ENET_RXIC_ICFT_SHIFT (20U)
36174#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
36175
36176#define ENET_RXIC_ICCS_MASK (0x40000000U)
36177#define ENET_RXIC_ICCS_SHIFT (30U)
36182#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
36183
36184#define ENET_RXIC_ICEN_MASK (0x80000000U)
36185#define ENET_RXIC_ICEN_SHIFT (31U)
36190#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
36193/* The count of ENET_RXIC */
36194#define ENET_RXIC_COUNT (3U)
36195
36199#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
36200#define ENET_IAUR_IADDR1_SHIFT (0U)
36201#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
36207#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
36208#define ENET_IALR_IADDR2_SHIFT (0U)
36209#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
36215#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
36216#define ENET_GAUR_GADDR1_SHIFT (0U)
36217#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
36223#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
36224#define ENET_GALR_GADDR2_SHIFT (0U)
36225#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
36231#define ENET_TFWR_TFWR_MASK (0x3FU)
36232#define ENET_TFWR_TFWR_SHIFT (0U)
36240#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
36241
36242#define ENET_TFWR_STRFWD_MASK (0x100U)
36243#define ENET_TFWR_STRFWD_SHIFT (8U)
36248#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
36254#define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U)
36255#define ENET_RDSR1_R_DES_START_SHIFT (3U)
36256#define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)
36262#define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U)
36263#define ENET_TDSR1_X_DES_START_SHIFT (3U)
36264#define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)
36270#define ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U)
36271#define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U)
36272#define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)
36278#define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U)
36279#define ENET_RDSR2_R_DES_START_SHIFT (3U)
36280#define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)
36286#define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U)
36287#define ENET_TDSR2_X_DES_START_SHIFT (3U)
36288#define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)
36294#define ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U)
36295#define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U)
36296#define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)
36302#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
36303#define ENET_RDSR_R_DES_START_SHIFT (3U)
36304#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
36310#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
36311#define ENET_TDSR_X_DES_START_SHIFT (3U)
36312#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
36318#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) /* Merged from fields with different position or width, of widths (7, 10), largest definition used */
36319#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
36320#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) /* Merged from fields with different position or width, of widths (7, 10), largest definition used */
36326#define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36327#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
36330#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36336#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36337#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
36340#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36341
36342#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
36343#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
36346#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
36352#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36353#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
36356#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36362#define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36363#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
36366#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36372#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36373#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
36376#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36382#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36383#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
36386#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36392#define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36393#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
36396#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36402#define ENET_TIPG_IPG_MASK (0x1FU)
36403#define ENET_TIPG_IPG_SHIFT (0U)
36406#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
36412#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
36413#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
36416#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
36422#define ENET_TACC_SHIFT16_MASK (0x1U)
36423#define ENET_TACC_SHIFT16_SHIFT (0U)
36431#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
36432
36433#define ENET_TACC_IPCHK_MASK (0x8U)
36434#define ENET_TACC_IPCHK_SHIFT (3U)
36440#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
36441
36442#define ENET_TACC_PROCHK_MASK (0x10U)
36443#define ENET_TACC_PROCHK_SHIFT (4U)
36449#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
36455#define ENET_RACC_PADREM_MASK (0x1U)
36456#define ENET_RACC_PADREM_SHIFT (0U)
36461#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
36462
36463#define ENET_RACC_IPDIS_MASK (0x2U)
36464#define ENET_RACC_IPDIS_SHIFT (1U)
36471#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
36472
36473#define ENET_RACC_PRODIS_MASK (0x4U)
36474#define ENET_RACC_PRODIS_SHIFT (2U)
36481#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
36482
36483#define ENET_RACC_LINEDIS_MASK (0x40U)
36484#define ENET_RACC_LINEDIS_SHIFT (6U)
36489#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
36490
36491#define ENET_RACC_SHIFT16_MASK (0x80U)
36492#define ENET_RACC_SHIFT16_SHIFT (7U)
36497#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
36503#define ENET_RCMR_CMP0_MASK (0x7U)
36504#define ENET_RCMR_CMP0_SHIFT (0U)
36507#define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)
36508
36509#define ENET_RCMR_CMP1_MASK (0x70U)
36510#define ENET_RCMR_CMP1_SHIFT (4U)
36513#define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)
36514
36515#define ENET_RCMR_CMP2_MASK (0x700U)
36516#define ENET_RCMR_CMP2_SHIFT (8U)
36519#define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)
36520
36521#define ENET_RCMR_CMP3_MASK (0x7000U)
36522#define ENET_RCMR_CMP3_SHIFT (12U)
36525#define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)
36526
36527#define ENET_RCMR_MATCHEN_MASK (0x10000U)
36528#define ENET_RCMR_MATCHEN_SHIFT (16U)
36533#define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)
36536/* The count of ENET_RCMR */
36537#define ENET_RCMR_COUNT (2U)
36538
36542#define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU)
36543#define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U)
36546#define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)
36547
36548#define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U)
36549#define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U)
36556#define ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)
36557
36558#define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U)
36559#define ENET_DMACFG_CALC_NOIPG_SHIFT (17U)
36568#define ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)
36571/* The count of ENET_DMACFG */
36572#define ENET_DMACFG_COUNT (2U)
36573
36577#define ENET_RDAR1_RDAR_MASK (0x1000000U)
36578#define ENET_RDAR1_RDAR_SHIFT (24U)
36581#define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)
36587#define ENET_TDAR1_TDAR_MASK (0x1000000U)
36588#define ENET_TDAR1_TDAR_SHIFT (24U)
36591#define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)
36597#define ENET_RDAR2_RDAR_MASK (0x1000000U)
36598#define ENET_RDAR2_RDAR_SHIFT (24U)
36601#define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)
36607#define ENET_TDAR2_TDAR_MASK (0x1000000U)
36608#define ENET_TDAR2_TDAR_SHIFT (24U)
36611#define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)
36617#define ENET_QOS_TX_SCHEME_MASK (0x7U)
36618#define ENET_QOS_TX_SCHEME_SHIFT (0U)
36624#define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)
36625
36626#define ENET_QOS_RX_FLUSH0_MASK (0x8U)
36627#define ENET_QOS_RX_FLUSH0_SHIFT (3U)
36632#define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)
36633
36634#define ENET_QOS_RX_FLUSH1_MASK (0x10U)
36635#define ENET_QOS_RX_FLUSH1_SHIFT (4U)
36640#define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)
36641
36642#define ENET_QOS_RX_FLUSH2_MASK (0x20U)
36643#define ENET_QOS_RX_FLUSH2_SHIFT (5U)
36648#define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)
36654#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
36655#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
36658#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
36664#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
36665#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
36668#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
36674#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
36675#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
36678#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
36684#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
36685#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
36688#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
36694#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
36695#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
36698#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
36704#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
36705#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
36708#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
36714#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
36715#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
36718#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
36724#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
36725#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
36728#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
36734#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
36735#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
36738#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
36744#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
36745#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
36748#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
36754#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
36755#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
36758#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
36764#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
36765#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
36768#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
36774#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
36775#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
36778#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
36784#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
36785#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
36788#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
36794#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
36795#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
36798#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
36804#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
36805#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
36808#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
36814#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
36815#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
36818#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
36824#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
36825#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
36828#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
36834#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
36835#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
36838#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
36844#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
36845#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
36848#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
36854#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
36855#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
36858#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
36864#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
36865#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
36868#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
36874#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
36875#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
36878#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
36884#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
36885#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
36888#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
36894#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
36895#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
36898#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
36904#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
36905#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
36908#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
36914#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
36915#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
36918#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
36924#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
36925#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
36928#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
36934#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
36935#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
36938#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
36944#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
36945#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
36948#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
36954#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
36955#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
36958#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
36964#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
36965#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
36968#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
36974#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
36975#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
36978#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
36984#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
36985#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
36988#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
36994#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
36995#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
36998#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
37004#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
37005#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
37008#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
37014#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
37015#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
37018#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
37024#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
37025#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
37028#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
37034#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
37035#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
37038#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
37044#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
37045#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
37048#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
37054#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
37055#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
37058#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
37064#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
37065#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
37068#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
37074#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
37075#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
37078#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
37084#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
37085#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
37088#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
37094#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
37095#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
37098#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
37104#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
37105#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
37108#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
37114#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
37115#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
37118#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
37124#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
37125#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
37128#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
37134#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
37135#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
37138#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
37144#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
37145#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
37148#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
37154#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
37155#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
37158#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
37164#define ENET_ATCR_EN_MASK (0x1U)
37165#define ENET_ATCR_EN_SHIFT (0U)
37170#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
37171
37172#define ENET_ATCR_OFFEN_MASK (0x4U)
37173#define ENET_ATCR_OFFEN_SHIFT (2U)
37180#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
37181
37182#define ENET_ATCR_OFFRST_MASK (0x8U)
37183#define ENET_ATCR_OFFRST_SHIFT (3U)
37188#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
37189
37190#define ENET_ATCR_PEREN_MASK (0x10U)
37191#define ENET_ATCR_PEREN_SHIFT (4U)
37198#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
37199
37200#define ENET_ATCR_PINPER_MASK (0x80U)
37201#define ENET_ATCR_PINPER_SHIFT (7U)
37206#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
37207
37208#define ENET_ATCR_RESTART_MASK (0x200U)
37209#define ENET_ATCR_RESTART_SHIFT (9U)
37212#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
37213
37214#define ENET_ATCR_CAPTURE_MASK (0x800U)
37215#define ENET_ATCR_CAPTURE_SHIFT (11U)
37220#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
37221
37222#define ENET_ATCR_SLAVE_MASK (0x2000U)
37223#define ENET_ATCR_SLAVE_SHIFT (13U)
37229#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
37235#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
37236#define ENET_ATVR_ATIME_SHIFT (0U)
37237#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
37243#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
37244#define ENET_ATOFF_OFFSET_SHIFT (0U)
37245#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
37251#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
37252#define ENET_ATPER_PERIOD_SHIFT (0U)
37255#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
37261#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
37262#define ENET_ATCOR_COR_SHIFT (0U)
37265#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
37271#define ENET_ATINC_INC_MASK (0x7FU)
37272#define ENET_ATINC_INC_SHIFT (0U)
37275#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
37276
37277#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
37278#define ENET_ATINC_INC_CORR_SHIFT (8U)
37281#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
37287#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
37288#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
37292#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
37298#define ENET_TGSR_TF0_MASK (0x1U)
37299#define ENET_TGSR_TF0_SHIFT (0U)
37304#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
37305
37306#define ENET_TGSR_TF1_MASK (0x2U)
37307#define ENET_TGSR_TF1_SHIFT (1U)
37312#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
37313
37314#define ENET_TGSR_TF2_MASK (0x4U)
37315#define ENET_TGSR_TF2_SHIFT (2U)
37320#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
37321
37322#define ENET_TGSR_TF3_MASK (0x8U)
37323#define ENET_TGSR_TF3_SHIFT (3U)
37328#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
37334#define ENET_TCSR_TDRE_MASK (0x1U)
37335#define ENET_TCSR_TDRE_SHIFT (0U)
37340#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
37341
37342#define ENET_TCSR_TMODE_MASK (0x3CU)
37343#define ENET_TCSR_TMODE_SHIFT (2U)
37360#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
37361
37362#define ENET_TCSR_TIE_MASK (0x40U)
37363#define ENET_TCSR_TIE_SHIFT (6U)
37368#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
37369
37370#define ENET_TCSR_TF_MASK (0x80U)
37371#define ENET_TCSR_TF_SHIFT (7U)
37376#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
37377
37378#define ENET_TCSR_TPWC_MASK (0xF800U)
37379#define ENET_TCSR_TPWC_SHIFT (11U)
37387#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
37390/* The count of ENET_TCSR */
37391#define ENET_TCSR_COUNT (4U)
37392
37396#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
37397#define ENET_TCCR_TCC_SHIFT (0U)
37400#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
37403/* The count of ENET_TCCR */
37404#define ENET_TCCR_COUNT (4U)
37405
37406 /* end of group ENET_Register_Masks */
37410
37411
37412/* ENET - Peripheral instance base addresses */
37414#define ENET_BASE (0x40424000u)
37416#define ENET ((ENET_Type *)ENET_BASE)
37418#define ENET_1G_BASE (0x40420000u)
37420#define ENET_1G ((ENET_Type *)ENET_1G_BASE)
37422#define ENET_BASE_ADDRS { ENET_BASE, ENET_1G_BASE }
37424#define ENET_BASE_PTRS { ENET, ENET_1G }
37426#define ENET_Transmit_IRQS { ENET_IRQn, ENET_1G_IRQn }
37427#define ENET_Receive_IRQS { ENET_IRQn, ENET_1G_IRQn }
37428#define ENET_Error_IRQS { ENET_IRQn, ENET_1G_IRQn }
37429#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, ENET_1G_1588_Timer_IRQn }
37430#define ENET_Ts_IRQS { ENET_IRQn, ENET_1G_IRQn }
37431/* ENET Buffer Descriptor and Buffer Address Alignment. */
37432#define ENET_BUFF_ALIGNMENT (64U)
37433
37434 /* end of group ENET_Peripheral_Access_Layer */
37438
37439
37440/* ----------------------------------------------------------------------------
37441 -- ETHERNET_PLL Peripheral Access Layer
37442 ---------------------------------------------------------------------------- */
37443
37450typedef struct {
37451 struct { /* offset: 0x0 */
37452 __IO uint32_t RW;
37453 __IO uint32_t SET;
37454 __IO uint32_t CLR;
37455 __IO uint32_t TOG;
37456 } CTRL0;
37457 struct { /* offset: 0x10 */
37458 __IO uint32_t RW;
37459 __IO uint32_t SET;
37460 __IO uint32_t CLR;
37461 __IO uint32_t TOG;
37462 } SPREAD_SPECTRUM;
37463 struct { /* offset: 0x20 */
37464 __IO uint32_t RW;
37465 __IO uint32_t SET;
37466 __IO uint32_t CLR;
37467 __IO uint32_t TOG;
37468 } NUMERATOR;
37469 struct { /* offset: 0x30 */
37470 __IO uint32_t RW;
37471 __IO uint32_t SET;
37472 __IO uint32_t CLR;
37473 __IO uint32_t TOG;
37474 } DENOMINATOR;
37476
37477/* ----------------------------------------------------------------------------
37478 -- ETHERNET_PLL Register Masks
37479 ---------------------------------------------------------------------------- */
37480
37489#define ETHERNET_PLL_CTRL0_DIV_SELECT_MASK (0x7FU)
37490#define ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT (0U)
37493#define ETHERNET_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_DIV_SELECT_MASK)
37494
37495#define ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK (0x100U)
37496#define ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT (8U)
37501#define ETHERNET_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK)
37502
37503#define ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U)
37504#define ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U)
37509#define ETHERNET_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK)
37510
37511#define ETHERNET_PLL_CTRL0_POWERUP_MASK (0x4000U)
37512#define ETHERNET_PLL_CTRL0_POWERUP_SHIFT (14U)
37517#define ETHERNET_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POWERUP_SHIFT)) & ETHERNET_PLL_CTRL0_POWERUP_MASK)
37518
37519#define ETHERNET_PLL_CTRL0_ENABLE_MASK (0x8000U)
37520#define ETHERNET_PLL_CTRL0_ENABLE_SHIFT (15U)
37525#define ETHERNET_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_MASK)
37526
37527#define ETHERNET_PLL_CTRL0_BYPASS_MASK (0x10000U)
37528#define ETHERNET_PLL_CTRL0_BYPASS_SHIFT (16U)
37533#define ETHERNET_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BYPASS_SHIFT)) & ETHERNET_PLL_CTRL0_BYPASS_MASK)
37534
37535#define ETHERNET_PLL_CTRL0_DITHER_EN_MASK (0x20000U)
37536#define ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT (17U)
37541#define ETHERNET_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT)) & ETHERNET_PLL_CTRL0_DITHER_EN_MASK)
37542
37543#define ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U)
37544#define ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT (19U)
37547#define ETHERNET_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK)
37548
37549#define ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U)
37550#define ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT (22U)
37553#define ETHERNET_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT)) & ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK)
37554
37555#define ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U)
37556#define ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U)
37565#define ETHERNET_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK)
37566
37567#define ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK (0x20000000U)
37568#define ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT (29U)
37573#define ETHERNET_PLL_CTRL0_BIAS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK)
37579#define ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU)
37580#define ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U)
37583#define ETHERNET_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK)
37584
37585#define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U)
37586#define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U)
37589#define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
37590
37591#define ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U)
37592#define ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U)
37595#define ETHERNET_PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK)
37601#define ETHERNET_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
37602#define ETHERNET_PLL_NUMERATOR_NUM_SHIFT (0U)
37605#define ETHERNET_PLL_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_NUMERATOR_NUM_SHIFT)) & ETHERNET_PLL_NUMERATOR_NUM_MASK)
37611#define ETHERNET_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
37612#define ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT (0U)
37615#define ETHERNET_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT)) & ETHERNET_PLL_DENOMINATOR_DENOM_MASK) /* end of group ETHERNET_PLL_Register_Masks */
37622
37623
37624/* ETHERNET_PLL - Peripheral instance base addresses */
37626#define ETHERNET_PLL_BASE (0u)
37628#define ETHERNET_PLL ((ETHERNET_PLL_Type *)ETHERNET_PLL_BASE)
37630#define ETHERNET_PLL_BASE_ADDRS { ETHERNET_PLL_BASE }
37632#define ETHERNET_PLL_BASE_PTRS { ETHERNET_PLL }
37633 /* end of group ETHERNET_PLL_Peripheral_Access_Layer */
37637
37638
37639/* ----------------------------------------------------------------------------
37640 -- EWM Peripheral Access Layer
37641 ---------------------------------------------------------------------------- */
37642
37649typedef struct {
37650 __IO uint8_t CTRL;
37651 __O uint8_t SERV;
37652 __IO uint8_t CMPL;
37653 __IO uint8_t CMPH;
37654 __IO uint8_t CLKCTRL;
37655 __IO uint8_t CLKPRESCALER;
37656} EWM_Type;
37657
37658/* ----------------------------------------------------------------------------
37659 -- EWM Register Masks
37660 ---------------------------------------------------------------------------- */
37661
37670#define EWM_CTRL_EWMEN_MASK (0x1U)
37671#define EWM_CTRL_EWMEN_SHIFT (0U)
37676#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
37677
37678#define EWM_CTRL_ASSIN_MASK (0x2U)
37679#define EWM_CTRL_ASSIN_SHIFT (1U)
37684#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
37685
37686#define EWM_CTRL_INEN_MASK (0x4U)
37687#define EWM_CTRL_INEN_SHIFT (2U)
37692#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
37693
37694#define EWM_CTRL_INTEN_MASK (0x8U)
37695#define EWM_CTRL_INTEN_SHIFT (3U)
37700#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
37706#define EWM_SERV_SERVICE_MASK (0xFFU)
37707#define EWM_SERV_SERVICE_SHIFT (0U)
37710#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
37716#define EWM_CMPL_COMPAREL_MASK (0xFFU)
37717#define EWM_CMPL_COMPAREL_SHIFT (0U)
37720#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
37726#define EWM_CMPH_COMPAREH_MASK (0xFFU)
37727#define EWM_CMPH_COMPAREH_SHIFT (0U)
37730#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
37736#define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
37737#define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
37740#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
37746#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
37747#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
37750#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) /* end of group EWM_Register_Masks */
37757
37758
37759/* EWM - Peripheral instance base addresses */
37761#define EWM_BASE (0x4002C000u)
37763#define EWM ((EWM_Type *)EWM_BASE)
37765#define EWM_BASE_ADDRS { EWM_BASE }
37767#define EWM_BASE_PTRS { EWM }
37769#define EWM_IRQS { EWM_IRQn }
37770 /* end of group EWM_Peripheral_Access_Layer */
37774
37775
37776/* ----------------------------------------------------------------------------
37777 -- FLEXIO Peripheral Access Layer
37778 ---------------------------------------------------------------------------- */
37779
37786typedef struct {
37787 __I uint32_t VERID;
37788 __I uint32_t PARAM;
37789 __IO uint32_t CTRL;
37790 __I uint32_t PIN;
37791 __IO uint32_t SHIFTSTAT;
37792 __IO uint32_t SHIFTERR;
37793 __IO uint32_t TIMSTAT;
37794 uint8_t RESERVED_0[4];
37795 __IO uint32_t SHIFTSIEN;
37796 __IO uint32_t SHIFTEIEN;
37797 __IO uint32_t TIMIEN;
37798 uint8_t RESERVED_1[4];
37799 __IO uint32_t SHIFTSDEN;
37800 uint8_t RESERVED_2[4];
37801 __IO uint32_t TIMERSDEN;
37802 uint8_t RESERVED_3[4];
37803 __IO uint32_t SHIFTSTATE;
37804 uint8_t RESERVED_4[60];
37805 __IO uint32_t SHIFTCTL[8];
37806 uint8_t RESERVED_5[96];
37807 __IO uint32_t SHIFTCFG[8];
37808 uint8_t RESERVED_6[224];
37809 __IO uint32_t SHIFTBUF[8];
37810 uint8_t RESERVED_7[96];
37811 __IO uint32_t SHIFTBUFBIS[8];
37812 uint8_t RESERVED_8[96];
37813 __IO uint32_t SHIFTBUFBYS[8];
37814 uint8_t RESERVED_9[96];
37815 __IO uint32_t SHIFTBUFBBS[8];
37816 uint8_t RESERVED_10[96];
37817 __IO uint32_t TIMCTL[8];
37818 uint8_t RESERVED_11[96];
37819 __IO uint32_t TIMCFG[8];
37820 uint8_t RESERVED_12[96];
37821 __IO uint32_t TIMCMP[8];
37822 uint8_t RESERVED_13[352];
37823 __IO uint32_t SHIFTBUFNBS[8];
37824 uint8_t RESERVED_14[96];
37825 __IO uint32_t SHIFTBUFHWS[8];
37826 uint8_t RESERVED_15[96];
37827 __IO uint32_t SHIFTBUFNIS[8];
37828 uint8_t RESERVED_16[96];
37829 __IO uint32_t SHIFTBUFOES[8];
37830 uint8_t RESERVED_17[96];
37831 __IO uint32_t SHIFTBUFEOS[8];
37832} FLEXIO_Type;
37833
37834/* ----------------------------------------------------------------------------
37835 -- FLEXIO Register Masks
37836 ---------------------------------------------------------------------------- */
37837
37846#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
37847#define FLEXIO_VERID_FEATURE_SHIFT (0U)
37854#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
37855
37856#define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
37857#define FLEXIO_VERID_MINOR_SHIFT (16U)
37860#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
37861
37862#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
37863#define FLEXIO_VERID_MAJOR_SHIFT (24U)
37866#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
37872#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
37873#define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
37876#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
37877
37878#define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
37879#define FLEXIO_PARAM_TIMER_SHIFT (8U)
37882#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
37883
37884#define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
37885#define FLEXIO_PARAM_PIN_SHIFT (16U)
37888#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
37889
37890#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
37891#define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
37894#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
37900#define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
37901#define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
37906#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
37907
37908#define FLEXIO_CTRL_SWRST_MASK (0x2U)
37909#define FLEXIO_CTRL_SWRST_SHIFT (1U)
37914#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
37915
37916#define FLEXIO_CTRL_FASTACC_MASK (0x4U)
37917#define FLEXIO_CTRL_FASTACC_SHIFT (2U)
37922#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
37923
37924#define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
37925#define FLEXIO_CTRL_DBGE_SHIFT (30U)
37930#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
37931
37932#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
37933#define FLEXIO_CTRL_DOZEN_SHIFT (31U)
37938#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
37944#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)
37945#define FLEXIO_PIN_PDI_SHIFT (0U)
37948#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
37954#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU)
37955#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
37958#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
37964#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU)
37965#define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
37968#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
37974#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU)
37975#define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
37978#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
37984#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU)
37985#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
37988#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
37994#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU)
37995#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
37998#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
38004#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU)
38005#define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
38008#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
38014#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU)
38015#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
38018#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
38024#define FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU)
38025#define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U)
38028#define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)
38034#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
38035#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
38038#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
38044#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
38045#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
38056#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
38057
38058#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
38059#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
38064#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
38065
38066#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)
38067#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
38070#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
38071
38072#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
38073#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
38080#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
38081
38082#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
38083#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
38088#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
38089
38090#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U)
38091#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
38094#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
38097/* The count of FLEXIO_SHIFTCTL */
38098#define FLEXIO_SHIFTCTL_COUNT (8U)
38099
38103#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
38104#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
38111#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
38112
38113#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
38114#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
38121#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
38122
38123#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
38124#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
38129#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
38130
38131#define FLEXIO_SHIFTCFG_LATST_MASK (0x200U)
38132#define FLEXIO_SHIFTCFG_LATST_SHIFT (9U)
38137#define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)
38138
38139#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)
38140#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
38143#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
38146/* The count of FLEXIO_SHIFTCFG */
38147#define FLEXIO_SHIFTCFG_COUNT (8U)
38148
38152#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
38153#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
38156#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
38159/* The count of FLEXIO_SHIFTBUF */
38160#define FLEXIO_SHIFTBUF_COUNT (8U)
38161
38165#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
38166#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
38169#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
38172/* The count of FLEXIO_SHIFTBUFBIS */
38173#define FLEXIO_SHIFTBUFBIS_COUNT (8U)
38174
38178#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
38179#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
38182#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
38185/* The count of FLEXIO_SHIFTBUFBYS */
38186#define FLEXIO_SHIFTBUFBYS_COUNT (8U)
38187
38191#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
38192#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
38195#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
38198/* The count of FLEXIO_SHIFTBUFBBS */
38199#define FLEXIO_SHIFTBUFBBS_COUNT (8U)
38200
38204#define FLEXIO_TIMCTL_TIMOD_MASK (0x7U)
38205#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
38216#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
38217
38218#define FLEXIO_TIMCTL_ONETIM_MASK (0x20U)
38219#define FLEXIO_TIMCTL_ONETIM_SHIFT (5U)
38224#define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)
38225
38226#define FLEXIO_TIMCTL_PININS_MASK (0x40U)
38227#define FLEXIO_TIMCTL_PININS_SHIFT (6U)
38232#define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)
38233
38234#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
38235#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
38240#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
38241
38242#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)
38243#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
38246#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
38247
38248#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
38249#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
38256#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
38257
38258#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
38259#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
38264#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
38265
38266#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
38267#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
38272#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
38273
38274#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)
38275#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
38278#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
38281/* The count of FLEXIO_TIMCTL */
38282#define FLEXIO_TIMCTL_COUNT (8U)
38283
38287#define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
38288#define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
38293#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
38294
38295#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
38296#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
38303#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
38304
38305#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
38306#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
38317#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
38318
38319#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
38320#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
38331#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
38332
38333#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
38334#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
38345#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
38346
38347#define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U)
38348#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
38359#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
38360
38361#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
38362#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
38369#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
38372/* The count of FLEXIO_TIMCFG */
38373#define FLEXIO_TIMCFG_COUNT (8U)
38374
38378#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
38379#define FLEXIO_TIMCMP_CMP_SHIFT (0U)
38382#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
38385/* The count of FLEXIO_TIMCMP */
38386#define FLEXIO_TIMCMP_COUNT (8U)
38387
38391#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
38392#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
38395#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
38398/* The count of FLEXIO_SHIFTBUFNBS */
38399#define FLEXIO_SHIFTBUFNBS_COUNT (8U)
38400
38404#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
38405#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
38408#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
38411/* The count of FLEXIO_SHIFTBUFHWS */
38412#define FLEXIO_SHIFTBUFHWS_COUNT (8U)
38413
38417#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
38418#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
38421#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
38424/* The count of FLEXIO_SHIFTBUFNIS */
38425#define FLEXIO_SHIFTBUFNIS_COUNT (8U)
38426
38430#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU)
38431#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U)
38434#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)
38437/* The count of FLEXIO_SHIFTBUFOES */
38438#define FLEXIO_SHIFTBUFOES_COUNT (8U)
38439
38443#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU)
38444#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U)
38447#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)
38450/* The count of FLEXIO_SHIFTBUFEOS */
38451#define FLEXIO_SHIFTBUFEOS_COUNT (8U)
38452
38453 /* end of group FLEXIO_Register_Masks */
38457
38458
38459/* FLEXIO - Peripheral instance base addresses */
38461#define FLEXIO1_BASE (0x400AC000u)
38463#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)
38465#define FLEXIO2_BASE (0x400B0000u)
38467#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)
38469#define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
38471#define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
38473#define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }
38474 /* end of group FLEXIO_Peripheral_Access_Layer */
38478
38479
38480/* ----------------------------------------------------------------------------
38481 -- FLEXRAM Peripheral Access Layer
38482 ---------------------------------------------------------------------------- */
38483
38490typedef struct {
38491 __IO uint32_t TCM_CTRL;
38492 __IO uint32_t OCRAM_MAGIC_ADDR;
38493 __IO uint32_t DTCM_MAGIC_ADDR;
38494 __IO uint32_t ITCM_MAGIC_ADDR;
38495 __IO uint32_t INT_STATUS;
38496 __IO uint32_t INT_STAT_EN;
38497 __IO uint32_t INT_SIG_EN;
38498 __I uint32_t OCRAM_ECC_SINGLE_ERROR_INFO;
38499 __I uint32_t OCRAM_ECC_SINGLE_ERROR_ADDR;
38500 __I uint32_t OCRAM_ECC_SINGLE_ERROR_DATA_LSB;
38501 __I uint32_t OCRAM_ECC_SINGLE_ERROR_DATA_MSB;
38502 __I uint32_t OCRAM_ECC_MULTI_ERROR_INFO;
38503 __I uint32_t OCRAM_ECC_MULTI_ERROR_ADDR;
38504 __I uint32_t OCRAM_ECC_MULTI_ERROR_DATA_LSB;
38505 __I uint32_t OCRAM_ECC_MULTI_ERROR_DATA_MSB;
38506 __I uint32_t ITCM_ECC_SINGLE_ERROR_INFO;
38507 __I uint32_t ITCM_ECC_SINGLE_ERROR_ADDR;
38508 __I uint32_t ITCM_ECC_SINGLE_ERROR_DATA_LSB;
38509 __I uint32_t ITCM_ECC_SINGLE_ERROR_DATA_MSB;
38510 __I uint32_t ITCM_ECC_MULTI_ERROR_INFO;
38511 __I uint32_t ITCM_ECC_MULTI_ERROR_ADDR;
38512 __I uint32_t ITCM_ECC_MULTI_ERROR_DATA_LSB;
38513 __I uint32_t ITCM_ECC_MULTI_ERROR_DATA_MSB;
38514 __I uint32_t D0TCM_ECC_SINGLE_ERROR_INFO;
38515 __I uint32_t D0TCM_ECC_SINGLE_ERROR_ADDR;
38516 __I uint32_t D0TCM_ECC_SINGLE_ERROR_DATA;
38517 __I uint32_t D0TCM_ECC_MULTI_ERROR_INFO;
38518 __I uint32_t D0TCM_ECC_MULTI_ERROR_ADDR;
38519 __I uint32_t D0TCM_ECC_MULTI_ERROR_DATA;
38520 __I uint32_t D1TCM_ECC_SINGLE_ERROR_INFO;
38521 __I uint32_t D1TCM_ECC_SINGLE_ERROR_ADDR;
38522 __I uint32_t D1TCM_ECC_SINGLE_ERROR_DATA;
38523 __I uint32_t D1TCM_ECC_MULTI_ERROR_INFO;
38524 __I uint32_t D1TCM_ECC_MULTI_ERROR_ADDR;
38525 __I uint32_t D1TCM_ECC_MULTI_ERROR_DATA;
38526 uint8_t RESERVED_0[124];
38527 __IO uint32_t FLEXRAM_CTRL;
38528 __I uint32_t OCRAM_PIPELINE_STATUS;
38529} FLEXRAM_Type;
38530
38531/* ----------------------------------------------------------------------------
38532 -- FLEXRAM Register Masks
38533 ---------------------------------------------------------------------------- */
38534
38543#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)
38544#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)
38549#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
38550
38551#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)
38552#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)
38557#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
38558
38559#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)
38560#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)
38563#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
38564
38565#define FLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U)
38566#define FLEXRAM_TCM_CTRL_Reserved_SHIFT (3U)
38569#define FLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK)
38575#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U)
38576#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U)
38581#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK)
38582
38583#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x3FFFEU)
38584#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U)
38587#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK)
38588
38589#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U)
38590#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (18U)
38593#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
38599#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U)
38600#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U)
38605#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK)
38606
38607#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU)
38608#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U)
38611#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK)
38612
38613#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)
38614#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U)
38617#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK)
38623#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U)
38624#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U)
38629#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK)
38630
38631#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU)
38632#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U)
38635#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK)
38636
38637#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)
38638#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U)
38641#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK)
38647#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U)
38648#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U)
38653#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK)
38654
38655#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U)
38656#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U)
38661#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK)
38662
38663#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U)
38664#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U)
38669#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK)
38670
38671#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)
38672#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
38677#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
38678
38679#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)
38680#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
38685#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
38686
38687#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
38688#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
38693#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
38694
38695#define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK (0x40U)
38696#define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT (6U)
38701#define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK)
38702
38703#define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK (0x80U)
38704#define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT (7U)
38709#define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK)
38710
38711#define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK (0x100U)
38712#define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT (8U)
38717#define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK)
38718
38719#define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK (0x200U)
38720#define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT (9U)
38725#define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK)
38726
38727#define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK (0x400U)
38728#define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT (10U)
38733#define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK)
38734
38735#define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK (0x800U)
38736#define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT (11U)
38741#define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK)
38742
38743#define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK (0x1000U)
38744#define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT (12U)
38749#define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK)
38750
38751#define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK (0x2000U)
38752#define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT (13U)
38757#define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK)
38758
38759#define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK (0x4000U)
38760#define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT (14U)
38765#define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK)
38766
38767#define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK (0x8000U)
38768#define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT (15U)
38773#define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK)
38774
38775#define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK (0x10000U)
38776#define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT (16U)
38781#define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK)
38782
38783#define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK (0x20000U)
38784#define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT (17U)
38789#define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK)
38790
38791#define FLEXRAM_INT_STATUS_Reserved_MASK (0xFFFC0000U)
38792#define FLEXRAM_INT_STATUS_Reserved_SHIFT (18U)
38795#define FLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK)
38801#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U)
38802#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U)
38807#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK)
38808
38809#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U)
38810#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U)
38815#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK)
38816
38817#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U)
38818#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U)
38823#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK)
38824
38825#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
38826#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
38831#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
38832
38833#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
38834#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
38839#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
38840
38841#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
38842#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
38847#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
38848
38849#define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK (0x40U)
38850#define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT (6U)
38855#define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK)
38856
38857#define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK (0x80U)
38858#define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT (7U)
38863#define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK)
38864
38865#define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK (0x100U)
38866#define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT (8U)
38871#define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK)
38872
38873#define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK (0x200U)
38874#define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT (9U)
38879#define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK)
38880
38881#define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK (0x400U)
38882#define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT (10U)
38887#define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK)
38888
38889#define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK (0x800U)
38890#define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT (11U)
38895#define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK)
38896
38897#define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK (0x1000U)
38898#define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT (12U)
38903#define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK)
38904
38905#define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK (0x2000U)
38906#define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT (13U)
38911#define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK)
38912
38913#define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK (0x4000U)
38914#define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT (14U)
38919#define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK)
38920
38921#define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK (0x8000U)
38922#define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT (15U)
38927#define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK)
38928
38929#define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK (0x10000U)
38930#define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT (16U)
38935#define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK)
38936
38937#define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK (0x20000U)
38938#define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT (17U)
38943#define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK)
38944
38945#define FLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFC0000U)
38946#define FLEXRAM_INT_STAT_EN_Reserved_SHIFT (18U)
38949#define FLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK)
38955#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U)
38956#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U)
38961#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK)
38962
38963#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U)
38964#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U)
38969#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK)
38970
38971#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U)
38972#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U)
38977#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK)
38978
38979#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)
38980#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
38985#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
38986
38987#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)
38988#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
38993#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
38994
38995#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
38996#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
39001#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
39002
39003#define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK (0x40U)
39004#define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT (6U)
39009#define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK)
39010
39011#define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK (0x80U)
39012#define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT (7U)
39017#define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK)
39018
39019#define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK (0x100U)
39020#define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT (8U)
39025#define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK)
39026
39027#define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK (0x200U)
39028#define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT (9U)
39033#define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK)
39034
39035#define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK (0x400U)
39036#define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT (10U)
39041#define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK)
39042
39043#define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK (0x800U)
39044#define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT (11U)
39049#define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK)
39050
39051#define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK (0x1000U)
39052#define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT (12U)
39057#define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK)
39058
39059#define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK (0x2000U)
39060#define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT (13U)
39065#define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK)
39066
39067#define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK (0x4000U)
39068#define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT (14U)
39073#define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK)
39074
39075#define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x8000U)
39076#define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (15U)
39081#define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK)
39082
39083#define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x10000U)
39084#define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (16U)
39089#define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK)
39090
39091#define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK (0x20000U)
39092#define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT (17U)
39097#define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK)
39098
39099#define FLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFC0000U)
39100#define FLEXRAM_INT_SIG_EN_Reserved_SHIFT (18U)
39103#define FLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK)
39109#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK (0xFFU)
39110#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT (0U)
39113#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK)
39114
39115#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK (0xFF00U)
39116#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT (8U)
39119#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK)
39120
39121#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFFF0000U)
39122#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (16U)
39125#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
39131#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
39132#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT (0U)
39135#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK)
39141#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
39142#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT (0U)
39145#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK)
39151#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
39152#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT (0U)
39155#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK)
39161#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK (0xFFU)
39162#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT (0U)
39165#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK)
39166
39167#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFFFFF00U)
39168#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (8U)
39171#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
39177#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
39178#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT (0U)
39181#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK)
39187#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
39188#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT (0U)
39191#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK)
39197#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
39198#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT (0U)
39201#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK)
39207#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK (0x1U)
39208#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT (0U)
39211#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK)
39212
39213#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK (0xEU)
39214#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT (1U)
39217#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK)
39218
39219#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK (0xF0U)
39220#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT (4U)
39223#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK)
39224
39225#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK (0xF00U)
39226#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT (8U)
39229#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK)
39230
39231#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK (0xFF000U)
39232#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT (12U)
39235#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK)
39236
39237#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF00000U)
39238#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (20U)
39241#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
39247#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
39248#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT (0U)
39251#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK)
39257#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
39258#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT (0U)
39261#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK)
39267#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
39268#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT (0U)
39271#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK)
39277#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK (0x1U)
39278#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT (0U)
39281#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK)
39282
39283#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK (0xEU)
39284#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT (1U)
39287#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK)
39288
39289#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK (0xF0U)
39290#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT (4U)
39293#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK)
39294
39295#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK (0xF00U)
39296#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT (8U)
39299#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK)
39300
39301#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK (0xFF000U)
39302#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT (12U)
39305#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK)
39306
39307#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF00000U)
39308#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (20U)
39311#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
39317#define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
39318#define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT (0U)
39321#define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK)
39327#define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
39328#define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT (0U)
39331#define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK)
39337#define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
39338#define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT (0U)
39341#define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK)
39347#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK (0x1U)
39348#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT (0U)
39351#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK)
39352
39353#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK (0xEU)
39354#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT (1U)
39357#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK)
39358
39359#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK (0xF0U)
39360#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT (4U)
39363#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK)
39364
39365#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK (0xF00U)
39366#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT (8U)
39369#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK)
39370
39371#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK (0x7F000U)
39372#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT (12U)
39375#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK)
39376
39377#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U)
39378#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U)
39381#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
39387#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
39388#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT (0U)
39391#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK)
39397#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU)
39398#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT (0U)
39401#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK)
39407#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK (0x1U)
39408#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT (0U)
39411#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK)
39412
39413#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK (0xEU)
39414#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT (1U)
39417#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK)
39418
39419#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK (0xF0U)
39420#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT (4U)
39423#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK)
39424
39425#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK (0xF00U)
39426#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT (8U)
39429#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK)
39430
39431#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK (0x7F000U)
39432#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT (12U)
39435#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK)
39436
39437#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U)
39438#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U)
39441#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
39447#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
39448#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT (0U)
39451#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK)
39457#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU)
39458#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT (0U)
39461#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK)
39467#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK (0x1U)
39468#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT (0U)
39471#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK)
39472
39473#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK (0xEU)
39474#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT (1U)
39477#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK)
39478
39479#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK (0xF0U)
39480#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT (4U)
39483#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK)
39484
39485#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK (0xF00U)
39486#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT (8U)
39489#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK)
39490
39491#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK (0x7F000U)
39492#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT (12U)
39495#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK)
39496
39497#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U)
39498#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U)
39501#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
39507#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
39508#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT (0U)
39511#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK)
39517#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU)
39518#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT (0U)
39521#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK)
39527#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK (0x1U)
39528#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT (0U)
39531#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK)
39532
39533#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK (0xEU)
39534#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT (1U)
39537#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK)
39538
39539#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK (0xF0U)
39540#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT (4U)
39543#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK)
39544
39545#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK (0xF00U)
39546#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT (8U)
39549#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK)
39550
39551#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK (0x7F000U)
39552#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT (12U)
39555#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK)
39556
39557#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U)
39558#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U)
39561#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
39567#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
39568#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT (0U)
39571#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK)
39577#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU)
39578#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT (0U)
39581#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK)
39587#define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK (0x1U)
39588#define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT (0U)
39591#define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK)
39592
39593#define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK (0x2U)
39594#define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT (1U)
39597#define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK)
39598
39599#define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK (0x4U)
39600#define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT (2U)
39603#define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK)
39604
39605#define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK (0x8U)
39606#define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT (3U)
39609#define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK)
39610
39611#define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK (0x10U)
39612#define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT (4U)
39615#define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK)
39616
39617#define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK (0x20U)
39618#define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT (5U)
39621#define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK)
39622
39623#define FLEXRAM_FLEXRAM_CTRL_Reserved_MASK (0xFFFFFFC0U)
39624#define FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT (6U)
39627#define FLEXRAM_FLEXRAM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_Reserved_MASK)
39633#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK (0x1U)
39634#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT (0U)
39637#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK)
39638
39639#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x2U)
39640#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (1U)
39643#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK)
39644
39645#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK (0x4U)
39646#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT (2U)
39649#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK)
39650
39651#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x8U)
39652#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (3U)
39655#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK)
39656
39657#define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK (0xFFFFFFF0U)
39658#define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT (4U)
39661#define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK) /* end of group FLEXRAM_Register_Masks */
39668
39669
39670/* FLEXRAM - Peripheral instance base addresses */
39672#define FLEXRAM_BASE (0x40028000u)
39674#define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)
39676#define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE }
39678#define FLEXRAM_BASE_PTRS { FLEXRAM }
39680#define FLEXRAM_IRQS { FLEXRAM_IRQn }
39681#define FLEXRAM_ECC_IRQS { FLEXRAM_ECC_IRQn }
39682 /* end of group FLEXRAM_Peripheral_Access_Layer */
39686
39687
39688/* ----------------------------------------------------------------------------
39689 -- FLEXSPI Peripheral Access Layer
39690 ---------------------------------------------------------------------------- */
39691
39698typedef struct {
39699 __IO uint32_t MCR0;
39700 __IO uint32_t MCR1;
39701 __IO uint32_t MCR2;
39702 __IO uint32_t AHBCR;
39703 __IO uint32_t INTEN;
39704 __IO uint32_t INTR;
39705 __IO uint32_t LUTKEY;
39706 __IO uint32_t LUTCR;
39707 __IO uint32_t AHBRXBUFCR0[8];
39708 uint8_t RESERVED_0[32];
39709 __IO uint32_t FLSHCR0[4];
39710 __IO uint32_t FLSHCR1[4];
39711 __IO uint32_t FLSHCR2[4];
39712 uint8_t RESERVED_1[4];
39713 __IO uint32_t FLSHCR4;
39714 uint8_t RESERVED_2[8];
39715 __IO uint32_t IPCR0;
39716 __IO uint32_t IPCR1;
39717 uint8_t RESERVED_3[8];
39718 __IO uint32_t IPCMD;
39719 uint8_t RESERVED_4[4];
39720 __IO uint32_t IPRXFCR;
39721 __IO uint32_t IPTXFCR;
39722 __IO uint32_t DLLCR[2];
39723 uint8_t RESERVED_5[8];
39724 __I uint32_t MISCCR4;
39725 __I uint32_t MISCCR5;
39726 __I uint32_t MISCCR6;
39727 __I uint32_t MISCCR7;
39728 __I uint32_t STS0;
39729 __I uint32_t STS1;
39730 __I uint32_t STS2;
39731 __I uint32_t AHBSPNDSTS;
39732 __I uint32_t IPRXFSTS;
39733 __I uint32_t IPTXFSTS;
39734 uint8_t RESERVED_6[8];
39735 __I uint32_t RFDR[32];
39736 __O uint32_t TFDR[32];
39737 __IO uint32_t LUT[64];
39738 uint8_t RESERVED_7[256];
39739 __IO uint32_t HMSTRCR[8];
39740 __IO uint32_t HADDRSTART;
39741 __IO uint32_t HADDREND;
39742 __IO uint32_t HADDROFFSET;
39743 uint8_t RESERVED_8[4];
39744 __IO uint32_t IPSNSZSTART0;
39745 __IO uint32_t IPSNSZEND0;
39746 __IO uint32_t IPSNSZSTART1;
39747 __IO uint32_t IPSNSZEND1;
39748 __IO uint32_t AHBBUFREGIONSTART0;
39749 __IO uint32_t AHBBUFREGIONEND0;
39750 __IO uint32_t AHBBUFREGIONSTART1;
39751 __IO uint32_t AHBBUFREGIONEND1;
39752 __IO uint32_t AHBBUFREGIONSTART2;
39753 __IO uint32_t AHBBUFREGIONEND2;
39754 __IO uint32_t AHBBUFREGIONSTART3;
39755 __IO uint32_t AHBBUFREGIONEND3;
39756} FLEXSPI_Type;
39757
39758/* ----------------------------------------------------------------------------
39759 -- FLEXSPI Register Masks
39760 ---------------------------------------------------------------------------- */
39761
39770#define FLEXSPI_MCR0_SWRESET_MASK (0x1U)
39771#define FLEXSPI_MCR0_SWRESET_SHIFT (0U)
39774#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
39775
39776#define FLEXSPI_MCR0_MDIS_MASK (0x2U)
39777#define FLEXSPI_MCR0_MDIS_SHIFT (1U)
39780#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
39781
39782#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
39783#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
39790#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
39791
39792#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U)
39793#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U)
39798#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
39799
39800#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U)
39801#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U)
39806#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
39807
39808#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U)
39809#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U)
39820#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
39821
39822#define FLEXSPI_MCR0_HSEN_MASK (0x800U)
39823#define FLEXSPI_MCR0_HSEN_SHIFT (11U)
39828#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
39829
39830#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
39831#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
39836#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
39837
39838#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
39839#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)
39845#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
39846
39847#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
39848#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
39855#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
39856
39857#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
39858#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
39861#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
39862
39863#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
39864#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
39867#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
39873#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
39874#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
39875#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
39876
39877#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
39878#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
39879#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
39885#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
39886#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
39894#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
39895
39896#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
39897#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
39905#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
39906
39907#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
39908#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
39915#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
39916
39917#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
39918#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
39921#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
39927#define FLEXSPI_AHBCR_APAREN_MASK (0x1U)
39928#define FLEXSPI_AHBCR_APAREN_SHIFT (0U)
39933#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
39934
39935#define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK (0x2U)
39936#define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT (1U)
39939#define FLEXSPI_AHBCR_CLRAHBRXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK)
39940
39941#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
39942#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
39947#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
39948
39949#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
39950#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
39958#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
39959
39960#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
39961#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
39964#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
39965
39966#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
39967#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
39973#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
39974
39975#define FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U)
39976#define FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U)
39981#define FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK)
39982
39983#define FLEXSPI_AHBCR_ECCEN_MASK (0x800U)
39984#define FLEXSPI_AHBCR_ECCEN_SHIFT (11U)
39989#define FLEXSPI_AHBCR_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCEN_SHIFT)) & FLEXSPI_AHBCR_ECCEN_MASK)
39990
39991#define FLEXSPI_AHBCR_SPLITEN_MASK (0x1000U)
39992#define FLEXSPI_AHBCR_SPLITEN_SHIFT (12U)
39997#define FLEXSPI_AHBCR_SPLITEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLITEN_SHIFT)) & FLEXSPI_AHBCR_SPLITEN_MASK)
39998
39999#define FLEXSPI_AHBCR_SPLIT_LIMIT_MASK (0x6000U)
40000#define FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT (13U)
40007#define FLEXSPI_AHBCR_SPLIT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT)) & FLEXSPI_AHBCR_SPLIT_LIMIT_MASK)
40008
40009#define FLEXSPI_AHBCR_KEYECCEN_MASK (0x8000U)
40010#define FLEXSPI_AHBCR_KEYECCEN_SHIFT (15U)
40015#define FLEXSPI_AHBCR_KEYECCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_KEYECCEN_SHIFT)) & FLEXSPI_AHBCR_KEYECCEN_MASK)
40016
40017#define FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK (0x10000U)
40018#define FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT (16U)
40021#define FLEXSPI_AHBCR_ECCSINGLEERRCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK)
40022
40023#define FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK (0x20000U)
40024#define FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT (17U)
40027#define FLEXSPI_AHBCR_ECCMULTIERRCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK)
40028
40029#define FLEXSPI_AHBCR_HMSTRIDREMAP_MASK (0x40000U)
40030#define FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT (18U)
40033#define FLEXSPI_AHBCR_HMSTRIDREMAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT)) & FLEXSPI_AHBCR_HMSTRIDREMAP_MASK)
40034
40035#define FLEXSPI_AHBCR_ECCSWAPEN_MASK (0x80000U)
40036#define FLEXSPI_AHBCR_ECCSWAPEN_SHIFT (19U)
40041#define FLEXSPI_AHBCR_ECCSWAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSWAPEN_SHIFT)) & FLEXSPI_AHBCR_ECCSWAPEN_MASK)
40042
40043#define FLEXSPI_AHBCR_ALIGNMENT_MASK (0x300000U)
40044#define FLEXSPI_AHBCR_ALIGNMENT_SHIFT (20U)
40051#define FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK)
40057#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
40058#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
40061#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
40062
40063#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
40064#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
40067#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
40068
40069#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
40070#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
40073#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
40074
40075#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
40076#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
40079#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
40080
40081#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
40082#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
40085#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
40086
40087#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
40088#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
40091#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
40092
40093#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
40094#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
40097#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
40098
40099#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
40100#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
40103#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
40104
40105#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
40106#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
40109#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
40110
40111#define FLEXSPI_INTEN_AHBBUSERROREN_MASK (0x400U)
40112#define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT (10U)
40115#define FLEXSPI_INTEN_AHBBUSERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK)
40116
40117#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
40118#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
40121#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
40122
40123#define FLEXSPI_INTEN_KEYDONEEN_MASK (0x1000U)
40124#define FLEXSPI_INTEN_KEYDONEEN_SHIFT (12U)
40127#define FLEXSPI_INTEN_KEYDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK)
40128
40129#define FLEXSPI_INTEN_KEYERROREN_MASK (0x2000U)
40130#define FLEXSPI_INTEN_KEYERROREN_SHIFT (13U)
40133#define FLEXSPI_INTEN_KEYERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK)
40134
40135#define FLEXSPI_INTEN_ECCMULTIERREN_MASK (0x4000U)
40136#define FLEXSPI_INTEN_ECCMULTIERREN_SHIFT (14U)
40139#define FLEXSPI_INTEN_ECCMULTIERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCMULTIERREN_SHIFT)) & FLEXSPI_INTEN_ECCMULTIERREN_MASK)
40140
40141#define FLEXSPI_INTEN_ECCSINGLEERREN_MASK (0x8000U)
40142#define FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT (15U)
40145#define FLEXSPI_INTEN_ECCSINGLEERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT)) & FLEXSPI_INTEN_ECCSINGLEERREN_MASK)
40146
40147#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK (0x10000U)
40148#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT (16U)
40151#define FLEXSPI_INTEN_IPCMDSECUREVIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK)
40157#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
40158#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
40162#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
40163
40164#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
40165#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
40168#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
40169
40170#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
40171#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
40174#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
40175
40176#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
40177#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
40181#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
40182
40183#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
40184#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
40188#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
40189
40190#define FLEXSPI_INTR_IPRXWA_MASK (0x20U)
40191#define FLEXSPI_INTR_IPRXWA_SHIFT (5U)
40194#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
40195
40196#define FLEXSPI_INTR_IPTXWE_MASK (0x40U)
40197#define FLEXSPI_INTR_IPTXWE_SHIFT (6U)
40200#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
40201
40202#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
40203#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
40206#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
40207
40208#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
40209#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
40212#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
40213
40214#define FLEXSPI_INTR_AHBBUSERROR_MASK (0x400U)
40215#define FLEXSPI_INTR_AHBBUSERROR_SHIFT (10U)
40218#define FLEXSPI_INTR_AHBBUSERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK)
40219
40220#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
40221#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
40224#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
40225
40226#define FLEXSPI_INTR_KEYDONE_MASK (0x1000U)
40227#define FLEXSPI_INTR_KEYDONE_SHIFT (12U)
40230#define FLEXSPI_INTR_KEYDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK)
40231
40232#define FLEXSPI_INTR_KEYERROR_MASK (0x2000U)
40233#define FLEXSPI_INTR_KEYERROR_SHIFT (13U)
40236#define FLEXSPI_INTR_KEYERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK)
40237
40238#define FLEXSPI_INTR_ECCMULTIERR_MASK (0x4000U)
40239#define FLEXSPI_INTR_ECCMULTIERR_SHIFT (14U)
40242#define FLEXSPI_INTR_ECCMULTIERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCMULTIERR_SHIFT)) & FLEXSPI_INTR_ECCMULTIERR_MASK)
40243
40244#define FLEXSPI_INTR_ECCSINGLEERR_MASK (0x8000U)
40245#define FLEXSPI_INTR_ECCSINGLEERR_SHIFT (15U)
40248#define FLEXSPI_INTR_ECCSINGLEERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCSINGLEERR_SHIFT)) & FLEXSPI_INTR_ECCSINGLEERR_MASK)
40249
40250#define FLEXSPI_INTR_IPCMDSECUREVIO_MASK (0x10000U)
40251#define FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT (16U)
40254#define FLEXSPI_INTR_IPCMDSECUREVIO(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK)
40260#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
40261#define FLEXSPI_LUTKEY_KEY_SHIFT (0U)
40264#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
40270#define FLEXSPI_LUTCR_LOCK_MASK (0x1U)
40271#define FLEXSPI_LUTCR_LOCK_SHIFT (0U)
40274#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
40275
40276#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
40277#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
40280#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
40281
40282#define FLEXSPI_LUTCR_PROTECT_MASK (0x4U)
40283#define FLEXSPI_LUTCR_PROTECT_SHIFT (2U)
40286#define FLEXSPI_LUTCR_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK)
40292#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x3FFU)
40293#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
40296#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
40297
40298#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
40299#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
40302#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
40303
40304#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U)
40305#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
40308#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
40309
40310#define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK (0x40000000U)
40311#define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT (30U)
40314#define FLEXSPI_AHBRXBUFCR0_REGIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK)
40315
40316#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
40317#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
40320#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
40323/* The count of FLEXSPI_AHBRXBUFCR0 */
40324#define FLEXSPI_AHBRXBUFCR0_COUNT (8U)
40325
40329#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
40330#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
40333#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
40334
40335#define FLEXSPI_FLSHCR0_SPLITWREN_MASK (0x40000000U)
40336#define FLEXSPI_FLSHCR0_SPLITWREN_SHIFT (30U)
40339#define FLEXSPI_FLSHCR0_SPLITWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK)
40340
40341#define FLEXSPI_FLSHCR0_SPLITRDEN_MASK (0x80000000U)
40342#define FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT (31U)
40345#define FLEXSPI_FLSHCR0_SPLITRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK)
40348/* The count of FLEXSPI_FLSHCR0 */
40349#define FLEXSPI_FLSHCR0_COUNT (4U)
40350
40354#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
40355#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
40358#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
40359
40360#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
40361#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
40364#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
40365
40366#define FLEXSPI_FLSHCR1_WA_MASK (0x400U)
40367#define FLEXSPI_FLSHCR1_WA_SHIFT (10U)
40370#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
40371
40372#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
40373#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
40376#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
40377
40378#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
40379#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
40384#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
40385
40386#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
40387#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
40393#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
40396/* The count of FLEXSPI_FLSHCR1 */
40397#define FLEXSPI_FLSHCR1_COUNT (4U)
40398
40402#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)
40403#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
40406#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
40407
40408#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
40409#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
40412#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
40413
40414#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)
40415#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
40418#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
40419
40420#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
40421#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
40424#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
40425
40426#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
40427#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
40428#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
40429
40430#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
40431#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
40442#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
40443
40444#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
40445#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
40449#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
40452/* The count of FLEXSPI_FLSHCR2 */
40453#define FLEXSPI_FLSHCR2_COUNT (4U)
40454
40458#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
40459#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
40466#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
40467
40468#define FLEXSPI_FLSHCR4_WMOPT2_MASK (0x2U)
40469#define FLEXSPI_FLSHCR4_WMOPT2_SHIFT (1U)
40477#define FLEXSPI_FLSHCR4_WMOPT2(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK)
40478
40479#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
40480#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
40486#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
40487
40488#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
40489#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
40495#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
40496
40497#define FLEXSPI_FLSHCR4_PAR_WM_MASK (0x600U)
40498#define FLEXSPI_FLSHCR4_PAR_WM_SHIFT (9U)
40501#define FLEXSPI_FLSHCR4_PAR_WM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_WM_SHIFT)) & FLEXSPI_FLSHCR4_PAR_WM_MASK)
40502
40503#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK (0x800U)
40504#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT (11U)
40507#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT)) & FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK)
40513#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
40514#define FLEXSPI_IPCR0_SFAR_SHIFT (0U)
40517#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
40523#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
40524#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
40527#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
40528
40529#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)
40530#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
40533#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
40534
40535#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
40536#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
40539#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
40540
40541#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
40542#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
40547#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
40553#define FLEXSPI_IPCMD_TRG_MASK (0x1U)
40554#define FLEXSPI_IPCMD_TRG_SHIFT (0U)
40557#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
40563#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
40564#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
40567#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
40568
40569#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
40570#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
40575#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
40576
40577#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x7CU)
40578#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
40581#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
40587#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
40588#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
40591#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
40592
40593#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
40594#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
40599#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
40600
40601#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x7CU)
40602#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
40605#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
40611#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
40612#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
40615#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
40616
40617#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
40618#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
40624#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
40625
40626#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
40627#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
40632#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
40633
40634#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
40635#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
40638#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
40639
40640#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
40641#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
40644#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
40647/* The count of FLEXSPI_DLLCR */
40648#define FLEXSPI_DLLCR_COUNT (2U)
40649
40653#define FLEXSPI_MISCCR4_AHBADDRESS_MASK (0xFFFFFFFFU)
40654#define FLEXSPI_MISCCR4_AHBADDRESS_SHIFT (0U)
40657#define FLEXSPI_MISCCR4_AHBADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR4_AHBADDRESS_SHIFT)) & FLEXSPI_MISCCR4_AHBADDRESS_MASK)
40663#define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK (0xFFFFFFFFU)
40664#define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT (0U)
40667#define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT)) & FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK)
40673#define FLEXSPI_MISCCR6_VALID_MASK (0x1U)
40674#define FLEXSPI_MISCCR6_VALID_SHIFT (0U)
40677#define FLEXSPI_MISCCR6_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_VALID_SHIFT)) & FLEXSPI_MISCCR6_VALID_MASK)
40678
40679#define FLEXSPI_MISCCR6_HIT_MASK (0x2U)
40680#define FLEXSPI_MISCCR6_HIT_SHIFT (1U)
40683#define FLEXSPI_MISCCR6_HIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_HIT_SHIFT)) & FLEXSPI_MISCCR6_HIT_MASK)
40684
40685#define FLEXSPI_MISCCR6_ADDRESS_MASK (0xFFFFFFFCU)
40686#define FLEXSPI_MISCCR6_ADDRESS_SHIFT (2U)
40689#define FLEXSPI_MISCCR6_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_ADDRESS_SHIFT)) & FLEXSPI_MISCCR6_ADDRESS_MASK)
40695#define FLEXSPI_MISCCR7_VALID_MASK (0x1U)
40696#define FLEXSPI_MISCCR7_VALID_SHIFT (0U)
40699#define FLEXSPI_MISCCR7_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_VALID_SHIFT)) & FLEXSPI_MISCCR7_VALID_MASK)
40700
40701#define FLEXSPI_MISCCR7_HIT_MASK (0x2U)
40702#define FLEXSPI_MISCCR7_HIT_SHIFT (1U)
40705#define FLEXSPI_MISCCR7_HIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_HIT_SHIFT)) & FLEXSPI_MISCCR7_HIT_MASK)
40706
40707#define FLEXSPI_MISCCR7_ADDRESS_MASK (0xFFFFFFFCU)
40708#define FLEXSPI_MISCCR7_ADDRESS_SHIFT (2U)
40711#define FLEXSPI_MISCCR7_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_ADDRESS_SHIFT)) & FLEXSPI_MISCCR7_ADDRESS_MASK)
40717#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
40718#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
40722#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
40723
40724#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
40725#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
40731#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
40732
40733#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
40734#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
40742#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
40748#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)
40749#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
40753#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
40754
40755#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
40756#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
40766#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
40767
40768#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)
40769#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
40773#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
40774
40775#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
40776#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
40788#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
40794#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
40795#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
40798#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
40799
40800#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
40801#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
40804#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
40805
40806#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
40807#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
40810#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
40811
40812#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
40813#define FLEXSPI_STS2_AREFSEL_SHIFT (8U)
40816#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
40817
40818#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
40819#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
40822#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
40823
40824#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
40825#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
40828#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
40829
40830#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
40831#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
40834#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
40835
40836#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
40837#define FLEXSPI_STS2_BREFSEL_SHIFT (24U)
40840#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
40846#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
40847#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
40850#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
40851
40852#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
40853#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
40856#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
40857
40858#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
40859#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
40862#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
40868#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
40869#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
40872#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
40873
40874#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
40875#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
40878#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
40884#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
40885#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
40888#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
40889
40890#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
40891#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
40894#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
40900#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
40901#define FLEXSPI_RFDR_RXDATA_SHIFT (0U)
40904#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
40907/* The count of FLEXSPI_RFDR */
40908#define FLEXSPI_RFDR_COUNT (32U)
40909
40913#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
40914#define FLEXSPI_TFDR_TXDATA_SHIFT (0U)
40917#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
40920/* The count of FLEXSPI_TFDR */
40921#define FLEXSPI_TFDR_COUNT (32U)
40922
40926#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
40927#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
40930#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
40931
40932#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
40933#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
40936#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
40937
40938#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
40939#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
40942#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
40943
40944#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
40945#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
40948#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
40949
40950#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
40951#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
40954#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
40955
40956#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
40957#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
40960#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
40963/* The count of FLEXSPI_LUT */
40964#define FLEXSPI_LUT_COUNT (64U)
40965
40969#define FLEXSPI_HMSTRCR_MASK_MASK (0xFFFFU)
40970#define FLEXSPI_HMSTRCR_MASK_SHIFT (0U)
40975#define FLEXSPI_HMSTRCR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MASK_SHIFT)) & FLEXSPI_HMSTRCR_MASK_MASK)
40976
40977#define FLEXSPI_HMSTRCR_MSTRID_MASK (0xFFFF0000U)
40978#define FLEXSPI_HMSTRCR_MSTRID_SHIFT (16U)
40981#define FLEXSPI_HMSTRCR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MSTRID_SHIFT)) & FLEXSPI_HMSTRCR_MSTRID_MASK)
40984/* The count of FLEXSPI_HMSTRCR */
40985#define FLEXSPI_HMSTRCR_COUNT (8U)
40986
40990#define FLEXSPI_HADDRSTART_REMAPEN_MASK (0x1U)
40991#define FLEXSPI_HADDRSTART_REMAPEN_SHIFT (0U)
40996#define FLEXSPI_HADDRSTART_REMAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK)
40997
40998#define FLEXSPI_HADDRSTART_KBINECC_MASK (0x2U)
40999#define FLEXSPI_HADDRSTART_KBINECC_SHIFT (1U)
41004#define FLEXSPI_HADDRSTART_KBINECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_KBINECC_SHIFT)) & FLEXSPI_HADDRSTART_KBINECC_MASK)
41005
41006#define FLEXSPI_HADDRSTART_ADDRSTART_MASK (0xFFFFF000U)
41007#define FLEXSPI_HADDRSTART_ADDRSTART_SHIFT (12U)
41008#define FLEXSPI_HADDRSTART_ADDRSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK)
41014#define FLEXSPI_HADDREND_ENDSTART_MASK (0xFFFFF000U)
41015#define FLEXSPI_HADDREND_ENDSTART_SHIFT (12U)
41016#define FLEXSPI_HADDREND_ENDSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK)
41022#define FLEXSPI_HADDROFFSET_ADDROFFSET_MASK (0xFFFFF000U)
41023#define FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT (12U)
41024#define FLEXSPI_HADDROFFSET_ADDROFFSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK)
41030#define FLEXSPI_IPSNSZSTART0_start_address_MASK (0xFFFFF000U)
41031#define FLEXSPI_IPSNSZSTART0_start_address_SHIFT (12U)
41034#define FLEXSPI_IPSNSZSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK)
41040#define FLEXSPI_IPSNSZEND0_end_address_MASK (0xFFFFF000U)
41041#define FLEXSPI_IPSNSZEND0_end_address_SHIFT (12U)
41044#define FLEXSPI_IPSNSZEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK)
41050#define FLEXSPI_IPSNSZSTART1_start_address_MASK (0xFFFFF000U)
41051#define FLEXSPI_IPSNSZSTART1_start_address_SHIFT (12U)
41054#define FLEXSPI_IPSNSZSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK)
41060#define FLEXSPI_IPSNSZEND1_end_address_MASK (0xFFFFF000U)
41061#define FLEXSPI_IPSNSZEND1_end_address_SHIFT (12U)
41064#define FLEXSPI_IPSNSZEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK)
41070#define FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK (0xFFFFF000U)
41071#define FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT (12U)
41074#define FLEXSPI_AHBBUFREGIONSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK)
41080#define FLEXSPI_AHBBUFREGIONEND0_end_address_MASK (0xFFFFF000U)
41081#define FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT (12U)
41084#define FLEXSPI_AHBBUFREGIONEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_end_address_MASK)
41090#define FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK (0xFFFFF000U)
41091#define FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT (12U)
41094#define FLEXSPI_AHBBUFREGIONSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK)
41100#define FLEXSPI_AHBBUFREGIONEND1_end_address_MASK (0xFFFFF000U)
41101#define FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT (12U)
41104#define FLEXSPI_AHBBUFREGIONEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_end_address_MASK)
41110#define FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK (0xFFFFF000U)
41111#define FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT (12U)
41114#define FLEXSPI_AHBBUFREGIONSTART2_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK)
41120#define FLEXSPI_AHBBUFREGIONEND2_end_address_MASK (0xFFFFF000U)
41121#define FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT (12U)
41124#define FLEXSPI_AHBBUFREGIONEND2_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_end_address_MASK)
41130#define FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK (0xFFFFF000U)
41131#define FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT (12U)
41134#define FLEXSPI_AHBBUFREGIONSTART3_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK)
41140#define FLEXSPI_AHBBUFREGIONEND3_end_address_MASK (0xFFFFF000U)
41141#define FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT (12U)
41144#define FLEXSPI_AHBBUFREGIONEND3_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_end_address_MASK) /* end of group FLEXSPI_Register_Masks */
41151
41152
41153/* FLEXSPI - Peripheral instance base addresses */
41155#define FLEXSPI1_BASE (0x400CC000u)
41157#define FLEXSPI1 ((FLEXSPI_Type *)FLEXSPI1_BASE)
41159#define FLEXSPI2_BASE (0x400D0000u)
41161#define FLEXSPI2 ((FLEXSPI_Type *)FLEXSPI2_BASE)
41163#define FLEXSPI_BASE_ADDRS { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE }
41165#define FLEXSPI_BASE_PTRS { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 }
41167#define FLEXSPI_IRQS { NotAvail_IRQn, FLEXSPI1_IRQn, FLEXSPI2_IRQn }
41168/* FlexSPI1 AMBA address. */
41169#define FlexSPI1_AMBA_BASE (0x30000000U)
41170/* FlexSPI1 ASFM address. */
41171#define FlexSPI1_ASFM_BASE (0x30000000U)
41172/* Base Address of AHB address space mapped to IP RX FIFO. */
41173#define FlexSPI1_ARDF_BASE (0x2FC00000U)
41174/* Base Address of AHB address space mapped to IP TX FIFO. */
41175#define FlexSPI1_ATDF_BASE (0x2F800000U)
41176/* FlexSPI1 alias base address. */
41177#define FlexSPI1_ALIAS_BASE (0x8000000U)
41178/* FlexSPI2 AMBA address. */
41179#define FlexSPI2_AMBA_BASE (0x60000000U)
41180/* FlexSPI ASFM address. */
41181#define FlexSPI2_ASFM_BASE (0x60000000U)
41182/* Base Address of AHB address space mapped to IP RX FIFO. */
41183#define FlexSPI2_ARDF_BASE (0x7FC00000U)
41184/* Base Address of AHB address space mapped to IP TX FIFO. */
41185#define FlexSPI2_ATDF_BASE (0x7F800000U)
41186
41187 /* end of group FLEXSPI_Peripheral_Access_Layer */
41191
41192
41193/* ----------------------------------------------------------------------------
41194 -- GPC_CPU_MODE_CTRL Peripheral Access Layer
41195 ---------------------------------------------------------------------------- */
41196
41203typedef struct {
41204 uint8_t RESERVED_0[4];
41205 __IO uint32_t CM_AUTHEN_CTRL;
41206 __IO uint32_t CM_INT_CTRL;
41207 __IO uint32_t CM_MISC;
41208 __IO uint32_t CM_MODE_CTRL;
41209 __I uint32_t CM_MODE_STAT;
41210 uint8_t RESERVED_1[232];
41211 __IO uint32_t CM_IRQ_WAKEUP_MASK[8];
41212 uint8_t RESERVED_2[32];
41213 __IO uint32_t CM_NON_IRQ_WAKEUP_MASK;
41214 uint8_t RESERVED_3[12];
41215 __I uint32_t CM_IRQ_WAKEUP_STAT[8];
41216 uint8_t RESERVED_4[32];
41217 __I uint32_t CM_NON_IRQ_WAKEUP_STAT;
41218 uint8_t RESERVED_5[108];
41219 __IO uint32_t CM_SLEEP_SSAR_CTRL;
41220 uint8_t RESERVED_6[4];
41221 __IO uint32_t CM_SLEEP_LPCG_CTRL;
41222 uint8_t RESERVED_7[4];
41223 __IO uint32_t CM_SLEEP_PLL_CTRL;
41224 uint8_t RESERVED_8[4];
41225 __IO uint32_t CM_SLEEP_ISO_CTRL;
41226 uint8_t RESERVED_9[4];
41227 __IO uint32_t CM_SLEEP_RESET_CTRL;
41228 uint8_t RESERVED_10[4];
41229 __IO uint32_t CM_SLEEP_POWER_CTRL;
41230 uint8_t RESERVED_11[100];
41231 __IO uint32_t CM_WAKEUP_POWER_CTRL;
41232 uint8_t RESERVED_12[4];
41233 __IO uint32_t CM_WAKEUP_RESET_CTRL;
41234 uint8_t RESERVED_13[4];
41235 __IO uint32_t CM_WAKEUP_ISO_CTRL;
41236 uint8_t RESERVED_14[4];
41237 __IO uint32_t CM_WAKEUP_PLL_CTRL;
41238 uint8_t RESERVED_15[4];
41239 __IO uint32_t CM_WAKEUP_LPCG_CTRL;
41240 uint8_t RESERVED_16[4];
41241 __IO uint32_t CM_WAKEUP_SSAR_CTRL;
41242 uint8_t RESERVED_17[68];
41243 __IO uint32_t CM_SP_CTRL;
41244 __I uint32_t CM_SP_STAT;
41245 uint8_t RESERVED_18[8];
41246 __IO uint32_t CM_RUN_MODE_MAPPING;
41247 __IO uint32_t CM_WAIT_MODE_MAPPING;
41248 __IO uint32_t CM_STOP_MODE_MAPPING;
41249 __IO uint32_t CM_SUSPEND_MODE_MAPPING;
41250 __IO uint32_t CM_SP_MAPPING[16];
41251 uint8_t RESERVED_19[32];
41252 __IO uint32_t CM_STBY_CTRL;
41254
41255/* ----------------------------------------------------------------------------
41256 -- GPC_CPU_MODE_CTRL Register Masks
41257 ---------------------------------------------------------------------------- */
41258
41267#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK (0x1U)
41268#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT (0U)
41273#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK)
41274
41275#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
41276#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
41281#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK)
41282
41283#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
41284#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
41287#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK)
41288
41289#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
41290#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
41293#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK)
41294
41295#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
41296#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
41299#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK)
41300
41301#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
41302#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
41305#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK)
41311#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK (0x1U)
41312#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT (0U)
41317#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK)
41318
41319#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK (0x2U)
41320#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT (1U)
41325#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK)
41326
41327#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK (0x4U)
41328#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT (2U)
41333#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK)
41334
41335#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK (0x10000U)
41336#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT (16U)
41339#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK)
41340
41341#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK (0x20000U)
41342#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT (17U)
41345#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK)
41346
41347#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK (0x40000U)
41348#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT (18U)
41351#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK)
41357#define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK (0x1U)
41358#define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT (0U)
41363#define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK)
41364
41365#define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK (0x2U)
41366#define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT (1U)
41371#define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK)
41372
41373#define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK (0x4U)
41374#define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT (2U)
41377#define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK)
41378
41379#define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK (0x10U)
41380#define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT (4U)
41383#define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK)
41389#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK (0x3U)
41390#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT (0U)
41397#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK)
41398
41399#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK (0x10U)
41400#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT (4U)
41405#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK)
41411#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK (0x3U)
41412#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT (0U)
41419#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK)
41420
41421#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK (0xCU)
41422#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT (2U)
41429#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK)
41435#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK (0xFFFFFFFFU)
41436#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT (0U)
41439#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK)
41440
41441#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK (0xFFFFFFFFU)
41442#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT (0U)
41445#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK)
41446
41447#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK (0xFFFFFFFFU)
41448#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT (0U)
41451#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK)
41452
41453#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK (0xFFFFFFFFU)
41454#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT (0U)
41457#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK)
41458
41459#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK (0xFFFFFFFFU)
41460#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT (0U)
41463#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK)
41464
41465#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK (0xFFFFFFFFU)
41466#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT (0U)
41469#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK)
41470
41471#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK (0xFFFFFFFFU)
41472#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT (0U)
41475#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK)
41476
41477#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU)
41478#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT (0U)
41481#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK)
41484/* The count of GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK */
41485#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_COUNT (8U)
41486
41490#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK (0x1U)
41491#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT (0U)
41495#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK)
41496
41497#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK (0x2U)
41498#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT (1U)
41501#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK)
41507#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU)
41508#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT (0U)
41513#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK)
41514
41515#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK (0xFFFFFFFFU)
41516#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT (0U)
41521#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK)
41522
41523#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK (0xFFFFFFFFU)
41524#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT (0U)
41529#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK)
41530
41531#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK (0xFFFFFFFFU)
41532#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT (0U)
41537#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK)
41538
41539#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK (0xFFFFFFFFU)
41540#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT (0U)
41545#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK)
41546
41547#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK (0xFFFFFFFFU)
41548#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT (0U)
41553#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK)
41554
41555#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK (0xFFFFFFFFU)
41556#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT (0U)
41561#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK)
41562
41563#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK (0xFFFFFFFFU)
41564#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT (0U)
41569#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK)
41572/* The count of GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT */
41573#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_COUNT (8U)
41574
41578#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK (0x1U)
41579#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT (0U)
41583#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK)
41584
41585#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK (0x2U)
41586#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT (1U)
41589#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK)
41595#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU)
41596#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT (0U)
41599#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK)
41600
41601#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U)
41602#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT (28U)
41609#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK)
41610
41611#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK (0x80000000U)
41612#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT (31U)
41615#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK)
41621#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU)
41622#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT (0U)
41625#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK)
41626
41627#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U)
41628#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT (28U)
41635#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK)
41636
41637#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK (0x80000000U)
41638#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT (31U)
41641#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK)
41647#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU)
41648#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT (0U)
41651#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK)
41652
41653#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK (0x30000000U)
41654#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT (28U)
41661#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK)
41662
41663#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK (0x80000000U)
41664#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT (31U)
41667#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK)
41673#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU)
41674#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT (0U)
41677#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK)
41678
41679#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK (0x30000000U)
41680#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT (28U)
41687#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK)
41688
41689#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK (0x80000000U)
41690#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT (31U)
41693#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK)
41699#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU)
41700#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT (0U)
41703#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK)
41704
41705#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK (0x30000000U)
41706#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT (28U)
41713#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK)
41714
41715#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK (0x80000000U)
41716#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT (31U)
41719#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK)
41725#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU)
41726#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT (0U)
41729#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK)
41730
41731#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK (0x30000000U)
41732#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT (28U)
41739#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK)
41740
41741#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK (0x80000000U)
41742#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT (31U)
41745#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK)
41751#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU)
41752#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT (0U)
41755#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK)
41756
41757#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK (0x30000000U)
41758#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT (28U)
41765#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK)
41766
41767#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK (0x80000000U)
41768#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT (31U)
41771#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK)
41777#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU)
41778#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT (0U)
41781#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK)
41782
41783#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK (0x30000000U)
41784#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT (28U)
41791#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK)
41792
41793#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK (0x80000000U)
41794#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT (31U)
41797#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK)
41803#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU)
41804#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT (0U)
41807#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK)
41808
41809#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK (0x30000000U)
41810#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT (28U)
41817#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK)
41818
41819#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK (0x80000000U)
41820#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT (31U)
41823#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK)
41829#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU)
41830#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT (0U)
41833#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK)
41834
41835#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK (0x30000000U)
41836#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT (28U)
41843#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK)
41844
41845#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK (0x80000000U)
41846#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT (31U)
41849#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK)
41855#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU)
41856#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT (0U)
41859#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK)
41860
41861#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U)
41862#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT (28U)
41869#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK)
41870
41871#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK (0x80000000U)
41872#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT (31U)
41875#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK)
41881#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU)
41882#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT (0U)
41885#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK)
41886
41887#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U)
41888#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT (28U)
41895#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK)
41896
41897#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK (0x80000000U)
41898#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT (31U)
41901#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK)
41907#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK (0x1U)
41908#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT (0U)
41911#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK)
41912
41913#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK (0x1EU)
41914#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT (1U)
41917#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK)
41918
41919#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK (0x20U)
41920#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT (5U)
41923#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK)
41924
41925#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK (0x3C0U)
41926#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT (6U)
41929#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK)
41930
41931#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK (0x400U)
41932#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT (10U)
41935#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK)
41936
41937#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK (0x7800U)
41938#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT (11U)
41941#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK)
41942
41943#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK (0x8000U)
41944#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT (15U)
41949#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK)
41955#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK (0xFU)
41956#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT (0U)
41959#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK)
41960
41961#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK (0xF0U)
41962#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT (4U)
41965#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK)
41966
41967#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK (0xF00U)
41968#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT (8U)
41971#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK)
41977#define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK (0xFFFFU)
41978#define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT (0U)
41981#define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK)
41987#define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK (0xFFFFU)
41988#define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT (0U)
41991#define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK)
41997#define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK (0xFFFFU)
41998#define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT (0U)
42001#define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK)
42007#define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK (0xFFFFU)
42008#define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT (0U)
42011#define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK)
42017#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK (0xFFFFU)
42018#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT (0U)
42021#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK)
42022
42023#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK (0xFFFFU)
42024#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT (0U)
42027#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK)
42028
42029#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK (0xFFFFU)
42030#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT (0U)
42033#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK)
42034
42035#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK (0xFFFFU)
42036#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT (0U)
42039#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK)
42040
42041#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK (0xFFFFU)
42042#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT (0U)
42045#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK)
42046
42047#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK (0xFFFFU)
42048#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT (0U)
42051#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK)
42052
42053#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK (0xFFFFU)
42054#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT (0U)
42057#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK)
42058
42059#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK (0xFFFFU)
42060#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT (0U)
42063#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK)
42064
42065#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK (0xFFFFU)
42066#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT (0U)
42069#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK)
42070
42071#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK (0xFFFFU)
42072#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT (0U)
42075#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK)
42076
42077#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK (0xFFFFU)
42078#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT (0U)
42081#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK)
42082
42083#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK (0xFFFFU)
42084#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT (0U)
42087#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK)
42088
42089#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK (0xFFFFU)
42090#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT (0U)
42093#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK)
42094
42095#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK (0xFFFFU)
42096#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT (0U)
42099#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK)
42100
42101#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK (0xFFFFU)
42102#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT (0U)
42105#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK)
42106
42107#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK (0xFFFFU)
42108#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT (0U)
42111#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK)
42114/* The count of GPC_CPU_MODE_CTRL_CM_SP_MAPPING */
42115#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_COUNT (16U)
42116
42120#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK (0x1U)
42121#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT (0U)
42124#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK)
42125
42126#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK (0x2U)
42127#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT (1U)
42130#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK)
42131
42132#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK (0x4U)
42133#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT (2U)
42136#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK)
42137
42138#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK (0x10000U)
42139#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT (16U)
42142#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK)
42143
42144#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK (0x20000U)
42145#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT (17U)
42148#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK) /* end of group GPC_CPU_MODE_CTRL_Register_Masks */
42155
42156
42157/* GPC_CPU_MODE_CTRL - Peripheral instance base addresses */
42159#define GPC_CPU_MODE_CTRL_0_BASE (0x40C00000u)
42161#define GPC_CPU_MODE_CTRL_0 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_0_BASE)
42163#define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u)
42165#define GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
42167#define GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
42169#define GPC_CPU_MODE_CTRL_BASE_PTRS { GPC_CPU_MODE_CTRL_0, GPC_CPU_MODE_CTRL_1 }
42170 /* end of group GPC_CPU_MODE_CTRL_Peripheral_Access_Layer */
42174
42175
42176/* ----------------------------------------------------------------------------
42177 -- GPC_SET_POINT_CTRL Peripheral Access Layer
42178 ---------------------------------------------------------------------------- */
42179
42186typedef struct {
42187 uint8_t RESERVED_0[4];
42188 __IO uint32_t SP_AUTHEN_CTRL;
42189 __IO uint32_t SP_INT_CTRL;
42190 uint8_t RESERVED_1[4];
42191 __I uint32_t SP_CPU_REQ;
42192 __I uint32_t SP_SYS_STAT;
42193 uint8_t RESERVED_2[4];
42194 __IO uint32_t SP_ROSC_CTRL;
42195 uint8_t RESERVED_3[32];
42196 __IO uint32_t SP_PRIORITY_0_7;
42197 __IO uint32_t SP_PRIORITY_8_15;
42198 uint8_t RESERVED_4[184];
42199 __IO uint32_t SP_SSAR_SAVE_CTRL;
42200 uint8_t RESERVED_5[12];
42201 __IO uint32_t SP_LPCG_OFF_CTRL;
42202 uint8_t RESERVED_6[12];
42203 __IO uint32_t SP_GROUP_DOWN_CTRL;
42204 uint8_t RESERVED_7[12];
42205 __IO uint32_t SP_ROOT_DOWN_CTRL;
42206 uint8_t RESERVED_8[12];
42207 __IO uint32_t SP_PLL_OFF_CTRL;
42208 uint8_t RESERVED_9[12];
42209 __IO uint32_t SP_ISO_ON_CTRL;
42210 uint8_t RESERVED_10[12];
42211 __IO uint32_t SP_RESET_EARLY_CTRL;
42212 uint8_t RESERVED_11[12];
42213 __IO uint32_t SP_POWER_OFF_CTRL;
42214 uint8_t RESERVED_12[12];
42215 __IO uint32_t SP_BIAS_OFF_CTRL;
42216 uint8_t RESERVED_13[12];
42217 __IO uint32_t SP_BG_PLDO_OFF_CTRL;
42218 uint8_t RESERVED_14[12];
42219 __IO uint32_t SP_LDO_PRE_CTRL;
42220 uint8_t RESERVED_15[12];
42221 __IO uint32_t SP_DCDC_DOWN_CTRL;
42222 uint8_t RESERVED_16[76];
42223 __IO uint32_t SP_DCDC_UP_CTRL;
42224 uint8_t RESERVED_17[12];
42225 __IO uint32_t SP_LDO_POST_CTRL;
42226 uint8_t RESERVED_18[12];
42227 __IO uint32_t SP_BG_PLDO_ON_CTRL;
42228 uint8_t RESERVED_19[12];
42229 __IO uint32_t SP_BIAS_ON_CTRL;
42230 uint8_t RESERVED_20[12];
42231 __IO uint32_t SP_POWER_ON_CTRL;
42232 uint8_t RESERVED_21[12];
42233 __IO uint32_t SP_RESET_LATE_CTRL;
42234 uint8_t RESERVED_22[12];
42235 __IO uint32_t SP_ISO_OFF_CTRL;
42236 uint8_t RESERVED_23[12];
42237 __IO uint32_t SP_PLL_ON_CTRL;
42238 uint8_t RESERVED_24[12];
42239 __IO uint32_t SP_ROOT_UP_CTRL;
42240 uint8_t RESERVED_25[12];
42241 __IO uint32_t SP_GROUP_UP_CTRL;
42242 uint8_t RESERVED_26[12];
42243 __IO uint32_t SP_LPCG_ON_CTRL;
42244 uint8_t RESERVED_27[12];
42245 __IO uint32_t SP_SSAR_RESTORE_CTRL;
42247
42248/* ----------------------------------------------------------------------------
42249 -- GPC_SET_POINT_CTRL Register Masks
42250 ---------------------------------------------------------------------------- */
42251
42260#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK (0x1U)
42261#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT (0U)
42266#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK)
42267
42268#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
42269#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
42274#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK)
42275
42276#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
42277#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
42280#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK)
42281
42282#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
42283#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
42286#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK)
42287
42288#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
42289#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
42292#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK)
42293
42294#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
42295#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
42298#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK)
42304#define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK (0x1U)
42305#define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT (0U)
42308#define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK)
42309
42310#define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK (0x2U)
42311#define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT (1U)
42314#define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK)
42320#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK (0xFU)
42321#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT (0U)
42324#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK)
42325
42326#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK (0xF0U)
42327#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT (4U)
42330#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK)
42331
42332#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK (0xF00U)
42333#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT (8U)
42336#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK)
42337
42338#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK (0xF000U)
42339#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT (12U)
42342#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK)
42343
42344#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK (0xF0000U)
42345#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT (16U)
42348#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK)
42349
42350#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK (0xF00000U)
42351#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT (20U)
42354#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK)
42355
42356#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK (0xF000000U)
42357#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT (24U)
42360#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK)
42361
42362#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK (0xF0000000U)
42363#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT (28U)
42366#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK)
42372#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK (0xFFFFU)
42373#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT (0U)
42376#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK)
42377
42378#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK (0xF0000U)
42379#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT (16U)
42382#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK)
42383
42384#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK (0xF00000U)
42385#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT (20U)
42388#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK)
42389
42390#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK (0xF000000U)
42391#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT (24U)
42394#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK)
42400#define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK (0xFFFFU)
42401#define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT (0U)
42404#define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK)
42410#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK (0xFU)
42411#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT (0U)
42414#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK)
42415
42416#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK (0xF0U)
42417#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT (4U)
42420#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK)
42421
42422#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK (0xF00U)
42423#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT (8U)
42426#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK)
42427
42428#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK (0xF000U)
42429#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT (12U)
42432#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK)
42433
42434#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK (0xF0000U)
42435#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT (16U)
42438#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK)
42439
42440#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK (0xF00000U)
42441#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT (20U)
42444#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK)
42445
42446#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK (0xF000000U)
42447#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT (24U)
42450#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK)
42451
42452#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK (0xF0000000U)
42453#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT (28U)
42456#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK)
42462#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK (0xFU)
42463#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT (0U)
42466#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK)
42467
42468#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK (0xF0U)
42469#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT (4U)
42472#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK)
42473
42474#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK (0xF00U)
42475#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT (8U)
42478#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK)
42479
42480#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK (0xF000U)
42481#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT (12U)
42484#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK)
42485
42486#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK (0xF0000U)
42487#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT (16U)
42490#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK)
42491
42492#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK (0xF00000U)
42493#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT (20U)
42496#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK)
42497
42498#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK (0xF000000U)
42499#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT (24U)
42502#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK)
42503
42504#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK (0xF0000000U)
42505#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT (28U)
42508#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK)
42514#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK (0xFFFFU)
42515#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT (0U)
42518#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK)
42519
42520#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK (0x30000000U)
42521#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT (28U)
42528#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK)
42529
42530#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK (0x80000000U)
42531#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT (31U)
42534#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK)
42540#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
42541#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT (0U)
42544#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK)
42545
42546#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
42547#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT (28U)
42554#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK)
42555
42556#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK (0x80000000U)
42557#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT (31U)
42560#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK)
42566#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
42567#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT (0U)
42570#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK)
42571
42572#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
42573#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT (28U)
42580#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK)
42581
42582#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK (0x80000000U)
42583#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT (31U)
42586#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK)
42592#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
42593#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT (0U)
42596#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK)
42597
42598#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
42599#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT (28U)
42606#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK)
42607
42608#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK (0x80000000U)
42609#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT (31U)
42612#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK)
42618#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
42619#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT (0U)
42622#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK)
42623
42624#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
42625#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT (28U)
42632#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK)
42633
42634#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK (0x80000000U)
42635#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT (31U)
42638#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK)
42644#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
42645#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT (0U)
42648#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK)
42649
42650#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK (0x30000000U)
42651#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT (28U)
42658#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK)
42659
42660#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK (0x80000000U)
42661#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT (31U)
42664#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK)
42670#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK (0xFFFFU)
42671#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT (0U)
42674#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK)
42675
42676#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK (0x30000000U)
42677#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT (28U)
42684#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK)
42685
42686#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK (0x80000000U)
42687#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT (31U)
42690#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK)
42696#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
42697#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT (0U)
42700#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK)
42701
42702#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
42703#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT (28U)
42710#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK)
42711
42712#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK (0x80000000U)
42713#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT (31U)
42716#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK)
42722#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
42723#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT (0U)
42726#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK)
42727
42728#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
42729#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT (28U)
42736#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK)
42737
42738#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK (0x80000000U)
42739#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT (31U)
42742#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK)
42748#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
42749#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT (0U)
42752#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK)
42753
42754#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
42755#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT (28U)
42762#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK)
42763
42764#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK (0x80000000U)
42765#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT (31U)
42768#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK)
42774#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK (0xFFFFU)
42775#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT (0U)
42778#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK)
42779
42780#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK (0x30000000U)
42781#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT (28U)
42788#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK)
42789
42790#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK (0x80000000U)
42791#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT (31U)
42794#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK)
42800#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
42801#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT (0U)
42804#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK)
42805
42806#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
42807#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT (28U)
42814#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK)
42815
42816#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK (0x80000000U)
42817#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT (31U)
42820#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK)
42826#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
42827#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT (0U)
42830#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK)
42831
42832#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK (0x30000000U)
42833#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT (28U)
42840#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK)
42841
42842#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK (0x80000000U)
42843#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT (31U)
42846#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK)
42852#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK (0xFFFFU)
42853#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT (0U)
42856#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK)
42857
42858#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK (0x30000000U)
42859#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT (28U)
42866#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK)
42867
42868#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK (0x80000000U)
42869#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT (31U)
42872#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK)
42878#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
42879#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT (0U)
42882#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK)
42883
42884#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK (0x30000000U)
42885#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT (28U)
42892#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK)
42893
42894#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK (0x80000000U)
42895#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT (31U)
42898#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK)
42904#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
42905#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT (0U)
42908#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK)
42909
42910#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK (0x30000000U)
42911#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT (28U)
42918#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK)
42919
42920#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK (0x80000000U)
42921#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT (31U)
42924#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK)
42930#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
42931#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT (0U)
42934#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK)
42935
42936#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK (0x30000000U)
42937#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT (28U)
42944#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK)
42945
42946#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK (0x80000000U)
42947#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT (31U)
42950#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK)
42956#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK (0xFFFFU)
42957#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT (0U)
42960#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK)
42961
42962#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK (0x30000000U)
42963#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT (28U)
42970#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK)
42971
42972#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK (0x80000000U)
42973#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT (31U)
42976#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK)
42982#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
42983#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT (0U)
42986#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK)
42987
42988#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
42989#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT (28U)
42996#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK)
42997
42998#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK (0x80000000U)
42999#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT (31U)
43002#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK)
43008#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
43009#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT (0U)
43012#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK)
43013
43014#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK (0x30000000U)
43015#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT (28U)
43022#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK)
43023
43024#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK (0x80000000U)
43025#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT (31U)
43028#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK)
43034#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
43035#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT (0U)
43038#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK)
43039
43040#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK (0x30000000U)
43041#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT (28U)
43048#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK)
43049
43050#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK (0x80000000U)
43051#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT (31U)
43054#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK)
43060#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
43061#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT (0U)
43064#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK)
43065
43066#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK (0x30000000U)
43067#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT (28U)
43074#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK)
43075
43076#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK (0x80000000U)
43077#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT (31U)
43080#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK)
43086#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
43087#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT (0U)
43090#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK)
43091
43092#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK (0x30000000U)
43093#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT (28U)
43100#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK)
43101
43102#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK (0x80000000U)
43103#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT (31U)
43106#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK)
43112#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK (0xFFFFU)
43113#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT (0U)
43116#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK)
43117
43118#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK (0x30000000U)
43119#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT (28U)
43126#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK)
43127
43128#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK (0x80000000U)
43129#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT (31U)
43132#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK) /* end of group GPC_SET_POINT_CTRL_Register_Masks */
43139
43140
43141/* GPC_SET_POINT_CTRL - Peripheral instance base addresses */
43143#define GPC_SET_POINT_CTRL_BASE (0x40C02000u)
43145#define GPC_SET_POINT_CTRL ((GPC_SET_POINT_CTRL_Type *)GPC_SET_POINT_CTRL_BASE)
43147#define GPC_SET_POINT_CTRL_BASE_ADDRS { GPC_SET_POINT_CTRL_BASE }
43149#define GPC_SET_POINT_CTRL_BASE_PTRS { GPC_SET_POINT_CTRL }
43150 /* end of group GPC_SET_POINT_CTRL_Peripheral_Access_Layer */
43154
43155
43156/* ----------------------------------------------------------------------------
43157 -- GPC_STBY_CTRL Peripheral Access Layer
43158 ---------------------------------------------------------------------------- */
43159
43166typedef struct {
43167 uint8_t RESERVED_0[4];
43168 __IO uint32_t STBY_AUTHEN_CTRL;
43169 uint8_t RESERVED_1[4];
43170 __IO uint32_t STBY_MISC;
43171 uint8_t RESERVED_2[224];
43172 __IO uint32_t STBY_LPCG_IN_CTRL;
43173 uint8_t RESERVED_3[12];
43174 __IO uint32_t STBY_PLL_IN_CTRL;
43175 uint8_t RESERVED_4[12];
43176 __IO uint32_t STBY_BIAS_IN_CTRL;
43177 uint8_t RESERVED_5[12];
43178 __IO uint32_t STBY_PLDO_IN_CTRL;
43179 uint8_t RESERVED_6[4];
43180 __IO uint32_t STBY_BANDGAP_IN_CTRL;
43181 uint8_t RESERVED_7[4];
43182 __IO uint32_t STBY_LDO_IN_CTRL;
43183 uint8_t RESERVED_8[12];
43184 __IO uint32_t STBY_DCDC_IN_CTRL;
43185 uint8_t RESERVED_9[12];
43186 __IO uint32_t STBY_PMIC_IN_CTRL;
43187 uint8_t RESERVED_10[172];
43188 __IO uint32_t STBY_PMIC_OUT_CTRL;
43189 uint8_t RESERVED_11[12];
43190 __IO uint32_t STBY_DCDC_OUT_CTRL;
43191 uint8_t RESERVED_12[12];
43192 __IO uint32_t STBY_LDO_OUT_CTRL;
43193 uint8_t RESERVED_13[12];
43194 __IO uint32_t STBY_BANDGAP_OUT_CTRL;
43195 uint8_t RESERVED_14[4];
43196 __IO uint32_t STBY_PLDO_OUT_CTRL;
43197 uint8_t RESERVED_15[4];
43198 __IO uint32_t STBY_BIAS_OUT_CTRL;
43199 uint8_t RESERVED_16[12];
43200 __IO uint32_t STBY_PLL_OUT_CTRL;
43201 uint8_t RESERVED_17[12];
43202 __IO uint32_t STBY_LPCG_OUT_CTRL;
43204
43205/* ----------------------------------------------------------------------------
43206 -- GPC_STBY_CTRL Register Masks
43207 ---------------------------------------------------------------------------- */
43208
43217#define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
43218#define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
43221#define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK)
43227#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK (0x1U)
43228#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT (0U)
43231#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK)
43232
43233#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK (0x2U)
43234#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT (1U)
43237#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK)
43238
43239#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK (0x4U)
43240#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT (2U)
43243#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK)
43244
43245#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK (0x8U)
43246#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT (3U)
43249#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK)
43255#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
43256#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT (0U)
43259#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK)
43260
43261#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK (0x30000000U)
43262#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT (28U)
43269#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK)
43270
43271#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK (0x80000000U)
43272#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT (31U)
43275#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK)
43281#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
43282#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT (0U)
43285#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK)
43286
43287#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK (0x30000000U)
43288#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT (28U)
43295#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK)
43296
43297#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK (0x80000000U)
43298#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT (31U)
43301#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK)
43307#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
43308#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT (0U)
43311#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK)
43312
43313#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK (0x30000000U)
43314#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT (28U)
43321#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK)
43322
43323#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK (0x80000000U)
43324#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT (31U)
43327#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK)
43333#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
43334#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT (0U)
43337#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK)
43338
43339#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK (0x30000000U)
43340#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT (28U)
43347#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK)
43348
43349#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK (0x80000000U)
43350#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT (31U)
43353#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK)
43359#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
43360#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT (0U)
43363#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK)
43364
43365#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK (0x30000000U)
43366#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT (28U)
43373#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK)
43374
43375#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK (0x80000000U)
43376#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT (31U)
43379#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK)
43385#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
43386#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT (0U)
43389#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK)
43390
43391#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK (0x30000000U)
43392#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT (28U)
43399#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK)
43400
43401#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK (0x80000000U)
43402#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT (31U)
43405#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK)
43411#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
43412#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT (0U)
43415#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK)
43416
43417#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK (0x30000000U)
43418#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT (28U)
43425#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK)
43426
43427#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK (0x80000000U)
43428#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT (31U)
43431#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK)
43437#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
43438#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT (0U)
43441#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK)
43442
43443#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK (0x30000000U)
43444#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT (28U)
43451#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK)
43452
43453#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK (0x80000000U)
43454#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT (31U)
43457#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK)
43463#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
43464#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT (0U)
43467#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK)
43468
43469#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
43470#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT (28U)
43477#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK)
43478
43479#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK (0x80000000U)
43480#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT (31U)
43483#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK)
43489#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
43490#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT (0U)
43493#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK)
43494
43495#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
43496#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT (28U)
43503#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK)
43504
43505#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK (0x80000000U)
43506#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT (31U)
43509#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK)
43515#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
43516#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT (0U)
43519#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK)
43520
43521#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
43522#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT (28U)
43529#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK)
43530
43531#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK (0x80000000U)
43532#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT (31U)
43535#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK)
43541#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
43542#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT (0U)
43545#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK)
43546
43547#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
43548#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT (28U)
43555#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK)
43556
43557#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK (0x80000000U)
43558#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT (31U)
43561#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK)
43567#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
43568#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT (0U)
43571#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK)
43572
43573#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
43574#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT (28U)
43581#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK)
43582
43583#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK (0x80000000U)
43584#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT (31U)
43587#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK)
43593#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
43594#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT (0U)
43597#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK)
43598
43599#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
43600#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT (28U)
43607#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK)
43608
43609#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK (0x80000000U)
43610#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT (31U)
43613#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK)
43619#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
43620#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT (0U)
43623#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK)
43624
43625#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
43626#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT (28U)
43633#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK)
43634
43635#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK (0x80000000U)
43636#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT (31U)
43639#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK)
43645#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
43646#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT (0U)
43649#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK)
43650
43651#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
43652#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT (28U)
43659#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK)
43660
43661#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK (0x80000000U)
43662#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT (31U)
43665#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK) /* end of group GPC_STBY_CTRL_Register_Masks */
43672
43673
43674/* GPC_STBY_CTRL - Peripheral instance base addresses */
43676#define GPC_STBY_CTRL_BASE (0x40C02800u)
43678#define GPC_STBY_CTRL ((GPC_STBY_CTRL_Type *)GPC_STBY_CTRL_BASE)
43680#define GPC_STBY_CTRL_BASE_ADDRS { GPC_STBY_CTRL_BASE }
43682#define GPC_STBY_CTRL_BASE_PTRS { GPC_STBY_CTRL }
43683 /* end of group GPC_STBY_CTRL_Peripheral_Access_Layer */
43687
43688
43689/* ----------------------------------------------------------------------------
43690 -- GPIO Peripheral Access Layer
43691 ---------------------------------------------------------------------------- */
43692
43699typedef struct {
43700 __IO uint32_t DR;
43701 __IO uint32_t GDIR;
43702 __I uint32_t PSR;
43703 __IO uint32_t ICR1;
43704 __IO uint32_t ICR2;
43705 __IO uint32_t IMR;
43706 __IO uint32_t ISR;
43707 __IO uint32_t EDGE_SEL;
43708 uint8_t RESERVED_0[100];
43709 __O uint32_t DR_SET;
43710 __O uint32_t DR_CLEAR;
43711 __O uint32_t DR_TOGGLE;
43712} GPIO_Type;
43713
43714/* ----------------------------------------------------------------------------
43715 -- GPIO Register Masks
43716 ---------------------------------------------------------------------------- */
43717
43726#define GPIO_DR_DR_MASK (0xFFFFFFFFU)
43727#define GPIO_DR_DR_SHIFT (0U)
43730#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
43736#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
43737#define GPIO_GDIR_GDIR_SHIFT (0U)
43740#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
43746#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
43747#define GPIO_PSR_PSR_SHIFT (0U)
43750#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
43756#define GPIO_ICR1_ICR0_MASK (0x3U)
43757#define GPIO_ICR1_ICR0_SHIFT (0U)
43764#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
43765
43766#define GPIO_ICR1_ICR1_MASK (0xCU)
43767#define GPIO_ICR1_ICR1_SHIFT (2U)
43774#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
43775
43776#define GPIO_ICR1_ICR2_MASK (0x30U)
43777#define GPIO_ICR1_ICR2_SHIFT (4U)
43784#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
43785
43786#define GPIO_ICR1_ICR3_MASK (0xC0U)
43787#define GPIO_ICR1_ICR3_SHIFT (6U)
43794#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
43795
43796#define GPIO_ICR1_ICR4_MASK (0x300U)
43797#define GPIO_ICR1_ICR4_SHIFT (8U)
43804#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
43805
43806#define GPIO_ICR1_ICR5_MASK (0xC00U)
43807#define GPIO_ICR1_ICR5_SHIFT (10U)
43814#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
43815
43816#define GPIO_ICR1_ICR6_MASK (0x3000U)
43817#define GPIO_ICR1_ICR6_SHIFT (12U)
43824#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
43825
43826#define GPIO_ICR1_ICR7_MASK (0xC000U)
43827#define GPIO_ICR1_ICR7_SHIFT (14U)
43834#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
43835
43836#define GPIO_ICR1_ICR8_MASK (0x30000U)
43837#define GPIO_ICR1_ICR8_SHIFT (16U)
43844#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
43845
43846#define GPIO_ICR1_ICR9_MASK (0xC0000U)
43847#define GPIO_ICR1_ICR9_SHIFT (18U)
43854#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
43855
43856#define GPIO_ICR1_ICR10_MASK (0x300000U)
43857#define GPIO_ICR1_ICR10_SHIFT (20U)
43864#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
43865
43866#define GPIO_ICR1_ICR11_MASK (0xC00000U)
43867#define GPIO_ICR1_ICR11_SHIFT (22U)
43874#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
43875
43876#define GPIO_ICR1_ICR12_MASK (0x3000000U)
43877#define GPIO_ICR1_ICR12_SHIFT (24U)
43884#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
43885
43886#define GPIO_ICR1_ICR13_MASK (0xC000000U)
43887#define GPIO_ICR1_ICR13_SHIFT (26U)
43894#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
43895
43896#define GPIO_ICR1_ICR14_MASK (0x30000000U)
43897#define GPIO_ICR1_ICR14_SHIFT (28U)
43904#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
43905
43906#define GPIO_ICR1_ICR15_MASK (0xC0000000U)
43907#define GPIO_ICR1_ICR15_SHIFT (30U)
43914#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
43920#define GPIO_ICR2_ICR16_MASK (0x3U)
43921#define GPIO_ICR2_ICR16_SHIFT (0U)
43928#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
43929
43930#define GPIO_ICR2_ICR17_MASK (0xCU)
43931#define GPIO_ICR2_ICR17_SHIFT (2U)
43938#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
43939
43940#define GPIO_ICR2_ICR18_MASK (0x30U)
43941#define GPIO_ICR2_ICR18_SHIFT (4U)
43948#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
43949
43950#define GPIO_ICR2_ICR19_MASK (0xC0U)
43951#define GPIO_ICR2_ICR19_SHIFT (6U)
43958#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
43959
43960#define GPIO_ICR2_ICR20_MASK (0x300U)
43961#define GPIO_ICR2_ICR20_SHIFT (8U)
43968#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
43969
43970#define GPIO_ICR2_ICR21_MASK (0xC00U)
43971#define GPIO_ICR2_ICR21_SHIFT (10U)
43978#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
43979
43980#define GPIO_ICR2_ICR22_MASK (0x3000U)
43981#define GPIO_ICR2_ICR22_SHIFT (12U)
43988#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
43989
43990#define GPIO_ICR2_ICR23_MASK (0xC000U)
43991#define GPIO_ICR2_ICR23_SHIFT (14U)
43998#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
43999
44000#define GPIO_ICR2_ICR24_MASK (0x30000U)
44001#define GPIO_ICR2_ICR24_SHIFT (16U)
44008#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
44009
44010#define GPIO_ICR2_ICR25_MASK (0xC0000U)
44011#define GPIO_ICR2_ICR25_SHIFT (18U)
44018#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
44019
44020#define GPIO_ICR2_ICR26_MASK (0x300000U)
44021#define GPIO_ICR2_ICR26_SHIFT (20U)
44028#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
44029
44030#define GPIO_ICR2_ICR27_MASK (0xC00000U)
44031#define GPIO_ICR2_ICR27_SHIFT (22U)
44038#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
44039
44040#define GPIO_ICR2_ICR28_MASK (0x3000000U)
44041#define GPIO_ICR2_ICR28_SHIFT (24U)
44048#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
44049
44050#define GPIO_ICR2_ICR29_MASK (0xC000000U)
44051#define GPIO_ICR2_ICR29_SHIFT (26U)
44058#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
44059
44060#define GPIO_ICR2_ICR30_MASK (0x30000000U)
44061#define GPIO_ICR2_ICR30_SHIFT (28U)
44068#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
44069
44070#define GPIO_ICR2_ICR31_MASK (0xC0000000U)
44071#define GPIO_ICR2_ICR31_SHIFT (30U)
44078#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
44084#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
44085#define GPIO_IMR_IMR_SHIFT (0U)
44088#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
44094#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
44095#define GPIO_ISR_ISR_SHIFT (0U)
44098#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
44104#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
44105#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
44108#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
44114#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)
44115#define GPIO_DR_SET_DR_SET_SHIFT (0U)
44118#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
44124#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)
44125#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)
44128#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
44134#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)
44135#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)
44138#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) /* end of group GPIO_Register_Masks */
44145
44146
44147/* GPIO - Peripheral instance base addresses */
44149#define GPIO1_BASE (0x4012C000u)
44151#define GPIO1 ((GPIO_Type *)GPIO1_BASE)
44153#define GPIO2_BASE (0x40130000u)
44155#define GPIO2 ((GPIO_Type *)GPIO2_BASE)
44157#define GPIO3_BASE (0x40134000u)
44159#define GPIO3 ((GPIO_Type *)GPIO3_BASE)
44161#define GPIO4_BASE (0x40138000u)
44163#define GPIO4 ((GPIO_Type *)GPIO4_BASE)
44165#define GPIO5_BASE (0x4013C000u)
44167#define GPIO5 ((GPIO_Type *)GPIO5_BASE)
44169#define GPIO6_BASE (0x40140000u)
44171#define GPIO6 ((GPIO_Type *)GPIO6_BASE)
44173#define GPIO7_BASE (0x40C5C000u)
44175#define GPIO7 ((GPIO_Type *)GPIO7_BASE)
44177#define GPIO8_BASE (0x40C60000u)
44179#define GPIO8 ((GPIO_Type *)GPIO8_BASE)
44181#define GPIO9_BASE (0x40C64000u)
44183#define GPIO9 ((GPIO_Type *)GPIO9_BASE)
44185#define GPIO10_BASE (0x40C68000u)
44187#define GPIO10 ((GPIO_Type *)GPIO10_BASE)
44189#define GPIO11_BASE (0x40C6C000u)
44191#define GPIO11 ((GPIO_Type *)GPIO11_BASE)
44193#define GPIO12_BASE (0x40C70000u)
44195#define GPIO12 ((GPIO_Type *)GPIO12_BASE)
44197#define GPIO13_BASE (0x40CA0000u)
44199#define GPIO13 ((GPIO_Type *)GPIO13_BASE)
44201#define CM7_GPIO2_BASE (0x42008000u)
44203#define CM7_GPIO2 ((GPIO_Type *)CM7_GPIO2_BASE)
44205#define CM7_GPIO3_BASE (0x4200C000u)
44207#define CM7_GPIO3 ((GPIO_Type *)CM7_GPIO3_BASE)
44209#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE, GPIO10_BASE, GPIO11_BASE, GPIO12_BASE, GPIO13_BASE, CM7_GPIO2_BASE, CM7_GPIO3_BASE }
44211#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, CM7_GPIO2, CM7_GPIO3 }
44213#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, GPIO6_Combined_0_15_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, GPIO13_Combined_0_31_IRQn, CM7_GPIO2_3_IRQn, CM7_GPIO2_3_IRQn }
44214#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, GPIO6_Combined_16_31_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, GPIO13_Combined_0_31_IRQn, CM7_GPIO2_3_IRQn, CM7_GPIO2_3_IRQn }
44215 /* end of group GPIO_Peripheral_Access_Layer */
44219
44220
44221/* ----------------------------------------------------------------------------
44222 -- GPT Peripheral Access Layer
44223 ---------------------------------------------------------------------------- */
44224
44231typedef struct {
44232 __IO uint32_t CR;
44233 __IO uint32_t PR;
44234 __IO uint32_t SR;
44235 __IO uint32_t IR;
44236 __IO uint32_t OCR[3];
44237 __I uint32_t ICR[2];
44238 __I uint32_t CNT;
44239} GPT_Type;
44240
44241/* ----------------------------------------------------------------------------
44242 -- GPT Register Masks
44243 ---------------------------------------------------------------------------- */
44244
44253#define GPT_CR_EN_MASK (0x1U)
44254#define GPT_CR_EN_SHIFT (0U)
44259#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
44260
44261#define GPT_CR_ENMOD_MASK (0x2U)
44262#define GPT_CR_ENMOD_SHIFT (1U)
44267#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
44268
44269#define GPT_CR_DBGEN_MASK (0x4U)
44270#define GPT_CR_DBGEN_SHIFT (2U)
44275#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
44276
44277#define GPT_CR_WAITEN_MASK (0x8U)
44278#define GPT_CR_WAITEN_SHIFT (3U)
44283#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
44284
44285#define GPT_CR_DOZEEN_MASK (0x10U)
44286#define GPT_CR_DOZEEN_SHIFT (4U)
44291#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
44292
44293#define GPT_CR_STOPEN_MASK (0x20U)
44294#define GPT_CR_STOPEN_SHIFT (5U)
44299#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
44300
44301#define GPT_CR_CLKSRC_MASK (0x1C0U)
44302#define GPT_CR_CLKSRC_SHIFT (6U)
44311#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
44312
44313#define GPT_CR_FRR_MASK (0x200U)
44314#define GPT_CR_FRR_SHIFT (9U)
44319#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
44320
44321#define GPT_CR_EN_24M_MASK (0x400U)
44322#define GPT_CR_EN_24M_SHIFT (10U)
44327#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
44328
44329#define GPT_CR_SWR_MASK (0x8000U)
44330#define GPT_CR_SWR_SHIFT (15U)
44335#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
44336
44337#define GPT_CR_IM1_MASK (0x30000U)
44338#define GPT_CR_IM1_SHIFT (16U)
44345#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
44346
44347#define GPT_CR_IM2_MASK (0xC0000U)
44348#define GPT_CR_IM2_SHIFT (18U)
44355#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
44356
44357#define GPT_CR_OM1_MASK (0x700000U)
44358#define GPT_CR_OM1_SHIFT (20U)
44368#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
44369
44370#define GPT_CR_OM2_MASK (0x3800000U)
44371#define GPT_CR_OM2_SHIFT (23U)
44381#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
44382
44383#define GPT_CR_OM3_MASK (0x1C000000U)
44384#define GPT_CR_OM3_SHIFT (26U)
44394#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
44395
44396#define GPT_CR_FO1_MASK (0x20000000U)
44397#define GPT_CR_FO1_SHIFT (29U)
44402#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
44403
44404#define GPT_CR_FO2_MASK (0x40000000U)
44405#define GPT_CR_FO2_SHIFT (30U)
44410#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
44411
44412#define GPT_CR_FO3_MASK (0x80000000U)
44413#define GPT_CR_FO3_SHIFT (31U)
44418#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
44424#define GPT_PR_PRESCALER_MASK (0xFFFU)
44425#define GPT_PR_PRESCALER_SHIFT (0U)
44431#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
44432
44433#define GPT_PR_PRESCALER24M_MASK (0xF000U)
44434#define GPT_PR_PRESCALER24M_SHIFT (12U)
44440#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
44446#define GPT_SR_OF1_MASK (0x1U)
44447#define GPT_SR_OF1_SHIFT (0U)
44452#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
44453
44454#define GPT_SR_OF2_MASK (0x2U)
44455#define GPT_SR_OF2_SHIFT (1U)
44460#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
44461
44462#define GPT_SR_OF3_MASK (0x4U)
44463#define GPT_SR_OF3_SHIFT (2U)
44468#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
44469
44470#define GPT_SR_IF1_MASK (0x8U)
44471#define GPT_SR_IF1_SHIFT (3U)
44476#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
44477
44478#define GPT_SR_IF2_MASK (0x10U)
44479#define GPT_SR_IF2_SHIFT (4U)
44484#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
44485
44486#define GPT_SR_ROV_MASK (0x20U)
44487#define GPT_SR_ROV_SHIFT (5U)
44492#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
44498#define GPT_IR_OF1IE_MASK (0x1U)
44499#define GPT_IR_OF1IE_SHIFT (0U)
44504#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
44505
44506#define GPT_IR_OF2IE_MASK (0x2U)
44507#define GPT_IR_OF2IE_SHIFT (1U)
44512#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
44513
44514#define GPT_IR_OF3IE_MASK (0x4U)
44515#define GPT_IR_OF3IE_SHIFT (2U)
44520#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
44521
44522#define GPT_IR_IF1IE_MASK (0x8U)
44523#define GPT_IR_IF1IE_SHIFT (3U)
44528#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
44529
44530#define GPT_IR_IF2IE_MASK (0x10U)
44531#define GPT_IR_IF2IE_SHIFT (4U)
44536#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
44537
44538#define GPT_IR_ROVIE_MASK (0x20U)
44539#define GPT_IR_ROVIE_SHIFT (5U)
44544#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
44550#define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
44551#define GPT_OCR_COMP_SHIFT (0U)
44554#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
44557/* The count of GPT_OCR */
44558#define GPT_OCR_COUNT (3U)
44559
44563#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
44564#define GPT_ICR_CAPT_SHIFT (0U)
44567#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
44570/* The count of GPT_ICR */
44571#define GPT_ICR_COUNT (2U)
44572
44576#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
44577#define GPT_CNT_COUNT_SHIFT (0U)
44580#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) /* end of group GPT_Register_Masks */
44587
44588
44589/* GPT - Peripheral instance base addresses */
44591#define GPT1_BASE (0x400EC000u)
44593#define GPT1 ((GPT_Type *)GPT1_BASE)
44595#define GPT2_BASE (0x400F0000u)
44597#define GPT2 ((GPT_Type *)GPT2_BASE)
44599#define GPT3_BASE (0x400F4000u)
44601#define GPT3 ((GPT_Type *)GPT3_BASE)
44603#define GPT4_BASE (0x400F8000u)
44605#define GPT4 ((GPT_Type *)GPT4_BASE)
44607#define GPT5_BASE (0x400FC000u)
44609#define GPT5 ((GPT_Type *)GPT5_BASE)
44611#define GPT6_BASE (0x40100000u)
44613#define GPT6 ((GPT_Type *)GPT6_BASE)
44615#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE }
44617#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 }
44619#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn }
44620 /* end of group GPT_Peripheral_Access_Layer */
44624
44625
44626/* ----------------------------------------------------------------------------
44627 -- I2S Peripheral Access Layer
44628 ---------------------------------------------------------------------------- */
44629
44636typedef struct {
44637 __I uint32_t VERID;
44638 __I uint32_t PARAM;
44639 __IO uint32_t TCSR;
44640 __IO uint32_t TCR1;
44641 __IO uint32_t TCR2;
44642 __IO uint32_t TCR3;
44643 __IO uint32_t TCR4;
44644 __IO uint32_t TCR5;
44645 __O uint32_t TDR[4];
44646 uint8_t RESERVED_0[16];
44647 __I uint32_t TFR[4];
44648 uint8_t RESERVED_1[16];
44649 __IO uint32_t TMR;
44650 uint8_t RESERVED_2[36];
44651 __IO uint32_t RCSR;
44652 __IO uint32_t RCR1;
44653 __IO uint32_t RCR2;
44654 __IO uint32_t RCR3;
44655 __IO uint32_t RCR4;
44656 __IO uint32_t RCR5;
44657 __I uint32_t RDR[4];
44658 uint8_t RESERVED_3[16];
44659 __I uint32_t RFR[4];
44660 uint8_t RESERVED_4[16];
44661 __IO uint32_t RMR;
44662} I2S_Type;
44663
44664/* ----------------------------------------------------------------------------
44665 -- I2S Register Masks
44666 ---------------------------------------------------------------------------- */
44667
44676#define I2S_VERID_FEATURE_MASK (0xFFFFU)
44677#define I2S_VERID_FEATURE_SHIFT (0U)
44681#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
44682
44683#define I2S_VERID_MINOR_MASK (0xFF0000U)
44684#define I2S_VERID_MINOR_SHIFT (16U)
44687#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
44688
44689#define I2S_VERID_MAJOR_MASK (0xFF000000U)
44690#define I2S_VERID_MAJOR_SHIFT (24U)
44693#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
44699#define I2S_PARAM_DATALINE_MASK (0xFU)
44700#define I2S_PARAM_DATALINE_SHIFT (0U)
44703#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
44704
44705#define I2S_PARAM_FIFO_MASK (0xF00U)
44706#define I2S_PARAM_FIFO_SHIFT (8U)
44709#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
44710
44711#define I2S_PARAM_FRAME_MASK (0xF0000U)
44712#define I2S_PARAM_FRAME_SHIFT (16U)
44715#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
44721#define I2S_TCSR_FRDE_MASK (0x1U)
44722#define I2S_TCSR_FRDE_SHIFT (0U)
44727#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
44728
44729#define I2S_TCSR_FWDE_MASK (0x2U)
44730#define I2S_TCSR_FWDE_SHIFT (1U)
44735#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
44736
44737#define I2S_TCSR_FRIE_MASK (0x100U)
44738#define I2S_TCSR_FRIE_SHIFT (8U)
44743#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
44744
44745#define I2S_TCSR_FWIE_MASK (0x200U)
44746#define I2S_TCSR_FWIE_SHIFT (9U)
44751#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
44752
44753#define I2S_TCSR_FEIE_MASK (0x400U)
44754#define I2S_TCSR_FEIE_SHIFT (10U)
44759#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
44760
44761#define I2S_TCSR_SEIE_MASK (0x800U)
44762#define I2S_TCSR_SEIE_SHIFT (11U)
44767#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
44768
44769#define I2S_TCSR_WSIE_MASK (0x1000U)
44770#define I2S_TCSR_WSIE_SHIFT (12U)
44775#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
44776
44777#define I2S_TCSR_FRF_MASK (0x10000U)
44778#define I2S_TCSR_FRF_SHIFT (16U)
44783#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
44784
44785#define I2S_TCSR_FWF_MASK (0x20000U)
44786#define I2S_TCSR_FWF_SHIFT (17U)
44791#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
44792
44793#define I2S_TCSR_FEF_MASK (0x40000U)
44794#define I2S_TCSR_FEF_SHIFT (18U)
44799#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
44800
44801#define I2S_TCSR_SEF_MASK (0x80000U)
44802#define I2S_TCSR_SEF_SHIFT (19U)
44807#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
44808
44809#define I2S_TCSR_WSF_MASK (0x100000U)
44810#define I2S_TCSR_WSF_SHIFT (20U)
44815#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
44816
44817#define I2S_TCSR_SR_MASK (0x1000000U)
44818#define I2S_TCSR_SR_SHIFT (24U)
44823#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
44824
44825#define I2S_TCSR_FR_MASK (0x2000000U)
44826#define I2S_TCSR_FR_SHIFT (25U)
44831#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
44832
44833#define I2S_TCSR_BCE_MASK (0x10000000U)
44834#define I2S_TCSR_BCE_SHIFT (28U)
44839#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
44840
44841#define I2S_TCSR_DBGE_MASK (0x20000000U)
44842#define I2S_TCSR_DBGE_SHIFT (29U)
44847#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
44848
44849#define I2S_TCSR_STOPE_MASK (0x40000000U)
44850#define I2S_TCSR_STOPE_SHIFT (30U)
44855#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
44856
44857#define I2S_TCSR_TE_MASK (0x80000000U)
44858#define I2S_TCSR_TE_SHIFT (31U)
44863#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
44869#define I2S_TCR1_TFW_MASK (0x1FU)
44870#define I2S_TCR1_TFW_SHIFT (0U)
44873#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
44879#define I2S_TCR2_DIV_MASK (0xFFU)
44880#define I2S_TCR2_DIV_SHIFT (0U)
44883#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
44884
44885#define I2S_TCR2_BYP_MASK (0x800000U)
44886#define I2S_TCR2_BYP_SHIFT (23U)
44891#define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)
44892
44893#define I2S_TCR2_BCD_MASK (0x1000000U)
44894#define I2S_TCR2_BCD_SHIFT (24U)
44899#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
44900
44901#define I2S_TCR2_BCP_MASK (0x2000000U)
44902#define I2S_TCR2_BCP_SHIFT (25U)
44907#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
44908
44909#define I2S_TCR2_MSEL_MASK (0xC000000U)
44910#define I2S_TCR2_MSEL_SHIFT (26U)
44917#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
44918
44919#define I2S_TCR2_BCI_MASK (0x10000000U)
44920#define I2S_TCR2_BCI_SHIFT (28U)
44925#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
44926
44927#define I2S_TCR2_BCS_MASK (0x20000000U)
44928#define I2S_TCR2_BCS_SHIFT (29U)
44933#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
44934
44935#define I2S_TCR2_SYNC_MASK (0x40000000U)
44936#define I2S_TCR2_SYNC_SHIFT (30U)
44941#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
44947#define I2S_TCR3_WDFL_MASK (0x1FU)
44948#define I2S_TCR3_WDFL_SHIFT (0U)
44951#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
44952
44953#define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
44954#define I2S_TCR3_TCE_SHIFT (16U)
44957#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
44958
44959#define I2S_TCR3_CFR_MASK (0xF000000U)
44960#define I2S_TCR3_CFR_SHIFT (24U)
44963#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
44969#define I2S_TCR4_FSD_MASK (0x1U)
44970#define I2S_TCR4_FSD_SHIFT (0U)
44975#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
44976
44977#define I2S_TCR4_FSP_MASK (0x2U)
44978#define I2S_TCR4_FSP_SHIFT (1U)
44983#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
44984
44985#define I2S_TCR4_ONDEM_MASK (0x4U)
44986#define I2S_TCR4_ONDEM_SHIFT (2U)
44991#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
44992
44993#define I2S_TCR4_FSE_MASK (0x8U)
44994#define I2S_TCR4_FSE_SHIFT (3U)
44999#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
45000
45001#define I2S_TCR4_MF_MASK (0x10U)
45002#define I2S_TCR4_MF_SHIFT (4U)
45007#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
45008
45009#define I2S_TCR4_CHMOD_MASK (0x20U)
45010#define I2S_TCR4_CHMOD_SHIFT (5U)
45015#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
45016
45017#define I2S_TCR4_SYWD_MASK (0x1F00U)
45018#define I2S_TCR4_SYWD_SHIFT (8U)
45021#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
45022
45023#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
45024#define I2S_TCR4_FRSZ_SHIFT (16U)
45027#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
45028
45029#define I2S_TCR4_FPACK_MASK (0x3000000U)
45030#define I2S_TCR4_FPACK_SHIFT (24U)
45037#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
45038
45039#define I2S_TCR4_FCOMB_MASK (0xC000000U)
45040#define I2S_TCR4_FCOMB_SHIFT (26U)
45047#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
45048
45049#define I2S_TCR4_FCONT_MASK (0x10000000U)
45050#define I2S_TCR4_FCONT_SHIFT (28U)
45055#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
45061#define I2S_TCR5_FBT_MASK (0x1F00U)
45062#define I2S_TCR5_FBT_SHIFT (8U)
45065#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
45066
45067#define I2S_TCR5_W0W_MASK (0x1F0000U)
45068#define I2S_TCR5_W0W_SHIFT (16U)
45071#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
45072
45073#define I2S_TCR5_WNW_MASK (0x1F000000U)
45074#define I2S_TCR5_WNW_SHIFT (24U)
45077#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
45083#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
45084#define I2S_TDR_TDR_SHIFT (0U)
45087#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
45090/* The count of I2S_TDR */
45091#define I2S_TDR_COUNT (4U)
45092
45096#define I2S_TFR_RFP_MASK (0x3FU)
45097#define I2S_TFR_RFP_SHIFT (0U)
45100#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
45101
45102#define I2S_TFR_WFP_MASK (0x3F0000U)
45103#define I2S_TFR_WFP_SHIFT (16U)
45106#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
45107
45108#define I2S_TFR_WCP_MASK (0x80000000U)
45109#define I2S_TFR_WCP_SHIFT (31U)
45114#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
45117/* The count of I2S_TFR */
45118#define I2S_TFR_COUNT (4U)
45119
45123#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
45124#define I2S_TMR_TWM_SHIFT (0U)
45129#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
45135#define I2S_RCSR_FRDE_MASK (0x1U)
45136#define I2S_RCSR_FRDE_SHIFT (0U)
45141#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
45142
45143#define I2S_RCSR_FWDE_MASK (0x2U)
45144#define I2S_RCSR_FWDE_SHIFT (1U)
45149#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
45150
45151#define I2S_RCSR_FRIE_MASK (0x100U)
45152#define I2S_RCSR_FRIE_SHIFT (8U)
45157#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
45158
45159#define I2S_RCSR_FWIE_MASK (0x200U)
45160#define I2S_RCSR_FWIE_SHIFT (9U)
45165#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
45166
45167#define I2S_RCSR_FEIE_MASK (0x400U)
45168#define I2S_RCSR_FEIE_SHIFT (10U)
45173#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
45174
45175#define I2S_RCSR_SEIE_MASK (0x800U)
45176#define I2S_RCSR_SEIE_SHIFT (11U)
45181#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
45182
45183#define I2S_RCSR_WSIE_MASK (0x1000U)
45184#define I2S_RCSR_WSIE_SHIFT (12U)
45189#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
45190
45191#define I2S_RCSR_FRF_MASK (0x10000U)
45192#define I2S_RCSR_FRF_SHIFT (16U)
45197#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
45198
45199#define I2S_RCSR_FWF_MASK (0x20000U)
45200#define I2S_RCSR_FWF_SHIFT (17U)
45205#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
45206
45207#define I2S_RCSR_FEF_MASK (0x40000U)
45208#define I2S_RCSR_FEF_SHIFT (18U)
45213#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
45214
45215#define I2S_RCSR_SEF_MASK (0x80000U)
45216#define I2S_RCSR_SEF_SHIFT (19U)
45221#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
45222
45223#define I2S_RCSR_WSF_MASK (0x100000U)
45224#define I2S_RCSR_WSF_SHIFT (20U)
45229#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
45230
45231#define I2S_RCSR_SR_MASK (0x1000000U)
45232#define I2S_RCSR_SR_SHIFT (24U)
45237#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
45238
45239#define I2S_RCSR_FR_MASK (0x2000000U)
45240#define I2S_RCSR_FR_SHIFT (25U)
45245#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
45246
45247#define I2S_RCSR_BCE_MASK (0x10000000U)
45248#define I2S_RCSR_BCE_SHIFT (28U)
45253#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
45254
45255#define I2S_RCSR_DBGE_MASK (0x20000000U)
45256#define I2S_RCSR_DBGE_SHIFT (29U)
45261#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
45262
45263#define I2S_RCSR_STOPE_MASK (0x40000000U)
45264#define I2S_RCSR_STOPE_SHIFT (30U)
45269#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
45270
45271#define I2S_RCSR_RE_MASK (0x80000000U)
45272#define I2S_RCSR_RE_SHIFT (31U)
45277#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
45283#define I2S_RCR1_RFW_MASK (0x1FU)
45284#define I2S_RCR1_RFW_SHIFT (0U)
45287#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
45293#define I2S_RCR2_DIV_MASK (0xFFU)
45294#define I2S_RCR2_DIV_SHIFT (0U)
45297#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
45298
45299#define I2S_RCR2_BYP_MASK (0x800000U)
45300#define I2S_RCR2_BYP_SHIFT (23U)
45305#define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)
45306
45307#define I2S_RCR2_BCD_MASK (0x1000000U)
45308#define I2S_RCR2_BCD_SHIFT (24U)
45313#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
45314
45315#define I2S_RCR2_BCP_MASK (0x2000000U)
45316#define I2S_RCR2_BCP_SHIFT (25U)
45321#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
45322
45323#define I2S_RCR2_MSEL_MASK (0xC000000U)
45324#define I2S_RCR2_MSEL_SHIFT (26U)
45331#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
45332
45333#define I2S_RCR2_BCI_MASK (0x10000000U)
45334#define I2S_RCR2_BCI_SHIFT (28U)
45339#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
45340
45341#define I2S_RCR2_BCS_MASK (0x20000000U)
45342#define I2S_RCR2_BCS_SHIFT (29U)
45347#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
45348
45349#define I2S_RCR2_SYNC_MASK (0x40000000U)
45350#define I2S_RCR2_SYNC_SHIFT (30U)
45355#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
45361#define I2S_RCR3_WDFL_MASK (0x1FU)
45362#define I2S_RCR3_WDFL_SHIFT (0U)
45365#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
45366
45367#define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
45368#define I2S_RCR3_RCE_SHIFT (16U)
45371#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
45372
45373#define I2S_RCR3_CFR_MASK (0xF000000U)
45374#define I2S_RCR3_CFR_SHIFT (24U)
45377#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
45383#define I2S_RCR4_FSD_MASK (0x1U)
45384#define I2S_RCR4_FSD_SHIFT (0U)
45389#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
45390
45391#define I2S_RCR4_FSP_MASK (0x2U)
45392#define I2S_RCR4_FSP_SHIFT (1U)
45397#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
45398
45399#define I2S_RCR4_ONDEM_MASK (0x4U)
45400#define I2S_RCR4_ONDEM_SHIFT (2U)
45405#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
45406
45407#define I2S_RCR4_FSE_MASK (0x8U)
45408#define I2S_RCR4_FSE_SHIFT (3U)
45413#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
45414
45415#define I2S_RCR4_MF_MASK (0x10U)
45416#define I2S_RCR4_MF_SHIFT (4U)
45421#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
45422
45423#define I2S_RCR4_SYWD_MASK (0x1F00U)
45424#define I2S_RCR4_SYWD_SHIFT (8U)
45427#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
45428
45429#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
45430#define I2S_RCR4_FRSZ_SHIFT (16U)
45433#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
45434
45435#define I2S_RCR4_FPACK_MASK (0x3000000U)
45436#define I2S_RCR4_FPACK_SHIFT (24U)
45443#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
45444
45445#define I2S_RCR4_FCOMB_MASK (0xC000000U)
45446#define I2S_RCR4_FCOMB_SHIFT (26U)
45453#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
45454
45455#define I2S_RCR4_FCONT_MASK (0x10000000U)
45456#define I2S_RCR4_FCONT_SHIFT (28U)
45461#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
45467#define I2S_RCR5_FBT_MASK (0x1F00U)
45468#define I2S_RCR5_FBT_SHIFT (8U)
45471#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
45472
45473#define I2S_RCR5_W0W_MASK (0x1F0000U)
45474#define I2S_RCR5_W0W_SHIFT (16U)
45477#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
45478
45479#define I2S_RCR5_WNW_MASK (0x1F000000U)
45480#define I2S_RCR5_WNW_SHIFT (24U)
45483#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
45489#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
45490#define I2S_RDR_RDR_SHIFT (0U)
45493#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
45496/* The count of I2S_RDR */
45497#define I2S_RDR_COUNT (4U)
45498
45502#define I2S_RFR_RFP_MASK (0x3FU)
45503#define I2S_RFR_RFP_SHIFT (0U)
45506#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
45507
45508#define I2S_RFR_RCP_MASK (0x8000U)
45509#define I2S_RFR_RCP_SHIFT (15U)
45514#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
45515
45516#define I2S_RFR_WFP_MASK (0x3F0000U)
45517#define I2S_RFR_WFP_SHIFT (16U)
45520#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
45523/* The count of I2S_RFR */
45524#define I2S_RFR_COUNT (4U)
45525
45529#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
45530#define I2S_RMR_RWM_SHIFT (0U)
45535#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) /* end of group I2S_Register_Masks */
45542
45543
45544/* I2S - Peripheral instance base addresses */
45546#define SAI1_BASE (0x40404000u)
45548#define SAI1 ((I2S_Type *)SAI1_BASE)
45550#define SAI2_BASE (0x40408000u)
45552#define SAI2 ((I2S_Type *)SAI2_BASE)
45554#define SAI3_BASE (0x4040C000u)
45556#define SAI3 ((I2S_Type *)SAI3_BASE)
45558#define SAI4_BASE (0x40C40000u)
45560#define SAI4 ((I2S_Type *)SAI4_BASE)
45562#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE }
45564#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 }
45566#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn, SAI4_RX_IRQn }
45567#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn, SAI4_TX_IRQn }
45568 /* end of group I2S_Peripheral_Access_Layer */
45572
45573
45574/* ----------------------------------------------------------------------------
45575 -- IEE Peripheral Access Layer
45576 ---------------------------------------------------------------------------- */
45577
45584typedef struct {
45585 __IO uint32_t GCFG;
45586 __I uint32_t STA;
45587 __IO uint32_t TSTMD;
45588 __O uint32_t DPAMS;
45589 uint8_t RESERVED_0[16];
45590 __IO uint32_t PC_S_LT;
45591 __IO uint32_t PC_M_LT;
45592 uint8_t RESERVED_1[24];
45593 __IO uint32_t PC_BLK_ENC;
45594 __IO uint32_t PC_BLK_DEC;
45595 uint8_t RESERVED_2[8];
45596 __IO uint32_t PC_SR_TRANS;
45597 __IO uint32_t PC_SW_TRANS;
45598 __IO uint32_t PC_MR_TRANS;
45599 __IO uint32_t PC_MW_TRANS;
45600 uint8_t RESERVED_3[4];
45601 __IO uint32_t PC_M_MBR;
45602 uint8_t RESERVED_4[8];
45603 __IO uint32_t PC_SR_TBC_U;
45604 __IO uint32_t PC_SR_TBC_L;
45605 __IO uint32_t PC_SW_TBC_U;
45606 __IO uint32_t PC_SW_TBC_L;
45607 __IO uint32_t PC_MR_TBC_U;
45608 __IO uint32_t PC_MR_TBC_L;
45609 __IO uint32_t PC_MW_TBC_U;
45610 __IO uint32_t PC_MW_TBC_L;
45611 __IO uint32_t PC_SR_TLGTT;
45612 __IO uint32_t PC_SW_TLGTT;
45613 __IO uint32_t PC_MR_TLGTT;
45614 __IO uint32_t PC_MW_TLGTT;
45615 __IO uint32_t PC_SR_TLAT_U;
45616 __IO uint32_t PC_SR_TLAT_L;
45617 __IO uint32_t PC_SW_TLAT_U;
45618 __IO uint32_t PC_SW_TLAT_L;
45619 __IO uint32_t PC_MR_TLAT_U;
45620 __IO uint32_t PC_MR_TLAT_L;
45621 __IO uint32_t PC_MW_TLAT_U;
45622 __IO uint32_t PC_MW_TLAT_L;
45623 __IO uint32_t PC_SR_TNRT_U;
45624 __IO uint32_t PC_SR_TNRT_L;
45625 __IO uint32_t PC_SW_TNRT_U;
45626 __IO uint32_t PC_SW_TNRT_L;
45627 uint8_t RESERVED_5[32];
45628 __I uint32_t VIDR1;
45629 uint8_t RESERVED_6[4];
45630 __I uint32_t AESVID;
45631 uint8_t RESERVED_7[4];
45632 struct { /* offset: 0x100, array step: 0x100 */
45633 __IO uint32_t REGATTR;
45634 uint8_t RESERVED_0[4];
45635 __IO uint32_t REGPO;
45636 uint8_t RESERVED_1[52];
45637 __O uint32_t REGKEY1[8];
45638 uint8_t RESERVED_2[32];
45639 __O uint32_t REGKEY2[8];
45640 uint8_t RESERVED_3[96];
45641 } REGX[8];
45642 uint8_t RESERVED_8[1536];
45643 __IO uint32_t AES_TST_DB[32];
45644} IEE_Type;
45645
45646/* ----------------------------------------------------------------------------
45647 -- IEE Register Masks
45648 ---------------------------------------------------------------------------- */
45649
45658#define IEE_GCFG_RL0_MASK (0x1U)
45659#define IEE_GCFG_RL0_SHIFT (0U)
45664#define IEE_GCFG_RL0(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL0_SHIFT)) & IEE_GCFG_RL0_MASK)
45665
45666#define IEE_GCFG_RL1_MASK (0x2U)
45667#define IEE_GCFG_RL1_SHIFT (1U)
45672#define IEE_GCFG_RL1(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL1_SHIFT)) & IEE_GCFG_RL1_MASK)
45673
45674#define IEE_GCFG_RL2_MASK (0x4U)
45675#define IEE_GCFG_RL2_SHIFT (2U)
45680#define IEE_GCFG_RL2(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL2_SHIFT)) & IEE_GCFG_RL2_MASK)
45681
45682#define IEE_GCFG_RL3_MASK (0x8U)
45683#define IEE_GCFG_RL3_SHIFT (3U)
45688#define IEE_GCFG_RL3(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL3_SHIFT)) & IEE_GCFG_RL3_MASK)
45689
45690#define IEE_GCFG_RL4_MASK (0x10U)
45691#define IEE_GCFG_RL4_SHIFT (4U)
45696#define IEE_GCFG_RL4(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL4_SHIFT)) & IEE_GCFG_RL4_MASK)
45697
45698#define IEE_GCFG_RL5_MASK (0x20U)
45699#define IEE_GCFG_RL5_SHIFT (5U)
45704#define IEE_GCFG_RL5(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL5_SHIFT)) & IEE_GCFG_RL5_MASK)
45705
45706#define IEE_GCFG_RL6_MASK (0x40U)
45707#define IEE_GCFG_RL6_SHIFT (6U)
45712#define IEE_GCFG_RL6(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL6_SHIFT)) & IEE_GCFG_RL6_MASK)
45713
45714#define IEE_GCFG_RL7_MASK (0x80U)
45715#define IEE_GCFG_RL7_SHIFT (7U)
45720#define IEE_GCFG_RL7(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL7_SHIFT)) & IEE_GCFG_RL7_MASK)
45721
45722#define IEE_GCFG_TME_MASK (0x10000U)
45723#define IEE_GCFG_TME_SHIFT (16U)
45728#define IEE_GCFG_TME(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TME_SHIFT)) & IEE_GCFG_TME_MASK)
45729
45730#define IEE_GCFG_TMD_MASK (0x20000U)
45731#define IEE_GCFG_TMD_SHIFT (17U)
45736#define IEE_GCFG_TMD(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TMD_SHIFT)) & IEE_GCFG_TMD_MASK)
45737
45738#define IEE_GCFG_KEY_RD_DIS_MASK (0x2000000U)
45739#define IEE_GCFG_KEY_RD_DIS_SHIFT (25U)
45744#define IEE_GCFG_KEY_RD_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_KEY_RD_DIS_SHIFT)) & IEE_GCFG_KEY_RD_DIS_MASK)
45745
45746#define IEE_GCFG_MON_EN_MASK (0x10000000U)
45747#define IEE_GCFG_MON_EN_SHIFT (28U)
45752#define IEE_GCFG_MON_EN(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_MON_EN_SHIFT)) & IEE_GCFG_MON_EN_MASK)
45753
45754#define IEE_GCFG_CLR_MON_MASK (0x20000000U)
45755#define IEE_GCFG_CLR_MON_SHIFT (29U)
45760#define IEE_GCFG_CLR_MON(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_CLR_MON_SHIFT)) & IEE_GCFG_CLR_MON_MASK)
45761
45762#define IEE_GCFG_RST_MASK (0x80000000U)
45763#define IEE_GCFG_RST_SHIFT (31U)
45768#define IEE_GCFG_RST(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RST_SHIFT)) & IEE_GCFG_RST_MASK)
45774#define IEE_STA_DSR_MASK (0x1U)
45775#define IEE_STA_DSR_SHIFT (0U)
45780#define IEE_STA_DSR(x) (((uint32_t)(((uint32_t)(x)) << IEE_STA_DSR_SHIFT)) & IEE_STA_DSR_MASK)
45781
45782#define IEE_STA_AFD_MASK (0x10U)
45783#define IEE_STA_AFD_SHIFT (4U)
45788#define IEE_STA_AFD(x) (((uint32_t)(((uint32_t)(x)) << IEE_STA_AFD_SHIFT)) & IEE_STA_AFD_MASK)
45794#define IEE_TSTMD_TMRDY_MASK (0x1U)
45795#define IEE_TSTMD_TMRDY_SHIFT (0U)
45800#define IEE_TSTMD_TMRDY(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMRDY_SHIFT)) & IEE_TSTMD_TMRDY_MASK)
45801
45802#define IEE_TSTMD_TMR_MASK (0x2U)
45803#define IEE_TSTMD_TMR_SHIFT (1U)
45808#define IEE_TSTMD_TMR(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMR_SHIFT)) & IEE_TSTMD_TMR_MASK)
45809
45810#define IEE_TSTMD_TMENCR_MASK (0x4U)
45811#define IEE_TSTMD_TMENCR_SHIFT (2U)
45816#define IEE_TSTMD_TMENCR(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMENCR_SHIFT)) & IEE_TSTMD_TMENCR_MASK)
45817
45818#define IEE_TSTMD_TMCONT_MASK (0x8U)
45819#define IEE_TSTMD_TMCONT_SHIFT (3U)
45824#define IEE_TSTMD_TMCONT(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMCONT_SHIFT)) & IEE_TSTMD_TMCONT_MASK)
45825
45826#define IEE_TSTMD_TMDONE_MASK (0x10U)
45827#define IEE_TSTMD_TMDONE_SHIFT (4U)
45832#define IEE_TSTMD_TMDONE(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMDONE_SHIFT)) & IEE_TSTMD_TMDONE_MASK)
45833
45834#define IEE_TSTMD_TMLEN_MASK (0xF00U)
45835#define IEE_TSTMD_TMLEN_SHIFT (8U)
45836#define IEE_TSTMD_TMLEN(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMLEN_SHIFT)) & IEE_TSTMD_TMLEN_MASK)
45842#define IEE_DPAMS_DPAMS_MASK (0xFFFFFFFFU)
45843#define IEE_DPAMS_DPAMS_SHIFT (0U)
45844#define IEE_DPAMS_DPAMS(x) (((uint32_t)(((uint32_t)(x)) << IEE_DPAMS_DPAMS_SHIFT)) & IEE_DPAMS_DPAMS_MASK)
45850#define IEE_PC_S_LT_SW_LT_MASK (0xFFFFU)
45851#define IEE_PC_S_LT_SW_LT_SHIFT (0U)
45852#define IEE_PC_S_LT_SW_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SW_LT_SHIFT)) & IEE_PC_S_LT_SW_LT_MASK)
45853
45854#define IEE_PC_S_LT_SR_LT_MASK (0xFFFF0000U)
45855#define IEE_PC_S_LT_SR_LT_SHIFT (16U)
45856#define IEE_PC_S_LT_SR_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SR_LT_SHIFT)) & IEE_PC_S_LT_SR_LT_MASK)
45862#define IEE_PC_M_LT_MW_LT_MASK (0xFFFU)
45863#define IEE_PC_M_LT_MW_LT_SHIFT (0U)
45864#define IEE_PC_M_LT_MW_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MW_LT_SHIFT)) & IEE_PC_M_LT_MW_LT_MASK)
45865
45866#define IEE_PC_M_LT_MR_LT_MASK (0xFFF0000U)
45867#define IEE_PC_M_LT_MR_LT_SHIFT (16U)
45868#define IEE_PC_M_LT_MR_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MR_LT_SHIFT)) & IEE_PC_M_LT_MR_LT_MASK)
45874#define IEE_PC_BLK_ENC_BLK_ENC_MASK (0xFFFFFFFFU)
45875#define IEE_PC_BLK_ENC_BLK_ENC_SHIFT (0U)
45876#define IEE_PC_BLK_ENC_BLK_ENC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_ENC_BLK_ENC_SHIFT)) & IEE_PC_BLK_ENC_BLK_ENC_MASK)
45882#define IEE_PC_BLK_DEC_BLK_DEC_MASK (0xFFFFFFFFU)
45883#define IEE_PC_BLK_DEC_BLK_DEC_SHIFT (0U)
45884#define IEE_PC_BLK_DEC_BLK_DEC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_DEC_BLK_DEC_SHIFT)) & IEE_PC_BLK_DEC_BLK_DEC_MASK)
45890#define IEE_PC_SR_TRANS_SR_TRANS_MASK (0xFFFFFFFFU)
45891#define IEE_PC_SR_TRANS_SR_TRANS_SHIFT (0U)
45892#define IEE_PC_SR_TRANS_SR_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TRANS_SR_TRANS_SHIFT)) & IEE_PC_SR_TRANS_SR_TRANS_MASK)
45898#define IEE_PC_SW_TRANS_SW_TRANS_MASK (0xFFFFFFFFU)
45899#define IEE_PC_SW_TRANS_SW_TRANS_SHIFT (0U)
45900#define IEE_PC_SW_TRANS_SW_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TRANS_SW_TRANS_SHIFT)) & IEE_PC_SW_TRANS_SW_TRANS_MASK)
45906#define IEE_PC_MR_TRANS_MR_TRANS_MASK (0xFFFFFFFFU)
45907#define IEE_PC_MR_TRANS_MR_TRANS_SHIFT (0U)
45908#define IEE_PC_MR_TRANS_MR_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TRANS_MR_TRANS_SHIFT)) & IEE_PC_MR_TRANS_MR_TRANS_MASK)
45914#define IEE_PC_MW_TRANS_MW_TRANS_MASK (0xFFFFFFFFU)
45915#define IEE_PC_MW_TRANS_MW_TRANS_SHIFT (0U)
45916#define IEE_PC_MW_TRANS_MW_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TRANS_MW_TRANS_SHIFT)) & IEE_PC_MW_TRANS_MW_TRANS_MASK)
45922#define IEE_PC_M_MBR_M_MBR_MASK (0xFFFFFFFFU)
45923#define IEE_PC_M_MBR_M_MBR_SHIFT (0U)
45924#define IEE_PC_M_MBR_M_MBR(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_MBR_M_MBR_SHIFT)) & IEE_PC_M_MBR_M_MBR_MASK)
45930#define IEE_PC_SR_TBC_U_SR_TBC_MASK (0xFFFFU)
45931#define IEE_PC_SR_TBC_U_SR_TBC_SHIFT (0U)
45932#define IEE_PC_SR_TBC_U_SR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_U_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_U_SR_TBC_MASK)
45938#define IEE_PC_SR_TBC_L_SR_TBC_MASK (0xFFFFFFFFU)
45939#define IEE_PC_SR_TBC_L_SR_TBC_SHIFT (0U)
45940#define IEE_PC_SR_TBC_L_SR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_L_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_L_SR_TBC_MASK)
45946#define IEE_PC_SW_TBC_U_SW_TBC_MASK (0xFFFFU)
45947#define IEE_PC_SW_TBC_U_SW_TBC_SHIFT (0U)
45948#define IEE_PC_SW_TBC_U_SW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_U_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_U_SW_TBC_MASK)
45954#define IEE_PC_SW_TBC_L_SW_TBC_MASK (0xFFFFFFFFU)
45955#define IEE_PC_SW_TBC_L_SW_TBC_SHIFT (0U)
45956#define IEE_PC_SW_TBC_L_SW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_L_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_L_SW_TBC_MASK)
45962#define IEE_PC_MR_TBC_U_MR_TBC_MASK (0xFFFFU)
45963#define IEE_PC_MR_TBC_U_MR_TBC_SHIFT (0U)
45964#define IEE_PC_MR_TBC_U_MR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_U_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_U_MR_TBC_MASK)
45970#define IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK (0xFU)
45971#define IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT (0U)
45972#define IEE_PC_MR_TBC_L_MR_TBC_LSB(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK)
45973
45974#define IEE_PC_MR_TBC_L_MR_TBC_MASK (0xFFFFFFF0U)
45975#define IEE_PC_MR_TBC_L_MR_TBC_SHIFT (4U)
45976#define IEE_PC_MR_TBC_L_MR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_MASK)
45982#define IEE_PC_MW_TBC_U_MW_TBC_MASK (0xFFFFU)
45983#define IEE_PC_MW_TBC_U_MW_TBC_SHIFT (0U)
45984#define IEE_PC_MW_TBC_U_MW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_U_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_U_MW_TBC_MASK)
45990#define IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK (0xFU)
45991#define IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT (0U)
45992#define IEE_PC_MW_TBC_L_MW_TBC_LSB(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK)
45993
45994#define IEE_PC_MW_TBC_L_MW_TBC_MASK (0xFFFFFFF0U)
45995#define IEE_PC_MW_TBC_L_MW_TBC_SHIFT (4U)
45996#define IEE_PC_MW_TBC_L_MW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_MASK)
46002#define IEE_PC_SR_TLGTT_SR_TLGTT_MASK (0xFFFFFFFFU)
46003#define IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT (0U)
46004#define IEE_PC_SR_TLGTT_SR_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT)) & IEE_PC_SR_TLGTT_SR_TLGTT_MASK)
46010#define IEE_PC_SW_TLGTT_SW_TLGTT_MASK (0xFFFFFFFFU)
46011#define IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT (0U)
46012#define IEE_PC_SW_TLGTT_SW_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT)) & IEE_PC_SW_TLGTT_SW_TLGTT_MASK)
46018#define IEE_PC_MR_TLGTT_MR_TLGTT_MASK (0xFFFFFFFFU)
46019#define IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT (0U)
46020#define IEE_PC_MR_TLGTT_MR_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT)) & IEE_PC_MR_TLGTT_MR_TLGTT_MASK)
46026#define IEE_PC_MW_TLGTT_MW_TGTT_MASK (0xFFFFFFFFU)
46027#define IEE_PC_MW_TLGTT_MW_TGTT_SHIFT (0U)
46028#define IEE_PC_MW_TLGTT_MW_TGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLGTT_MW_TGTT_SHIFT)) & IEE_PC_MW_TLGTT_MW_TGTT_MASK)
46034#define IEE_PC_SR_TLAT_U_SR_TLAT_MASK (0xFFFFU)
46035#define IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT (0U)
46036#define IEE_PC_SR_TLAT_U_SR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_U_SR_TLAT_MASK)
46042#define IEE_PC_SR_TLAT_L_SR_TLAT_MASK (0xFFFFFFFFU)
46043#define IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT (0U)
46044#define IEE_PC_SR_TLAT_L_SR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_L_SR_TLAT_MASK)
46050#define IEE_PC_SW_TLAT_U_SW_TLAT_MASK (0xFFFFU)
46051#define IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT (0U)
46052#define IEE_PC_SW_TLAT_U_SW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_U_SW_TLAT_MASK)
46058#define IEE_PC_SW_TLAT_L_SW_TLAT_MASK (0xFFFFFFFFU)
46059#define IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT (0U)
46060#define IEE_PC_SW_TLAT_L_SW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_L_SW_TLAT_MASK)
46066#define IEE_PC_MR_TLAT_U_MR_TLAT_MASK (0xFFFFU)
46067#define IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT (0U)
46068#define IEE_PC_MR_TLAT_U_MR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_U_MR_TLAT_MASK)
46074#define IEE_PC_MR_TLAT_L_MR_TLAT_MASK (0xFFFFFFFFU)
46075#define IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT (0U)
46076#define IEE_PC_MR_TLAT_L_MR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_L_MR_TLAT_MASK)
46082#define IEE_PC_MW_TLAT_U_MW_TLAT_MASK (0xFFFFU)
46083#define IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT (0U)
46084#define IEE_PC_MW_TLAT_U_MW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_U_MW_TLAT_MASK)
46090#define IEE_PC_MW_TLAT_L_MW_TLAT_MASK (0xFFFFFFFFU)
46091#define IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT (0U)
46092#define IEE_PC_MW_TLAT_L_MW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_L_MW_TLAT_MASK)
46098#define IEE_PC_SR_TNRT_U_SR_TNRT_MASK (0xFFFFU)
46099#define IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT (0U)
46100#define IEE_PC_SR_TNRT_U_SR_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_U_SR_TNRT_MASK)
46106#define IEE_PC_SR_TNRT_L_SR_TNRT_MASK (0xFFFFFFFFU)
46107#define IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT (0U)
46108#define IEE_PC_SR_TNRT_L_SR_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_L_SR_TNRT_MASK)
46114#define IEE_PC_SW_TNRT_U_SW_TNRT_MASK (0xFFFFU)
46115#define IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT (0U)
46116#define IEE_PC_SW_TNRT_U_SW_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_U_SW_TNRT_MASK)
46122#define IEE_PC_SW_TNRT_L_SW_TNRT_MASK (0xFFFFFFFFU)
46123#define IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT (0U)
46124#define IEE_PC_SW_TNRT_L_SW_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_L_SW_TNRT_MASK)
46130#define IEE_VIDR1_MIN_REV_MASK (0xFFU)
46131#define IEE_VIDR1_MIN_REV_SHIFT (0U)
46132#define IEE_VIDR1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MIN_REV_SHIFT)) & IEE_VIDR1_MIN_REV_MASK)
46133
46134#define IEE_VIDR1_MAJ_REV_MASK (0xFF00U)
46135#define IEE_VIDR1_MAJ_REV_SHIFT (8U)
46136#define IEE_VIDR1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MAJ_REV_SHIFT)) & IEE_VIDR1_MAJ_REV_MASK)
46137
46138#define IEE_VIDR1_IP_ID_MASK (0xFFFF0000U)
46139#define IEE_VIDR1_IP_ID_SHIFT (16U)
46140#define IEE_VIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_IP_ID_SHIFT)) & IEE_VIDR1_IP_ID_MASK)
46146#define IEE_AESVID_AESRN_MASK (0xFU)
46147#define IEE_AESVID_AESRN_SHIFT (0U)
46148#define IEE_AESVID_AESRN(x) (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESRN_SHIFT)) & IEE_AESVID_AESRN_MASK)
46149
46150#define IEE_AESVID_AESVID_MASK (0xF0U)
46151#define IEE_AESVID_AESVID_SHIFT (4U)
46152#define IEE_AESVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESVID_SHIFT)) & IEE_AESVID_AESVID_MASK)
46158#define IEE_REGATTR_KS_MASK (0x1U)
46159#define IEE_REGATTR_KS_SHIFT (0U)
46164#define IEE_REGATTR_KS(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_KS_SHIFT)) & IEE_REGATTR_KS_MASK)
46165
46166#define IEE_REGATTR_MD_MASK (0x70U)
46167#define IEE_REGATTR_MD_SHIFT (4U)
46178#define IEE_REGATTR_MD(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_MD_SHIFT)) & IEE_REGATTR_MD_MASK)
46179
46180#define IEE_REGATTR_BYP_MASK (0x80U)
46181#define IEE_REGATTR_BYP_SHIFT (7U)
46186#define IEE_REGATTR_BYP(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_BYP_SHIFT)) & IEE_REGATTR_BYP_MASK)
46189/* The count of IEE_REGATTR */
46190#define IEE_REGATTR_COUNT (8U)
46191
46195#define IEE_REGPO_PGOFF_MASK (0xFFFFFFU)
46196#define IEE_REGPO_PGOFF_SHIFT (0U)
46197#define IEE_REGPO_PGOFF(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGPO_PGOFF_SHIFT)) & IEE_REGPO_PGOFF_MASK)
46200/* The count of IEE_REGPO */
46201#define IEE_REGPO_COUNT (8U)
46202
46206#define IEE_REGKEY1_KEY1_MASK (0xFFFFFFFFU)
46207#define IEE_REGKEY1_KEY1_SHIFT (0U)
46208#define IEE_REGKEY1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY1_KEY1_SHIFT)) & IEE_REGKEY1_KEY1_MASK)
46211/* The count of IEE_REGKEY1 */
46212#define IEE_REGKEY1_COUNT (8U)
46213
46214/* The count of IEE_REGKEY1 */
46215#define IEE_REGKEY1_COUNT2 (8U)
46216
46220#define IEE_REGKEY2_KEY2_MASK (0xFFFFFFFFU)
46221#define IEE_REGKEY2_KEY2_SHIFT (0U)
46222#define IEE_REGKEY2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY2_KEY2_SHIFT)) & IEE_REGKEY2_KEY2_MASK)
46225/* The count of IEE_REGKEY2 */
46226#define IEE_REGKEY2_COUNT (8U)
46227
46228/* The count of IEE_REGKEY2 */
46229#define IEE_REGKEY2_COUNT2 (8U)
46230
46234#define IEE_AES_TST_DB_AES_TST_DB0_MASK (0xFFFFFFFFU)
46235#define IEE_AES_TST_DB_AES_TST_DB0_SHIFT (0U)
46236#define IEE_AES_TST_DB_AES_TST_DB0(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB0_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB0_MASK)
46237
46238#define IEE_AES_TST_DB_AES_TST_DB1_MASK (0xFFFFFFFFU)
46239#define IEE_AES_TST_DB_AES_TST_DB1_SHIFT (0U)
46240#define IEE_AES_TST_DB_AES_TST_DB1(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB1_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB1_MASK)
46241
46242#define IEE_AES_TST_DB_AES_TST_DB2_MASK (0xFFFFFFFFU)
46243#define IEE_AES_TST_DB_AES_TST_DB2_SHIFT (0U)
46244#define IEE_AES_TST_DB_AES_TST_DB2(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB2_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB2_MASK)
46245
46246#define IEE_AES_TST_DB_AES_TST_DB3_MASK (0xFFFFFFFFU)
46247#define IEE_AES_TST_DB_AES_TST_DB3_SHIFT (0U)
46248#define IEE_AES_TST_DB_AES_TST_DB3(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB3_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB3_MASK)
46249
46250#define IEE_AES_TST_DB_AES_TST_DB4_MASK (0xFFFFFFFFU)
46251#define IEE_AES_TST_DB_AES_TST_DB4_SHIFT (0U)
46252#define IEE_AES_TST_DB_AES_TST_DB4(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB4_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB4_MASK)
46253
46254#define IEE_AES_TST_DB_AES_TST_DB5_MASK (0xFFFFFFFFU)
46255#define IEE_AES_TST_DB_AES_TST_DB5_SHIFT (0U)
46256#define IEE_AES_TST_DB_AES_TST_DB5(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB5_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB5_MASK)
46257
46258#define IEE_AES_TST_DB_AES_TST_DB6_MASK (0xFFFFFFFFU)
46259#define IEE_AES_TST_DB_AES_TST_DB6_SHIFT (0U)
46260#define IEE_AES_TST_DB_AES_TST_DB6(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB6_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB6_MASK)
46261
46262#define IEE_AES_TST_DB_AES_TST_DB7_MASK (0xFFFFFFFFU)
46263#define IEE_AES_TST_DB_AES_TST_DB7_SHIFT (0U)
46264#define IEE_AES_TST_DB_AES_TST_DB7(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB7_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB7_MASK)
46265
46266#define IEE_AES_TST_DB_AES_TST_DB8_MASK (0xFFFFFFFFU)
46267#define IEE_AES_TST_DB_AES_TST_DB8_SHIFT (0U)
46268#define IEE_AES_TST_DB_AES_TST_DB8(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB8_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB8_MASK)
46269
46270#define IEE_AES_TST_DB_AES_TST_DB9_MASK (0xFFFFFFFFU)
46271#define IEE_AES_TST_DB_AES_TST_DB9_SHIFT (0U)
46272#define IEE_AES_TST_DB_AES_TST_DB9(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB9_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB9_MASK)
46273
46274#define IEE_AES_TST_DB_AES_TST_DB10_MASK (0xFFFFFFFFU)
46275#define IEE_AES_TST_DB_AES_TST_DB10_SHIFT (0U)
46276#define IEE_AES_TST_DB_AES_TST_DB10(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB10_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB10_MASK)
46277
46278#define IEE_AES_TST_DB_AES_TST_DB11_MASK (0xFFFFFFFFU)
46279#define IEE_AES_TST_DB_AES_TST_DB11_SHIFT (0U)
46280#define IEE_AES_TST_DB_AES_TST_DB11(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB11_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB11_MASK)
46281
46282#define IEE_AES_TST_DB_AES_TST_DB12_MASK (0xFFFFFFFFU)
46283#define IEE_AES_TST_DB_AES_TST_DB12_SHIFT (0U)
46284#define IEE_AES_TST_DB_AES_TST_DB12(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB12_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB12_MASK)
46285
46286#define IEE_AES_TST_DB_AES_TST_DB13_MASK (0xFFFFFFFFU)
46287#define IEE_AES_TST_DB_AES_TST_DB13_SHIFT (0U)
46288#define IEE_AES_TST_DB_AES_TST_DB13(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB13_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB13_MASK)
46289
46290#define IEE_AES_TST_DB_AES_TST_DB14_MASK (0xFFFFFFFFU)
46291#define IEE_AES_TST_DB_AES_TST_DB14_SHIFT (0U)
46292#define IEE_AES_TST_DB_AES_TST_DB14(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB14_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB14_MASK)
46293
46294#define IEE_AES_TST_DB_AES_TST_DB15_MASK (0xFFFFFFFFU)
46295#define IEE_AES_TST_DB_AES_TST_DB15_SHIFT (0U)
46296#define IEE_AES_TST_DB_AES_TST_DB15(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB15_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB15_MASK)
46297
46298#define IEE_AES_TST_DB_AES_TST_DB16_MASK (0xFFFFFFFFU)
46299#define IEE_AES_TST_DB_AES_TST_DB16_SHIFT (0U)
46300#define IEE_AES_TST_DB_AES_TST_DB16(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB16_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB16_MASK)
46301
46302#define IEE_AES_TST_DB_AES_TST_DB17_MASK (0xFFFFFFFFU)
46303#define IEE_AES_TST_DB_AES_TST_DB17_SHIFT (0U)
46304#define IEE_AES_TST_DB_AES_TST_DB17(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB17_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB17_MASK)
46305
46306#define IEE_AES_TST_DB_AES_TST_DB18_MASK (0xFFFFFFFFU)
46307#define IEE_AES_TST_DB_AES_TST_DB18_SHIFT (0U)
46308#define IEE_AES_TST_DB_AES_TST_DB18(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB18_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB18_MASK)
46309
46310#define IEE_AES_TST_DB_AES_TST_DB19_MASK (0xFFFFFFFFU)
46311#define IEE_AES_TST_DB_AES_TST_DB19_SHIFT (0U)
46312#define IEE_AES_TST_DB_AES_TST_DB19(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB19_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB19_MASK)
46313
46314#define IEE_AES_TST_DB_AES_TST_DB20_MASK (0xFFFFFFFFU)
46315#define IEE_AES_TST_DB_AES_TST_DB20_SHIFT (0U)
46316#define IEE_AES_TST_DB_AES_TST_DB20(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB20_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB20_MASK)
46317
46318#define IEE_AES_TST_DB_AES_TST_DB21_MASK (0xFFFFFFFFU)
46319#define IEE_AES_TST_DB_AES_TST_DB21_SHIFT (0U)
46320#define IEE_AES_TST_DB_AES_TST_DB21(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB21_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB21_MASK)
46321
46322#define IEE_AES_TST_DB_AES_TST_DB22_MASK (0xFFFFFFFFU)
46323#define IEE_AES_TST_DB_AES_TST_DB22_SHIFT (0U)
46324#define IEE_AES_TST_DB_AES_TST_DB22(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB22_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB22_MASK)
46325
46326#define IEE_AES_TST_DB_AES_TST_DB23_MASK (0xFFFFFFFFU)
46327#define IEE_AES_TST_DB_AES_TST_DB23_SHIFT (0U)
46328#define IEE_AES_TST_DB_AES_TST_DB23(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB23_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB23_MASK)
46329
46330#define IEE_AES_TST_DB_AES_TST_DB24_MASK (0xFFFFFFFFU)
46331#define IEE_AES_TST_DB_AES_TST_DB24_SHIFT (0U)
46332#define IEE_AES_TST_DB_AES_TST_DB24(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB24_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB24_MASK)
46333
46334#define IEE_AES_TST_DB_AES_TST_DB25_MASK (0xFFFFFFFFU)
46335#define IEE_AES_TST_DB_AES_TST_DB25_SHIFT (0U)
46336#define IEE_AES_TST_DB_AES_TST_DB25(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB25_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB25_MASK)
46337
46338#define IEE_AES_TST_DB_AES_TST_DB26_MASK (0xFFFFFFFFU)
46339#define IEE_AES_TST_DB_AES_TST_DB26_SHIFT (0U)
46340#define IEE_AES_TST_DB_AES_TST_DB26(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB26_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB26_MASK)
46341
46342#define IEE_AES_TST_DB_AES_TST_DB27_MASK (0xFFFFFFFFU)
46343#define IEE_AES_TST_DB_AES_TST_DB27_SHIFT (0U)
46344#define IEE_AES_TST_DB_AES_TST_DB27(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB27_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB27_MASK)
46345
46346#define IEE_AES_TST_DB_AES_TST_DB28_MASK (0xFFFFFFFFU)
46347#define IEE_AES_TST_DB_AES_TST_DB28_SHIFT (0U)
46348#define IEE_AES_TST_DB_AES_TST_DB28(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB28_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB28_MASK)
46349
46350#define IEE_AES_TST_DB_AES_TST_DB29_MASK (0xFFFFFFFFU)
46351#define IEE_AES_TST_DB_AES_TST_DB29_SHIFT (0U)
46352#define IEE_AES_TST_DB_AES_TST_DB29(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB29_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB29_MASK)
46353
46354#define IEE_AES_TST_DB_AES_TST_DB30_MASK (0xFFFFFFFFU)
46355#define IEE_AES_TST_DB_AES_TST_DB30_SHIFT (0U)
46356#define IEE_AES_TST_DB_AES_TST_DB30(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB30_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB30_MASK)
46357
46358#define IEE_AES_TST_DB_AES_TST_DB31_MASK (0xFFFFFFFFU)
46359#define IEE_AES_TST_DB_AES_TST_DB31_SHIFT (0U)
46360#define IEE_AES_TST_DB_AES_TST_DB31(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB31_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB31_MASK)
46363/* The count of IEE_AES_TST_DB */
46364#define IEE_AES_TST_DB_COUNT (32U)
46365
46366 /* end of group IEE_Register_Masks */
46370
46371
46372/* IEE - Peripheral instance base addresses */
46374#define IEE__IEE_RT1170_BASE (0x4006C000u)
46376#define IEE__IEE_RT1170 ((IEE_Type *)IEE__IEE_RT1170_BASE)
46378#define IEE_BASE_ADDRS { IEE__IEE_RT1170_BASE }
46380#define IEE_BASE_PTRS { IEE__IEE_RT1170 }
46381 /* end of group IEE_Peripheral_Access_Layer */
46385
46386
46387/* ----------------------------------------------------------------------------
46388 -- IEE_APC Peripheral Access Layer
46389 ---------------------------------------------------------------------------- */
46390
46397typedef struct {
46398 __IO uint32_t REGION0_TOP_ADDR;
46399 __IO uint32_t REGION0_BOT_ADDR;
46400 __IO uint32_t REGION0_RDC_D0;
46401 __IO uint32_t REGION0_RDC_D1;
46402 __IO uint32_t REGION1_TOP_ADDR;
46403 __IO uint32_t REGION1_BOT_ADDR;
46404 __IO uint32_t REGION1_RDC_D0;
46405 __IO uint32_t REGION1_RDC_D1;
46406 __IO uint32_t REGION2_TOP_ADDR;
46407 __IO uint32_t REGION2_BOT_ADDR;
46408 __IO uint32_t REGION2_RDC_D0;
46409 __IO uint32_t REGION2_RDC_D1;
46410 __IO uint32_t REGION3_TOP_ADDR;
46411 __IO uint32_t REGION3_BOT_ADDR;
46412 __IO uint32_t REGION3_RDC_D0;
46413 __IO uint32_t REGION3_RDC_D1;
46414 __IO uint32_t REGION4_TOP_ADDR;
46415 __IO uint32_t REGION4_BOT_ADDR;
46416 __IO uint32_t REGION4_RDC_D0;
46417 __IO uint32_t REGION4_RDC_D1;
46418 __IO uint32_t REGION5_TOP_ADDR;
46419 __IO uint32_t REGION5_BOT_ADDR;
46420 __IO uint32_t REGION5_RDC_D0;
46421 __IO uint32_t REGION5_RDC_D1;
46422 __IO uint32_t REGION6_TOP_ADDR;
46423 __IO uint32_t REGION6_BOT_ADDR;
46424 __IO uint32_t REGION6_RDC_D0;
46425 __IO uint32_t REGION6_RDC_D1;
46426 __IO uint32_t REGION7_TOP_ADDR;
46427 __IO uint32_t REGION7_BOT_ADDR;
46428 __IO uint32_t REGION7_RDC_D0;
46429 __IO uint32_t REGION7_RDC_D1;
46430} IEE_APC_Type;
46431
46432/* ----------------------------------------------------------------------------
46433 -- IEE_APC Register Masks
46434 ---------------------------------------------------------------------------- */
46435
46444#define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
46445#define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT (0U)
46448#define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK)
46454#define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
46455#define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT (0U)
46458#define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK)
46464#define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
46465#define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
46470#define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK)
46471
46472#define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
46473#define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
46478#define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK)
46484#define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
46485#define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
46490#define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK)
46491
46492#define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
46493#define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
46498#define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK)
46504#define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
46505#define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT (0U)
46508#define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK)
46514#define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
46515#define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT (0U)
46518#define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK)
46524#define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
46525#define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
46530#define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK)
46531
46532#define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
46533#define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
46538#define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK)
46544#define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
46545#define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
46550#define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK)
46551
46552#define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
46553#define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
46558#define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK)
46564#define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
46565#define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT (0U)
46568#define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK)
46574#define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
46575#define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT (0U)
46578#define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK)
46584#define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
46585#define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
46590#define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK)
46591
46592#define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
46593#define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
46598#define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK)
46604#define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
46605#define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
46610#define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK)
46611
46612#define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
46613#define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
46618#define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK)
46624#define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
46625#define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT (0U)
46628#define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK)
46634#define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
46635#define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT (0U)
46638#define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK)
46644#define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
46645#define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
46650#define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK)
46651
46652#define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
46653#define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
46658#define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK)
46664#define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
46665#define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
46670#define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK)
46671
46672#define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
46673#define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
46678#define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK)
46684#define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
46685#define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT (0U)
46688#define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK)
46694#define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
46695#define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT (0U)
46698#define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK)
46704#define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
46705#define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
46710#define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK)
46711
46712#define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
46713#define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
46718#define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK)
46724#define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
46725#define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
46730#define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK)
46731
46732#define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
46733#define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
46738#define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK)
46744#define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
46745#define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT (0U)
46748#define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK)
46754#define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
46755#define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT (0U)
46758#define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK)
46764#define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
46765#define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
46770#define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK)
46771
46772#define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
46773#define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
46778#define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK)
46784#define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
46785#define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
46790#define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK)
46791
46792#define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
46793#define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
46798#define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK)
46804#define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
46805#define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT (0U)
46808#define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK)
46814#define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
46815#define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT (0U)
46818#define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK)
46824#define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
46825#define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
46830#define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK)
46831
46832#define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
46833#define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
46838#define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK)
46844#define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
46845#define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
46850#define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK)
46851
46852#define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
46853#define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
46858#define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK)
46864#define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
46865#define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT (0U)
46868#define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK)
46874#define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
46875#define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT (0U)
46878#define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK)
46884#define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
46885#define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
46890#define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK)
46891
46892#define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
46893#define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
46898#define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK)
46904#define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
46905#define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
46910#define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK)
46911
46912#define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
46913#define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
46918#define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK) /* end of group IEE_APC_Register_Masks */
46925
46926
46927/* IEE_APC - Peripheral instance base addresses */
46929#define IEE_APC_BASE (0x40068000u)
46931#define IEE_APC ((IEE_APC_Type *)IEE_APC_BASE)
46933#define IEE_APC_BASE_ADDRS { IEE_APC_BASE }
46935#define IEE_APC_BASE_PTRS { IEE_APC }
46936 /* end of group IEE_APC_Peripheral_Access_Layer */
46940
46941
46942/* ----------------------------------------------------------------------------
46943 -- IOMUXC Peripheral Access Layer
46944 ---------------------------------------------------------------------------- */
46945
46952typedef struct {
46953 uint8_t RESERVED_0[16];
46954 __IO uint32_t SW_MUX_CTL_PAD[145];
46955 __IO uint32_t SW_PAD_CTL_PAD[145];
46956 __IO uint32_t SELECT_INPUT[160];
46957} IOMUXC_Type;
46958
46959/* ----------------------------------------------------------------------------
46960 -- IOMUXC Register Masks
46961 ---------------------------------------------------------------------------- */
46962
46971#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU)
46972#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
46987#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
46988
46989#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
46990#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
46995#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
46998/* The count of IOMUXC_SW_MUX_CTL_PAD */
46999#define IOMUXC_SW_MUX_CTL_PAD_COUNT (145U)
47000
47004#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)
47005#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)
47010#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
47011
47012#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x2U)
47013#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (1U)
47018#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
47019
47020#define IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK (0x2U)
47021#define IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT (1U)
47026#define IOMUXC_SW_PAD_CTL_PAD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK)
47027
47028#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x4U)
47029#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (2U)
47034#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
47035
47036#define IOMUXC_SW_PAD_CTL_PAD_PULL_MASK (0xCU)
47037#define IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT (2U)
47044#define IOMUXC_SW_PAD_CTL_PAD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PULL_MASK)
47045
47046#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0x8U)
47047#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (3U)
47052#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
47053
47054#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x10U)
47055#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (4U)
47060#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
47061
47062#define IOMUXC_SW_PAD_CTL_PAD_DWP_MASK (0x30000000U)
47063#define IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT (28U)
47070#define IOMUXC_SW_PAD_CTL_PAD_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_MASK)
47071
47072#define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U)
47073#define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U)
47080#define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK)
47083/* The count of IOMUXC_SW_PAD_CTL_PAD */
47084#define IOMUXC_SW_PAD_CTL_PAD_COUNT (145U)
47085
47089#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
47090#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
47097#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
47100/* The count of IOMUXC_SELECT_INPUT */
47101#define IOMUXC_SELECT_INPUT_COUNT (160U)
47102
47103 /* end of group IOMUXC_Register_Masks */
47107
47108
47109/* IOMUXC - Peripheral instance base addresses */
47111#define IOMUXC_BASE (0x400E8000u)
47113#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
47115#define IOMUXC_BASE_ADDRS { IOMUXC_BASE }
47117#define IOMUXC_BASE_PTRS { IOMUXC }
47118 /* end of group IOMUXC_Peripheral_Access_Layer */
47122
47123
47124/* ----------------------------------------------------------------------------
47125 -- IOMUXC_GPR Peripheral Access Layer
47126 ---------------------------------------------------------------------------- */
47127
47134typedef struct {
47135 __IO uint32_t GPR0;
47136 __IO uint32_t GPR1;
47137 __IO uint32_t GPR2;
47138 __IO uint32_t GPR3;
47139 __IO uint32_t GPR4;
47140 __IO uint32_t GPR5;
47141 uint8_t RESERVED_0[4];
47142 __IO uint32_t GPR7;
47143 __IO uint32_t GPR8;
47144 __IO uint32_t GPR9;
47145 __IO uint32_t GPR10;
47146 __IO uint32_t GPR11;
47147 __IO uint32_t GPR12;
47148 __IO uint32_t GPR13;
47149 __IO uint32_t GPR14;
47150 __IO uint32_t GPR15;
47151 __IO uint32_t GPR16;
47152 __IO uint32_t GPR17;
47153 __IO uint32_t GPR18;
47154 uint8_t RESERVED_1[4];
47155 __IO uint32_t GPR20;
47156 __IO uint32_t GPR21;
47157 __IO uint32_t GPR22;
47158 __IO uint32_t GPR23;
47159 __IO uint32_t GPR24;
47160 __IO uint32_t GPR25;
47161 __IO uint32_t GPR26;
47162 __IO uint32_t GPR27;
47163 __IO uint32_t GPR28;
47164 __IO uint32_t GPR29;
47165 __IO uint32_t GPR30;
47166 __IO uint32_t GPR31;
47167 __IO uint32_t GPR32;
47168 __IO uint32_t GPR33;
47169 __IO uint32_t GPR34;
47170 __IO uint32_t GPR35;
47171 __IO uint32_t GPR36;
47172 __IO uint32_t GPR37;
47173 __IO uint32_t GPR38;
47174 __IO uint32_t GPR39;
47175 __IO uint32_t GPR40;
47176 __IO uint32_t GPR41;
47177 __IO uint32_t GPR42;
47178 __IO uint32_t GPR43;
47179 __IO uint32_t GPR44;
47180 __IO uint32_t GPR45;
47181 __IO uint32_t GPR46;
47182 __IO uint32_t GPR47;
47183 __IO uint32_t GPR48;
47184 __IO uint32_t GPR49;
47185 __IO uint32_t GPR50;
47186 __IO uint32_t GPR51;
47187 __IO uint32_t GPR52;
47188 __IO uint32_t GPR53;
47189 __IO uint32_t GPR54;
47190 __IO uint32_t GPR55;
47191 uint8_t RESERVED_2[12];
47192 __IO uint32_t GPR59;
47193 uint8_t RESERVED_3[8];
47194 __IO uint32_t GPR62;
47195 __I uint32_t GPR63;
47196 __IO uint32_t GPR64;
47197 __IO uint32_t GPR65;
47198 __IO uint32_t GPR66;
47199 __IO uint32_t GPR67;
47200 __IO uint32_t GPR68;
47201 __IO uint32_t GPR69;
47202 __IO uint32_t GPR70;
47203 __IO uint32_t GPR71;
47204 __IO uint32_t GPR72;
47205 __IO uint32_t GPR73;
47206 __IO uint32_t GPR74;
47207 __I uint32_t GPR75;
47208 __I uint32_t GPR76;
47210
47211/* ----------------------------------------------------------------------------
47212 -- IOMUXC_GPR Register Masks
47213 ---------------------------------------------------------------------------- */
47214
47223#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U)
47224#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT (0U)
47227#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
47228
47229#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK (0x38U)
47230#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT (3U)
47233#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK)
47234
47235#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK (0xC0U)
47236#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT (6U)
47239#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK)
47240
47241#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK (0x100U)
47242#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT (8U)
47245#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK)
47246
47247#define IOMUXC_GPR_GPR0_DWP_MASK (0x30000000U)
47248#define IOMUXC_GPR_GPR0_DWP_SHIFT (28U)
47255#define IOMUXC_GPR_GPR0_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_SHIFT)) & IOMUXC_GPR_GPR0_DWP_MASK)
47256
47257#define IOMUXC_GPR_GPR0_DWP_LOCK_MASK (0xC0000000U)
47258#define IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT (30U)
47265#define IOMUXC_GPR_GPR0_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR0_DWP_LOCK_MASK)
47271#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x3U)
47272#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (0U)
47275#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
47276
47277#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100U)
47278#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (8U)
47281#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
47282
47283#define IOMUXC_GPR_GPR1_DWP_MASK (0x30000000U)
47284#define IOMUXC_GPR_GPR1_DWP_SHIFT (28U)
47291#define IOMUXC_GPR_GPR1_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_SHIFT)) & IOMUXC_GPR_GPR1_DWP_MASK)
47292
47293#define IOMUXC_GPR_GPR1_DWP_LOCK_MASK (0xC0000000U)
47294#define IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT (30U)
47301#define IOMUXC_GPR_GPR1_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_DWP_LOCK_MASK)
47307#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK (0x3U)
47308#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT (0U)
47311#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK)
47312
47313#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK (0x100U)
47314#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT (8U)
47317#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK)
47318
47319#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK (0x200U)
47320#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT (9U)
47323#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK)
47324
47325#define IOMUXC_GPR_GPR2_DWP_MASK (0x30000000U)
47326#define IOMUXC_GPR_GPR2_DWP_SHIFT (28U)
47333#define IOMUXC_GPR_GPR2_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_SHIFT)) & IOMUXC_GPR_GPR2_DWP_MASK)
47334
47335#define IOMUXC_GPR_GPR2_DWP_LOCK_MASK (0xC0000000U)
47336#define IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT (30U)
47343#define IOMUXC_GPR_GPR2_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR2_DWP_LOCK_MASK)
47349#define IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK (0xFFU)
47350#define IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT (0U)
47353#define IOMUXC_GPR_GPR3_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK)
47354
47355#define IOMUXC_GPR_GPR3_MQS_SW_RST_MASK (0x100U)
47356#define IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT (8U)
47359#define IOMUXC_GPR_GPR3_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR3_MQS_SW_RST_MASK)
47360
47361#define IOMUXC_GPR_GPR3_MQS_EN_MASK (0x200U)
47362#define IOMUXC_GPR_GPR3_MQS_EN_SHIFT (9U)
47365#define IOMUXC_GPR_GPR3_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR3_MQS_EN_MASK)
47366
47367#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK (0x400U)
47368#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT (10U)
47371#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK)
47372
47373#define IOMUXC_GPR_GPR3_DWP_MASK (0x30000000U)
47374#define IOMUXC_GPR_GPR3_DWP_SHIFT (28U)
47381#define IOMUXC_GPR_GPR3_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_SHIFT)) & IOMUXC_GPR_GPR3_DWP_MASK)
47382
47383#define IOMUXC_GPR_GPR3_DWP_LOCK_MASK (0xC0000000U)
47384#define IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT (30U)
47391#define IOMUXC_GPR_GPR3_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR3_DWP_LOCK_MASK)
47397#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK (0x1U)
47398#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT (0U)
47401#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK)
47402
47403#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK (0x2U)
47404#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT (1U)
47407#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK)
47408
47409#define IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK (0x4U)
47410#define IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT (2U)
47413#define IOMUXC_GPR_GPR4_ENET_TIME_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK)
47414
47415#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK (0x8U)
47416#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT (3U)
47419#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK)
47420
47421#define IOMUXC_GPR_GPR4_DWP_MASK (0x30000000U)
47422#define IOMUXC_GPR_GPR4_DWP_SHIFT (28U)
47429#define IOMUXC_GPR_GPR4_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_SHIFT)) & IOMUXC_GPR_GPR4_DWP_MASK)
47430
47431#define IOMUXC_GPR_GPR4_DWP_LOCK_MASK (0xC0000000U)
47432#define IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT (30U)
47439#define IOMUXC_GPR_GPR4_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR4_DWP_LOCK_MASK)
47445#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK (0x1U)
47446#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT (0U)
47449#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK)
47450
47451#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK (0x2U)
47452#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT (1U)
47455#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK)
47456
47457#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK (0x4U)
47458#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT (2U)
47461#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK)
47462
47463#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK (0x8U)
47464#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT (3U)
47467#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK)
47468
47469#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK (0x10U)
47470#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT (4U)
47473#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK)
47474
47475#define IOMUXC_GPR_GPR5_DWP_MASK (0x30000000U)
47476#define IOMUXC_GPR_GPR5_DWP_SHIFT (28U)
47483#define IOMUXC_GPR_GPR5_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_SHIFT)) & IOMUXC_GPR_GPR5_DWP_MASK)
47484
47485#define IOMUXC_GPR_GPR5_DWP_LOCK_MASK (0xC0000000U)
47486#define IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT (30U)
47493#define IOMUXC_GPR_GPR5_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR5_DWP_LOCK_MASK)
47499#define IOMUXC_GPR_GPR7_GINT_MASK (0x1U)
47500#define IOMUXC_GPR_GPR7_GINT_SHIFT (0U)
47503#define IOMUXC_GPR_GPR7_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GINT_SHIFT)) & IOMUXC_GPR_GPR7_GINT_MASK)
47504
47505#define IOMUXC_GPR_GPR7_DWP_MASK (0x30000000U)
47506#define IOMUXC_GPR_GPR7_DWP_SHIFT (28U)
47513#define IOMUXC_GPR_GPR7_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_SHIFT)) & IOMUXC_GPR_GPR7_DWP_MASK)
47514
47515#define IOMUXC_GPR_GPR7_DWP_LOCK_MASK (0xC0000000U)
47516#define IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT (30U)
47523#define IOMUXC_GPR_GPR7_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR7_DWP_LOCK_MASK)
47529#define IOMUXC_GPR_GPR8_WDOG1_MASK_MASK (0x1U)
47530#define IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT (0U)
47533#define IOMUXC_GPR_GPR8_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR8_WDOG1_MASK_MASK)
47534
47535#define IOMUXC_GPR_GPR8_DWP_MASK (0x30000000U)
47536#define IOMUXC_GPR_GPR8_DWP_SHIFT (28U)
47543#define IOMUXC_GPR_GPR8_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_SHIFT)) & IOMUXC_GPR_GPR8_DWP_MASK)
47544
47545#define IOMUXC_GPR_GPR8_DWP_LOCK_MASK (0xC0000000U)
47546#define IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT (30U)
47553#define IOMUXC_GPR_GPR8_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR8_DWP_LOCK_MASK)
47559#define IOMUXC_GPR_GPR9_WDOG2_MASK_MASK (0x1U)
47560#define IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT (0U)
47563#define IOMUXC_GPR_GPR9_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR9_WDOG2_MASK_MASK)
47564
47565#define IOMUXC_GPR_GPR9_DWP_MASK (0x30000000U)
47566#define IOMUXC_GPR_GPR9_DWP_SHIFT (28U)
47573#define IOMUXC_GPR_GPR9_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_SHIFT)) & IOMUXC_GPR_GPR9_DWP_MASK)
47574
47575#define IOMUXC_GPR_GPR9_DWP_LOCK_MASK (0xC0000000U)
47576#define IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT (30U)
47583#define IOMUXC_GPR_GPR9_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR9_DWP_LOCK_MASK)
47589#define IOMUXC_GPR_GPR10_DWP_MASK (0x30000000U)
47590#define IOMUXC_GPR_GPR10_DWP_SHIFT (28U)
47597#define IOMUXC_GPR_GPR10_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_SHIFT)) & IOMUXC_GPR_GPR10_DWP_MASK)
47598
47599#define IOMUXC_GPR_GPR10_DWP_LOCK_MASK (0xC0000000U)
47600#define IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT (30U)
47607#define IOMUXC_GPR_GPR10_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR10_DWP_LOCK_MASK)
47613#define IOMUXC_GPR_GPR11_DWP_MASK (0x30000000U)
47614#define IOMUXC_GPR_GPR11_DWP_SHIFT (28U)
47621#define IOMUXC_GPR_GPR11_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_SHIFT)) & IOMUXC_GPR_GPR11_DWP_MASK)
47622
47623#define IOMUXC_GPR_GPR11_DWP_LOCK_MASK (0xC0000000U)
47624#define IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT (30U)
47631#define IOMUXC_GPR_GPR11_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR11_DWP_LOCK_MASK)
47637#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK (0x1U)
47638#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT (0U)
47641#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK)
47642
47643#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK (0x100U)
47644#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT (8U)
47647#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK)
47648
47649#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK (0x200U)
47650#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT (9U)
47653#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK)
47654
47655#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK (0x400U)
47656#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT (10U)
47659#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK)
47660
47661#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK (0x800U)
47662#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT (11U)
47665#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK)
47666
47667#define IOMUXC_GPR_GPR12_DWP_MASK (0x30000000U)
47668#define IOMUXC_GPR_GPR12_DWP_SHIFT (28U)
47675#define IOMUXC_GPR_GPR12_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_SHIFT)) & IOMUXC_GPR_GPR12_DWP_MASK)
47676
47677#define IOMUXC_GPR_GPR12_DWP_LOCK_MASK (0xC0000000U)
47678#define IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT (30U)
47685#define IOMUXC_GPR_GPR12_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR12_DWP_LOCK_MASK)
47691#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK (0x1U)
47692#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT (0U)
47695#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK)
47696
47697#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK (0x100U)
47698#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT (8U)
47701#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK)
47702
47703#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK (0x200U)
47704#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT (9U)
47707#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK)
47708
47709#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK (0x400U)
47710#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT (10U)
47713#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK)
47714
47715#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK (0x800U)
47716#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT (11U)
47719#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK)
47720
47721#define IOMUXC_GPR_GPR13_DWP_MASK (0x30000000U)
47722#define IOMUXC_GPR_GPR13_DWP_SHIFT (28U)
47729#define IOMUXC_GPR_GPR13_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_SHIFT)) & IOMUXC_GPR_GPR13_DWP_MASK)
47730
47731#define IOMUXC_GPR_GPR13_DWP_LOCK_MASK (0xC0000000U)
47732#define IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT (30U)
47739#define IOMUXC_GPR_GPR13_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR13_DWP_LOCK_MASK)
47745#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK (0x1U)
47746#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT (0U)
47749#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK)
47750
47751#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
47752#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
47755#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK)
47756
47757#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
47758#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
47761#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK)
47762
47763#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
47764#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
47767#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK)
47768
47769#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
47770#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
47773#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK)
47774
47775#define IOMUXC_GPR_GPR14_DWP_MASK (0x30000000U)
47776#define IOMUXC_GPR_GPR14_DWP_SHIFT (28U)
47783#define IOMUXC_GPR_GPR14_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_SHIFT)) & IOMUXC_GPR_GPR14_DWP_MASK)
47784
47785#define IOMUXC_GPR_GPR14_DWP_LOCK_MASK (0xC0000000U)
47786#define IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT (30U)
47793#define IOMUXC_GPR_GPR14_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR14_DWP_LOCK_MASK)
47799#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK (0x1U)
47800#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT (0U)
47803#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK)
47804
47805#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK (0x100U)
47806#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT (8U)
47809#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK)
47810
47811#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK (0x200U)
47812#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT (9U)
47815#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK)
47816
47817#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK (0x400U)
47818#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT (10U)
47821#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK)
47822
47823#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK (0x800U)
47824#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT (11U)
47827#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK)
47828
47829#define IOMUXC_GPR_GPR15_DWP_MASK (0x30000000U)
47830#define IOMUXC_GPR_GPR15_DWP_SHIFT (28U)
47837#define IOMUXC_GPR_GPR15_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_SHIFT)) & IOMUXC_GPR_GPR15_DWP_MASK)
47838
47839#define IOMUXC_GPR_GPR15_DWP_LOCK_MASK (0xC0000000U)
47840#define IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT (30U)
47847#define IOMUXC_GPR_GPR15_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR15_DWP_LOCK_MASK)
47853#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
47854#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
47857#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
47858
47859#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK (0x8U)
47860#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT (3U)
47863#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK)
47864
47865#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK (0x20U)
47866#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT (5U)
47869#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK)
47870
47871#define IOMUXC_GPR_GPR16_DWP_MASK (0x30000000U)
47872#define IOMUXC_GPR_GPR16_DWP_SHIFT (28U)
47879#define IOMUXC_GPR_GPR16_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_SHIFT)) & IOMUXC_GPR_GPR16_DWP_MASK)
47880
47881#define IOMUXC_GPR_GPR16_DWP_LOCK_MASK (0xC0000000U)
47882#define IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT (30U)
47889#define IOMUXC_GPR_GPR16_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR16_DWP_LOCK_MASK)
47895#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK (0xFFFFU)
47896#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT (0U)
47899#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK)
47900
47901#define IOMUXC_GPR_GPR17_DWP_MASK (0x30000000U)
47902#define IOMUXC_GPR_GPR17_DWP_SHIFT (28U)
47909#define IOMUXC_GPR_GPR17_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_SHIFT)) & IOMUXC_GPR_GPR17_DWP_MASK)
47910
47911#define IOMUXC_GPR_GPR17_DWP_LOCK_MASK (0xC0000000U)
47912#define IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT (30U)
47919#define IOMUXC_GPR_GPR17_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR17_DWP_LOCK_MASK)
47925#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK (0xFFFFU)
47926#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT (0U)
47929#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT)) & IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK)
47930
47931#define IOMUXC_GPR_GPR18_DWP_MASK (0x30000000U)
47932#define IOMUXC_GPR_GPR18_DWP_SHIFT (28U)
47939#define IOMUXC_GPR_GPR18_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_SHIFT)) & IOMUXC_GPR_GPR18_DWP_MASK)
47940
47941#define IOMUXC_GPR_GPR18_DWP_LOCK_MASK (0xC0000000U)
47942#define IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT (30U)
47949#define IOMUXC_GPR_GPR18_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR18_DWP_LOCK_MASK)
47955#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK (0x1U)
47956#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT (0U)
47959#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK)
47960
47961#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK (0x2U)
47962#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT (1U)
47965#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK)
47966
47967#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK (0x4U)
47968#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT (2U)
47971#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK)
47972
47973#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK (0x8U)
47974#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT (3U)
47977#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK)
47978
47979#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK (0x10U)
47980#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT (4U)
47983#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK)
47984
47985#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK (0x20U)
47986#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT (5U)
47989#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK)
47990
47991#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK (0x40U)
47992#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT (6U)
47995#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK)
47996
47997#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK (0x80U)
47998#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT (7U)
48001#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK)
48002
48003#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK (0x100U)
48004#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT (8U)
48007#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK)
48008
48009#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK (0x200U)
48010#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT (9U)
48013#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK)
48014
48015#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK (0x400U)
48016#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT (10U)
48019#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK)
48020
48021#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK (0x800U)
48022#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT (11U)
48025#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK)
48026
48027#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK (0x1000U)
48028#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT (12U)
48031#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK)
48032
48033#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK (0x2000U)
48034#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT (13U)
48037#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK)
48038
48039#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK (0x4000U)
48040#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT (14U)
48043#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK)
48044
48045#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK (0x8000U)
48046#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT (15U)
48049#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK)
48050
48051#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK (0x10000U)
48052#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT (16U)
48055#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK)
48056
48057#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK (0x20000U)
48058#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT (17U)
48061#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK)
48062
48063#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK (0x40000U)
48064#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT (18U)
48067#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK)
48068
48069#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK (0x80000U)
48070#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT (19U)
48073#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK)
48074
48075#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK (0x100000U)
48076#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT (20U)
48079#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK)
48080
48081#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK (0x200000U)
48082#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT (21U)
48085#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK)
48086
48087#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK (0x400000U)
48088#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT (22U)
48091#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK)
48092
48093#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK (0x800000U)
48094#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT (23U)
48097#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK)
48098
48099#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK (0x1000000U)
48100#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT (24U)
48103#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK)
48104
48105#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK (0x2000000U)
48106#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT (25U)
48109#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK)
48110
48111#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK (0x4000000U)
48112#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT (26U)
48115#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK)
48116
48117#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK (0x8000000U)
48118#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT (27U)
48121#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK)
48122
48123#define IOMUXC_GPR_GPR20_DWP_MASK (0x30000000U)
48124#define IOMUXC_GPR_GPR20_DWP_SHIFT (28U)
48131#define IOMUXC_GPR_GPR20_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_SHIFT)) & IOMUXC_GPR_GPR20_DWP_MASK)
48132
48133#define IOMUXC_GPR_GPR20_DWP_LOCK_MASK (0xC0000000U)
48134#define IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT (30U)
48141#define IOMUXC_GPR_GPR20_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR20_DWP_LOCK_MASK)
48147#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK (0x1U)
48148#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT (0U)
48151#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK)
48152
48153#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK (0x2U)
48154#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT (1U)
48157#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK)
48158
48159#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK (0x4U)
48160#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT (2U)
48163#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK)
48164
48165#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK (0x8U)
48166#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT (3U)
48169#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK)
48170
48171#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK (0x10U)
48172#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT (4U)
48175#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK)
48176
48177#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK (0x20U)
48178#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT (5U)
48181#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK)
48182
48183#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK (0x40U)
48184#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT (6U)
48187#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK)
48188
48189#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK (0x80U)
48190#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT (7U)
48193#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK)
48194
48195#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK (0x100U)
48196#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT (8U)
48199#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK)
48200
48201#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK (0x200U)
48202#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT (9U)
48205#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK)
48206
48207#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK (0x400U)
48208#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT (10U)
48211#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK)
48212
48213#define IOMUXC_GPR_GPR21_DWP_MASK (0x30000000U)
48214#define IOMUXC_GPR_GPR21_DWP_SHIFT (28U)
48221#define IOMUXC_GPR_GPR21_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_SHIFT)) & IOMUXC_GPR_GPR21_DWP_MASK)
48222
48223#define IOMUXC_GPR_GPR21_DWP_LOCK_MASK (0xC0000000U)
48224#define IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT (30U)
48231#define IOMUXC_GPR_GPR21_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR21_DWP_LOCK_MASK)
48237#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK (0x1U)
48238#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT (0U)
48241#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK)
48242
48243#define IOMUXC_GPR_GPR22_DWP_MASK (0x30000000U)
48244#define IOMUXC_GPR_GPR22_DWP_SHIFT (28U)
48251#define IOMUXC_GPR_GPR22_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_SHIFT)) & IOMUXC_GPR_GPR22_DWP_MASK)
48252
48253#define IOMUXC_GPR_GPR22_DWP_LOCK_MASK (0xC0000000U)
48254#define IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT (30U)
48261#define IOMUXC_GPR_GPR22_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR22_DWP_LOCK_MASK)
48267#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK (0x1U)
48268#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT (0U)
48271#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK)
48272
48273#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK (0x2U)
48274#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT (1U)
48277#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK)
48278
48279#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK (0x4U)
48280#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT (2U)
48283#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK)
48284
48285#define IOMUXC_GPR_GPR23_DWP_MASK (0x30000000U)
48286#define IOMUXC_GPR_GPR23_DWP_SHIFT (28U)
48293#define IOMUXC_GPR_GPR23_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_SHIFT)) & IOMUXC_GPR_GPR23_DWP_MASK)
48294
48295#define IOMUXC_GPR_GPR23_DWP_LOCK_MASK (0xC0000000U)
48296#define IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT (30U)
48303#define IOMUXC_GPR_GPR23_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR23_DWP_LOCK_MASK)
48309#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK (0x1U)
48310#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT (0U)
48313#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT)) & IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK)
48314
48315#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK (0x2U)
48316#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT (1U)
48319#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK)
48320
48321#define IOMUXC_GPR_GPR24_DWP_MASK (0x30000000U)
48322#define IOMUXC_GPR_GPR24_DWP_SHIFT (28U)
48329#define IOMUXC_GPR_GPR24_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_SHIFT)) & IOMUXC_GPR_GPR24_DWP_MASK)
48330
48331#define IOMUXC_GPR_GPR24_DWP_LOCK_MASK (0xC0000000U)
48332#define IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT (30U)
48339#define IOMUXC_GPR_GPR24_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR24_DWP_LOCK_MASK)
48345#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK (0x1U)
48346#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT (0U)
48349#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT)) & IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK)
48350
48351#define IOMUXC_GPR_GPR25_DWP_MASK (0x30000000U)
48352#define IOMUXC_GPR_GPR25_DWP_SHIFT (28U)
48359#define IOMUXC_GPR_GPR25_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_SHIFT)) & IOMUXC_GPR_GPR25_DWP_MASK)
48360
48361#define IOMUXC_GPR_GPR25_DWP_LOCK_MASK (0xC0000000U)
48362#define IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT (30U)
48369#define IOMUXC_GPR_GPR25_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR25_DWP_LOCK_MASK)
48375#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK (0x1U)
48376#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT (0U)
48379#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT)) & IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK)
48380
48381#define IOMUXC_GPR_GPR26_DWP_MASK (0x30000000U)
48382#define IOMUXC_GPR_GPR26_DWP_SHIFT (28U)
48389#define IOMUXC_GPR_GPR26_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_SHIFT)) & IOMUXC_GPR_GPR26_DWP_MASK)
48390
48391#define IOMUXC_GPR_GPR26_DWP_LOCK_MASK (0xC0000000U)
48392#define IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT (30U)
48399#define IOMUXC_GPR_GPR26_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR26_DWP_LOCK_MASK)
48405#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK (0x1U)
48406#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT (0U)
48409#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT)) & IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK)
48410
48411#define IOMUXC_GPR_GPR27_DWP_MASK (0x30000000U)
48412#define IOMUXC_GPR_GPR27_DWP_SHIFT (28U)
48419#define IOMUXC_GPR_GPR27_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_SHIFT)) & IOMUXC_GPR_GPR27_DWP_MASK)
48420
48421#define IOMUXC_GPR_GPR27_DWP_LOCK_MASK (0xC0000000U)
48422#define IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT (30U)
48429#define IOMUXC_GPR_GPR27_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR27_DWP_LOCK_MASK)
48435#define IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK (0x1U)
48436#define IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT (0U)
48439#define IOMUXC_GPR_GPR28_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK)
48440
48441#define IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK (0x2U)
48442#define IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT (1U)
48445#define IOMUXC_GPR_GPR28_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK)
48446
48447#define IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK (0x20U)
48448#define IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT (5U)
48449#define IOMUXC_GPR_GPR28_CACHE_ENET1G(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK)
48450
48451#define IOMUXC_GPR_GPR28_CACHE_ENET_MASK (0x80U)
48452#define IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT (7U)
48455#define IOMUXC_GPR_GPR28_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET_MASK)
48456
48457#define IOMUXC_GPR_GPR28_CACHE_USB_MASK (0x2000U)
48458#define IOMUXC_GPR_GPR28_CACHE_USB_SHIFT (13U)
48461#define IOMUXC_GPR_GPR28_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_USB_MASK)
48462
48463#define IOMUXC_GPR_GPR28_DWP_MASK (0x30000000U)
48464#define IOMUXC_GPR_GPR28_DWP_SHIFT (28U)
48471#define IOMUXC_GPR_GPR28_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_SHIFT)) & IOMUXC_GPR_GPR28_DWP_MASK)
48472
48473#define IOMUXC_GPR_GPR28_DWP_LOCK_MASK (0xC0000000U)
48474#define IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT (30U)
48481#define IOMUXC_GPR_GPR28_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR28_DWP_LOCK_MASK)
48487#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK (0x1U)
48488#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT (0U)
48491#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK)
48492
48493#define IOMUXC_GPR_GPR29_DWP_MASK (0x30000000U)
48494#define IOMUXC_GPR_GPR29_DWP_SHIFT (28U)
48501#define IOMUXC_GPR_GPR29_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_SHIFT)) & IOMUXC_GPR_GPR29_DWP_MASK)
48502
48503#define IOMUXC_GPR_GPR29_DWP_LOCK_MASK (0xC0000000U)
48504#define IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT (30U)
48511#define IOMUXC_GPR_GPR29_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR29_DWP_LOCK_MASK)
48517#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK (0x1U)
48518#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT (0U)
48521#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK)
48522
48523#define IOMUXC_GPR_GPR30_DWP_MASK (0x30000000U)
48524#define IOMUXC_GPR_GPR30_DWP_SHIFT (28U)
48531#define IOMUXC_GPR_GPR30_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_SHIFT)) & IOMUXC_GPR_GPR30_DWP_MASK)
48532
48533#define IOMUXC_GPR_GPR30_DWP_LOCK_MASK (0xC0000000U)
48534#define IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT (30U)
48541#define IOMUXC_GPR_GPR30_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR30_DWP_LOCK_MASK)
48547#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK (0x1U)
48548#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT (0U)
48551#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK)
48552
48553#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK (0x4U)
48554#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT (2U)
48557#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT)) & IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK)
48558
48559#define IOMUXC_GPR_GPR31_DWP_MASK (0x30000000U)
48560#define IOMUXC_GPR_GPR31_DWP_SHIFT (28U)
48567#define IOMUXC_GPR_GPR31_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_SHIFT)) & IOMUXC_GPR_GPR31_DWP_MASK)
48568
48569#define IOMUXC_GPR_GPR31_DWP_LOCK_MASK (0xC0000000U)
48570#define IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT (30U)
48577#define IOMUXC_GPR_GPR31_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR31_DWP_LOCK_MASK)
48583#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK (0x1U)
48584#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT (0U)
48587#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK)
48588
48589#define IOMUXC_GPR_GPR32_DWP_MASK (0x30000000U)
48590#define IOMUXC_GPR_GPR32_DWP_SHIFT (28U)
48597#define IOMUXC_GPR_GPR32_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_SHIFT)) & IOMUXC_GPR_GPR32_DWP_MASK)
48598
48599#define IOMUXC_GPR_GPR32_DWP_LOCK_MASK (0xC0000000U)
48600#define IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT (30U)
48607#define IOMUXC_GPR_GPR32_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR32_DWP_LOCK_MASK)
48613#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK (0x1U)
48614#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT (0U)
48617#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK)
48618
48619#define IOMUXC_GPR_GPR33_DWP_MASK (0x30000000U)
48620#define IOMUXC_GPR_GPR33_DWP_SHIFT (28U)
48627#define IOMUXC_GPR_GPR33_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_SHIFT)) & IOMUXC_GPR_GPR33_DWP_MASK)
48628
48629#define IOMUXC_GPR_GPR33_DWP_LOCK_MASK (0xC0000000U)
48630#define IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT (30U)
48637#define IOMUXC_GPR_GPR33_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR33_DWP_LOCK_MASK)
48643#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK (0x1U)
48644#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT (0U)
48647#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK)
48648
48649#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK (0x2U)
48650#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT (1U)
48653#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK)
48654
48655#define IOMUXC_GPR_GPR34_DWP_MASK (0x30000000U)
48656#define IOMUXC_GPR_GPR34_DWP_SHIFT (28U)
48663#define IOMUXC_GPR_GPR34_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_SHIFT)) & IOMUXC_GPR_GPR34_DWP_MASK)
48664
48665#define IOMUXC_GPR_GPR34_DWP_LOCK_MASK (0xC0000000U)
48666#define IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT (30U)
48673#define IOMUXC_GPR_GPR34_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR34_DWP_LOCK_MASK)
48679#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK (0x1U)
48680#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT (0U)
48683#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK)
48684
48685#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK (0x2U)
48686#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT (1U)
48689#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK)
48690
48691#define IOMUXC_GPR_GPR35_DWP_MASK (0x30000000U)
48692#define IOMUXC_GPR_GPR35_DWP_SHIFT (28U)
48699#define IOMUXC_GPR_GPR35_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_SHIFT)) & IOMUXC_GPR_GPR35_DWP_MASK)
48700
48701#define IOMUXC_GPR_GPR35_DWP_LOCK_MASK (0xC0000000U)
48702#define IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT (30U)
48709#define IOMUXC_GPR_GPR35_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR35_DWP_LOCK_MASK)
48715#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK (0x1U)
48716#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT (0U)
48719#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK)
48720
48721#define IOMUXC_GPR_GPR36_DWP_MASK (0x30000000U)
48722#define IOMUXC_GPR_GPR36_DWP_SHIFT (28U)
48729#define IOMUXC_GPR_GPR36_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_SHIFT)) & IOMUXC_GPR_GPR36_DWP_MASK)
48730
48731#define IOMUXC_GPR_GPR36_DWP_LOCK_MASK (0xC0000000U)
48732#define IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT (30U)
48739#define IOMUXC_GPR_GPR36_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR36_DWP_LOCK_MASK)
48745#define IOMUXC_GPR_GPR37_NIDEN_MASK (0x1U)
48746#define IOMUXC_GPR_GPR37_NIDEN_SHIFT (0U)
48749#define IOMUXC_GPR_GPR37_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_NIDEN_SHIFT)) & IOMUXC_GPR_GPR37_NIDEN_MASK)
48750
48751#define IOMUXC_GPR_GPR37_DBG_EN_MASK (0x2U)
48752#define IOMUXC_GPR_GPR37_DBG_EN_SHIFT (1U)
48755#define IOMUXC_GPR_GPR37_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR37_DBG_EN_MASK)
48756
48757#define IOMUXC_GPR_GPR37_EXC_MON_MASK (0x8U)
48758#define IOMUXC_GPR_GPR37_EXC_MON_SHIFT (3U)
48761#define IOMUXC_GPR_GPR37_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR37_EXC_MON_MASK)
48762
48763#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK (0x20U)
48764#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT (5U)
48767#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK)
48768
48769#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK (0x40U)
48770#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT (6U)
48773#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK)
48774
48775#define IOMUXC_GPR_GPR37_DWP_MASK (0x30000000U)
48776#define IOMUXC_GPR_GPR37_DWP_SHIFT (28U)
48783#define IOMUXC_GPR_GPR37_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_SHIFT)) & IOMUXC_GPR_GPR37_DWP_MASK)
48784
48785#define IOMUXC_GPR_GPR37_DWP_LOCK_MASK (0xC0000000U)
48786#define IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT (30U)
48793#define IOMUXC_GPR_GPR37_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR37_DWP_LOCK_MASK)
48799#define IOMUXC_GPR_GPR38_DWP_MASK (0x30000000U)
48800#define IOMUXC_GPR_GPR38_DWP_SHIFT (28U)
48807#define IOMUXC_GPR_GPR38_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_SHIFT)) & IOMUXC_GPR_GPR38_DWP_MASK)
48808
48809#define IOMUXC_GPR_GPR38_DWP_LOCK_MASK (0xC0000000U)
48810#define IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT (30U)
48817#define IOMUXC_GPR_GPR38_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR38_DWP_LOCK_MASK)
48823#define IOMUXC_GPR_GPR39_DWP_MASK (0x30000000U)
48824#define IOMUXC_GPR_GPR39_DWP_SHIFT (28U)
48831#define IOMUXC_GPR_GPR39_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_SHIFT)) & IOMUXC_GPR_GPR39_DWP_MASK)
48832
48833#define IOMUXC_GPR_GPR39_DWP_LOCK_MASK (0xC0000000U)
48834#define IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT (30U)
48841#define IOMUXC_GPR_GPR39_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR39_DWP_LOCK_MASK)
48847#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK (0xFFFFU)
48848#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT (0U)
48851#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK)
48852
48853#define IOMUXC_GPR_GPR40_DWP_MASK (0x30000000U)
48854#define IOMUXC_GPR_GPR40_DWP_SHIFT (28U)
48861#define IOMUXC_GPR_GPR40_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_SHIFT)) & IOMUXC_GPR_GPR40_DWP_MASK)
48862
48863#define IOMUXC_GPR_GPR40_DWP_LOCK_MASK (0xC0000000U)
48864#define IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT (30U)
48871#define IOMUXC_GPR_GPR40_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR40_DWP_LOCK_MASK)
48877#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK (0xFFFFU)
48878#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT (0U)
48881#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK)
48882
48883#define IOMUXC_GPR_GPR41_DWP_MASK (0x30000000U)
48884#define IOMUXC_GPR_GPR41_DWP_SHIFT (28U)
48891#define IOMUXC_GPR_GPR41_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_SHIFT)) & IOMUXC_GPR_GPR41_DWP_MASK)
48892
48893#define IOMUXC_GPR_GPR41_DWP_LOCK_MASK (0xC0000000U)
48894#define IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT (30U)
48901#define IOMUXC_GPR_GPR41_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR41_DWP_LOCK_MASK)
48907#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK (0xFFFFU)
48908#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT (0U)
48911#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK)
48912
48913#define IOMUXC_GPR_GPR42_DWP_MASK (0x30000000U)
48914#define IOMUXC_GPR_GPR42_DWP_SHIFT (28U)
48921#define IOMUXC_GPR_GPR42_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_SHIFT)) & IOMUXC_GPR_GPR42_DWP_MASK)
48922
48923#define IOMUXC_GPR_GPR42_DWP_LOCK_MASK (0xC0000000U)
48924#define IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT (30U)
48931#define IOMUXC_GPR_GPR42_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR42_DWP_LOCK_MASK)
48937#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK (0xFFFFU)
48938#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT (0U)
48941#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK)
48942
48943#define IOMUXC_GPR_GPR43_DWP_MASK (0x30000000U)
48944#define IOMUXC_GPR_GPR43_DWP_SHIFT (28U)
48951#define IOMUXC_GPR_GPR43_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_SHIFT)) & IOMUXC_GPR_GPR43_DWP_MASK)
48952
48953#define IOMUXC_GPR_GPR43_DWP_LOCK_MASK (0xC0000000U)
48954#define IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT (30U)
48961#define IOMUXC_GPR_GPR43_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR43_DWP_LOCK_MASK)
48967#define IOMUXC_GPR_GPR44_DWP_MASK (0x30000000U)
48968#define IOMUXC_GPR_GPR44_DWP_SHIFT (28U)
48975#define IOMUXC_GPR_GPR44_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_SHIFT)) & IOMUXC_GPR_GPR44_DWP_MASK)
48976
48977#define IOMUXC_GPR_GPR44_DWP_LOCK_MASK (0xC0000000U)
48978#define IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT (30U)
48985#define IOMUXC_GPR_GPR44_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR44_DWP_LOCK_MASK)
48991#define IOMUXC_GPR_GPR45_DWP_MASK (0x30000000U)
48992#define IOMUXC_GPR_GPR45_DWP_SHIFT (28U)
48999#define IOMUXC_GPR_GPR45_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_SHIFT)) & IOMUXC_GPR_GPR45_DWP_MASK)
49000
49001#define IOMUXC_GPR_GPR45_DWP_LOCK_MASK (0xC0000000U)
49002#define IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT (30U)
49009#define IOMUXC_GPR_GPR45_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR45_DWP_LOCK_MASK)
49015#define IOMUXC_GPR_GPR46_DWP_MASK (0x30000000U)
49016#define IOMUXC_GPR_GPR46_DWP_SHIFT (28U)
49023#define IOMUXC_GPR_GPR46_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_SHIFT)) & IOMUXC_GPR_GPR46_DWP_MASK)
49024
49025#define IOMUXC_GPR_GPR46_DWP_LOCK_MASK (0xC0000000U)
49026#define IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT (30U)
49033#define IOMUXC_GPR_GPR46_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR46_DWP_LOCK_MASK)
49039#define IOMUXC_GPR_GPR47_DWP_MASK (0x30000000U)
49040#define IOMUXC_GPR_GPR47_DWP_SHIFT (28U)
49047#define IOMUXC_GPR_GPR47_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_SHIFT)) & IOMUXC_GPR_GPR47_DWP_MASK)
49048
49049#define IOMUXC_GPR_GPR47_DWP_LOCK_MASK (0xC0000000U)
49050#define IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT (30U)
49057#define IOMUXC_GPR_GPR47_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR47_DWP_LOCK_MASK)
49063#define IOMUXC_GPR_GPR48_DWP_MASK (0x30000000U)
49064#define IOMUXC_GPR_GPR48_DWP_SHIFT (28U)
49071#define IOMUXC_GPR_GPR48_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_SHIFT)) & IOMUXC_GPR_GPR48_DWP_MASK)
49072
49073#define IOMUXC_GPR_GPR48_DWP_LOCK_MASK (0xC0000000U)
49074#define IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT (30U)
49081#define IOMUXC_GPR_GPR48_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR48_DWP_LOCK_MASK)
49087#define IOMUXC_GPR_GPR49_DWP_MASK (0x30000000U)
49088#define IOMUXC_GPR_GPR49_DWP_SHIFT (28U)
49095#define IOMUXC_GPR_GPR49_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_SHIFT)) & IOMUXC_GPR_GPR49_DWP_MASK)
49096
49097#define IOMUXC_GPR_GPR49_DWP_LOCK_MASK (0xC0000000U)
49098#define IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT (30U)
49105#define IOMUXC_GPR_GPR49_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR49_DWP_LOCK_MASK)
49111#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK (0x1FU)
49112#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT (0U)
49115#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT)) & IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK)
49116
49117#define IOMUXC_GPR_GPR50_DWP_MASK (0x30000000U)
49118#define IOMUXC_GPR_GPR50_DWP_SHIFT (28U)
49125#define IOMUXC_GPR_GPR50_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_SHIFT)) & IOMUXC_GPR_GPR50_DWP_MASK)
49126
49127#define IOMUXC_GPR_GPR50_DWP_LOCK_MASK (0xC0000000U)
49128#define IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT (30U)
49135#define IOMUXC_GPR_GPR50_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR50_DWP_LOCK_MASK)
49141#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK (0x1U)
49142#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT (0U)
49145#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT)) & IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK)
49146
49147#define IOMUXC_GPR_GPR51_DWP_MASK (0x30000000U)
49148#define IOMUXC_GPR_GPR51_DWP_SHIFT (28U)
49155#define IOMUXC_GPR_GPR51_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_SHIFT)) & IOMUXC_GPR_GPR51_DWP_MASK)
49156
49157#define IOMUXC_GPR_GPR51_DWP_LOCK_MASK (0xC0000000U)
49158#define IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT (30U)
49165#define IOMUXC_GPR_GPR51_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR51_DWP_LOCK_MASK)
49171#define IOMUXC_GPR_GPR52_DWP_MASK (0x30000000U)
49172#define IOMUXC_GPR_GPR52_DWP_SHIFT (28U)
49179#define IOMUXC_GPR_GPR52_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_SHIFT)) & IOMUXC_GPR_GPR52_DWP_MASK)
49180
49181#define IOMUXC_GPR_GPR52_DWP_LOCK_MASK (0xC0000000U)
49182#define IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT (30U)
49189#define IOMUXC_GPR_GPR52_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR52_DWP_LOCK_MASK)
49195#define IOMUXC_GPR_GPR53_DWP_MASK (0x30000000U)
49196#define IOMUXC_GPR_GPR53_DWP_SHIFT (28U)
49203#define IOMUXC_GPR_GPR53_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_SHIFT)) & IOMUXC_GPR_GPR53_DWP_MASK)
49204
49205#define IOMUXC_GPR_GPR53_DWP_LOCK_MASK (0xC0000000U)
49206#define IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT (30U)
49213#define IOMUXC_GPR_GPR53_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR53_DWP_LOCK_MASK)
49219#define IOMUXC_GPR_GPR54_DWP_MASK (0x30000000U)
49220#define IOMUXC_GPR_GPR54_DWP_SHIFT (28U)
49227#define IOMUXC_GPR_GPR54_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_SHIFT)) & IOMUXC_GPR_GPR54_DWP_MASK)
49228
49229#define IOMUXC_GPR_GPR54_DWP_LOCK_MASK (0xC0000000U)
49230#define IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT (30U)
49237#define IOMUXC_GPR_GPR54_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR54_DWP_LOCK_MASK)
49243#define IOMUXC_GPR_GPR55_DWP_MASK (0x30000000U)
49244#define IOMUXC_GPR_GPR55_DWP_SHIFT (28U)
49251#define IOMUXC_GPR_GPR55_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_SHIFT)) & IOMUXC_GPR_GPR55_DWP_MASK)
49252
49253#define IOMUXC_GPR_GPR55_DWP_LOCK_MASK (0xC0000000U)
49254#define IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT (30U)
49261#define IOMUXC_GPR_GPR55_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR55_DWP_LOCK_MASK)
49267#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK (0x1U)
49268#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT (0U)
49271#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK)
49272
49273#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK (0x2U)
49274#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT (1U)
49279#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK)
49280
49281#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK (0x4U)
49282#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT (2U)
49286#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK)
49287
49288#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK (0x8U)
49289#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT (3U)
49292#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK)
49293
49294#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK (0x10U)
49295#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT (4U)
49298#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK)
49299
49300#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK (0x20U)
49301#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT (5U)
49304#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)
49305
49306#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK (0xC0U)
49307#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT (6U)
49310#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK)
49311
49312#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK (0x300U)
49313#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT (8U)
49320#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK)
49321
49322#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK (0xC00U)
49323#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT (10U)
49326#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK)
49327
49328#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK (0x3F000U)
49329#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT (12U)
49332#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)
49333
49334#define IOMUXC_GPR_GPR59_DWP_MASK (0x30000000U)
49335#define IOMUXC_GPR_GPR59_DWP_SHIFT (28U)
49342#define IOMUXC_GPR_GPR59_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_SHIFT)) & IOMUXC_GPR_GPR59_DWP_MASK)
49343
49344#define IOMUXC_GPR_GPR59_DWP_LOCK_MASK (0xC0000000U)
49345#define IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT (30U)
49352#define IOMUXC_GPR_GPR59_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR59_DWP_LOCK_MASK)
49358#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK (0x7U)
49359#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT (0U)
49362#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK)
49363
49364#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK (0x38U)
49365#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT (3U)
49368#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK)
49369
49370#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK (0x1C0U)
49371#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT (6U)
49374#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK)
49375
49376#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK (0x600U)
49377#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT (9U)
49380#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK)
49381
49382#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK (0x3800U)
49383#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT (11U)
49386#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK)
49387
49388#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK (0x10000U)
49389#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT (16U)
49394#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK)
49395
49396#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK (0x20000U)
49397#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT (17U)
49402#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK)
49403
49404#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK (0x40000U)
49405#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT (18U)
49410#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK)
49411
49412#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK (0x80000U)
49413#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT (19U)
49418#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK)
49419
49420#define IOMUXC_GPR_GPR62_DWP_MASK (0x30000000U)
49421#define IOMUXC_GPR_GPR62_DWP_SHIFT (28U)
49428#define IOMUXC_GPR_GPR62_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_SHIFT)) & IOMUXC_GPR_GPR62_DWP_MASK)
49429
49430#define IOMUXC_GPR_GPR62_DWP_LOCK_MASK (0xC0000000U)
49431#define IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT (30U)
49438#define IOMUXC_GPR_GPR62_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR62_DWP_LOCK_MASK)
49444#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK (0x7U)
49445#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT (0U)
49448#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK)
49454#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK (0x1U)
49455#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT (0U)
49458#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK)
49459
49460#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK (0x2U)
49461#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT (1U)
49464#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK)
49465
49466#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK (0x4U)
49467#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT (2U)
49470#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK)
49471
49472#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK (0x8U)
49473#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT (3U)
49476#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK)
49477
49478#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK (0xF0U)
49479#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT (4U)
49482#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK)
49483
49484#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK (0xF00U)
49485#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT (8U)
49488#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK)
49489
49490#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK (0x1000U)
49491#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT (12U)
49494#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK)
49495
49496#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK (0x2000U)
49497#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT (13U)
49500#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK)
49501
49502#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK (0x4000U)
49503#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT (14U)
49506#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK)
49507
49508#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK (0x100000U)
49509#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT (20U)
49512#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK)
49513
49514#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK (0x1E00000U)
49515#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT (21U)
49518#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK)
49519
49520#define IOMUXC_GPR_GPR64_DWP_MASK (0x30000000U)
49521#define IOMUXC_GPR_GPR64_DWP_SHIFT (28U)
49528#define IOMUXC_GPR_GPR64_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_SHIFT)) & IOMUXC_GPR_GPR64_DWP_MASK)
49529
49530#define IOMUXC_GPR_GPR64_DWP_LOCK_MASK (0xC0000000U)
49531#define IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT (30U)
49538#define IOMUXC_GPR_GPR64_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR64_DWP_LOCK_MASK)
49544#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK (0x1U)
49545#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT (0U)
49548#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK)
49549
49550#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK (0x2U)
49551#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT (1U)
49554#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK)
49555
49556#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK (0x4U)
49557#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT (2U)
49560#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK)
49561
49562#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK (0x8U)
49563#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT (3U)
49566#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK)
49567
49568#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK (0xF0U)
49569#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT (4U)
49572#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK)
49573
49574#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK (0xF00U)
49575#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT (8U)
49578#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK)
49579
49580#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK (0x1000U)
49581#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT (12U)
49584#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK)
49585
49586#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK (0x2000U)
49587#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT (13U)
49590#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK)
49591
49592#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK (0x4000U)
49593#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT (14U)
49596#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK)
49597
49598#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK (0x100000U)
49599#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT (20U)
49602#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK)
49603
49604#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK (0x1E00000U)
49605#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT (21U)
49608#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK)
49609
49610#define IOMUXC_GPR_GPR65_DWP_MASK (0x30000000U)
49611#define IOMUXC_GPR_GPR65_DWP_SHIFT (28U)
49618#define IOMUXC_GPR_GPR65_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_SHIFT)) & IOMUXC_GPR_GPR65_DWP_MASK)
49619
49620#define IOMUXC_GPR_GPR65_DWP_LOCK_MASK (0xC0000000U)
49621#define IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT (30U)
49628#define IOMUXC_GPR_GPR65_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR65_DWP_LOCK_MASK)
49634#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK (0x1U)
49635#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT (0U)
49638#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK)
49639
49640#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK (0x2U)
49641#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT (1U)
49644#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK)
49645
49646#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK (0x4U)
49647#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT (2U)
49650#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK)
49651
49652#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK (0x8U)
49653#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT (3U)
49656#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK)
49657
49658#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK (0xF0U)
49659#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT (4U)
49662#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK)
49663
49664#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK (0xF00U)
49665#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT (8U)
49668#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK)
49669
49670#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK (0x1000U)
49671#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT (12U)
49674#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK)
49675
49676#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK (0x2000U)
49677#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT (13U)
49680#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK)
49681
49682#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK (0x4000U)
49683#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT (14U)
49686#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK)
49687
49688#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK (0x100000U)
49689#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT (20U)
49692#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK)
49693
49694#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK (0x1E00000U)
49695#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT (21U)
49698#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK)
49699
49700#define IOMUXC_GPR_GPR66_DWP_MASK (0x30000000U)
49701#define IOMUXC_GPR_GPR66_DWP_SHIFT (28U)
49708#define IOMUXC_GPR_GPR66_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_SHIFT)) & IOMUXC_GPR_GPR66_DWP_MASK)
49709
49710#define IOMUXC_GPR_GPR66_DWP_LOCK_MASK (0xC0000000U)
49711#define IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT (30U)
49718#define IOMUXC_GPR_GPR66_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR66_DWP_LOCK_MASK)
49724#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK (0x1U)
49725#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT (0U)
49728#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK)
49729
49730#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK (0x2U)
49731#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT (1U)
49734#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK)
49735
49736#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK (0x4U)
49737#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT (2U)
49740#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK)
49741
49742#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK (0x8U)
49743#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT (3U)
49746#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK)
49747
49748#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK (0xF0U)
49749#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT (4U)
49752#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK)
49753
49754#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK (0xF00U)
49755#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT (8U)
49758#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK)
49759
49760#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK (0x1000U)
49761#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT (12U)
49764#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK)
49765
49766#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK (0x2000U)
49767#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT (13U)
49770#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK)
49771
49772#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK (0x4000U)
49773#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT (14U)
49776#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK)
49777
49778#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK (0x100000U)
49779#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT (20U)
49782#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK)
49783
49784#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK (0x1E00000U)
49785#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT (21U)
49788#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK)
49789
49790#define IOMUXC_GPR_GPR67_DWP_MASK (0x30000000U)
49791#define IOMUXC_GPR_GPR67_DWP_SHIFT (28U)
49798#define IOMUXC_GPR_GPR67_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_SHIFT)) & IOMUXC_GPR_GPR67_DWP_MASK)
49799
49800#define IOMUXC_GPR_GPR67_DWP_LOCK_MASK (0xC0000000U)
49801#define IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT (30U)
49808#define IOMUXC_GPR_GPR67_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR67_DWP_LOCK_MASK)
49814#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK (0x1U)
49815#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT (0U)
49818#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK)
49819
49820#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK (0x2U)
49821#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT (1U)
49824#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK)
49825
49826#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK (0x4U)
49827#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT (2U)
49830#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK)
49831
49832#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK (0x8U)
49833#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT (3U)
49836#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK)
49837
49838#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK (0xF0U)
49839#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT (4U)
49842#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK)
49843
49844#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK (0xF00U)
49845#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT (8U)
49848#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK)
49849
49850#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK (0x1000U)
49851#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT (12U)
49854#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK)
49855
49856#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK (0x2000U)
49857#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT (13U)
49860#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK)
49861
49862#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK (0x4000U)
49863#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT (14U)
49866#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK)
49867
49868#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK (0x100000U)
49869#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT (20U)
49872#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK)
49873
49874#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK (0x1E00000U)
49875#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT (21U)
49878#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK)
49879
49880#define IOMUXC_GPR_GPR68_DWP_MASK (0x30000000U)
49881#define IOMUXC_GPR_GPR68_DWP_SHIFT (28U)
49888#define IOMUXC_GPR_GPR68_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_SHIFT)) & IOMUXC_GPR_GPR68_DWP_MASK)
49889
49890#define IOMUXC_GPR_GPR68_DWP_LOCK_MASK (0xC0000000U)
49891#define IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT (30U)
49898#define IOMUXC_GPR_GPR68_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR68_DWP_LOCK_MASK)
49904#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK (0x2U)
49905#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT (1U)
49908#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK)
49909
49910#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK (0x4U)
49911#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT (2U)
49914#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK)
49915
49916#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK (0x10U)
49917#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT (4U)
49920#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK)
49921
49922#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK (0x20U)
49923#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT (5U)
49926#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK)
49927
49928#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK (0x80U)
49929#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT (7U)
49932#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK)
49933
49934#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK (0x100U)
49935#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT (8U)
49938#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK)
49939
49940#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK (0x200U)
49941#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT (9U)
49944#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK)
49945
49946#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK (0x400U)
49947#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT (10U)
49950#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK)
49951
49952#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK (0x800U)
49953#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT (11U)
49956#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK)
49957
49958#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK (0x1000U)
49959#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT (12U)
49962#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK)
49963
49964#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK (0x2000U)
49965#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT (13U)
49968#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK)
49969
49970#define IOMUXC_GPR_GPR69_DWP_MASK (0x30000000U)
49971#define IOMUXC_GPR_GPR69_DWP_SHIFT (28U)
49978#define IOMUXC_GPR_GPR69_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_SHIFT)) & IOMUXC_GPR_GPR69_DWP_MASK)
49979
49980#define IOMUXC_GPR_GPR69_DWP_LOCK_MASK (0xC0000000U)
49981#define IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT (30U)
49988#define IOMUXC_GPR_GPR69_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR69_DWP_LOCK_MASK)
49994#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK (0x1U)
49995#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT (0U)
49998#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK)
49999
50000#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK (0x2U)
50001#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT (1U)
50004#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK)
50005
50006#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK (0x4U)
50007#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT (2U)
50012#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK)
50013
50014#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK (0x8U)
50015#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT (3U)
50018#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK)
50019
50020#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK (0x10U)
50021#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT (4U)
50024#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK)
50025
50026#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK (0x20U)
50027#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT (5U)
50032#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK)
50033
50034#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK (0x40U)
50035#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT (6U)
50038#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK)
50039
50040#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK (0x80U)
50041#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT (7U)
50044#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK)
50045
50046#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK (0x100U)
50047#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT (8U)
50050#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK)
50051
50052#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK (0x200U)
50053#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT (9U)
50056#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK)
50057
50058#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK (0x400U)
50059#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT (10U)
50062#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK)
50063
50064#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK (0x800U)
50065#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT (11U)
50068#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK)
50069
50070#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK (0x1000U)
50071#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT (12U)
50074#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK)
50075
50076#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK (0x2000U)
50077#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT (13U)
50080#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK)
50081
50082#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK (0x8000U)
50083#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT (15U)
50086#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK)
50087
50088#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK (0x10000U)
50089#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT (16U)
50092#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK)
50093
50094#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK (0x20000U)
50095#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT (17U)
50098#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK)
50099
50100#define IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK (0x40000U)
50101#define IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT (18U)
50104#define IOMUXC_GPR_GPR70_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK)
50105
50106#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK (0x80000U)
50107#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT (19U)
50110#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK)
50111
50112#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK (0x100000U)
50113#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT (20U)
50116#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK)
50117
50118#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK (0x200000U)
50119#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT (21U)
50122#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK)
50123
50124#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK (0x400000U)
50125#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT (22U)
50128#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK)
50129
50130#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK (0x800000U)
50131#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT (23U)
50134#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK)
50135
50136#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK (0x1000000U)
50137#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT (24U)
50140#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK)
50141
50142#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK (0x2000000U)
50143#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT (25U)
50146#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK)
50147
50148#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK (0x4000000U)
50149#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT (26U)
50152#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK)
50153
50154#define IOMUXC_GPR_GPR70_DWP_MASK (0x30000000U)
50155#define IOMUXC_GPR_GPR70_DWP_SHIFT (28U)
50162#define IOMUXC_GPR_GPR70_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_SHIFT)) & IOMUXC_GPR_GPR70_DWP_MASK)
50163
50164#define IOMUXC_GPR_GPR70_DWP_LOCK_MASK (0xC0000000U)
50165#define IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT (30U)
50172#define IOMUXC_GPR_GPR70_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR70_DWP_LOCK_MASK)
50178#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK (0x1U)
50179#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT (0U)
50182#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK)
50183
50184#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK (0x2U)
50185#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT (1U)
50188#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK)
50189
50190#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK (0x4U)
50191#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT (2U)
50194#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK)
50195
50196#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK (0x8U)
50197#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT (3U)
50200#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK)
50201
50202#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK (0x10U)
50203#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT (4U)
50206#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK)
50207
50208#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK (0x20U)
50209#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT (5U)
50212#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK)
50213
50214#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK (0x40U)
50215#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT (6U)
50218#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK)
50219
50220#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK (0x80U)
50221#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT (7U)
50224#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK)
50225
50226#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK (0x100U)
50227#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT (8U)
50232#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK)
50233
50234#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK (0x200U)
50235#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT (9U)
50238#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK)
50239
50240#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK (0x400U)
50241#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT (10U)
50244#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK)
50245
50246#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK (0x800U)
50247#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT (11U)
50252#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK)
50253
50254#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK (0x1000U)
50255#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT (12U)
50258#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK)
50259
50260#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK (0x2000U)
50261#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT (13U)
50264#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK)
50265
50266#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK (0x4000U)
50267#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT (14U)
50272#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK)
50273
50274#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK (0x8000U)
50275#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT (15U)
50278#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK)
50279
50280#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK (0x10000U)
50281#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT (16U)
50284#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK)
50285
50286#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK (0x20000U)
50287#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT (17U)
50292#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK)
50293
50294#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK (0x40000U)
50295#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT (18U)
50298#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK)
50299
50300#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK (0x80000U)
50301#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT (19U)
50304#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK)
50305
50306#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK (0x100000U)
50307#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT (20U)
50312#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK)
50313
50314#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK (0x200000U)
50315#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT (21U)
50318#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK)
50319
50320#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK (0x400000U)
50321#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT (22U)
50324#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK)
50325
50326#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK (0x800000U)
50327#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT (23U)
50332#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK)
50333
50334#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK (0x1000000U)
50335#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT (24U)
50338#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK)
50339
50340#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK (0x2000000U)
50341#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT (25U)
50344#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK)
50345
50346#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U)
50347#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT (26U)
50352#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK)
50353
50354#define IOMUXC_GPR_GPR71_DWP_MASK (0x30000000U)
50355#define IOMUXC_GPR_GPR71_DWP_SHIFT (28U)
50362#define IOMUXC_GPR_GPR71_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_SHIFT)) & IOMUXC_GPR_GPR71_DWP_MASK)
50363
50364#define IOMUXC_GPR_GPR71_DWP_LOCK_MASK (0xC0000000U)
50365#define IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT (30U)
50372#define IOMUXC_GPR_GPR71_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR71_DWP_LOCK_MASK)
50378#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK (0x1U)
50379#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT (0U)
50382#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK)
50383
50384#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK (0x2U)
50385#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT (1U)
50388#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK)
50389
50390#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK (0x4U)
50391#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT (2U)
50396#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK)
50397
50398#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK (0x8U)
50399#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT (3U)
50402#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK)
50403
50404#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK (0x10U)
50405#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT (4U)
50408#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK)
50409
50410#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK (0x20U)
50411#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT (5U)
50416#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK)
50417
50418#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK (0x40U)
50419#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT (6U)
50422#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK)
50423
50424#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK (0x80U)
50425#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT (7U)
50428#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK)
50429
50430#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK (0x100U)
50431#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT (8U)
50436#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK)
50437
50438#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK (0x200U)
50439#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT (9U)
50442#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK)
50443
50444#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK (0x400U)
50445#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT (10U)
50448#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK)
50449
50450#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK (0x800U)
50451#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT (11U)
50456#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK)
50457
50458#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK (0x1000U)
50459#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT (12U)
50462#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK)
50463
50464#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK (0x2000U)
50465#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT (13U)
50468#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK)
50469
50470#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK (0x4000U)
50471#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT (14U)
50476#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK)
50477
50478#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK (0x8000U)
50479#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT (15U)
50482#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK)
50483
50484#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK (0x10000U)
50485#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT (16U)
50488#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK)
50489
50490#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK (0x20000U)
50491#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT (17U)
50496#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK)
50497
50498#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK (0x40000U)
50499#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT (18U)
50502#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK)
50503
50504#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK (0x80000U)
50505#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT (19U)
50508#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK)
50509
50510#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK (0x100000U)
50511#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT (20U)
50516#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK)
50517
50518#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK (0x200000U)
50519#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT (21U)
50522#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK)
50523
50524#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK (0x400000U)
50525#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT (22U)
50528#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK)
50529
50530#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK (0x800000U)
50531#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT (23U)
50536#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK)
50537
50538#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK (0x1000000U)
50539#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT (24U)
50542#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK)
50543
50544#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK (0x2000000U)
50545#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT (25U)
50548#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK)
50549
50550#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK (0x4000000U)
50551#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT (26U)
50556#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK)
50557
50558#define IOMUXC_GPR_GPR72_DWP_MASK (0x30000000U)
50559#define IOMUXC_GPR_GPR72_DWP_SHIFT (28U)
50566#define IOMUXC_GPR_GPR72_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_SHIFT)) & IOMUXC_GPR_GPR72_DWP_MASK)
50567
50568#define IOMUXC_GPR_GPR72_DWP_LOCK_MASK (0xC0000000U)
50569#define IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT (30U)
50576#define IOMUXC_GPR_GPR72_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR72_DWP_LOCK_MASK)
50582#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK (0x1U)
50583#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT (0U)
50586#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK)
50587
50588#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK (0x2U)
50589#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT (1U)
50592#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK)
50593
50594#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK (0x4U)
50595#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT (2U)
50600#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK)
50601
50602#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK (0x8U)
50603#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT (3U)
50606#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK)
50607
50608#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK (0x10U)
50609#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT (4U)
50612#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK)
50613
50614#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK (0x20U)
50615#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT (5U)
50620#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK)
50621
50622#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK (0x40U)
50623#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT (6U)
50626#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK)
50627
50628#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK (0x80U)
50629#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT (7U)
50632#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK)
50633
50634#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK (0x100U)
50635#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT (8U)
50640#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK)
50641
50642#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK (0x200U)
50643#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT (9U)
50646#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK)
50647
50648#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK (0x400U)
50649#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT (10U)
50652#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK)
50653
50654#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK (0x800U)
50655#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT (11U)
50660#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK)
50661
50662#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK (0x1000U)
50663#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT (12U)
50666#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK)
50667
50668#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK (0x2000U)
50669#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT (13U)
50672#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK)
50673
50674#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK (0x4000U)
50675#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT (14U)
50680#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK)
50681
50682#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK (0x8000U)
50683#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT (15U)
50686#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK)
50687
50688#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK (0x10000U)
50689#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT (16U)
50692#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK)
50693
50694#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK (0x20000U)
50695#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT (17U)
50700#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK)
50701
50702#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK (0x40000U)
50703#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT (18U)
50706#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK)
50707
50708#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK (0x80000U)
50709#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT (19U)
50712#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK)
50713
50714#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK (0x100000U)
50715#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT (20U)
50720#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK)
50721
50722#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK (0x200000U)
50723#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT (21U)
50726#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK)
50727
50728#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK (0x400000U)
50729#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT (22U)
50732#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK)
50733
50734#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK (0x800000U)
50735#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT (23U)
50740#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK)
50741
50742#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK (0x1000000U)
50743#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT (24U)
50746#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK)
50747
50748#define IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK (0x2000000U)
50749#define IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT (25U)
50752#define IOMUXC_GPR_GPR73_MIC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK)
50753
50754#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK (0x4000000U)
50755#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT (26U)
50760#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK)
50761
50762#define IOMUXC_GPR_GPR73_DWP_MASK (0x30000000U)
50763#define IOMUXC_GPR_GPR73_DWP_SHIFT (28U)
50770#define IOMUXC_GPR_GPR73_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_SHIFT)) & IOMUXC_GPR_GPR73_DWP_MASK)
50771
50772#define IOMUXC_GPR_GPR73_DWP_LOCK_MASK (0xC0000000U)
50773#define IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT (30U)
50780#define IOMUXC_GPR_GPR73_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR73_DWP_LOCK_MASK)
50786#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK (0x2U)
50787#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT (1U)
50790#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK)
50791
50792#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK (0x4U)
50793#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT (2U)
50796#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK)
50797
50798#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK (0x8U)
50799#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT (3U)
50802#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK)
50803
50804#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK (0x10U)
50805#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT (4U)
50808#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK)
50809
50810#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK (0x20U)
50811#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT (5U)
50814#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK)
50815
50816#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK (0x40U)
50817#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT (6U)
50820#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK)
50821
50822#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK (0x80U)
50823#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT (7U)
50826#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK)
50827
50828#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK (0x100U)
50829#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT (8U)
50832#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK)
50833
50834#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK (0x200U)
50835#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT (9U)
50838#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK)
50839
50840#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK (0x400U)
50841#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT (10U)
50844#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK)
50845
50846#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK (0x800U)
50847#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT (11U)
50850#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK)
50851
50852#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK (0x1000U)
50853#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT (12U)
50856#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK)
50857
50858#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK (0x2000U)
50859#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT (13U)
50862#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK)
50863
50864#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U)
50865#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT (14U)
50868#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK)
50869
50870#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK (0x8000U)
50871#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT (15U)
50874#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK)
50875
50876#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U)
50877#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT (16U)
50880#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK)
50881
50882#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK (0x20000U)
50883#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT (17U)
50886#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK)
50887
50888#define IOMUXC_GPR_GPR74_DWP_MASK (0x30000000U)
50889#define IOMUXC_GPR_GPR74_DWP_SHIFT (28U)
50896#define IOMUXC_GPR_GPR74_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_SHIFT)) & IOMUXC_GPR_GPR74_DWP_MASK)
50897
50898#define IOMUXC_GPR_GPR74_DWP_LOCK_MASK (0xC0000000U)
50899#define IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT (30U)
50906#define IOMUXC_GPR_GPR74_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR74_DWP_LOCK_MASK)
50912#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK (0x1U)
50913#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT (0U)
50916#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK)
50917
50918#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK (0x2U)
50919#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT (1U)
50922#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK)
50923
50924#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK (0x4U)
50925#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT (2U)
50928#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK)
50929
50930#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK (0x8U)
50931#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT (3U)
50934#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK)
50935
50936#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK (0x10U)
50937#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT (4U)
50940#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK)
50941
50942#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK (0x20U)
50943#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT (5U)
50946#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK)
50947
50948#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK (0x40U)
50949#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT (6U)
50952#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK)
50953
50954#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK (0x80U)
50955#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT (7U)
50958#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK)
50959
50960#define IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK (0x100U)
50961#define IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT (8U)
50964#define IOMUXC_GPR_GPR75_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK)
50965
50966#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK (0x200U)
50967#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT (9U)
50970#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK)
50971
50972#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK (0x400U)
50973#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT (10U)
50976#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK)
50977
50978#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK (0x800U)
50979#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT (11U)
50982#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK)
50983
50984#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK (0x1000U)
50985#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT (12U)
50988#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK)
50989
50990#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK (0x2000U)
50991#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT (13U)
50994#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK)
50995
50996#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK (0x4000U)
50997#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT (14U)
51000#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK)
51001
51002#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK (0x8000U)
51003#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT (15U)
51006#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK)
51007
51008#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK (0x10000U)
51009#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT (16U)
51012#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK)
51013
51014#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK (0x20000U)
51015#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT (17U)
51018#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK)
51019
51020#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK (0x40000U)
51021#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT (18U)
51024#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK)
51025
51026#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK (0x80000U)
51027#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT (19U)
51030#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK)
51031
51032#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK (0x100000U)
51033#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT (20U)
51036#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK)
51037
51038#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK (0x200000U)
51039#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT (21U)
51042#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK)
51043
51044#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK (0x400000U)
51045#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT (22U)
51048#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK)
51049
51050#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK (0x800000U)
51051#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT (23U)
51054#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK)
51055
51056#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK (0x1000000U)
51057#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT (24U)
51060#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK)
51061
51062#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK (0x2000000U)
51063#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT (25U)
51066#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK)
51067
51068#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK (0x4000000U)
51069#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT (26U)
51072#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK)
51073
51074#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK (0x8000000U)
51075#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT (27U)
51078#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK)
51079
51080#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK (0x10000000U)
51081#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT (28U)
51084#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK)
51085
51086#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK (0x20000000U)
51087#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT (29U)
51090#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK)
51091
51092#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK (0x40000000U)
51093#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT (30U)
51096#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK)
51097
51098#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK (0x80000000U)
51099#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT (31U)
51102#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK)
51108#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK (0x1U)
51109#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT (0U)
51112#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK)
51113
51114#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK (0x2U)
51115#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT (1U)
51118#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK)
51119
51120#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK (0x4U)
51121#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT (2U)
51124#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK)
51125
51126#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK (0x8U)
51127#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT (3U)
51130#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK)
51131
51132#define IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK (0x10U)
51133#define IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT (4U)
51136#define IOMUXC_GPR_GPR76_MIC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK)
51137
51138#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK (0x20U)
51139#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT (5U)
51142#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK)
51143
51144#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK (0x40U)
51145#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT (6U)
51148#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK)
51149
51150#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK (0x80U)
51151#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT (7U)
51154#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK)
51155
51156#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK (0x100U)
51157#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT (8U)
51160#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK)
51161
51162#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK (0x200U)
51163#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT (9U)
51166#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK)
51167
51168#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK (0x400U)
51169#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT (10U)
51172#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK)
51173
51174#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK (0x800U)
51175#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT (11U)
51178#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK)
51179
51180#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK (0x1000U)
51181#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT (12U)
51184#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK)
51185
51186#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U)
51187#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT (13U)
51190#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK)
51191
51192#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK (0x4000U)
51193#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT (14U)
51196#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK)
51197
51198#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U)
51199#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT (15U)
51202#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK)
51203
51204#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK (0x10000U)
51205#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT (16U)
51208#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK) /* end of group IOMUXC_GPR_Register_Masks */
51215
51216
51217/* IOMUXC_GPR - Peripheral instance base addresses */
51219#define IOMUXC_GPR_BASE (0x400E4000u)
51221#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
51223#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }
51225#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }
51226 /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
51230
51231
51232/* ----------------------------------------------------------------------------
51233 -- IOMUXC_LPSR Peripheral Access Layer
51234 ---------------------------------------------------------------------------- */
51235
51242typedef struct {
51243 __IO uint32_t SW_MUX_CTL_PAD[16];
51244 __IO uint32_t SW_PAD_CTL_PAD[16];
51245 __IO uint32_t SELECT_INPUT[24];
51247
51248/* ----------------------------------------------------------------------------
51249 -- IOMUXC_LPSR Register Masks
51250 ---------------------------------------------------------------------------- */
51251
51260#define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU)
51261#define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
51274#define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK)
51275
51276#define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK (0x10U)
51277#define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT (4U)
51282#define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK)
51285/* The count of IOMUXC_LPSR_SW_MUX_CTL_PAD */
51286#define IOMUXC_LPSR_SW_MUX_CTL_PAD_COUNT (16U)
51287
51291#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK (0x1U)
51292#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT (0U)
51297#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK)
51298
51299#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK (0x2U)
51300#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT (1U)
51305#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK)
51306
51307#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK (0x4U)
51308#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT (2U)
51313#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK)
51314
51315#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK (0x8U)
51316#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT (3U)
51321#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK)
51322
51323#define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK (0x20U)
51324#define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT (5U)
51329#define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK)
51330
51331#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK (0x30000000U)
51332#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT (28U)
51339#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK)
51340
51341#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U)
51342#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U)
51349#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK)
51352/* The count of IOMUXC_LPSR_SW_PAD_CTL_PAD */
51353#define IOMUXC_LPSR_SW_PAD_CTL_PAD_COUNT (16U)
51354
51358#define IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
51359#define IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT (0U)
51365#define IOMUXC_LPSR_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
51368/* The count of IOMUXC_LPSR_SELECT_INPUT */
51369#define IOMUXC_LPSR_SELECT_INPUT_COUNT (24U)
51370
51371 /* end of group IOMUXC_LPSR_Register_Masks */
51375
51376
51377/* IOMUXC_LPSR - Peripheral instance base addresses */
51379#define IOMUXC_LPSR_BASE (0x40C08000u)
51381#define IOMUXC_LPSR ((IOMUXC_LPSR_Type *)IOMUXC_LPSR_BASE)
51383#define IOMUXC_LPSR_BASE_ADDRS { IOMUXC_LPSR_BASE }
51385#define IOMUXC_LPSR_BASE_PTRS { IOMUXC_LPSR }
51386 /* end of group IOMUXC_LPSR_Peripheral_Access_Layer */
51390
51391
51392/* ----------------------------------------------------------------------------
51393 -- IOMUXC_LPSR_GPR Peripheral Access Layer
51394 ---------------------------------------------------------------------------- */
51395
51402typedef struct {
51403 __IO uint32_t GPR0;
51404 __IO uint32_t GPR1;
51405 __IO uint32_t GPR2;
51406 __IO uint32_t GPR3;
51407 __IO uint32_t GPR4;
51408 __IO uint32_t GPR5;
51409 __IO uint32_t GPR6;
51410 __IO uint32_t GPR7;
51411 __IO uint32_t GPR8;
51412 __IO uint32_t GPR9;
51413 __IO uint32_t GPR10;
51414 __IO uint32_t GPR11;
51415 __IO uint32_t GPR12;
51416 __IO uint32_t GPR13;
51417 __IO uint32_t GPR14;
51418 __IO uint32_t GPR15;
51419 __IO uint32_t GPR16;
51420 __IO uint32_t GPR17;
51421 __IO uint32_t GPR18;
51422 __IO uint32_t GPR19;
51423 __IO uint32_t GPR20;
51424 __IO uint32_t GPR21;
51425 __IO uint32_t GPR22;
51426 __IO uint32_t GPR23;
51427 __IO uint32_t GPR24;
51428 __IO uint32_t GPR25;
51429 __IO uint32_t GPR26;
51430 uint8_t RESERVED_0[24];
51431 __IO uint32_t GPR33;
51432 __IO uint32_t GPR34;
51433 __IO uint32_t GPR35;
51434 __IO uint32_t GPR36;
51435 __IO uint32_t GPR37;
51436 __IO uint32_t GPR38;
51437 __IO uint32_t GPR39;
51438 __I uint32_t GPR40;
51439 __I uint32_t GPR41;
51441
51442/* ----------------------------------------------------------------------------
51443 -- IOMUXC_LPSR_GPR Register Masks
51444 ---------------------------------------------------------------------------- */
51445
51454#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK (0xFFF8U)
51455#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT (3U)
51458#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK)
51459
51460#define IOMUXC_LPSR_GPR_GPR0_DWP_MASK (0x30000000U)
51461#define IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT (28U)
51468#define IOMUXC_LPSR_GPR_GPR0_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK)
51469
51470#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK (0xC0000000U)
51471#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT (30U)
51478#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK)
51484#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK (0xFFFFU)
51485#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT (0U)
51488#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK)
51489
51490#define IOMUXC_LPSR_GPR_GPR1_DWP_MASK (0x30000000U)
51491#define IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT (28U)
51498#define IOMUXC_LPSR_GPR_GPR1_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK)
51499
51500#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK (0xC0000000U)
51501#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT (30U)
51508#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK)
51514#define IOMUXC_LPSR_GPR_GPR2_LOCK_MASK (0x1U)
51515#define IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT (0U)
51520#define IOMUXC_LPSR_GPR_GPR2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK)
51521
51522#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)
51523#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT (3U)
51526#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK)
51532#define IOMUXC_LPSR_GPR_GPR3_LOCK_MASK (0x1U)
51533#define IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT (0U)
51538#define IOMUXC_LPSR_GPR_GPR3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK)
51539
51540#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)
51541#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT (3U)
51544#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK)
51550#define IOMUXC_LPSR_GPR_GPR4_LOCK_MASK (0x1U)
51551#define IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT (0U)
51556#define IOMUXC_LPSR_GPR_GPR4_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK)
51557
51558#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)
51559#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT (3U)
51562#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK)
51568#define IOMUXC_LPSR_GPR_GPR5_LOCK_MASK (0x1U)
51569#define IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT (0U)
51574#define IOMUXC_LPSR_GPR_GPR5_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK)
51575
51576#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)
51577#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT (3U)
51580#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK)
51586#define IOMUXC_LPSR_GPR_GPR6_LOCK_MASK (0x1U)
51587#define IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT (0U)
51592#define IOMUXC_LPSR_GPR_GPR6_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_LOCK_MASK)
51593
51594#define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)
51595#define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT (3U)
51598#define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK)
51604#define IOMUXC_LPSR_GPR_GPR7_LOCK_MASK (0x1U)
51605#define IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT (0U)
51610#define IOMUXC_LPSR_GPR_GPR7_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK)
51611
51612#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)
51613#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT (3U)
51616#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK)
51622#define IOMUXC_LPSR_GPR_GPR8_LOCK_MASK (0x1U)
51623#define IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT (0U)
51628#define IOMUXC_LPSR_GPR_GPR8_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK)
51629
51630#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK (0xFFFFFFF8U)
51631#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT (3U)
51634#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK)
51640#define IOMUXC_LPSR_GPR_GPR9_LOCK_MASK (0x1U)
51641#define IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT (0U)
51646#define IOMUXC_LPSR_GPR_GPR9_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK)
51647
51648#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)
51649#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT (3U)
51652#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK)
51658#define IOMUXC_LPSR_GPR_GPR10_LOCK_MASK (0x1U)
51659#define IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT (0U)
51664#define IOMUXC_LPSR_GPR_GPR10_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK)
51665
51666#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK (0xFFFFFFF8U)
51667#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT (3U)
51670#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK)
51676#define IOMUXC_LPSR_GPR_GPR11_LOCK_MASK (0x1U)
51677#define IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT (0U)
51682#define IOMUXC_LPSR_GPR_GPR11_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK)
51683
51684#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK (0xFFFFFFF8U)
51685#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT (3U)
51688#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK)
51694#define IOMUXC_LPSR_GPR_GPR12_LOCK_MASK (0x1U)
51695#define IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT (0U)
51700#define IOMUXC_LPSR_GPR_GPR12_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK)
51701
51702#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK (0xFFFFFFF8U)
51703#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT (3U)
51706#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK)
51712#define IOMUXC_LPSR_GPR_GPR13_LOCK_MASK (0x1U)
51713#define IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT (0U)
51718#define IOMUXC_LPSR_GPR_GPR13_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK)
51719
51720#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK (0xFFFFFFF8U)
51721#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT (3U)
51724#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK)
51730#define IOMUXC_LPSR_GPR_GPR14_LOCK_MASK (0x1U)
51731#define IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT (0U)
51736#define IOMUXC_LPSR_GPR_GPR14_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK)
51737
51738#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK (0xFFFFFFF8U)
51739#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT (3U)
51742#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK)
51748#define IOMUXC_LPSR_GPR_GPR15_LOCK_MASK (0x1U)
51749#define IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT (0U)
51754#define IOMUXC_LPSR_GPR_GPR15_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK)
51755
51756#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK (0xFFFFFFF8U)
51757#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT (3U)
51760#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK)
51766#define IOMUXC_LPSR_GPR_GPR16_LOCK_MASK (0x1U)
51767#define IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT (0U)
51772#define IOMUXC_LPSR_GPR_GPR16_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK)
51773
51774#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK (0xFFFFFFF8U)
51775#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT (3U)
51778#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK)
51784#define IOMUXC_LPSR_GPR_GPR17_LOCK_MASK (0x1U)
51785#define IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT (0U)
51790#define IOMUXC_LPSR_GPR_GPR17_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK)
51791
51792#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK (0xFFFFFFF8U)
51793#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT (3U)
51796#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK)
51802#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK (0x10U)
51803#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT (4U)
51808#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK)
51809
51810#define IOMUXC_LPSR_GPR_GPR18_LOCK_MASK (0xFFFF0000U)
51811#define IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT (16U)
51814#define IOMUXC_LPSR_GPR_GPR18_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK)
51820#define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK (0x10U)
51821#define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT (4U)
51826#define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK)
51827
51828#define IOMUXC_LPSR_GPR_GPR19_LOCK_MASK (0xFFFF0000U)
51829#define IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT (16U)
51832#define IOMUXC_LPSR_GPR_GPR19_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_LOCK_MASK)
51838#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK (0x10U)
51839#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT (4U)
51844#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK)
51845
51846#define IOMUXC_LPSR_GPR_GPR20_LOCK_MASK (0xFFFF0000U)
51847#define IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT (16U)
51850#define IOMUXC_LPSR_GPR_GPR20_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK)
51856#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK (0x10U)
51857#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT (4U)
51862#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK)
51863
51864#define IOMUXC_LPSR_GPR_GPR21_LOCK_MASK (0xFFFF0000U)
51865#define IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT (16U)
51868#define IOMUXC_LPSR_GPR_GPR21_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK)
51874#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK (0x10U)
51875#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT (4U)
51880#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK)
51881
51882#define IOMUXC_LPSR_GPR_GPR22_LOCK_MASK (0xFFFF0000U)
51883#define IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT (16U)
51886#define IOMUXC_LPSR_GPR_GPR22_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK)
51892#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK (0x10U)
51893#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT (4U)
51898#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK)
51899
51900#define IOMUXC_LPSR_GPR_GPR23_LOCK_MASK (0xFFFF0000U)
51901#define IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT (16U)
51904#define IOMUXC_LPSR_GPR_GPR23_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK)
51910#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK (0x10U)
51911#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT (4U)
51916#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK)
51917
51918#define IOMUXC_LPSR_GPR_GPR24_LOCK_MASK (0xFFFF0000U)
51919#define IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT (16U)
51922#define IOMUXC_LPSR_GPR_GPR24_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK)
51928#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK (0x10U)
51929#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT (4U)
51934#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK)
51935
51936#define IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK (0x20U)
51937#define IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT (5U)
51942#define IOMUXC_LPSR_GPR_GPR25_APC_VALID(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK)
51943
51944#define IOMUXC_LPSR_GPR_GPR25_LOCK_MASK (0xFFFF0000U)
51945#define IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT (16U)
51948#define IOMUXC_LPSR_GPR_GPR25_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK)
51954#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK (0x1FFFFFFU)
51955#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT (0U)
51959#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK)
51960
51961#define IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK (0xE000000U)
51962#define IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT (25U)
51965#define IOMUXC_LPSR_GPR_GPR26_FIELD_0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK)
51966
51967#define IOMUXC_LPSR_GPR_GPR26_DWP_MASK (0x30000000U)
51968#define IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT (28U)
51975#define IOMUXC_LPSR_GPR_GPR26_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK)
51976
51977#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK (0xC0000000U)
51978#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT (30U)
51985#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK)
51991#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK (0x1U)
51992#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT (0U)
51995#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK)
51996
51997#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK (0x100U)
51998#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT (8U)
52001#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK)
52002
52003#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK (0x200U)
52004#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT (9U)
52007#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK)
52008
52009#define IOMUXC_LPSR_GPR_GPR33_DWP_MASK (0x30000000U)
52010#define IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT (28U)
52017#define IOMUXC_LPSR_GPR_GPR33_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK)
52018
52019#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK (0xC0000000U)
52020#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT (30U)
52027#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK)
52033#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK (0x2U)
52034#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT (1U)
52037#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK)
52038
52039#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK (0x4U)
52040#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT (2U)
52043#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK)
52044
52045#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK (0x8U)
52046#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT (3U)
52051#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK)
52052
52053#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK (0x10U)
52054#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT (4U)
52059#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK)
52060
52061#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK (0x20U)
52062#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT (5U)
52067#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK)
52068
52069#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK (0x800U)
52070#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT (11U)
52075#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK)
52076
52077#define IOMUXC_LPSR_GPR_GPR34_DWP_MASK (0x30000000U)
52078#define IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT (28U)
52085#define IOMUXC_LPSR_GPR_GPR34_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK)
52086
52087#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK (0xC0000000U)
52088#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT (30U)
52095#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK)
52101#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK (0x1U)
52102#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT (0U)
52107#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK)
52108
52109#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK (0x2U)
52110#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT (1U)
52115#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK)
52116
52117#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK (0x4U)
52118#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT (2U)
52123#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK)
52124
52125#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK (0x8U)
52126#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT (3U)
52131#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK)
52132
52133#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK (0x10U)
52134#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT (4U)
52139#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK)
52140
52141#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK (0x20U)
52142#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT (5U)
52147#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK)
52148
52149#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK (0x40U)
52150#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT (6U)
52155#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK)
52156
52157#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK (0x80U)
52158#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT (7U)
52163#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK)
52164
52165#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK (0x100U)
52166#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT (8U)
52171#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK)
52172
52173#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK (0x200U)
52174#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT (9U)
52179#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK)
52180
52181#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK (0x400U)
52182#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT (10U)
52187#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK)
52188
52189#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK (0x800U)
52190#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT (11U)
52195#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK)
52196
52197#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK (0x1000U)
52198#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT (12U)
52203#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK)
52204
52205#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK (0x2000U)
52206#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT (13U)
52211#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK)
52212
52213#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK (0x8000U)
52214#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT (15U)
52219#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK)
52220
52221#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK (0x10000U)
52222#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT (16U)
52227#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK)
52228
52229#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK (0x20000U)
52230#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT (17U)
52235#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK)
52236
52237#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK (0x40000U)
52238#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT (18U)
52243#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK)
52244
52245#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK (0x80000U)
52246#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT (19U)
52251#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK)
52252
52253#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK (0x100000U)
52254#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT (20U)
52259#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK)
52260
52261#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK (0x200000U)
52262#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT (21U)
52267#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK)
52268
52269#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK (0x400000U)
52270#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT (22U)
52275#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK)
52276
52277#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK (0x800000U)
52278#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT (23U)
52283#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK)
52284
52285#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK (0x1000000U)
52286#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT (24U)
52291#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK)
52292
52293#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK (0x2000000U)
52294#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT (25U)
52299#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK)
52300
52301#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK (0x4000000U)
52302#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT (26U)
52307#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK)
52308
52309#define IOMUXC_LPSR_GPR_GPR35_DWP_MASK (0x30000000U)
52310#define IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT (28U)
52317#define IOMUXC_LPSR_GPR_GPR35_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK)
52318
52319#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK (0xC0000000U)
52320#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT (30U)
52327#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK)
52333#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK (0x1U)
52334#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT (0U)
52339#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK)
52340
52341#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK (0x2U)
52342#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT (1U)
52347#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK)
52348
52349#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK (0x4U)
52350#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT (2U)
52355#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK)
52356
52357#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK (0x8U)
52358#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT (3U)
52363#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK)
52364
52365#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK (0x10U)
52366#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT (4U)
52371#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK)
52372
52373#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK (0x20U)
52374#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT (5U)
52379#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK)
52380
52381#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK (0x40U)
52382#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT (6U)
52387#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK)
52388
52389#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK (0x80U)
52390#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT (7U)
52395#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK)
52396
52397#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK (0x100U)
52398#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT (8U)
52403#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK)
52404
52405#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK (0x200U)
52406#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT (9U)
52411#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK)
52412
52413#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK (0x400U)
52414#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT (10U)
52419#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK)
52420
52421#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK (0x800U)
52422#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT (11U)
52427#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK)
52428
52429#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK (0x1000U)
52430#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT (12U)
52435#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK)
52436
52437#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK (0x2000U)
52438#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT (13U)
52443#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK)
52444
52445#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK (0x4000U)
52446#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT (14U)
52451#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK)
52452
52453#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK (0x8000U)
52454#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT (15U)
52459#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK)
52460
52461#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK (0x10000U)
52462#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT (16U)
52467#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK)
52468
52469#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK (0x20000U)
52470#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT (17U)
52475#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK)
52476
52477#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK (0x40000U)
52478#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT (18U)
52483#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK)
52484
52485#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK (0x80000U)
52486#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT (19U)
52491#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK)
52492
52493#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK (0x100000U)
52494#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT (20U)
52499#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK)
52500
52501#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK (0x200000U)
52502#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT (21U)
52507#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK)
52508
52509#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK (0x400000U)
52510#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT (22U)
52515#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK)
52516
52517#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK (0x800000U)
52518#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT (23U)
52523#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK)
52524
52525#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK (0x1000000U)
52526#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT (24U)
52531#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK)
52532
52533#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK (0x2000000U)
52534#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT (25U)
52539#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK)
52540
52541#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U)
52542#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT (26U)
52547#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK)
52548
52549#define IOMUXC_LPSR_GPR_GPR36_DWP_MASK (0x30000000U)
52550#define IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT (28U)
52557#define IOMUXC_LPSR_GPR_GPR36_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK)
52558
52559#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK (0xC0000000U)
52560#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT (30U)
52567#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK)
52573#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK (0x1U)
52574#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT (0U)
52579#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK)
52580
52581#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK (0x2U)
52582#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT (1U)
52587#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK)
52588
52589#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK (0x4U)
52590#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT (2U)
52595#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK)
52596
52597#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK (0x8U)
52598#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT (3U)
52603#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK)
52604
52605#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK (0x10U)
52606#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT (4U)
52611#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK)
52612
52613#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK (0x20U)
52614#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT (5U)
52619#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK)
52620
52621#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK (0x40U)
52622#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT (6U)
52627#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK)
52628
52629#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK (0x80U)
52630#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT (7U)
52635#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK)
52636
52637#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK (0x100U)
52638#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT (8U)
52643#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK)
52644
52645#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK (0x200U)
52646#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT (9U)
52651#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK)
52652
52653#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK (0x400U)
52654#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT (10U)
52659#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK)
52660
52661#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK (0x800U)
52662#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT (11U)
52667#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK)
52668
52669#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK (0x1000U)
52670#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT (12U)
52675#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK)
52676
52677#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK (0x2000U)
52678#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT (13U)
52683#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK)
52684
52685#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK (0x4000U)
52686#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT (14U)
52691#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK)
52692
52693#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK (0x8000U)
52694#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT (15U)
52699#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK)
52700
52701#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK (0x10000U)
52702#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT (16U)
52707#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK)
52708
52709#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK (0x20000U)
52710#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT (17U)
52715#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK)
52716
52717#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK (0x40000U)
52718#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT (18U)
52723#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK)
52724
52725#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK (0x80000U)
52726#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT (19U)
52731#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK)
52732
52733#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK (0x100000U)
52734#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT (20U)
52739#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK)
52740
52741#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK (0x200000U)
52742#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT (21U)
52747#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK)
52748
52749#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK (0x400000U)
52750#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT (22U)
52755#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK)
52756
52757#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK (0x800000U)
52758#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT (23U)
52763#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK)
52764
52765#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK (0x1000000U)
52766#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT (24U)
52771#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK)
52772
52773#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK (0x2000000U)
52774#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT (25U)
52779#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK)
52780
52781#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK (0x4000000U)
52782#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT (26U)
52787#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK)
52788
52789#define IOMUXC_LPSR_GPR_GPR37_DWP_MASK (0x30000000U)
52790#define IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT (28U)
52797#define IOMUXC_LPSR_GPR_GPR37_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK)
52798
52799#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK (0xC0000000U)
52800#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT (30U)
52807#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK)
52813#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK (0x1U)
52814#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT (0U)
52819#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK)
52820
52821#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK (0x2U)
52822#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT (1U)
52827#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK)
52828
52829#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK (0x4U)
52830#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT (2U)
52835#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK)
52836
52837#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK (0x8U)
52838#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT (3U)
52843#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK)
52844
52845#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK (0x10U)
52846#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT (4U)
52851#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK)
52852
52853#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK (0x20U)
52854#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT (5U)
52859#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK)
52860
52861#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK (0x40U)
52862#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT (6U)
52867#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK)
52868
52869#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK (0x80U)
52870#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT (7U)
52875#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK)
52876
52877#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK (0x100U)
52878#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT (8U)
52883#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK)
52884
52885#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK (0x200U)
52886#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT (9U)
52891#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK)
52892
52893#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK (0x400U)
52894#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT (10U)
52899#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK)
52900
52901#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK (0x800U)
52902#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT (11U)
52907#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK)
52908
52909#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK (0x1000U)
52910#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT (12U)
52915#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK)
52916
52917#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK (0x2000U)
52918#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT (13U)
52923#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK)
52924
52925#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK (0x4000U)
52926#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT (14U)
52931#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK)
52932
52933#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK (0x8000U)
52934#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT (15U)
52939#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK)
52940
52941#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK (0x10000U)
52942#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT (16U)
52947#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK)
52948
52949#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK (0x20000U)
52950#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT (17U)
52955#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK)
52956
52957#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK (0x40000U)
52958#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT (18U)
52963#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK)
52964
52965#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK (0x80000U)
52966#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT (19U)
52971#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK)
52972
52973#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK (0x100000U)
52974#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT (20U)
52979#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK)
52980
52981#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK (0x200000U)
52982#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT (21U)
52987#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK)
52988
52989#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK (0x400000U)
52990#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT (22U)
52995#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK)
52996
52997#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK (0x800000U)
52998#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT (23U)
53003#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK)
53004
53005#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK (0x1000000U)
53006#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT (24U)
53011#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK)
53012
53013#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK (0x2000000U)
53014#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT (25U)
53019#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK)
53020
53021#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK (0x4000000U)
53022#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT (26U)
53027#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK)
53028
53029#define IOMUXC_LPSR_GPR_GPR38_DWP_MASK (0x30000000U)
53030#define IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT (28U)
53037#define IOMUXC_LPSR_GPR_GPR38_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK)
53038
53039#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK (0xC0000000U)
53040#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT (30U)
53047#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK)
53053#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK (0x2U)
53054#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT (1U)
53059#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK)
53060
53061#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK (0x4U)
53062#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT (2U)
53067#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK)
53068
53069#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK (0x8U)
53070#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT (3U)
53075#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK)
53076
53077#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK (0x10U)
53078#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT (4U)
53083#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK)
53084
53085#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK (0x20U)
53086#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT (5U)
53091#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK)
53092
53093#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK (0x40U)
53094#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT (6U)
53099#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK)
53100
53101#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK (0x80U)
53102#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT (7U)
53107#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK)
53108
53109#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK (0x100U)
53110#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT (8U)
53115#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK)
53116
53117#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK (0x200U)
53118#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT (9U)
53123#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK)
53124
53125#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK (0x400U)
53126#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT (10U)
53131#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK)
53132
53133#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK (0x800U)
53134#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT (11U)
53139#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK)
53140
53141#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK (0x1000U)
53142#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT (12U)
53147#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK)
53148
53149#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK (0x2000U)
53150#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT (13U)
53155#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK)
53156
53157#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U)
53158#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT (14U)
53163#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK)
53164
53165#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK (0x8000U)
53166#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT (15U)
53171#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK)
53172
53173#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U)
53174#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT (16U)
53179#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK)
53180
53181#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK (0x20000U)
53182#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT (17U)
53187#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK)
53188
53189#define IOMUXC_LPSR_GPR_GPR39_DWP_MASK (0x30000000U)
53190#define IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT (28U)
53197#define IOMUXC_LPSR_GPR_GPR39_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK)
53198
53199#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK (0xC0000000U)
53200#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT (30U)
53207#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK)
53213#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK (0x1U)
53214#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT (0U)
53217#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK)
53218
53219#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK (0x2U)
53220#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT (1U)
53223#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK)
53224
53225#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK (0x4U)
53226#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT (2U)
53229#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK)
53230
53231#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK (0x8U)
53232#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT (3U)
53235#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK)
53236
53237#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK (0x10U)
53238#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT (4U)
53241#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK)
53242
53243#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK (0x20U)
53244#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT (5U)
53247#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK)
53248
53249#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK (0x40U)
53250#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT (6U)
53253#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK)
53254
53255#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK (0x80U)
53256#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT (7U)
53259#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK)
53260
53261#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK (0x100U)
53262#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT (8U)
53265#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK)
53266
53267#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK (0x200U)
53268#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT (9U)
53271#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK)
53272
53273#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK (0x400U)
53274#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT (10U)
53277#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK)
53278
53279#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK (0x800U)
53280#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT (11U)
53283#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK)
53284
53285#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK (0x1000U)
53286#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT (12U)
53289#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK)
53290
53291#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK (0x2000U)
53292#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT (13U)
53295#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK)
53296
53297#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK (0x4000U)
53298#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT (14U)
53301#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK)
53302
53303#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK (0x8000U)
53304#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT (15U)
53307#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK)
53308
53309#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK (0x10000U)
53310#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT (16U)
53313#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK)
53314
53315#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK (0x20000U)
53316#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT (17U)
53319#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK)
53320
53321#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK (0x40000U)
53322#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT (18U)
53325#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK)
53326
53327#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK (0x80000U)
53328#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT (19U)
53331#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK)
53332
53333#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK (0x100000U)
53334#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT (20U)
53337#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK)
53338
53339#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK (0x200000U)
53340#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT (21U)
53343#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK)
53344
53345#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK (0x400000U)
53346#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT (22U)
53349#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK)
53350
53351#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK (0x800000U)
53352#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT (23U)
53355#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK)
53356
53357#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK (0x1000000U)
53358#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT (24U)
53361#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK)
53362
53363#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK (0x2000000U)
53364#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT (25U)
53367#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK)
53368
53369#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK (0x4000000U)
53370#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT (26U)
53373#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK)
53374
53375#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK (0x8000000U)
53376#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT (27U)
53379#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK)
53380
53381#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK (0x10000000U)
53382#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT (28U)
53385#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK)
53386
53387#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK (0x20000000U)
53388#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT (29U)
53391#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK)
53392
53393#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK (0x40000000U)
53394#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT (30U)
53397#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK)
53398
53399#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK (0x80000000U)
53400#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT (31U)
53403#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK)
53409#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK (0x1U)
53410#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT (0U)
53413#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK)
53414
53415#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK (0x2U)
53416#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT (1U)
53419#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK)
53420
53421#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK (0x4U)
53422#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT (2U)
53425#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK)
53426
53427#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK (0x8U)
53428#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT (3U)
53431#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK)
53432
53433#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK (0x10U)
53434#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT (4U)
53437#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK)
53438
53439#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK (0x20U)
53440#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT (5U)
53443#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK)
53444
53445#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK (0x40U)
53446#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT (6U)
53449#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK)
53450
53451#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK (0x80U)
53452#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT (7U)
53455#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK)
53456
53457#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK (0x100U)
53458#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT (8U)
53461#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK)
53462
53463#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK (0x200U)
53464#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT (9U)
53467#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK)
53468
53469#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK (0x400U)
53470#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT (10U)
53473#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK)
53474
53475#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK (0x800U)
53476#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT (11U)
53479#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK)
53480
53481#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK (0x1000U)
53482#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT (12U)
53485#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK)
53486
53487#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U)
53488#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT (13U)
53491#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK)
53492
53493#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK (0x4000U)
53494#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT (14U)
53497#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK)
53498
53499#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U)
53500#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT (15U)
53503#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK)
53504
53505#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK (0x10000U)
53506#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT (16U)
53509#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK)
53510
53511#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK (0x1000000U)
53512#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT (24U)
53515#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK) /* end of group IOMUXC_LPSR_GPR_Register_Masks */
53522
53523
53524/* IOMUXC_LPSR_GPR - Peripheral instance base addresses */
53526#define IOMUXC_LPSR_GPR_BASE (0x40C0C000u)
53528#define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE)
53530#define IOMUXC_LPSR_GPR_BASE_ADDRS { IOMUXC_LPSR_GPR_BASE }
53532#define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
53533 /* end of group IOMUXC_LPSR_GPR_Peripheral_Access_Layer */
53537
53538
53539/* ----------------------------------------------------------------------------
53540 -- IOMUXC_SNVS Peripheral Access Layer
53541 ---------------------------------------------------------------------------- */
53542
53549typedef struct {
53550 __IO uint32_t SW_MUX_CTL_PAD_WAKEUP_DIG;
53551 __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG;
53552 __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG;
53553 __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG;
53554 __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG;
53555 __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG;
53556 __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG;
53557 __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG;
53558 __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG;
53559 __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG;
53560 __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG;
53561 __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG;
53562 __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG;
53563 __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE_DIG;
53564 __IO uint32_t SW_PAD_CTL_PAD_POR_B_DIG;
53565 __IO uint32_t SW_PAD_CTL_PAD_ONOFF_DIG;
53566 __IO uint32_t SW_PAD_CTL_PAD_WAKEUP_DIG;
53567 __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG;
53568 __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG;
53569 __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG;
53570 __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG;
53571 __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG;
53572 __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG;
53573 __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG;
53574 __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG;
53575 __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG;
53576 __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG;
53577 __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG;
53578 __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG;
53580
53581/* ----------------------------------------------------------------------------
53582 -- IOMUXC_SNVS Register Masks
53583 ---------------------------------------------------------------------------- */
53584
53593#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK (0x7U)
53594#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT (0U)
53599#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK)
53600
53601#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK (0x10U)
53602#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT (4U)
53607#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK)
53613#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK (0x7U)
53614#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT (0U)
53619#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK)
53620
53621#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK (0x10U)
53622#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT (4U)
53627#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK)
53633#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK (0x7U)
53634#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT (0U)
53639#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK)
53640
53641#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK (0x10U)
53642#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT (4U)
53647#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK)
53653#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK (0x7U)
53654#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT (0U)
53659#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK)
53660
53661#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK (0x10U)
53662#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT (4U)
53667#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK)
53673#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK (0x7U)
53674#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT (0U)
53679#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK)
53680
53681#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK (0x10U)
53682#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT (4U)
53687#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK)
53693#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK (0x7U)
53694#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT (0U)
53699#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK)
53700
53701#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK (0x10U)
53702#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT (4U)
53707#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK)
53713#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK (0x7U)
53714#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT (0U)
53719#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK)
53720
53721#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK (0x10U)
53722#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT (4U)
53727#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK)
53733#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK (0x7U)
53734#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT (0U)
53739#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK)
53740
53741#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK (0x10U)
53742#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT (4U)
53747#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK)
53753#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK (0x7U)
53754#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT (0U)
53759#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK)
53760
53761#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK (0x10U)
53762#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT (4U)
53767#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK)
53773#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK (0x7U)
53774#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT (0U)
53779#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK)
53780
53781#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK (0x10U)
53782#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT (4U)
53787#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK)
53793#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK (0x7U)
53794#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT (0U)
53799#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK)
53800
53801#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK (0x10U)
53802#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT (4U)
53807#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK)
53813#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK (0x7U)
53814#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT (0U)
53819#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK)
53820
53821#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK (0x10U)
53822#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT (4U)
53827#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK)
53833#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK (0x7U)
53834#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT (0U)
53839#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK)
53840
53841#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK (0x10U)
53842#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT (4U)
53847#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK)
53853#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK (0x1U)
53854#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT (0U)
53859#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK)
53860
53861#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK (0x2U)
53862#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT (1U)
53867#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK)
53868
53869#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK (0x4U)
53870#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT (2U)
53875#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK)
53876
53877#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK (0x8U)
53878#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT (3U)
53883#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK)
53884
53885#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK (0x30000000U)
53886#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT (28U)
53893#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK)
53894
53895#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK (0xC0000000U)
53896#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT (30U)
53903#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK)
53909#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK (0x1U)
53910#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT (0U)
53915#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK)
53916
53917#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK (0x2U)
53918#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT (1U)
53923#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK)
53924
53925#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK (0x4U)
53926#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT (2U)
53931#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK)
53932
53933#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK (0x8U)
53934#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT (3U)
53939#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK)
53940
53941#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK (0x30000000U)
53942#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT (28U)
53949#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK)
53950
53951#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK (0xC0000000U)
53952#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT (30U)
53959#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK)
53965#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK (0x1U)
53966#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT (0U)
53971#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK)
53972
53973#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK (0x2U)
53974#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT (1U)
53979#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK)
53980
53981#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK (0x4U)
53982#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT (2U)
53987#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK)
53988
53989#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK (0x8U)
53990#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT (3U)
53995#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK)
53996
53997#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK (0x30000000U)
53998#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT (28U)
54005#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK)
54006
54007#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK (0xC0000000U)
54008#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT (30U)
54015#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK)
54021#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK (0x1U)
54022#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT (0U)
54027#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK)
54028
54029#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK (0x2U)
54030#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT (1U)
54035#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK)
54036
54037#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK (0x4U)
54038#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT (2U)
54043#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK)
54044
54045#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK (0x8U)
54046#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT (3U)
54051#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK)
54052
54053#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK (0x40U)
54054#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT (6U)
54059#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK)
54060
54061#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK (0x30000000U)
54062#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT (28U)
54069#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK)
54070
54071#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK (0xC0000000U)
54072#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT (30U)
54079#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK)
54085#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK (0x1U)
54086#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT (0U)
54091#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK)
54092
54093#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK (0x2U)
54094#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT (1U)
54099#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK)
54100
54101#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK (0x4U)
54102#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT (2U)
54107#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK)
54108
54109#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK (0x8U)
54110#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT (3U)
54115#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK)
54116
54117#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK (0x40U)
54118#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT (6U)
54123#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK)
54124
54125#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK (0x30000000U)
54126#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT (28U)
54133#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK)
54134
54135#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)
54136#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT (30U)
54143#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK)
54149#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK (0x1U)
54150#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT (0U)
54155#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK)
54156
54157#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK (0x2U)
54158#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT (1U)
54163#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK)
54164
54165#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK (0x4U)
54166#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT (2U)
54171#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK)
54172
54173#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK (0x8U)
54174#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT (3U)
54179#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK)
54180
54181#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK (0x40U)
54182#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT (6U)
54187#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK)
54188
54189#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK (0x30000000U)
54190#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT (28U)
54197#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK)
54198
54199#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)
54200#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT (30U)
54207#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK)
54213#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK (0x1U)
54214#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT (0U)
54219#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK)
54220
54221#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK (0x2U)
54222#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT (1U)
54227#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK)
54228
54229#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK (0x4U)
54230#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT (2U)
54235#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK)
54236
54237#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK (0x8U)
54238#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT (3U)
54243#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK)
54244
54245#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK (0x40U)
54246#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT (6U)
54251#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK)
54252
54253#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK (0x30000000U)
54254#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT (28U)
54261#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK)
54262
54263#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK (0xC0000000U)
54264#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT (30U)
54271#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK)
54277#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK (0x1U)
54278#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT (0U)
54283#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK)
54284
54285#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK (0x2U)
54286#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT (1U)
54291#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK)
54292
54293#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK (0x4U)
54294#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT (2U)
54299#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK)
54300
54301#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK (0x8U)
54302#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT (3U)
54307#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK)
54308
54309#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK (0x40U)
54310#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT (6U)
54315#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK)
54316
54317#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK (0x30000000U)
54318#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT (28U)
54325#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK)
54326
54327#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK (0xC0000000U)
54328#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT (30U)
54335#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK)
54341#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK (0x1U)
54342#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT (0U)
54347#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK)
54348
54349#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK (0x2U)
54350#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT (1U)
54355#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK)
54356
54357#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK (0x4U)
54358#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT (2U)
54363#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK)
54364
54365#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK (0x8U)
54366#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT (3U)
54371#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK)
54372
54373#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK (0x40U)
54374#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT (6U)
54379#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK)
54380
54381#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK (0x30000000U)
54382#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT (28U)
54389#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK)
54390
54391#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK (0xC0000000U)
54392#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT (30U)
54399#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK)
54405#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK (0x1U)
54406#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT (0U)
54411#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK)
54412
54413#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK (0x2U)
54414#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT (1U)
54419#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK)
54420
54421#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK (0x4U)
54422#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT (2U)
54427#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK)
54428
54429#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK (0x8U)
54430#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT (3U)
54435#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK)
54436
54437#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK (0x40U)
54438#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT (6U)
54443#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK)
54444
54445#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK (0x30000000U)
54446#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT (28U)
54453#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK)
54454
54455#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK (0xC0000000U)
54456#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT (30U)
54463#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK)
54469#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK (0x1U)
54470#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT (0U)
54475#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK)
54476
54477#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK (0x2U)
54478#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT (1U)
54483#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK)
54484
54485#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK (0x4U)
54486#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT (2U)
54491#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK)
54492
54493#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK (0x8U)
54494#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT (3U)
54499#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK)
54500
54501#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK (0x40U)
54502#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT (6U)
54507#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK)
54508
54509#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK (0x30000000U)
54510#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT (28U)
54517#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK)
54518
54519#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK (0xC0000000U)
54520#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT (30U)
54527#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK)
54533#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK (0x1U)
54534#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT (0U)
54539#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK)
54540
54541#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK (0x2U)
54542#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT (1U)
54547#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK)
54548
54549#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK (0x4U)
54550#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT (2U)
54555#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK)
54556
54557#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK (0x8U)
54558#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT (3U)
54563#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK)
54564
54565#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK (0x40U)
54566#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT (6U)
54571#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK)
54572
54573#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK (0x30000000U)
54574#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT (28U)
54581#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK)
54582
54583#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK (0xC0000000U)
54584#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT (30U)
54591#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK)
54597#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK (0x1U)
54598#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT (0U)
54603#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK)
54604
54605#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK (0x2U)
54606#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT (1U)
54611#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK)
54612
54613#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK (0x4U)
54614#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT (2U)
54619#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK)
54620
54621#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK (0x8U)
54622#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT (3U)
54627#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK)
54628
54629#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK (0x40U)
54630#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT (6U)
54635#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK)
54636
54637#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK (0x30000000U)
54638#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT (28U)
54645#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK)
54646
54647#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK (0xC0000000U)
54648#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT (30U)
54655#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK)
54661#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK (0x1U)
54662#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT (0U)
54667#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK)
54668
54669#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK (0x2U)
54670#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT (1U)
54675#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK)
54676
54677#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK (0x4U)
54678#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT (2U)
54683#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK)
54684
54685#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK (0x8U)
54686#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT (3U)
54691#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK)
54692
54693#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK (0x40U)
54694#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT (6U)
54699#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK)
54700
54701#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK (0x30000000U)
54702#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT (28U)
54709#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK)
54710
54711#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK (0xC0000000U)
54712#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT (30U)
54719#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK)
54725#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK (0x1U)
54726#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT (0U)
54731#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK)
54732
54733#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK (0x2U)
54734#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT (1U)
54739#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK)
54740
54741#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK (0x4U)
54742#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT (2U)
54747#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK)
54748
54749#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK (0x8U)
54750#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT (3U)
54755#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK)
54756
54757#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK (0x40U)
54758#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT (6U)
54763#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK)
54764
54765#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK (0x30000000U)
54766#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT (28U)
54773#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK)
54774
54775#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK (0xC0000000U)
54776#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT (30U)
54783#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK)
54789#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK (0x1U)
54790#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT (0U)
54795#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK)
54796
54797#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK (0x2U)
54798#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT (1U)
54803#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK)
54804
54805#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK (0x4U)
54806#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT (2U)
54811#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK)
54812
54813#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK (0x8U)
54814#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT (3U)
54819#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK)
54820
54821#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK (0x40U)
54822#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT (6U)
54827#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK)
54828
54829#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK (0x30000000U)
54830#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT (28U)
54837#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK)
54838
54839#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK (0xC0000000U)
54840#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT (30U)
54847#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK) /* end of group IOMUXC_SNVS_Register_Masks */
54854
54855
54856/* IOMUXC_SNVS - Peripheral instance base addresses */
54858#define IOMUXC_SNVS_BASE (0x40C94000u)
54860#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
54862#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }
54864#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }
54865 /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
54869
54870
54871/* ----------------------------------------------------------------------------
54872 -- IOMUXC_SNVS_GPR Peripheral Access Layer
54873 ---------------------------------------------------------------------------- */
54874
54881typedef struct {
54882 __IO uint32_t GPR[32];
54883 __IO uint32_t GPR32;
54884 __IO uint32_t GPR33;
54885 __IO uint32_t GPR34;
54886 __IO uint32_t GPR35;
54887 __IO uint32_t GPR36;
54888 __IO uint32_t GPR37;
54890
54891/* ----------------------------------------------------------------------------
54892 -- IOMUXC_SNVS_GPR Register Masks
54893 ---------------------------------------------------------------------------- */
54894
54903#define IOMUXC_SNVS_GPR_GPR_GPR_MASK (0xFFFFFFFFU)
54904#define IOMUXC_SNVS_GPR_GPR_GPR_SHIFT (0U)
54907#define IOMUXC_SNVS_GPR_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR_GPR_MASK)
54910/* The count of IOMUXC_SNVS_GPR_GPR */
54911#define IOMUXC_SNVS_GPR_GPR_COUNT (32U)
54912
54916#define IOMUXC_SNVS_GPR_GPR32_GPR_MASK (0xFFFEU)
54917#define IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT (1U)
54920#define IOMUXC_SNVS_GPR_GPR32_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK)
54921
54922#define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U)
54923#define IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT (16U)
54926#define IOMUXC_SNVS_GPR_GPR32_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
54932#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
54933#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
54938#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK)
54939
54940#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK (0x4U)
54941#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT (2U)
54946#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK)
54947
54948#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK (0x10000U)
54949#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT (16U)
54954#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK)
54955
54956#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK (0x20000U)
54957#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT (17U)
54962#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK)
54963
54964#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK (0x40000U)
54965#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT (18U)
54970#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK)
54971
54972#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK (0x80000U)
54973#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT (19U)
54978#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK)
54979
54980#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK (0x100000U)
54981#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT (20U)
54986#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK)
54992#define IOMUXC_SNVS_GPR_GPR34_LOCK_MASK (0x1U)
54993#define IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT (0U)
54998#define IOMUXC_SNVS_GPR_GPR34_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK)
54999
55000#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK (0x2U)
55001#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT (1U)
55006#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK)
55007
55008#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK (0xCU)
55009#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT (2U)
55012#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK)
55013
55014#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK (0x80U)
55015#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT (7U)
55020#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK)
55021
55022#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK (0xFF00U)
55023#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT (8U)
55026#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK)
55027
55028#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK (0x30000U)
55029#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT (16U)
55036#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK)
55037
55038#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK (0xC0000U)
55039#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT (18U)
55046#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK)
55047
55048#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK (0x800000U)
55049#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT (23U)
55054#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK)
55055
55056#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK (0xF000000U)
55057#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT (24U)
55060#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK)
55066#define IOMUXC_SNVS_GPR_GPR35_LOCK_MASK (0x1U)
55067#define IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT (0U)
55072#define IOMUXC_SNVS_GPR_GPR35_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK)
55073
55074#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK (0x8U)
55075#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT (3U)
55080#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK)
55081
55082#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK (0xFF0U)
55083#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT (4U)
55086#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK)
55087
55088#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK (0x8000U)
55089#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT (15U)
55094#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK)
55095
55096#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK (0xFFF0000U)
55097#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT (16U)
55100#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK)
55101
55102#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK (0x30000000U)
55103#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT (28U)
55110#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK)
55111
55112#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK (0xC0000000U)
55113#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT (30U)
55120#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK)
55126#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK (0x800000U)
55127#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT (23U)
55132#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK)
55133
55134#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK (0x4000000U)
55135#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT (26U)
55142#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK)
55143
55144#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK (0x8000000U)
55145#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT (27U)
55150#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK)
55151
55152#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK (0x10000000U)
55153#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT (28U)
55158#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK)
55159
55160#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK (0x20000000U)
55161#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT (29U)
55166#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK)
55167
55168#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK (0x40000000U)
55169#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT (30U)
55174#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK)
55175
55176#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK (0x80000000U)
55177#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT (31U)
55182#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK)
55188#define IOMUXC_SNVS_GPR_GPR37_LOCK_MASK (0x1U)
55189#define IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT (0U)
55194#define IOMUXC_SNVS_GPR_GPR37_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK)
55195
55196#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK (0x7FEU)
55197#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT (1U)
55200#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK)
55201
55202#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK (0x1FF800U)
55203#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT (11U)
55206#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK) /* end of group IOMUXC_SNVS_GPR_Register_Masks */
55213
55214
55215/* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
55217#define IOMUXC_SNVS_GPR_BASE (0x40C98000u)
55219#define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
55221#define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }
55223#define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }
55224 /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
55228
55229
55230/* ----------------------------------------------------------------------------
55231 -- IPS_DOMAIN Peripheral Access Layer
55232 ---------------------------------------------------------------------------- */
55233
55240typedef struct {
55241 struct { /* offset: 0x0, array step: 0x10 */
55242 __IO uint32_t SLOT_CTRL;
55243 uint8_t RESERVED_0[12];
55244 } SLOT_CTRL[38];
55246
55247/* ----------------------------------------------------------------------------
55248 -- IPS_DOMAIN Register Masks
55249 ---------------------------------------------------------------------------- */
55250
55259#define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU)
55260#define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U)
55263#define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK)
55264
55265#define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK (0x8000U)
55266#define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT (15U)
55271#define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK)
55272
55273#define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK (0x10000U)
55274#define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT (16U)
55279#define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK)
55280
55281#define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK (0x20000U)
55282#define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT (17U)
55287#define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK)
55288
55289#define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK (0x80000000U)
55290#define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT (31U)
55295#define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK)
55298/* The count of IPS_DOMAIN_SLOT_CTRL */
55299#define IPS_DOMAIN_SLOT_CTRL_COUNT (38U)
55300
55301 /* end of group IPS_DOMAIN_Register_Masks */
55305
55306
55307/* IPS_DOMAIN - Peripheral instance base addresses */
55309#define IPS_DOMAIN_BASE (0x40C87C00u)
55311#define IPS_DOMAIN ((IPS_DOMAIN_Type *)IPS_DOMAIN_BASE)
55313#define IPS_DOMAIN_BASE_ADDRS { IPS_DOMAIN_BASE }
55315#define IPS_DOMAIN_BASE_PTRS { IPS_DOMAIN }
55316 /* end of group IPS_DOMAIN_Peripheral_Access_Layer */
55320
55321
55322/* ----------------------------------------------------------------------------
55323 -- KEY_MANAGER Peripheral Access Layer
55324 ---------------------------------------------------------------------------- */
55325
55332typedef struct {
55333 __IO uint32_t MASTER_KEY_CTRL;
55334 uint8_t RESERVED_0[12];
55335 __IO uint32_t OTFAD1_KEY_CTRL;
55336 uint8_t RESERVED_1[4];
55337 __IO uint32_t OTFAD2_KEY_CTRL;
55338 uint8_t RESERVED_2[4];
55339 __IO uint32_t IEE_KEY_CTRL;
55340 uint8_t RESERVED_3[12];
55341 __IO uint32_t PUF_KEY_CTRL;
55342 uint8_t RESERVED_4[972];
55343 __IO uint32_t SLOT0_CTRL;
55344 __IO uint32_t SLOT1_CTRL;
55345 __IO uint32_t SLOT2_CTRL;
55346 __IO uint32_t SLOT3_CTRL;
55347 __IO uint32_t SLOT4_CTRL;
55349
55350/* ----------------------------------------------------------------------------
55351 -- KEY_MANAGER Register Masks
55352 ---------------------------------------------------------------------------- */
55353
55362#define KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK (0x1U)
55363#define KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT (0U)
55368#define KEY_MANAGER_MASTER_KEY_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK)
55369
55370#define KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK (0x10000U)
55371#define KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT (16U)
55376#define KEY_MANAGER_MASTER_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK)
55382#define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK (0x1U)
55383#define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT (0U)
55388#define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK)
55389
55390#define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK (0x10000U)
55391#define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT (16U)
55396#define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK)
55402#define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK (0x1U)
55403#define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT (0U)
55408#define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK)
55409
55410#define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK (0x10000U)
55411#define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT (16U)
55416#define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK)
55422#define KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK (0x1U)
55423#define KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT (0U)
55428#define KEY_MANAGER_IEE_KEY_CTRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT)) & KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK)
55434#define KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK (0x1U)
55435#define KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT (0U)
55441#define KEY_MANAGER_PUF_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK)
55447#define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK (0xFU)
55448#define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT (0U)
55451#define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK)
55452
55453#define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK (0x8000U)
55454#define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT (15U)
55459#define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK)
55460
55461#define KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK (0x10000U)
55462#define KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT (16U)
55467#define KEY_MANAGER_SLOT0_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK)
55468
55469#define KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK (0x20000U)
55470#define KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT (17U)
55475#define KEY_MANAGER_SLOT0_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK)
55476
55477#define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK (0x80000000U)
55478#define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT (31U)
55483#define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK)
55489#define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK (0xFU)
55490#define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT (0U)
55493#define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK)
55494
55495#define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK (0x8000U)
55496#define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT (15U)
55501#define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK)
55502
55503#define KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK (0x10000U)
55504#define KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT (16U)
55509#define KEY_MANAGER_SLOT1_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK)
55510
55511#define KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK (0x20000U)
55512#define KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT (17U)
55517#define KEY_MANAGER_SLOT1_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK)
55518
55519#define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK (0x80000000U)
55520#define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT (31U)
55525#define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK)
55531#define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK (0xFU)
55532#define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT (0U)
55535#define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK)
55536
55537#define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK (0x8000U)
55538#define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT (15U)
55543#define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK)
55544
55545#define KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK (0x10000U)
55546#define KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT (16U)
55551#define KEY_MANAGER_SLOT2_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK)
55552
55553#define KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK (0x20000U)
55554#define KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT (17U)
55559#define KEY_MANAGER_SLOT2_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK)
55560
55561#define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK (0x80000000U)
55562#define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT (31U)
55567#define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK)
55573#define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK (0xFU)
55574#define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT (0U)
55577#define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK)
55578
55579#define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK (0x8000U)
55580#define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT (15U)
55585#define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK)
55586
55587#define KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK (0x10000U)
55588#define KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT (16U)
55593#define KEY_MANAGER_SLOT3_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK)
55594
55595#define KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK (0x20000U)
55596#define KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT (17U)
55601#define KEY_MANAGER_SLOT3_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK)
55602
55603#define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK (0x80000000U)
55604#define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT (31U)
55609#define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK)
55615#define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK (0xFU)
55616#define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT (0U)
55619#define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK)
55620
55621#define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK (0x8000U)
55622#define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT (15U)
55627#define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK)
55628
55629#define KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK (0x10000U)
55630#define KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT (16U)
55635#define KEY_MANAGER_SLOT4_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK)
55636
55637#define KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK (0x20000U)
55638#define KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT (17U)
55643#define KEY_MANAGER_SLOT4_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK)
55644
55645#define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK (0x80000000U)
55646#define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT (31U)
55651#define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK) /* end of group KEY_MANAGER_Register_Masks */
55658
55659
55660/* KEY_MANAGER - Peripheral instance base addresses */
55662#define KEY_MANAGER_BASE (0x40C80000u)
55664#define KEY_MANAGER ((KEY_MANAGER_Type *)KEY_MANAGER_BASE)
55666#define KEY_MANAGER_BASE_ADDRS { KEY_MANAGER_BASE }
55668#define KEY_MANAGER_BASE_PTRS { KEY_MANAGER }
55669 /* end of group KEY_MANAGER_Peripheral_Access_Layer */
55673
55674
55675/* ----------------------------------------------------------------------------
55676 -- KPP Peripheral Access Layer
55677 ---------------------------------------------------------------------------- */
55678
55685typedef struct {
55686 __IO uint16_t KPCR;
55687 __IO uint16_t KPSR;
55688 __IO uint16_t KDDR;
55689 __IO uint16_t KPDR;
55690} KPP_Type;
55691
55692/* ----------------------------------------------------------------------------
55693 -- KPP Register Masks
55694 ---------------------------------------------------------------------------- */
55695
55704#define KPP_KPCR_KRE_MASK (0xFFU)
55705#define KPP_KPCR_KRE_SHIFT (0U)
55710#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
55711
55712#define KPP_KPCR_KCO_MASK (0xFF00U)
55713#define KPP_KPCR_KCO_SHIFT (8U)
55718#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
55724#define KPP_KPSR_KPKD_MASK (0x1U)
55725#define KPP_KPSR_KPKD_SHIFT (0U)
55730#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
55731
55732#define KPP_KPSR_KPKR_MASK (0x2U)
55733#define KPP_KPSR_KPKR_SHIFT (1U)
55738#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
55739
55740#define KPP_KPSR_KDSC_MASK (0x4U)
55741#define KPP_KPSR_KDSC_SHIFT (2U)
55746#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
55747
55748#define KPP_KPSR_KRSS_MASK (0x8U)
55749#define KPP_KPSR_KRSS_SHIFT (3U)
55754#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
55755
55756#define KPP_KPSR_KDIE_MASK (0x100U)
55757#define KPP_KPSR_KDIE_SHIFT (8U)
55762#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
55763
55764#define KPP_KPSR_KRIE_MASK (0x200U)
55765#define KPP_KPSR_KRIE_SHIFT (9U)
55770#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
55776#define KPP_KDDR_KRDD_MASK (0xFFU)
55777#define KPP_KDDR_KRDD_SHIFT (0U)
55782#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
55783
55784#define KPP_KDDR_KCDD_MASK (0xFF00U)
55785#define KPP_KDDR_KCDD_SHIFT (8U)
55790#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
55796#define KPP_KPDR_KRD_MASK (0xFFU)
55797#define KPP_KPDR_KRD_SHIFT (0U)
55800#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
55801
55802#define KPP_KPDR_KCD_MASK (0xFF00U)
55803#define KPP_KPDR_KCD_SHIFT (8U)
55806#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) /* end of group KPP_Register_Masks */
55813
55814
55815/* KPP - Peripheral instance base addresses */
55817#define KPP_BASE (0x400E0000u)
55819#define KPP ((KPP_Type *)KPP_BASE)
55821#define KPP_BASE_ADDRS { KPP_BASE }
55823#define KPP_BASE_PTRS { KPP }
55825#define KPP_IRQS { KPP_IRQn }
55826 /* end of group KPP_Peripheral_Access_Layer */
55830
55831
55832/* ----------------------------------------------------------------------------
55833 -- LCDIF Peripheral Access Layer
55834 ---------------------------------------------------------------------------- */
55835
55842typedef struct {
55843 __IO uint32_t CTRL;
55844 __IO uint32_t CTRL_SET;
55845 __IO uint32_t CTRL_CLR;
55846 __IO uint32_t CTRL_TOG;
55847 __IO uint32_t CTRL1;
55848 __IO uint32_t CTRL1_SET;
55849 __IO uint32_t CTRL1_CLR;
55850 __IO uint32_t CTRL1_TOG;
55851 __IO uint32_t CTRL2;
55852 __IO uint32_t CTRL2_SET;
55853 __IO uint32_t CTRL2_CLR;
55854 __IO uint32_t CTRL2_TOG;
55855 __IO uint32_t TRANSFER_COUNT;
55856 uint8_t RESERVED_0[12];
55857 __IO uint32_t CUR_BUF;
55858 uint8_t RESERVED_1[12];
55859 __IO uint32_t NEXT_BUF;
55860 uint8_t RESERVED_2[28];
55861 __IO uint32_t VDCTRL0;
55862 __IO uint32_t VDCTRL0_SET;
55863 __IO uint32_t VDCTRL0_CLR;
55864 __IO uint32_t VDCTRL0_TOG;
55865 __IO uint32_t VDCTRL1;
55866 uint8_t RESERVED_3[12];
55867 __IO uint32_t VDCTRL2;
55868 uint8_t RESERVED_4[12];
55869 __IO uint32_t VDCTRL3;
55870 uint8_t RESERVED_5[12];
55871 __IO uint32_t VDCTRL4;
55872 uint8_t RESERVED_6[220];
55873 __IO uint32_t BM_ERROR_STAT;
55874 uint8_t RESERVED_7[12];
55875 __IO uint32_t CRC_STAT;
55876 uint8_t RESERVED_8[12];
55877 __I uint32_t STAT;
55878 uint8_t RESERVED_9[76];
55879 __IO uint32_t THRES;
55880 uint8_t RESERVED_10[380];
55881 __IO uint32_t PIGEONCTRL0;
55882 __IO uint32_t PIGEONCTRL0_SET;
55883 __IO uint32_t PIGEONCTRL0_CLR;
55884 __IO uint32_t PIGEONCTRL0_TOG;
55885 __IO uint32_t PIGEONCTRL1;
55886 __IO uint32_t PIGEONCTRL1_SET;
55887 __IO uint32_t PIGEONCTRL1_CLR;
55888 __IO uint32_t PIGEONCTRL1_TOG;
55889 __IO uint32_t PIGEONCTRL2;
55890 __IO uint32_t PIGEONCTRL2_SET;
55891 __IO uint32_t PIGEONCTRL2_CLR;
55892 __IO uint32_t PIGEONCTRL2_TOG;
55893 uint8_t RESERVED_11[1104];
55894 struct { /* offset: 0x800, array step: 0x40 */
55895 __IO uint32_t PIGEON_0;
55896 uint8_t RESERVED_0[12];
55897 __IO uint32_t PIGEON_1;
55898 uint8_t RESERVED_1[12];
55899 __IO uint32_t PIGEON_2;
55900 uint8_t RESERVED_2[28];
55901 } PIGEON[12];
55902 __IO uint32_t LUT_CTRL;
55903 uint8_t RESERVED_12[12];
55904 __IO uint32_t LUT0_ADDR;
55905 uint8_t RESERVED_13[12];
55906 __IO uint32_t LUT0_DATA;
55907 uint8_t RESERVED_14[12];
55908 __IO uint32_t LUT1_ADDR;
55909 uint8_t RESERVED_15[12];
55910 __IO uint32_t LUT1_DATA;
55911} LCDIF_Type;
55912
55913/* ----------------------------------------------------------------------------
55914 -- LCDIF Register Masks
55915 ---------------------------------------------------------------------------- */
55916
55925#define LCDIF_CTRL_RUN_MASK (0x1U)
55926#define LCDIF_CTRL_RUN_SHIFT (0U)
55927#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
55928
55929#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)
55930#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)
55936#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
55937
55938#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)
55939#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)
55944#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
55945
55946#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)
55947#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)
55948#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
55949
55950#define LCDIF_CTRL_RSRVD0_MASK (0x10U)
55951#define LCDIF_CTRL_RSRVD0_SHIFT (4U)
55952#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
55953
55954#define LCDIF_CTRL_MASTER_MASK (0x20U)
55955#define LCDIF_CTRL_MASTER_SHIFT (5U)
55956#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
55957
55958#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
55959#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
55960#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
55961
55962#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)
55963#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)
55970#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
55971
55972#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)
55973#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)
55980#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
55981
55982#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)
55983#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)
55992#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
55993
55994#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)
55995#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)
56004#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
56005
56006#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)
56007#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)
56008#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
56009
56010#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)
56011#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)
56012#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
56013
56014#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)
56015#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)
56016#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
56017
56018#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)
56019#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)
56024#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
56025
56026#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U)
56027#define LCDIF_CTRL_CLKGATE_SHIFT (30U)
56028#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
56029
56030#define LCDIF_CTRL_SFTRST_MASK (0x80000000U)
56031#define LCDIF_CTRL_SFTRST_SHIFT (31U)
56032#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
56038#define LCDIF_CTRL_SET_RUN_MASK (0x1U)
56039#define LCDIF_CTRL_SET_RUN_SHIFT (0U)
56040#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
56041
56042#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)
56043#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)
56049#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
56050
56051#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)
56052#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)
56057#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
56058
56059#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)
56060#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)
56061#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
56062
56063#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)
56064#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)
56065#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
56066
56067#define LCDIF_CTRL_SET_MASTER_MASK (0x20U)
56068#define LCDIF_CTRL_SET_MASTER_SHIFT (5U)
56069#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
56070
56071#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
56072#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
56073#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
56074
56075#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)
56076#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)
56083#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
56084
56085#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)
56086#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)
56093#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
56094
56095#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)
56096#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)
56105#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
56106
56107#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)
56108#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)
56117#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
56118
56119#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)
56120#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)
56121#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
56122
56123#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)
56124#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)
56125#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
56126
56127#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)
56128#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)
56129#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
56130
56131#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)
56132#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)
56137#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
56138
56139#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)
56140#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)
56141#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
56142
56143#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)
56144#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U)
56145#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
56151#define LCDIF_CTRL_CLR_RUN_MASK (0x1U)
56152#define LCDIF_CTRL_CLR_RUN_SHIFT (0U)
56153#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
56154
56155#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)
56156#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)
56162#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
56163
56164#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)
56165#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)
56170#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
56171
56172#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)
56173#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)
56174#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
56175
56176#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)
56177#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)
56178#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
56179
56180#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U)
56181#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U)
56182#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
56183
56184#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
56185#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
56186#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
56187
56188#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)
56189#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)
56196#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
56197
56198#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)
56199#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)
56206#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
56207
56208#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)
56209#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)
56218#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
56219
56220#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)
56221#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)
56230#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
56231
56232#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)
56233#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)
56234#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
56235
56236#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)
56237#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)
56238#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
56239
56240#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)
56241#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)
56242#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
56243
56244#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)
56245#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)
56250#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
56251
56252#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)
56253#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)
56254#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
56255
56256#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)
56257#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)
56258#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
56264#define LCDIF_CTRL_TOG_RUN_MASK (0x1U)
56265#define LCDIF_CTRL_TOG_RUN_SHIFT (0U)
56266#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
56267
56268#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)
56269#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)
56275#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
56276
56277#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)
56278#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)
56283#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
56284
56285#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)
56286#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)
56287#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
56288
56289#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)
56290#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)
56291#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
56292
56293#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U)
56294#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U)
56295#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
56296
56297#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
56298#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
56299#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
56300
56301#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)
56302#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)
56309#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
56310
56311#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)
56312#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)
56319#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
56320
56321#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)
56322#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)
56331#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
56332
56333#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)
56334#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)
56343#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
56344
56345#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)
56346#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)
56347#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
56348
56349#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)
56350#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)
56351#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
56352
56353#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)
56354#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)
56355#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
56356
56357#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)
56358#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)
56363#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
56364
56365#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)
56366#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)
56367#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
56368
56369#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)
56370#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)
56371#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
56377#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U)
56378#define LCDIF_CTRL1_RSRVD0_SHIFT (3U)
56379#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
56380
56381#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)
56382#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)
56387#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
56388
56389#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)
56390#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)
56395#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
56396
56397#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)
56398#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)
56403#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
56404
56405#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)
56406#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)
56411#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
56412
56413#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
56414#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
56415#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
56416
56417#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
56418#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
56419#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
56420
56421#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)
56422#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)
56423#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
56424
56425#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)
56426#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)
56427#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
56428
56429#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)
56430#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)
56431#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
56432
56433#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
56434#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
56435#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
56436
56437#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)
56438#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)
56439#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
56440
56441#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
56442#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
56443#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
56444
56445#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)
56446#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)
56447#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
56448
56449#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
56450#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)
56451#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
56452
56453#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)
56454#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)
56459#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
56460
56461#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)
56462#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)
56463#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
56464
56465#define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)
56466#define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)
56467#define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)
56468
56469#define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)
56470#define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)
56471#define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)
56477#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)
56478#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)
56479#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
56480
56481#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)
56482#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)
56487#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
56488
56489#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)
56490#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
56495#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
56496
56497#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)
56498#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)
56503#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
56504
56505#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)
56506#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)
56511#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
56512
56513#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
56514#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
56515#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
56516
56517#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
56518#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
56519#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
56520
56521#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)
56522#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)
56523#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
56524
56525#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)
56526#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)
56527#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
56528
56529#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
56530#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
56531#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
56532
56533#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
56534#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
56535#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
56536
56537#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)
56538#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)
56539#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
56540
56541#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
56542#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
56543#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
56544
56545#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)
56546#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)
56547#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
56548
56549#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
56550#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
56551#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
56552
56553#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)
56554#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)
56559#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
56560
56561#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)
56562#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)
56563#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
56564
56565#define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)
56566#define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)
56567#define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)
56568
56569#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)
56570#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)
56571#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)
56577#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)
56578#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)
56579#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
56580
56581#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)
56582#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)
56587#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
56588
56589#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)
56590#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
56595#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
56596
56597#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)
56598#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)
56603#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
56604
56605#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)
56606#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)
56611#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
56612
56613#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
56614#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
56615#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
56616
56617#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
56618#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
56619#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
56620
56621#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)
56622#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)
56623#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
56624
56625#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)
56626#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)
56627#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
56628
56629#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
56630#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
56631#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
56632
56633#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
56634#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
56635#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
56636
56637#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)
56638#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)
56639#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
56640
56641#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
56642#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
56643#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
56644
56645#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)
56646#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)
56647#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
56648
56649#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
56650#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
56651#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
56652
56653#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)
56654#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)
56659#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
56660
56661#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)
56662#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)
56663#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
56664
56665#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)
56666#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)
56667#define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)
56668
56669#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)
56670#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)
56671#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)
56677#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)
56678#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)
56679#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
56680
56681#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)
56682#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)
56687#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
56688
56689#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)
56690#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
56695#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
56696
56697#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)
56698#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)
56703#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
56704
56705#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)
56706#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)
56711#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
56712
56713#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
56714#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
56715#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
56716
56717#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
56718#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
56719#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
56720
56721#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)
56722#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)
56723#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
56724
56725#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)
56726#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)
56727#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
56728
56729#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
56730#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
56731#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
56732
56733#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
56734#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
56735#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
56736
56737#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)
56738#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)
56739#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
56740
56741#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
56742#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
56743#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
56744
56745#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)
56746#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)
56747#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
56748
56749#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
56750#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
56751#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
56752
56753#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)
56754#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)
56759#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
56760
56761#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)
56762#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)
56763#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
56764
56765#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)
56766#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)
56767#define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)
56768
56769#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)
56770#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)
56771#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)
56777#define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU)
56778#define LCDIF_CTRL2_RSRVD0_SHIFT (0U)
56779#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
56780
56781#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)
56782#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)
56791#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
56792
56793#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U)
56794#define LCDIF_CTRL2_RSRVD3_SHIFT (15U)
56795#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
56796
56797#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)
56798#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)
56807#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
56808
56809#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U)
56810#define LCDIF_CTRL2_RSRVD4_SHIFT (19U)
56811#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
56812
56813#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)
56814#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)
56815#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
56816
56817#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)
56818#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)
56826#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
56827
56828#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)
56829#define LCDIF_CTRL2_RSRVD5_SHIFT (24U)
56830#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
56836#define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)
56837#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)
56838#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
56839
56840#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)
56841#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)
56850#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
56851
56852#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)
56853#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)
56854#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
56855
56856#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)
56857#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)
56866#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
56867
56868#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)
56869#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)
56870#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
56871
56872#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)
56873#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)
56874#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
56875
56876#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)
56877#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)
56885#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
56886
56887#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)
56888#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)
56889#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
56895#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)
56896#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)
56897#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
56898
56899#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)
56900#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)
56909#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
56910
56911#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)
56912#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)
56913#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
56914
56915#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)
56916#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)
56925#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
56926
56927#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)
56928#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)
56929#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
56930
56931#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)
56932#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)
56933#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
56934
56935#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)
56936#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)
56944#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
56945
56946#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)
56947#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)
56948#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
56954#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)
56955#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)
56956#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
56957
56958#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)
56959#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)
56968#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
56969
56970#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)
56971#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)
56972#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
56973
56974#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)
56975#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)
56984#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
56985
56986#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)
56987#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)
56988#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
56989
56990#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)
56991#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)
56992#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
56993
56994#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)
56995#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)
57003#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
57004
57005#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)
57006#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)
57007#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
57013#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)
57014#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)
57015#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
57016
57017#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)
57018#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)
57019#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
57025#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)
57026#define LCDIF_CUR_BUF_ADDR_SHIFT (0U)
57027#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
57033#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)
57034#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U)
57035#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
57041#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
57042#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)
57043#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
57044
57045#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)
57046#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)
57047#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
57048
57049#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)
57050#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)
57051#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
57052
57053#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
57054#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
57055#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
57056
57057#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)
57058#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)
57059#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
57060
57061#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)
57062#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)
57063#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
57064
57065#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)
57066#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)
57067#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
57068
57069#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)
57070#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)
57071#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
57072
57073#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)
57074#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)
57075#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
57076
57077#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)
57078#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)
57079#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
57080
57081#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)
57082#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)
57083#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
57084
57085#define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U)
57086#define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U)
57091#define LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK)
57092
57093#define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U)
57094#define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U)
57095#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
57101#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
57102#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
57103#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
57104
57105#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)
57106#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)
57107#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
57108
57109#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)
57110#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)
57111#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
57112
57113#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
57114#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
57115#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
57116
57117#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
57118#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
57119#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
57120
57121#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)
57122#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)
57123#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
57124
57125#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)
57126#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)
57127#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
57128
57129#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)
57130#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)
57131#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
57132
57133#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)
57134#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)
57135#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
57136
57137#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)
57138#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)
57139#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
57140
57141#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)
57142#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)
57143#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
57144
57145#define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U)
57146#define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U)
57151#define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK)
57152
57153#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U)
57154#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U)
57155#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
57161#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
57162#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
57163#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
57164
57165#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)
57166#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)
57167#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
57168
57169#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)
57170#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)
57171#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
57172
57173#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
57174#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
57175#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
57176
57177#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
57178#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
57179#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
57180
57181#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)
57182#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)
57183#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
57184
57185#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)
57186#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)
57187#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
57188
57189#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)
57190#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)
57191#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
57192
57193#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)
57194#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)
57195#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
57196
57197#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)
57198#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)
57199#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
57200
57201#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)
57202#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)
57203#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
57204
57205#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U)
57206#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U)
57211#define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK)
57212
57213#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U)
57214#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U)
57215#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
57221#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
57222#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
57223#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
57224
57225#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)
57226#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)
57227#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
57228
57229#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)
57230#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)
57231#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
57232
57233#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
57234#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
57235#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
57236
57237#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
57238#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
57239#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
57240
57241#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)
57242#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)
57243#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
57244
57245#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)
57246#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)
57247#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
57248
57249#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)
57250#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)
57251#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
57252
57253#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)
57254#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)
57255#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
57256
57257#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)
57258#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)
57259#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
57260
57261#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)
57262#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)
57263#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
57264
57265#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U)
57266#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U)
57271#define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK)
57272
57273#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U)
57274#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U)
57275#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
57281#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)
57282#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)
57283#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
57289#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)
57290#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)
57291#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
57292
57293#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)
57294#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)
57295#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
57301#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)
57302#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)
57303#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
57304
57305#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)
57306#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)
57307#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
57308
57309#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)
57310#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)
57311#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
57312
57313#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)
57314#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)
57315#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
57316
57317#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)
57318#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)
57319#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
57325#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
57326#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
57327#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
57328
57329#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)
57330#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)
57331#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
57332
57333#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)
57334#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)
57335#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
57336
57337#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)
57338#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)
57339#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
57345#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)
57346#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)
57347#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
57353#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)
57354#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)
57355#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
57361#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)
57362#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)
57363#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
57364
57365#define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)
57366#define LCDIF_STAT_RSRVD0_SHIFT (9U)
57367#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
57368
57369#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)
57370#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)
57371#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
57372
57373#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)
57374#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)
57375#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
57376
57377#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)
57378#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)
57379#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
57380
57381#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)
57382#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U)
57383#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
57384
57385#define LCDIF_STAT_DMA_REQ_MASK (0x40000000U)
57386#define LCDIF_STAT_DMA_REQ_SHIFT (30U)
57387#define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)
57388
57389#define LCDIF_STAT_PRESENT_MASK (0x80000000U)
57390#define LCDIF_STAT_PRESENT_SHIFT (31U)
57391#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
57397#define LCDIF_THRES_RSRVD_MASK (0x1FFU)
57398#define LCDIF_THRES_RSRVD_SHIFT (0U)
57399#define LCDIF_THRES_RSRVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD_SHIFT)) & LCDIF_THRES_RSRVD_MASK)
57400
57401#define LCDIF_THRES_RSRVD1_MASK (0xFE00U)
57402#define LCDIF_THRES_RSRVD1_SHIFT (9U)
57403#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)
57404
57405#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U)
57406#define LCDIF_THRES_FASTCLOCK_SHIFT (16U)
57407#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)
57408
57409#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U)
57410#define LCDIF_THRES_RSRVD2_SHIFT (25U)
57411#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)
57417#define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)
57418#define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)
57419#define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
57420
57421#define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)
57422#define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)
57423#define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
57429#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)
57430#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)
57431#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
57432
57433#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)
57434#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)
57435#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
57441#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)
57442#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)
57443#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
57444
57445#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)
57446#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)
57447#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
57453#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)
57454#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)
57455#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
57456
57457#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)
57458#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)
57459#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
57465#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)
57466#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
57467#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
57468
57469#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
57470#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
57471#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
57477#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
57478#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
57479#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
57480
57481#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
57482#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
57483#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
57489#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
57490#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
57491#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
57492
57493#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
57494#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
57495#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
57501#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
57502#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
57503#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
57504
57505#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
57506#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
57507#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
57513#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)
57514#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)
57515#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
57516
57517#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)
57518#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)
57519#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
57525#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
57526#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
57527#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
57528
57529#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
57530#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
57531#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
57537#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
57538#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
57539#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
57540
57541#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
57542#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
57543#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
57549#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
57550#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
57551#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
57552
57553#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
57554#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
57555#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
57561#define LCDIF_PIGEON_0_EN_MASK (0x1U)
57562#define LCDIF_PIGEON_0_EN_SHIFT (0U)
57563#define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
57564
57565#define LCDIF_PIGEON_0_POL_MASK (0x2U)
57566#define LCDIF_PIGEON_0_POL_SHIFT (1U)
57571#define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
57572
57573#define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU)
57574#define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U)
57581#define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
57582
57583#define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U)
57584#define LCDIF_PIGEON_0_OFFSET_SHIFT (4U)
57585#define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
57586
57587#define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)
57588#define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)
57599#define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
57600
57601#define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)
57602#define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)
57603#define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
57604
57605#define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)
57606#define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)
57617#define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
57620/* The count of LCDIF_PIGEON_0 */
57621#define LCDIF_PIGEON_0_COUNT (12U)
57622
57626#define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)
57627#define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U)
57631#define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
57632
57633#define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)
57634#define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)
57638#define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
57641/* The count of LCDIF_PIGEON_1 */
57642#define LCDIF_PIGEON_1_COUNT (12U)
57643
57647#define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)
57648#define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)
57655#define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
57656
57657#define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)
57658#define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)
57662#define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
57663
57664#define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)
57665#define LCDIF_PIGEON_2_RSVD_SHIFT (9U)
57666#define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)
57669/* The count of LCDIF_PIGEON_2 */
57670#define LCDIF_PIGEON_2_COUNT (12U)
57671
57675#define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)
57676#define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)
57677#define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)
57683#define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)
57684#define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U)
57685#define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)
57691#define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)
57692#define LCDIF_LUT0_DATA_DATA_SHIFT (0U)
57693#define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)
57699#define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)
57700#define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U)
57701#define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)
57707#define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)
57708#define LCDIF_LUT1_DATA_DATA_SHIFT (0U)
57709#define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK) /* end of group LCDIF_Register_Masks */
57716
57717
57718/* LCDIF - Peripheral instance base addresses */
57720#define LCDIF_BASE (0x40804000u)
57722#define LCDIF ((LCDIF_Type *)LCDIF_BASE)
57724#define LCDIF_BASE_ADDRS { LCDIF_BASE }
57726#define LCDIF_BASE_PTRS { LCDIF }
57728#define LCDIF_IRQ0_IRQS { eLCDIF_IRQn }
57729 /* end of group LCDIF_Peripheral_Access_Layer */
57733
57734
57735/* ----------------------------------------------------------------------------
57736 -- LCDIFV2 Peripheral Access Layer
57737 ---------------------------------------------------------------------------- */
57738
57745typedef struct {
57746 __IO uint32_t CTRL;
57747 __IO uint32_t CTRL_SET;
57748 __IO uint32_t CTRL_CLR;
57749 __IO uint32_t CTRL_TOG;
57750 __IO uint32_t DISP_PARA;
57751 __IO uint32_t DISP_SIZE;
57752 __IO uint32_t HSYN_PARA;
57753 __IO uint32_t VSYN_PARA;
57754 struct { /* offset: 0x20, array step: 0x10 */
57755 __IO uint32_t INT_STATUS;
57756 __IO uint32_t INT_ENABLE;
57757 uint8_t RESERVED_0[8];
57758 } INT[2];
57759 __IO uint32_t PDI_PARA;
57760 uint8_t RESERVED_0[444];
57761 struct { /* offset: 0x200, array step: 0x40 */
57762 __IO uint32_t CTRLDESCL1;
57763 __IO uint32_t CTRLDESCL2;
57764 __IO uint32_t CTRLDESCL3;
57765 __IO uint32_t CTRLDESCL4;
57766 __IO uint32_t CTRLDESCL5;
57767 __IO uint32_t CTRLDESCL6;
57768 __IO uint32_t CSC_COEF0;
57769 __IO uint32_t CSC_COEF1;
57770 __IO uint32_t CSC_COEF2;
57771 uint8_t RESERVED_0[28];
57772 } LAYER[8];
57773 __IO uint32_t CLUT_LOAD;
57774} LCDIFV2_Type;
57775
57776/* ----------------------------------------------------------------------------
57777 -- LCDIFV2 Register Masks
57778 ---------------------------------------------------------------------------- */
57779
57788#define LCDIFV2_CTRL_INV_HS_MASK (0x1U)
57789#define LCDIFV2_CTRL_INV_HS_SHIFT (0U)
57794#define LCDIFV2_CTRL_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_HS_SHIFT)) & LCDIFV2_CTRL_INV_HS_MASK)
57795
57796#define LCDIFV2_CTRL_INV_VS_MASK (0x2U)
57797#define LCDIFV2_CTRL_INV_VS_SHIFT (1U)
57802#define LCDIFV2_CTRL_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_VS_SHIFT)) & LCDIFV2_CTRL_INV_VS_MASK)
57803
57804#define LCDIFV2_CTRL_INV_DE_MASK (0x4U)
57805#define LCDIFV2_CTRL_INV_DE_SHIFT (2U)
57810#define LCDIFV2_CTRL_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_DE_SHIFT)) & LCDIFV2_CTRL_INV_DE_MASK)
57811
57812#define LCDIFV2_CTRL_INV_PXCK_MASK (0x8U)
57813#define LCDIFV2_CTRL_INV_PXCK_SHIFT (3U)
57818#define LCDIFV2_CTRL_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_INV_PXCK_MASK)
57819
57820#define LCDIFV2_CTRL_NEG_MASK (0x10U)
57821#define LCDIFV2_CTRL_NEG_SHIFT (4U)
57826#define LCDIFV2_CTRL_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_NEG_SHIFT)) & LCDIFV2_CTRL_NEG_MASK)
57827
57828#define LCDIFV2_CTRL_SW_RESET_MASK (0x80000000U)
57829#define LCDIFV2_CTRL_SW_RESET_SHIFT (31U)
57834#define LCDIFV2_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SW_RESET_MASK)
57840#define LCDIFV2_CTRL_SET_INV_HS_MASK (0x1U)
57841#define LCDIFV2_CTRL_SET_INV_HS_SHIFT (0U)
57844#define LCDIFV2_CTRL_SET_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_HS_SHIFT)) & LCDIFV2_CTRL_SET_INV_HS_MASK)
57845
57846#define LCDIFV2_CTRL_SET_INV_VS_MASK (0x2U)
57847#define LCDIFV2_CTRL_SET_INV_VS_SHIFT (1U)
57850#define LCDIFV2_CTRL_SET_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_VS_SHIFT)) & LCDIFV2_CTRL_SET_INV_VS_MASK)
57851
57852#define LCDIFV2_CTRL_SET_INV_DE_MASK (0x4U)
57853#define LCDIFV2_CTRL_SET_INV_DE_SHIFT (2U)
57856#define LCDIFV2_CTRL_SET_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_DE_SHIFT)) & LCDIFV2_CTRL_SET_INV_DE_MASK)
57857
57858#define LCDIFV2_CTRL_SET_INV_PXCK_MASK (0x8U)
57859#define LCDIFV2_CTRL_SET_INV_PXCK_SHIFT (3U)
57862#define LCDIFV2_CTRL_SET_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_SET_INV_PXCK_MASK)
57863
57864#define LCDIFV2_CTRL_SET_NEG_MASK (0x10U)
57865#define LCDIFV2_CTRL_SET_NEG_SHIFT (4U)
57868#define LCDIFV2_CTRL_SET_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_NEG_SHIFT)) & LCDIFV2_CTRL_SET_NEG_MASK)
57869
57870#define LCDIFV2_CTRL_SET_SW_RESET_MASK (0x80000000U)
57871#define LCDIFV2_CTRL_SET_SW_RESET_SHIFT (31U)
57874#define LCDIFV2_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SET_SW_RESET_MASK)
57880#define LCDIFV2_CTRL_CLR_INV_HS_MASK (0x1U)
57881#define LCDIFV2_CTRL_CLR_INV_HS_SHIFT (0U)
57884#define LCDIFV2_CTRL_CLR_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_HS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_HS_MASK)
57885
57886#define LCDIFV2_CTRL_CLR_INV_VS_MASK (0x2U)
57887#define LCDIFV2_CTRL_CLR_INV_VS_SHIFT (1U)
57890#define LCDIFV2_CTRL_CLR_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_VS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_VS_MASK)
57891
57892#define LCDIFV2_CTRL_CLR_INV_DE_MASK (0x4U)
57893#define LCDIFV2_CTRL_CLR_INV_DE_SHIFT (2U)
57896#define LCDIFV2_CTRL_CLR_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_DE_SHIFT)) & LCDIFV2_CTRL_CLR_INV_DE_MASK)
57897
57898#define LCDIFV2_CTRL_CLR_INV_PXCK_MASK (0x8U)
57899#define LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT (3U)
57902#define LCDIFV2_CTRL_CLR_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_CLR_INV_PXCK_MASK)
57903
57904#define LCDIFV2_CTRL_CLR_NEG_MASK (0x10U)
57905#define LCDIFV2_CTRL_CLR_NEG_SHIFT (4U)
57908#define LCDIFV2_CTRL_CLR_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_NEG_SHIFT)) & LCDIFV2_CTRL_CLR_NEG_MASK)
57909
57910#define LCDIFV2_CTRL_CLR_SW_RESET_MASK (0x80000000U)
57911#define LCDIFV2_CTRL_CLR_SW_RESET_SHIFT (31U)
57914#define LCDIFV2_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_SW_RESET_SHIFT)) & LCDIFV2_CTRL_CLR_SW_RESET_MASK)
57920#define LCDIFV2_CTRL_TOG_INV_HS_MASK (0x1U)
57921#define LCDIFV2_CTRL_TOG_INV_HS_SHIFT (0U)
57924#define LCDIFV2_CTRL_TOG_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_HS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_HS_MASK)
57925
57926#define LCDIFV2_CTRL_TOG_INV_VS_MASK (0x2U)
57927#define LCDIFV2_CTRL_TOG_INV_VS_SHIFT (1U)
57930#define LCDIFV2_CTRL_TOG_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_VS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_VS_MASK)
57931
57932#define LCDIFV2_CTRL_TOG_INV_DE_MASK (0x4U)
57933#define LCDIFV2_CTRL_TOG_INV_DE_SHIFT (2U)
57936#define LCDIFV2_CTRL_TOG_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_DE_SHIFT)) & LCDIFV2_CTRL_TOG_INV_DE_MASK)
57937
57938#define LCDIFV2_CTRL_TOG_INV_PXCK_MASK (0x8U)
57939#define LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT (3U)
57942#define LCDIFV2_CTRL_TOG_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_TOG_INV_PXCK_MASK)
57943
57944#define LCDIFV2_CTRL_TOG_NEG_MASK (0x10U)
57945#define LCDIFV2_CTRL_TOG_NEG_SHIFT (4U)
57948#define LCDIFV2_CTRL_TOG_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_NEG_SHIFT)) & LCDIFV2_CTRL_TOG_NEG_MASK)
57949
57950#define LCDIFV2_CTRL_TOG_SW_RESET_MASK (0x80000000U)
57951#define LCDIFV2_CTRL_TOG_SW_RESET_SHIFT (31U)
57954#define LCDIFV2_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_SW_RESET_SHIFT)) & LCDIFV2_CTRL_TOG_SW_RESET_MASK)
57960#define LCDIFV2_DISP_PARA_BGND_B_MASK (0xFFU)
57961#define LCDIFV2_DISP_PARA_BGND_B_SHIFT (0U)
57964#define LCDIFV2_DISP_PARA_BGND_B(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_B_SHIFT)) & LCDIFV2_DISP_PARA_BGND_B_MASK)
57965
57966#define LCDIFV2_DISP_PARA_BGND_G_MASK (0xFF00U)
57967#define LCDIFV2_DISP_PARA_BGND_G_SHIFT (8U)
57970#define LCDIFV2_DISP_PARA_BGND_G(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_G_SHIFT)) & LCDIFV2_DISP_PARA_BGND_G_MASK)
57971
57972#define LCDIFV2_DISP_PARA_BGND_R_MASK (0xFF0000U)
57973#define LCDIFV2_DISP_PARA_BGND_R_SHIFT (16U)
57976#define LCDIFV2_DISP_PARA_BGND_R(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_R_SHIFT)) & LCDIFV2_DISP_PARA_BGND_R_MASK)
57977
57978#define LCDIFV2_DISP_PARA_DISP_MODE_MASK (0x3000000U)
57979#define LCDIFV2_DISP_PARA_DISP_MODE_SHIFT (24U)
57986#define LCDIFV2_DISP_PARA_DISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_MODE_SHIFT)) & LCDIFV2_DISP_PARA_DISP_MODE_MASK)
57987
57988#define LCDIFV2_DISP_PARA_LINE_PATTERN_MASK (0x1C000000U)
57989#define LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT (26U)
57998#define LCDIFV2_DISP_PARA_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIFV2_DISP_PARA_LINE_PATTERN_MASK)
57999
58000#define LCDIFV2_DISP_PARA_DISP_ON_MASK (0x80000000U)
58001#define LCDIFV2_DISP_PARA_DISP_ON_SHIFT (31U)
58006#define LCDIFV2_DISP_PARA_DISP_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_ON_SHIFT)) & LCDIFV2_DISP_PARA_DISP_ON_MASK)
58012#define LCDIFV2_DISP_SIZE_DELTA_X_MASK (0xFFFU)
58013#define LCDIFV2_DISP_SIZE_DELTA_X_SHIFT (0U)
58016#define LCDIFV2_DISP_SIZE_DELTA_X(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_X_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_X_MASK)
58017
58018#define LCDIFV2_DISP_SIZE_DELTA_Y_MASK (0xFFF0000U)
58019#define LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT (16U)
58022#define LCDIFV2_DISP_SIZE_DELTA_Y(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_Y_MASK)
58028#define LCDIFV2_HSYN_PARA_FP_H_MASK (0x1FFU)
58029#define LCDIFV2_HSYN_PARA_FP_H_SHIFT (0U)
58032#define LCDIFV2_HSYN_PARA_FP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_FP_H_SHIFT)) & LCDIFV2_HSYN_PARA_FP_H_MASK)
58033
58034#define LCDIFV2_HSYN_PARA_PW_H_MASK (0xFF800U)
58035#define LCDIFV2_HSYN_PARA_PW_H_SHIFT (11U)
58038#define LCDIFV2_HSYN_PARA_PW_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_PW_H_SHIFT)) & LCDIFV2_HSYN_PARA_PW_H_MASK)
58039
58040#define LCDIFV2_HSYN_PARA_BP_H_MASK (0x7FC00000U)
58041#define LCDIFV2_HSYN_PARA_BP_H_SHIFT (22U)
58044#define LCDIFV2_HSYN_PARA_BP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_BP_H_SHIFT)) & LCDIFV2_HSYN_PARA_BP_H_MASK)
58050#define LCDIFV2_VSYN_PARA_FP_V_MASK (0x1FFU)
58051#define LCDIFV2_VSYN_PARA_FP_V_SHIFT (0U)
58054#define LCDIFV2_VSYN_PARA_FP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_FP_V_SHIFT)) & LCDIFV2_VSYN_PARA_FP_V_MASK)
58055
58056#define LCDIFV2_VSYN_PARA_PW_V_MASK (0xFF800U)
58057#define LCDIFV2_VSYN_PARA_PW_V_SHIFT (11U)
58060#define LCDIFV2_VSYN_PARA_PW_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_PW_V_SHIFT)) & LCDIFV2_VSYN_PARA_PW_V_MASK)
58061
58062#define LCDIFV2_VSYN_PARA_BP_V_MASK (0x7FC00000U)
58063#define LCDIFV2_VSYN_PARA_BP_V_SHIFT (22U)
58066#define LCDIFV2_VSYN_PARA_BP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_BP_V_SHIFT)) & LCDIFV2_VSYN_PARA_BP_V_MASK)
58072#define LCDIFV2_INT_STATUS_VSYNC_MASK (0x1U)
58073#define LCDIFV2_INT_STATUS_VSYNC_SHIFT (0U)
58078#define LCDIFV2_INT_STATUS_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VSYNC_SHIFT)) & LCDIFV2_INT_STATUS_VSYNC_MASK)
58079
58080#define LCDIFV2_INT_STATUS_UNDERRUN_MASK (0x2U)
58081#define LCDIFV2_INT_STATUS_UNDERRUN_SHIFT (1U)
58086#define LCDIFV2_INT_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_UNDERRUN_SHIFT)) & LCDIFV2_INT_STATUS_UNDERRUN_MASK)
58087
58088#define LCDIFV2_INT_STATUS_VS_BLANK_MASK (0x4U)
58089#define LCDIFV2_INT_STATUS_VS_BLANK_SHIFT (2U)
58094#define LCDIFV2_INT_STATUS_VS_BLANK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VS_BLANK_SHIFT)) & LCDIFV2_INT_STATUS_VS_BLANK_MASK)
58095
58096#define LCDIFV2_INT_STATUS_DMA_ERR_MASK (0xFF00U)
58097#define LCDIFV2_INT_STATUS_DMA_ERR_SHIFT (8U)
58100#define LCDIFV2_INT_STATUS_DMA_ERR(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_ERR_SHIFT)) & LCDIFV2_INT_STATUS_DMA_ERR_MASK)
58101
58102#define LCDIFV2_INT_STATUS_DMA_DONE_MASK (0xFF0000U)
58103#define LCDIFV2_INT_STATUS_DMA_DONE_SHIFT (16U)
58106#define LCDIFV2_INT_STATUS_DMA_DONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_DONE_SHIFT)) & LCDIFV2_INT_STATUS_DMA_DONE_MASK)
58107
58108#define LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK (0xFF000000U)
58109#define LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT (24U)
58112#define LCDIFV2_INT_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT)) & LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK)
58115/* The count of LCDIFV2_INT_STATUS */
58116#define LCDIFV2_INT_STATUS_COUNT (2U)
58117
58121#define LCDIFV2_INT_ENABLE_VSYNC_EN_MASK (0x1U)
58122#define LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT (0U)
58127#define LCDIFV2_INT_ENABLE_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VSYNC_EN_MASK)
58128
58129#define LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK (0x2U)
58130#define LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT (1U)
58135#define LCDIFV2_INT_ENABLE_UNDERRUN_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT)) & LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK)
58136
58137#define LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK (0x4U)
58138#define LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT (2U)
58143#define LCDIFV2_INT_ENABLE_VS_BLANK_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK)
58144
58145#define LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK (0xFF00U)
58146#define LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT (8U)
58149#define LCDIFV2_INT_ENABLE_DMA_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK)
58150
58151#define LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK (0xFF0000U)
58152#define LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT (16U)
58155#define LCDIFV2_INT_ENABLE_DMA_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK)
58156
58157#define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK (0xFF000000U)
58158#define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT (24U)
58161#define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT)) & LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK)
58164/* The count of LCDIFV2_INT_ENABLE */
58165#define LCDIFV2_INT_ENABLE_COUNT (2U)
58166
58170#define LCDIFV2_PDI_PARA_INV_PDI_HS_MASK (0x1U)
58171#define LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT (0U)
58176#define LCDIFV2_PDI_PARA_INV_PDI_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_HS_MASK)
58177
58178#define LCDIFV2_PDI_PARA_INV_PDI_VS_MASK (0x2U)
58179#define LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT (1U)
58184#define LCDIFV2_PDI_PARA_INV_PDI_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_VS_MASK)
58185
58186#define LCDIFV2_PDI_PARA_INV_PDI_DE_MASK (0x4U)
58187#define LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT (2U)
58192#define LCDIFV2_PDI_PARA_INV_PDI_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_DE_MASK)
58193
58194#define LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK (0x8U)
58195#define LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT (3U)
58200#define LCDIFV2_PDI_PARA_INV_PDI_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK)
58201
58202#define LCDIFV2_PDI_PARA_MODE_MASK (0xF0U)
58203#define LCDIFV2_PDI_PARA_MODE_SHIFT (4U)
58213#define LCDIFV2_PDI_PARA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_MODE_SHIFT)) & LCDIFV2_PDI_PARA_MODE_MASK)
58214
58215#define LCDIFV2_PDI_PARA_PDI_SEL_MASK (0x40000000U)
58216#define LCDIFV2_PDI_PARA_PDI_SEL_SHIFT (30U)
58221#define LCDIFV2_PDI_PARA_PDI_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_SEL_SHIFT)) & LCDIFV2_PDI_PARA_PDI_SEL_MASK)
58222
58223#define LCDIFV2_PDI_PARA_PDI_EN_MASK (0x80000000U)
58224#define LCDIFV2_PDI_PARA_PDI_EN_SHIFT (31U)
58229#define LCDIFV2_PDI_PARA_PDI_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_EN_SHIFT)) & LCDIFV2_PDI_PARA_PDI_EN_MASK)
58235#define LCDIFV2_CTRLDESCL1_WIDTH_MASK (0xFFFU)
58236#define LCDIFV2_CTRLDESCL1_WIDTH_SHIFT (0U)
58239#define LCDIFV2_CTRLDESCL1_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_WIDTH_SHIFT)) & LCDIFV2_CTRLDESCL1_WIDTH_MASK)
58240
58241#define LCDIFV2_CTRLDESCL1_HEIGHT_MASK (0xFFF0000U)
58242#define LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT (16U)
58245#define LCDIFV2_CTRLDESCL1_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT)) & LCDIFV2_CTRLDESCL1_HEIGHT_MASK)
58248/* The count of LCDIFV2_CTRLDESCL1 */
58249#define LCDIFV2_CTRLDESCL1_COUNT (8U)
58250
58254#define LCDIFV2_CTRLDESCL2_POSX_MASK (0xFFFU)
58255#define LCDIFV2_CTRLDESCL2_POSX_SHIFT (0U)
58259#define LCDIFV2_CTRLDESCL2_POSX(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSX_SHIFT)) & LCDIFV2_CTRLDESCL2_POSX_MASK)
58260
58261#define LCDIFV2_CTRLDESCL2_POSY_MASK (0xFFF0000U)
58262#define LCDIFV2_CTRLDESCL2_POSY_SHIFT (16U)
58266#define LCDIFV2_CTRLDESCL2_POSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSY_SHIFT)) & LCDIFV2_CTRLDESCL2_POSY_MASK)
58269/* The count of LCDIFV2_CTRLDESCL2 */
58270#define LCDIFV2_CTRLDESCL2_COUNT (8U)
58271
58275#define LCDIFV2_CTRLDESCL3_PITCH_MASK (0xFFFFU)
58276#define LCDIFV2_CTRLDESCL3_PITCH_SHIFT (0U)
58280#define LCDIFV2_CTRLDESCL3_PITCH(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL3_PITCH_SHIFT)) & LCDIFV2_CTRLDESCL3_PITCH_MASK)
58283/* The count of LCDIFV2_CTRLDESCL3 */
58284#define LCDIFV2_CTRLDESCL3_COUNT (8U)
58285
58289#define LCDIFV2_CTRLDESCL4_ADDR_MASK (0xFFFFFFFFU)
58290#define LCDIFV2_CTRLDESCL4_ADDR_SHIFT (0U)
58293#define LCDIFV2_CTRLDESCL4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL4_ADDR_SHIFT)) & LCDIFV2_CTRLDESCL4_ADDR_MASK)
58296/* The count of LCDIFV2_CTRLDESCL4 */
58297#define LCDIFV2_CTRLDESCL4_COUNT (8U)
58298
58302#define LCDIFV2_CTRLDESCL5_AB_MODE_MASK (0x3U)
58303#define LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT (0U)
58310#define LCDIFV2_CTRLDESCL5_AB_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_AB_MODE_MASK)
58311
58312#define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK (0x30U)
58313#define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT (4U)
58320#define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK)
58321
58322#define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK (0xC0U)
58323#define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT (6U)
58330#define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK)
58331
58332#define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK (0x100U)
58333#define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT (8U)
58338#define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK)
58339
58340#define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK (0x200U)
58341#define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT (9U)
58346#define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK)
58347
58348#define LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK (0xC000U)
58349#define LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT (14U)
58356#define LCDIFV2_CTRLDESCL5_YUV_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT)) & LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK)
58357
58358#define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK (0xFF0000U)
58359#define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT (16U)
58362#define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT)) & LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK)
58363
58364#define LCDIFV2_CTRLDESCL5_BPP_MASK (0xF000000U)
58365#define LCDIFV2_CTRLDESCL5_BPP_SHIFT (24U)
58379#define LCDIFV2_CTRLDESCL5_BPP(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_BPP_SHIFT)) & LCDIFV2_CTRLDESCL5_BPP_MASK)
58380
58381#define LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK (0x10000000U)
58382#define LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT (28U)
58387#define LCDIFV2_CTRLDESCL5_SAFETY_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK)
58388
58389#define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK (0x40000000U)
58390#define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT (30U)
58393#define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK)
58394
58395#define LCDIFV2_CTRLDESCL5_EN_MASK (0x80000000U)
58396#define LCDIFV2_CTRLDESCL5_EN_SHIFT (31U)
58401#define LCDIFV2_CTRLDESCL5_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_EN_MASK)
58404/* The count of LCDIFV2_CTRLDESCL5 */
58405#define LCDIFV2_CTRLDESCL5_COUNT (8U)
58406
58410#define LCDIFV2_CTRLDESCL6_BCLR_B_MASK (0xFFU)
58411#define LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT (0U)
58414#define LCDIFV2_CTRLDESCL6_BCLR_B(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_B_MASK)
58415
58416#define LCDIFV2_CTRLDESCL6_BCLR_G_MASK (0xFF00U)
58417#define LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT (8U)
58420#define LCDIFV2_CTRLDESCL6_BCLR_G(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_G_MASK)
58421
58422#define LCDIFV2_CTRLDESCL6_BCLR_R_MASK (0xFF0000U)
58423#define LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT (16U)
58426#define LCDIFV2_CTRLDESCL6_BCLR_R(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_R_MASK)
58429/* The count of LCDIFV2_CTRLDESCL6 */
58430#define LCDIFV2_CTRLDESCL6_COUNT (8U)
58431
58435#define LCDIFV2_CSC_COEF0_Y_OFFSET_MASK (0x1FFU)
58436#define LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT (0U)
58440#define LCDIFV2_CSC_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_Y_OFFSET_MASK)
58441
58442#define LCDIFV2_CSC_COEF0_UV_OFFSET_MASK (0x3FE00U)
58443#define LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT (9U)
58448#define LCDIFV2_CSC_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_UV_OFFSET_MASK)
58449
58450#define LCDIFV2_CSC_COEF0_C0_MASK (0x1FFC0000U)
58451#define LCDIFV2_CSC_COEF0_C0_SHIFT (18U)
58454#define LCDIFV2_CSC_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_C0_SHIFT)) & LCDIFV2_CSC_COEF0_C0_MASK)
58455
58456#define LCDIFV2_CSC_COEF0_ENABLE_MASK (0x40000000U)
58457#define LCDIFV2_CSC_COEF0_ENABLE_SHIFT (30U)
58462#define LCDIFV2_CSC_COEF0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_ENABLE_SHIFT)) & LCDIFV2_CSC_COEF0_ENABLE_MASK)
58463
58464#define LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK (0x80000000U)
58465#define LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT (31U)
58470#define LCDIFV2_CSC_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT)) & LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK)
58473/* The count of LCDIFV2_CSC_COEF0 */
58474#define LCDIFV2_CSC_COEF0_COUNT (8U)
58475
58479#define LCDIFV2_CSC_COEF1_C4_MASK (0x7FFU)
58480#define LCDIFV2_CSC_COEF1_C4_SHIFT (0U)
58483#define LCDIFV2_CSC_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C4_SHIFT)) & LCDIFV2_CSC_COEF1_C4_MASK)
58484
58485#define LCDIFV2_CSC_COEF1_C1_MASK (0x7FF0000U)
58486#define LCDIFV2_CSC_COEF1_C1_SHIFT (16U)
58489#define LCDIFV2_CSC_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C1_SHIFT)) & LCDIFV2_CSC_COEF1_C1_MASK)
58492/* The count of LCDIFV2_CSC_COEF1 */
58493#define LCDIFV2_CSC_COEF1_COUNT (8U)
58494
58498#define LCDIFV2_CSC_COEF2_C3_MASK (0x7FFU)
58499#define LCDIFV2_CSC_COEF2_C3_SHIFT (0U)
58502#define LCDIFV2_CSC_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C3_SHIFT)) & LCDIFV2_CSC_COEF2_C3_MASK)
58503
58504#define LCDIFV2_CSC_COEF2_C2_MASK (0x7FF0000U)
58505#define LCDIFV2_CSC_COEF2_C2_SHIFT (16U)
58508#define LCDIFV2_CSC_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C2_SHIFT)) & LCDIFV2_CSC_COEF2_C2_MASK)
58511/* The count of LCDIFV2_CSC_COEF2 */
58512#define LCDIFV2_CSC_COEF2_COUNT (8U)
58513
58517#define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK (0x1U)
58518#define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT (0U)
58521#define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT)) & LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK)
58522
58523#define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK (0x70U)
58524#define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT (4U)
58527#define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT)) & LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK) /* end of group LCDIFV2_Register_Masks */
58534
58535
58536/* LCDIFV2 - Peripheral instance base addresses */
58538#define LCDIFV2_BASE (0x40808000u)
58540#define LCDIFV2 ((LCDIFV2_Type *)LCDIFV2_BASE)
58542#define LCDIFV2_BASE_ADDRS { LCDIFV2_BASE }
58544#define LCDIFV2_BASE_PTRS { LCDIFV2 }
58545 /* end of group LCDIFV2_Peripheral_Access_Layer */
58549
58550
58551/* ----------------------------------------------------------------------------
58552 -- LPI2C Peripheral Access Layer
58553 ---------------------------------------------------------------------------- */
58554
58561typedef struct {
58562 __I uint32_t VERID;
58563 __I uint32_t PARAM;
58564 uint8_t RESERVED_0[8];
58565 __IO uint32_t MCR;
58566 __IO uint32_t MSR;
58567 __IO uint32_t MIER;
58568 __IO uint32_t MDER;
58569 __IO uint32_t MCFGR0;
58570 __IO uint32_t MCFGR1;
58571 __IO uint32_t MCFGR2;
58572 __IO uint32_t MCFGR3;
58573 uint8_t RESERVED_1[16];
58574 __IO uint32_t MDMR;
58575 uint8_t RESERVED_2[4];
58576 __IO uint32_t MCCR0;
58577 uint8_t RESERVED_3[4];
58578 __IO uint32_t MCCR1;
58579 uint8_t RESERVED_4[4];
58580 __IO uint32_t MFCR;
58581 __I uint32_t MFSR;
58582 __O uint32_t MTDR;
58583 uint8_t RESERVED_5[12];
58584 __I uint32_t MRDR;
58585 uint8_t RESERVED_6[156];
58586 __IO uint32_t SCR;
58587 __IO uint32_t SSR;
58588 __IO uint32_t SIER;
58589 __IO uint32_t SDER;
58590 uint8_t RESERVED_7[4];
58591 __IO uint32_t SCFGR1;
58592 __IO uint32_t SCFGR2;
58593 uint8_t RESERVED_8[20];
58594 __IO uint32_t SAMR;
58595 uint8_t RESERVED_9[12];
58596 __I uint32_t SASR;
58597 __IO uint32_t STAR;
58598 uint8_t RESERVED_10[8];
58599 __O uint32_t STDR;
58600 uint8_t RESERVED_11[12];
58601 __I uint32_t SRDR;
58602} LPI2C_Type;
58603
58604/* ----------------------------------------------------------------------------
58605 -- LPI2C Register Masks
58606 ---------------------------------------------------------------------------- */
58607
58616#define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
58617#define LPI2C_VERID_FEATURE_SHIFT (0U)
58622#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
58623
58624#define LPI2C_VERID_MINOR_MASK (0xFF0000U)
58625#define LPI2C_VERID_MINOR_SHIFT (16U)
58628#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
58629
58630#define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
58631#define LPI2C_VERID_MAJOR_SHIFT (24U)
58634#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
58640#define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
58641#define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
58644#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
58645
58646#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
58647#define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
58650#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
58656#define LPI2C_MCR_MEN_MASK (0x1U)
58657#define LPI2C_MCR_MEN_SHIFT (0U)
58662#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
58663
58664#define LPI2C_MCR_RST_MASK (0x2U)
58665#define LPI2C_MCR_RST_SHIFT (1U)
58670#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
58671
58672#define LPI2C_MCR_DOZEN_MASK (0x4U)
58673#define LPI2C_MCR_DOZEN_SHIFT (2U)
58678#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
58679
58680#define LPI2C_MCR_DBGEN_MASK (0x8U)
58681#define LPI2C_MCR_DBGEN_SHIFT (3U)
58686#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
58687
58688#define LPI2C_MCR_RTF_MASK (0x100U)
58689#define LPI2C_MCR_RTF_SHIFT (8U)
58694#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
58695
58696#define LPI2C_MCR_RRF_MASK (0x200U)
58697#define LPI2C_MCR_RRF_SHIFT (9U)
58702#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
58708#define LPI2C_MSR_TDF_MASK (0x1U)
58709#define LPI2C_MSR_TDF_SHIFT (0U)
58714#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
58715
58716#define LPI2C_MSR_RDF_MASK (0x2U)
58717#define LPI2C_MSR_RDF_SHIFT (1U)
58722#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
58723
58724#define LPI2C_MSR_EPF_MASK (0x100U)
58725#define LPI2C_MSR_EPF_SHIFT (8U)
58730#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
58731
58732#define LPI2C_MSR_SDF_MASK (0x200U)
58733#define LPI2C_MSR_SDF_SHIFT (9U)
58738#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
58739
58740#define LPI2C_MSR_NDF_MASK (0x400U)
58741#define LPI2C_MSR_NDF_SHIFT (10U)
58746#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
58747
58748#define LPI2C_MSR_ALF_MASK (0x800U)
58749#define LPI2C_MSR_ALF_SHIFT (11U)
58754#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
58755
58756#define LPI2C_MSR_FEF_MASK (0x1000U)
58757#define LPI2C_MSR_FEF_SHIFT (12U)
58762#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
58763
58764#define LPI2C_MSR_PLTF_MASK (0x2000U)
58765#define LPI2C_MSR_PLTF_SHIFT (13U)
58770#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
58771
58772#define LPI2C_MSR_DMF_MASK (0x4000U)
58773#define LPI2C_MSR_DMF_SHIFT (14U)
58778#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
58779
58780#define LPI2C_MSR_MBF_MASK (0x1000000U)
58781#define LPI2C_MSR_MBF_SHIFT (24U)
58786#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
58787
58788#define LPI2C_MSR_BBF_MASK (0x2000000U)
58789#define LPI2C_MSR_BBF_SHIFT (25U)
58794#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
58800#define LPI2C_MIER_TDIE_MASK (0x1U)
58801#define LPI2C_MIER_TDIE_SHIFT (0U)
58806#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
58807
58808#define LPI2C_MIER_RDIE_MASK (0x2U)
58809#define LPI2C_MIER_RDIE_SHIFT (1U)
58814#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
58815
58816#define LPI2C_MIER_EPIE_MASK (0x100U)
58817#define LPI2C_MIER_EPIE_SHIFT (8U)
58822#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
58823
58824#define LPI2C_MIER_SDIE_MASK (0x200U)
58825#define LPI2C_MIER_SDIE_SHIFT (9U)
58830#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
58831
58832#define LPI2C_MIER_NDIE_MASK (0x400U)
58833#define LPI2C_MIER_NDIE_SHIFT (10U)
58838#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
58839
58840#define LPI2C_MIER_ALIE_MASK (0x800U)
58841#define LPI2C_MIER_ALIE_SHIFT (11U)
58846#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
58847
58848#define LPI2C_MIER_FEIE_MASK (0x1000U)
58849#define LPI2C_MIER_FEIE_SHIFT (12U)
58854#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
58855
58856#define LPI2C_MIER_PLTIE_MASK (0x2000U)
58857#define LPI2C_MIER_PLTIE_SHIFT (13U)
58862#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
58863
58864#define LPI2C_MIER_DMIE_MASK (0x4000U)
58865#define LPI2C_MIER_DMIE_SHIFT (14U)
58870#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
58876#define LPI2C_MDER_TDDE_MASK (0x1U)
58877#define LPI2C_MDER_TDDE_SHIFT (0U)
58882#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
58883
58884#define LPI2C_MDER_RDDE_MASK (0x2U)
58885#define LPI2C_MDER_RDDE_SHIFT (1U)
58890#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
58896#define LPI2C_MCFGR0_HREN_MASK (0x1U)
58897#define LPI2C_MCFGR0_HREN_SHIFT (0U)
58902#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
58903
58904#define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
58905#define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
58910#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
58911
58912#define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
58913#define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
58918#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
58919
58920#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
58921#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
58926#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
58927
58928#define LPI2C_MCFGR0_RDMO_MASK (0x200U)
58929#define LPI2C_MCFGR0_RDMO_SHIFT (9U)
58934#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
58940#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
58941#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
58952#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
58953
58954#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
58955#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
58960#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
58961
58962#define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
58963#define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
58968#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
58969
58970#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
58971#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
58976#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
58977
58978#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
58979#define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
58990#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
58991
58992#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
58993#define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
59004#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
59010#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
59011#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
59014#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
59015
59016#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
59017#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
59020#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
59021
59022#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
59023#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
59026#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
59032#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
59033#define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
59036#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
59042#define LPI2C_MDMR_MATCH0_MASK (0xFFU)
59043#define LPI2C_MDMR_MATCH0_SHIFT (0U)
59046#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
59047
59048#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
59049#define LPI2C_MDMR_MATCH1_SHIFT (16U)
59052#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
59058#define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
59059#define LPI2C_MCCR0_CLKLO_SHIFT (0U)
59062#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
59063
59064#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
59065#define LPI2C_MCCR0_CLKHI_SHIFT (8U)
59068#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
59069
59070#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
59071#define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
59074#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
59075
59076#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
59077#define LPI2C_MCCR0_DATAVD_SHIFT (24U)
59080#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
59086#define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
59087#define LPI2C_MCCR1_CLKLO_SHIFT (0U)
59090#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
59091
59092#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
59093#define LPI2C_MCCR1_CLKHI_SHIFT (8U)
59096#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
59097
59098#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
59099#define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
59102#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
59103
59104#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
59105#define LPI2C_MCCR1_DATAVD_SHIFT (24U)
59108#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
59114#define LPI2C_MFCR_TXWATER_MASK (0x3U)
59115#define LPI2C_MFCR_TXWATER_SHIFT (0U)
59118#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
59119
59120#define LPI2C_MFCR_RXWATER_MASK (0x30000U)
59121#define LPI2C_MFCR_RXWATER_SHIFT (16U)
59124#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
59130#define LPI2C_MFSR_TXCOUNT_MASK (0x7U)
59131#define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
59134#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
59135
59136#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U)
59137#define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
59140#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
59146#define LPI2C_MTDR_DATA_MASK (0xFFU)
59147#define LPI2C_MTDR_DATA_SHIFT (0U)
59150#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
59151
59152#define LPI2C_MTDR_CMD_MASK (0x700U)
59153#define LPI2C_MTDR_CMD_SHIFT (8U)
59164#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
59170#define LPI2C_MRDR_DATA_MASK (0xFFU)
59171#define LPI2C_MRDR_DATA_SHIFT (0U)
59174#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
59175
59176#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
59177#define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
59182#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
59188#define LPI2C_SCR_SEN_MASK (0x1U)
59189#define LPI2C_SCR_SEN_SHIFT (0U)
59194#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
59195
59196#define LPI2C_SCR_RST_MASK (0x2U)
59197#define LPI2C_SCR_RST_SHIFT (1U)
59202#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
59203
59204#define LPI2C_SCR_FILTEN_MASK (0x10U)
59205#define LPI2C_SCR_FILTEN_SHIFT (4U)
59210#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
59211
59212#define LPI2C_SCR_FILTDZ_MASK (0x20U)
59213#define LPI2C_SCR_FILTDZ_SHIFT (5U)
59218#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
59219
59220#define LPI2C_SCR_RTF_MASK (0x100U)
59221#define LPI2C_SCR_RTF_SHIFT (8U)
59226#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
59227
59228#define LPI2C_SCR_RRF_MASK (0x200U)
59229#define LPI2C_SCR_RRF_SHIFT (9U)
59234#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
59240#define LPI2C_SSR_TDF_MASK (0x1U)
59241#define LPI2C_SSR_TDF_SHIFT (0U)
59246#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
59247
59248#define LPI2C_SSR_RDF_MASK (0x2U)
59249#define LPI2C_SSR_RDF_SHIFT (1U)
59254#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
59255
59256#define LPI2C_SSR_AVF_MASK (0x4U)
59257#define LPI2C_SSR_AVF_SHIFT (2U)
59262#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
59263
59264#define LPI2C_SSR_TAF_MASK (0x8U)
59265#define LPI2C_SSR_TAF_SHIFT (3U)
59270#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
59271
59272#define LPI2C_SSR_RSF_MASK (0x100U)
59273#define LPI2C_SSR_RSF_SHIFT (8U)
59278#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
59279
59280#define LPI2C_SSR_SDF_MASK (0x200U)
59281#define LPI2C_SSR_SDF_SHIFT (9U)
59286#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
59287
59288#define LPI2C_SSR_BEF_MASK (0x400U)
59289#define LPI2C_SSR_BEF_SHIFT (10U)
59294#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
59295
59296#define LPI2C_SSR_FEF_MASK (0x800U)
59297#define LPI2C_SSR_FEF_SHIFT (11U)
59302#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
59303
59304#define LPI2C_SSR_AM0F_MASK (0x1000U)
59305#define LPI2C_SSR_AM0F_SHIFT (12U)
59310#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
59311
59312#define LPI2C_SSR_AM1F_MASK (0x2000U)
59313#define LPI2C_SSR_AM1F_SHIFT (13U)
59318#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
59319
59320#define LPI2C_SSR_GCF_MASK (0x4000U)
59321#define LPI2C_SSR_GCF_SHIFT (14U)
59326#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
59327
59328#define LPI2C_SSR_SARF_MASK (0x8000U)
59329#define LPI2C_SSR_SARF_SHIFT (15U)
59334#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
59335
59336#define LPI2C_SSR_SBF_MASK (0x1000000U)
59337#define LPI2C_SSR_SBF_SHIFT (24U)
59342#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
59343
59344#define LPI2C_SSR_BBF_MASK (0x2000000U)
59345#define LPI2C_SSR_BBF_SHIFT (25U)
59350#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
59356#define LPI2C_SIER_TDIE_MASK (0x1U)
59357#define LPI2C_SIER_TDIE_SHIFT (0U)
59362#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
59363
59364#define LPI2C_SIER_RDIE_MASK (0x2U)
59365#define LPI2C_SIER_RDIE_SHIFT (1U)
59370#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
59371
59372#define LPI2C_SIER_AVIE_MASK (0x4U)
59373#define LPI2C_SIER_AVIE_SHIFT (2U)
59378#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
59379
59380#define LPI2C_SIER_TAIE_MASK (0x8U)
59381#define LPI2C_SIER_TAIE_SHIFT (3U)
59386#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
59387
59388#define LPI2C_SIER_RSIE_MASK (0x100U)
59389#define LPI2C_SIER_RSIE_SHIFT (8U)
59394#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
59395
59396#define LPI2C_SIER_SDIE_MASK (0x200U)
59397#define LPI2C_SIER_SDIE_SHIFT (9U)
59402#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
59403
59404#define LPI2C_SIER_BEIE_MASK (0x400U)
59405#define LPI2C_SIER_BEIE_SHIFT (10U)
59410#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
59411
59412#define LPI2C_SIER_FEIE_MASK (0x800U)
59413#define LPI2C_SIER_FEIE_SHIFT (11U)
59418#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
59419
59420#define LPI2C_SIER_AM0IE_MASK (0x1000U)
59421#define LPI2C_SIER_AM0IE_SHIFT (12U)
59426#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
59427
59428#define LPI2C_SIER_AM1IE_MASK (0x2000U)
59429#define LPI2C_SIER_AM1IE_SHIFT (13U)
59434#define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)
59435
59436#define LPI2C_SIER_GCIE_MASK (0x4000U)
59437#define LPI2C_SIER_GCIE_SHIFT (14U)
59442#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
59443
59444#define LPI2C_SIER_SARIE_MASK (0x8000U)
59445#define LPI2C_SIER_SARIE_SHIFT (15U)
59450#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
59456#define LPI2C_SDER_TDDE_MASK (0x1U)
59457#define LPI2C_SDER_TDDE_SHIFT (0U)
59462#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
59463
59464#define LPI2C_SDER_RDDE_MASK (0x2U)
59465#define LPI2C_SDER_RDDE_SHIFT (1U)
59470#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
59471
59472#define LPI2C_SDER_AVDE_MASK (0x4U)
59473#define LPI2C_SDER_AVDE_SHIFT (2U)
59478#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
59484#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
59485#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
59490#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
59491
59492#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
59493#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
59498#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
59499
59500#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
59501#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
59506#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
59507
59508#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
59509#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
59514#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
59515
59516#define LPI2C_SCFGR1_GCEN_MASK (0x100U)
59517#define LPI2C_SCFGR1_GCEN_SHIFT (8U)
59522#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
59523
59524#define LPI2C_SCFGR1_SAEN_MASK (0x200U)
59525#define LPI2C_SCFGR1_SAEN_SHIFT (9U)
59530#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
59531
59532#define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
59533#define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
59538#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
59539
59540#define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
59541#define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
59548#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
59549
59550#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
59551#define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
59556#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
59557
59558#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
59559#define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
59564#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
59565
59566#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
59567#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
59578#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
59584#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
59585#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
59588#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
59589
59590#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
59591#define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
59594#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
59595
59596#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
59597#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
59600#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
59601
59602#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
59603#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
59606#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
59612#define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
59613#define LPI2C_SAMR_ADDR0_SHIFT (1U)
59616#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
59617
59618#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
59619#define LPI2C_SAMR_ADDR1_SHIFT (17U)
59622#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
59628#define LPI2C_SASR_RADDR_MASK (0x7FFU)
59629#define LPI2C_SASR_RADDR_SHIFT (0U)
59632#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
59633
59634#define LPI2C_SASR_ANV_MASK (0x4000U)
59635#define LPI2C_SASR_ANV_SHIFT (14U)
59640#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
59646#define LPI2C_STAR_TXNACK_MASK (0x1U)
59647#define LPI2C_STAR_TXNACK_SHIFT (0U)
59652#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
59658#define LPI2C_STDR_DATA_MASK (0xFFU)
59659#define LPI2C_STDR_DATA_SHIFT (0U)
59662#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
59668#define LPI2C_SRDR_DATA_MASK (0xFFU)
59669#define LPI2C_SRDR_DATA_SHIFT (0U)
59672#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
59673
59674#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
59675#define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
59680#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
59681
59682#define LPI2C_SRDR_SOF_MASK (0x8000U)
59683#define LPI2C_SRDR_SOF_SHIFT (15U)
59688#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) /* end of group LPI2C_Register_Masks */
59695
59696
59697/* LPI2C - Peripheral instance base addresses */
59699#define LPI2C1_BASE (0x40104000u)
59701#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
59703#define LPI2C2_BASE (0x40108000u)
59705#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
59707#define LPI2C3_BASE (0x4010C000u)
59709#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE)
59711#define LPI2C4_BASE (0x40110000u)
59713#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE)
59715#define LPI2C5_BASE (0x40C34000u)
59717#define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE)
59719#define LPI2C6_BASE (0x40C38000u)
59721#define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE)
59723#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE }
59725#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6 }
59727#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn, LPI2C5_IRQn, LPI2C6_IRQn }
59728 /* end of group LPI2C_Peripheral_Access_Layer */
59732
59733
59734/* ----------------------------------------------------------------------------
59735 -- LPSPI Peripheral Access Layer
59736 ---------------------------------------------------------------------------- */
59737
59744typedef struct {
59745 __I uint32_t VERID;
59746 __I uint32_t PARAM;
59747 uint8_t RESERVED_0[8];
59748 __IO uint32_t CR;
59749 __IO uint32_t SR;
59750 __IO uint32_t IER;
59751 __IO uint32_t DER;
59752 __IO uint32_t CFGR0;
59753 __IO uint32_t CFGR1;
59754 uint8_t RESERVED_1[8];
59755 __IO uint32_t DMR0;
59756 __IO uint32_t DMR1;
59757 uint8_t RESERVED_2[8];
59758 __IO uint32_t CCR;
59759 uint8_t RESERVED_3[20];
59760 __IO uint32_t FCR;
59761 __I uint32_t FSR;
59762 __IO uint32_t TCR;
59763 __O uint32_t TDR;
59764 uint8_t RESERVED_4[8];
59765 __I uint32_t RSR;
59766 __I uint32_t RDR;
59767} LPSPI_Type;
59768
59769/* ----------------------------------------------------------------------------
59770 -- LPSPI Register Masks
59771 ---------------------------------------------------------------------------- */
59772
59781#define LPSPI_VERID_FEATURE_MASK (0xFFFFU)
59782#define LPSPI_VERID_FEATURE_SHIFT (0U)
59786#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
59787
59788#define LPSPI_VERID_MINOR_MASK (0xFF0000U)
59789#define LPSPI_VERID_MINOR_SHIFT (16U)
59792#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
59793
59794#define LPSPI_VERID_MAJOR_MASK (0xFF000000U)
59795#define LPSPI_VERID_MAJOR_SHIFT (24U)
59798#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
59804#define LPSPI_PARAM_TXFIFO_MASK (0xFFU)
59805#define LPSPI_PARAM_TXFIFO_SHIFT (0U)
59808#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
59809
59810#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
59811#define LPSPI_PARAM_RXFIFO_SHIFT (8U)
59814#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
59815
59816#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)
59817#define LPSPI_PARAM_PCSNUM_SHIFT (16U)
59820#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
59826#define LPSPI_CR_MEN_MASK (0x1U)
59827#define LPSPI_CR_MEN_SHIFT (0U)
59832#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
59833
59834#define LPSPI_CR_RST_MASK (0x2U)
59835#define LPSPI_CR_RST_SHIFT (1U)
59840#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
59841
59842#define LPSPI_CR_DOZEN_MASK (0x4U)
59843#define LPSPI_CR_DOZEN_SHIFT (2U)
59848#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
59849
59850#define LPSPI_CR_DBGEN_MASK (0x8U)
59851#define LPSPI_CR_DBGEN_SHIFT (3U)
59856#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
59857
59858#define LPSPI_CR_RTF_MASK (0x100U)
59859#define LPSPI_CR_RTF_SHIFT (8U)
59864#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
59865
59866#define LPSPI_CR_RRF_MASK (0x200U)
59867#define LPSPI_CR_RRF_SHIFT (9U)
59872#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
59878#define LPSPI_SR_TDF_MASK (0x1U)
59879#define LPSPI_SR_TDF_SHIFT (0U)
59884#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
59885
59886#define LPSPI_SR_RDF_MASK (0x2U)
59887#define LPSPI_SR_RDF_SHIFT (1U)
59892#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
59893
59894#define LPSPI_SR_WCF_MASK (0x100U)
59895#define LPSPI_SR_WCF_SHIFT (8U)
59900#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
59901
59902#define LPSPI_SR_FCF_MASK (0x200U)
59903#define LPSPI_SR_FCF_SHIFT (9U)
59908#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
59909
59910#define LPSPI_SR_TCF_MASK (0x400U)
59911#define LPSPI_SR_TCF_SHIFT (10U)
59916#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
59917
59918#define LPSPI_SR_TEF_MASK (0x800U)
59919#define LPSPI_SR_TEF_SHIFT (11U)
59924#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
59925
59926#define LPSPI_SR_REF_MASK (0x1000U)
59927#define LPSPI_SR_REF_SHIFT (12U)
59932#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
59933
59934#define LPSPI_SR_DMF_MASK (0x2000U)
59935#define LPSPI_SR_DMF_SHIFT (13U)
59940#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
59941
59942#define LPSPI_SR_MBF_MASK (0x1000000U)
59943#define LPSPI_SR_MBF_SHIFT (24U)
59948#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
59954#define LPSPI_IER_TDIE_MASK (0x1U)
59955#define LPSPI_IER_TDIE_SHIFT (0U)
59960#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
59961
59962#define LPSPI_IER_RDIE_MASK (0x2U)
59963#define LPSPI_IER_RDIE_SHIFT (1U)
59968#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
59969
59970#define LPSPI_IER_WCIE_MASK (0x100U)
59971#define LPSPI_IER_WCIE_SHIFT (8U)
59976#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
59977
59978#define LPSPI_IER_FCIE_MASK (0x200U)
59979#define LPSPI_IER_FCIE_SHIFT (9U)
59984#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
59985
59986#define LPSPI_IER_TCIE_MASK (0x400U)
59987#define LPSPI_IER_TCIE_SHIFT (10U)
59992#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
59993
59994#define LPSPI_IER_TEIE_MASK (0x800U)
59995#define LPSPI_IER_TEIE_SHIFT (11U)
60000#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
60001
60002#define LPSPI_IER_REIE_MASK (0x1000U)
60003#define LPSPI_IER_REIE_SHIFT (12U)
60008#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
60009
60010#define LPSPI_IER_DMIE_MASK (0x2000U)
60011#define LPSPI_IER_DMIE_SHIFT (13U)
60016#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
60022#define LPSPI_DER_TDDE_MASK (0x1U)
60023#define LPSPI_DER_TDDE_SHIFT (0U)
60028#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
60029
60030#define LPSPI_DER_RDDE_MASK (0x2U)
60031#define LPSPI_DER_RDDE_SHIFT (1U)
60036#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
60041#ifdef __rtems__
60042#define LPSPI_CFGR0_HREN_MASK (0x1U)
60043#define LPSPI_CFGR0_HREN_SHIFT (0U)
60048#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
60049
60050#define LPSPI_CFGR0_HRPOL_MASK (0x2U)
60051#define LPSPI_CFGR0_HRPOL_SHIFT (1U)
60056#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
60057
60058#define LPSPI_CFGR0_HRSEL_MASK (0x4U)
60059#define LPSPI_CFGR0_HRSEL_SHIFT (2U)
60064#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
60065#endif /* __rtems__ */
60066
60067#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
60068#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
60073#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
60074
60075#define LPSPI_CFGR0_RDMO_MASK (0x200U)
60076#define LPSPI_CFGR0_RDMO_SHIFT (9U)
60081#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
60087#define LPSPI_CFGR1_MASTER_MASK (0x1U)
60088#define LPSPI_CFGR1_MASTER_SHIFT (0U)
60093#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
60094
60095#define LPSPI_CFGR1_SAMPLE_MASK (0x2U)
60096#define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
60101#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
60102
60103#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
60104#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
60109#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
60110
60111#define LPSPI_CFGR1_NOSTALL_MASK (0x8U)
60112#define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
60117#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
60118
60119#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
60120#define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
60123#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
60124
60125#define LPSPI_CFGR1_MATCFG_MASK (0x70000U)
60126#define LPSPI_CFGR1_MATCFG_SHIFT (16U)
60137#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
60138
60139#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
60140#define LPSPI_CFGR1_PINCFG_SHIFT (24U)
60147#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
60148
60149#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
60150#define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
60155#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
60156
60157#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
60158#define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
60163#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
60169#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
60170#define LPSPI_DMR0_MATCH0_SHIFT (0U)
60173#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
60179#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
60180#define LPSPI_DMR1_MATCH1_SHIFT (0U)
60183#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
60189#define LPSPI_CCR_SCKDIV_MASK (0xFFU)
60190#define LPSPI_CCR_SCKDIV_SHIFT (0U)
60193#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
60194
60195#define LPSPI_CCR_DBT_MASK (0xFF00U)
60196#define LPSPI_CCR_DBT_SHIFT (8U)
60199#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
60200
60201#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
60202#define LPSPI_CCR_PCSSCK_SHIFT (16U)
60205#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
60206
60207#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
60208#define LPSPI_CCR_SCKPCS_SHIFT (24U)
60211#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
60217#define LPSPI_FCR_TXWATER_MASK (0xFU)
60218#define LPSPI_FCR_TXWATER_SHIFT (0U)
60221#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
60222
60223#define LPSPI_FCR_RXWATER_MASK (0xF0000U)
60224#define LPSPI_FCR_RXWATER_SHIFT (16U)
60227#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
60233#define LPSPI_FSR_TXCOUNT_MASK (0x1FU)
60234#define LPSPI_FSR_TXCOUNT_SHIFT (0U)
60237#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
60238
60239#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)
60240#define LPSPI_FSR_RXCOUNT_SHIFT (16U)
60243#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
60249#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
60250#define LPSPI_TCR_FRAMESZ_SHIFT (0U)
60253#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
60254
60255#define LPSPI_TCR_WIDTH_MASK (0x30000U)
60256#define LPSPI_TCR_WIDTH_SHIFT (16U)
60263#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
60264
60265#define LPSPI_TCR_TXMSK_MASK (0x40000U)
60266#define LPSPI_TCR_TXMSK_SHIFT (18U)
60271#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
60272
60273#define LPSPI_TCR_RXMSK_MASK (0x80000U)
60274#define LPSPI_TCR_RXMSK_SHIFT (19U)
60279#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
60280
60281#define LPSPI_TCR_CONTC_MASK (0x100000U)
60282#define LPSPI_TCR_CONTC_SHIFT (20U)
60287#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
60288
60289#define LPSPI_TCR_CONT_MASK (0x200000U)
60290#define LPSPI_TCR_CONT_SHIFT (21U)
60295#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
60296
60297#define LPSPI_TCR_BYSW_MASK (0x400000U)
60298#define LPSPI_TCR_BYSW_SHIFT (22U)
60303#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
60304
60305#define LPSPI_TCR_LSBF_MASK (0x800000U)
60306#define LPSPI_TCR_LSBF_SHIFT (23U)
60311#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
60312
60313#define LPSPI_TCR_PCS_MASK (0x3000000U)
60314#define LPSPI_TCR_PCS_SHIFT (24U)
60321#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
60322
60323#define LPSPI_TCR_PRESCALE_MASK (0x38000000U)
60324#define LPSPI_TCR_PRESCALE_SHIFT (27U)
60335#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
60336
60337#define LPSPI_TCR_CPHA_MASK (0x40000000U)
60338#define LPSPI_TCR_CPHA_SHIFT (30U)
60343#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
60344
60345#define LPSPI_TCR_CPOL_MASK (0x80000000U)
60346#define LPSPI_TCR_CPOL_SHIFT (31U)
60351#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
60357#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
60358#define LPSPI_TDR_DATA_SHIFT (0U)
60361#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
60367#define LPSPI_RSR_SOF_MASK (0x1U)
60368#define LPSPI_RSR_SOF_SHIFT (0U)
60373#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
60374
60375#define LPSPI_RSR_RXEMPTY_MASK (0x2U)
60376#define LPSPI_RSR_RXEMPTY_SHIFT (1U)
60381#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
60387#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
60388#define LPSPI_RDR_DATA_SHIFT (0U)
60391#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) /* end of group LPSPI_Register_Masks */
60398
60399
60400/* LPSPI - Peripheral instance base addresses */
60402#define LPSPI1_BASE (0x40114000u)
60404#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
60406#define LPSPI2_BASE (0x40118000u)
60408#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
60410#define LPSPI3_BASE (0x4011C000u)
60412#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE)
60414#define LPSPI4_BASE (0x40120000u)
60416#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE)
60418#define LPSPI5_BASE (0x40C2C000u)
60420#define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE)
60422#define LPSPI6_BASE (0x40C30000u)
60424#define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE)
60426#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE }
60428#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6 }
60430#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn, LPSPI5_IRQn, LPSPI6_IRQn }
60431 /* end of group LPSPI_Peripheral_Access_Layer */
60435
60436
60437/* ----------------------------------------------------------------------------
60438 -- LPUART Peripheral Access Layer
60439 ---------------------------------------------------------------------------- */
60440
60447typedef struct {
60448 __I uint32_t VERID;
60449 __I uint32_t PARAM;
60450 __IO uint32_t GLOBAL;
60451 __IO uint32_t PINCFG;
60452 __IO uint32_t BAUD;
60453 __IO uint32_t STAT;
60454 __IO uint32_t CTRL;
60455 __IO uint32_t DATA;
60456 __IO uint32_t MATCH;
60457 __IO uint32_t MODIR;
60458 __IO uint32_t FIFO;
60459 __IO uint32_t WATER;
60460} LPUART_Type;
60461
60462/* ----------------------------------------------------------------------------
60463 -- LPUART Register Masks
60464 ---------------------------------------------------------------------------- */
60465
60474#define LPUART_VERID_FEATURE_MASK (0xFFFFU)
60475#define LPUART_VERID_FEATURE_SHIFT (0U)
60480#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
60481
60482#define LPUART_VERID_MINOR_MASK (0xFF0000U)
60483#define LPUART_VERID_MINOR_SHIFT (16U)
60486#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
60487
60488#define LPUART_VERID_MAJOR_MASK (0xFF000000U)
60489#define LPUART_VERID_MAJOR_SHIFT (24U)
60492#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
60498#define LPUART_PARAM_TXFIFO_MASK (0xFFU)
60499#define LPUART_PARAM_TXFIFO_SHIFT (0U)
60502#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
60503
60504#define LPUART_PARAM_RXFIFO_MASK (0xFF00U)
60505#define LPUART_PARAM_RXFIFO_SHIFT (8U)
60508#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
60514#define LPUART_GLOBAL_RST_MASK (0x2U)
60515#define LPUART_GLOBAL_RST_SHIFT (1U)
60520#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
60526#define LPUART_PINCFG_TRGSEL_MASK (0x3U)
60527#define LPUART_PINCFG_TRGSEL_SHIFT (0U)
60535#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
60541#define LPUART_BAUD_SBR_MASK (0x1FFFU)
60542#define LPUART_BAUD_SBR_SHIFT (0U)
60545#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
60546
60547#define LPUART_BAUD_SBNS_MASK (0x2000U)
60548#define LPUART_BAUD_SBNS_SHIFT (13U)
60553#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
60554
60555#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
60556#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
60561#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
60562
60563#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
60564#define LPUART_BAUD_LBKDIE_SHIFT (15U)
60569#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
60570
60571#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
60572#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
60577#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
60578
60579#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
60580#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
60585#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
60586
60587#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
60588#define LPUART_BAUD_MATCFG_SHIFT (18U)
60595#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
60596
60597#define LPUART_BAUD_RDMAE_MASK (0x200000U)
60598#define LPUART_BAUD_RDMAE_SHIFT (21U)
60603#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
60604
60605#define LPUART_BAUD_TDMAE_MASK (0x800000U)
60606#define LPUART_BAUD_TDMAE_SHIFT (23U)
60611#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
60612
60613#define LPUART_BAUD_OSR_MASK (0x1F000000U)
60614#define LPUART_BAUD_OSR_SHIFT (24U)
60649#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
60650
60651#define LPUART_BAUD_M10_MASK (0x20000000U)
60652#define LPUART_BAUD_M10_SHIFT (29U)
60657#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
60658
60659#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
60660#define LPUART_BAUD_MAEN2_SHIFT (30U)
60665#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
60666
60667#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
60668#define LPUART_BAUD_MAEN1_SHIFT (31U)
60673#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
60679#define LPUART_STAT_MA2F_MASK (0x4000U)
60680#define LPUART_STAT_MA2F_SHIFT (14U)
60685#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
60686
60687#define LPUART_STAT_MA1F_MASK (0x8000U)
60688#define LPUART_STAT_MA1F_SHIFT (15U)
60693#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
60694
60695#define LPUART_STAT_PF_MASK (0x10000U)
60696#define LPUART_STAT_PF_SHIFT (16U)
60701#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
60702
60703#define LPUART_STAT_FE_MASK (0x20000U)
60704#define LPUART_STAT_FE_SHIFT (17U)
60709#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
60710
60711#define LPUART_STAT_NF_MASK (0x40000U)
60712#define LPUART_STAT_NF_SHIFT (18U)
60717#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
60718
60719#define LPUART_STAT_OR_MASK (0x80000U)
60720#define LPUART_STAT_OR_SHIFT (19U)
60725#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
60726
60727#define LPUART_STAT_IDLE_MASK (0x100000U)
60728#define LPUART_STAT_IDLE_SHIFT (20U)
60733#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
60734
60735#define LPUART_STAT_RDRF_MASK (0x200000U)
60736#define LPUART_STAT_RDRF_SHIFT (21U)
60741#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
60742
60743#define LPUART_STAT_TC_MASK (0x400000U)
60744#define LPUART_STAT_TC_SHIFT (22U)
60749#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
60750
60751#define LPUART_STAT_TDRE_MASK (0x800000U)
60752#define LPUART_STAT_TDRE_SHIFT (23U)
60757#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
60758
60759#define LPUART_STAT_RAF_MASK (0x1000000U)
60760#define LPUART_STAT_RAF_SHIFT (24U)
60765#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
60766
60767#define LPUART_STAT_LBKDE_MASK (0x2000000U)
60768#define LPUART_STAT_LBKDE_SHIFT (25U)
60773#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
60774
60775#define LPUART_STAT_BRK13_MASK (0x4000000U)
60776#define LPUART_STAT_BRK13_SHIFT (26U)
60781#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
60782
60783#define LPUART_STAT_RWUID_MASK (0x8000000U)
60784#define LPUART_STAT_RWUID_SHIFT (27U)
60791#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
60792
60793#define LPUART_STAT_RXINV_MASK (0x10000000U)
60794#define LPUART_STAT_RXINV_SHIFT (28U)
60799#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
60800
60801#define LPUART_STAT_MSBF_MASK (0x20000000U)
60802#define LPUART_STAT_MSBF_SHIFT (29U)
60809#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
60810
60811#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
60812#define LPUART_STAT_RXEDGIF_SHIFT (30U)
60817#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
60818
60819#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
60820#define LPUART_STAT_LBKDIF_SHIFT (31U)
60825#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
60831#define LPUART_CTRL_PT_MASK (0x1U)
60832#define LPUART_CTRL_PT_SHIFT (0U)
60837#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
60838
60839#define LPUART_CTRL_PE_MASK (0x2U)
60840#define LPUART_CTRL_PE_SHIFT (1U)
60845#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
60846
60847#define LPUART_CTRL_ILT_MASK (0x4U)
60848#define LPUART_CTRL_ILT_SHIFT (2U)
60853#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
60854
60855#define LPUART_CTRL_WAKE_MASK (0x8U)
60856#define LPUART_CTRL_WAKE_SHIFT (3U)
60861#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
60862
60863#define LPUART_CTRL_M_MASK (0x10U)
60864#define LPUART_CTRL_M_SHIFT (4U)
60869#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
60870
60871#define LPUART_CTRL_RSRC_MASK (0x20U)
60872#define LPUART_CTRL_RSRC_SHIFT (5U)
60877#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
60878
60879#define LPUART_CTRL_DOZEEN_MASK (0x40U)
60880#define LPUART_CTRL_DOZEEN_SHIFT (6U)
60885#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
60886
60887#define LPUART_CTRL_LOOPS_MASK (0x80U)
60888#define LPUART_CTRL_LOOPS_SHIFT (7U)
60893#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
60894
60895#define LPUART_CTRL_IDLECFG_MASK (0x700U)
60896#define LPUART_CTRL_IDLECFG_SHIFT (8U)
60907#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
60908
60909#define LPUART_CTRL_M7_MASK (0x800U)
60910#define LPUART_CTRL_M7_SHIFT (11U)
60915#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
60916
60917#define LPUART_CTRL_MA2IE_MASK (0x4000U)
60918#define LPUART_CTRL_MA2IE_SHIFT (14U)
60923#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
60924
60925#define LPUART_CTRL_MA1IE_MASK (0x8000U)
60926#define LPUART_CTRL_MA1IE_SHIFT (15U)
60931#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
60932
60933#define LPUART_CTRL_SBK_MASK (0x10000U)
60934#define LPUART_CTRL_SBK_SHIFT (16U)
60939#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
60940
60941#define LPUART_CTRL_RWU_MASK (0x20000U)
60942#define LPUART_CTRL_RWU_SHIFT (17U)
60947#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
60948
60949#define LPUART_CTRL_RE_MASK (0x40000U)
60950#define LPUART_CTRL_RE_SHIFT (18U)
60955#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
60956
60957#define LPUART_CTRL_TE_MASK (0x80000U)
60958#define LPUART_CTRL_TE_SHIFT (19U)
60963#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
60964
60965#define LPUART_CTRL_ILIE_MASK (0x100000U)
60966#define LPUART_CTRL_ILIE_SHIFT (20U)
60971#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
60972
60973#define LPUART_CTRL_RIE_MASK (0x200000U)
60974#define LPUART_CTRL_RIE_SHIFT (21U)
60979#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
60980
60981#define LPUART_CTRL_TCIE_MASK (0x400000U)
60982#define LPUART_CTRL_TCIE_SHIFT (22U)
60987#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
60988
60989#define LPUART_CTRL_TIE_MASK (0x800000U)
60990#define LPUART_CTRL_TIE_SHIFT (23U)
60995#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
60996
60997#define LPUART_CTRL_PEIE_MASK (0x1000000U)
60998#define LPUART_CTRL_PEIE_SHIFT (24U)
61003#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
61004
61005#define LPUART_CTRL_FEIE_MASK (0x2000000U)
61006#define LPUART_CTRL_FEIE_SHIFT (25U)
61011#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
61012
61013#define LPUART_CTRL_NEIE_MASK (0x4000000U)
61014#define LPUART_CTRL_NEIE_SHIFT (26U)
61019#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
61020
61021#define LPUART_CTRL_ORIE_MASK (0x8000000U)
61022#define LPUART_CTRL_ORIE_SHIFT (27U)
61027#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
61028
61029#define LPUART_CTRL_TXINV_MASK (0x10000000U)
61030#define LPUART_CTRL_TXINV_SHIFT (28U)
61035#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
61036
61037#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
61038#define LPUART_CTRL_TXDIR_SHIFT (29U)
61043#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
61044
61045#define LPUART_CTRL_R9T8_MASK (0x40000000U)
61046#define LPUART_CTRL_R9T8_SHIFT (30U)
61049#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
61050
61051#define LPUART_CTRL_R8T9_MASK (0x80000000U)
61052#define LPUART_CTRL_R8T9_SHIFT (31U)
61055#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
61061#define LPUART_DATA_R0T0_MASK (0x1U)
61062#define LPUART_DATA_R0T0_SHIFT (0U)
61065#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
61066
61067#define LPUART_DATA_R1T1_MASK (0x2U)
61068#define LPUART_DATA_R1T1_SHIFT (1U)
61071#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
61072
61073#define LPUART_DATA_R2T2_MASK (0x4U)
61074#define LPUART_DATA_R2T2_SHIFT (2U)
61077#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
61078
61079#define LPUART_DATA_R3T3_MASK (0x8U)
61080#define LPUART_DATA_R3T3_SHIFT (3U)
61083#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
61084
61085#define LPUART_DATA_R4T4_MASK (0x10U)
61086#define LPUART_DATA_R4T4_SHIFT (4U)
61089#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
61090
61091#define LPUART_DATA_R5T5_MASK (0x20U)
61092#define LPUART_DATA_R5T5_SHIFT (5U)
61095#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
61096
61097#define LPUART_DATA_R6T6_MASK (0x40U)
61098#define LPUART_DATA_R6T6_SHIFT (6U)
61101#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
61102
61103#define LPUART_DATA_R7T7_MASK (0x80U)
61104#define LPUART_DATA_R7T7_SHIFT (7U)
61107#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
61108
61109#define LPUART_DATA_R8T8_MASK (0x100U)
61110#define LPUART_DATA_R8T8_SHIFT (8U)
61113#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
61114
61115#define LPUART_DATA_R9T9_MASK (0x200U)
61116#define LPUART_DATA_R9T9_SHIFT (9U)
61119#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
61120
61121#define LPUART_DATA_IDLINE_MASK (0x800U)
61122#define LPUART_DATA_IDLINE_SHIFT (11U)
61127#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
61128
61129#define LPUART_DATA_RXEMPT_MASK (0x1000U)
61130#define LPUART_DATA_RXEMPT_SHIFT (12U)
61135#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
61136
61137#define LPUART_DATA_FRETSC_MASK (0x2000U)
61138#define LPUART_DATA_FRETSC_SHIFT (13U)
61143#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
61144
61145#define LPUART_DATA_PARITYE_MASK (0x4000U)
61146#define LPUART_DATA_PARITYE_SHIFT (14U)
61151#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
61152
61153#define LPUART_DATA_NOISY_MASK (0x8000U)
61154#define LPUART_DATA_NOISY_SHIFT (15U)
61159#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
61165#define LPUART_MATCH_MA1_MASK (0x3FFU)
61166#define LPUART_MATCH_MA1_SHIFT (0U)
61169#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
61170
61171#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
61172#define LPUART_MATCH_MA2_SHIFT (16U)
61175#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
61181#define LPUART_MODIR_TXCTSE_MASK (0x1U)
61182#define LPUART_MODIR_TXCTSE_SHIFT (0U)
61190#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
61191
61192#define LPUART_MODIR_TXRTSE_MASK (0x2U)
61193#define LPUART_MODIR_TXRTSE_SHIFT (1U)
61200#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
61201
61202#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
61203#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
61208#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
61209
61210#define LPUART_MODIR_RXRTSE_MASK (0x8U)
61211#define LPUART_MODIR_RXRTSE_SHIFT (3U)
61218#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
61219
61220#define LPUART_MODIR_TXCTSC_MASK (0x10U)
61221#define LPUART_MODIR_TXCTSC_SHIFT (4U)
61226#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
61227
61228#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
61229#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
61234#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
61235
61236#define LPUART_MODIR_RTSWATER_MASK (0x300U)
61237#define LPUART_MODIR_RTSWATER_SHIFT (8U)
61240#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
61241
61242#define LPUART_MODIR_TNP_MASK (0x30000U)
61243#define LPUART_MODIR_TNP_SHIFT (16U)
61250#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
61251
61252#define LPUART_MODIR_IREN_MASK (0x40000U)
61253#define LPUART_MODIR_IREN_SHIFT (18U)
61258#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
61264#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
61265#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
61276#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
61277
61278#define LPUART_FIFO_RXFE_MASK (0x8U)
61279#define LPUART_FIFO_RXFE_SHIFT (3U)
61284#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
61285
61286#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
61287#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
61298#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
61299
61300#define LPUART_FIFO_TXFE_MASK (0x80U)
61301#define LPUART_FIFO_TXFE_SHIFT (7U)
61306#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
61307
61308#define LPUART_FIFO_RXUFE_MASK (0x100U)
61309#define LPUART_FIFO_RXUFE_SHIFT (8U)
61314#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
61315
61316#define LPUART_FIFO_TXOFE_MASK (0x200U)
61317#define LPUART_FIFO_TXOFE_SHIFT (9U)
61322#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
61323
61324#define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
61325#define LPUART_FIFO_RXIDEN_SHIFT (10U)
61336#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
61337
61338#define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
61339#define LPUART_FIFO_RXFLUSH_SHIFT (14U)
61344#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
61345
61346#define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
61347#define LPUART_FIFO_TXFLUSH_SHIFT (15U)
61352#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
61353
61354#define LPUART_FIFO_RXUF_MASK (0x10000U)
61355#define LPUART_FIFO_RXUF_SHIFT (16U)
61360#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
61361
61362#define LPUART_FIFO_TXOF_MASK (0x20000U)
61363#define LPUART_FIFO_TXOF_SHIFT (17U)
61368#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
61369
61370#define LPUART_FIFO_RXEMPT_MASK (0x400000U)
61371#define LPUART_FIFO_RXEMPT_SHIFT (22U)
61376#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
61377
61378#define LPUART_FIFO_TXEMPT_MASK (0x800000U)
61379#define LPUART_FIFO_TXEMPT_SHIFT (23U)
61384#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
61390#define LPUART_WATER_TXWATER_MASK (0x3U)
61391#define LPUART_WATER_TXWATER_SHIFT (0U)
61394#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
61395
61396#define LPUART_WATER_TXCOUNT_MASK (0x700U)
61397#define LPUART_WATER_TXCOUNT_SHIFT (8U)
61400#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
61401
61402#define LPUART_WATER_RXWATER_MASK (0x30000U)
61403#define LPUART_WATER_RXWATER_SHIFT (16U)
61406#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
61407
61408#define LPUART_WATER_RXCOUNT_MASK (0x7000000U)
61409#define LPUART_WATER_RXCOUNT_SHIFT (24U)
61412#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) /* end of group LPUART_Register_Masks */
61419
61420
61421/* LPUART - Peripheral instance base addresses */
61423#define LPUART1_BASE (0x4007C000u)
61425#define LPUART1 ((LPUART_Type *)LPUART1_BASE)
61427#define LPUART2_BASE (0x40080000u)
61429#define LPUART2 ((LPUART_Type *)LPUART2_BASE)
61431#define LPUART3_BASE (0x40084000u)
61433#define LPUART3 ((LPUART_Type *)LPUART3_BASE)
61435#define LPUART4_BASE (0x40088000u)
61437#define LPUART4 ((LPUART_Type *)LPUART4_BASE)
61439#define LPUART5_BASE (0x4008C000u)
61441#define LPUART5 ((LPUART_Type *)LPUART5_BASE)
61443#define LPUART6_BASE (0x40090000u)
61445#define LPUART6 ((LPUART_Type *)LPUART6_BASE)
61447#define LPUART7_BASE (0x40094000u)
61449#define LPUART7 ((LPUART_Type *)LPUART7_BASE)
61451#define LPUART8_BASE (0x40098000u)
61453#define LPUART8 ((LPUART_Type *)LPUART8_BASE)
61455#define LPUART9_BASE (0x4009C000u)
61457#define LPUART9 ((LPUART_Type *)LPUART9_BASE)
61459#define LPUART10_BASE (0x400A0000u)
61461#define LPUART10 ((LPUART_Type *)LPUART10_BASE)
61463#define LPUART11_BASE (0x40C24000u)
61465#define LPUART11 ((LPUART_Type *)LPUART11_BASE)
61467#define LPUART12_BASE (0x40C28000u)
61469#define LPUART12 ((LPUART_Type *)LPUART12_BASE)
61471#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE, LPUART10_BASE, LPUART11_BASE, LPUART12_BASE }
61473#define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LPUART10, LPUART11, LPUART12 }
61475#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn, LPUART9_IRQn, LPUART10_IRQn, LPUART11_IRQn, LPUART12_IRQn }
61476 /* end of group LPUART_Peripheral_Access_Layer */
61480
61481
61482/* ----------------------------------------------------------------------------
61483 -- MCM Peripheral Access Layer
61484 ---------------------------------------------------------------------------- */
61485
61492typedef struct {
61493 uint8_t RESERVED_0[16];
61494 __IO uint32_t ISCR;
61495} MCM_Type;
61496
61497/* ----------------------------------------------------------------------------
61498 -- MCM Register Masks
61499 ---------------------------------------------------------------------------- */
61500
61509#define MCM_ISCR_WABS_MASK (0x20U)
61510#define MCM_ISCR_WABS_SHIFT (5U)
61515#define MCM_ISCR_WABS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABS_SHIFT)) & MCM_ISCR_WABS_MASK)
61516
61517#define MCM_ISCR_WABSO_MASK (0x40U)
61518#define MCM_ISCR_WABSO_SHIFT (6U)
61523#define MCM_ISCR_WABSO(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABSO_SHIFT)) & MCM_ISCR_WABSO_MASK)
61524
61525#define MCM_ISCR_FIOC_MASK (0x100U)
61526#define MCM_ISCR_FIOC_SHIFT (8U)
61531#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
61532
61533#define MCM_ISCR_FDZC_MASK (0x200U)
61534#define MCM_ISCR_FDZC_SHIFT (9U)
61539#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
61540
61541#define MCM_ISCR_FOFC_MASK (0x400U)
61542#define MCM_ISCR_FOFC_SHIFT (10U)
61547#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
61548
61549#define MCM_ISCR_FUFC_MASK (0x800U)
61550#define MCM_ISCR_FUFC_SHIFT (11U)
61555#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
61556
61557#define MCM_ISCR_FIXC_MASK (0x1000U)
61558#define MCM_ISCR_FIXC_SHIFT (12U)
61563#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
61564
61565#define MCM_ISCR_FIDC_MASK (0x8000U)
61566#define MCM_ISCR_FIDC_SHIFT (15U)
61571#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
61572
61573#define MCM_ISCR_WABE_MASK (0x200000U)
61574#define MCM_ISCR_WABE_SHIFT (21U)
61579#define MCM_ISCR_WABE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABE_SHIFT)) & MCM_ISCR_WABE_MASK)
61580
61581#define MCM_ISCR_FIOCE_MASK (0x1000000U)
61582#define MCM_ISCR_FIOCE_SHIFT (24U)
61587#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
61588
61589#define MCM_ISCR_FDZCE_MASK (0x2000000U)
61590#define MCM_ISCR_FDZCE_SHIFT (25U)
61595#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
61596
61597#define MCM_ISCR_FOFCE_MASK (0x4000000U)
61598#define MCM_ISCR_FOFCE_SHIFT (26U)
61603#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
61604
61605#define MCM_ISCR_FUFCE_MASK (0x8000000U)
61606#define MCM_ISCR_FUFCE_SHIFT (27U)
61611#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
61612
61613#define MCM_ISCR_FIXCE_MASK (0x10000000U)
61614#define MCM_ISCR_FIXCE_SHIFT (28U)
61619#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
61620
61621#define MCM_ISCR_FIDCE_MASK (0x80000000U)
61622#define MCM_ISCR_FIDCE_SHIFT (31U)
61627#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) /* end of group MCM_Register_Masks */
61634
61635
61636/* MCM - Peripheral instance base addresses */
61638#define CM7_MCM_BASE (0xE0080000u)
61640#define CM7_MCM ((MCM_Type *)CM7_MCM_BASE)
61642#define MCM_BASE_ADDRS { CM7_MCM_BASE }
61644#define MCM_BASE_PTRS { CM7_MCM }
61645 /* end of group MCM_Peripheral_Access_Layer */
61649
61650
61651/* ----------------------------------------------------------------------------
61652 -- MECC Peripheral Access Layer
61653 ---------------------------------------------------------------------------- */
61654
61661typedef struct {
61662 __IO uint32_t ERR_STATUS;
61663 __IO uint32_t ERR_STAT_EN;
61664 __IO uint32_t ERR_SIG_EN;
61665 __IO uint32_t ERR_DATA_INJ_LOW0;
61666 __IO uint32_t ERR_DATA_INJ_HIGH0;
61667 __IO uint32_t ERR_ECC_INJ0;
61668 __IO uint32_t ERR_DATA_INJ_LOW1;
61669 __IO uint32_t ERR_DATA_INJ_HIGH1;
61670 __IO uint32_t ERR_ECC_INJ1;
61671 __IO uint32_t ERR_DATA_INJ_LOW2;
61672 __IO uint32_t ERR_DATA_INJ_HIGH2;
61673 __IO uint32_t ERR_ECC_INJ2;
61674 __IO uint32_t ERR_DATA_INJ_LOW3;
61675 __IO uint32_t ERR_DATA_INJ_HIGH3;
61676 __IO uint32_t ERR_ECC_INJ3;
61677 __I uint32_t SINGLE_ERR_ADDR_ECC0;
61678 __I uint32_t SINGLE_ERR_DATA_LOW0;
61679 __I uint32_t SINGLE_ERR_DATA_HIGH0;
61680 __I uint32_t SINGLE_ERR_POS_LOW0;
61681 __I uint32_t SINGLE_ERR_POS_HIGH0;
61682 __I uint32_t SINGLE_ERR_ADDR_ECC1;
61683 __I uint32_t SINGLE_ERR_DATA_LOW1;
61684 __I uint32_t SINGLE_ERR_DATA_HIGH1;
61685 __I uint32_t SINGLE_ERR_POS_LOW1;
61686 __I uint32_t SINGLE_ERR_POS_HIGH1;
61687 __I uint32_t SINGLE_ERR_ADDR_ECC2;
61688 __I uint32_t SINGLE_ERR_DATA_LOW2;
61689 __I uint32_t SINGLE_ERR_DATA_HIGH2;
61690 __I uint32_t SINGLE_ERR_POS_LOW2;
61691 __I uint32_t SINGLE_ERR_POS_HIGH2;
61692 __I uint32_t SINGLE_ERR_ADDR_ECC3;
61693 __I uint32_t SINGLE_ERR_DATA_LOW3;
61694 __I uint32_t SINGLE_ERR_DATA_HIGH3;
61695 __I uint32_t SINGLE_ERR_POS_LOW3;
61696 __I uint32_t SINGLE_ERR_POS_HIGH3;
61697 __I uint32_t MULTI_ERR_ADDR_ECC0;
61698 __I uint32_t MULTI_ERR_DATA_LOW0;
61699 __I uint32_t MULTI_ERR_DATA_HIGH0;
61700 __I uint32_t MULTI_ERR_ADDR_ECC1;
61701 __I uint32_t MULTI_ERR_DATA_LOW1;
61702 __I uint32_t MULTI_ERR_DATA_HIGH1;
61703 __I uint32_t MULTI_ERR_ADDR_ECC2;
61704 __I uint32_t MULTI_ERR_DATA_LOW2;
61705 __I uint32_t MULTI_ERR_DATA_HIGH2;
61706 __I uint32_t MULTI_ERR_ADDR_ECC3;
61707 __I uint32_t MULTI_ERR_DATA_LOW3;
61708 __I uint32_t MULTI_ERR_DATA_HIGH3;
61709 uint8_t RESERVED_0[68];
61710 __IO uint32_t PIPE_ECC_EN;
61711 __I uint32_t PENDING_STAT;
61712} MECC_Type;
61713
61714/* ----------------------------------------------------------------------------
61715 -- MECC Register Masks
61716 ---------------------------------------------------------------------------- */
61717
61726#define MECC_ERR_STATUS_SINGLE_ERR0_MASK (0x1U)
61727#define MECC_ERR_STATUS_SINGLE_ERR0_SHIFT (0U)
61732#define MECC_ERR_STATUS_SINGLE_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR0_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR0_MASK)
61733
61734#define MECC_ERR_STATUS_SINGLE_ERR1_MASK (0x2U)
61735#define MECC_ERR_STATUS_SINGLE_ERR1_SHIFT (1U)
61740#define MECC_ERR_STATUS_SINGLE_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR1_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR1_MASK)
61741
61742#define MECC_ERR_STATUS_SINGLE_ERR2_MASK (0x4U)
61743#define MECC_ERR_STATUS_SINGLE_ERR2_SHIFT (2U)
61748#define MECC_ERR_STATUS_SINGLE_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR2_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR2_MASK)
61749
61750#define MECC_ERR_STATUS_SINGLE_ERR3_MASK (0x8U)
61751#define MECC_ERR_STATUS_SINGLE_ERR3_SHIFT (3U)
61756#define MECC_ERR_STATUS_SINGLE_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR3_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR3_MASK)
61757
61758#define MECC_ERR_STATUS_MULTI_ERR0_MASK (0x10U)
61759#define MECC_ERR_STATUS_MULTI_ERR0_SHIFT (4U)
61764#define MECC_ERR_STATUS_MULTI_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR0_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR0_MASK)
61765
61766#define MECC_ERR_STATUS_MULTI_ERR1_MASK (0x20U)
61767#define MECC_ERR_STATUS_MULTI_ERR1_SHIFT (5U)
61772#define MECC_ERR_STATUS_MULTI_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR1_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR1_MASK)
61773
61774#define MECC_ERR_STATUS_MULTI_ERR2_MASK (0x40U)
61775#define MECC_ERR_STATUS_MULTI_ERR2_SHIFT (6U)
61780#define MECC_ERR_STATUS_MULTI_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR2_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR2_MASK)
61781
61782#define MECC_ERR_STATUS_MULTI_ERR3_MASK (0x80U)
61783#define MECC_ERR_STATUS_MULTI_ERR3_SHIFT (7U)
61788#define MECC_ERR_STATUS_MULTI_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR3_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR3_MASK)
61789
61790#define MECC_ERR_STATUS_STRB_ERR0_MASK (0x100U)
61791#define MECC_ERR_STATUS_STRB_ERR0_SHIFT (8U)
61796#define MECC_ERR_STATUS_STRB_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR0_SHIFT)) & MECC_ERR_STATUS_STRB_ERR0_MASK)
61797
61798#define MECC_ERR_STATUS_STRB_ERR1_MASK (0x200U)
61799#define MECC_ERR_STATUS_STRB_ERR1_SHIFT (9U)
61804#define MECC_ERR_STATUS_STRB_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR1_SHIFT)) & MECC_ERR_STATUS_STRB_ERR1_MASK)
61805
61806#define MECC_ERR_STATUS_STRB_ERR2_MASK (0x400U)
61807#define MECC_ERR_STATUS_STRB_ERR2_SHIFT (10U)
61812#define MECC_ERR_STATUS_STRB_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR2_SHIFT)) & MECC_ERR_STATUS_STRB_ERR2_MASK)
61813
61814#define MECC_ERR_STATUS_STRB_ERR3_MASK (0x800U)
61815#define MECC_ERR_STATUS_STRB_ERR3_SHIFT (11U)
61820#define MECC_ERR_STATUS_STRB_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR3_SHIFT)) & MECC_ERR_STATUS_STRB_ERR3_MASK)
61821
61822#define MECC_ERR_STATUS_ADDR_ERR0_MASK (0x1000U)
61823#define MECC_ERR_STATUS_ADDR_ERR0_SHIFT (12U)
61828#define MECC_ERR_STATUS_ADDR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR0_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR0_MASK)
61829
61830#define MECC_ERR_STATUS_ADDR_ERR1_MASK (0x2000U)
61831#define MECC_ERR_STATUS_ADDR_ERR1_SHIFT (13U)
61836#define MECC_ERR_STATUS_ADDR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR1_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR1_MASK)
61837
61838#define MECC_ERR_STATUS_ADDR_ERR2_MASK (0x4000U)
61839#define MECC_ERR_STATUS_ADDR_ERR2_SHIFT (14U)
61844#define MECC_ERR_STATUS_ADDR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR2_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR2_MASK)
61845
61846#define MECC_ERR_STATUS_ADDR_ERR3_MASK (0x8000U)
61847#define MECC_ERR_STATUS_ADDR_ERR3_SHIFT (15U)
61852#define MECC_ERR_STATUS_ADDR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR3_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR3_MASK)
61858#define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK (0x1U)
61859#define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT (0U)
61864#define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK)
61865
61866#define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK (0x2U)
61867#define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT (1U)
61872#define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK)
61873
61874#define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK (0x4U)
61875#define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT (2U)
61880#define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK)
61881
61882#define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK (0x8U)
61883#define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT (3U)
61888#define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK)
61889
61890#define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK (0x10U)
61891#define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT (4U)
61896#define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK)
61897
61898#define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK (0x20U)
61899#define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT (5U)
61904#define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK)
61905
61906#define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK (0x40U)
61907#define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT (6U)
61912#define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK)
61913
61914#define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK (0x80U)
61915#define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT (7U)
61920#define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK)
61921
61922#define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK (0x100U)
61923#define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT (8U)
61928#define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK)
61929
61930#define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK (0x200U)
61931#define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT (9U)
61936#define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK)
61937
61938#define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK (0x400U)
61939#define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT (10U)
61944#define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK)
61945
61946#define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK (0x800U)
61947#define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT (11U)
61952#define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK)
61953
61954#define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK (0x1000U)
61955#define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT (12U)
61960#define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK)
61961
61962#define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK (0x2000U)
61963#define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT (13U)
61968#define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK)
61969
61970#define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK (0x4000U)
61971#define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT (14U)
61976#define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK)
61977
61978#define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK (0x8000U)
61979#define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT (15U)
61984#define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK)
61990#define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK (0x1U)
61991#define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT (0U)
61996#define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK)
61997
61998#define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK (0x2U)
61999#define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT (1U)
62004#define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK)
62005
62006#define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK (0x4U)
62007#define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT (2U)
62012#define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK)
62013
62014#define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK (0x8U)
62015#define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT (3U)
62020#define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK)
62021
62022#define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK (0x10U)
62023#define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT (4U)
62028#define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK)
62029
62030#define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK (0x20U)
62031#define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT (5U)
62036#define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK)
62037
62038#define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK (0x40U)
62039#define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT (6U)
62044#define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK)
62045
62046#define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK (0x80U)
62047#define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT (7U)
62052#define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK)
62053
62054#define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK (0x100U)
62055#define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT (8U)
62060#define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK)
62061
62062#define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK (0x200U)
62063#define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT (9U)
62068#define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK)
62069
62070#define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK (0x400U)
62071#define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT (10U)
62076#define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK)
62077
62078#define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK (0x800U)
62079#define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT (11U)
62084#define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK)
62085
62086#define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK (0x1000U)
62087#define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT (12U)
62092#define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK)
62093
62094#define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK (0x2000U)
62095#define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT (13U)
62100#define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK)
62101
62102#define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK (0x4000U)
62103#define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT (14U)
62108#define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK)
62109
62110#define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK (0x8000U)
62111#define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT (15U)
62116#define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK)
62122#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
62123#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT (0U)
62126#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK)
62132#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
62133#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT (0U)
62136#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK)
62142#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK (0xFFU)
62143#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT (0U)
62146#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK)
62152#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
62153#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT (0U)
62156#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK)
62162#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
62163#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT (0U)
62166#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK)
62172#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK (0xFFU)
62173#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT (0U)
62176#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK)
62182#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
62183#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT (0U)
62186#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK)
62192#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
62193#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT (0U)
62196#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK)
62202#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK (0xFFU)
62203#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT (0U)
62206#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK)
62212#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
62213#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT (0U)
62216#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK)
62222#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
62223#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT (0U)
62226#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK)
62232#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK (0xFFU)
62233#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT (0U)
62236#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK)
62242#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK (0xFFU)
62243#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT (0U)
62246#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK)
62247
62248#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
62249#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT (8U)
62252#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK)
62258#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
62259#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT (0U)
62262#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK)
62268#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
62269#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT (0U)
62272#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK)
62278#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
62279#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT (0U)
62282#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK)
62288#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
62289#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT (0U)
62292#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK)
62298#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK (0xFFU)
62299#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT (0U)
62302#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK)
62303
62304#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
62305#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT (8U)
62308#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK)
62314#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
62315#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT (0U)
62318#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK)
62324#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
62325#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT (0U)
62328#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK)
62334#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
62335#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT (0U)
62338#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK)
62344#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
62345#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT (0U)
62348#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK)
62354#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK (0xFFU)
62355#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT (0U)
62358#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK)
62359
62360#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
62361#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT (8U)
62364#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK)
62370#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
62371#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT (0U)
62374#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK)
62380#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
62381#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT (0U)
62384#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK)
62390#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
62391#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT (0U)
62394#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK)
62400#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
62401#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT (0U)
62404#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK)
62410#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK (0xFFU)
62411#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT (0U)
62414#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK)
62415
62416#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
62417#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT (8U)
62420#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK)
62426#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
62427#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT (0U)
62430#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK)
62436#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
62437#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT (0U)
62440#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK)
62446#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
62447#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT (0U)
62450#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK)
62456#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
62457#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT (0U)
62460#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK)
62466#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK (0xFFU)
62467#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT (0U)
62470#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK)
62471
62472#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
62473#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT (8U)
62476#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK)
62482#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
62483#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT (0U)
62486#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK)
62492#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
62493#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT (0U)
62496#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK)
62502#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK (0xFFU)
62503#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT (0U)
62506#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK)
62507
62508#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
62509#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT (8U)
62512#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK)
62518#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
62519#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT (0U)
62522#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK)
62528#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
62529#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT (0U)
62532#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK)
62538#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK (0xFFU)
62539#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT (0U)
62542#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK)
62543
62544#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
62545#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT (8U)
62548#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK)
62554#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
62555#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT (0U)
62558#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK)
62564#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
62565#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT (0U)
62568#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK)
62574#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK (0xFFU)
62575#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT (0U)
62578#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK)
62579
62580#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
62581#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT (8U)
62584#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK)
62590#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
62591#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT (0U)
62594#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK)
62600#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
62601#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT (0U)
62604#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK)
62610#define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK (0x1U)
62611#define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT (0U)
62616#define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK)
62617
62618#define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK (0x2U)
62619#define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT (1U)
62624#define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK)
62625
62626#define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK (0x4U)
62627#define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT (2U)
62632#define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK)
62633
62634#define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK (0x8U)
62635#define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT (3U)
62640#define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK)
62641
62642#define MECC_PIPE_ECC_EN_ECC_EN_MASK (0x10U)
62643#define MECC_PIPE_ECC_EN_ECC_EN_SHIFT (4U)
62648#define MECC_PIPE_ECC_EN_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_ECC_EN_SHIFT)) & MECC_PIPE_ECC_EN_ECC_EN_MASK)
62654#define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK (0x1U)
62655#define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT (0U)
62660#define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK)
62661
62662#define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK (0x2U)
62663#define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT (1U)
62668#define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK)
62669
62670#define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK (0x4U)
62671#define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT (2U)
62676#define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK)
62677
62678#define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK (0x8U)
62679#define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT (3U)
62684#define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK) /* end of group MECC_Register_Masks */
62691
62692
62693/* MECC - Peripheral instance base addresses */
62695#define MECC1_BASE (0x40014000u)
62697#define MECC1 ((MECC_Type *)MECC1_BASE)
62699#define MECC2_BASE (0x40018000u)
62701#define MECC2 ((MECC_Type *)MECC2_BASE)
62703#define MECC_BASE_ADDRS { 0u, MECC1_BASE, MECC2_BASE }
62705#define MECC_BASE_PTRS { (MECC_Type *)0u, MECC1, MECC2 }
62706 /* end of group MECC_Peripheral_Access_Layer */
62710
62711
62712/* ----------------------------------------------------------------------------
62713 -- MIPI_CSI2RX Peripheral Access Layer
62714 ---------------------------------------------------------------------------- */
62715
62722typedef struct {
62723 uint8_t RESERVED_0[256];
62724 __IO uint32_t CFG_NUM_LANES;
62725 __IO uint32_t CFG_DISABLE_DATA_LANES;
62726 __I uint32_t BIT_ERR;
62727 __I uint32_t IRQ_STATUS;
62728 __IO uint32_t IRQ_MASK;
62729 __I uint32_t ULPS_STATUS;
62730 __I uint32_t PPI_ERRSOT_HS;
62731 __I uint32_t PPI_ERRSOTSYNC_HS;
62732 __I uint32_t PPI_ERRESC;
62733 __I uint32_t PPI_ERRSYNCESC;
62734 __I uint32_t PPI_ERRCONTROL;
62735 __IO uint32_t CFG_DISABLE_PAYLOAD_0;
62736 __IO uint32_t CFG_DISABLE_PAYLOAD_1;
62737 uint8_t RESERVED_1[76];
62738 __IO uint32_t CFG_IGNORE_VC;
62739 __IO uint32_t CFG_VID_VC;
62740 __IO uint32_t CFG_VID_P_FIFO_SEND_LEVEL;
62741 __IO uint32_t CFG_VID_VSYNC;
62742 __IO uint32_t CFG_VID_HSYNC_FP;
62743 __IO uint32_t CFG_VID_HSYNC;
62744 __IO uint32_t CFG_VID_HSYNC_BP;
62746
62747/* ----------------------------------------------------------------------------
62748 -- MIPI_CSI2RX Register Masks
62749 ---------------------------------------------------------------------------- */
62750
62759#define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK (0x3U)
62760#define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT (0U)
62766#define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT)) & MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK)
62772#define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK (0xFU)
62773#define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT (0U)
62776#define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK)
62782#define MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK (0x3FFU)
62783#define MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT (0U)
62786#define MIPI_CSI2RX_BIT_ERR_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT)) & MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK)
62792#define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK (0x1FFU)
62793#define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT (0U)
62796#define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT)) & MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK)
62802#define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK (0x1FFU)
62803#define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT (0U)
62806#define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT)) & MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK)
62812#define MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK (0x3FFU)
62813#define MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT (0U)
62816#define MIPI_CSI2RX_ULPS_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT)) & MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK)
62822#define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK (0xFU)
62823#define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT (0U)
62826#define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK)
62832#define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK (0xFU)
62833#define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT (0U)
62836#define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK)
62842#define MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK (0xFU)
62843#define MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT (0U)
62846#define MIPI_CSI2RX_PPI_ERRESC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK)
62852#define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK (0xFU)
62853#define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT (0U)
62856#define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK)
62862#define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK (0xFU)
62863#define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT (0U)
62866#define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK)
62872#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK (0x1U)
62873#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT (0U)
62876#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK)
62877
62878#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK (0x2U)
62879#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT (1U)
62882#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK)
62883
62884#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK (0x4U)
62885#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT (2U)
62888#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK)
62889
62890#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK (0x400U)
62891#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT (10U)
62894#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK)
62895
62896#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK (0x4000U)
62897#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT (14U)
62900#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK)
62901
62902#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK (0x10000U)
62903#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT (16U)
62906#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK)
62907
62908#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK (0x20000U)
62909#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT (17U)
62912#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK)
62913
62914#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK (0x40000U)
62915#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT (18U)
62918#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK)
62919
62920#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK (0x80000U)
62921#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT (19U)
62924#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK)
62925
62926#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK (0x100000U)
62927#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT (20U)
62930#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK)
62936#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK (0x1U)
62937#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT (0U)
62940#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK)
62941
62942#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK (0x2U)
62943#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT (1U)
62946#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK)
62947
62948#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK (0x4U)
62949#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT (2U)
62952#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK)
62953
62954#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK (0x8U)
62955#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT (3U)
62958#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK)
62959
62960#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK (0x10U)
62961#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT (4U)
62964#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK)
62965
62966#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK (0x20U)
62967#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT (5U)
62970#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK)
62971
62972#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK (0x40U)
62973#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT (6U)
62976#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK)
62977
62978#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK (0x80U)
62979#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT (7U)
62982#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK)
62983
62984#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK (0x10000U)
62985#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT (16U)
62988#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK)
62994#define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK (0x1U)
62995#define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT (0U)
62996#define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT)) & MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK)
63002#define MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK (0x3U)
63003#define MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT (0U)
63004#define MIPI_CSI2RX_CFG_VID_VC_VID_VC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT)) & MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK)
63010#define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK (0xFFFFU)
63011#define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT (0U)
63014#define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT)) & MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK)
63020#define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK (0xFFU)
63021#define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT (0U)
63024#define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK)
63030#define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK (0xFFU)
63031#define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT (0U)
63034#define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK)
63040#define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK (0xFFU)
63041#define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT (0U)
63044#define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK)
63050#define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK (0xFFU)
63051#define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT (0U)
63054#define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK) /* end of group MIPI_CSI2RX_Register_Masks */
63061
63062
63063/* MIPI_CSI2RX - Peripheral instance base addresses */
63065#define MIPI_CSI2RX_BASE (0x40810000u)
63067#define MIPI_CSI2RX ((MIPI_CSI2RX_Type *)MIPI_CSI2RX_BASE)
63069#define MIPI_CSI2RX_BASE_ADDRS { MIPI_CSI2RX_BASE }
63071#define MIPI_CSI2RX_BASE_PTRS { MIPI_CSI2RX }
63072 /* end of group MIPI_CSI2RX_Peripheral_Access_Layer */
63076
63077
63078/* ----------------------------------------------------------------------------
63079 -- MU Peripheral Access Layer
63080 ---------------------------------------------------------------------------- */
63081
63088typedef struct {
63089 __IO uint32_t TR[4];
63090 __I uint32_t RR[4];
63091 __IO uint32_t SR;
63092 __IO uint32_t CR;
63093} MU_Type;
63094
63095/* ----------------------------------------------------------------------------
63096 -- MU Register Masks
63097 ---------------------------------------------------------------------------- */
63098
63107#define MU_TR_DATA_MASK (0xFFFFFFFFU)
63108#define MU_TR_DATA_SHIFT (0U)
63111#define MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)
63114/* The count of MU_TR */
63115#define MU_TR_COUNT (4U)
63116
63120#define MU_RR_DATA_MASK (0xFFFFFFFFU)
63121#define MU_RR_DATA_SHIFT (0U)
63124#define MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)
63127/* The count of MU_RR */
63128#define MU_RR_COUNT (4U)
63129
63133#define MU_SR_Fn_MASK (0x7U)
63134#define MU_SR_Fn_SHIFT (0U)
63139#define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
63140
63141#define MU_SR_EP_MASK (0x10U)
63142#define MU_SR_EP_SHIFT (4U)
63147#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
63148
63149#define MU_SR_RS_MASK (0x80U)
63150#define MU_SR_RS_SHIFT (7U)
63155#define MU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK)
63156
63157#define MU_SR_FUP_MASK (0x100U)
63158#define MU_SR_FUP_SHIFT (8U)
63163#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
63164
63165#define MU_SR_TEn_MASK (0xF00000U)
63166#define MU_SR_TEn_SHIFT (20U)
63171#define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
63172
63173#define MU_SR_RFn_MASK (0xF000000U)
63174#define MU_SR_RFn_SHIFT (24U)
63179#define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
63180
63181#define MU_SR_GIPn_MASK (0xF0000000U)
63182#define MU_SR_GIPn_SHIFT (28U)
63187#define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
63193#define MU_CR_Fn_MASK (0x7U)
63194#define MU_CR_Fn_SHIFT (0U)
63199#define MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)
63200
63201#define MU_CR_MUR_MASK (0x20U)
63202#define MU_CR_MUR_SHIFT (5U)
63207#define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
63208
63209#define MU_CR_GIRn_MASK (0xF0000U)
63210#define MU_CR_GIRn_SHIFT (16U)
63215#define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
63216
63217#define MU_CR_TIEn_MASK (0xF00000U)
63218#define MU_CR_TIEn_SHIFT (20U)
63223#define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
63224
63225#define MU_CR_RIEn_MASK (0xF000000U)
63226#define MU_CR_RIEn_SHIFT (24U)
63231#define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
63232
63233#define MU_CR_GIEn_MASK (0xF0000000U)
63234#define MU_CR_GIEn_SHIFT (28U)
63239#define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK) /* end of group MU_Register_Masks */
63246
63247
63248/* MU - Peripheral instance base addresses */
63250#define MUA_BASE (0x40C48000u)
63252#define MUA ((MU_Type *)MUA_BASE)
63254#define MU_BASE_ADDRS { MUA_BASE }
63256#define MU_BASE_PTRS { MUA }
63258#define MU_IRQS { MUA_IRQn }
63259 /* end of group MU_Peripheral_Access_Layer */
63263
63264
63265/* ----------------------------------------------------------------------------
63266 -- OCOTP Peripheral Access Layer
63267 ---------------------------------------------------------------------------- */
63268
63275typedef struct {
63276 __IO uint32_t CTRL;
63277 __IO uint32_t CTRL_SET;
63278 __IO uint32_t CTRL_CLR;
63279 __IO uint32_t CTRL_TOG;
63280 __IO uint32_t PDN;
63281 uint8_t RESERVED_0[12];
63282 __IO uint32_t DATA;
63283 uint8_t RESERVED_1[12];
63284 __IO uint32_t READ_CTRL;
63285 uint8_t RESERVED_2[92];
63286 __IO uint32_t OUT_STATUS;
63287 __IO uint32_t OUT_STATUS_SET;
63288 __IO uint32_t OUT_STATUS_CLR;
63289 __IO uint32_t OUT_STATUS_TOG;
63290 uint8_t RESERVED_3[16];
63291 __I uint32_t VERSION;
63292 uint8_t RESERVED_4[76];
63293 struct { /* offset: 0x100, array step: 0x10 */
63295 uint8_t RESERVED_0[12];
63296 } READ_FUSE_DATAS[4];
63297 __IO uint32_t SW_LOCK;
63298 uint8_t RESERVED_5[12];
63299 __IO uint32_t BIT_LOCK;
63300 uint8_t RESERVED_6[1196];
63301 __I uint32_t LOCKED0;
63302 uint8_t RESERVED_7[12];
63303 __I uint32_t LOCKED1;
63304 uint8_t RESERVED_8[12];
63305 __I uint32_t LOCKED2;
63306 uint8_t RESERVED_9[12];
63307 __I uint32_t LOCKED3;
63308 uint8_t RESERVED_10[12];
63309 __I uint32_t LOCKED4;
63310 uint8_t RESERVED_11[444];
63311 struct { /* offset: 0x800, array step: 0x10 */
63312 __I uint32_t FUSE;
63313 uint8_t RESERVED_0[12];
63314 } FUSEN[144];
63315} OCOTP_Type;
63316
63317/* ----------------------------------------------------------------------------
63318 -- OCOTP Register Masks
63319 ---------------------------------------------------------------------------- */
63320
63329#define OCOTP_CTRL_ADDR_MASK (0x3FFU)
63330#define OCOTP_CTRL_ADDR_SHIFT (0U)
63335#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
63336
63337#define OCOTP_CTRL_BUSY_MASK (0x400U)
63338#define OCOTP_CTRL_BUSY_SHIFT (10U)
63343#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
63344
63345#define OCOTP_CTRL_ERROR_MASK (0x800U)
63346#define OCOTP_CTRL_ERROR_SHIFT (11U)
63351#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
63352
63353#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x1000U)
63354#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (12U)
63359#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
63360
63361#define OCOTP_CTRL_WORDLOCK_MASK (0x8000U)
63362#define OCOTP_CTRL_WORDLOCK_SHIFT (15U)
63367#define OCOTP_CTRL_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WORDLOCK_SHIFT)) & OCOTP_CTRL_WORDLOCK_MASK)
63368
63369#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
63370#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
63375#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
63381#define OCOTP_CTRL_SET_ADDR_MASK (0x3FFU)
63382#define OCOTP_CTRL_SET_ADDR_SHIFT (0U)
63385#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
63386
63387#define OCOTP_CTRL_SET_BUSY_MASK (0x400U)
63388#define OCOTP_CTRL_SET_BUSY_SHIFT (10U)
63391#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
63392
63393#define OCOTP_CTRL_SET_ERROR_MASK (0x800U)
63394#define OCOTP_CTRL_SET_ERROR_SHIFT (11U)
63397#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
63398
63399#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x1000U)
63400#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (12U)
63403#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
63404
63405#define OCOTP_CTRL_SET_WORDLOCK_MASK (0x8000U)
63406#define OCOTP_CTRL_SET_WORDLOCK_SHIFT (15U)
63409#define OCOTP_CTRL_SET_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WORDLOCK_SHIFT)) & OCOTP_CTRL_SET_WORDLOCK_MASK)
63410
63411#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
63412#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
63415#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
63421#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FFU)
63422#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
63425#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
63426
63427#define OCOTP_CTRL_CLR_BUSY_MASK (0x400U)
63428#define OCOTP_CTRL_CLR_BUSY_SHIFT (10U)
63431#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
63432
63433#define OCOTP_CTRL_CLR_ERROR_MASK (0x800U)
63434#define OCOTP_CTRL_CLR_ERROR_SHIFT (11U)
63437#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
63438
63439#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x1000U)
63440#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (12U)
63443#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
63444
63445#define OCOTP_CTRL_CLR_WORDLOCK_MASK (0x8000U)
63446#define OCOTP_CTRL_CLR_WORDLOCK_SHIFT (15U)
63449#define OCOTP_CTRL_CLR_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WORDLOCK_SHIFT)) & OCOTP_CTRL_CLR_WORDLOCK_MASK)
63450
63451#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
63452#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
63455#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
63461#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FFU)
63462#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
63465#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
63466
63467#define OCOTP_CTRL_TOG_BUSY_MASK (0x400U)
63468#define OCOTP_CTRL_TOG_BUSY_SHIFT (10U)
63471#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
63472
63473#define OCOTP_CTRL_TOG_ERROR_MASK (0x800U)
63474#define OCOTP_CTRL_TOG_ERROR_SHIFT (11U)
63477#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
63478
63479#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x1000U)
63480#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (12U)
63483#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
63484
63485#define OCOTP_CTRL_TOG_WORDLOCK_MASK (0x8000U)
63486#define OCOTP_CTRL_TOG_WORDLOCK_SHIFT (15U)
63489#define OCOTP_CTRL_TOG_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WORDLOCK_SHIFT)) & OCOTP_CTRL_TOG_WORDLOCK_MASK)
63490
63491#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
63492#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
63495#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
63501#define OCOTP_PDN_PDN_MASK (0x1U)
63502#define OCOTP_PDN_PDN_SHIFT (0U)
63507#define OCOTP_PDN_PDN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_PDN_PDN_SHIFT)) & OCOTP_PDN_PDN_MASK)
63513#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
63514#define OCOTP_DATA_DATA_SHIFT (0U)
63517#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
63523#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
63524#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
63529#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
63530
63531#define OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK (0x6U)
63532#define OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT (1U)
63539#define OCOTP_READ_CTRL_READ_FUSE_CNTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK)
63540
63541#define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK (0x8U)
63542#define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT (3U)
63547#define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK)
63548
63549#define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK (0x10U)
63550#define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT (4U)
63555#define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK)
63561#define OCOTP_OUT_STATUS_SEC_MASK (0x200U)
63562#define OCOTP_OUT_STATUS_SEC_SHIFT (9U)
63565#define OCOTP_OUT_STATUS_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_SHIFT)) & OCOTP_OUT_STATUS_SEC_MASK)
63566
63567#define OCOTP_OUT_STATUS_DED_MASK (0x400U)
63568#define OCOTP_OUT_STATUS_DED_SHIFT (10U)
63571#define OCOTP_OUT_STATUS_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_SHIFT)) & OCOTP_OUT_STATUS_DED_MASK)
63572
63573#define OCOTP_OUT_STATUS_LOCKED_MASK (0x800U)
63574#define OCOTP_OUT_STATUS_LOCKED_SHIFT (11U)
63577#define OCOTP_OUT_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_LOCKED_MASK)
63578
63579#define OCOTP_OUT_STATUS_PROGFAIL_MASK (0x1000U)
63580#define OCOTP_OUT_STATUS_PROGFAIL_SHIFT (12U)
63583#define OCOTP_OUT_STATUS_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_PROGFAIL_MASK)
63584
63585#define OCOTP_OUT_STATUS_ACK_MASK (0x2000U)
63586#define OCOTP_OUT_STATUS_ACK_SHIFT (13U)
63589#define OCOTP_OUT_STATUS_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_ACK_SHIFT)) & OCOTP_OUT_STATUS_ACK_MASK)
63590
63591#define OCOTP_OUT_STATUS_PWOK_MASK (0x4000U)
63592#define OCOTP_OUT_STATUS_PWOK_SHIFT (14U)
63595#define OCOTP_OUT_STATUS_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PWOK_SHIFT)) & OCOTP_OUT_STATUS_PWOK_MASK)
63596
63597#define OCOTP_OUT_STATUS_FLAGSTATE_MASK (0x78000U)
63598#define OCOTP_OUT_STATUS_FLAGSTATE_SHIFT (15U)
63601#define OCOTP_OUT_STATUS_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_FLAGSTATE_MASK)
63602
63603#define OCOTP_OUT_STATUS_SEC_RELOAD_MASK (0x80000U)
63604#define OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT (19U)
63607#define OCOTP_OUT_STATUS_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SEC_RELOAD_MASK)
63608
63609#define OCOTP_OUT_STATUS_DED_RELOAD_MASK (0x100000U)
63610#define OCOTP_OUT_STATUS_DED_RELOAD_SHIFT (20U)
63613#define OCOTP_OUT_STATUS_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_DED_RELOAD_MASK)
63614
63615#define OCOTP_OUT_STATUS_CALIBRATED_MASK (0x200000U)
63616#define OCOTP_OUT_STATUS_CALIBRATED_SHIFT (21U)
63619#define OCOTP_OUT_STATUS_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CALIBRATED_MASK)
63620
63621#define OCOTP_OUT_STATUS_READ_DONE_INTR_MASK (0x400000U)
63622#define OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT (22U)
63625#define OCOTP_OUT_STATUS_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_DONE_INTR_MASK)
63626
63627#define OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK (0x800000U)
63628#define OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT (23U)
63633#define OCOTP_OUT_STATUS_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK)
63634
63635#define OCOTP_OUT_STATUS_DED0_MASK (0x1000000U)
63636#define OCOTP_OUT_STATUS_DED0_SHIFT (24U)
63639#define OCOTP_OUT_STATUS_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED0_SHIFT)) & OCOTP_OUT_STATUS_DED0_MASK)
63640
63641#define OCOTP_OUT_STATUS_DED1_MASK (0x2000000U)
63642#define OCOTP_OUT_STATUS_DED1_SHIFT (25U)
63645#define OCOTP_OUT_STATUS_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED1_SHIFT)) & OCOTP_OUT_STATUS_DED1_MASK)
63646
63647#define OCOTP_OUT_STATUS_DED2_MASK (0x4000000U)
63648#define OCOTP_OUT_STATUS_DED2_SHIFT (26U)
63651#define OCOTP_OUT_STATUS_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED2_SHIFT)) & OCOTP_OUT_STATUS_DED2_MASK)
63652
63653#define OCOTP_OUT_STATUS_DED3_MASK (0x8000000U)
63654#define OCOTP_OUT_STATUS_DED3_SHIFT (27U)
63657#define OCOTP_OUT_STATUS_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED3_SHIFT)) & OCOTP_OUT_STATUS_DED3_MASK)
63663#define OCOTP_OUT_STATUS_SET_SEC_MASK (0x200U)
63664#define OCOTP_OUT_STATUS_SET_SEC_SHIFT (9U)
63667#define OCOTP_OUT_STATUS_SET_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_MASK)
63668
63669#define OCOTP_OUT_STATUS_SET_DED_MASK (0x400U)
63670#define OCOTP_OUT_STATUS_SET_DED_SHIFT (10U)
63673#define OCOTP_OUT_STATUS_SET_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_MASK)
63674
63675#define OCOTP_OUT_STATUS_SET_LOCKED_MASK (0x800U)
63676#define OCOTP_OUT_STATUS_SET_LOCKED_SHIFT (11U)
63679#define OCOTP_OUT_STATUS_SET_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_SET_LOCKED_MASK)
63680
63681#define OCOTP_OUT_STATUS_SET_PROGFAIL_MASK (0x1000U)
63682#define OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT (12U)
63685#define OCOTP_OUT_STATUS_SET_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_SET_PROGFAIL_MASK)
63686
63687#define OCOTP_OUT_STATUS_SET_ACK_MASK (0x2000U)
63688#define OCOTP_OUT_STATUS_SET_ACK_SHIFT (13U)
63691#define OCOTP_OUT_STATUS_SET_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_ACK_SHIFT)) & OCOTP_OUT_STATUS_SET_ACK_MASK)
63692
63693#define OCOTP_OUT_STATUS_SET_PWOK_MASK (0x4000U)
63694#define OCOTP_OUT_STATUS_SET_PWOK_SHIFT (14U)
63697#define OCOTP_OUT_STATUS_SET_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PWOK_SHIFT)) & OCOTP_OUT_STATUS_SET_PWOK_MASK)
63698
63699#define OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK (0x78000U)
63700#define OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT (15U)
63703#define OCOTP_OUT_STATUS_SET_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK)
63704
63705#define OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK (0x80000U)
63706#define OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT (19U)
63709#define OCOTP_OUT_STATUS_SET_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK)
63710
63711#define OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK (0x100000U)
63712#define OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT (20U)
63715#define OCOTP_OUT_STATUS_SET_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK)
63716
63717#define OCOTP_OUT_STATUS_SET_CALIBRATED_MASK (0x200000U)
63718#define OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT (21U)
63721#define OCOTP_OUT_STATUS_SET_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_SET_CALIBRATED_MASK)
63722
63723#define OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK (0x400000U)
63724#define OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT (22U)
63727#define OCOTP_OUT_STATUS_SET_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK)
63728
63729#define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK (0x800000U)
63730#define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT (23U)
63733#define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK)
63734
63735#define OCOTP_OUT_STATUS_SET_DED0_MASK (0x1000000U)
63736#define OCOTP_OUT_STATUS_SET_DED0_SHIFT (24U)
63739#define OCOTP_OUT_STATUS_SET_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED0_SHIFT)) & OCOTP_OUT_STATUS_SET_DED0_MASK)
63740
63741#define OCOTP_OUT_STATUS_SET_DED1_MASK (0x2000000U)
63742#define OCOTP_OUT_STATUS_SET_DED1_SHIFT (25U)
63745#define OCOTP_OUT_STATUS_SET_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED1_SHIFT)) & OCOTP_OUT_STATUS_SET_DED1_MASK)
63746
63747#define OCOTP_OUT_STATUS_SET_DED2_MASK (0x4000000U)
63748#define OCOTP_OUT_STATUS_SET_DED2_SHIFT (26U)
63751#define OCOTP_OUT_STATUS_SET_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED2_SHIFT)) & OCOTP_OUT_STATUS_SET_DED2_MASK)
63752
63753#define OCOTP_OUT_STATUS_SET_DED3_MASK (0x8000000U)
63754#define OCOTP_OUT_STATUS_SET_DED3_SHIFT (27U)
63757#define OCOTP_OUT_STATUS_SET_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED3_SHIFT)) & OCOTP_OUT_STATUS_SET_DED3_MASK)
63763#define OCOTP_OUT_STATUS_CLR_SEC_MASK (0x200U)
63764#define OCOTP_OUT_STATUS_CLR_SEC_SHIFT (9U)
63767#define OCOTP_OUT_STATUS_CLR_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_MASK)
63768
63769#define OCOTP_OUT_STATUS_CLR_DED_MASK (0x400U)
63770#define OCOTP_OUT_STATUS_CLR_DED_SHIFT (10U)
63773#define OCOTP_OUT_STATUS_CLR_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_MASK)
63774
63775#define OCOTP_OUT_STATUS_CLR_LOCKED_MASK (0x800U)
63776#define OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT (11U)
63779#define OCOTP_OUT_STATUS_CLR_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_CLR_LOCKED_MASK)
63780
63781#define OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK (0x1000U)
63782#define OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT (12U)
63785#define OCOTP_OUT_STATUS_CLR_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK)
63786
63787#define OCOTP_OUT_STATUS_CLR_ACK_MASK (0x2000U)
63788#define OCOTP_OUT_STATUS_CLR_ACK_SHIFT (13U)
63791#define OCOTP_OUT_STATUS_CLR_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_ACK_SHIFT)) & OCOTP_OUT_STATUS_CLR_ACK_MASK)
63792
63793#define OCOTP_OUT_STATUS_CLR_PWOK_MASK (0x4000U)
63794#define OCOTP_OUT_STATUS_CLR_PWOK_SHIFT (14U)
63797#define OCOTP_OUT_STATUS_CLR_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PWOK_SHIFT)) & OCOTP_OUT_STATUS_CLR_PWOK_MASK)
63798
63799#define OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK (0x78000U)
63800#define OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT (15U)
63803#define OCOTP_OUT_STATUS_CLR_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK)
63804
63805#define OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK (0x80000U)
63806#define OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT (19U)
63809#define OCOTP_OUT_STATUS_CLR_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK)
63810
63811#define OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK (0x100000U)
63812#define OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT (20U)
63815#define OCOTP_OUT_STATUS_CLR_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK)
63816
63817#define OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK (0x200000U)
63818#define OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT (21U)
63821#define OCOTP_OUT_STATUS_CLR_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK)
63822
63823#define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK (0x400000U)
63824#define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT (22U)
63827#define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK)
63828
63829#define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK (0x800000U)
63830#define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT (23U)
63833#define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK)
63834
63835#define OCOTP_OUT_STATUS_CLR_DED0_MASK (0x1000000U)
63836#define OCOTP_OUT_STATUS_CLR_DED0_SHIFT (24U)
63839#define OCOTP_OUT_STATUS_CLR_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED0_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED0_MASK)
63840
63841#define OCOTP_OUT_STATUS_CLR_DED1_MASK (0x2000000U)
63842#define OCOTP_OUT_STATUS_CLR_DED1_SHIFT (25U)
63845#define OCOTP_OUT_STATUS_CLR_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED1_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED1_MASK)
63846
63847#define OCOTP_OUT_STATUS_CLR_DED2_MASK (0x4000000U)
63848#define OCOTP_OUT_STATUS_CLR_DED2_SHIFT (26U)
63851#define OCOTP_OUT_STATUS_CLR_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED2_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED2_MASK)
63852
63853#define OCOTP_OUT_STATUS_CLR_DED3_MASK (0x8000000U)
63854#define OCOTP_OUT_STATUS_CLR_DED3_SHIFT (27U)
63857#define OCOTP_OUT_STATUS_CLR_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED3_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED3_MASK)
63863#define OCOTP_OUT_STATUS_TOG_SEC_MASK (0x200U)
63864#define OCOTP_OUT_STATUS_TOG_SEC_SHIFT (9U)
63867#define OCOTP_OUT_STATUS_TOG_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_MASK)
63868
63869#define OCOTP_OUT_STATUS_TOG_DED_MASK (0x400U)
63870#define OCOTP_OUT_STATUS_TOG_DED_SHIFT (10U)
63873#define OCOTP_OUT_STATUS_TOG_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_MASK)
63874
63875#define OCOTP_OUT_STATUS_TOG_LOCKED_MASK (0x800U)
63876#define OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT (11U)
63879#define OCOTP_OUT_STATUS_TOG_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_TOG_LOCKED_MASK)
63880
63881#define OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK (0x1000U)
63882#define OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT (12U)
63885#define OCOTP_OUT_STATUS_TOG_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK)
63886
63887#define OCOTP_OUT_STATUS_TOG_ACK_MASK (0x2000U)
63888#define OCOTP_OUT_STATUS_TOG_ACK_SHIFT (13U)
63891#define OCOTP_OUT_STATUS_TOG_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_ACK_SHIFT)) & OCOTP_OUT_STATUS_TOG_ACK_MASK)
63892
63893#define OCOTP_OUT_STATUS_TOG_PWOK_MASK (0x4000U)
63894#define OCOTP_OUT_STATUS_TOG_PWOK_SHIFT (14U)
63897#define OCOTP_OUT_STATUS_TOG_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PWOK_SHIFT)) & OCOTP_OUT_STATUS_TOG_PWOK_MASK)
63898
63899#define OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK (0x78000U)
63900#define OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT (15U)
63903#define OCOTP_OUT_STATUS_TOG_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK)
63904
63905#define OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK (0x80000U)
63906#define OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT (19U)
63909#define OCOTP_OUT_STATUS_TOG_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK)
63910
63911#define OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK (0x100000U)
63912#define OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT (20U)
63915#define OCOTP_OUT_STATUS_TOG_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK)
63916
63917#define OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK (0x200000U)
63918#define OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT (21U)
63921#define OCOTP_OUT_STATUS_TOG_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK)
63922
63923#define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK (0x400000U)
63924#define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT (22U)
63927#define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK)
63928
63929#define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK (0x800000U)
63930#define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT (23U)
63933#define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK)
63934
63935#define OCOTP_OUT_STATUS_TOG_DED0_MASK (0x1000000U)
63936#define OCOTP_OUT_STATUS_TOG_DED0_SHIFT (24U)
63939#define OCOTP_OUT_STATUS_TOG_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED0_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED0_MASK)
63940
63941#define OCOTP_OUT_STATUS_TOG_DED1_MASK (0x2000000U)
63942#define OCOTP_OUT_STATUS_TOG_DED1_SHIFT (25U)
63945#define OCOTP_OUT_STATUS_TOG_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED1_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED1_MASK)
63946
63947#define OCOTP_OUT_STATUS_TOG_DED2_MASK (0x4000000U)
63948#define OCOTP_OUT_STATUS_TOG_DED2_SHIFT (26U)
63951#define OCOTP_OUT_STATUS_TOG_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED2_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED2_MASK)
63952
63953#define OCOTP_OUT_STATUS_TOG_DED3_MASK (0x8000000U)
63954#define OCOTP_OUT_STATUS_TOG_DED3_SHIFT (27U)
63957#define OCOTP_OUT_STATUS_TOG_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED3_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED3_MASK)
63963#define OCOTP_VERSION_STEP_MASK (0xFFFFU)
63964#define OCOTP_VERSION_STEP_SHIFT (0U)
63967#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
63968
63969#define OCOTP_VERSION_MINOR_MASK (0xFF0000U)
63970#define OCOTP_VERSION_MINOR_SHIFT (16U)
63973#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
63974
63975#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
63976#define OCOTP_VERSION_MAJOR_SHIFT (24U)
63979#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
63985#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
63986#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
63989#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
63992/* The count of OCOTP_READ_FUSE_DATA */
63993#define OCOTP_READ_FUSE_DATA_COUNT (4U)
63994
63998#define OCOTP_SW_LOCK_SW_LOCK_MASK (0xFFFFFFFFU)
63999#define OCOTP_SW_LOCK_SW_LOCK_SHIFT (0U)
64000#define OCOTP_SW_LOCK_SW_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_LOCK_SW_LOCK_SHIFT)) & OCOTP_SW_LOCK_SW_LOCK_MASK)
64006#define OCOTP_BIT_LOCK_BIT_LOCK_MASK (0xFFFFFFFFU)
64007#define OCOTP_BIT_LOCK_BIT_LOCK_SHIFT (0U)
64008#define OCOTP_BIT_LOCK_BIT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BIT_LOCK_BIT_LOCK_SHIFT)) & OCOTP_BIT_LOCK_BIT_LOCK_MASK)
64014#define OCOTP_LOCKED0_LOCKED_MASK (0xFFFFU)
64015#define OCOTP_LOCKED0_LOCKED_SHIFT (0U)
64016#define OCOTP_LOCKED0_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED0_LOCKED_SHIFT)) & OCOTP_LOCKED0_LOCKED_MASK)
64022#define OCOTP_LOCKED1_LOCKED_MASK (0xFFFFFFFFU)
64023#define OCOTP_LOCKED1_LOCKED_SHIFT (0U)
64024#define OCOTP_LOCKED1_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED1_LOCKED_SHIFT)) & OCOTP_LOCKED1_LOCKED_MASK)
64030#define OCOTP_LOCKED2_LOCKED_MASK (0xFFFFFFFFU)
64031#define OCOTP_LOCKED2_LOCKED_SHIFT (0U)
64032#define OCOTP_LOCKED2_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED2_LOCKED_SHIFT)) & OCOTP_LOCKED2_LOCKED_MASK)
64038#define OCOTP_LOCKED3_LOCKED_MASK (0xFFFFFFFFU)
64039#define OCOTP_LOCKED3_LOCKED_SHIFT (0U)
64040#define OCOTP_LOCKED3_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED3_LOCKED_SHIFT)) & OCOTP_LOCKED3_LOCKED_MASK)
64046#define OCOTP_LOCKED4_LOCKED_MASK (0xFFFFFFFFU)
64047#define OCOTP_LOCKED4_LOCKED_SHIFT (0U)
64048#define OCOTP_LOCKED4_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED4_LOCKED_SHIFT)) & OCOTP_LOCKED4_LOCKED_MASK)
64054#define OCOTP_FUSE_BITS_MASK (0xFFFFFFFFU)
64055#define OCOTP_FUSE_BITS_SHIFT (0U)
64058#define OCOTP_FUSE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE_BITS_SHIFT)) & OCOTP_FUSE_BITS_MASK)
64061/* The count of OCOTP_FUSE */
64062#define OCOTP_FUSE_COUNT (144U)
64063
64064 /* end of group OCOTP_Register_Masks */
64068
64069
64070/* OCOTP - Peripheral instance base addresses */
64072#define OCOTP_BASE (0x40CAC000u)
64074#define OCOTP ((OCOTP_Type *)OCOTP_BASE)
64076#define OCOTP_BASE_ADDRS { OCOTP_BASE }
64078#define OCOTP_BASE_PTRS { OCOTP }
64079 /* end of group OCOTP_Peripheral_Access_Layer */
64083
64084
64085/* ----------------------------------------------------------------------------
64086 -- OSC_RC_400M Peripheral Access Layer
64087 ---------------------------------------------------------------------------- */
64088
64095typedef struct {
64096 struct { /* offset: 0x0 */
64097 __IO uint32_t RW;
64098 __IO uint32_t SET;
64099 __IO uint32_t CLR;
64100 __IO uint32_t TOG;
64101 } CTRL0;
64102 struct { /* offset: 0x10 */
64103 __IO uint32_t RW;
64104 __IO uint32_t SET;
64105 __IO uint32_t CLR;
64106 __IO uint32_t TOG;
64107 } CTRL1;
64108 struct { /* offset: 0x20 */
64109 __IO uint32_t RW;
64110 __IO uint32_t SET;
64111 __IO uint32_t CLR;
64112 __IO uint32_t TOG;
64113 } CTRL2;
64114 struct { /* offset: 0x30 */
64115 __IO uint32_t RW;
64116 __IO uint32_t SET;
64117 __IO uint32_t CLR;
64118 __IO uint32_t TOG;
64119 } CTRL3;
64120 uint8_t RESERVED_0[16];
64121 struct { /* offset: 0x50 */
64122 __I uint32_t RW;
64123 __I uint32_t SET;
64124 __I uint32_t CLR;
64125 __I uint32_t TOG;
64126 } STAT0;
64127 struct { /* offset: 0x60 */
64128 __I uint32_t RW;
64129 __I uint32_t SET;
64130 __I uint32_t CLR;
64131 __I uint32_t TOG;
64132 } STAT1;
64133 struct { /* offset: 0x70 */
64134 __I uint32_t RW;
64135 __I uint32_t SET;
64136 __I uint32_t CLR;
64137 __I uint32_t TOG;
64138 } STAT2;
64140
64141/* ----------------------------------------------------------------------------
64142 -- OSC_RC_400M Register Masks
64143 ---------------------------------------------------------------------------- */
64144
64153#define OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK (0x3F000000U)
64154#define OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT (24U)
64157#define OSC_RC_400M_CTRL0_REF_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT)) & OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK)
64163#define OSC_RC_400M_CTRL1_HYST_MINUS_MASK (0xFU)
64164#define OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT (0U)
64167#define OSC_RC_400M_CTRL1_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_MINUS_MASK)
64168
64169#define OSC_RC_400M_CTRL1_HYST_PLUS_MASK (0xF00U)
64170#define OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT (8U)
64173#define OSC_RC_400M_CTRL1_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_PLUS_MASK)
64174
64175#define OSC_RC_400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U)
64176#define OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT (16U)
64179#define OSC_RC_400M_CTRL1_TARGET_COUNT(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT)) & OSC_RC_400M_CTRL1_TARGET_COUNT_MASK)
64185#define OSC_RC_400M_CTRL2_TUNE_BYP_MASK (0x400U)
64186#define OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT (10U)
64191#define OSC_RC_400M_CTRL2_TUNE_BYP(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_BYP_MASK)
64192
64193#define OSC_RC_400M_CTRL2_TUNE_EN_MASK (0x1000U)
64194#define OSC_RC_400M_CTRL2_TUNE_EN_SHIFT (12U)
64199#define OSC_RC_400M_CTRL2_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_EN_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_EN_MASK)
64200
64201#define OSC_RC_400M_CTRL2_TUNE_START_MASK (0x4000U)
64202#define OSC_RC_400M_CTRL2_TUNE_START_SHIFT (14U)
64207#define OSC_RC_400M_CTRL2_TUNE_START(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_START_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_START_MASK)
64208
64209#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U)
64210#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U)
64213#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK)
64219#define OSC_RC_400M_CTRL3_CLR_ERR_MASK (0x1U)
64220#define OSC_RC_400M_CTRL3_CLR_ERR_SHIFT (0U)
64225#define OSC_RC_400M_CTRL3_CLR_ERR(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_CLR_ERR_SHIFT)) & OSC_RC_400M_CTRL3_CLR_ERR_MASK)
64226
64227#define OSC_RC_400M_CTRL3_EN_1M_CLK_MASK (0x100U)
64228#define OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT (8U)
64233#define OSC_RC_400M_CTRL3_EN_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_EN_1M_CLK_MASK)
64234
64235#define OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK (0x400U)
64236#define OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT (10U)
64241#define OSC_RC_400M_CTRL3_MUX_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK)
64242
64243#define OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK (0xFFFF0000U)
64244#define OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT (16U)
64247#define OSC_RC_400M_CTRL3_COUNT_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK)
64253#define OSC_RC_400M_STAT0_CLK1M_ERR_MASK (0x1U)
64254#define OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT (0U)
64259#define OSC_RC_400M_STAT0_CLK1M_ERR(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT)) & OSC_RC_400M_STAT0_CLK1M_ERR_MASK)
64265#define OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK (0xFFFF0000U)
64266#define OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT (16U)
64269#define OSC_RC_400M_STAT1_CURR_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT)) & OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK)
64275#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U)
64276#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U)
64279#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK) /* end of group OSC_RC_400M_Register_Masks */
64286
64287
64288/* OSC_RC_400M - Peripheral instance base addresses */
64290#define OSC_RC_400M_BASE (0u)
64292#define OSC_RC_400M ((OSC_RC_400M_Type *)OSC_RC_400M_BASE)
64294#define OSC_RC_400M_BASE_ADDRS { OSC_RC_400M_BASE }
64296#define OSC_RC_400M_BASE_PTRS { OSC_RC_400M }
64297 /* end of group OSC_RC_400M_Peripheral_Access_Layer */
64301
64302
64303/* ----------------------------------------------------------------------------
64304 -- OTFAD Peripheral Access Layer
64305 ---------------------------------------------------------------------------- */
64306
64313typedef struct {
64314 uint8_t RESERVED_0[3072];
64315 __IO uint32_t CR;
64316 __IO uint32_t SR;
64317 uint8_t RESERVED_1[248];
64318 struct { /* offset: 0xD00, array step: 0x40 */
64319 __IO uint32_t KEY[4];
64320 __IO uint32_t CTR[2];
64321 __IO uint32_t RGD_W0;
64322 __IO uint32_t RGD_W1;
64323 uint8_t RESERVED_0[32];
64324 } CTX[4];
64325} OTFAD_Type;
64326
64327/* ----------------------------------------------------------------------------
64328 -- OTFAD Register Masks
64329 ---------------------------------------------------------------------------- */
64330
64339#define OTFAD_CR_FERR_MASK (0x2U)
64340#define OTFAD_CR_FERR_SHIFT (1U)
64345#define OTFAD_CR_FERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)
64346
64347#define OTFAD_CR_FLDM_MASK (0x8U)
64348#define OTFAD_CR_FLDM_SHIFT (3U)
64353#define OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)
64354
64355#define OTFAD_CR_KBSE_MASK (0x10U)
64356#define OTFAD_CR_KBSE_SHIFT (4U)
64361#define OTFAD_CR_KBSE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)
64362
64363#define OTFAD_CR_KBPE_MASK (0x20U)
64364#define OTFAD_CR_KBPE_SHIFT (5U)
64369#define OTFAD_CR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)
64370
64371#define OTFAD_CR_RRAE_MASK (0x80U)
64372#define OTFAD_CR_RRAE_SHIFT (7U)
64377#define OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)
64378
64379#define OTFAD_CR_SKBP_MASK (0x40000000U)
64380#define OTFAD_CR_SKBP_SHIFT (30U)
64385#define OTFAD_CR_SKBP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)
64386
64387#define OTFAD_CR_GE_MASK (0x80000000U)
64388#define OTFAD_CR_GE_SHIFT (31U)
64393#define OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)
64399#define OTFAD_SR_KBERR_MASK (0x1U)
64400#define OTFAD_SR_KBERR_SHIFT (0U)
64405#define OTFAD_SR_KBERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK)
64406
64407#define OTFAD_SR_MDPCP_MASK (0x2U)
64408#define OTFAD_SR_MDPCP_SHIFT (1U)
64411#define OTFAD_SR_MDPCP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)
64412
64413#define OTFAD_SR_MODE_MASK (0xCU)
64414#define OTFAD_SR_MODE_SHIFT (2U)
64421#define OTFAD_SR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)
64422
64423#define OTFAD_SR_NCTX_MASK (0xF0U)
64424#define OTFAD_SR_NCTX_SHIFT (4U)
64427#define OTFAD_SR_NCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)
64428
64429#define OTFAD_SR_CTXER0_MASK (0x100U)
64430#define OTFAD_SR_CTXER0_SHIFT (8U)
64435#define OTFAD_SR_CTXER0(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK)
64436
64437#define OTFAD_SR_CTXER1_MASK (0x200U)
64438#define OTFAD_SR_CTXER1_SHIFT (9U)
64443#define OTFAD_SR_CTXER1(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK)
64444
64445#define OTFAD_SR_CTXER2_MASK (0x400U)
64446#define OTFAD_SR_CTXER2_SHIFT (10U)
64451#define OTFAD_SR_CTXER2(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK)
64452
64453#define OTFAD_SR_CTXER3_MASK (0x800U)
64454#define OTFAD_SR_CTXER3_SHIFT (11U)
64459#define OTFAD_SR_CTXER3(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK)
64460
64461#define OTFAD_SR_CTXIE0_MASK (0x10000U)
64462#define OTFAD_SR_CTXIE0_SHIFT (16U)
64467#define OTFAD_SR_CTXIE0(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK)
64468
64469#define OTFAD_SR_CTXIE1_MASK (0x20000U)
64470#define OTFAD_SR_CTXIE1_SHIFT (17U)
64475#define OTFAD_SR_CTXIE1(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK)
64476
64477#define OTFAD_SR_CTXIE2_MASK (0x40000U)
64478#define OTFAD_SR_CTXIE2_SHIFT (18U)
64483#define OTFAD_SR_CTXIE2(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK)
64484
64485#define OTFAD_SR_CTXIE3_MASK (0x80000U)
64486#define OTFAD_SR_CTXIE3_SHIFT (19U)
64491#define OTFAD_SR_CTXIE3(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK)
64492
64493#define OTFAD_SR_HRL_MASK (0xF000000U)
64494#define OTFAD_SR_HRL_SHIFT (24U)
64497#define OTFAD_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)
64498
64499#define OTFAD_SR_RRAM_MASK (0x10000000U)
64500#define OTFAD_SR_RRAM_SHIFT (28U)
64505#define OTFAD_SR_RRAM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
64506
64507#define OTFAD_SR_GEM_MASK (0x20000000U)
64508#define OTFAD_SR_GEM_SHIFT (29U)
64513#define OTFAD_SR_GEM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)
64514
64515#define OTFAD_SR_KBPE_MASK (0x40000000U)
64516#define OTFAD_SR_KBPE_SHIFT (30U)
64521#define OTFAD_SR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK)
64522
64523#define OTFAD_SR_KBD_MASK (0x80000000U)
64524#define OTFAD_SR_KBD_SHIFT (31U)
64529#define OTFAD_SR_KBD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK)
64535#define OTFAD_KEY_KEY_MASK (0xFFFFFFFFU)
64536#define OTFAD_KEY_KEY_SHIFT (0U)
64539#define OTFAD_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK)
64542/* The count of OTFAD_KEY */
64543#define OTFAD_KEY_COUNT (4U)
64544
64545/* The count of OTFAD_KEY */
64546#define OTFAD_KEY_COUNT2 (4U)
64547
64551#define OTFAD_CTR_CTR_MASK (0xFFFFFFFFU)
64552#define OTFAD_CTR_CTR_SHIFT (0U)
64555#define OTFAD_CTR_CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK)
64558/* The count of OTFAD_CTR */
64559#define OTFAD_CTR_COUNT (4U)
64560
64561/* The count of OTFAD_CTR */
64562#define OTFAD_CTR_COUNT2 (2U)
64563
64567#define OTFAD_RGD_W0_SRTADDR_MASK (0xFFFFFC00U)
64568#define OTFAD_RGD_W0_SRTADDR_SHIFT (10U)
64571#define OTFAD_RGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK)
64574/* The count of OTFAD_RGD_W0 */
64575#define OTFAD_RGD_W0_COUNT (4U)
64576
64580#define OTFAD_RGD_W1_VLD_MASK (0x1U)
64581#define OTFAD_RGD_W1_VLD_SHIFT (0U)
64586#define OTFAD_RGD_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK)
64587
64588#define OTFAD_RGD_W1_ADE_MASK (0x2U)
64589#define OTFAD_RGD_W1_ADE_SHIFT (1U)
64594#define OTFAD_RGD_W1_ADE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK)
64595
64596#define OTFAD_RGD_W1_RO_MASK (0x4U)
64597#define OTFAD_RGD_W1_RO_SHIFT (2U)
64602#define OTFAD_RGD_W1_RO(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK)
64603
64604#define OTFAD_RGD_W1_ENDADDR_MASK (0xFFFFFC00U)
64605#define OTFAD_RGD_W1_ENDADDR_SHIFT (10U)
64608#define OTFAD_RGD_W1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK)
64611/* The count of OTFAD_RGD_W1 */
64612#define OTFAD_RGD_W1_COUNT (4U)
64613
64614 /* end of group OTFAD_Register_Masks */
64618
64619
64620/* OTFAD - Peripheral instance base addresses */
64622#define OTFAD1_BASE (0x400CC000u)
64624#define OTFAD1 ((OTFAD_Type *)OTFAD1_BASE)
64626#define OTFAD2_BASE (0x400D0000u)
64628#define OTFAD2 ((OTFAD_Type *)OTFAD2_BASE)
64630#define OTFAD_BASE_ADDRS { 0u, OTFAD1_BASE, OTFAD2_BASE }
64632#define OTFAD_BASE_PTRS { (OTFAD_Type *)0u, OTFAD1, OTFAD2 }
64633 /* end of group OTFAD_Peripheral_Access_Layer */
64637
64638
64639/* ----------------------------------------------------------------------------
64640 -- PDM Peripheral Access Layer
64641 ---------------------------------------------------------------------------- */
64642
64649typedef struct {
64650 __IO uint32_t CTRL_1;
64651 __IO uint32_t CTRL_2;
64652 __IO uint32_t STAT;
64653 uint8_t RESERVED_0[4];
64654 __IO uint32_t FIFO_CTRL;
64655 __IO uint32_t FIFO_STAT;
64656 uint8_t RESERVED_1[12];
64657 __I uint32_t DATACH[8];
64658 uint8_t RESERVED_2[32];
64659 __IO uint32_t DC_CTRL;
64660 uint8_t RESERVED_3[12];
64661 __IO uint32_t RANGE_CTRL;
64662 uint8_t RESERVED_4[4];
64663 __IO uint32_t RANGE_STAT;
64664 uint8_t RESERVED_5[16];
64665 __IO uint32_t VAD0_CTRL_1;
64666 __IO uint32_t VAD0_CTRL_2;
64667 __IO uint32_t VAD0_STAT;
64668 __IO uint32_t VAD0_SCONFIG;
64669 __IO uint32_t VAD0_NCONFIG;
64670 __I uint32_t VAD0_NDATA;
64671 __IO uint32_t VAD0_ZCD;
64672} PDM_Type;
64673
64674/* ----------------------------------------------------------------------------
64675 -- PDM Register Masks
64676 ---------------------------------------------------------------------------- */
64677
64686#define PDM_CTRL_1_CH0EN_MASK (0x1U)
64687#define PDM_CTRL_1_CH0EN_SHIFT (0U)
64690#define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)
64691
64692#define PDM_CTRL_1_CH1EN_MASK (0x2U)
64693#define PDM_CTRL_1_CH1EN_SHIFT (1U)
64696#define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)
64697
64698#define PDM_CTRL_1_CH2EN_MASK (0x4U)
64699#define PDM_CTRL_1_CH2EN_SHIFT (2U)
64702#define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)
64703
64704#define PDM_CTRL_1_CH3EN_MASK (0x8U)
64705#define PDM_CTRL_1_CH3EN_SHIFT (3U)
64708#define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)
64709
64710#define PDM_CTRL_1_CH4EN_MASK (0x10U)
64711#define PDM_CTRL_1_CH4EN_SHIFT (4U)
64714#define PDM_CTRL_1_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)
64715
64716#define PDM_CTRL_1_CH5EN_MASK (0x20U)
64717#define PDM_CTRL_1_CH5EN_SHIFT (5U)
64720#define PDM_CTRL_1_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)
64721
64722#define PDM_CTRL_1_CH6EN_MASK (0x40U)
64723#define PDM_CTRL_1_CH6EN_SHIFT (6U)
64726#define PDM_CTRL_1_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)
64727
64728#define PDM_CTRL_1_CH7EN_MASK (0x80U)
64729#define PDM_CTRL_1_CH7EN_SHIFT (7U)
64732#define PDM_CTRL_1_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)
64733
64734#define PDM_CTRL_1_ERREN_MASK (0x800000U)
64735#define PDM_CTRL_1_ERREN_SHIFT (23U)
64740#define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)
64741
64742#define PDM_CTRL_1_DISEL_MASK (0x3000000U)
64743#define PDM_CTRL_1_DISEL_SHIFT (24U)
64750#define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)
64751
64752#define PDM_CTRL_1_DBGE_MASK (0x4000000U)
64753#define PDM_CTRL_1_DBGE_SHIFT (26U)
64758#define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)
64759
64760#define PDM_CTRL_1_SRES_MASK (0x8000000U)
64761#define PDM_CTRL_1_SRES_SHIFT (27U)
64766#define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)
64767
64768#define PDM_CTRL_1_DBG_MASK (0x10000000U)
64769#define PDM_CTRL_1_DBG_SHIFT (28U)
64774#define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)
64775
64776#define PDM_CTRL_1_PDMIEN_MASK (0x20000000U)
64777#define PDM_CTRL_1_PDMIEN_SHIFT (29U)
64782#define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)
64783
64784#define PDM_CTRL_1_DOZEN_MASK (0x40000000U)
64785#define PDM_CTRL_1_DOZEN_SHIFT (30U)
64788#define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)
64789
64790#define PDM_CTRL_1_MDIS_MASK (0x80000000U)
64791#define PDM_CTRL_1_MDIS_SHIFT (31U)
64796#define PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
64802#define PDM_CTRL_2_CLKDIV_MASK (0xFFU)
64803#define PDM_CTRL_2_CLKDIV_SHIFT (0U)
64806#define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)
64807
64808#define PDM_CTRL_2_CICOSR_MASK (0xF0000U)
64809#define PDM_CTRL_2_CICOSR_SHIFT (16U)
64812#define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)
64813
64814#define PDM_CTRL_2_QSEL_MASK (0xE000000U)
64815#define PDM_CTRL_2_QSEL_SHIFT (25U)
64824#define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
64830#define PDM_STAT_CH0F_MASK (0x1U)
64831#define PDM_STAT_CH0F_SHIFT (0U)
64836#define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)
64837
64838#define PDM_STAT_CH1F_MASK (0x2U)
64839#define PDM_STAT_CH1F_SHIFT (1U)
64844#define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)
64845
64846#define PDM_STAT_CH2F_MASK (0x4U)
64847#define PDM_STAT_CH2F_SHIFT (2U)
64852#define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)
64853
64854#define PDM_STAT_CH3F_MASK (0x8U)
64855#define PDM_STAT_CH3F_SHIFT (3U)
64860#define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)
64861
64862#define PDM_STAT_CH4F_MASK (0x10U)
64863#define PDM_STAT_CH4F_SHIFT (4U)
64868#define PDM_STAT_CH4F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)
64869
64870#define PDM_STAT_CH5F_MASK (0x20U)
64871#define PDM_STAT_CH5F_SHIFT (5U)
64876#define PDM_STAT_CH5F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)
64877
64878#define PDM_STAT_CH6F_MASK (0x40U)
64879#define PDM_STAT_CH6F_SHIFT (6U)
64884#define PDM_STAT_CH6F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)
64885
64886#define PDM_STAT_CH7F_MASK (0x80U)
64887#define PDM_STAT_CH7F_SHIFT (7U)
64892#define PDM_STAT_CH7F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)
64893
64894#define PDM_STAT_LOWFREQF_MASK (0x20000000U)
64895#define PDM_STAT_LOWFREQF_SHIFT (29U)
64900#define PDM_STAT_LOWFREQF(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)
64901
64902#define PDM_STAT_FIR_RDY_MASK (0x40000000U)
64903#define PDM_STAT_FIR_RDY_SHIFT (30U)
64908#define PDM_STAT_FIR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)
64909
64910#define PDM_STAT_BSY_FIL_MASK (0x80000000U)
64911#define PDM_STAT_BSY_FIL_SHIFT (31U)
64916#define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
64922#define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U)
64923#define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U)
64926#define PDM_FIFO_CTRL_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
64932#define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U)
64933#define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U)
64938#define PDM_FIFO_STAT_FIFOOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)
64939
64940#define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U)
64941#define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U)
64946#define PDM_FIFO_STAT_FIFOOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)
64947
64948#define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U)
64949#define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U)
64954#define PDM_FIFO_STAT_FIFOOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)
64955
64956#define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U)
64957#define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U)
64962#define PDM_FIFO_STAT_FIFOOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)
64963
64964#define PDM_FIFO_STAT_FIFOOVF4_MASK (0x10U)
64965#define PDM_FIFO_STAT_FIFOOVF4_SHIFT (4U)
64970#define PDM_FIFO_STAT_FIFOOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)
64971
64972#define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U)
64973#define PDM_FIFO_STAT_FIFOOVF5_SHIFT (5U)
64978#define PDM_FIFO_STAT_FIFOOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
64979
64980#define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U)
64981#define PDM_FIFO_STAT_FIFOOVF6_SHIFT (6U)
64986#define PDM_FIFO_STAT_FIFOOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
64987
64988#define PDM_FIFO_STAT_FIFOOVF7_MASK (0x80U)
64989#define PDM_FIFO_STAT_FIFOOVF7_SHIFT (7U)
64994#define PDM_FIFO_STAT_FIFOOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)
64995
64996#define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U)
64997#define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U)
65002#define PDM_FIFO_STAT_FIFOUND0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)
65003
65004#define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U)
65005#define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U)
65010#define PDM_FIFO_STAT_FIFOUND1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)
65011
65012#define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U)
65013#define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U)
65018#define PDM_FIFO_STAT_FIFOUND2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)
65019
65020#define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U)
65021#define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U)
65026#define PDM_FIFO_STAT_FIFOUND3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)
65027
65028#define PDM_FIFO_STAT_FIFOUND4_MASK (0x1000U)
65029#define PDM_FIFO_STAT_FIFOUND4_SHIFT (12U)
65034#define PDM_FIFO_STAT_FIFOUND4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)
65035
65036#define PDM_FIFO_STAT_FIFOUND5_MASK (0x2000U)
65037#define PDM_FIFO_STAT_FIFOUND5_SHIFT (13U)
65042#define PDM_FIFO_STAT_FIFOUND5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)
65043
65044#define PDM_FIFO_STAT_FIFOUND6_MASK (0x4000U)
65045#define PDM_FIFO_STAT_FIFOUND6_SHIFT (14U)
65050#define PDM_FIFO_STAT_FIFOUND6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)
65051
65052#define PDM_FIFO_STAT_FIFOUND7_MASK (0x8000U)
65053#define PDM_FIFO_STAT_FIFOUND7_SHIFT (15U)
65058#define PDM_FIFO_STAT_FIFOUND7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
65064#define PDM_DATACH_DATA_MASK (0xFFFFFFFFU)
65065#define PDM_DATACH_DATA_SHIFT (0U)
65068#define PDM_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
65071/* The count of PDM_DATACH */
65072#define PDM_DATACH_COUNT (8U)
65073
65077#define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U)
65078#define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U)
65085#define PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)
65086
65087#define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU)
65088#define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U)
65095#define PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)
65096
65097#define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U)
65098#define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U)
65105#define PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)
65106
65107#define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U)
65108#define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U)
65115#define PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)
65116
65117#define PDM_DC_CTRL_DCCONFIG4_MASK (0x300U)
65118#define PDM_DC_CTRL_DCCONFIG4_SHIFT (8U)
65125#define PDM_DC_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)
65126
65127#define PDM_DC_CTRL_DCCONFIG5_MASK (0xC00U)
65128#define PDM_DC_CTRL_DCCONFIG5_SHIFT (10U)
65135#define PDM_DC_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)
65136
65137#define PDM_DC_CTRL_DCCONFIG6_MASK (0x3000U)
65138#define PDM_DC_CTRL_DCCONFIG6_SHIFT (12U)
65145#define PDM_DC_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)
65146
65147#define PDM_DC_CTRL_DCCONFIG7_MASK (0xC000U)
65148#define PDM_DC_CTRL_DCCONFIG7_SHIFT (14U)
65155#define PDM_DC_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
65161#define PDM_RANGE_CTRL_RANGEADJ0_MASK (0xFU)
65162#define PDM_RANGE_CTRL_RANGEADJ0_SHIFT (0U)
65165#define PDM_RANGE_CTRL_RANGEADJ0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)
65166
65167#define PDM_RANGE_CTRL_RANGEADJ1_MASK (0xF0U)
65168#define PDM_RANGE_CTRL_RANGEADJ1_SHIFT (4U)
65171#define PDM_RANGE_CTRL_RANGEADJ1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)
65172
65173#define PDM_RANGE_CTRL_RANGEADJ2_MASK (0xF00U)
65174#define PDM_RANGE_CTRL_RANGEADJ2_SHIFT (8U)
65177#define PDM_RANGE_CTRL_RANGEADJ2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)
65178
65179#define PDM_RANGE_CTRL_RANGEADJ3_MASK (0xF000U)
65180#define PDM_RANGE_CTRL_RANGEADJ3_SHIFT (12U)
65183#define PDM_RANGE_CTRL_RANGEADJ3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)
65184
65185#define PDM_RANGE_CTRL_RANGEADJ4_MASK (0xF0000U)
65186#define PDM_RANGE_CTRL_RANGEADJ4_SHIFT (16U)
65189#define PDM_RANGE_CTRL_RANGEADJ4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)
65190
65191#define PDM_RANGE_CTRL_RANGEADJ5_MASK (0xF00000U)
65192#define PDM_RANGE_CTRL_RANGEADJ5_SHIFT (20U)
65195#define PDM_RANGE_CTRL_RANGEADJ5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)
65196
65197#define PDM_RANGE_CTRL_RANGEADJ6_MASK (0xF000000U)
65198#define PDM_RANGE_CTRL_RANGEADJ6_SHIFT (24U)
65201#define PDM_RANGE_CTRL_RANGEADJ6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)
65202
65203#define PDM_RANGE_CTRL_RANGEADJ7_MASK (0xF0000000U)
65204#define PDM_RANGE_CTRL_RANGEADJ7_SHIFT (28U)
65207#define PDM_RANGE_CTRL_RANGEADJ7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)
65213#define PDM_RANGE_STAT_RANGEOVF0_MASK (0x1U)
65214#define PDM_RANGE_STAT_RANGEOVF0_SHIFT (0U)
65219#define PDM_RANGE_STAT_RANGEOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)
65220
65221#define PDM_RANGE_STAT_RANGEOVF1_MASK (0x2U)
65222#define PDM_RANGE_STAT_RANGEOVF1_SHIFT (1U)
65227#define PDM_RANGE_STAT_RANGEOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)
65228
65229#define PDM_RANGE_STAT_RANGEOVF2_MASK (0x4U)
65230#define PDM_RANGE_STAT_RANGEOVF2_SHIFT (2U)
65235#define PDM_RANGE_STAT_RANGEOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)
65236
65237#define PDM_RANGE_STAT_RANGEOVF3_MASK (0x8U)
65238#define PDM_RANGE_STAT_RANGEOVF3_SHIFT (3U)
65243#define PDM_RANGE_STAT_RANGEOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)
65244
65245#define PDM_RANGE_STAT_RANGEOVF4_MASK (0x10U)
65246#define PDM_RANGE_STAT_RANGEOVF4_SHIFT (4U)
65251#define PDM_RANGE_STAT_RANGEOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)
65252
65253#define PDM_RANGE_STAT_RANGEOVF5_MASK (0x20U)
65254#define PDM_RANGE_STAT_RANGEOVF5_SHIFT (5U)
65259#define PDM_RANGE_STAT_RANGEOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)
65260
65261#define PDM_RANGE_STAT_RANGEOVF6_MASK (0x40U)
65262#define PDM_RANGE_STAT_RANGEOVF6_SHIFT (6U)
65267#define PDM_RANGE_STAT_RANGEOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)
65268
65269#define PDM_RANGE_STAT_RANGEOVF7_MASK (0x80U)
65270#define PDM_RANGE_STAT_RANGEOVF7_SHIFT (7U)
65275#define PDM_RANGE_STAT_RANGEOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)
65276
65277#define PDM_RANGE_STAT_RANGEUNF0_MASK (0x10000U)
65278#define PDM_RANGE_STAT_RANGEUNF0_SHIFT (16U)
65283#define PDM_RANGE_STAT_RANGEUNF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)
65284
65285#define PDM_RANGE_STAT_RANGEUNF1_MASK (0x20000U)
65286#define PDM_RANGE_STAT_RANGEUNF1_SHIFT (17U)
65291#define PDM_RANGE_STAT_RANGEUNF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)
65292
65293#define PDM_RANGE_STAT_RANGEUNF2_MASK (0x40000U)
65294#define PDM_RANGE_STAT_RANGEUNF2_SHIFT (18U)
65299#define PDM_RANGE_STAT_RANGEUNF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)
65300
65301#define PDM_RANGE_STAT_RANGEUNF3_MASK (0x80000U)
65302#define PDM_RANGE_STAT_RANGEUNF3_SHIFT (19U)
65307#define PDM_RANGE_STAT_RANGEUNF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)
65308
65309#define PDM_RANGE_STAT_RANGEUNF4_MASK (0x100000U)
65310#define PDM_RANGE_STAT_RANGEUNF4_SHIFT (20U)
65315#define PDM_RANGE_STAT_RANGEUNF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)
65316
65317#define PDM_RANGE_STAT_RANGEUNF5_MASK (0x200000U)
65318#define PDM_RANGE_STAT_RANGEUNF5_SHIFT (21U)
65323#define PDM_RANGE_STAT_RANGEUNF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)
65324
65325#define PDM_RANGE_STAT_RANGEUNF6_MASK (0x400000U)
65326#define PDM_RANGE_STAT_RANGEUNF6_SHIFT (22U)
65331#define PDM_RANGE_STAT_RANGEUNF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)
65332
65333#define PDM_RANGE_STAT_RANGEUNF7_MASK (0x800000U)
65334#define PDM_RANGE_STAT_RANGEUNF7_SHIFT (23U)
65339#define PDM_RANGE_STAT_RANGEUNF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)
65345#define PDM_VAD0_CTRL_1_VADEN_MASK (0x1U)
65346#define PDM_VAD0_CTRL_1_VADEN_SHIFT (0U)
65351#define PDM_VAD0_CTRL_1_VADEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)
65352
65353#define PDM_VAD0_CTRL_1_VADRST_MASK (0x2U)
65354#define PDM_VAD0_CTRL_1_VADRST_SHIFT (1U)
65357#define PDM_VAD0_CTRL_1_VADRST(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)
65358
65359#define PDM_VAD0_CTRL_1_VADIE_MASK (0x4U)
65360#define PDM_VAD0_CTRL_1_VADIE_SHIFT (2U)
65365#define PDM_VAD0_CTRL_1_VADIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)
65366
65367#define PDM_VAD0_CTRL_1_VADERIE_MASK (0x8U)
65368#define PDM_VAD0_CTRL_1_VADERIE_SHIFT (3U)
65373#define PDM_VAD0_CTRL_1_VADERIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)
65374
65375#define PDM_VAD0_CTRL_1_VADST10_MASK (0x10U)
65376#define PDM_VAD0_CTRL_1_VADST10_SHIFT (4U)
65381#define PDM_VAD0_CTRL_1_VADST10(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)
65382
65383#define PDM_VAD0_CTRL_1_VADINITT_MASK (0x1F00U)
65384#define PDM_VAD0_CTRL_1_VADINITT_SHIFT (8U)
65387#define PDM_VAD0_CTRL_1_VADINITT(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)
65388
65389#define PDM_VAD0_CTRL_1_VADCICOSR_MASK (0xF0000U)
65390#define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT (16U)
65393#define PDM_VAD0_CTRL_1_VADCICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)
65394
65395#define PDM_VAD0_CTRL_1_VADCHSEL_MASK (0x7000000U)
65396#define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT (24U)
65399#define PDM_VAD0_CTRL_1_VADCHSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
65405#define PDM_VAD0_CTRL_2_VADHPF_MASK (0x3U)
65406#define PDM_VAD0_CTRL_2_VADHPF_SHIFT (0U)
65413#define PDM_VAD0_CTRL_2_VADHPF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)
65414
65415#define PDM_VAD0_CTRL_2_VADINPGAIN_MASK (0xF00U)
65416#define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT (8U)
65419#define PDM_VAD0_CTRL_2_VADINPGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)
65420
65421#define PDM_VAD0_CTRL_2_VADFRAMET_MASK (0x3F0000U)
65422#define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT (16U)
65425#define PDM_VAD0_CTRL_2_VADFRAMET(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)
65426
65427#define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK (0x10000000U)
65428#define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT (28U)
65433#define PDM_VAD0_CTRL_2_VADFOUTDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)
65434
65435#define PDM_VAD0_CTRL_2_VADPREFEN_MASK (0x40000000U)
65436#define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT (30U)
65441#define PDM_VAD0_CTRL_2_VADPREFEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)
65442
65443#define PDM_VAD0_CTRL_2_VADFRENDIS_MASK (0x80000000U)
65444#define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT (31U)
65449#define PDM_VAD0_CTRL_2_VADFRENDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
65455#define PDM_VAD0_STAT_VADIF_MASK (0x1U)
65456#define PDM_VAD0_STAT_VADIF_SHIFT (0U)
65461#define PDM_VAD0_STAT_VADIF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)
65462
65463#define PDM_VAD0_STAT_VADEF_MASK (0x8000U)
65464#define PDM_VAD0_STAT_VADEF_SHIFT (15U)
65469#define PDM_VAD0_STAT_VADEF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK)
65470
65471#define PDM_VAD0_STAT_VADINSATF_MASK (0x10000U)
65472#define PDM_VAD0_STAT_VADINSATF_SHIFT (16U)
65477#define PDM_VAD0_STAT_VADINSATF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)
65478
65479#define PDM_VAD0_STAT_VADINITF_MASK (0x80000000U)
65480#define PDM_VAD0_STAT_VADINITF_SHIFT (31U)
65485#define PDM_VAD0_STAT_VADINITF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
65491#define PDM_VAD0_SCONFIG_VADSGAIN_MASK (0xFU)
65492#define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT (0U)
65495#define PDM_VAD0_SCONFIG_VADSGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)
65496
65497#define PDM_VAD0_SCONFIG_VADSMAXEN_MASK (0x40000000U)
65498#define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT (30U)
65503#define PDM_VAD0_SCONFIG_VADSMAXEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)
65504
65505#define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U)
65506#define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT (31U)
65511#define PDM_VAD0_SCONFIG_VADSFILEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
65517#define PDM_VAD0_NCONFIG_VADNGAIN_MASK (0xFU)
65518#define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT (0U)
65521#define PDM_VAD0_NCONFIG_VADNGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)
65522
65523#define PDM_VAD0_NCONFIG_VADNFILADJ_MASK (0x1F00U)
65524#define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT (8U)
65527#define PDM_VAD0_NCONFIG_VADNFILADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)
65528
65529#define PDM_VAD0_NCONFIG_VADNOREN_MASK (0x10000000U)
65530#define PDM_VAD0_NCONFIG_VADNOREN_SHIFT (28U)
65535#define PDM_VAD0_NCONFIG_VADNOREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)
65536
65537#define PDM_VAD0_NCONFIG_VADNDECEN_MASK (0x20000000U)
65538#define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT (29U)
65543#define PDM_VAD0_NCONFIG_VADNDECEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)
65544
65545#define PDM_VAD0_NCONFIG_VADNMINEN_MASK (0x40000000U)
65546#define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT (30U)
65551#define PDM_VAD0_NCONFIG_VADNMINEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)
65552
65553#define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK (0x80000000U)
65554#define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT (31U)
65559#define PDM_VAD0_NCONFIG_VADNFILAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
65565#define PDM_VAD0_NDATA_VADNDATA_MASK (0xFFFFU)
65566#define PDM_VAD0_NDATA_VADNDATA_SHIFT (0U)
65569#define PDM_VAD0_NDATA_VADNDATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
65575#define PDM_VAD0_ZCD_VADZCDEN_MASK (0x1U)
65576#define PDM_VAD0_ZCD_VADZCDEN_SHIFT (0U)
65581#define PDM_VAD0_ZCD_VADZCDEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)
65582
65583#define PDM_VAD0_ZCD_VADZCDAUTO_MASK (0x4U)
65584#define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT (2U)
65589#define PDM_VAD0_ZCD_VADZCDAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)
65590
65591#define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U)
65592#define PDM_VAD0_ZCD_VADZCDAND_SHIFT (4U)
65597#define PDM_VAD0_ZCD_VADZCDAND(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
65598
65599#define PDM_VAD0_ZCD_VADZCDADJ_MASK (0xF00U)
65600#define PDM_VAD0_ZCD_VADZCDADJ_SHIFT (8U)
65603#define PDM_VAD0_ZCD_VADZCDADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)
65604
65605#define PDM_VAD0_ZCD_VADZCDTH_MASK (0x3FF0000U)
65606#define PDM_VAD0_ZCD_VADZCDTH_SHIFT (16U)
65609#define PDM_VAD0_ZCD_VADZCDTH(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK) /* end of group PDM_Register_Masks */
65616
65617
65618/* PDM - Peripheral instance base addresses */
65620#define PDM_BASE (0x40C20000u)
65622#define PDM ((PDM_Type *)PDM_BASE)
65624#define PDM_BASE_ADDRS { PDM_BASE }
65626#define PDM_BASE_PTRS { PDM }
65627 /* end of group PDM_Peripheral_Access_Layer */
65631
65632
65633/* ----------------------------------------------------------------------------
65634 -- PGMC_BPC Peripheral Access Layer
65635 ---------------------------------------------------------------------------- */
65636
65643typedef struct {
65644 uint8_t RESERVED_0[4];
65645 __IO uint32_t BPC_AUTHEN_CTRL;
65646 uint8_t RESERVED_1[8];
65647 __IO uint32_t BPC_MODE;
65648 __IO uint32_t BPC_POWER_CTRL;
65649 uint8_t RESERVED_2[20];
65650 __IO uint32_t BPC_FLAG;
65651 uint8_t RESERVED_3[16];
65652 __IO uint32_t BPC_SSAR_SAVE_CTRL;
65653 __IO uint32_t BPC_SSAR_RESTORE_CTRL;
65655
65656/* ----------------------------------------------------------------------------
65657 -- PGMC_BPC Register Masks
65658 ---------------------------------------------------------------------------- */
65659
65668#define PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK (0x1U)
65669#define PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT (0U)
65674#define PGMC_BPC_BPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK)
65675
65676#define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
65677#define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
65682#define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK)
65683
65684#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
65685#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
65688#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
65689
65690#define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
65691#define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
65694#define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK)
65695
65696#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
65697#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
65700#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK)
65701
65702#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
65703#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
65706#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK)
65712#define PGMC_BPC_BPC_MODE_CTRL_MODE_MASK (0x3U)
65713#define PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT (0U)
65720#define PGMC_BPC_BPC_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT)) & PGMC_BPC_BPC_MODE_CTRL_MODE_MASK)
65721
65722#define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK (0x30U)
65723#define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT (4U)
65730#define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK)
65736#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U)
65737#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U)
65740#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)
65741
65742#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U)
65743#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U)
65746#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK)
65747
65748#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U)
65749#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U)
65752#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)
65753
65754#define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U)
65755#define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U)
65758#define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK)
65759
65760#define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U)
65761#define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U)
65764#define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK)
65765
65766#define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U)
65767#define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U)
65770#define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK)
65771
65772#define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U)
65773#define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U)
65776#define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK)
65777
65778#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK (0xFFFF0000U)
65779#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT (16U)
65782#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK)
65788#define PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK (0x1U)
65789#define PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT (0U)
65792#define PGMC_BPC_BPC_FLAG_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT)) & PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK)
65798#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK (0x1U)
65799#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT (0U)
65802#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK)
65803
65804#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK (0x2U)
65805#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT (1U)
65808#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK)
65809
65810#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK (0x4U)
65811#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT (2U)
65814#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK)
65815
65816#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK (0x8U)
65817#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT (3U)
65820#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK)
65821
65822#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK (0xFFFF0000U)
65823#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT (16U)
65826#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK)
65832#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK (0x1U)
65833#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT (0U)
65836#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK)
65837
65838#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK (0xFFFF0000U)
65839#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT (16U)
65842#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK) /* end of group PGMC_BPC_Register_Masks */
65849
65850
65851/* PGMC_BPC - Peripheral instance base addresses */
65853#define PGMC_BPC0_BASE (0x40C88000u)
65855#define PGMC_BPC0 ((PGMC_BPC_Type *)PGMC_BPC0_BASE)
65857#define PGMC_BPC1_BASE (0x40C88200u)
65859#define PGMC_BPC1 ((PGMC_BPC_Type *)PGMC_BPC1_BASE)
65861#define PGMC_BPC2_BASE (0x40C88400u)
65863#define PGMC_BPC2 ((PGMC_BPC_Type *)PGMC_BPC2_BASE)
65865#define PGMC_BPC3_BASE (0x40C88600u)
65867#define PGMC_BPC3 ((PGMC_BPC_Type *)PGMC_BPC3_BASE)
65869#define PGMC_BPC4_BASE (0x40C88800u)
65871#define PGMC_BPC4 ((PGMC_BPC_Type *)PGMC_BPC4_BASE)
65873#define PGMC_BPC5_BASE (0x40C88A00u)
65875#define PGMC_BPC5 ((PGMC_BPC_Type *)PGMC_BPC5_BASE)
65877#define PGMC_BPC6_BASE (0x40C88C00u)
65879#define PGMC_BPC6 ((PGMC_BPC_Type *)PGMC_BPC6_BASE)
65881#define PGMC_BPC7_BASE (0x40C88E00u)
65883#define PGMC_BPC7 ((PGMC_BPC_Type *)PGMC_BPC7_BASE)
65885#define PGMC_BPC_BASE_ADDRS { PGMC_BPC0_BASE, PGMC_BPC1_BASE, PGMC_BPC2_BASE, PGMC_BPC3_BASE, PGMC_BPC4_BASE, PGMC_BPC5_BASE, PGMC_BPC6_BASE, PGMC_BPC7_BASE }
65887#define PGMC_BPC_BASE_PTRS { PGMC_BPC0, PGMC_BPC1, PGMC_BPC2, PGMC_BPC3, PGMC_BPC4, PGMC_BPC5, PGMC_BPC6, PGMC_BPC7 }
65888 /* end of group PGMC_BPC_Peripheral_Access_Layer */
65892
65893
65894/* ----------------------------------------------------------------------------
65895 -- PGMC_CPC Peripheral Access Layer
65896 ---------------------------------------------------------------------------- */
65897
65904typedef struct {
65905 uint8_t RESERVED_0[4];
65906 __IO uint32_t CPC_AUTHEN_CTRL;
65907 uint8_t RESERVED_1[8];
65908 __IO uint32_t CPC_CORE_MODE;
65909 __IO uint32_t CPC_CORE_POWER_CTRL;
65910 uint8_t RESERVED_2[20];
65911 __IO uint32_t CPC_FLAG;
65912 uint8_t RESERVED_3[16];
65913 __IO uint32_t CPC_CACHE_MODE;
65914 __IO uint32_t CPC_CACHE_CM_CTRL;
65915 __IO uint32_t CPC_CACHE_SP_CTRL_0;
65916 __IO uint32_t CPC_CACHE_SP_CTRL_1;
65917 uint8_t RESERVED_4[112];
65918 __IO uint32_t CPC_LMEM_MODE;
65919 __IO uint32_t CPC_LMEM_CM_CTRL;
65920 __IO uint32_t CPC_LMEM_SP_CTRL_0;
65921 __IO uint32_t CPC_LMEM_SP_CTRL_1;
65923
65924/* ----------------------------------------------------------------------------
65925 -- PGMC_CPC Register Masks
65926 ---------------------------------------------------------------------------- */
65927
65936#define PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK (0x1U)
65937#define PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT (0U)
65940#define PGMC_CPC_CPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK)
65941
65942#define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
65943#define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
65946#define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK)
65947
65948#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
65949#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
65952#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
65953
65954#define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
65955#define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
65958#define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK)
65959
65960#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
65961#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
65964#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK)
65965
65966#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
65967#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
65970#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK)
65976#define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK (0x3U)
65977#define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT (0U)
65984#define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK)
65990#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U)
65991#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U)
65994#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)
65995
65996#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U)
65997#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U)
66000#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK)
66001
66002#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U)
66003#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U)
66006#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)
66007
66008#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U)
66009#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U)
66012#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK)
66013
66014#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U)
66015#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U)
66018#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK)
66019
66020#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U)
66021#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U)
66024#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK)
66025
66026#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U)
66027#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U)
66030#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK)
66036#define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK (0x1U)
66037#define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT (0U)
66040#define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT)) & PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK)
66046#define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK (0x3U)
66047#define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT (0U)
66054#define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK)
66060#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)
66061#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)
66064#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK)
66065
66066#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)
66067#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)
66070#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK)
66071
66072#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)
66073#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)
66076#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK)
66077
66078#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)
66079#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)
66082#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK)
66083
66084#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK (0x10000U)
66085#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT (16U)
66088#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK)
66094#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)
66095#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)
66098#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK)
66099
66100#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)
66101#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)
66104#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK)
66105
66106#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)
66107#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)
66110#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK)
66111
66112#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)
66113#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)
66116#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK)
66117
66118#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)
66119#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)
66122#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK)
66123
66124#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)
66125#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)
66128#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK)
66129
66130#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)
66131#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)
66134#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK)
66135
66136#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)
66137#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)
66140#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK)
66146#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)
66147#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)
66150#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK)
66151
66152#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)
66153#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)
66156#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK)
66157
66158#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)
66159#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)
66162#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK)
66163
66164#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)
66165#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)
66168#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK)
66169
66170#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)
66171#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)
66174#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK)
66175
66176#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)
66177#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)
66180#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK)
66181
66182#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)
66183#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)
66186#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK)
66187
66188#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)
66189#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)
66192#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK)
66198#define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK (0x3U)
66199#define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT (0U)
66206#define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK)
66212#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)
66213#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)
66216#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK)
66217
66218#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)
66219#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)
66222#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK)
66223
66224#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)
66225#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)
66228#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK)
66229
66230#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)
66231#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)
66234#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK)
66235
66236#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK (0x10000U)
66237#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT (16U)
66240#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK)
66246#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)
66247#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)
66250#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK)
66251
66252#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)
66253#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)
66256#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK)
66257
66258#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)
66259#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)
66262#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK)
66263
66264#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)
66265#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)
66268#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK)
66269
66270#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)
66271#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)
66274#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK)
66275
66276#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)
66277#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)
66280#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK)
66281
66282#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)
66283#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)
66286#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK)
66287
66288#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)
66289#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)
66292#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK)
66298#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)
66299#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)
66302#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK)
66303
66304#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)
66305#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)
66308#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK)
66309
66310#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)
66311#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)
66314#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK)
66315
66316#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)
66317#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)
66320#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK)
66321
66322#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)
66323#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)
66326#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK)
66327
66328#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)
66329#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)
66332#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK)
66333
66334#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)
66335#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)
66338#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK)
66339
66340#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)
66341#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)
66344#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK) /* end of group PGMC_CPC_Register_Masks */
66351
66352
66353/* PGMC_CPC - Peripheral instance base addresses */
66355#define PGMC_CPC0_BASE (0x40C89000u)
66357#define PGMC_CPC0 ((PGMC_CPC_Type *)PGMC_CPC0_BASE)
66359#define PGMC_CPC1_BASE (0x40C89400u)
66361#define PGMC_CPC1 ((PGMC_CPC_Type *)PGMC_CPC1_BASE)
66363#define PGMC_CPC_BASE_ADDRS { PGMC_CPC0_BASE, PGMC_CPC1_BASE }
66365#define PGMC_CPC_BASE_PTRS { PGMC_CPC0, PGMC_CPC1 }
66366 /* end of group PGMC_CPC_Peripheral_Access_Layer */
66370
66371
66372/* ----------------------------------------------------------------------------
66373 -- PGMC_MIF Peripheral Access Layer
66374 ---------------------------------------------------------------------------- */
66375
66382typedef struct {
66383 uint8_t RESERVED_0[4];
66384 __IO uint32_t MIF_AUTHEN_CTRL;
66385 uint8_t RESERVED_1[8];
66386 __IO uint32_t MIF_MLPL_SLEEP;
66387 uint8_t RESERVED_2[12];
66388 __IO uint32_t MIF_MLPL_IG;
66389 uint8_t RESERVED_3[12];
66390 __IO uint32_t MIF_MLPL_LS;
66391 uint8_t RESERVED_4[12];
66392 __IO uint32_t MIF_MLPL_HS;
66393 uint8_t RESERVED_5[12];
66394 __IO uint32_t MIF_MLPL_STDBY;
66395 uint8_t RESERVED_6[12];
66396 __IO uint32_t MIF_MLPL_ARR_PDN;
66397 uint8_t RESERVED_7[12];
66398 __IO uint32_t MIF_MLPL_PER_PDN;
66399 uint8_t RESERVED_8[12];
66400 __IO uint32_t MIF_MLPL_INITN;
66401 uint8_t RESERVED_9[44];
66402 __IO uint32_t MIF_MLPL_ISO;
66404
66405/* ----------------------------------------------------------------------------
66406 -- PGMC_MIF Register Masks
66407 ---------------------------------------------------------------------------- */
66408
66417#define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
66418#define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
66421#define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK)
66427#define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK (0xFFFFU)
66428#define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT (0U)
66431#define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK)
66437#define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK (0xFFFFU)
66438#define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT (0U)
66441#define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK)
66447#define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK (0xFFFFU)
66448#define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT (0U)
66451#define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK)
66457#define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK (0xFFFFU)
66458#define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT (0U)
66461#define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK)
66467#define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK (0xFFFFU)
66468#define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT (0U)
66471#define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK)
66477#define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK (0xFFFFU)
66478#define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT (0U)
66481#define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK)
66487#define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK (0xFFFFU)
66488#define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT (0U)
66491#define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK)
66497#define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK (0xFFFFU)
66498#define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT (0U)
66501#define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK)
66502
66503#define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK (0x80000000U)
66504#define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT (31U)
66507#define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK)
66513#define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK (0xFFFFU)
66514#define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT (0U)
66517#define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK) /* end of group PGMC_MIF_Register_Masks */
66524
66525
66526/* PGMC_MIF - Peripheral instance base addresses */
66528#define PGMC_CPC0_MIF0_BASE (0x40C89100u)
66530#define PGMC_CPC0_MIF0 ((PGMC_MIF_Type *)PGMC_CPC0_MIF0_BASE)
66532#define PGMC_CPC0_MIF1_BASE (0x40C89200u)
66534#define PGMC_CPC0_MIF1 ((PGMC_MIF_Type *)PGMC_CPC0_MIF1_BASE)
66536#define PGMC_CPC1_MIF0_BASE (0x40C89500u)
66538#define PGMC_CPC1_MIF0 ((PGMC_MIF_Type *)PGMC_CPC1_MIF0_BASE)
66540#define PGMC_CPC1_MIF1_BASE (0x40C89600u)
66542#define PGMC_CPC1_MIF1 ((PGMC_MIF_Type *)PGMC_CPC1_MIF1_BASE)
66544#define PGMC_MIF_BASE_ADDRS { PGMC_CPC0_MIF0_BASE, PGMC_CPC0_MIF1_BASE, PGMC_CPC1_MIF0_BASE, PGMC_CPC1_MIF1_BASE }
66546#define PGMC_MIF_BASE_PTRS { PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 }
66547 /* end of group PGMC_MIF_Peripheral_Access_Layer */
66551
66552
66553/* ----------------------------------------------------------------------------
66554 -- PGMC_PPC Peripheral Access Layer
66555 ---------------------------------------------------------------------------- */
66556
66563typedef struct {
66564 uint8_t RESERVED_0[4];
66565 __IO uint32_t PPC_AUTHEN_CTRL;
66566 uint8_t RESERVED_1[8];
66567 __IO uint32_t PPC_MODE;
66568 __IO uint32_t PPC_STBY_CM_CTRL;
66569 __IO uint32_t PPC_STBY_SP_CTRL;
66571
66572/* ----------------------------------------------------------------------------
66573 -- PGMC_PPC Register Masks
66574 ---------------------------------------------------------------------------- */
66575
66584#define PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK (0x1U)
66585#define PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT (0U)
66588#define PGMC_PPC_PPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK)
66589
66590#define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
66591#define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
66594#define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK)
66595
66596#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
66597#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
66600#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
66601
66602#define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
66603#define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
66606#define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK)
66607
66608#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
66609#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
66612#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK)
66613
66614#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
66615#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
66618#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK)
66624#define PGMC_PPC_PPC_MODE_CTRL_MODE_MASK (0x3U)
66625#define PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT (0U)
66632#define PGMC_PPC_PPC_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT)) & PGMC_PPC_PPC_MODE_CTRL_MODE_MASK)
66633
66634#define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK (0x30U)
66635#define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT (4U)
66642#define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK)
66648#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK (0x2U)
66649#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT (1U)
66652#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK)
66653
66654#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK (0x4U)
66655#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT (2U)
66658#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK)
66659
66660#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK (0x8U)
66661#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT (3U)
66664#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK)
66665
66666#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK (0x100U)
66667#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT (8U)
66670#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK)
66671
66672#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK (0x200U)
66673#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT (9U)
66676#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK)
66682#define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK (0xFFFFU)
66683#define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT (0U)
66686#define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK)
66687
66688#define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK (0xFFFF0000U)
66689#define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT (16U)
66693#define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK) /* end of group PGMC_PPC_Register_Masks */
66700
66701
66702/* PGMC_PPC - Peripheral instance base addresses */
66704#define PGMC_PPC0_BASE (0x40C8B000u)
66706#define PGMC_PPC0 ((PGMC_PPC_Type *)PGMC_PPC0_BASE)
66708#define PGMC_PPC_BASE_ADDRS { PGMC_PPC0_BASE }
66710#define PGMC_PPC_BASE_PTRS { PGMC_PPC0 }
66711 /* end of group PGMC_PPC_Peripheral_Access_Layer */
66715
66716
66717/* ----------------------------------------------------------------------------
66718 -- PHY_LDO Peripheral Access Layer
66719 ---------------------------------------------------------------------------- */
66720
66727typedef struct {
66728 struct { /* offset: 0x0 */
66729 __IO uint32_t RW;
66730 __IO uint32_t SET;
66731 __IO uint32_t CLR;
66732 __IO uint32_t TOG;
66733 } CTRL0;
66734 uint8_t RESERVED_0[64];
66735 struct { /* offset: 0x50 */
66736 __I uint32_t RW;
66737 __I uint32_t SET;
66738 __I uint32_t CLR;
66739 __I uint32_t TOG;
66740 } STAT0;
66741} PHY_LDO_Type;
66742
66743/* ----------------------------------------------------------------------------
66744 -- PHY_LDO Register Masks
66745 ---------------------------------------------------------------------------- */
66746
66755#define PHY_LDO_CTRL0_LINREG_EN_MASK (0x1U)
66756#define PHY_LDO_CTRL0_LINREG_EN_SHIFT (0U)
66759#define PHY_LDO_CTRL0_LINREG_EN(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_EN_MASK)
66760
66761#define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK (0x2U)
66762#define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT (1U)
66767#define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT)) & PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK)
66768
66769#define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK (0x4U)
66770#define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT (2U)
66773#define PHY_LDO_CTRL0_LINREG_ILIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK)
66774
66775#define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK (0x1F0U)
66776#define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT (4U)
66782#define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT)) & PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK)
66783
66784#define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK (0x8000U)
66785#define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT (15U)
66788#define PHY_LDO_CTRL0_LINREG_PHY_ISO_B(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT)) & PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK)
66794#define PHY_LDO_STAT0_LINREG_STAT_MASK (0xFU)
66795#define PHY_LDO_STAT0_LINREG_STAT_SHIFT (0U)
66798#define PHY_LDO_STAT0_LINREG_STAT(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & PHY_LDO_STAT0_LINREG_STAT_MASK) /* end of group PHY_LDO_Register_Masks */
66805
66806
66807/* PHY_LDO - Peripheral instance base addresses */
66809#define PHY_LDO_BASE (0u)
66811#define PHY_LDO ((PHY_LDO_Type *)PHY_LDO_BASE)
66813#define PHY_LDO_BASE_ADDRS { PHY_LDO_BASE }
66815#define PHY_LDO_BASE_PTRS { PHY_LDO }
66816 /* end of group PHY_LDO_Peripheral_Access_Layer */
66820
66821
66822/* ----------------------------------------------------------------------------
66823 -- PIT Peripheral Access Layer
66824 ---------------------------------------------------------------------------- */
66825
66832typedef struct {
66833 __IO uint32_t MCR;
66834 uint8_t RESERVED_0[220];
66835 __I uint32_t LTMR64H;
66836 __I uint32_t LTMR64L;
66837 uint8_t RESERVED_1[24];
66838 struct { /* offset: 0x100, array step: 0x10 */
66839 __IO uint32_t LDVAL;
66840 __I uint32_t CVAL;
66841 __IO uint32_t TCTRL;
66842 __IO uint32_t TFLG;
66843 } CHANNEL[4];
66844} PIT_Type;
66845
66846/* ----------------------------------------------------------------------------
66847 -- PIT Register Masks
66848 ---------------------------------------------------------------------------- */
66849
66858#define PIT_MCR_FRZ_MASK (0x1U)
66859#define PIT_MCR_FRZ_SHIFT (0U)
66864#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
66865
66866#define PIT_MCR_MDIS_MASK (0x2U)
66867#define PIT_MCR_MDIS_SHIFT (1U)
66872#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
66878#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
66879#define PIT_LTMR64H_LTH_SHIFT (0U)
66882#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
66888#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
66889#define PIT_LTMR64L_LTL_SHIFT (0U)
66892#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
66898#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
66899#define PIT_LDVAL_TSV_SHIFT (0U)
66902#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
66905/* The count of PIT_LDVAL */
66906#define PIT_LDVAL_COUNT (4U)
66907
66911#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
66912#define PIT_CVAL_TVL_SHIFT (0U)
66915#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
66918/* The count of PIT_CVAL */
66919#define PIT_CVAL_COUNT (4U)
66920
66924#define PIT_TCTRL_TEN_MASK (0x1U)
66925#define PIT_TCTRL_TEN_SHIFT (0U)
66930#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
66931
66932#define PIT_TCTRL_TIE_MASK (0x2U)
66933#define PIT_TCTRL_TIE_SHIFT (1U)
66938#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
66939
66940#define PIT_TCTRL_CHN_MASK (0x4U)
66941#define PIT_TCTRL_CHN_SHIFT (2U)
66946#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
66949/* The count of PIT_TCTRL */
66950#define PIT_TCTRL_COUNT (4U)
66951
66955#define PIT_TFLG_TIF_MASK (0x1U)
66956#define PIT_TFLG_TIF_SHIFT (0U)
66961#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
66964/* The count of PIT_TFLG */
66965#define PIT_TFLG_COUNT (4U)
66966
66967 /* end of group PIT_Register_Masks */
66971
66972
66973/* PIT - Peripheral instance base addresses */
66975#define PIT1_BASE (0x400D8000u)
66977#define PIT1 ((PIT_Type *)PIT1_BASE)
66979#define PIT2_BASE (0x40CB0000u)
66981#define PIT2 ((PIT_Type *)PIT2_BASE)
66983#define PIT_BASE_ADDRS { 0u, PIT1_BASE, PIT2_BASE }
66985#define PIT_BASE_PTRS { (PIT_Type *)0u, PIT1, PIT2 }
66987#define PIT_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PIT1_IRQn, PIT1_IRQn, PIT1_IRQn, PIT1_IRQn }, { PIT2_IRQn, PIT2_IRQn, PIT2_IRQn, PIT2_IRQn } }
66988 /* end of group PIT_Peripheral_Access_Layer */
66992
66993
66994/* ----------------------------------------------------------------------------
66995 -- PUF Peripheral Access Layer
66996 ---------------------------------------------------------------------------- */
66997
67004typedef struct {
67005 __IO uint32_t CTRL;
67006 __IO uint32_t KEYINDEX;
67007 __IO uint32_t KEYSIZE;
67008 uint8_t RESERVED_0[20];
67009 __I uint32_t STAT;
67010 uint8_t RESERVED_1[4];
67011 __I uint32_t ALLOW;
67012 uint8_t RESERVED_2[20];
67013 __O uint32_t KEYINPUT;
67014 __O uint32_t CODEINPUT;
67015 __I uint32_t CODEOUTPUT;
67016 uint8_t RESERVED_3[20];
67017 __I uint32_t KEYOUTINDEX;
67018 __I uint32_t KEYOUTPUT;
67019 uint8_t RESERVED_4[116];
67020 __IO uint32_t IFSTAT;
67021 uint8_t RESERVED_5[28];
67022 __I uint32_t VERSION;
67023 __IO uint32_t INTEN;
67024 __IO uint32_t INTSTAT;
67025 __IO uint32_t PWRCTRL;
67026 __IO uint32_t CFG;
67027 uint8_t RESERVED_6[240];
67028 __IO uint32_t KEYLOCK;
67029 __IO uint32_t KEYENABLE;
67030 __IO uint32_t KEYRESET;
67031 __IO uint32_t IDXBLK;
67032 __IO uint32_t IDXBLK_DP;
67033 __IO uint32_t KEYMASK[2];
67034 uint8_t RESERVED_7[56];
67035 __I uint32_t IDXBLK_STATUS;
67036 __I uint32_t IDXBLK_SHIFT;
67037} PUF_Type;
67038
67039/* ----------------------------------------------------------------------------
67040 -- PUF Register Masks
67041 ---------------------------------------------------------------------------- */
67042
67051#define PUF_CTRL_ZEROIZE_MASK (0x1U)
67052#define PUF_CTRL_ZEROIZE_SHIFT (0U)
67057#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK)
67058
67059#define PUF_CTRL_ENROLL_MASK (0x2U)
67060#define PUF_CTRL_ENROLL_SHIFT (1U)
67065#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK)
67066
67067#define PUF_CTRL_START_MASK (0x4U)
67068#define PUF_CTRL_START_SHIFT (2U)
67073#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK)
67074
67075#define PUF_CTRL_GENERATEKEY_MASK (0x8U)
67076#define PUF_CTRL_GENERATEKEY_SHIFT (3U)
67081#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK)
67082
67083#define PUF_CTRL_SETKEY_MASK (0x10U)
67084#define PUF_CTRL_SETKEY_SHIFT (4U)
67089#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK)
67090
67091#define PUF_CTRL_GETKEY_MASK (0x40U)
67092#define PUF_CTRL_GETKEY_SHIFT (6U)
67097#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK)
67103#define PUF_KEYINDEX_KEYIDX_MASK (0xFU)
67104#define PUF_KEYINDEX_KEYIDX_SHIFT (0U)
67123#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK)
67129#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU)
67130#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U)
67197#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK)
67203#define PUF_STAT_BUSY_MASK (0x1U)
67204#define PUF_STAT_BUSY_SHIFT (0U)
67209#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK)
67210
67211#define PUF_STAT_SUCCESS_MASK (0x2U)
67212#define PUF_STAT_SUCCESS_SHIFT (1U)
67217#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK)
67218
67219#define PUF_STAT_ERROR_MASK (0x4U)
67220#define PUF_STAT_ERROR_SHIFT (2U)
67225#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK)
67226
67227#define PUF_STAT_KEYINREQ_MASK (0x10U)
67228#define PUF_STAT_KEYINREQ_SHIFT (4U)
67233#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK)
67234
67235#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U)
67236#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U)
67241#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK)
67242
67243#define PUF_STAT_CODEINREQ_MASK (0x40U)
67244#define PUF_STAT_CODEINREQ_SHIFT (6U)
67249#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK)
67250
67251#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U)
67252#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U)
67257#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK)
67263#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U)
67264#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U)
67269#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK)
67270
67271#define PUF_ALLOW_ALLOWSTART_MASK (0x2U)
67272#define PUF_ALLOW_ALLOWSTART_SHIFT (1U)
67277#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK)
67278
67279#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U)
67280#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U)
67285#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK)
67286
67287#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U)
67288#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U)
67293#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK)
67299#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU)
67300#define PUF_KEYINPUT_KEYIN_SHIFT (0U)
67303#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK)
67309#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU)
67310#define PUF_CODEINPUT_CODEIN_SHIFT (0U)
67313#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK)
67319#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU)
67320#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U)
67323#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK)
67329#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFFFFFFFFU)
67330#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U)
67333#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK)
67339#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU)
67340#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U)
67343#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK)
67349#define PUF_IFSTAT_ERROR_MASK (0x1U)
67350#define PUF_IFSTAT_ERROR_SHIFT (0U)
67355#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK)
67361#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU)
67362#define PUF_VERSION_VERSION_SHIFT (0U)
67365#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK)
67371#define PUF_INTEN_READYEN_MASK (0x1U)
67372#define PUF_INTEN_READYEN_SHIFT (0U)
67377#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK)
67378
67379#define PUF_INTEN_SUCCESSEN_MASK (0x2U)
67380#define PUF_INTEN_SUCCESSEN_SHIFT (1U)
67385#define PUF_INTEN_SUCCESSEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESSEN_SHIFT)) & PUF_INTEN_SUCCESSEN_MASK)
67386
67387#define PUF_INTEN_ERROREN_MASK (0x4U)
67388#define PUF_INTEN_ERROREN_SHIFT (2U)
67393#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK)
67394
67395#define PUF_INTEN_KEYINREQEN_MASK (0x10U)
67396#define PUF_INTEN_KEYINREQEN_SHIFT (4U)
67401#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK)
67402
67403#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U)
67404#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U)
67409#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK)
67410
67411#define PUF_INTEN_CODEINREQEN_MASK (0x40U)
67412#define PUF_INTEN_CODEINREQEN_SHIFT (6U)
67417#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK)
67418
67419#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U)
67420#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U)
67425#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK)
67431#define PUF_INTSTAT_READY_MASK (0x1U)
67432#define PUF_INTSTAT_READY_SHIFT (0U)
67437#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK)
67438
67439#define PUF_INTSTAT_SUCCESS_MASK (0x2U)
67440#define PUF_INTSTAT_SUCCESS_SHIFT (1U)
67445#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK)
67446
67447#define PUF_INTSTAT_ERROR_MASK (0x4U)
67448#define PUF_INTSTAT_ERROR_SHIFT (2U)
67453#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK)
67454
67455#define PUF_INTSTAT_KEYINREQ_MASK (0x10U)
67456#define PUF_INTSTAT_KEYINREQ_SHIFT (4U)
67461#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK)
67462
67463#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U)
67464#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U)
67469#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK)
67470
67471#define PUF_INTSTAT_CODEINREQ_MASK (0x40U)
67472#define PUF_INTSTAT_CODEINREQ_SHIFT (6U)
67477#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK)
67478
67479#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U)
67480#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U)
67485#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK)
67491#define PUF_PWRCTRL_RAM_ON_MASK (0x1U)
67492#define PUF_PWRCTRL_RAM_ON_SHIFT (0U)
67497#define PUF_PWRCTRL_RAM_ON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_ON_SHIFT)) & PUF_PWRCTRL_RAM_ON_MASK)
67498
67499#define PUF_PWRCTRL_CK_DIS_MASK (0x4U)
67500#define PUF_PWRCTRL_CK_DIS_SHIFT (2U)
67505#define PUF_PWRCTRL_CK_DIS(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_CK_DIS_SHIFT)) & PUF_PWRCTRL_CK_DIS_MASK)
67506
67507#define PUF_PWRCTRL_RAM_INITN_MASK (0x8U)
67508#define PUF_PWRCTRL_RAM_INITN_SHIFT (3U)
67513#define PUF_PWRCTRL_RAM_INITN(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_INITN_SHIFT)) & PUF_PWRCTRL_RAM_INITN_MASK)
67514
67515#define PUF_PWRCTRL_RAM_PSW_MASK (0xF0U)
67516#define PUF_PWRCTRL_RAM_PSW_SHIFT (4U)
67519#define PUF_PWRCTRL_RAM_PSW(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_PSW_SHIFT)) & PUF_PWRCTRL_RAM_PSW_MASK)
67525#define PUF_CFG_PUF_BLOCK_SET_KEY_MASK (0x1U)
67526#define PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT (0U)
67531#define PUF_CFG_PUF_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT)) & PUF_CFG_PUF_BLOCK_SET_KEY_MASK)
67532
67533#define PUF_CFG_PUF_BLOCK_ENROLL_MASK (0x2U)
67534#define PUF_CFG_PUF_BLOCK_ENROLL_SHIFT (1U)
67539#define PUF_CFG_PUF_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_ENROLL_SHIFT)) & PUF_CFG_PUF_BLOCK_ENROLL_MASK)
67545#define PUF_KEYLOCK_LOCK0_MASK (0x3U)
67546#define PUF_KEYLOCK_LOCK0_SHIFT (0U)
67553#define PUF_KEYLOCK_LOCK0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK0_SHIFT)) & PUF_KEYLOCK_LOCK0_MASK)
67554
67555#define PUF_KEYLOCK_LOCK1_MASK (0xCU)
67556#define PUF_KEYLOCK_LOCK1_SHIFT (2U)
67563#define PUF_KEYLOCK_LOCK1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK1_SHIFT)) & PUF_KEYLOCK_LOCK1_MASK)
67569#define PUF_KEYENABLE_ENABLE0_MASK (0x3U)
67570#define PUF_KEYENABLE_ENABLE0_SHIFT (0U)
67577#define PUF_KEYENABLE_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE0_SHIFT)) & PUF_KEYENABLE_ENABLE0_MASK)
67578
67579#define PUF_KEYENABLE_ENABLE1_MASK (0xCU)
67580#define PUF_KEYENABLE_ENABLE1_SHIFT (2U)
67587#define PUF_KEYENABLE_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE1_SHIFT)) & PUF_KEYENABLE_ENABLE1_MASK)
67593#define PUF_KEYRESET_RESET0_MASK (0x3U)
67594#define PUF_KEYRESET_RESET0_SHIFT (0U)
67601#define PUF_KEYRESET_RESET0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET0_SHIFT)) & PUF_KEYRESET_RESET0_MASK)
67602
67603#define PUF_KEYRESET_RESET1_MASK (0xCU)
67604#define PUF_KEYRESET_RESET1_SHIFT (2U)
67611#define PUF_KEYRESET_RESET1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET1_SHIFT)) & PUF_KEYRESET_RESET1_MASK)
67617#define PUF_IDXBLK_IDXBLK0_MASK (0x3U)
67618#define PUF_IDXBLK_IDXBLK0_SHIFT (0U)
67621#define PUF_IDXBLK_IDXBLK0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK0_SHIFT)) & PUF_IDXBLK_IDXBLK0_MASK)
67622
67623#define PUF_IDXBLK_IDXBLK1_MASK (0xCU)
67624#define PUF_IDXBLK_IDXBLK1_SHIFT (2U)
67627#define PUF_IDXBLK_IDXBLK1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK1_SHIFT)) & PUF_IDXBLK_IDXBLK1_MASK)
67628
67629#define PUF_IDXBLK_IDXBLK2_MASK (0x30U)
67630#define PUF_IDXBLK_IDXBLK2_SHIFT (4U)
67633#define PUF_IDXBLK_IDXBLK2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK2_SHIFT)) & PUF_IDXBLK_IDXBLK2_MASK)
67634
67635#define PUF_IDXBLK_IDXBLK3_MASK (0xC0U)
67636#define PUF_IDXBLK_IDXBLK3_SHIFT (6U)
67639#define PUF_IDXBLK_IDXBLK3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK3_SHIFT)) & PUF_IDXBLK_IDXBLK3_MASK)
67640
67641#define PUF_IDXBLK_IDXBLK4_MASK (0x300U)
67642#define PUF_IDXBLK_IDXBLK4_SHIFT (8U)
67645#define PUF_IDXBLK_IDXBLK4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK4_SHIFT)) & PUF_IDXBLK_IDXBLK4_MASK)
67646
67647#define PUF_IDXBLK_IDXBLK5_MASK (0xC00U)
67648#define PUF_IDXBLK_IDXBLK5_SHIFT (10U)
67651#define PUF_IDXBLK_IDXBLK5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK5_SHIFT)) & PUF_IDXBLK_IDXBLK5_MASK)
67652
67653#define PUF_IDXBLK_IDXBLK6_MASK (0x3000U)
67654#define PUF_IDXBLK_IDXBLK6_SHIFT (12U)
67657#define PUF_IDXBLK_IDXBLK6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK6_SHIFT)) & PUF_IDXBLK_IDXBLK6_MASK)
67658
67659#define PUF_IDXBLK_IDXBLK7_MASK (0xC000U)
67660#define PUF_IDXBLK_IDXBLK7_SHIFT (14U)
67663#define PUF_IDXBLK_IDXBLK7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK7_SHIFT)) & PUF_IDXBLK_IDXBLK7_MASK)
67664
67665#define PUF_IDXBLK_IDXBLK8_MASK (0x30000U)
67666#define PUF_IDXBLK_IDXBLK8_SHIFT (16U)
67669#define PUF_IDXBLK_IDXBLK8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK8_SHIFT)) & PUF_IDXBLK_IDXBLK8_MASK)
67670
67671#define PUF_IDXBLK_IDXBLK9_MASK (0xC0000U)
67672#define PUF_IDXBLK_IDXBLK9_SHIFT (18U)
67675#define PUF_IDXBLK_IDXBLK9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK9_SHIFT)) & PUF_IDXBLK_IDXBLK9_MASK)
67676
67677#define PUF_IDXBLK_IDXBLK10_MASK (0x300000U)
67678#define PUF_IDXBLK_IDXBLK10_SHIFT (20U)
67681#define PUF_IDXBLK_IDXBLK10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK10_SHIFT)) & PUF_IDXBLK_IDXBLK10_MASK)
67682
67683#define PUF_IDXBLK_IDXBLK11_MASK (0xC00000U)
67684#define PUF_IDXBLK_IDXBLK11_SHIFT (22U)
67687#define PUF_IDXBLK_IDXBLK11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK11_SHIFT)) & PUF_IDXBLK_IDXBLK11_MASK)
67688
67689#define PUF_IDXBLK_IDXBLK12_MASK (0x3000000U)
67690#define PUF_IDXBLK_IDXBLK12_SHIFT (24U)
67693#define PUF_IDXBLK_IDXBLK12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK12_SHIFT)) & PUF_IDXBLK_IDXBLK12_MASK)
67694
67695#define PUF_IDXBLK_IDXBLK13_MASK (0xC000000U)
67696#define PUF_IDXBLK_IDXBLK13_SHIFT (26U)
67699#define PUF_IDXBLK_IDXBLK13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK13_SHIFT)) & PUF_IDXBLK_IDXBLK13_MASK)
67700
67701#define PUF_IDXBLK_IDXBLK14_MASK (0x30000000U)
67702#define PUF_IDXBLK_IDXBLK14_SHIFT (28U)
67705#define PUF_IDXBLK_IDXBLK14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK14_SHIFT)) & PUF_IDXBLK_IDXBLK14_MASK)
67706
67707#define PUF_IDXBLK_IDXBLK15_MASK (0xC0000000U)
67708#define PUF_IDXBLK_IDXBLK15_SHIFT (30U)
67711#define PUF_IDXBLK_IDXBLK15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK15_SHIFT)) & PUF_IDXBLK_IDXBLK15_MASK)
67717#define PUF_IDXBLK_DP_IDXBLK_DP0_MASK (0x3U)
67718#define PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT (0U)
67721#define PUF_IDXBLK_DP_IDXBLK_DP0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP0_MASK)
67722
67723#define PUF_IDXBLK_DP_IDXBLK_DP1_MASK (0xCU)
67724#define PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT (2U)
67727#define PUF_IDXBLK_DP_IDXBLK_DP1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP1_MASK)
67728
67729#define PUF_IDXBLK_DP_IDXBLK_DP2_MASK (0x30U)
67730#define PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT (4U)
67733#define PUF_IDXBLK_DP_IDXBLK_DP2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP2_MASK)
67734
67735#define PUF_IDXBLK_DP_IDXBLK_DP3_MASK (0xC0U)
67736#define PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT (6U)
67739#define PUF_IDXBLK_DP_IDXBLK_DP3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP3_MASK)
67740
67741#define PUF_IDXBLK_DP_IDXBLK_DP4_MASK (0x300U)
67742#define PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT (8U)
67745#define PUF_IDXBLK_DP_IDXBLK_DP4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP4_MASK)
67746
67747#define PUF_IDXBLK_DP_IDXBLK_DP5_MASK (0xC00U)
67748#define PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT (10U)
67751#define PUF_IDXBLK_DP_IDXBLK_DP5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP5_MASK)
67752
67753#define PUF_IDXBLK_DP_IDXBLK_DP6_MASK (0x3000U)
67754#define PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT (12U)
67757#define PUF_IDXBLK_DP_IDXBLK_DP6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP6_MASK)
67758
67759#define PUF_IDXBLK_DP_IDXBLK_DP7_MASK (0xC000U)
67760#define PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT (14U)
67763#define PUF_IDXBLK_DP_IDXBLK_DP7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP7_MASK)
67764
67765#define PUF_IDXBLK_DP_IDXBLK_DP8_MASK (0x30000U)
67766#define PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT (16U)
67769#define PUF_IDXBLK_DP_IDXBLK_DP8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP8_MASK)
67770
67771#define PUF_IDXBLK_DP_IDXBLK_DP9_MASK (0xC0000U)
67772#define PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT (18U)
67775#define PUF_IDXBLK_DP_IDXBLK_DP9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP9_MASK)
67776
67777#define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U)
67778#define PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT (20U)
67781#define PUF_IDXBLK_DP_IDXBLK_DP10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
67782
67783#define PUF_IDXBLK_DP_IDXBLK_DP11_MASK (0xC00000U)
67784#define PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT (22U)
67787#define PUF_IDXBLK_DP_IDXBLK_DP11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP11_MASK)
67788
67789#define PUF_IDXBLK_DP_IDXBLK_DP12_MASK (0x3000000U)
67790#define PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT (24U)
67793#define PUF_IDXBLK_DP_IDXBLK_DP12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP12_MASK)
67794
67795#define PUF_IDXBLK_DP_IDXBLK_DP13_MASK (0xC000000U)
67796#define PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT (26U)
67799#define PUF_IDXBLK_DP_IDXBLK_DP13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP13_MASK)
67800
67801#define PUF_IDXBLK_DP_IDXBLK_DP14_MASK (0x30000000U)
67802#define PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT (28U)
67805#define PUF_IDXBLK_DP_IDXBLK_DP14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP14_MASK)
67806
67807#define PUF_IDXBLK_DP_IDXBLK_DP15_MASK (0xC0000000U)
67808#define PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT (30U)
67811#define PUF_IDXBLK_DP_IDXBLK_DP15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP15_MASK)
67817#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU)
67818#define PUF_KEYMASK_KEYMASK_SHIFT (0U)
67821#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK)
67824/* The count of PUF_KEYMASK */
67825#define PUF_KEYMASK_COUNT (2U)
67826
67830#define PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK (0x3U)
67831#define PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT (0U)
67834#define PUF_IDXBLK_STATUS_IDXBLK_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK)
67835
67836#define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU)
67837#define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT (2U)
67840#define PUF_IDXBLK_STATUS_IDXBLK_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
67841
67842#define PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK (0x30U)
67843#define PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT (4U)
67846#define PUF_IDXBLK_STATUS_IDXBLK_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK)
67847
67848#define PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK (0xC0U)
67849#define PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT (6U)
67852#define PUF_IDXBLK_STATUS_IDXBLK_STATUS3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK)
67853
67854#define PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK (0x300U)
67855#define PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT (8U)
67858#define PUF_IDXBLK_STATUS_IDXBLK_STATUS4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK)
67859
67860#define PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK (0xC00U)
67861#define PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT (10U)
67864#define PUF_IDXBLK_STATUS_IDXBLK_STATUS5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK)
67865
67866#define PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK (0x3000U)
67867#define PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT (12U)
67870#define PUF_IDXBLK_STATUS_IDXBLK_STATUS6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK)
67871
67872#define PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK (0xC000U)
67873#define PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT (14U)
67876#define PUF_IDXBLK_STATUS_IDXBLK_STATUS7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK)
67877
67878#define PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK (0x30000U)
67879#define PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT (16U)
67882#define PUF_IDXBLK_STATUS_IDXBLK_STATUS8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK)
67883
67884#define PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK (0xC0000U)
67885#define PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT (18U)
67888#define PUF_IDXBLK_STATUS_IDXBLK_STATUS9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK)
67889
67890#define PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK (0x300000U)
67891#define PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT (20U)
67894#define PUF_IDXBLK_STATUS_IDXBLK_STATUS10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK)
67895
67896#define PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK (0xC00000U)
67897#define PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT (22U)
67900#define PUF_IDXBLK_STATUS_IDXBLK_STATUS11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK)
67901
67902#define PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK (0x3000000U)
67903#define PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT (24U)
67906#define PUF_IDXBLK_STATUS_IDXBLK_STATUS12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK)
67907
67908#define PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK (0xC000000U)
67909#define PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT (26U)
67912#define PUF_IDXBLK_STATUS_IDXBLK_STATUS13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK)
67913
67914#define PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK (0x30000000U)
67915#define PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT (28U)
67918#define PUF_IDXBLK_STATUS_IDXBLK_STATUS14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK)
67919
67920#define PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK (0xC0000000U)
67921#define PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT (30U)
67924#define PUF_IDXBLK_STATUS_IDXBLK_STATUS15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK)
67930#define PUF_IDXBLK_SHIFT_IND_KEY0_MASK (0xFU)
67931#define PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT (0U)
67934#define PUF_IDXBLK_SHIFT_IND_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY0_MASK)
67935
67936#define PUF_IDXBLK_SHIFT_IND_KEY1_MASK (0xF0U)
67937#define PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT (4U)
67940#define PUF_IDXBLK_SHIFT_IND_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY1_MASK) /* end of group PUF_Register_Masks */
67947
67948
67949/* PUF - Peripheral instance base addresses */
67951#define KEY_MANAGER__PUF_BASE (0x40C82000u)
67953#define KEY_MANAGER__PUF ((PUF_Type *)KEY_MANAGER__PUF_BASE)
67955#define PUF_BASE_ADDRS { KEY_MANAGER__PUF_BASE }
67957#define PUF_BASE_PTRS { KEY_MANAGER__PUF }
67958 /* end of group PUF_Peripheral_Access_Layer */
67962
67963
67964/* ----------------------------------------------------------------------------
67965 -- PWM Peripheral Access Layer
67966 ---------------------------------------------------------------------------- */
67967
67974typedef struct {
67975 struct { /* offset: 0x0, array step: 0x60 */
67976 __I uint16_t CNT;
67977 __IO uint16_t INIT;
67978 __IO uint16_t CTRL2;
67979 __IO uint16_t CTRL;
67980 uint8_t RESERVED_0[2];
67981 __IO uint16_t VAL0;
67982 __IO uint16_t FRACVAL1;
67983 __IO uint16_t VAL1;
67984 __IO uint16_t FRACVAL2;
67985 __IO uint16_t VAL2;
67986 __IO uint16_t FRACVAL3;
67987 __IO uint16_t VAL3;
67988 __IO uint16_t FRACVAL4;
67989 __IO uint16_t VAL4;
67990 __IO uint16_t FRACVAL5;
67991 __IO uint16_t VAL5;
67992 __IO uint16_t FRCTRL;
67993 __IO uint16_t OCTRL;
67994 __IO uint16_t STS;
67995 __IO uint16_t INTEN;
67996 __IO uint16_t DMAEN;
67997 __IO uint16_t TCTRL;
67998 __IO uint16_t DISMAP[1];
67999 uint8_t RESERVED_1[2];
68000 __IO uint16_t DTCNT0;
68001 __IO uint16_t DTCNT1;
68002 __IO uint16_t CAPTCTRLA;
68003 __IO uint16_t CAPTCOMPA;
68004 __IO uint16_t CAPTCTRLB;
68005 __IO uint16_t CAPTCOMPB;
68006 __IO uint16_t CAPTCTRLX;
68007 __IO uint16_t CAPTCOMPX;
68008 __I uint16_t CVAL0;
68009 __I uint16_t CVAL0CYC;
68010 __I uint16_t CVAL1;
68011 __I uint16_t CVAL1CYC;
68012 __I uint16_t CVAL2;
68013 __I uint16_t CVAL2CYC;
68014 __I uint16_t CVAL3;
68015 __I uint16_t CVAL3CYC;
68016 __I uint16_t CVAL4;
68017 __I uint16_t CVAL4CYC;
68018 __I uint16_t CVAL5;
68019 __I uint16_t CVAL5CYC;
68020 uint8_t RESERVED_2[8];
68021 } SM[4];
68022 __IO uint16_t OUTEN;
68023 __IO uint16_t MASK;
68024 __IO uint16_t SWCOUT;
68025 __IO uint16_t DTSRCSEL;
68026 __IO uint16_t MCTRL;
68027 __IO uint16_t MCTRL2;
68028 __IO uint16_t FCTRL;
68029 __IO uint16_t FSTS;
68030 __IO uint16_t FFILT;
68031 __IO uint16_t FTST;
68032 __IO uint16_t FCTRL2;
68033} PWM_Type;
68034
68035/* ----------------------------------------------------------------------------
68036 -- PWM Register Masks
68037 ---------------------------------------------------------------------------- */
68038
68047#define PWM_CNT_CNT_MASK (0xFFFFU)
68048#define PWM_CNT_CNT_SHIFT (0U)
68051#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
68054/* The count of PWM_CNT */
68055#define PWM_CNT_COUNT (4U)
68056
68060#define PWM_INIT_INIT_MASK (0xFFFFU)
68061#define PWM_INIT_INIT_SHIFT (0U)
68064#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
68067/* The count of PWM_INIT */
68068#define PWM_INIT_COUNT (4U)
68069
68073#define PWM_CTRL2_CLK_SEL_MASK (0x3U)
68074#define PWM_CTRL2_CLK_SEL_SHIFT (0U)
68082#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
68083
68084#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U)
68085#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U)
68091#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
68092
68093#define PWM_CTRL2_FORCE_SEL_MASK (0x38U)
68094#define PWM_CTRL2_FORCE_SEL_SHIFT (3U)
68108#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
68109
68110#define PWM_CTRL2_FORCE_MASK (0x40U)
68111#define PWM_CTRL2_FORCE_SHIFT (6U)
68114#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
68115
68116#define PWM_CTRL2_FRCEN_MASK (0x80U)
68117#define PWM_CTRL2_FRCEN_SHIFT (7U)
68122#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
68123
68124#define PWM_CTRL2_INIT_SEL_MASK (0x300U)
68125#define PWM_CTRL2_INIT_SEL_SHIFT (8U)
68135#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
68136
68137#define PWM_CTRL2_PWMX_INIT_MASK (0x400U)
68138#define PWM_CTRL2_PWMX_INIT_SHIFT (10U)
68141#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
68142
68143#define PWM_CTRL2_PWM45_INIT_MASK (0x800U)
68144#define PWM_CTRL2_PWM45_INIT_SHIFT (11U)
68147#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
68148
68149#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U)
68150#define PWM_CTRL2_PWM23_INIT_SHIFT (12U)
68153#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
68154
68155#define PWM_CTRL2_INDEP_MASK (0x2000U)
68156#define PWM_CTRL2_INDEP_SHIFT (13U)
68161#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
68162
68163#define PWM_CTRL2_WAITEN_MASK (0x4000U)
68164#define PWM_CTRL2_WAITEN_SHIFT (14U)
68167#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
68168
68169#define PWM_CTRL2_DBGEN_MASK (0x8000U)
68170#define PWM_CTRL2_DBGEN_SHIFT (15U)
68173#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
68176/* The count of PWM_CTRL2 */
68177#define PWM_CTRL2_COUNT (4U)
68178
68182#define PWM_CTRL_DBLEN_MASK (0x1U)
68183#define PWM_CTRL_DBLEN_SHIFT (0U)
68188#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
68189
68190#define PWM_CTRL_DBLX_MASK (0x2U)
68191#define PWM_CTRL_DBLX_SHIFT (1U)
68196#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
68197
68198#define PWM_CTRL_LDMOD_MASK (0x4U)
68199#define PWM_CTRL_LDMOD_SHIFT (2U)
68205#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
68206
68207#define PWM_CTRL_SPLIT_MASK (0x8U)
68208#define PWM_CTRL_SPLIT_SHIFT (3U)
68213#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
68214
68215#define PWM_CTRL_PRSC_MASK (0x70U)
68216#define PWM_CTRL_PRSC_SHIFT (4U)
68227#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
68228
68229#define PWM_CTRL_COMPMODE_MASK (0x80U)
68230#define PWM_CTRL_COMPMODE_SHIFT (7U)
68241#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
68242
68243#define PWM_CTRL_DT_MASK (0x300U)
68244#define PWM_CTRL_DT_SHIFT (8U)
68247#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
68248
68249#define PWM_CTRL_FULL_MASK (0x400U)
68250#define PWM_CTRL_FULL_SHIFT (10U)
68255#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
68256
68257#define PWM_CTRL_HALF_MASK (0x800U)
68258#define PWM_CTRL_HALF_SHIFT (11U)
68263#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
68264
68265#define PWM_CTRL_LDFQ_MASK (0xF000U)
68266#define PWM_CTRL_LDFQ_SHIFT (12U)
68285#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
68288/* The count of PWM_CTRL */
68289#define PWM_CTRL_COUNT (4U)
68290
68294#define PWM_VAL0_VAL0_MASK (0xFFFFU)
68295#define PWM_VAL0_VAL0_SHIFT (0U)
68298#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
68301/* The count of PWM_VAL0 */
68302#define PWM_VAL0_COUNT (4U)
68303
68307#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)
68308#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U)
68311#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
68314/* The count of PWM_FRACVAL1 */
68315#define PWM_FRACVAL1_COUNT (4U)
68316
68320#define PWM_VAL1_VAL1_MASK (0xFFFFU)
68321#define PWM_VAL1_VAL1_SHIFT (0U)
68324#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
68327/* The count of PWM_VAL1 */
68328#define PWM_VAL1_COUNT (4U)
68329
68333#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)
68334#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U)
68337#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
68340/* The count of PWM_FRACVAL2 */
68341#define PWM_FRACVAL2_COUNT (4U)
68342
68346#define PWM_VAL2_VAL2_MASK (0xFFFFU)
68347#define PWM_VAL2_VAL2_SHIFT (0U)
68350#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
68353/* The count of PWM_VAL2 */
68354#define PWM_VAL2_COUNT (4U)
68355
68359#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)
68360#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U)
68363#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
68366/* The count of PWM_FRACVAL3 */
68367#define PWM_FRACVAL3_COUNT (4U)
68368
68372#define PWM_VAL3_VAL3_MASK (0xFFFFU)
68373#define PWM_VAL3_VAL3_SHIFT (0U)
68376#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
68379/* The count of PWM_VAL3 */
68380#define PWM_VAL3_COUNT (4U)
68381
68385#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)
68386#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U)
68389#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
68392/* The count of PWM_FRACVAL4 */
68393#define PWM_FRACVAL4_COUNT (4U)
68394
68398#define PWM_VAL4_VAL4_MASK (0xFFFFU)
68399#define PWM_VAL4_VAL4_SHIFT (0U)
68402#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
68405/* The count of PWM_VAL4 */
68406#define PWM_VAL4_COUNT (4U)
68407
68411#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)
68412#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U)
68415#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
68418/* The count of PWM_FRACVAL5 */
68419#define PWM_FRACVAL5_COUNT (4U)
68420
68424#define PWM_VAL5_VAL5_MASK (0xFFFFU)
68425#define PWM_VAL5_VAL5_SHIFT (0U)
68428#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
68431/* The count of PWM_VAL5 */
68432#define PWM_VAL5_COUNT (4U)
68433
68437#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U)
68438#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U)
68443#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
68444
68445#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U)
68446#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U)
68451#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
68452
68453#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U)
68454#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U)
68459#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
68460
68461#define PWM_FRCTRL_TEST_MASK (0x8000U)
68462#define PWM_FRCTRL_TEST_SHIFT (15U)
68465#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
68468/* The count of PWM_FRCTRL */
68469#define PWM_FRCTRL_COUNT (4U)
68470
68474#define PWM_OCTRL_PWMXFS_MASK (0x3U)
68475#define PWM_OCTRL_PWMXFS_SHIFT (0U)
68481#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
68482
68483#define PWM_OCTRL_PWMBFS_MASK (0xCU)
68484#define PWM_OCTRL_PWMBFS_SHIFT (2U)
68490#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
68491
68492#define PWM_OCTRL_PWMAFS_MASK (0x30U)
68493#define PWM_OCTRL_PWMAFS_SHIFT (4U)
68499#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
68500
68501#define PWM_OCTRL_POLX_MASK (0x100U)
68502#define PWM_OCTRL_POLX_SHIFT (8U)
68507#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
68508
68509#define PWM_OCTRL_POLB_MASK (0x200U)
68510#define PWM_OCTRL_POLB_SHIFT (9U)
68515#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
68516
68517#define PWM_OCTRL_POLA_MASK (0x400U)
68518#define PWM_OCTRL_POLA_SHIFT (10U)
68523#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
68524
68525#define PWM_OCTRL_PWMX_IN_MASK (0x2000U)
68526#define PWM_OCTRL_PWMX_IN_SHIFT (13U)
68529#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
68530
68531#define PWM_OCTRL_PWMB_IN_MASK (0x4000U)
68532#define PWM_OCTRL_PWMB_IN_SHIFT (14U)
68535#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
68536
68537#define PWM_OCTRL_PWMA_IN_MASK (0x8000U)
68538#define PWM_OCTRL_PWMA_IN_SHIFT (15U)
68541#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
68544/* The count of PWM_OCTRL */
68545#define PWM_OCTRL_COUNT (4U)
68546
68550#define PWM_STS_CMPF_MASK (0x3FU)
68551#define PWM_STS_CMPF_SHIFT (0U)
68556#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
68557
68558#define PWM_STS_CFX0_MASK (0x40U)
68559#define PWM_STS_CFX0_SHIFT (6U)
68562#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
68563
68564#define PWM_STS_CFX1_MASK (0x80U)
68565#define PWM_STS_CFX1_SHIFT (7U)
68568#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
68569
68570#define PWM_STS_CFB0_MASK (0x100U)
68571#define PWM_STS_CFB0_SHIFT (8U)
68574#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
68575
68576#define PWM_STS_CFB1_MASK (0x200U)
68577#define PWM_STS_CFB1_SHIFT (9U)
68580#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
68581
68582#define PWM_STS_CFA0_MASK (0x400U)
68583#define PWM_STS_CFA0_SHIFT (10U)
68586#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
68587
68588#define PWM_STS_CFA1_MASK (0x800U)
68589#define PWM_STS_CFA1_SHIFT (11U)
68592#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
68593
68594#define PWM_STS_RF_MASK (0x1000U)
68595#define PWM_STS_RF_SHIFT (12U)
68600#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
68601
68602#define PWM_STS_REF_MASK (0x2000U)
68603#define PWM_STS_REF_SHIFT (13U)
68608#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
68609
68610#define PWM_STS_RUF_MASK (0x4000U)
68611#define PWM_STS_RUF_SHIFT (14U)
68616#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
68619/* The count of PWM_STS */
68620#define PWM_STS_COUNT (4U)
68621
68625#define PWM_INTEN_CMPIE_MASK (0x3FU)
68626#define PWM_INTEN_CMPIE_SHIFT (0U)
68631#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
68632
68633#define PWM_INTEN_CX0IE_MASK (0x40U)
68634#define PWM_INTEN_CX0IE_SHIFT (6U)
68639#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
68640
68641#define PWM_INTEN_CX1IE_MASK (0x80U)
68642#define PWM_INTEN_CX1IE_SHIFT (7U)
68647#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
68648
68649#define PWM_INTEN_CB0IE_MASK (0x100U)
68650#define PWM_INTEN_CB0IE_SHIFT (8U)
68655#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
68656
68657#define PWM_INTEN_CB1IE_MASK (0x200U)
68658#define PWM_INTEN_CB1IE_SHIFT (9U)
68663#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
68664
68665#define PWM_INTEN_CA0IE_MASK (0x400U)
68666#define PWM_INTEN_CA0IE_SHIFT (10U)
68671#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
68672
68673#define PWM_INTEN_CA1IE_MASK (0x800U)
68674#define PWM_INTEN_CA1IE_SHIFT (11U)
68679#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
68680
68681#define PWM_INTEN_RIE_MASK (0x1000U)
68682#define PWM_INTEN_RIE_SHIFT (12U)
68687#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
68688
68689#define PWM_INTEN_REIE_MASK (0x2000U)
68690#define PWM_INTEN_REIE_SHIFT (13U)
68695#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
68698/* The count of PWM_INTEN */
68699#define PWM_INTEN_COUNT (4U)
68700
68704#define PWM_DMAEN_CX0DE_MASK (0x1U)
68705#define PWM_DMAEN_CX0DE_SHIFT (0U)
68708#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
68709
68710#define PWM_DMAEN_CX1DE_MASK (0x2U)
68711#define PWM_DMAEN_CX1DE_SHIFT (1U)
68714#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
68715
68716#define PWM_DMAEN_CB0DE_MASK (0x4U)
68717#define PWM_DMAEN_CB0DE_SHIFT (2U)
68720#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
68721
68722#define PWM_DMAEN_CB1DE_MASK (0x8U)
68723#define PWM_DMAEN_CB1DE_SHIFT (3U)
68726#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
68727
68728#define PWM_DMAEN_CA0DE_MASK (0x10U)
68729#define PWM_DMAEN_CA0DE_SHIFT (4U)
68732#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
68733
68734#define PWM_DMAEN_CA1DE_MASK (0x20U)
68735#define PWM_DMAEN_CA1DE_SHIFT (5U)
68738#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
68739
68740#define PWM_DMAEN_CAPTDE_MASK (0xC0U)
68741#define PWM_DMAEN_CAPTDE_SHIFT (6U)
68750#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
68751
68752#define PWM_DMAEN_FAND_MASK (0x100U)
68753#define PWM_DMAEN_FAND_SHIFT (8U)
68758#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
68759
68760#define PWM_DMAEN_VALDE_MASK (0x200U)
68761#define PWM_DMAEN_VALDE_SHIFT (9U)
68766#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
68769/* The count of PWM_DMAEN */
68770#define PWM_DMAEN_COUNT (4U)
68771
68775#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)
68776#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)
68785#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
68786
68787#define PWM_TCTRL_TRGFRQ_MASK (0x1000U)
68788#define PWM_TCTRL_TRGFRQ_SHIFT (12U)
68794#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
68795
68796#define PWM_TCTRL_PWBOT1_MASK (0x4000U)
68797#define PWM_TCTRL_PWBOT1_SHIFT (14U)
68802#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
68803
68804#define PWM_TCTRL_PWAOT0_MASK (0x8000U)
68805#define PWM_TCTRL_PWAOT0_SHIFT (15U)
68810#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
68813/* The count of PWM_TCTRL */
68814#define PWM_TCTRL_COUNT (4U)
68815
68819#define PWM_DISMAP_DIS0A_MASK (0xFU)
68820#define PWM_DISMAP_DIS0A_SHIFT (0U)
68823#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
68824
68825#define PWM_DISMAP_DIS0B_MASK (0xF0U)
68826#define PWM_DISMAP_DIS0B_SHIFT (4U)
68829#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
68830
68831#define PWM_DISMAP_DIS0X_MASK (0xF00U)
68832#define PWM_DISMAP_DIS0X_SHIFT (8U)
68835#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
68838/* The count of PWM_DISMAP */
68839#define PWM_DISMAP_COUNT (4U)
68840
68841/* The count of PWM_DISMAP */
68842#define PWM_DISMAP_COUNT2 (1U)
68843
68847#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)
68848#define PWM_DTCNT0_DTCNT0_SHIFT (0U)
68851#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
68854/* The count of PWM_DTCNT0 */
68855#define PWM_DTCNT0_COUNT (4U)
68856
68860#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)
68861#define PWM_DTCNT1_DTCNT1_SHIFT (0U)
68864#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
68867/* The count of PWM_DTCNT1 */
68868#define PWM_DTCNT1_COUNT (4U)
68869
68873#define PWM_CAPTCTRLA_ARMA_MASK (0x1U)
68874#define PWM_CAPTCTRLA_ARMA_SHIFT (0U)
68879#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
68880
68881#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)
68882#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)
68887#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
68888
68889#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU)
68890#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U)
68897#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
68898
68899#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U)
68900#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U)
68907#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
68908
68909#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)
68910#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)
68915#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
68916
68917#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)
68918#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)
68923#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
68924
68925#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U)
68926#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U)
68929#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
68930
68931#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)
68932#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)
68935#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
68936
68937#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)
68938#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)
68941#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
68944/* The count of PWM_CAPTCTRLA */
68945#define PWM_CAPTCTRLA_COUNT (4U)
68946
68950#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)
68951#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)
68954#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
68955
68956#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)
68957#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)
68960#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
68963/* The count of PWM_CAPTCOMPA */
68964#define PWM_CAPTCOMPA_COUNT (4U)
68965
68969#define PWM_CAPTCTRLB_ARMB_MASK (0x1U)
68970#define PWM_CAPTCTRLB_ARMB_SHIFT (0U)
68975#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
68976
68977#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)
68978#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)
68983#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
68984
68985#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU)
68986#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U)
68993#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
68994
68995#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U)
68996#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U)
69003#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
69004
69005#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)
69006#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)
69011#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
69012
69013#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)
69014#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)
69019#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
69020
69021#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U)
69022#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U)
69025#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
69026
69027#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)
69028#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)
69031#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
69032
69033#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)
69034#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)
69037#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
69040/* The count of PWM_CAPTCTRLB */
69041#define PWM_CAPTCTRLB_COUNT (4U)
69042
69046#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)
69047#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)
69050#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
69051
69052#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)
69053#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)
69056#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
69059/* The count of PWM_CAPTCOMPB */
69060#define PWM_CAPTCOMPB_COUNT (4U)
69061
69065#define PWM_CAPTCTRLX_ARMX_MASK (0x1U)
69066#define PWM_CAPTCTRLX_ARMX_SHIFT (0U)
69071#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
69072
69073#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)
69074#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)
69079#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
69080
69081#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU)
69082#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U)
69089#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
69090
69091#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U)
69092#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U)
69099#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
69100
69101#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)
69102#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)
69107#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
69108
69109#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)
69110#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)
69115#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
69116
69117#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U)
69118#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U)
69121#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
69122
69123#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)
69124#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)
69127#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
69128
69129#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)
69130#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)
69133#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
69136/* The count of PWM_CAPTCTRLX */
69137#define PWM_CAPTCTRLX_COUNT (4U)
69138
69142#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)
69143#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)
69146#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
69147
69148#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)
69149#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)
69152#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
69155/* The count of PWM_CAPTCOMPX */
69156#define PWM_CAPTCOMPX_COUNT (4U)
69157
69161#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)
69162#define PWM_CVAL0_CAPTVAL0_SHIFT (0U)
69165#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
69168/* The count of PWM_CVAL0 */
69169#define PWM_CVAL0_COUNT (4U)
69170
69174#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)
69175#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)
69178#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
69181/* The count of PWM_CVAL0CYC */
69182#define PWM_CVAL0CYC_COUNT (4U)
69183
69187#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)
69188#define PWM_CVAL1_CAPTVAL1_SHIFT (0U)
69191#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
69194/* The count of PWM_CVAL1 */
69195#define PWM_CVAL1_COUNT (4U)
69196
69200#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)
69201#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)
69204#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
69207/* The count of PWM_CVAL1CYC */
69208#define PWM_CVAL1CYC_COUNT (4U)
69209
69213#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)
69214#define PWM_CVAL2_CAPTVAL2_SHIFT (0U)
69217#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
69220/* The count of PWM_CVAL2 */
69221#define PWM_CVAL2_COUNT (4U)
69222
69226#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)
69227#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)
69230#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
69233/* The count of PWM_CVAL2CYC */
69234#define PWM_CVAL2CYC_COUNT (4U)
69235
69239#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)
69240#define PWM_CVAL3_CAPTVAL3_SHIFT (0U)
69243#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
69246/* The count of PWM_CVAL3 */
69247#define PWM_CVAL3_COUNT (4U)
69248
69252#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)
69253#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)
69256#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
69259/* The count of PWM_CVAL3CYC */
69260#define PWM_CVAL3CYC_COUNT (4U)
69261
69265#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)
69266#define PWM_CVAL4_CAPTVAL4_SHIFT (0U)
69269#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
69272/* The count of PWM_CVAL4 */
69273#define PWM_CVAL4_COUNT (4U)
69274
69278#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)
69279#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)
69282#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
69285/* The count of PWM_CVAL4CYC */
69286#define PWM_CVAL4CYC_COUNT (4U)
69287
69291#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)
69292#define PWM_CVAL5_CAPTVAL5_SHIFT (0U)
69295#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
69298/* The count of PWM_CVAL5 */
69299#define PWM_CVAL5_COUNT (4U)
69300
69304#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)
69305#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)
69308#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
69311/* The count of PWM_CVAL5CYC */
69312#define PWM_CVAL5CYC_COUNT (4U)
69313
69317#define PWM_OUTEN_PWMX_EN_MASK (0xFU)
69318#define PWM_OUTEN_PWMX_EN_SHIFT (0U)
69323#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
69324
69325#define PWM_OUTEN_PWMB_EN_MASK (0xF0U)
69326#define PWM_OUTEN_PWMB_EN_SHIFT (4U)
69331#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
69332
69333#define PWM_OUTEN_PWMA_EN_MASK (0xF00U)
69334#define PWM_OUTEN_PWMA_EN_SHIFT (8U)
69339#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
69345#define PWM_MASK_MASKX_MASK (0xFU)
69346#define PWM_MASK_MASKX_SHIFT (0U)
69351#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
69352
69353#define PWM_MASK_MASKB_MASK (0xF0U)
69354#define PWM_MASK_MASKB_SHIFT (4U)
69359#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
69360
69361#define PWM_MASK_MASKA_MASK (0xF00U)
69362#define PWM_MASK_MASKA_SHIFT (8U)
69367#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
69373#define PWM_SWCOUT_SM0OUT45_MASK (0x1U)
69374#define PWM_SWCOUT_SM0OUT45_SHIFT (0U)
69379#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
69380
69381#define PWM_SWCOUT_SM0OUT23_MASK (0x2U)
69382#define PWM_SWCOUT_SM0OUT23_SHIFT (1U)
69387#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
69388
69389#define PWM_SWCOUT_SM1OUT45_MASK (0x4U)
69390#define PWM_SWCOUT_SM1OUT45_SHIFT (2U)
69395#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
69396
69397#define PWM_SWCOUT_SM1OUT23_MASK (0x8U)
69398#define PWM_SWCOUT_SM1OUT23_SHIFT (3U)
69403#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
69404
69405#define PWM_SWCOUT_SM2OUT45_MASK (0x10U)
69406#define PWM_SWCOUT_SM2OUT45_SHIFT (4U)
69411#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
69412
69413#define PWM_SWCOUT_SM2OUT23_MASK (0x20U)
69414#define PWM_SWCOUT_SM2OUT23_SHIFT (5U)
69419#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
69420
69421#define PWM_SWCOUT_SM3OUT45_MASK (0x40U)
69422#define PWM_SWCOUT_SM3OUT45_SHIFT (6U)
69427#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
69428
69429#define PWM_SWCOUT_SM3OUT23_MASK (0x80U)
69430#define PWM_SWCOUT_SM3OUT23_SHIFT (7U)
69435#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
69441#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)
69442#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)
69449#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
69450
69451#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)
69452#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)
69459#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
69460
69461#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)
69462#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)
69469#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
69470
69471#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)
69472#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)
69479#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
69480
69481#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)
69482#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)
69489#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
69490
69491#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)
69492#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)
69499#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
69500
69501#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)
69502#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)
69509#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
69510
69511#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)
69512#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)
69519#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
69525#define PWM_MCTRL_LDOK_MASK (0xFU)
69526#define PWM_MCTRL_LDOK_SHIFT (0U)
69531#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
69532
69533#define PWM_MCTRL_CLDOK_MASK (0xF0U)
69534#define PWM_MCTRL_CLDOK_SHIFT (4U)
69537#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
69538
69539#define PWM_MCTRL_RUN_MASK (0xF00U)
69540#define PWM_MCTRL_RUN_SHIFT (8U)
69545#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
69546
69547#define PWM_MCTRL_IPOL_MASK (0xF000U)
69548#define PWM_MCTRL_IPOL_SHIFT (12U)
69553#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
69559#define PWM_MCTRL2_MONPLL_MASK (0x3U)
69560#define PWM_MCTRL2_MONPLL_SHIFT (0U)
69569#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
69575#define PWM_FCTRL_FIE_MASK (0xFU)
69576#define PWM_FCTRL_FIE_SHIFT (0U)
69581#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
69582
69583#define PWM_FCTRL_FSAFE_MASK (0xF0U)
69584#define PWM_FCTRL_FSAFE_SHIFT (4U)
69596#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
69597
69598#define PWM_FCTRL_FAUTO_MASK (0xF00U)
69599#define PWM_FCTRL_FAUTO_SHIFT (8U)
69610#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
69611
69612#define PWM_FCTRL_FLVL_MASK (0xF000U)
69613#define PWM_FCTRL_FLVL_SHIFT (12U)
69618#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
69624#define PWM_FSTS_FFLAG_MASK (0xFU)
69625#define PWM_FSTS_FFLAG_SHIFT (0U)
69630#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
69631
69632#define PWM_FSTS_FFULL_MASK (0xF0U)
69633#define PWM_FSTS_FFULL_SHIFT (4U)
69638#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
69639
69640#define PWM_FSTS_FFPIN_MASK (0xF00U)
69641#define PWM_FSTS_FFPIN_SHIFT (8U)
69644#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
69645
69646#define PWM_FSTS_FHALF_MASK (0xF000U)
69647#define PWM_FSTS_FHALF_SHIFT (12U)
69652#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
69658#define PWM_FFILT_FILT_PER_MASK (0xFFU)
69659#define PWM_FFILT_FILT_PER_SHIFT (0U)
69662#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
69663
69664#define PWM_FFILT_FILT_CNT_MASK (0x700U)
69665#define PWM_FFILT_FILT_CNT_SHIFT (8U)
69668#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
69669
69670#define PWM_FFILT_GSTR_MASK (0x8000U)
69671#define PWM_FFILT_GSTR_SHIFT (15U)
69676#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
69682#define PWM_FTST_FTEST_MASK (0x1U)
69683#define PWM_FTST_FTEST_SHIFT (0U)
69688#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
69694#define PWM_FCTRL2_NOCOMB_MASK (0xFU)
69695#define PWM_FCTRL2_NOCOMB_SHIFT (0U)
69702#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) /* end of group PWM_Register_Masks */
69709
69710
69711/* PWM - Peripheral instance base addresses */
69713#define PWM1_BASE (0x4018C000u)
69715#define PWM1 ((PWM_Type *)PWM1_BASE)
69717#define PWM2_BASE (0x40190000u)
69719#define PWM2 ((PWM_Type *)PWM2_BASE)
69721#define PWM3_BASE (0x40194000u)
69723#define PWM3 ((PWM_Type *)PWM3_BASE)
69725#define PWM4_BASE (0x40198000u)
69727#define PWM4 ((PWM_Type *)PWM4_BASE)
69729#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
69731#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
69733#define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
69734#define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
69735#define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
69736#define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
69737#define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
69738 /* end of group PWM_Peripheral_Access_Layer */
69742
69743
69744/* ----------------------------------------------------------------------------
69745 -- PXP Peripheral Access Layer
69746 ---------------------------------------------------------------------------- */
69747
69754typedef struct {
69755 __IO uint32_t CTRL;
69756 __IO uint32_t CTRL_SET;
69757 __IO uint32_t CTRL_CLR;
69758 __IO uint32_t CTRL_TOG;
69759 __IO uint32_t STAT;
69760 __IO uint32_t STAT_SET;
69761 __IO uint32_t STAT_CLR;
69762 __IO uint32_t STAT_TOG;
69763 __IO uint32_t OUT_CTRL;
69764 __IO uint32_t OUT_CTRL_SET;
69765 __IO uint32_t OUT_CTRL_CLR;
69766 __IO uint32_t OUT_CTRL_TOG;
69767 __IO uint32_t OUT_BUF;
69768 uint8_t RESERVED_0[12];
69769 __IO uint32_t OUT_BUF2;
69770 uint8_t RESERVED_1[12];
69771 __IO uint32_t OUT_PITCH;
69772 uint8_t RESERVED_2[12];
69773 __IO uint32_t OUT_LRC;
69774 uint8_t RESERVED_3[12];
69775 __IO uint32_t OUT_PS_ULC;
69776 uint8_t RESERVED_4[12];
69777 __IO uint32_t OUT_PS_LRC;
69778 uint8_t RESERVED_5[12];
69779 __IO uint32_t OUT_AS_ULC;
69780 uint8_t RESERVED_6[12];
69781 __IO uint32_t OUT_AS_LRC;
69782 uint8_t RESERVED_7[12];
69783 __IO uint32_t PS_CTRL;
69784 __IO uint32_t PS_CTRL_SET;
69785 __IO uint32_t PS_CTRL_CLR;
69786 __IO uint32_t PS_CTRL_TOG;
69787 __IO uint32_t PS_BUF;
69788 uint8_t RESERVED_8[12];
69789 __IO uint32_t PS_UBUF;
69790 uint8_t RESERVED_9[12];
69791 __IO uint32_t PS_VBUF;
69792 uint8_t RESERVED_10[12];
69793 __IO uint32_t PS_PITCH;
69794 uint8_t RESERVED_11[12];
69795 __IO uint32_t PS_BACKGROUND;
69796 uint8_t RESERVED_12[12];
69797 __IO uint32_t PS_SCALE;
69798 uint8_t RESERVED_13[12];
69799 __IO uint32_t PS_OFFSET;
69800 uint8_t RESERVED_14[12];
69801 __IO uint32_t PS_CLRKEYLOW;
69802 uint8_t RESERVED_15[12];
69803 __IO uint32_t PS_CLRKEYHIGH;
69804 uint8_t RESERVED_16[12];
69805 __IO uint32_t AS_CTRL;
69806 uint8_t RESERVED_17[12];
69807 __IO uint32_t AS_BUF;
69808 uint8_t RESERVED_18[12];
69809 __IO uint32_t AS_PITCH;
69810 uint8_t RESERVED_19[12];
69811 __IO uint32_t AS_CLRKEYLOW;
69812 uint8_t RESERVED_20[12];
69813 __IO uint32_t AS_CLRKEYHIGH;
69814 uint8_t RESERVED_21[12];
69815 __IO uint32_t CSC1_COEF0;
69816 uint8_t RESERVED_22[12];
69817 __IO uint32_t CSC1_COEF1;
69818 uint8_t RESERVED_23[12];
69819 __IO uint32_t CSC1_COEF2;
69820 uint8_t RESERVED_24[348];
69821 __IO uint32_t POWER;
69822 uint8_t RESERVED_25[220];
69823 __IO uint32_t NEXT;
69824 uint8_t RESERVED_26[60];
69825 __IO uint32_t PORTER_DUFF_CTRL;
69826} PXP_Type;
69827
69828/* ----------------------------------------------------------------------------
69829 -- PXP Register Masks
69830 ---------------------------------------------------------------------------- */
69831
69840#define PXP_CTRL_ENABLE_MASK (0x1U)
69841#define PXP_CTRL_ENABLE_SHIFT (0U)
69846#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)
69847
69848#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U)
69849#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U)
69854#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)
69855
69856#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)
69857#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)
69862#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)
69863
69864#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
69865#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
69866#define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
69867
69868#define PXP_CTRL_ROTATE_MASK (0x300U)
69869#define PXP_CTRL_ROTATE_SHIFT (8U)
69876#define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
69877
69878#define PXP_CTRL_HFLIP_MASK (0x400U)
69879#define PXP_CTRL_HFLIP_SHIFT (10U)
69884#define PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)
69885
69886#define PXP_CTRL_VFLIP_MASK (0x800U)
69887#define PXP_CTRL_VFLIP_SHIFT (11U)
69892#define PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)
69893
69894#define PXP_CTRL_ROT_POS_MASK (0x400000U)
69895#define PXP_CTRL_ROT_POS_SHIFT (22U)
69896#define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
69897
69898#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)
69899#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U)
69904#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
69905
69906#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U)
69907#define PXP_CTRL_EN_REPEAT_SHIFT (28U)
69912#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)
69913
69914#define PXP_CTRL_CLKGATE_MASK (0x40000000U)
69915#define PXP_CTRL_CLKGATE_SHIFT (30U)
69920#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)
69921
69922#define PXP_CTRL_SFTRST_MASK (0x80000000U)
69923#define PXP_CTRL_SFTRST_SHIFT (31U)
69928#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
69934#define PXP_CTRL_SET_ENABLE_MASK (0x1U)
69935#define PXP_CTRL_SET_ENABLE_SHIFT (0U)
69940#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)
69941
69942#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)
69943#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)
69948#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)
69949
69950#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)
69951#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)
69956#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)
69957
69958#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
69959#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
69960#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)
69961
69962#define PXP_CTRL_SET_ROTATE_MASK (0x300U)
69963#define PXP_CTRL_SET_ROTATE_SHIFT (8U)
69970#define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
69971
69972#define PXP_CTRL_SET_HFLIP_MASK (0x400U)
69973#define PXP_CTRL_SET_HFLIP_SHIFT (10U)
69978#define PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)
69979
69980#define PXP_CTRL_SET_VFLIP_MASK (0x800U)
69981#define PXP_CTRL_SET_VFLIP_SHIFT (11U)
69986#define PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)
69987
69988#define PXP_CTRL_SET_ROT_POS_MASK (0x400000U)
69989#define PXP_CTRL_SET_ROT_POS_SHIFT (22U)
69990#define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
69991
69992#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)
69993#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)
69998#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
69999
70000#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)
70001#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)
70006#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)
70007
70008#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U)
70009#define PXP_CTRL_SET_CLKGATE_SHIFT (30U)
70014#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)
70015
70016#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U)
70017#define PXP_CTRL_SET_SFTRST_SHIFT (31U)
70022#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
70028#define PXP_CTRL_CLR_ENABLE_MASK (0x1U)
70029#define PXP_CTRL_CLR_ENABLE_SHIFT (0U)
70034#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)
70035
70036#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)
70037#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)
70042#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)
70043
70044#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)
70045#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)
70050#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)
70051
70052#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
70053#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
70054#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)
70055
70056#define PXP_CTRL_CLR_ROTATE_MASK (0x300U)
70057#define PXP_CTRL_CLR_ROTATE_SHIFT (8U)
70064#define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
70065
70066#define PXP_CTRL_CLR_HFLIP_MASK (0x400U)
70067#define PXP_CTRL_CLR_HFLIP_SHIFT (10U)
70072#define PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)
70073
70074#define PXP_CTRL_CLR_VFLIP_MASK (0x800U)
70075#define PXP_CTRL_CLR_VFLIP_SHIFT (11U)
70080#define PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)
70081
70082#define PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)
70083#define PXP_CTRL_CLR_ROT_POS_SHIFT (22U)
70084#define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
70085
70086#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)
70087#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)
70092#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
70093
70094#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)
70095#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)
70100#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)
70101
70102#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
70103#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U)
70108#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)
70109
70110#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)
70111#define PXP_CTRL_CLR_SFTRST_SHIFT (31U)
70116#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
70122#define PXP_CTRL_TOG_ENABLE_MASK (0x1U)
70123#define PXP_CTRL_TOG_ENABLE_SHIFT (0U)
70128#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)
70129
70130#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)
70131#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)
70136#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)
70137
70138#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)
70139#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)
70144#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)
70145
70146#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
70147#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
70148#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)
70149
70150#define PXP_CTRL_TOG_ROTATE_MASK (0x300U)
70151#define PXP_CTRL_TOG_ROTATE_SHIFT (8U)
70158#define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
70159
70160#define PXP_CTRL_TOG_HFLIP_MASK (0x400U)
70161#define PXP_CTRL_TOG_HFLIP_SHIFT (10U)
70166#define PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)
70167
70168#define PXP_CTRL_TOG_VFLIP_MASK (0x800U)
70169#define PXP_CTRL_TOG_VFLIP_SHIFT (11U)
70174#define PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)
70175
70176#define PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)
70177#define PXP_CTRL_TOG_ROT_POS_SHIFT (22U)
70178#define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
70179
70180#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)
70181#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)
70186#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
70187
70188#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)
70189#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)
70194#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)
70195
70196#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
70197#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U)
70202#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)
70203
70204#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)
70205#define PXP_CTRL_TOG_SFTRST_SHIFT (31U)
70210#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
70216#define PXP_STAT_IRQ_MASK (0x1U)
70217#define PXP_STAT_IRQ_SHIFT (0U)
70222#define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)
70223
70224#define PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)
70225#define PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)
70230#define PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)
70231
70232#define PXP_STAT_AXI_READ_ERROR_MASK (0x4U)
70233#define PXP_STAT_AXI_READ_ERROR_SHIFT (2U)
70238#define PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)
70239
70240#define PXP_STAT_NEXT_IRQ_MASK (0x8U)
70241#define PXP_STAT_NEXT_IRQ_SHIFT (3U)
70242#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)
70243
70244#define PXP_STAT_AXI_ERROR_ID_MASK (0xF0U)
70245#define PXP_STAT_AXI_ERROR_ID_SHIFT (4U)
70246#define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)
70247
70248#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
70249#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
70254#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)
70255
70256#define PXP_STAT_BLOCKY_MASK (0xFF0000U)
70257#define PXP_STAT_BLOCKY_SHIFT (16U)
70258#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)
70259
70260#define PXP_STAT_BLOCKX_MASK (0xFF000000U)
70261#define PXP_STAT_BLOCKX_SHIFT (24U)
70262#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
70268#define PXP_STAT_SET_IRQ_MASK (0x1U)
70269#define PXP_STAT_SET_IRQ_SHIFT (0U)
70274#define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)
70275
70276#define PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)
70277#define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)
70282#define PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)
70283
70284#define PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)
70285#define PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)
70290#define PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)
70291
70292#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)
70293#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)
70294#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)
70295
70296#define PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)
70297#define PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)
70298#define PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)
70299
70300#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
70301#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
70306#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)
70307
70308#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)
70309#define PXP_STAT_SET_BLOCKY_SHIFT (16U)
70310#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)
70311
70312#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)
70313#define PXP_STAT_SET_BLOCKX_SHIFT (24U)
70314#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
70320#define PXP_STAT_CLR_IRQ_MASK (0x1U)
70321#define PXP_STAT_CLR_IRQ_SHIFT (0U)
70326#define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)
70327
70328#define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)
70329#define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)
70334#define PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)
70335
70336#define PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)
70337#define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)
70342#define PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)
70343
70344#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)
70345#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)
70346#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)
70347
70348#define PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)
70349#define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)
70350#define PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)
70351
70352#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
70353#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
70358#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)
70359
70360#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)
70361#define PXP_STAT_CLR_BLOCKY_SHIFT (16U)
70362#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)
70363
70364#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)
70365#define PXP_STAT_CLR_BLOCKX_SHIFT (24U)
70366#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
70372#define PXP_STAT_TOG_IRQ_MASK (0x1U)
70373#define PXP_STAT_TOG_IRQ_SHIFT (0U)
70378#define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)
70379
70380#define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)
70381#define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)
70386#define PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)
70387
70388#define PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)
70389#define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)
70394#define PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)
70395
70396#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)
70397#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)
70398#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)
70399
70400#define PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)
70401#define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)
70402#define PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)
70403
70404#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
70405#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
70410#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)
70411
70412#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)
70413#define PXP_STAT_TOG_BLOCKY_SHIFT (16U)
70414#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)
70415
70416#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)
70417#define PXP_STAT_TOG_BLOCKX_SHIFT (24U)
70418#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
70424#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU)
70425#define PXP_OUT_CTRL_FORMAT_SHIFT (0U)
70445#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
70446
70447#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)
70448#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)
70455#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
70456
70457#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)
70458#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)
70463#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)
70464
70465#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)
70466#define PXP_OUT_CTRL_ALPHA_SHIFT (24U)
70467#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
70473#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)
70474#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)
70494#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
70495
70496#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)
70497#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
70504#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
70505
70506#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)
70507#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)
70512#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)
70513
70514#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)
70515#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)
70516#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
70522#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)
70523#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)
70543#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
70544
70545#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)
70546#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
70553#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
70554
70555#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)
70556#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)
70561#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)
70562
70563#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)
70564#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)
70565#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
70571#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)
70572#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)
70592#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
70593
70594#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)
70595#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
70602#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
70603
70604#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)
70605#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)
70610#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)
70611
70612#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)
70613#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)
70614#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
70620#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)
70621#define PXP_OUT_BUF_ADDR_SHIFT (0U)
70622#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
70628#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)
70629#define PXP_OUT_BUF2_ADDR_SHIFT (0U)
70630#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
70636#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)
70637#define PXP_OUT_PITCH_PITCH_SHIFT (0U)
70638#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)
70644#define PXP_OUT_LRC_Y_MASK (0x3FFFU)
70645#define PXP_OUT_LRC_Y_SHIFT (0U)
70646#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)
70647
70648#define PXP_OUT_LRC_X_MASK (0x3FFF0000U)
70649#define PXP_OUT_LRC_X_SHIFT (16U)
70650#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)
70656#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)
70657#define PXP_OUT_PS_ULC_Y_SHIFT (0U)
70658#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)
70659
70660#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)
70661#define PXP_OUT_PS_ULC_X_SHIFT (16U)
70662#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)
70668#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)
70669#define PXP_OUT_PS_LRC_Y_SHIFT (0U)
70670#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)
70671
70672#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)
70673#define PXP_OUT_PS_LRC_X_SHIFT (16U)
70674#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)
70680#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)
70681#define PXP_OUT_AS_ULC_Y_SHIFT (0U)
70682#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)
70683
70684#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)
70685#define PXP_OUT_AS_ULC_X_SHIFT (16U)
70686#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)
70692#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU)
70693#define PXP_OUT_AS_LRC_Y_SHIFT (0U)
70694#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)
70695
70696#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)
70697#define PXP_OUT_AS_LRC_X_SHIFT (16U)
70698#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)
70704#define PXP_PS_CTRL_FORMAT_MASK (0x3FU)
70705#define PXP_PS_CTRL_FORMAT_SHIFT (0U)
70726#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
70727
70728#define PXP_PS_CTRL_WB_SWAP_MASK (0x40U)
70729#define PXP_PS_CTRL_WB_SWAP_SHIFT (6U)
70734#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)
70735
70736#define PXP_PS_CTRL_DECY_MASK (0x300U)
70737#define PXP_PS_CTRL_DECY_SHIFT (8U)
70744#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
70745
70746#define PXP_PS_CTRL_DECX_MASK (0xC00U)
70747#define PXP_PS_CTRL_DECX_SHIFT (10U)
70754#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
70760#define PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU)
70761#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)
70782#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
70783
70784#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U)
70785#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U)
70790#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)
70791
70792#define PXP_PS_CTRL_SET_DECY_MASK (0x300U)
70793#define PXP_PS_CTRL_SET_DECY_SHIFT (8U)
70800#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
70801
70802#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U)
70803#define PXP_PS_CTRL_SET_DECX_SHIFT (10U)
70810#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
70816#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU)
70817#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)
70838#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
70839
70840#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U)
70841#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U)
70846#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)
70847
70848#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U)
70849#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U)
70856#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
70857
70858#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)
70859#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U)
70866#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
70872#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU)
70873#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)
70894#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
70895
70896#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U)
70897#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U)
70902#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)
70903
70904#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U)
70905#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U)
70912#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
70913
70914#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)
70915#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U)
70922#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
70928#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)
70929#define PXP_PS_BUF_ADDR_SHIFT (0U)
70930#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
70936#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)
70937#define PXP_PS_UBUF_ADDR_SHIFT (0U)
70938#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
70944#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)
70945#define PXP_PS_VBUF_ADDR_SHIFT (0U)
70946#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
70952#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU)
70953#define PXP_PS_PITCH_PITCH_SHIFT (0U)
70954#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)
70960#define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)
70961#define PXP_PS_BACKGROUND_COLOR_SHIFT (0U)
70962#define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)
70968#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU)
70969#define PXP_PS_SCALE_XSCALE_SHIFT (0U)
70970#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)
70971
70972#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)
70973#define PXP_PS_SCALE_YSCALE_SHIFT (16U)
70974#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)
70980#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)
70981#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U)
70982#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)
70983
70984#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)
70985#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U)
70986#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)
70992#define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
70993#define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)
70994#define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)
71000#define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
71001#define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)
71002#define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)
71008#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)
71009#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)
71017#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
71018
71019#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)
71020#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)
71025#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
71026
71027#define PXP_AS_CTRL_FORMAT_MASK (0xF0U)
71028#define PXP_AS_CTRL_FORMAT_SHIFT (4U)
71041#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
71042
71043#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U)
71044#define PXP_AS_CTRL_ALPHA_SHIFT (8U)
71045#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
71046
71047#define PXP_AS_CTRL_ROP_MASK (0xF0000U)
71048#define PXP_AS_CTRL_ROP_SHIFT (16U)
71063#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
71064
71065#define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)
71066#define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)
71071#define PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)
71077#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)
71078#define PXP_AS_BUF_ADDR_SHIFT (0U)
71079#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
71085#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU)
71086#define PXP_AS_PITCH_PITCH_SHIFT (0U)
71087#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)
71093#define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
71094#define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)
71095#define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)
71101#define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
71102#define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)
71103#define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)
71109#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)
71110#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)
71111#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)
71112
71113#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)
71114#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)
71115#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)
71116
71117#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)
71118#define PXP_CSC1_COEF0_C0_SHIFT (18U)
71119#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)
71120
71121#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)
71122#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U)
71123#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)
71124
71125#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)
71126#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)
71131#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
71137#define PXP_CSC1_COEF1_C4_MASK (0x7FFU)
71138#define PXP_CSC1_COEF1_C4_SHIFT (0U)
71139#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)
71140
71141#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U)
71142#define PXP_CSC1_COEF1_C1_SHIFT (16U)
71143#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)
71149#define PXP_CSC1_COEF2_C3_MASK (0x7FFU)
71150#define PXP_CSC1_COEF2_C3_SHIFT (0U)
71151#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)
71152
71153#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U)
71154#define PXP_CSC1_COEF2_C2_SHIFT (16U)
71155#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)
71161#define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)
71162#define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)
71169#define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
71175#define PXP_NEXT_ENABLED_MASK (0x1U)
71176#define PXP_NEXT_ENABLED_SHIFT (0U)
71177#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)
71178
71179#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)
71180#define PXP_NEXT_POINTER_SHIFT (2U)
71181#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
71187#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U)
71188#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U)
71193#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)
71194
71195#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)
71196#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
71203#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)
71204
71205#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
71206#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
71213#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
71214
71215#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)
71216#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)
71221#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)
71222
71223#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)
71224#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)
71229#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)
71230
71231#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)
71232#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
71239#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)
71240
71241#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
71242#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
71249#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
71250
71251#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)
71252#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)
71257#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)
71258
71259#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)
71260#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)
71265#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)
71266
71267#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)
71268#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)
71269#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)
71270
71271#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)
71272#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)
71273#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK) /* end of group PXP_Register_Masks */
71280
71281
71282/* PXP - Peripheral instance base addresses */
71284#define PXP_BASE (0x40814000u)
71286#define PXP ((PXP_Type *)PXP_BASE)
71288#define PXP_BASE_ADDRS { PXP_BASE }
71290#define PXP_BASE_PTRS { PXP }
71292#define PXP_IRQ0_IRQS { PXP_IRQn }
71293 /* end of group PXP_Peripheral_Access_Layer */
71297
71298
71299/* ----------------------------------------------------------------------------
71300 -- RDC Peripheral Access Layer
71301 ---------------------------------------------------------------------------- */
71302
71309typedef struct {
71310 __I uint32_t VIR;
71311 uint8_t RESERVED_0[32];
71312 __IO uint32_t STAT;
71313 __IO uint32_t INTCTRL;
71314 __IO uint32_t INTSTAT;
71315 uint8_t RESERVED_1[464];
71316 __IO uint32_t MDA[12];
71317 uint8_t RESERVED_2[464];
71318 __IO uint32_t PDAP[128];
71319 uint8_t RESERVED_3[512];
71320 struct { /* offset: 0x800, array step: 0x10 */
71321 __IO uint32_t MRSA;
71322 __IO uint32_t MREA;
71323 __IO uint32_t MRC;
71324 __IO uint32_t MRVS;
71325 } MR[59];
71326} RDC_Type;
71327
71328/* ----------------------------------------------------------------------------
71329 -- RDC Register Masks
71330 ---------------------------------------------------------------------------- */
71331
71340#define RDC_VIR_NDID_MASK (0xFU)
71341#define RDC_VIR_NDID_SHIFT (0U)
71344#define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)
71345
71346#define RDC_VIR_NMSTR_MASK (0xFF0U)
71347#define RDC_VIR_NMSTR_SHIFT (4U)
71350#define RDC_VIR_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)
71351
71352#define RDC_VIR_NPER_MASK (0xFF000U)
71353#define RDC_VIR_NPER_SHIFT (12U)
71356#define RDC_VIR_NPER(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)
71357
71358#define RDC_VIR_NRGN_MASK (0xFF00000U)
71359#define RDC_VIR_NRGN_SHIFT (20U)
71362#define RDC_VIR_NRGN(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)
71368#define RDC_STAT_DID_MASK (0xFU)
71369#define RDC_STAT_DID_SHIFT (0U)
71372#define RDC_STAT_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)
71373
71374#define RDC_STAT_PDS_MASK (0x100U)
71375#define RDC_STAT_PDS_SHIFT (8U)
71380#define RDC_STAT_PDS(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)
71386#define RDC_INTCTRL_RCI_EN_MASK (0x1U)
71387#define RDC_INTCTRL_RCI_EN_SHIFT (0U)
71392#define RDC_INTCTRL_RCI_EN(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)
71398#define RDC_INTSTAT_INT_MASK (0x1U)
71399#define RDC_INTSTAT_INT_SHIFT (0U)
71404#define RDC_INTSTAT_INT(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)
71410#define RDC_MDA_DID_MASK (0x3U)
71411#define RDC_MDA_DID_SHIFT (0U)
71418#define RDC_MDA_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)
71419
71420#define RDC_MDA_LCK_MASK (0x80000000U)
71421#define RDC_MDA_LCK_SHIFT (31U)
71426#define RDC_MDA_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)
71429/* The count of RDC_MDA */
71430#define RDC_MDA_COUNT (12U)
71431
71435#define RDC_PDAP_D0W_MASK (0x1U)
71436#define RDC_PDAP_D0W_SHIFT (0U)
71441#define RDC_PDAP_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)
71442
71443#define RDC_PDAP_D0R_MASK (0x2U)
71444#define RDC_PDAP_D0R_SHIFT (1U)
71449#define RDC_PDAP_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)
71450
71451#define RDC_PDAP_D1W_MASK (0x4U)
71452#define RDC_PDAP_D1W_SHIFT (2U)
71457#define RDC_PDAP_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)
71458
71459#define RDC_PDAP_D1R_MASK (0x8U)
71460#define RDC_PDAP_D1R_SHIFT (3U)
71465#define RDC_PDAP_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)
71466
71467#define RDC_PDAP_SREQ_MASK (0x40000000U)
71468#define RDC_PDAP_SREQ_SHIFT (30U)
71473#define RDC_PDAP_SREQ(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)
71474
71475#define RDC_PDAP_LCK_MASK (0x80000000U)
71476#define RDC_PDAP_LCK_SHIFT (31U)
71481#define RDC_PDAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)
71484/* The count of RDC_PDAP */
71485#define RDC_PDAP_COUNT (128U)
71486
71490#define RDC_MRSA_SADR_MASK (0xFFFFFF80U)
71491#define RDC_MRSA_SADR_SHIFT (7U)
71494#define RDC_MRSA_SADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)
71497/* The count of RDC_MRSA */
71498#define RDC_MRSA_COUNT (59U)
71499
71503#define RDC_MREA_EADR_MASK (0xFFFFFF80U)
71504#define RDC_MREA_EADR_SHIFT (7U)
71507#define RDC_MREA_EADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)
71510/* The count of RDC_MREA */
71511#define RDC_MREA_COUNT (59U)
71512
71516#define RDC_MRC_D0W_MASK (0x1U)
71517#define RDC_MRC_D0W_SHIFT (0U)
71522#define RDC_MRC_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)
71523
71524#define RDC_MRC_D0R_MASK (0x2U)
71525#define RDC_MRC_D0R_SHIFT (1U)
71530#define RDC_MRC_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)
71531
71532#define RDC_MRC_D1W_MASK (0x4U)
71533#define RDC_MRC_D1W_SHIFT (2U)
71538#define RDC_MRC_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)
71539
71540#define RDC_MRC_D1R_MASK (0x8U)
71541#define RDC_MRC_D1R_SHIFT (3U)
71546#define RDC_MRC_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)
71547
71548#define RDC_MRC_ENA_MASK (0x40000000U)
71549#define RDC_MRC_ENA_SHIFT (30U)
71554#define RDC_MRC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)
71555
71556#define RDC_MRC_LCK_MASK (0x80000000U)
71557#define RDC_MRC_LCK_SHIFT (31U)
71562#define RDC_MRC_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)
71565/* The count of RDC_MRC */
71566#define RDC_MRC_COUNT (59U)
71567
71571#define RDC_MRVS_VDID_MASK (0x3U)
71572#define RDC_MRVS_VDID_SHIFT (0U)
71579#define RDC_MRVS_VDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)
71580
71581#define RDC_MRVS_AD_MASK (0x10U)
71582#define RDC_MRVS_AD_SHIFT (4U)
71585#define RDC_MRVS_AD(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)
71586
71587#define RDC_MRVS_VADR_MASK (0xFFFFFFE0U)
71588#define RDC_MRVS_VADR_SHIFT (5U)
71591#define RDC_MRVS_VADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)
71594/* The count of RDC_MRVS */
71595#define RDC_MRVS_COUNT (59U)
71596
71597 /* end of group RDC_Register_Masks */
71601
71602
71603/* RDC - Peripheral instance base addresses */
71605#define RDC_BASE (0x40C78000u)
71607#define RDC ((RDC_Type *)RDC_BASE)
71609#define RDC_BASE_ADDRS { RDC_BASE }
71611#define RDC_BASE_PTRS { RDC }
71613#define RDC_IRQS { RDC_IRQn }
71614 /* end of group RDC_Peripheral_Access_Layer */
71618
71619
71620/* ----------------------------------------------------------------------------
71621 -- RDC_SEMAPHORE Peripheral Access Layer
71622 ---------------------------------------------------------------------------- */
71623
71630typedef struct {
71631 __IO uint8_t GATE[64];
71632 uint8_t RESERVED_0[2];
71633 union { /* offset: 0x42 */
71634 __IO uint16_t RSTGT_R;
71635 __IO uint16_t RSTGT_W;
71636 };
71638
71639/* ----------------------------------------------------------------------------
71640 -- RDC_SEMAPHORE Register Masks
71641 ---------------------------------------------------------------------------- */
71642
71651#define RDC_SEMAPHORE_GATE_GTFSM_MASK (0xFU)
71652#define RDC_SEMAPHORE_GATE_GTFSM_SHIFT (0U)
71671#define RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE_GTFSM_MASK)
71672
71673#define RDC_SEMAPHORE_GATE_LDOM_MASK (0x30U)
71674#define RDC_SEMAPHORE_GATE_LDOM_SHIFT (4U)
71681#define RDC_SEMAPHORE_GATE_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE_LDOM_MASK)
71684/* The count of RDC_SEMAPHORE_GATE */
71685#define RDC_SEMAPHORE_GATE_COUNT (64U)
71686
71690#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK (0xFU)
71691#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT (0U)
71692#define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)
71693
71694#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK (0x30U)
71695#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT (4U)
71704#define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)
71705
71706#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK (0xFF00U)
71707#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT (8U)
71708#define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)
71714#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU)
71715#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U)
71716#define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)
71717
71718#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U)
71719#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U)
71720#define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK) /* end of group RDC_SEMAPHORE_Register_Masks */
71727
71728
71729/* RDC_SEMAPHORE - Peripheral instance base addresses */
71731#define RDC_SEMAPHORE1_BASE (0x40C44000u)
71733#define RDC_SEMAPHORE1 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE)
71735#define RDC_SEMAPHORE2_BASE (0x40CCC000u)
71737#define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
71739#define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
71741#define RDC_SEMAPHORE_BASE_PTRS { RDC_SEMAPHORE1, RDC_SEMAPHORE2 }
71742 /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */
71746
71747
71748/* ----------------------------------------------------------------------------
71749 -- RTWDOG Peripheral Access Layer
71750 ---------------------------------------------------------------------------- */
71751
71758typedef struct {
71759 __IO uint32_t CS;
71760 __IO uint32_t CNT;
71761 __IO uint32_t TOVAL;
71762 __IO uint32_t WIN;
71763} RTWDOG_Type;
71764
71765/* ----------------------------------------------------------------------------
71766 -- RTWDOG Register Masks
71767 ---------------------------------------------------------------------------- */
71768
71777#define RTWDOG_CS_STOP_MASK (0x1U)
71778#define RTWDOG_CS_STOP_SHIFT (0U)
71783#define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
71784
71785#define RTWDOG_CS_WAIT_MASK (0x2U)
71786#define RTWDOG_CS_WAIT_SHIFT (1U)
71791#define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
71792
71793#define RTWDOG_CS_DBG_MASK (0x4U)
71794#define RTWDOG_CS_DBG_SHIFT (2U)
71799#define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
71800
71801#define RTWDOG_CS_TST_MASK (0x18U)
71802#define RTWDOG_CS_TST_SHIFT (3U)
71810#define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
71811
71812#define RTWDOG_CS_UPDATE_MASK (0x20U)
71813#define RTWDOG_CS_UPDATE_SHIFT (5U)
71818#define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
71819
71820#define RTWDOG_CS_INT_MASK (0x40U)
71821#define RTWDOG_CS_INT_SHIFT (6U)
71826#define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
71827
71828#define RTWDOG_CS_EN_MASK (0x80U)
71829#define RTWDOG_CS_EN_SHIFT (7U)
71834#define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
71835
71836#define RTWDOG_CS_CLK_MASK (0x300U)
71837#define RTWDOG_CS_CLK_SHIFT (8U)
71840#define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
71841
71842#define RTWDOG_CS_RCS_MASK (0x400U)
71843#define RTWDOG_CS_RCS_SHIFT (10U)
71848#define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
71849
71850#define RTWDOG_CS_ULK_MASK (0x800U)
71851#define RTWDOG_CS_ULK_SHIFT (11U)
71856#define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
71857
71858#define RTWDOG_CS_PRES_MASK (0x1000U)
71859#define RTWDOG_CS_PRES_SHIFT (12U)
71864#define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
71865
71866#define RTWDOG_CS_CMD32EN_MASK (0x2000U)
71867#define RTWDOG_CS_CMD32EN_SHIFT (13U)
71872#define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
71873
71874#define RTWDOG_CS_FLG_MASK (0x4000U)
71875#define RTWDOG_CS_FLG_SHIFT (14U)
71880#define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
71881
71882#define RTWDOG_CS_WIN_MASK (0x8000U)
71883#define RTWDOG_CS_WIN_SHIFT (15U)
71888#define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
71894#define RTWDOG_CNT_CNTLOW_MASK (0xFFU)
71895#define RTWDOG_CNT_CNTLOW_SHIFT (0U)
71898#define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
71899
71900#define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)
71901#define RTWDOG_CNT_CNTHIGH_SHIFT (8U)
71904#define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
71910#define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)
71911#define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)
71914#define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
71915
71916#define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)
71917#define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)
71920#define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
71926#define RTWDOG_WIN_WINLOW_MASK (0xFFU)
71927#define RTWDOG_WIN_WINLOW_SHIFT (0U)
71930#define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
71931
71932#define RTWDOG_WIN_WINHIGH_MASK (0xFF00U)
71933#define RTWDOG_WIN_WINHIGH_SHIFT (8U)
71936#define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) /* end of group RTWDOG_Register_Masks */
71943
71944
71945/* RTWDOG - Peripheral instance base addresses */
71947#define RTWDOG3_BASE (0x40038000u)
71949#define RTWDOG3 ((RTWDOG_Type *)RTWDOG3_BASE)
71951#define RTWDOG4_BASE (0x40C10000u)
71953#define RTWDOG4 ((RTWDOG_Type *)RTWDOG4_BASE)
71955#define RTWDOG_BASE_ADDRS { 0u, 0u, 0u, RTWDOG3_BASE, RTWDOG4_BASE }
71957#define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 }
71959#define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG3_IRQn, NotAvail_IRQn }
71960/* Extra definition */
71961#define RTWDOG_UPDATE_KEY (0xD928C520U)
71962#define RTWDOG_REFRESH_KEY (0xB480A602U)
71963
71964 /* end of group RTWDOG_Peripheral_Access_Layer */
71968
71969
71970/* ----------------------------------------------------------------------------
71971 -- SEMA4 Peripheral Access Layer
71972 ---------------------------------------------------------------------------- */
71973
71980typedef struct {
71981 __IO uint8_t GATE[16];
71982 uint8_t RESERVED_0[48];
71983 struct { /* offset: 0x40, array step: 0x8 */
71984 __IO uint16_t CPINE;
71985 uint8_t RESERVED_0[6];
71986 } CPINE[2];
71987 uint8_t RESERVED_1[48];
71988 struct { /* offset: 0x80, array step: 0x8 */
71989 __I uint16_t CPNTF;
71990 uint8_t RESERVED_0[6];
71991 } CPNTF[2];
71992 uint8_t RESERVED_2[112];
71993 __IO uint16_t RSTGT;
71994 uint8_t RESERVED_3[2];
71995 __IO uint16_t RSTNTF;
71996} SEMA4_Type;
71997
71998/* ----------------------------------------------------------------------------
71999 -- SEMA4 Register Masks
72000 ---------------------------------------------------------------------------- */
72001
72010#define SEMA4_GATE_GTFSM_MASK (0x3U)
72011#define SEMA4_GATE_GTFSM_SHIFT (0U)
72019#define SEMA4_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_GATE_GTFSM_SHIFT)) & SEMA4_GATE_GTFSM_MASK)
72022/* The count of SEMA4_GATE */
72023#define SEMA4_GATE_COUNT (16U)
72024
72028#define SEMA4_CPINE_INE7_MASK (0x1U)
72029#define SEMA4_CPINE_INE7_SHIFT (0U)
72035#define SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)
72036
72037#define SEMA4_CPINE_INE6_MASK (0x2U)
72038#define SEMA4_CPINE_INE6_SHIFT (1U)
72044#define SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)
72045
72046#define SEMA4_CPINE_INE5_MASK (0x4U)
72047#define SEMA4_CPINE_INE5_SHIFT (2U)
72053#define SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)
72054
72055#define SEMA4_CPINE_INE4_MASK (0x8U)
72056#define SEMA4_CPINE_INE4_SHIFT (3U)
72062#define SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)
72063
72064#define SEMA4_CPINE_INE3_MASK (0x10U)
72065#define SEMA4_CPINE_INE3_SHIFT (4U)
72070#define SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)
72071
72072#define SEMA4_CPINE_INE2_MASK (0x20U)
72073#define SEMA4_CPINE_INE2_SHIFT (5U)
72078#define SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)
72079
72080#define SEMA4_CPINE_INE1_MASK (0x40U)
72081#define SEMA4_CPINE_INE1_SHIFT (6U)
72086#define SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)
72087
72088#define SEMA4_CPINE_INE0_MASK (0x80U)
72089#define SEMA4_CPINE_INE0_SHIFT (7U)
72094#define SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)
72095
72096#define SEMA4_CPINE_INE15_MASK (0x100U)
72097#define SEMA4_CPINE_INE15_SHIFT (8U)
72103#define SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)
72104
72105#define SEMA4_CPINE_INE14_MASK (0x200U)
72106#define SEMA4_CPINE_INE14_SHIFT (9U)
72112#define SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)
72113
72114#define SEMA4_CPINE_INE13_MASK (0x400U)
72115#define SEMA4_CPINE_INE13_SHIFT (10U)
72121#define SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)
72122
72123#define SEMA4_CPINE_INE12_MASK (0x800U)
72124#define SEMA4_CPINE_INE12_SHIFT (11U)
72130#define SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)
72131
72132#define SEMA4_CPINE_INE11_MASK (0x1000U)
72133#define SEMA4_CPINE_INE11_SHIFT (12U)
72139#define SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)
72140
72141#define SEMA4_CPINE_INE10_MASK (0x2000U)
72142#define SEMA4_CPINE_INE10_SHIFT (13U)
72148#define SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)
72149
72150#define SEMA4_CPINE_INE9_MASK (0x4000U)
72151#define SEMA4_CPINE_INE9_SHIFT (14U)
72157#define SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)
72158
72159#define SEMA4_CPINE_INE8_MASK (0x8000U)
72160#define SEMA4_CPINE_INE8_SHIFT (15U)
72166#define SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)
72169/* The count of SEMA4_CPINE */
72170#define SEMA4_CPINE_COUNT (2U)
72171
72175#define SEMA4_CPNTF_GN7_MASK (0x1U)
72176#define SEMA4_CPNTF_GN7_SHIFT (0U)
72177#define SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK)
72178
72179#define SEMA4_CPNTF_GN6_MASK (0x2U)
72180#define SEMA4_CPNTF_GN6_SHIFT (1U)
72181#define SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK)
72182
72183#define SEMA4_CPNTF_GN5_MASK (0x4U)
72184#define SEMA4_CPNTF_GN5_SHIFT (2U)
72185#define SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK)
72186
72187#define SEMA4_CPNTF_GN4_MASK (0x8U)
72188#define SEMA4_CPNTF_GN4_SHIFT (3U)
72189#define SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK)
72190
72191#define SEMA4_CPNTF_GN3_MASK (0x10U)
72192#define SEMA4_CPNTF_GN3_SHIFT (4U)
72193#define SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK)
72194
72195#define SEMA4_CPNTF_GN2_MASK (0x20U)
72196#define SEMA4_CPNTF_GN2_SHIFT (5U)
72197#define SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK)
72198
72199#define SEMA4_CPNTF_GN1_MASK (0x40U)
72200#define SEMA4_CPNTF_GN1_SHIFT (6U)
72201#define SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK)
72202
72203#define SEMA4_CPNTF_GN0_MASK (0x80U)
72204#define SEMA4_CPNTF_GN0_SHIFT (7U)
72205#define SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK)
72206
72207#define SEMA4_CPNTF_GN15_MASK (0x100U)
72208#define SEMA4_CPNTF_GN15_SHIFT (8U)
72209#define SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK)
72210
72211#define SEMA4_CPNTF_GN14_MASK (0x200U)
72212#define SEMA4_CPNTF_GN14_SHIFT (9U)
72213#define SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK)
72214
72215#define SEMA4_CPNTF_GN13_MASK (0x400U)
72216#define SEMA4_CPNTF_GN13_SHIFT (10U)
72217#define SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK)
72218
72219#define SEMA4_CPNTF_GN12_MASK (0x800U)
72220#define SEMA4_CPNTF_GN12_SHIFT (11U)
72221#define SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK)
72222
72223#define SEMA4_CPNTF_GN11_MASK (0x1000U)
72224#define SEMA4_CPNTF_GN11_SHIFT (12U)
72225#define SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK)
72226
72227#define SEMA4_CPNTF_GN10_MASK (0x2000U)
72228#define SEMA4_CPNTF_GN10_SHIFT (13U)
72229#define SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK)
72230
72231#define SEMA4_CPNTF_GN9_MASK (0x4000U)
72232#define SEMA4_CPNTF_GN9_SHIFT (14U)
72233#define SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK)
72234
72235#define SEMA4_CPNTF_GN8_MASK (0x8000U)
72236#define SEMA4_CPNTF_GN8_SHIFT (15U)
72237#define SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK)
72240/* The count of SEMA4_CPNTF */
72241#define SEMA4_CPNTF_COUNT (2U)
72242
72246#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK (0xFFU)
72247#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT (0U)
72248#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)
72249
72250#define SEMA4_RSTGT_RSTGTN_MASK (0xFF00U)
72251#define SEMA4_RSTGT_RSTGTN_SHIFT (8U)
72252#define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK)
72258#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK (0xFFU)
72259#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT (0U)
72260#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)
72261
72262#define SEMA4_RSTNTF_RSTNTN_MASK (0xFF00U)
72263#define SEMA4_RSTNTF_RSTNTN_SHIFT (8U)
72264#define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK) /* end of group SEMA4_Register_Masks */
72271
72272
72273/* SEMA4 - Peripheral instance base addresses */
72275#define SEMA4_BASE (0x40CC8000u)
72277#define SEMA4 ((SEMA4_Type *)SEMA4_BASE)
72279#define SEMA4_BASE_ADDRS { SEMA4_BASE }
72281#define SEMA4_BASE_PTRS { SEMA4 }
72282 /* end of group SEMA4_Peripheral_Access_Layer */
72286
72287
72288/* ----------------------------------------------------------------------------
72289 -- SEMC Peripheral Access Layer
72290 ---------------------------------------------------------------------------- */
72291
72298typedef struct {
72299 __IO uint32_t MCR;
72300 __IO uint32_t IOCR;
72301 __IO uint32_t BMCR0;
72302 __IO uint32_t BMCR1;
72303 __IO uint32_t BR[9];
72304 __IO uint32_t DLLCR;
72305 __IO uint32_t INTEN;
72306 __IO uint32_t INTR;
72307 __IO uint32_t SDRAMCR0;
72308 __IO uint32_t SDRAMCR1;
72309 __IO uint32_t SDRAMCR2;
72310 __IO uint32_t SDRAMCR3;
72311 __IO uint32_t NANDCR0;
72312 __IO uint32_t NANDCR1;
72313 __IO uint32_t NANDCR2;
72314 __IO uint32_t NANDCR3;
72315 __IO uint32_t NORCR0;
72316 __IO uint32_t NORCR1;
72317 __IO uint32_t NORCR2;
72318 __IO uint32_t NORCR3;
72319 __IO uint32_t SRAMCR0;
72320 __IO uint32_t SRAMCR1;
72321 __IO uint32_t SRAMCR2;
72322 uint32_t SRAMCR3;
72323 __IO uint32_t DBICR0;
72324 __IO uint32_t DBICR1;
72325 __IO uint32_t DBICR2;
72326 uint8_t RESERVED_0[4];
72327 __IO uint32_t IPCR0;
72328 __IO uint32_t IPCR1;
72329 __IO uint32_t IPCR2;
72330 __IO uint32_t IPCMD;
72331 __IO uint32_t IPTXDAT;
72332 uint8_t RESERVED_1[12];
72333 __I uint32_t IPRXDAT;
72334 uint8_t RESERVED_2[12];
72335 __I uint32_t STS0;
72336 uint32_t STS1;
72337 __I uint32_t STS2;
72338 uint32_t STS3;
72339 uint32_t STS4;
72340 uint32_t STS5;
72341 uint32_t STS6;
72342 uint32_t STS7;
72343 uint32_t STS8;
72344 uint32_t STS9;
72345 uint32_t STS10;
72346 uint32_t STS11;
72347 __I uint32_t STS12;
72348 __I uint32_t STS13;
72349 uint32_t STS14;
72350 uint32_t STS15;
72351 __IO uint32_t BR9;
72352 __IO uint32_t BR10;
72353 __IO uint32_t BR11;
72354 uint8_t RESERVED_3[20];
72355 __IO uint32_t SRAMCR4;
72356 __IO uint32_t SRAMCR5;
72357 __IO uint32_t SRAMCR6;
72358 uint8_t RESERVED_4[36];
72359 __IO uint32_t DCCR;
72360} SEMC_Type;
72361
72362/* ----------------------------------------------------------------------------
72363 -- SEMC Register Masks
72364 ---------------------------------------------------------------------------- */
72365
72374#define SEMC_MCR_SWRST_MASK (0x1U)
72375#define SEMC_MCR_SWRST_SHIFT (0U)
72380#define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
72381
72382#define SEMC_MCR_MDIS_MASK (0x2U)
72383#define SEMC_MCR_MDIS_SHIFT (1U)
72388#define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
72389
72390#define SEMC_MCR_DQSMD_MASK (0x4U)
72391#define SEMC_MCR_DQSMD_SHIFT (2U)
72396#define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
72397
72398#define SEMC_MCR_WPOL0_MASK (0x40U)
72399#define SEMC_MCR_WPOL0_SHIFT (6U)
72404#define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
72405
72406#define SEMC_MCR_WPOL1_MASK (0x80U)
72407#define SEMC_MCR_WPOL1_SHIFT (7U)
72412#define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
72413
72414#define SEMC_MCR_CTO_MASK (0xFF0000U)
72415#define SEMC_MCR_CTO_SHIFT (16U)
72418#define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
72419
72420#define SEMC_MCR_BTO_MASK (0x1F000000U)
72421#define SEMC_MCR_BTO_SHIFT (24U)
72427#define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
72433#define SEMC_IOCR_MUX_A8_MASK (0xFU)
72434#define SEMC_IOCR_MUX_A8_SHIFT (0U)
72446#define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
72447
72448#define SEMC_IOCR_MUX_CSX0_MASK (0xF0U)
72449#define SEMC_IOCR_MUX_CSX0_SHIFT (4U)
72464#define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
72465
72466#define SEMC_IOCR_MUX_CSX1_MASK (0xF00U)
72467#define SEMC_IOCR_MUX_CSX1_SHIFT (8U)
72482#define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
72483
72484#define SEMC_IOCR_MUX_CSX2_MASK (0xF000U)
72485#define SEMC_IOCR_MUX_CSX2_SHIFT (12U)
72500#define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
72501
72502#define SEMC_IOCR_MUX_CSX3_MASK (0xF0000U)
72503#define SEMC_IOCR_MUX_CSX3_SHIFT (16U)
72518#define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
72519
72520#define SEMC_IOCR_MUX_RDY_MASK (0xF00000U)
72521#define SEMC_IOCR_MUX_RDY_SHIFT (20U)
72536#define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
72537
72538#define SEMC_IOCR_MUX_CLKX0_MASK (0x3000000U)
72539#define SEMC_IOCR_MUX_CLKX0_SHIFT (24U)
72546#define SEMC_IOCR_MUX_CLKX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK)
72547
72548#define SEMC_IOCR_MUX_CLKX1_MASK (0xC000000U)
72549#define SEMC_IOCR_MUX_CLKX1_SHIFT (26U)
72556#define SEMC_IOCR_MUX_CLKX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK)
72557
72558#define SEMC_IOCR_CLKX0_AO_MASK (0x10000000U)
72559#define SEMC_IOCR_CLKX0_AO_SHIFT (28U)
72564#define SEMC_IOCR_CLKX0_AO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX0_AO_SHIFT)) & SEMC_IOCR_CLKX0_AO_MASK)
72565
72566#define SEMC_IOCR_CLKX1_AO_MASK (0x20000000U)
72567#define SEMC_IOCR_CLKX1_AO_SHIFT (29U)
72572#define SEMC_IOCR_CLKX1_AO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX1_AO_SHIFT)) & SEMC_IOCR_CLKX1_AO_MASK)
72578#define SEMC_BMCR0_WQOS_MASK (0xFU)
72579#define SEMC_BMCR0_WQOS_SHIFT (0U)
72582#define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
72583
72584#define SEMC_BMCR0_WAGE_MASK (0xF0U)
72585#define SEMC_BMCR0_WAGE_SHIFT (4U)
72588#define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
72589
72590#define SEMC_BMCR0_WSH_MASK (0xFF00U)
72591#define SEMC_BMCR0_WSH_SHIFT (8U)
72594#define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
72595
72596#define SEMC_BMCR0_WRWS_MASK (0xFF0000U)
72597#define SEMC_BMCR0_WRWS_SHIFT (16U)
72600#define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
72606#define SEMC_BMCR1_WQOS_MASK (0xFU)
72607#define SEMC_BMCR1_WQOS_SHIFT (0U)
72610#define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
72611
72612#define SEMC_BMCR1_WAGE_MASK (0xF0U)
72613#define SEMC_BMCR1_WAGE_SHIFT (4U)
72616#define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
72617
72618#define SEMC_BMCR1_WPH_MASK (0xFF00U)
72619#define SEMC_BMCR1_WPH_SHIFT (8U)
72622#define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
72623
72624#define SEMC_BMCR1_WRWS_MASK (0xFF0000U)
72625#define SEMC_BMCR1_WRWS_SHIFT (16U)
72628#define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
72629
72630#define SEMC_BMCR1_WBR_MASK (0xFF000000U)
72631#define SEMC_BMCR1_WBR_SHIFT (24U)
72634#define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
72640#define SEMC_BR_VLD_MASK (0x1U)
72641#define SEMC_BR_VLD_SHIFT (0U)
72646#define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
72647
72648#define SEMC_BR_MS_MASK (0x3EU)
72649#define SEMC_BR_MS_SHIFT (1U)
72673#define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
72674
72675#define SEMC_BR_BA_MASK (0xFFFFF000U)
72676#define SEMC_BR_BA_SHIFT (12U)
72679#define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
72682/* The count of SEMC_BR */
72683#define SEMC_BR_COUNT (9U)
72684
72688#define SEMC_DLLCR_DLLEN_MASK (0x1U)
72689#define SEMC_DLLCR_DLLEN_SHIFT (0U)
72694#define SEMC_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK)
72695
72696#define SEMC_DLLCR_DLLRESET_MASK (0x2U)
72697#define SEMC_DLLCR_DLLRESET_SHIFT (1U)
72702#define SEMC_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK)
72703
72704#define SEMC_DLLCR_SLVDLYTARGET_MASK (0x78U)
72705#define SEMC_DLLCR_SLVDLYTARGET_SHIFT (3U)
72708#define SEMC_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK)
72709
72710#define SEMC_DLLCR_OVRDEN_MASK (0x100U)
72711#define SEMC_DLLCR_OVRDEN_SHIFT (8U)
72716#define SEMC_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK)
72717
72718#define SEMC_DLLCR_OVRDVAL_MASK (0x7E00U)
72719#define SEMC_DLLCR_OVRDVAL_SHIFT (9U)
72722#define SEMC_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK)
72728#define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)
72729#define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)
72734#define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
72735
72736#define SEMC_INTEN_IPCMDERREN_MASK (0x2U)
72737#define SEMC_INTEN_IPCMDERREN_SHIFT (1U)
72742#define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
72743
72744#define SEMC_INTEN_AXICMDERREN_MASK (0x4U)
72745#define SEMC_INTEN_AXICMDERREN_SHIFT (2U)
72750#define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
72751
72752#define SEMC_INTEN_AXIBUSERREN_MASK (0x8U)
72753#define SEMC_INTEN_AXIBUSERREN_SHIFT (3U)
72758#define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
72759
72760#define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)
72761#define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)
72766#define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
72767
72768#define SEMC_INTEN_NDNOPENDEN_MASK (0x20U)
72769#define SEMC_INTEN_NDNOPENDEN_SHIFT (5U)
72774#define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
72780#define SEMC_INTR_IPCMDDONE_MASK (0x1U)
72781#define SEMC_INTR_IPCMDDONE_SHIFT (0U)
72786#define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
72787
72788#define SEMC_INTR_IPCMDERR_MASK (0x2U)
72789#define SEMC_INTR_IPCMDERR_SHIFT (1U)
72794#define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
72795
72796#define SEMC_INTR_AXICMDERR_MASK (0x4U)
72797#define SEMC_INTR_AXICMDERR_SHIFT (2U)
72802#define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
72803
72804#define SEMC_INTR_AXIBUSERR_MASK (0x8U)
72805#define SEMC_INTR_AXIBUSERR_SHIFT (3U)
72810#define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
72811
72812#define SEMC_INTR_NDPAGEEND_MASK (0x10U)
72813#define SEMC_INTR_NDPAGEEND_SHIFT (4U)
72818#define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
72819
72820#define SEMC_INTR_NDNOPEND_MASK (0x20U)
72821#define SEMC_INTR_NDNOPEND_SHIFT (5U)
72826#define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
72832#define SEMC_SDRAMCR0_PS_MASK (0x3U)
72833#define SEMC_SDRAMCR0_PS_SHIFT (0U)
72840#define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
72841
72842#define SEMC_SDRAMCR0_BL_MASK (0x70U)
72843#define SEMC_SDRAMCR0_BL_SHIFT (4U)
72854#define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
72855
72856#define SEMC_SDRAMCR0_COL8_MASK (0x80U)
72857#define SEMC_SDRAMCR0_COL8_SHIFT (7U)
72862#define SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK)
72863
72864#define SEMC_SDRAMCR0_COL_MASK (0x300U)
72865#define SEMC_SDRAMCR0_COL_SHIFT (8U)
72872#define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
72873
72874#define SEMC_SDRAMCR0_CL_MASK (0xC00U)
72875#define SEMC_SDRAMCR0_CL_SHIFT (10U)
72882#define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
72883
72884#define SEMC_SDRAMCR0_BANK2_MASK (0x4000U)
72885#define SEMC_SDRAMCR0_BANK2_SHIFT (14U)
72890#define SEMC_SDRAMCR0_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK)
72896#define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)
72897#define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)
72900#define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
72901
72902#define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)
72903#define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)
72906#define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
72907
72908#define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U)
72909#define SEMC_SDRAMCR1_RFRC_SHIFT (8U)
72912#define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
72913
72914#define SEMC_SDRAMCR1_WRC_MASK (0xE000U)
72915#define SEMC_SDRAMCR1_WRC_SHIFT (13U)
72918#define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
72919
72920#define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)
72921#define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)
72924#define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
72925
72926#define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)
72927#define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)
72930#define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
72936#define SEMC_SDRAMCR2_SRRC_MASK (0xFFU)
72937#define SEMC_SDRAMCR2_SRRC_SHIFT (0U)
72940#define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
72941
72942#define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)
72943#define SEMC_SDRAMCR2_REF2REF_SHIFT (8U)
72946#define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
72947
72948#define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)
72949#define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)
72952#define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
72953
72954#define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)
72955#define SEMC_SDRAMCR2_ITO_SHIFT (24U)
72960#define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
72966#define SEMC_SDRAMCR3_REN_MASK (0x1U)
72967#define SEMC_SDRAMCR3_REN_SHIFT (0U)
72972#define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
72973
72974#define SEMC_SDRAMCR3_REBL_MASK (0xEU)
72975#define SEMC_SDRAMCR3_REBL_SHIFT (1U)
72986#define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
72987
72988#define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)
72989#define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)
72994#define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
72995
72996#define SEMC_SDRAMCR3_RT_MASK (0xFF0000U)
72997#define SEMC_SDRAMCR3_RT_SHIFT (16U)
73002#define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
73003
73004#define SEMC_SDRAMCR3_UT_MASK (0xFF000000U)
73005#define SEMC_SDRAMCR3_UT_SHIFT (24U)
73010#define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
73016#define SEMC_NANDCR0_PS_MASK (0x1U)
73017#define SEMC_NANDCR0_PS_SHIFT (0U)
73022#define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
73023
73024#define SEMC_NANDCR0_SYNCEN_MASK (0x2U)
73025#define SEMC_NANDCR0_SYNCEN_SHIFT (1U)
73030#define SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK)
73031
73032#define SEMC_NANDCR0_BL_MASK (0x70U)
73033#define SEMC_NANDCR0_BL_SHIFT (4U)
73044#define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
73045
73046#define SEMC_NANDCR0_EDO_MASK (0x80U)
73047#define SEMC_NANDCR0_EDO_SHIFT (7U)
73052#define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
73053
73054#define SEMC_NANDCR0_COL_MASK (0x700U)
73055#define SEMC_NANDCR0_COL_SHIFT (8U)
73066#define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
73072#define SEMC_NANDCR1_CES_MASK (0xFU)
73073#define SEMC_NANDCR1_CES_SHIFT (0U)
73076#define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
73077
73078#define SEMC_NANDCR1_CEH_MASK (0xF0U)
73079#define SEMC_NANDCR1_CEH_SHIFT (4U)
73082#define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
73083
73084#define SEMC_NANDCR1_WEL_MASK (0xF00U)
73085#define SEMC_NANDCR1_WEL_SHIFT (8U)
73088#define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
73089
73090#define SEMC_NANDCR1_WEH_MASK (0xF000U)
73091#define SEMC_NANDCR1_WEH_SHIFT (12U)
73094#define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
73095
73096#define SEMC_NANDCR1_REL_MASK (0xF0000U)
73097#define SEMC_NANDCR1_REL_SHIFT (16U)
73100#define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
73101
73102#define SEMC_NANDCR1_REH_MASK (0xF00000U)
73103#define SEMC_NANDCR1_REH_SHIFT (20U)
73106#define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
73107
73108#define SEMC_NANDCR1_TA_MASK (0xF000000U)
73109#define SEMC_NANDCR1_TA_SHIFT (24U)
73112#define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
73113
73114#define SEMC_NANDCR1_CEITV_MASK (0xF0000000U)
73115#define SEMC_NANDCR1_CEITV_SHIFT (28U)
73118#define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
73124#define SEMC_NANDCR2_TWHR_MASK (0x3FU)
73125#define SEMC_NANDCR2_TWHR_SHIFT (0U)
73128#define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
73129
73130#define SEMC_NANDCR2_TRHW_MASK (0xFC0U)
73131#define SEMC_NANDCR2_TRHW_SHIFT (6U)
73134#define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
73135
73136#define SEMC_NANDCR2_TADL_MASK (0x3F000U)
73137#define SEMC_NANDCR2_TADL_SHIFT (12U)
73140#define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
73141
73142#define SEMC_NANDCR2_TRR_MASK (0xFC0000U)
73143#define SEMC_NANDCR2_TRR_SHIFT (18U)
73146#define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
73147
73148#define SEMC_NANDCR2_TWB_MASK (0x3F000000U)
73149#define SEMC_NANDCR2_TWB_SHIFT (24U)
73152#define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
73158#define SEMC_NANDCR3_NDOPT1_MASK (0x1U)
73159#define SEMC_NANDCR3_NDOPT1_SHIFT (0U)
73162#define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
73163
73164#define SEMC_NANDCR3_NDOPT2_MASK (0x2U)
73165#define SEMC_NANDCR3_NDOPT2_SHIFT (1U)
73168#define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
73169
73170#define SEMC_NANDCR3_NDOPT3_MASK (0x4U)
73171#define SEMC_NANDCR3_NDOPT3_SHIFT (2U)
73174#define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
73175
73176#define SEMC_NANDCR3_CLE_MASK (0x8U)
73177#define SEMC_NANDCR3_CLE_SHIFT (3U)
73180#define SEMC_NANDCR3_CLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK)
73181
73182#define SEMC_NANDCR3_RDS_MASK (0xF0000U)
73183#define SEMC_NANDCR3_RDS_SHIFT (16U)
73186#define SEMC_NANDCR3_RDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK)
73187
73188#define SEMC_NANDCR3_RDH_MASK (0xF00000U)
73189#define SEMC_NANDCR3_RDH_SHIFT (20U)
73192#define SEMC_NANDCR3_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK)
73193
73194#define SEMC_NANDCR3_WDS_MASK (0xF000000U)
73195#define SEMC_NANDCR3_WDS_SHIFT (24U)
73198#define SEMC_NANDCR3_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK)
73199
73200#define SEMC_NANDCR3_WDH_MASK (0xF0000000U)
73201#define SEMC_NANDCR3_WDH_SHIFT (28U)
73204#define SEMC_NANDCR3_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK)
73210#define SEMC_NORCR0_PS_MASK (0x1U)
73211#define SEMC_NORCR0_PS_SHIFT (0U)
73216#define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
73217
73218#define SEMC_NORCR0_SYNCEN_MASK (0x2U)
73219#define SEMC_NORCR0_SYNCEN_SHIFT (1U)
73224#define SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK)
73225
73226#define SEMC_NORCR0_BL_MASK (0x70U)
73227#define SEMC_NORCR0_BL_SHIFT (4U)
73238#define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
73239
73240#define SEMC_NORCR0_AM_MASK (0x300U)
73241#define SEMC_NORCR0_AM_SHIFT (8U)
73248#define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
73249
73250#define SEMC_NORCR0_ADVP_MASK (0x400U)
73251#define SEMC_NORCR0_ADVP_SHIFT (10U)
73256#define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
73257
73258#define SEMC_NORCR0_ADVH_MASK (0x800U)
73259#define SEMC_NORCR0_ADVH_SHIFT (11U)
73264#define SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK)
73265
73266#define SEMC_NORCR0_COL_MASK (0xF000U)
73267#define SEMC_NORCR0_COL_SHIFT (12U)
73286#define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
73292#define SEMC_NORCR1_CES_MASK (0xFU)
73293#define SEMC_NORCR1_CES_SHIFT (0U)
73296#define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
73297
73298#define SEMC_NORCR1_CEH_MASK (0xF0U)
73299#define SEMC_NORCR1_CEH_SHIFT (4U)
73302#define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
73303
73304#define SEMC_NORCR1_AS_MASK (0xF00U)
73305#define SEMC_NORCR1_AS_SHIFT (8U)
73308#define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
73309
73310#define SEMC_NORCR1_AH_MASK (0xF000U)
73311#define SEMC_NORCR1_AH_SHIFT (12U)
73314#define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
73315
73316#define SEMC_NORCR1_WEL_MASK (0xF0000U)
73317#define SEMC_NORCR1_WEL_SHIFT (16U)
73320#define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
73321
73322#define SEMC_NORCR1_WEH_MASK (0xF00000U)
73323#define SEMC_NORCR1_WEH_SHIFT (20U)
73326#define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
73327
73328#define SEMC_NORCR1_REL_MASK (0xF000000U)
73329#define SEMC_NORCR1_REL_SHIFT (24U)
73332#define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
73333
73334#define SEMC_NORCR1_REH_MASK (0xF0000000U)
73335#define SEMC_NORCR1_REH_SHIFT (28U)
73338#define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
73344#define SEMC_NORCR2_TA_MASK (0xF00U)
73345#define SEMC_NORCR2_TA_SHIFT (8U)
73348#define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
73349
73350#define SEMC_NORCR2_AWDH_MASK (0xF000U)
73351#define SEMC_NORCR2_AWDH_SHIFT (12U)
73354#define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
73355
73356#define SEMC_NORCR2_LC_MASK (0xF0000U)
73357#define SEMC_NORCR2_LC_SHIFT (16U)
73360#define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
73361
73362#define SEMC_NORCR2_RD_MASK (0xF00000U)
73363#define SEMC_NORCR2_RD_SHIFT (20U)
73366#define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
73367
73368#define SEMC_NORCR2_CEITV_MASK (0xF000000U)
73369#define SEMC_NORCR2_CEITV_SHIFT (24U)
73372#define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
73373
73374#define SEMC_NORCR2_RDH_MASK (0xF0000000U)
73375#define SEMC_NORCR2_RDH_SHIFT (28U)
73378#define SEMC_NORCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
73384#define SEMC_NORCR3_ASSR_MASK (0xFU)
73385#define SEMC_NORCR3_ASSR_SHIFT (0U)
73388#define SEMC_NORCR3_ASSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK)
73389
73390#define SEMC_NORCR3_AHSR_MASK (0xF0U)
73391#define SEMC_NORCR3_AHSR_SHIFT (4U)
73394#define SEMC_NORCR3_AHSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK)
73400#define SEMC_SRAMCR0_PS_MASK (0x1U)
73401#define SEMC_SRAMCR0_PS_SHIFT (0U)
73406#define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
73407
73408#define SEMC_SRAMCR0_SYNCEN_MASK (0x2U)
73409#define SEMC_SRAMCR0_SYNCEN_SHIFT (1U)
73414#define SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK)
73415
73416#define SEMC_SRAMCR0_WAITEN_MASK (0x4U)
73417#define SEMC_SRAMCR0_WAITEN_SHIFT (2U)
73422#define SEMC_SRAMCR0_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITEN_SHIFT)) & SEMC_SRAMCR0_WAITEN_MASK)
73423
73424#define SEMC_SRAMCR0_WAITSP_MASK (0x8U)
73425#define SEMC_SRAMCR0_WAITSP_SHIFT (3U)
73430#define SEMC_SRAMCR0_WAITSP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITSP_SHIFT)) & SEMC_SRAMCR0_WAITSP_MASK)
73431
73432#define SEMC_SRAMCR0_BL_MASK (0x70U)
73433#define SEMC_SRAMCR0_BL_SHIFT (4U)
73444#define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
73445
73446#define SEMC_SRAMCR0_AM_MASK (0x300U)
73447#define SEMC_SRAMCR0_AM_SHIFT (8U)
73454#define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
73455
73456#define SEMC_SRAMCR0_ADVP_MASK (0x400U)
73457#define SEMC_SRAMCR0_ADVP_SHIFT (10U)
73462#define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
73463
73464#define SEMC_SRAMCR0_ADVH_MASK (0x800U)
73465#define SEMC_SRAMCR0_ADVH_SHIFT (11U)
73470#define SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK)
73471
73472#define SEMC_SRAMCR0_COL_MASK (0xF000U)
73473#define SEMC_SRAMCR0_COL_SHIFT (12U)
73492#define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
73498#define SEMC_SRAMCR1_CES_MASK (0xFU)
73499#define SEMC_SRAMCR1_CES_SHIFT (0U)
73502#define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
73503
73504#define SEMC_SRAMCR1_CEH_MASK (0xF0U)
73505#define SEMC_SRAMCR1_CEH_SHIFT (4U)
73508#define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
73509
73510#define SEMC_SRAMCR1_AS_MASK (0xF00U)
73511#define SEMC_SRAMCR1_AS_SHIFT (8U)
73514#define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
73515
73516#define SEMC_SRAMCR1_AH_MASK (0xF000U)
73517#define SEMC_SRAMCR1_AH_SHIFT (12U)
73520#define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
73521
73522#define SEMC_SRAMCR1_WEL_MASK (0xF0000U)
73523#define SEMC_SRAMCR1_WEL_SHIFT (16U)
73526#define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
73527
73528#define SEMC_SRAMCR1_WEH_MASK (0xF00000U)
73529#define SEMC_SRAMCR1_WEH_SHIFT (20U)
73532#define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
73533
73534#define SEMC_SRAMCR1_REL_MASK (0xF000000U)
73535#define SEMC_SRAMCR1_REL_SHIFT (24U)
73538#define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
73539
73540#define SEMC_SRAMCR1_REH_MASK (0xF0000000U)
73541#define SEMC_SRAMCR1_REH_SHIFT (28U)
73544#define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
73550#define SEMC_SRAMCR2_WDS_MASK (0xFU)
73551#define SEMC_SRAMCR2_WDS_SHIFT (0U)
73554#define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
73555
73556#define SEMC_SRAMCR2_WDH_MASK (0xF0U)
73557#define SEMC_SRAMCR2_WDH_SHIFT (4U)
73560#define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
73561
73562#define SEMC_SRAMCR2_TA_MASK (0xF00U)
73563#define SEMC_SRAMCR2_TA_SHIFT (8U)
73566#define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
73567
73568#define SEMC_SRAMCR2_AWDH_MASK (0xF000U)
73569#define SEMC_SRAMCR2_AWDH_SHIFT (12U)
73572#define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
73573
73574#define SEMC_SRAMCR2_LC_MASK (0xF0000U)
73575#define SEMC_SRAMCR2_LC_SHIFT (16U)
73578#define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
73579
73580#define SEMC_SRAMCR2_RD_MASK (0xF00000U)
73581#define SEMC_SRAMCR2_RD_SHIFT (20U)
73584#define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
73585
73586#define SEMC_SRAMCR2_CEITV_MASK (0xF000000U)
73587#define SEMC_SRAMCR2_CEITV_SHIFT (24U)
73590#define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
73591
73592#define SEMC_SRAMCR2_RDH_MASK (0xF0000000U)
73593#define SEMC_SRAMCR2_RDH_SHIFT (28U)
73596#define SEMC_SRAMCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK)
73602#define SEMC_DBICR0_PS_MASK (0x1U)
73603#define SEMC_DBICR0_PS_SHIFT (0U)
73608#define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
73609
73610#define SEMC_DBICR0_BL_MASK (0x70U)
73611#define SEMC_DBICR0_BL_SHIFT (4U)
73622#define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
73623
73624#define SEMC_DBICR0_COL_MASK (0xF000U)
73625#define SEMC_DBICR0_COL_SHIFT (12U)
73644#define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
73650#define SEMC_DBICR1_CES_MASK (0xFU)
73651#define SEMC_DBICR1_CES_SHIFT (0U)
73654#define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
73655
73656#define SEMC_DBICR1_CEH_MASK (0xF0U)
73657#define SEMC_DBICR1_CEH_SHIFT (4U)
73660#define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
73661
73662#define SEMC_DBICR1_WEL_MASK (0xF00U)
73663#define SEMC_DBICR1_WEL_SHIFT (8U)
73666#define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
73667
73668#define SEMC_DBICR1_WEH_MASK (0xF000U)
73669#define SEMC_DBICR1_WEH_SHIFT (12U)
73672#define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
73673
73674#define SEMC_DBICR1_REL_MASK (0x7F0000U)
73675#define SEMC_DBICR1_REL_SHIFT (16U)
73678#define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
73679
73680#define SEMC_DBICR1_REH_MASK (0x7F000000U)
73681#define SEMC_DBICR1_REH_SHIFT (24U)
73684#define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
73690#define SEMC_DBICR2_CEITV_MASK (0xFU)
73691#define SEMC_DBICR2_CEITV_SHIFT (0U)
73694#define SEMC_DBICR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR2_CEITV_SHIFT)) & SEMC_DBICR2_CEITV_MASK)
73700#define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)
73701#define SEMC_IPCR0_SA_SHIFT (0U)
73704#define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
73710#define SEMC_IPCR1_DATSZ_MASK (0x7U)
73711#define SEMC_IPCR1_DATSZ_SHIFT (0U)
73722#define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
73723
73724#define SEMC_IPCR1_NAND_EXT_ADDR_MASK (0xFF00U)
73725#define SEMC_IPCR1_NAND_EXT_ADDR_SHIFT (8U)
73728#define SEMC_IPCR1_NAND_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK)
73734#define SEMC_IPCR2_BM0_MASK (0x1U)
73735#define SEMC_IPCR2_BM0_SHIFT (0U)
73740#define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
73741
73742#define SEMC_IPCR2_BM1_MASK (0x2U)
73743#define SEMC_IPCR2_BM1_SHIFT (1U)
73748#define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
73749
73750#define SEMC_IPCR2_BM2_MASK (0x4U)
73751#define SEMC_IPCR2_BM2_SHIFT (2U)
73756#define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
73757
73758#define SEMC_IPCR2_BM3_MASK (0x8U)
73759#define SEMC_IPCR2_BM3_SHIFT (3U)
73764#define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
73770#define SEMC_IPCMD_CMD_MASK (0xFFFFU)
73771#define SEMC_IPCMD_CMD_SHIFT (0U)
73772#define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
73773
73774#define SEMC_IPCMD_KEY_MASK (0xFFFF0000U)
73775#define SEMC_IPCMD_KEY_SHIFT (16U)
73776#define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
73782#define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)
73783#define SEMC_IPTXDAT_DAT_SHIFT (0U)
73784#define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
73790#define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)
73791#define SEMC_IPRXDAT_DAT_SHIFT (0U)
73792#define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
73798#define SEMC_STS0_IDLE_MASK (0x1U)
73799#define SEMC_STS0_IDLE_SHIFT (0U)
73802#define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
73803
73804#define SEMC_STS0_NARDY_MASK (0x2U)
73805#define SEMC_STS0_NARDY_SHIFT (1U)
73810#define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
73816#define SEMC_STS2_NDWRPEND_MASK (0x8U)
73817#define SEMC_STS2_NDWRPEND_SHIFT (3U)
73822#define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
73828#define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)
73829#define SEMC_STS12_NDADDR_SHIFT (0U)
73832#define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
73838#define SEMC_STS13_SLVLOCK_MASK (0x1U)
73839#define SEMC_STS13_SLVLOCK_SHIFT (0U)
73844#define SEMC_STS13_SLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK)
73845
73846#define SEMC_STS13_REFLOCK_MASK (0x2U)
73847#define SEMC_STS13_REFLOCK_SHIFT (1U)
73852#define SEMC_STS13_REFLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK)
73853
73854#define SEMC_STS13_SLVSEL_MASK (0xFCU)
73855#define SEMC_STS13_SLVSEL_SHIFT (2U)
73858#define SEMC_STS13_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK)
73859
73860#define SEMC_STS13_REFSEL_MASK (0x3F00U)
73861#define SEMC_STS13_REFSEL_SHIFT (8U)
73864#define SEMC_STS13_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK)
73870#define SEMC_BR9_VLD_MASK (0x1U)
73871#define SEMC_BR9_VLD_SHIFT (0U)
73876#define SEMC_BR9_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_VLD_SHIFT)) & SEMC_BR9_VLD_MASK)
73877
73878#define SEMC_BR9_MS_MASK (0x3EU)
73879#define SEMC_BR9_MS_SHIFT (1U)
73903#define SEMC_BR9_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_MS_SHIFT)) & SEMC_BR9_MS_MASK)
73904
73905#define SEMC_BR9_BA_MASK (0xFFFFF000U)
73906#define SEMC_BR9_BA_SHIFT (12U)
73909#define SEMC_BR9_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_BA_SHIFT)) & SEMC_BR9_BA_MASK)
73915#define SEMC_BR10_VLD_MASK (0x1U)
73916#define SEMC_BR10_VLD_SHIFT (0U)
73921#define SEMC_BR10_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_VLD_SHIFT)) & SEMC_BR10_VLD_MASK)
73922
73923#define SEMC_BR10_MS_MASK (0x3EU)
73924#define SEMC_BR10_MS_SHIFT (1U)
73948#define SEMC_BR10_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_MS_SHIFT)) & SEMC_BR10_MS_MASK)
73949
73950#define SEMC_BR10_BA_MASK (0xFFFFF000U)
73951#define SEMC_BR10_BA_SHIFT (12U)
73954#define SEMC_BR10_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_BA_SHIFT)) & SEMC_BR10_BA_MASK)
73960#define SEMC_BR11_VLD_MASK (0x1U)
73961#define SEMC_BR11_VLD_SHIFT (0U)
73966#define SEMC_BR11_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_VLD_SHIFT)) & SEMC_BR11_VLD_MASK)
73967
73968#define SEMC_BR11_MS_MASK (0x3EU)
73969#define SEMC_BR11_MS_SHIFT (1U)
73993#define SEMC_BR11_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_MS_SHIFT)) & SEMC_BR11_MS_MASK)
73994
73995#define SEMC_BR11_BA_MASK (0xFFFFF000U)
73996#define SEMC_BR11_BA_SHIFT (12U)
73999#define SEMC_BR11_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_BA_SHIFT)) & SEMC_BR11_BA_MASK)
74005#define SEMC_SRAMCR4_PS_MASK (0x1U)
74006#define SEMC_SRAMCR4_PS_SHIFT (0U)
74011#define SEMC_SRAMCR4_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_PS_SHIFT)) & SEMC_SRAMCR4_PS_MASK)
74012
74013#define SEMC_SRAMCR4_SYNCEN_MASK (0x2U)
74014#define SEMC_SRAMCR4_SYNCEN_SHIFT (1U)
74019#define SEMC_SRAMCR4_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_SYNCEN_SHIFT)) & SEMC_SRAMCR4_SYNCEN_MASK)
74020
74021#define SEMC_SRAMCR4_WAITEN_MASK (0x4U)
74022#define SEMC_SRAMCR4_WAITEN_SHIFT (2U)
74027#define SEMC_SRAMCR4_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITEN_SHIFT)) & SEMC_SRAMCR4_WAITEN_MASK)
74028
74029#define SEMC_SRAMCR4_WAITSP_MASK (0x8U)
74030#define SEMC_SRAMCR4_WAITSP_SHIFT (3U)
74035#define SEMC_SRAMCR4_WAITSP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITSP_SHIFT)) & SEMC_SRAMCR4_WAITSP_MASK)
74036
74037#define SEMC_SRAMCR4_BL_MASK (0x70U)
74038#define SEMC_SRAMCR4_BL_SHIFT (4U)
74049#define SEMC_SRAMCR4_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
74050
74051#define SEMC_SRAMCR4_AM_MASK (0x300U)
74052#define SEMC_SRAMCR4_AM_SHIFT (8U)
74059#define SEMC_SRAMCR4_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_AM_SHIFT)) & SEMC_SRAMCR4_AM_MASK)
74060
74061#define SEMC_SRAMCR4_ADVP_MASK (0x400U)
74062#define SEMC_SRAMCR4_ADVP_SHIFT (10U)
74067#define SEMC_SRAMCR4_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVP_SHIFT)) & SEMC_SRAMCR4_ADVP_MASK)
74068
74069#define SEMC_SRAMCR4_ADVH_MASK (0x800U)
74070#define SEMC_SRAMCR4_ADVH_SHIFT (11U)
74075#define SEMC_SRAMCR4_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVH_SHIFT)) & SEMC_SRAMCR4_ADVH_MASK)
74076
74077#define SEMC_SRAMCR4_COL_MASK (0xF000U)
74078#define SEMC_SRAMCR4_COL_SHIFT (12U)
74097#define SEMC_SRAMCR4_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_COL_SHIFT)) & SEMC_SRAMCR4_COL_MASK)
74103#define SEMC_SRAMCR5_CES_MASK (0xFU)
74104#define SEMC_SRAMCR5_CES_SHIFT (0U)
74107#define SEMC_SRAMCR5_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CES_SHIFT)) & SEMC_SRAMCR5_CES_MASK)
74108
74109#define SEMC_SRAMCR5_CEH_MASK (0xF0U)
74110#define SEMC_SRAMCR5_CEH_SHIFT (4U)
74113#define SEMC_SRAMCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_SRAMCR5_CEH_MASK)
74114
74115#define SEMC_SRAMCR5_AS_MASK (0xF00U)
74116#define SEMC_SRAMCR5_AS_SHIFT (8U)
74119#define SEMC_SRAMCR5_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AS_SHIFT)) & SEMC_SRAMCR5_AS_MASK)
74120
74121#define SEMC_SRAMCR5_AH_MASK (0xF000U)
74122#define SEMC_SRAMCR5_AH_SHIFT (12U)
74125#define SEMC_SRAMCR5_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AH_SHIFT)) & SEMC_SRAMCR5_AH_MASK)
74126
74127#define SEMC_SRAMCR5_WEL_MASK (0xF0000U)
74128#define SEMC_SRAMCR5_WEL_SHIFT (16U)
74131#define SEMC_SRAMCR5_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEL_SHIFT)) & SEMC_SRAMCR5_WEL_MASK)
74132
74133#define SEMC_SRAMCR5_WEH_MASK (0xF00000U)
74134#define SEMC_SRAMCR5_WEH_SHIFT (20U)
74137#define SEMC_SRAMCR5_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEH_SHIFT)) & SEMC_SRAMCR5_WEH_MASK)
74138
74139#define SEMC_SRAMCR5_REL_MASK (0xF000000U)
74140#define SEMC_SRAMCR5_REL_SHIFT (24U)
74143#define SEMC_SRAMCR5_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REL_SHIFT)) & SEMC_SRAMCR5_REL_MASK)
74144
74145#define SEMC_SRAMCR5_REH_MASK (0xF0000000U)
74146#define SEMC_SRAMCR5_REH_SHIFT (28U)
74149#define SEMC_SRAMCR5_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REH_SHIFT)) & SEMC_SRAMCR5_REH_MASK)
74155#define SEMC_SRAMCR6_WDS_MASK (0xFU)
74156#define SEMC_SRAMCR6_WDS_SHIFT (0U)
74159#define SEMC_SRAMCR6_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDS_SHIFT)) & SEMC_SRAMCR6_WDS_MASK)
74160
74161#define SEMC_SRAMCR6_WDH_MASK (0xF0U)
74162#define SEMC_SRAMCR6_WDH_SHIFT (4U)
74165#define SEMC_SRAMCR6_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDH_SHIFT)) & SEMC_SRAMCR6_WDH_MASK)
74166
74167#define SEMC_SRAMCR6_TA_MASK (0xF00U)
74168#define SEMC_SRAMCR6_TA_SHIFT (8U)
74171#define SEMC_SRAMCR6_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_TA_SHIFT)) & SEMC_SRAMCR6_TA_MASK)
74172
74173#define SEMC_SRAMCR6_AWDH_MASK (0xF000U)
74174#define SEMC_SRAMCR6_AWDH_SHIFT (12U)
74177#define SEMC_SRAMCR6_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_AWDH_SHIFT)) & SEMC_SRAMCR6_AWDH_MASK)
74178
74179#define SEMC_SRAMCR6_LC_MASK (0xF0000U)
74180#define SEMC_SRAMCR6_LC_SHIFT (16U)
74183#define SEMC_SRAMCR6_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_LC_SHIFT)) & SEMC_SRAMCR6_LC_MASK)
74184
74185#define SEMC_SRAMCR6_RD_MASK (0xF00000U)
74186#define SEMC_SRAMCR6_RD_SHIFT (20U)
74189#define SEMC_SRAMCR6_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RD_SHIFT)) & SEMC_SRAMCR6_RD_MASK)
74190
74191#define SEMC_SRAMCR6_CEITV_MASK (0xF000000U)
74192#define SEMC_SRAMCR6_CEITV_SHIFT (24U)
74195#define SEMC_SRAMCR6_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_CEITV_SHIFT)) & SEMC_SRAMCR6_CEITV_MASK)
74196
74197#define SEMC_SRAMCR6_RDH_MASK (0xF0000000U)
74198#define SEMC_SRAMCR6_RDH_SHIFT (28U)
74201#define SEMC_SRAMCR6_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RDH_SHIFT)) & SEMC_SRAMCR6_RDH_MASK)
74207#define SEMC_DCCR_SDRAMEN_MASK (0x1U)
74208#define SEMC_DCCR_SDRAMEN_SHIFT (0U)
74213#define SEMC_DCCR_SDRAMEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMEN_SHIFT)) & SEMC_DCCR_SDRAMEN_MASK)
74214
74215#define SEMC_DCCR_SDRAMVAL_MASK (0x3EU)
74216#define SEMC_DCCR_SDRAMVAL_SHIFT (1U)
74219#define SEMC_DCCR_SDRAMVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMVAL_SHIFT)) & SEMC_DCCR_SDRAMVAL_MASK)
74220
74221#define SEMC_DCCR_NOREN_MASK (0x100U)
74222#define SEMC_DCCR_NOREN_SHIFT (8U)
74227#define SEMC_DCCR_NOREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NOREN_SHIFT)) & SEMC_DCCR_NOREN_MASK)
74228
74229#define SEMC_DCCR_NORVAL_MASK (0x3E00U)
74230#define SEMC_DCCR_NORVAL_SHIFT (9U)
74233#define SEMC_DCCR_NORVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NORVAL_SHIFT)) & SEMC_DCCR_NORVAL_MASK)
74234
74235#define SEMC_DCCR_SRAM0EN_MASK (0x10000U)
74236#define SEMC_DCCR_SRAM0EN_SHIFT (16U)
74241#define SEMC_DCCR_SRAM0EN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0EN_SHIFT)) & SEMC_DCCR_SRAM0EN_MASK)
74242
74243#define SEMC_DCCR_SRAM0VAL_MASK (0x3E0000U)
74244#define SEMC_DCCR_SRAM0VAL_SHIFT (17U)
74247#define SEMC_DCCR_SRAM0VAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0VAL_SHIFT)) & SEMC_DCCR_SRAM0VAL_MASK)
74248
74249#define SEMC_DCCR_SRAMXEN_MASK (0x1000000U)
74250#define SEMC_DCCR_SRAMXEN_SHIFT (24U)
74255#define SEMC_DCCR_SRAMXEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXEN_SHIFT)) & SEMC_DCCR_SRAMXEN_MASK)
74256
74257#define SEMC_DCCR_SRAMXVAL_MASK (0x3E000000U)
74258#define SEMC_DCCR_SRAMXVAL_SHIFT (25U)
74261#define SEMC_DCCR_SRAMXVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXVAL_SHIFT)) & SEMC_DCCR_SRAMXVAL_MASK) /* end of group SEMC_Register_Masks */
74268
74269
74270/* SEMC - Peripheral instance base addresses */
74272#define SEMC_BASE (0x400D4000u)
74274#define SEMC ((SEMC_Type *)SEMC_BASE)
74276#define SEMC_BASE_ADDRS { SEMC_BASE }
74278#define SEMC_BASE_PTRS { SEMC }
74280#define SEMC_IRQS { SEMC_IRQn }
74281 /* end of group SEMC_Peripheral_Access_Layer */
74285
74286
74287/* ----------------------------------------------------------------------------
74288 -- SNVS Peripheral Access Layer
74289 ---------------------------------------------------------------------------- */
74290
74297typedef struct {
74298 __IO uint32_t HPLR;
74299 __IO uint32_t HPCOMR;
74300 __IO uint32_t HPCR;
74301 __IO uint32_t HPSICR;
74302 __IO uint32_t HPSVCR;
74303 __IO uint32_t HPSR;
74304 __IO uint32_t HPSVSR;
74305 __IO uint32_t HPHACIVR;
74306 __I uint32_t HPHACR;
74307 __IO uint32_t HPRTCMR;
74308 __IO uint32_t HPRTCLR;
74309 __IO uint32_t HPTAMR;
74310 __IO uint32_t HPTALR;
74311 __IO uint32_t LPLR;
74312 __IO uint32_t LPCR;
74313 __IO uint32_t LPMKCR;
74314 __IO uint32_t LPSVCR;
74315 __IO uint32_t LPTGFCR;
74316 __IO uint32_t LPTDCR;
74317 __IO uint32_t LPSR;
74318 __IO uint32_t LPSRTCMR;
74319 __IO uint32_t LPSRTCLR;
74320 __IO uint32_t LPTAR;
74321 __IO uint32_t LPSMCMR;
74322 __IO uint32_t LPSMCLR;
74323 __IO uint32_t LPLVDR;
74324 __IO uint32_t LPGPR0_LEGACY_ALIAS;
74325 __IO uint32_t LPZMKR[8];
74326 uint8_t RESERVED_0[4];
74327 __IO uint32_t LPGPR_ALIAS[4];
74328 __IO uint32_t LPTDC2R;
74329 __IO uint32_t LPTDSR;
74330 __IO uint32_t LPTGF1CR;
74331 __IO uint32_t LPTGF2CR;
74332 uint8_t RESERVED_1[16];
74333 __O uint32_t LPATCR[5];
74334 uint8_t RESERVED_2[12];
74335 __IO uint32_t LPATCTLR;
74336 __IO uint32_t LPATCLKR;
74337 __IO uint32_t LPATRC1R;
74338 __IO uint32_t LPATRC2R;
74339 uint8_t RESERVED_3[16];
74340 __IO uint32_t LPGPR[4];
74341 uint8_t RESERVED_4[2792];
74342 __I uint32_t HPVIDR1;
74343 __I uint32_t HPVIDR2;
74344} SNVS_Type;
74345
74346/* ----------------------------------------------------------------------------
74347 -- SNVS Register Masks
74348 ---------------------------------------------------------------------------- */
74349
74358#define SNVS_HPLR_ZMK_WSL_MASK (0x1U)
74359#define SNVS_HPLR_ZMK_WSL_SHIFT (0U)
74364#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
74365
74366#define SNVS_HPLR_ZMK_RSL_MASK (0x2U)
74367#define SNVS_HPLR_ZMK_RSL_SHIFT (1U)
74372#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
74373
74374#define SNVS_HPLR_SRTC_SL_MASK (0x4U)
74375#define SNVS_HPLR_SRTC_SL_SHIFT (2U)
74380#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
74381
74382#define SNVS_HPLR_LPCALB_SL_MASK (0x8U)
74383#define SNVS_HPLR_LPCALB_SL_SHIFT (3U)
74388#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
74389
74390#define SNVS_HPLR_MC_SL_MASK (0x10U)
74391#define SNVS_HPLR_MC_SL_SHIFT (4U)
74396#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
74397
74398#define SNVS_HPLR_GPR_SL_MASK (0x20U)
74399#define SNVS_HPLR_GPR_SL_SHIFT (5U)
74404#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
74405
74406#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U)
74407#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U)
74412#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
74413
74414#define SNVS_HPLR_LPTGFCR_SL_MASK (0x80U)
74415#define SNVS_HPLR_LPTGFCR_SL_SHIFT (7U)
74420#define SNVS_HPLR_LPTGFCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTGFCR_SL_SHIFT)) & SNVS_HPLR_LPTGFCR_SL_MASK)
74421
74422#define SNVS_HPLR_LPSECR_SL_MASK (0x100U)
74423#define SNVS_HPLR_LPSECR_SL_SHIFT (8U)
74428#define SNVS_HPLR_LPSECR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)
74429
74430#define SNVS_HPLR_MKS_SL_MASK (0x200U)
74431#define SNVS_HPLR_MKS_SL_SHIFT (9U)
74436#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
74437
74438#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U)
74439#define SNVS_HPLR_HPSVCR_L_SHIFT (16U)
74444#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
74445
74446#define SNVS_HPLR_HPSICR_L_MASK (0x20000U)
74447#define SNVS_HPLR_HPSICR_L_SHIFT (17U)
74452#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
74453
74454#define SNVS_HPLR_HAC_L_MASK (0x40000U)
74455#define SNVS_HPLR_HAC_L_SHIFT (18U)
74460#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
74461
74462#define SNVS_HPLR_AT1_SL_MASK (0x1000000U)
74463#define SNVS_HPLR_AT1_SL_SHIFT (24U)
74468#define SNVS_HPLR_AT1_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT1_SL_SHIFT)) & SNVS_HPLR_AT1_SL_MASK)
74469
74470#define SNVS_HPLR_AT2_SL_MASK (0x2000000U)
74471#define SNVS_HPLR_AT2_SL_SHIFT (25U)
74476#define SNVS_HPLR_AT2_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT2_SL_SHIFT)) & SNVS_HPLR_AT2_SL_MASK)
74477
74478#define SNVS_HPLR_AT3_SL_MASK (0x4000000U)
74479#define SNVS_HPLR_AT3_SL_SHIFT (26U)
74484#define SNVS_HPLR_AT3_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT3_SL_SHIFT)) & SNVS_HPLR_AT3_SL_MASK)
74485
74486#define SNVS_HPLR_AT4_SL_MASK (0x8000000U)
74487#define SNVS_HPLR_AT4_SL_SHIFT (27U)
74492#define SNVS_HPLR_AT4_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT4_SL_SHIFT)) & SNVS_HPLR_AT4_SL_MASK)
74493
74494#define SNVS_HPLR_AT5_SL_MASK (0x10000000U)
74495#define SNVS_HPLR_AT5_SL_SHIFT (28U)
74500#define SNVS_HPLR_AT5_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT5_SL_SHIFT)) & SNVS_HPLR_AT5_SL_MASK)
74506#define SNVS_HPCOMR_SSM_ST_MASK (0x1U)
74507#define SNVS_HPCOMR_SSM_ST_SHIFT (0U)
74508#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
74509
74510#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)
74511#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)
74516#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
74517
74518#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)
74519#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)
74524#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
74525
74526#define SNVS_HPCOMR_LP_SWR_MASK (0x10U)
74527#define SNVS_HPCOMR_LP_SWR_SHIFT (4U)
74532#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
74533
74534#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)
74535#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)
74540#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
74541
74542#define SNVS_HPCOMR_SW_SV_MASK (0x100U)
74543#define SNVS_HPCOMR_SW_SV_SHIFT (8U)
74544#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
74545
74546#define SNVS_HPCOMR_SW_FSV_MASK (0x200U)
74547#define SNVS_HPCOMR_SW_FSV_SHIFT (9U)
74548#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
74549
74550#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U)
74551#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U)
74552#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
74553
74554#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)
74555#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)
74560#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
74561
74562#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U)
74563#define SNVS_HPCOMR_MKS_EN_SHIFT (13U)
74568#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
74569
74570#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U)
74571#define SNVS_HPCOMR_HAC_EN_SHIFT (16U)
74576#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
74577
74578#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)
74579#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)
74584#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
74585
74586#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)
74587#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)
74592#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
74593
74594#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)
74595#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U)
74596#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
74597
74598#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
74599#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
74600#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
74606#define SNVS_HPCR_RTC_EN_MASK (0x1U)
74607#define SNVS_HPCR_RTC_EN_SHIFT (0U)
74612#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
74613
74614#define SNVS_HPCR_HPTA_EN_MASK (0x2U)
74615#define SNVS_HPCR_HPTA_EN_SHIFT (1U)
74620#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
74621
74622#define SNVS_HPCR_DIS_PI_MASK (0x4U)
74623#define SNVS_HPCR_DIS_PI_SHIFT (2U)
74628#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
74629
74630#define SNVS_HPCR_PI_EN_MASK (0x8U)
74631#define SNVS_HPCR_PI_EN_SHIFT (3U)
74636#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
74637
74638#define SNVS_HPCR_PI_FREQ_MASK (0xF0U)
74639#define SNVS_HPCR_PI_FREQ_SHIFT (4U)
74658#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
74659
74660#define SNVS_HPCR_HPCALB_EN_MASK (0x100U)
74661#define SNVS_HPCR_HPCALB_EN_SHIFT (8U)
74666#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
74667
74668#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
74669#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
74680#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
74681
74682#define SNVS_HPCR_HP_TS_MASK (0x10000U)
74683#define SNVS_HPCR_HP_TS_SHIFT (16U)
74688#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
74689
74690#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)
74691#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U)
74692#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
74693
74694#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U)
74695#define SNVS_HPCR_BTN_MASK_SHIFT (27U)
74696#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
74702#define SNVS_HPSICR_CAAM_EN_MASK (0x1U)
74703#define SNVS_HPSICR_CAAM_EN_SHIFT (0U)
74708#define SNVS_HPSICR_CAAM_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_CAAM_EN_SHIFT)) & SNVS_HPSICR_CAAM_EN_MASK)
74709
74710#define SNVS_HPSICR_JTAGC_EN_MASK (0x2U)
74711#define SNVS_HPSICR_JTAGC_EN_SHIFT (1U)
74716#define SNVS_HPSICR_JTAGC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_JTAGC_EN_SHIFT)) & SNVS_HPSICR_JTAGC_EN_MASK)
74717
74718#define SNVS_HPSICR_WDOG2_EN_MASK (0x4U)
74719#define SNVS_HPSICR_WDOG2_EN_SHIFT (2U)
74724#define SNVS_HPSICR_WDOG2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_WDOG2_EN_SHIFT)) & SNVS_HPSICR_WDOG2_EN_MASK)
74725
74726#define SNVS_HPSICR_SRC_EN_MASK (0x10U)
74727#define SNVS_HPSICR_SRC_EN_SHIFT (4U)
74732#define SNVS_HPSICR_SRC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SRC_EN_SHIFT)) & SNVS_HPSICR_SRC_EN_MASK)
74733
74734#define SNVS_HPSICR_OCOTP_EN_MASK (0x20U)
74735#define SNVS_HPSICR_OCOTP_EN_SHIFT (5U)
74740#define SNVS_HPSICR_OCOTP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_OCOTP_EN_SHIFT)) & SNVS_HPSICR_OCOTP_EN_MASK)
74741
74742#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)
74743#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U)
74748#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
74754#define SNVS_HPSVCR_CAAM_CFG_MASK (0x1U)
74755#define SNVS_HPSVCR_CAAM_CFG_SHIFT (0U)
74760#define SNVS_HPSVCR_CAAM_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_CAAM_CFG_SHIFT)) & SNVS_HPSVCR_CAAM_CFG_MASK)
74761
74762#define SNVS_HPSVCR_JTAGC_CFG_MASK (0x2U)
74763#define SNVS_HPSVCR_JTAGC_CFG_SHIFT (1U)
74768#define SNVS_HPSVCR_JTAGC_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_JTAGC_CFG_SHIFT)) & SNVS_HPSVCR_JTAGC_CFG_MASK)
74769
74770#define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U)
74771#define SNVS_HPSVCR_WDOG2_CFG_SHIFT (2U)
74776#define SNVS_HPSVCR_WDOG2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
74777
74778#define SNVS_HPSVCR_SRC_CFG_MASK (0x10U)
74779#define SNVS_HPSVCR_SRC_CFG_SHIFT (4U)
74784#define SNVS_HPSVCR_SRC_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SRC_CFG_SHIFT)) & SNVS_HPSVCR_SRC_CFG_MASK)
74785
74786#define SNVS_HPSVCR_OCOTP_CFG_MASK (0x60U)
74787#define SNVS_HPSVCR_OCOTP_CFG_SHIFT (5U)
74793#define SNVS_HPSVCR_OCOTP_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_OCOTP_CFG_SHIFT)) & SNVS_HPSVCR_OCOTP_CFG_MASK)
74794
74795#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)
74796#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)
74802#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
74808#define SNVS_HPSR_HPTA_MASK (0x1U)
74809#define SNVS_HPSR_HPTA_SHIFT (0U)
74814#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
74815
74816#define SNVS_HPSR_PI_MASK (0x2U)
74817#define SNVS_HPSR_PI_SHIFT (1U)
74822#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
74823
74824#define SNVS_HPSR_LPDIS_MASK (0x10U)
74825#define SNVS_HPSR_LPDIS_SHIFT (4U)
74826#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
74827
74828#define SNVS_HPSR_BTN_MASK (0x40U)
74829#define SNVS_HPSR_BTN_SHIFT (6U)
74830#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
74831
74832#define SNVS_HPSR_BI_MASK (0x80U)
74833#define SNVS_HPSR_BI_SHIFT (7U)
74834#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
74835
74836#define SNVS_HPSR_SSM_STATE_MASK (0xF00U)
74837#define SNVS_HPSR_SSM_STATE_SHIFT (8U)
74848#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
74849
74850#define SNVS_HPSR_SYS_SECURITY_CFG_MASK (0x7000U)
74851#define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT (12U)
74858#define SNVS_HPSR_SYS_SECURITY_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)
74859
74860#define SNVS_HPSR_SYS_SECURE_BOOT_MASK (0x8000U)
74861#define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT (15U)
74862#define SNVS_HPSR_SYS_SECURE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)
74863
74864#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)
74865#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)
74870#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
74871
74872#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)
74873#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U)
74878#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
74884#define SNVS_HPSVSR_CAAM_MASK (0x1U)
74885#define SNVS_HPSVSR_CAAM_SHIFT (0U)
74890#define SNVS_HPSVSR_CAAM(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_CAAM_SHIFT)) & SNVS_HPSVSR_CAAM_MASK)
74891
74892#define SNVS_HPSVSR_JTAGC_MASK (0x2U)
74893#define SNVS_HPSVSR_JTAGC_SHIFT (1U)
74898#define SNVS_HPSVSR_JTAGC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_JTAGC_SHIFT)) & SNVS_HPSVSR_JTAGC_MASK)
74899
74900#define SNVS_HPSVSR_WDOG2_MASK (0x4U)
74901#define SNVS_HPSVSR_WDOG2_SHIFT (2U)
74906#define SNVS_HPSVSR_WDOG2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_WDOG2_SHIFT)) & SNVS_HPSVSR_WDOG2_MASK)
74907
74908#define SNVS_HPSVSR_SRC_MASK (0x10U)
74909#define SNVS_HPSVSR_SRC_SHIFT (4U)
74914#define SNVS_HPSVSR_SRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SRC_SHIFT)) & SNVS_HPSVSR_SRC_MASK)
74915
74916#define SNVS_HPSVSR_OCOTP_MASK (0x20U)
74917#define SNVS_HPSVSR_OCOTP_SHIFT (5U)
74922#define SNVS_HPSVSR_OCOTP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_OCOTP_SHIFT)) & SNVS_HPSVSR_OCOTP_MASK)
74923
74924#define SNVS_HPSVSR_SW_SV_MASK (0x2000U)
74925#define SNVS_HPSVSR_SW_SV_SHIFT (13U)
74926#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
74927
74928#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U)
74929#define SNVS_HPSVSR_SW_FSV_SHIFT (14U)
74930#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
74931
74932#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)
74933#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U)
74934#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
74935
74936#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)
74937#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)
74938#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
74939
74940#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)
74941#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)
74946#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
74947
74948#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)
74949#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)
74950#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
74956#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)
74957#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)
74958#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
74964#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)
74965#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)
74966#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
74972#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
74973#define SNVS_HPRTCMR_RTC_SHIFT (0U)
74974#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
74980#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
74981#define SNVS_HPRTCLR_RTC_SHIFT (0U)
74982#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
74988#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
74989#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
74990#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
74996#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
74997#define SNVS_HPTALR_HPTA_LS_SHIFT (0U)
74998#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
75004#define SNVS_LPLR_ZMK_WHL_MASK (0x1U)
75005#define SNVS_LPLR_ZMK_WHL_SHIFT (0U)
75010#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
75011
75012#define SNVS_LPLR_ZMK_RHL_MASK (0x2U)
75013#define SNVS_LPLR_ZMK_RHL_SHIFT (1U)
75018#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
75019
75020#define SNVS_LPLR_SRTC_HL_MASK (0x4U)
75021#define SNVS_LPLR_SRTC_HL_SHIFT (2U)
75026#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
75027
75028#define SNVS_LPLR_LPCALB_HL_MASK (0x8U)
75029#define SNVS_LPLR_LPCALB_HL_SHIFT (3U)
75034#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
75035
75036#define SNVS_LPLR_MC_HL_MASK (0x10U)
75037#define SNVS_LPLR_MC_HL_SHIFT (4U)
75042#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
75043
75044#define SNVS_LPLR_GPR_HL_MASK (0x20U)
75045#define SNVS_LPLR_GPR_HL_SHIFT (5U)
75050#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
75051
75052#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U)
75053#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U)
75058#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
75059
75060#define SNVS_LPLR_LPTGFCR_HL_MASK (0x80U)
75061#define SNVS_LPLR_LPTGFCR_HL_SHIFT (7U)
75066#define SNVS_LPLR_LPTGFCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTGFCR_HL_SHIFT)) & SNVS_LPLR_LPTGFCR_HL_MASK)
75067
75068#define SNVS_LPLR_LPSECR_HL_MASK (0x100U)
75069#define SNVS_LPLR_LPSECR_HL_SHIFT (8U)
75074#define SNVS_LPLR_LPSECR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)
75075
75076#define SNVS_LPLR_MKS_HL_MASK (0x200U)
75077#define SNVS_LPLR_MKS_HL_SHIFT (9U)
75082#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
75083
75084#define SNVS_LPLR_AT1_HL_MASK (0x1000000U)
75085#define SNVS_LPLR_AT1_HL_SHIFT (24U)
75090#define SNVS_LPLR_AT1_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT1_HL_SHIFT)) & SNVS_LPLR_AT1_HL_MASK)
75091
75092#define SNVS_LPLR_AT2_HL_MASK (0x2000000U)
75093#define SNVS_LPLR_AT2_HL_SHIFT (25U)
75098#define SNVS_LPLR_AT2_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT2_HL_SHIFT)) & SNVS_LPLR_AT2_HL_MASK)
75099
75100#define SNVS_LPLR_AT3_HL_MASK (0x4000000U)
75101#define SNVS_LPLR_AT3_HL_SHIFT (26U)
75106#define SNVS_LPLR_AT3_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT3_HL_SHIFT)) & SNVS_LPLR_AT3_HL_MASK)
75107
75108#define SNVS_LPLR_AT4_HL_MASK (0x8000000U)
75109#define SNVS_LPLR_AT4_HL_SHIFT (27U)
75114#define SNVS_LPLR_AT4_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT4_HL_SHIFT)) & SNVS_LPLR_AT4_HL_MASK)
75115
75116#define SNVS_LPLR_AT5_HL_MASK (0x10000000U)
75117#define SNVS_LPLR_AT5_HL_SHIFT (28U)
75122#define SNVS_LPLR_AT5_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT5_HL_SHIFT)) & SNVS_LPLR_AT5_HL_MASK)
75128#define SNVS_LPCR_SRTC_ENV_MASK (0x1U)
75129#define SNVS_LPCR_SRTC_ENV_SHIFT (0U)
75134#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
75135
75136#define SNVS_LPCR_LPTA_EN_MASK (0x2U)
75137#define SNVS_LPCR_LPTA_EN_SHIFT (1U)
75142#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
75143
75144#define SNVS_LPCR_MC_ENV_MASK (0x4U)
75145#define SNVS_LPCR_MC_ENV_SHIFT (2U)
75150#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
75151
75152#define SNVS_LPCR_LPWUI_EN_MASK (0x8U)
75153#define SNVS_LPCR_LPWUI_EN_SHIFT (3U)
75154#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
75155
75156#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)
75157#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)
75162#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
75163
75164#define SNVS_LPCR_DP_EN_MASK (0x20U)
75165#define SNVS_LPCR_DP_EN_SHIFT (5U)
75170#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
75171
75172#define SNVS_LPCR_TOP_MASK (0x40U)
75173#define SNVS_LPCR_TOP_SHIFT (6U)
75178#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
75179
75180#define SNVS_LPCR_LVD_EN_MASK (0x80U)
75181#define SNVS_LPCR_LVD_EN_SHIFT (7U)
75182#define SNVS_LPCR_LVD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK)
75183
75184#define SNVS_LPCR_LPCALB_EN_MASK (0x100U)
75185#define SNVS_LPCR_LPCALB_EN_SHIFT (8U)
75190#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
75191
75192#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)
75193#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U)
75204#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
75205
75206#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)
75207#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)
75208#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
75209
75210#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)
75211#define SNVS_LPCR_DEBOUNCE_SHIFT (18U)
75212#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
75213
75214#define SNVS_LPCR_ON_TIME_MASK (0x300000U)
75215#define SNVS_LPCR_ON_TIME_SHIFT (20U)
75216#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
75217
75218#define SNVS_LPCR_PK_EN_MASK (0x400000U)
75219#define SNVS_LPCR_PK_EN_SHIFT (22U)
75220#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
75221
75222#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)
75223#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)
75224#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
75225
75226#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)
75227#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)
75228#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
75234#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)
75235#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)
75241#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
75242
75243#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)
75244#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)
75249#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
75250
75251#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)
75252#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)
75257#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
75258
75259#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)
75260#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)
75265#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
75266
75267#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)
75268#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)
75269#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
75275#define SNVS_LPSVCR_CAAM_EN_MASK (0x1U)
75276#define SNVS_LPSVCR_CAAM_EN_SHIFT (0U)
75281#define SNVS_LPSVCR_CAAM_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_CAAM_EN_SHIFT)) & SNVS_LPSVCR_CAAM_EN_MASK)
75282
75283#define SNVS_LPSVCR_JTAGC_EN_MASK (0x2U)
75284#define SNVS_LPSVCR_JTAGC_EN_SHIFT (1U)
75289#define SNVS_LPSVCR_JTAGC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_JTAGC_EN_SHIFT)) & SNVS_LPSVCR_JTAGC_EN_MASK)
75290
75291#define SNVS_LPSVCR_WDOG2_EN_MASK (0x4U)
75292#define SNVS_LPSVCR_WDOG2_EN_SHIFT (2U)
75297#define SNVS_LPSVCR_WDOG2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_WDOG2_EN_SHIFT)) & SNVS_LPSVCR_WDOG2_EN_MASK)
75298
75299#define SNVS_LPSVCR_SRC_EN_MASK (0x10U)
75300#define SNVS_LPSVCR_SRC_EN_SHIFT (4U)
75305#define SNVS_LPSVCR_SRC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SRC_EN_SHIFT)) & SNVS_LPSVCR_SRC_EN_MASK)
75306
75307#define SNVS_LPSVCR_OCOTP_EN_MASK (0x20U)
75308#define SNVS_LPSVCR_OCOTP_EN_SHIFT (5U)
75313#define SNVS_LPSVCR_OCOTP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_OCOTP_EN_SHIFT)) & SNVS_LPSVCR_OCOTP_EN_MASK)
75319#define SNVS_LPTGFCR_WMTGF_MASK (0x1FU)
75320#define SNVS_LPTGFCR_WMTGF_SHIFT (0U)
75321#define SNVS_LPTGFCR_WMTGF(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_SHIFT)) & SNVS_LPTGFCR_WMTGF_MASK)
75322
75323#define SNVS_LPTGFCR_WMTGF_EN_MASK (0x80U)
75324#define SNVS_LPTGFCR_WMTGF_EN_SHIFT (7U)
75329#define SNVS_LPTGFCR_WMTGF_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_EN_SHIFT)) & SNVS_LPTGFCR_WMTGF_EN_MASK)
75330
75331#define SNVS_LPTGFCR_ETGF1_MASK (0x7F0000U)
75332#define SNVS_LPTGFCR_ETGF1_SHIFT (16U)
75333#define SNVS_LPTGFCR_ETGF1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_SHIFT)) & SNVS_LPTGFCR_ETGF1_MASK)
75334
75335#define SNVS_LPTGFCR_ETGF1_EN_MASK (0x800000U)
75336#define SNVS_LPTGFCR_ETGF1_EN_SHIFT (23U)
75341#define SNVS_LPTGFCR_ETGF1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_EN_SHIFT)) & SNVS_LPTGFCR_ETGF1_EN_MASK)
75342
75343#define SNVS_LPTGFCR_ETGF2_MASK (0x7F000000U)
75344#define SNVS_LPTGFCR_ETGF2_SHIFT (24U)
75345#define SNVS_LPTGFCR_ETGF2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_SHIFT)) & SNVS_LPTGFCR_ETGF2_MASK)
75346
75347#define SNVS_LPTGFCR_ETGF2_EN_MASK (0x80000000U)
75348#define SNVS_LPTGFCR_ETGF2_EN_SHIFT (31U)
75353#define SNVS_LPTGFCR_ETGF2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_EN_SHIFT)) & SNVS_LPTGFCR_ETGF2_EN_MASK)
75359#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)
75360#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)
75365#define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
75366
75367#define SNVS_LPTDCR_MCR_EN_MASK (0x4U)
75368#define SNVS_LPTDCR_MCR_EN_SHIFT (2U)
75373#define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
75374
75375#define SNVS_LPTDCR_CT_EN_MASK (0x10U)
75376#define SNVS_LPTDCR_CT_EN_SHIFT (4U)
75381#define SNVS_LPTDCR_CT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_CT_EN_SHIFT)) & SNVS_LPTDCR_CT_EN_MASK)
75382
75383#define SNVS_LPTDCR_TT_EN_MASK (0x20U)
75384#define SNVS_LPTDCR_TT_EN_SHIFT (5U)
75389#define SNVS_LPTDCR_TT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_TT_EN_SHIFT)) & SNVS_LPTDCR_TT_EN_MASK)
75390
75391#define SNVS_LPTDCR_VT_EN_MASK (0x40U)
75392#define SNVS_LPTDCR_VT_EN_SHIFT (6U)
75397#define SNVS_LPTDCR_VT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VT_EN_SHIFT)) & SNVS_LPTDCR_VT_EN_MASK)
75398
75399#define SNVS_LPTDCR_WMT1_EN_MASK (0x80U)
75400#define SNVS_LPTDCR_WMT1_EN_SHIFT (7U)
75405#define SNVS_LPTDCR_WMT1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT1_EN_SHIFT)) & SNVS_LPTDCR_WMT1_EN_MASK)
75406
75407#define SNVS_LPTDCR_WMT2_EN_MASK (0x100U)
75408#define SNVS_LPTDCR_WMT2_EN_SHIFT (8U)
75413#define SNVS_LPTDCR_WMT2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT2_EN_SHIFT)) & SNVS_LPTDCR_WMT2_EN_MASK)
75414
75415#define SNVS_LPTDCR_ET1_EN_MASK (0x200U)
75416#define SNVS_LPTDCR_ET1_EN_SHIFT (9U)
75421#define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
75422
75423#define SNVS_LPTDCR_ET2_EN_MASK (0x400U)
75424#define SNVS_LPTDCR_ET2_EN_SHIFT (10U)
75429#define SNVS_LPTDCR_ET2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2_EN_SHIFT)) & SNVS_LPTDCR_ET2_EN_MASK)
75430
75431#define SNVS_LPTDCR_ET1P_MASK (0x800U)
75432#define SNVS_LPTDCR_ET1P_SHIFT (11U)
75437#define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
75438
75439#define SNVS_LPTDCR_ET2P_MASK (0x1000U)
75440#define SNVS_LPTDCR_ET2P_SHIFT (12U)
75445#define SNVS_LPTDCR_ET2P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2P_SHIFT)) & SNVS_LPTDCR_ET2P_MASK)
75446
75447#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)
75448#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)
75449#define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
75450
75451#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)
75452#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)
75453#define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
75454
75455#define SNVS_LPTDCR_LTDC_MASK (0x70000U)
75456#define SNVS_LPTDCR_LTDC_SHIFT (16U)
75457#define SNVS_LPTDCR_LTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_LTDC_SHIFT)) & SNVS_LPTDCR_LTDC_MASK)
75458
75459#define SNVS_LPTDCR_HTDC_MASK (0x700000U)
75460#define SNVS_LPTDCR_HTDC_SHIFT (20U)
75461#define SNVS_LPTDCR_HTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_HTDC_SHIFT)) & SNVS_LPTDCR_HTDC_MASK)
75462
75463#define SNVS_LPTDCR_VRC_MASK (0x7000000U)
75464#define SNVS_LPTDCR_VRC_SHIFT (24U)
75465#define SNVS_LPTDCR_VRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VRC_SHIFT)) & SNVS_LPTDCR_VRC_MASK)
75466
75467#define SNVS_LPTDCR_OSCB_MASK (0x10000000U)
75468#define SNVS_LPTDCR_OSCB_SHIFT (28U)
75473#define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
75479#define SNVS_LPSR_LPTA_MASK (0x1U)
75480#define SNVS_LPSR_LPTA_SHIFT (0U)
75485#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
75486
75487#define SNVS_LPSR_SRTCR_MASK (0x2U)
75488#define SNVS_LPSR_SRTCR_SHIFT (1U)
75493#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
75494
75495#define SNVS_LPSR_MCR_MASK (0x4U)
75496#define SNVS_LPSR_MCR_SHIFT (2U)
75501#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
75502
75503#define SNVS_LPSR_LVD_MASK (0x8U)
75504#define SNVS_LPSR_LVD_SHIFT (3U)
75509#define SNVS_LPSR_LVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)
75510
75511#define SNVS_LPSR_CTD_MASK (0x10U)
75512#define SNVS_LPSR_CTD_SHIFT (4U)
75517#define SNVS_LPSR_CTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_CTD_SHIFT)) & SNVS_LPSR_CTD_MASK)
75518
75519#define SNVS_LPSR_TTD_MASK (0x20U)
75520#define SNVS_LPSR_TTD_SHIFT (5U)
75525#define SNVS_LPSR_TTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_TTD_SHIFT)) & SNVS_LPSR_TTD_MASK)
75526
75527#define SNVS_LPSR_VTD_MASK (0x40U)
75528#define SNVS_LPSR_VTD_SHIFT (6U)
75533#define SNVS_LPSR_VTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
75534
75535#define SNVS_LPSR_WMT1D_MASK (0x80U)
75536#define SNVS_LPSR_WMT1D_SHIFT (7U)
75541#define SNVS_LPSR_WMT1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT1D_SHIFT)) & SNVS_LPSR_WMT1D_MASK)
75542
75543#define SNVS_LPSR_WMT2D_MASK (0x100U)
75544#define SNVS_LPSR_WMT2D_SHIFT (8U)
75549#define SNVS_LPSR_WMT2D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT2D_SHIFT)) & SNVS_LPSR_WMT2D_MASK)
75550
75551#define SNVS_LPSR_ET1D_MASK (0x200U)
75552#define SNVS_LPSR_ET1D_SHIFT (9U)
75557#define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
75558
75559#define SNVS_LPSR_ET2D_MASK (0x400U)
75560#define SNVS_LPSR_ET2D_SHIFT (10U)
75565#define SNVS_LPSR_ET2D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
75566
75567#define SNVS_LPSR_ESVD_MASK (0x10000U)
75568#define SNVS_LPSR_ESVD_SHIFT (16U)
75573#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
75574
75575#define SNVS_LPSR_EO_MASK (0x20000U)
75576#define SNVS_LPSR_EO_SHIFT (17U)
75581#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
75582
75583#define SNVS_LPSR_SPOF_MASK (0x40000U)
75584#define SNVS_LPSR_SPOF_SHIFT (18U)
75589#define SNVS_LPSR_SPOF(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
75590
75591#define SNVS_LPSR_LPNS_MASK (0x40000000U)
75592#define SNVS_LPSR_LPNS_SHIFT (30U)
75597#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
75598
75599#define SNVS_LPSR_LPS_MASK (0x80000000U)
75600#define SNVS_LPSR_LPS_SHIFT (31U)
75605#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
75611#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)
75612#define SNVS_LPSRTCMR_SRTC_SHIFT (0U)
75613#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
75619#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)
75620#define SNVS_LPSRTCLR_SRTC_SHIFT (0U)
75621#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
75627#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)
75628#define SNVS_LPTAR_LPTA_SHIFT (0U)
75629#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
75635#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
75636#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
75637#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
75638
75639#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
75640#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
75641#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
75647#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
75648#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
75649#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
75655#define SNVS_LPLVDR_LVD_MASK (0xFFFFFFFFU)
75656#define SNVS_LPLVDR_LVD_SHIFT (0U)
75657#define SNVS_LPLVDR_LVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK)
75663#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
75664#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
75665#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
75671#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)
75672#define SNVS_LPZMKR_ZMK_SHIFT (0U)
75673#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
75676/* The count of SNVS_LPZMKR */
75677#define SNVS_LPZMKR_COUNT (8U)
75678
75682#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
75683#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
75684#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
75687/* The count of SNVS_LPGPR_ALIAS */
75688#define SNVS_LPGPR_ALIAS_COUNT (4U)
75689
75693#define SNVS_LPTDC2R_ET3_EN_MASK (0x1U)
75694#define SNVS_LPTDC2R_ET3_EN_SHIFT (0U)
75699#define SNVS_LPTDC2R_ET3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3_EN_SHIFT)) & SNVS_LPTDC2R_ET3_EN_MASK)
75700
75701#define SNVS_LPTDC2R_ET4_EN_MASK (0x2U)
75702#define SNVS_LPTDC2R_ET4_EN_SHIFT (1U)
75707#define SNVS_LPTDC2R_ET4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4_EN_SHIFT)) & SNVS_LPTDC2R_ET4_EN_MASK)
75708
75709#define SNVS_LPTDC2R_ET5_EN_MASK (0x4U)
75710#define SNVS_LPTDC2R_ET5_EN_SHIFT (2U)
75715#define SNVS_LPTDC2R_ET5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5_EN_SHIFT)) & SNVS_LPTDC2R_ET5_EN_MASK)
75716
75717#define SNVS_LPTDC2R_ET6_EN_MASK (0x8U)
75718#define SNVS_LPTDC2R_ET6_EN_SHIFT (3U)
75723#define SNVS_LPTDC2R_ET6_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6_EN_SHIFT)) & SNVS_LPTDC2R_ET6_EN_MASK)
75724
75725#define SNVS_LPTDC2R_ET7_EN_MASK (0x10U)
75726#define SNVS_LPTDC2R_ET7_EN_SHIFT (4U)
75731#define SNVS_LPTDC2R_ET7_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7_EN_SHIFT)) & SNVS_LPTDC2R_ET7_EN_MASK)
75732
75733#define SNVS_LPTDC2R_ET8_EN_MASK (0x20U)
75734#define SNVS_LPTDC2R_ET8_EN_SHIFT (5U)
75739#define SNVS_LPTDC2R_ET8_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8_EN_SHIFT)) & SNVS_LPTDC2R_ET8_EN_MASK)
75740
75741#define SNVS_LPTDC2R_ET9_EN_MASK (0x40U)
75742#define SNVS_LPTDC2R_ET9_EN_SHIFT (6U)
75747#define SNVS_LPTDC2R_ET9_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9_EN_SHIFT)) & SNVS_LPTDC2R_ET9_EN_MASK)
75748
75749#define SNVS_LPTDC2R_ET10_EN_MASK (0x80U)
75750#define SNVS_LPTDC2R_ET10_EN_SHIFT (7U)
75755#define SNVS_LPTDC2R_ET10_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10_EN_SHIFT)) & SNVS_LPTDC2R_ET10_EN_MASK)
75756
75757#define SNVS_LPTDC2R_ET3P_MASK (0x10000U)
75758#define SNVS_LPTDC2R_ET3P_SHIFT (16U)
75763#define SNVS_LPTDC2R_ET3P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3P_SHIFT)) & SNVS_LPTDC2R_ET3P_MASK)
75764
75765#define SNVS_LPTDC2R_ET4P_MASK (0x20000U)
75766#define SNVS_LPTDC2R_ET4P_SHIFT (17U)
75771#define SNVS_LPTDC2R_ET4P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4P_SHIFT)) & SNVS_LPTDC2R_ET4P_MASK)
75772
75773#define SNVS_LPTDC2R_ET5P_MASK (0x40000U)
75774#define SNVS_LPTDC2R_ET5P_SHIFT (18U)
75779#define SNVS_LPTDC2R_ET5P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5P_SHIFT)) & SNVS_LPTDC2R_ET5P_MASK)
75780
75781#define SNVS_LPTDC2R_ET6P_MASK (0x80000U)
75782#define SNVS_LPTDC2R_ET6P_SHIFT (19U)
75787#define SNVS_LPTDC2R_ET6P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6P_SHIFT)) & SNVS_LPTDC2R_ET6P_MASK)
75788
75789#define SNVS_LPTDC2R_ET7P_MASK (0x100000U)
75790#define SNVS_LPTDC2R_ET7P_SHIFT (20U)
75795#define SNVS_LPTDC2R_ET7P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7P_SHIFT)) & SNVS_LPTDC2R_ET7P_MASK)
75796
75797#define SNVS_LPTDC2R_ET8P_MASK (0x200000U)
75798#define SNVS_LPTDC2R_ET8P_SHIFT (21U)
75803#define SNVS_LPTDC2R_ET8P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8P_SHIFT)) & SNVS_LPTDC2R_ET8P_MASK)
75804
75805#define SNVS_LPTDC2R_ET9P_MASK (0x400000U)
75806#define SNVS_LPTDC2R_ET9P_SHIFT (22U)
75811#define SNVS_LPTDC2R_ET9P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9P_SHIFT)) & SNVS_LPTDC2R_ET9P_MASK)
75812
75813#define SNVS_LPTDC2R_ET10P_MASK (0x800000U)
75814#define SNVS_LPTDC2R_ET10P_SHIFT (23U)
75819#define SNVS_LPTDC2R_ET10P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10P_SHIFT)) & SNVS_LPTDC2R_ET10P_MASK)
75825#define SNVS_LPTDSR_ET3D_MASK (0x1U)
75826#define SNVS_LPTDSR_ET3D_SHIFT (0U)
75831#define SNVS_LPTDSR_ET3D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET3D_SHIFT)) & SNVS_LPTDSR_ET3D_MASK)
75832
75833#define SNVS_LPTDSR_ET4D_MASK (0x2U)
75834#define SNVS_LPTDSR_ET4D_SHIFT (1U)
75839#define SNVS_LPTDSR_ET4D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET4D_SHIFT)) & SNVS_LPTDSR_ET4D_MASK)
75840
75841#define SNVS_LPTDSR_ET5D_MASK (0x4U)
75842#define SNVS_LPTDSR_ET5D_SHIFT (2U)
75847#define SNVS_LPTDSR_ET5D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET5D_SHIFT)) & SNVS_LPTDSR_ET5D_MASK)
75848
75849#define SNVS_LPTDSR_ET6D_MASK (0x8U)
75850#define SNVS_LPTDSR_ET6D_SHIFT (3U)
75855#define SNVS_LPTDSR_ET6D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET6D_SHIFT)) & SNVS_LPTDSR_ET6D_MASK)
75856
75857#define SNVS_LPTDSR_ET7D_MASK (0x10U)
75858#define SNVS_LPTDSR_ET7D_SHIFT (4U)
75863#define SNVS_LPTDSR_ET7D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET7D_SHIFT)) & SNVS_LPTDSR_ET7D_MASK)
75864
75865#define SNVS_LPTDSR_ET8D_MASK (0x20U)
75866#define SNVS_LPTDSR_ET8D_SHIFT (5U)
75871#define SNVS_LPTDSR_ET8D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET8D_SHIFT)) & SNVS_LPTDSR_ET8D_MASK)
75872
75873#define SNVS_LPTDSR_ET9D_MASK (0x40U)
75874#define SNVS_LPTDSR_ET9D_SHIFT (6U)
75879#define SNVS_LPTDSR_ET9D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET9D_SHIFT)) & SNVS_LPTDSR_ET9D_MASK)
75880
75881#define SNVS_LPTDSR_ET10D_MASK (0x80U)
75882#define SNVS_LPTDSR_ET10D_SHIFT (7U)
75887#define SNVS_LPTDSR_ET10D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET10D_SHIFT)) & SNVS_LPTDSR_ET10D_MASK)
75893#define SNVS_LPTGF1CR_ETGF3_MASK (0x7FU)
75894#define SNVS_LPTGF1CR_ETGF3_SHIFT (0U)
75895#define SNVS_LPTGF1CR_ETGF3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_SHIFT)) & SNVS_LPTGF1CR_ETGF3_MASK)
75896
75897#define SNVS_LPTGF1CR_ETGF3_EN_MASK (0x80U)
75898#define SNVS_LPTGF1CR_ETGF3_EN_SHIFT (7U)
75903#define SNVS_LPTGF1CR_ETGF3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF3_EN_MASK)
75904
75905#define SNVS_LPTGF1CR_ETGF4_MASK (0x7F00U)
75906#define SNVS_LPTGF1CR_ETGF4_SHIFT (8U)
75907#define SNVS_LPTGF1CR_ETGF4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_SHIFT)) & SNVS_LPTGF1CR_ETGF4_MASK)
75908
75909#define SNVS_LPTGF1CR_ETGF4_EN_MASK (0x8000U)
75910#define SNVS_LPTGF1CR_ETGF4_EN_SHIFT (15U)
75915#define SNVS_LPTGF1CR_ETGF4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF4_EN_MASK)
75916
75917#define SNVS_LPTGF1CR_ETGF5_MASK (0x7F0000U)
75918#define SNVS_LPTGF1CR_ETGF5_SHIFT (16U)
75919#define SNVS_LPTGF1CR_ETGF5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_SHIFT)) & SNVS_LPTGF1CR_ETGF5_MASK)
75920
75921#define SNVS_LPTGF1CR_ETGF5_EN_MASK (0x800000U)
75922#define SNVS_LPTGF1CR_ETGF5_EN_SHIFT (23U)
75927#define SNVS_LPTGF1CR_ETGF5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF5_EN_MASK)
75928
75929#define SNVS_LPTGF1CR_ETGF6_MASK (0x7F000000U)
75930#define SNVS_LPTGF1CR_ETGF6_SHIFT (24U)
75931#define SNVS_LPTGF1CR_ETGF6(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_SHIFT)) & SNVS_LPTGF1CR_ETGF6_MASK)
75932
75933#define SNVS_LPTGF1CR_ETGF6_EN_MASK (0x80000000U)
75934#define SNVS_LPTGF1CR_ETGF6_EN_SHIFT (31U)
75939#define SNVS_LPTGF1CR_ETGF6_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF6_EN_MASK)
75945#define SNVS_LPTGF2CR_ETGF7_MASK (0x7FU)
75946#define SNVS_LPTGF2CR_ETGF7_SHIFT (0U)
75947#define SNVS_LPTGF2CR_ETGF7(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_SHIFT)) & SNVS_LPTGF2CR_ETGF7_MASK)
75948
75949#define SNVS_LPTGF2CR_ETGF7_EN_MASK (0x80U)
75950#define SNVS_LPTGF2CR_ETGF7_EN_SHIFT (7U)
75955#define SNVS_LPTGF2CR_ETGF7_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF7_EN_MASK)
75956
75957#define SNVS_LPTGF2CR_ETGF8_MASK (0x7F00U)
75958#define SNVS_LPTGF2CR_ETGF8_SHIFT (8U)
75959#define SNVS_LPTGF2CR_ETGF8(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_SHIFT)) & SNVS_LPTGF2CR_ETGF8_MASK)
75960
75961#define SNVS_LPTGF2CR_ETGF8_EN_MASK (0x8000U)
75962#define SNVS_LPTGF2CR_ETGF8_EN_SHIFT (15U)
75967#define SNVS_LPTGF2CR_ETGF8_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF8_EN_MASK)
75968
75969#define SNVS_LPTGF2CR_ETGF9_MASK (0x7F0000U)
75970#define SNVS_LPTGF2CR_ETGF9_SHIFT (16U)
75971#define SNVS_LPTGF2CR_ETGF9(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_SHIFT)) & SNVS_LPTGF2CR_ETGF9_MASK)
75972
75973#define SNVS_LPTGF2CR_ETGF9_EN_MASK (0x800000U)
75974#define SNVS_LPTGF2CR_ETGF9_EN_SHIFT (23U)
75979#define SNVS_LPTGF2CR_ETGF9_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF9_EN_MASK)
75980
75981#define SNVS_LPTGF2CR_ETGF10_MASK (0x7F000000U)
75982#define SNVS_LPTGF2CR_ETGF10_SHIFT (24U)
75983#define SNVS_LPTGF2CR_ETGF10(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_SHIFT)) & SNVS_LPTGF2CR_ETGF10_MASK)
75984
75985#define SNVS_LPTGF2CR_ETGF10_EN_MASK (0x80000000U)
75986#define SNVS_LPTGF2CR_ETGF10_EN_SHIFT (31U)
75991#define SNVS_LPTGF2CR_ETGF10_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF10_EN_MASK)
75997#define SNVS_LPATCR_Seed_MASK (0xFFFFU)
75998#define SNVS_LPATCR_Seed_SHIFT (0U)
75999#define SNVS_LPATCR_Seed(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Seed_SHIFT)) & SNVS_LPATCR_Seed_MASK)
76000
76001#define SNVS_LPATCR_Polynomial_MASK (0xFFFF0000U)
76002#define SNVS_LPATCR_Polynomial_SHIFT (16U)
76003#define SNVS_LPATCR_Polynomial(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Polynomial_SHIFT)) & SNVS_LPATCR_Polynomial_MASK)
76006/* The count of SNVS_LPATCR */
76007#define SNVS_LPATCR_COUNT (5U)
76008
76012#define SNVS_LPATCTLR_AT1_EN_MASK (0x1U)
76013#define SNVS_LPATCTLR_AT1_EN_SHIFT (0U)
76018#define SNVS_LPATCTLR_AT1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_EN_SHIFT)) & SNVS_LPATCTLR_AT1_EN_MASK)
76019
76020#define SNVS_LPATCTLR_AT2_EN_MASK (0x2U)
76021#define SNVS_LPATCTLR_AT2_EN_SHIFT (1U)
76026#define SNVS_LPATCTLR_AT2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_EN_SHIFT)) & SNVS_LPATCTLR_AT2_EN_MASK)
76027
76028#define SNVS_LPATCTLR_AT3_EN_MASK (0x4U)
76029#define SNVS_LPATCTLR_AT3_EN_SHIFT (2U)
76034#define SNVS_LPATCTLR_AT3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_EN_SHIFT)) & SNVS_LPATCTLR_AT3_EN_MASK)
76035
76036#define SNVS_LPATCTLR_AT4_EN_MASK (0x8U)
76037#define SNVS_LPATCTLR_AT4_EN_SHIFT (3U)
76042#define SNVS_LPATCTLR_AT4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_EN_SHIFT)) & SNVS_LPATCTLR_AT4_EN_MASK)
76043
76044#define SNVS_LPATCTLR_AT5_EN_MASK (0x10U)
76045#define SNVS_LPATCTLR_AT5_EN_SHIFT (4U)
76050#define SNVS_LPATCTLR_AT5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_EN_SHIFT)) & SNVS_LPATCTLR_AT5_EN_MASK)
76051
76052#define SNVS_LPATCTLR_AT1_PAD_EN_MASK (0x10000U)
76053#define SNVS_LPATCTLR_AT1_PAD_EN_SHIFT (16U)
76058#define SNVS_LPATCTLR_AT1_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT1_PAD_EN_MASK)
76059
76060#define SNVS_LPATCTLR_AT2_PAD_EN_MASK (0x20000U)
76061#define SNVS_LPATCTLR_AT2_PAD_EN_SHIFT (17U)
76066#define SNVS_LPATCTLR_AT2_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT2_PAD_EN_MASK)
76067
76068#define SNVS_LPATCTLR_AT3_PAD_EN_MASK (0x40000U)
76069#define SNVS_LPATCTLR_AT3_PAD_EN_SHIFT (18U)
76074#define SNVS_LPATCTLR_AT3_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT3_PAD_EN_MASK)
76075
76076#define SNVS_LPATCTLR_AT4_PAD_EN_MASK (0x80000U)
76077#define SNVS_LPATCTLR_AT4_PAD_EN_SHIFT (19U)
76082#define SNVS_LPATCTLR_AT4_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT4_PAD_EN_MASK)
76083
76084#define SNVS_LPATCTLR_AT5_PAD_EN_MASK (0x100000U)
76085#define SNVS_LPATCTLR_AT5_PAD_EN_SHIFT (20U)
76090#define SNVS_LPATCTLR_AT5_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT5_PAD_EN_MASK)
76096#define SNVS_LPATCLKR_AT1_CLK_CTL_MASK (0x3U)
76097#define SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT (0U)
76098#define SNVS_LPATCLKR_AT1_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT1_CLK_CTL_MASK)
76099
76100#define SNVS_LPATCLKR_AT2_CLK_CTL_MASK (0x30U)
76101#define SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT (4U)
76102#define SNVS_LPATCLKR_AT2_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT2_CLK_CTL_MASK)
76103
76104#define SNVS_LPATCLKR_AT3_CLK_CTL_MASK (0x300U)
76105#define SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT (8U)
76106#define SNVS_LPATCLKR_AT3_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT3_CLK_CTL_MASK)
76107
76108#define SNVS_LPATCLKR_AT4_CLK_CTL_MASK (0x3000U)
76109#define SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT (12U)
76110#define SNVS_LPATCLKR_AT4_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT4_CLK_CTL_MASK)
76111
76112#define SNVS_LPATCLKR_AT5_CLK_CTL_MASK (0x30000U)
76113#define SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT (16U)
76114#define SNVS_LPATCLKR_AT5_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT5_CLK_CTL_MASK)
76120#define SNVS_LPATRC1R_ET1RCTL_MASK (0x7U)
76121#define SNVS_LPATRC1R_ET1RCTL_SHIFT (0U)
76122#define SNVS_LPATRC1R_ET1RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET1RCTL_SHIFT)) & SNVS_LPATRC1R_ET1RCTL_MASK)
76123
76124#define SNVS_LPATRC1R_ET2RCTL_MASK (0x70U)
76125#define SNVS_LPATRC1R_ET2RCTL_SHIFT (4U)
76126#define SNVS_LPATRC1R_ET2RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET2RCTL_SHIFT)) & SNVS_LPATRC1R_ET2RCTL_MASK)
76127
76128#define SNVS_LPATRC1R_ET3RCTL_MASK (0x700U)
76129#define SNVS_LPATRC1R_ET3RCTL_SHIFT (8U)
76130#define SNVS_LPATRC1R_ET3RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET3RCTL_SHIFT)) & SNVS_LPATRC1R_ET3RCTL_MASK)
76131
76132#define SNVS_LPATRC1R_ET4RCTL_MASK (0x7000U)
76133#define SNVS_LPATRC1R_ET4RCTL_SHIFT (12U)
76134#define SNVS_LPATRC1R_ET4RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET4RCTL_SHIFT)) & SNVS_LPATRC1R_ET4RCTL_MASK)
76135
76136#define SNVS_LPATRC1R_ET5RCTL_MASK (0x70000U)
76137#define SNVS_LPATRC1R_ET5RCTL_SHIFT (16U)
76138#define SNVS_LPATRC1R_ET5RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET5RCTL_SHIFT)) & SNVS_LPATRC1R_ET5RCTL_MASK)
76139
76140#define SNVS_LPATRC1R_ET6RCTL_MASK (0x700000U)
76141#define SNVS_LPATRC1R_ET6RCTL_SHIFT (20U)
76142#define SNVS_LPATRC1R_ET6RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET6RCTL_SHIFT)) & SNVS_LPATRC1R_ET6RCTL_MASK)
76143
76144#define SNVS_LPATRC1R_ET7RCTL_MASK (0x7000000U)
76145#define SNVS_LPATRC1R_ET7RCTL_SHIFT (24U)
76146#define SNVS_LPATRC1R_ET7RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET7RCTL_SHIFT)) & SNVS_LPATRC1R_ET7RCTL_MASK)
76147
76148#define SNVS_LPATRC1R_ET8RCTL_MASK (0x70000000U)
76149#define SNVS_LPATRC1R_ET8RCTL_SHIFT (28U)
76150#define SNVS_LPATRC1R_ET8RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET8RCTL_SHIFT)) & SNVS_LPATRC1R_ET8RCTL_MASK)
76156#define SNVS_LPATRC2R_ET9RCTL_MASK (0x7U)
76157#define SNVS_LPATRC2R_ET9RCTL_SHIFT (0U)
76158#define SNVS_LPATRC2R_ET9RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET9RCTL_SHIFT)) & SNVS_LPATRC2R_ET9RCTL_MASK)
76159
76160#define SNVS_LPATRC2R_ET10RCTL_MASK (0x70U)
76161#define SNVS_LPATRC2R_ET10RCTL_SHIFT (4U)
76162#define SNVS_LPATRC2R_ET10RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET10RCTL_SHIFT)) & SNVS_LPATRC2R_ET10RCTL_MASK)
76168#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
76169#define SNVS_LPGPR_GPR_SHIFT (0U)
76170#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
76173/* The count of SNVS_LPGPR */
76174#define SNVS_LPGPR_COUNT (4U)
76175
76179#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
76180#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
76181#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
76182
76183#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
76184#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
76185#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
76186
76187#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
76188#define SNVS_HPVIDR1_IP_ID_SHIFT (16U)
76189#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
76195#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
76196#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
76197#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
76198
76199#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
76200#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
76201#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) /* end of group SNVS_Register_Masks */
76208
76209
76210/* SNVS - Peripheral instance base addresses */
76212#define SNVS_BASE (0x40C90000u)
76214#define SNVS ((SNVS_Type *)SNVS_BASE)
76216#define SNVS_BASE_ADDRS { SNVS_BASE }
76218#define SNVS_BASE_PTRS { SNVS }
76220#define SNVS_IRQS { SNVS_PULSE_EVENT_IRQn }
76221#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_NON_TZ_IRQn }
76222#define SNVS_SECURITY_IRQS { SNVS_HP_TZ_IRQn }
76223 /* end of group SNVS_Peripheral_Access_Layer */
76227
76228
76229/* ----------------------------------------------------------------------------
76230 -- SPDIF Peripheral Access Layer
76231 ---------------------------------------------------------------------------- */
76232
76239typedef struct {
76240 __IO uint32_t SCR;
76241 __IO uint32_t SRCD;
76242 __IO uint32_t SRPC;
76243 __IO uint32_t SIE;
76244 union { /* offset: 0x10 */
76245 __O uint32_t SIC;
76246 __I uint32_t SIS;
76247 };
76248 __I uint32_t SRL;
76249 __I uint32_t SRR;
76250 __I uint32_t SRCSH;
76251 __I uint32_t SRCSL;
76252 __I uint32_t SRU;
76253 __I uint32_t SRQ;
76254 __O uint32_t STL;
76255 __O uint32_t STR;
76256 __IO uint32_t STCSCH;
76257 __IO uint32_t STCSCL;
76258 uint8_t RESERVED_0[8];
76259 __I uint32_t SRFM;
76260 uint8_t RESERVED_1[8];
76261 __IO uint32_t STC;
76262} SPDIF_Type;
76263
76264/* ----------------------------------------------------------------------------
76265 -- SPDIF Register Masks
76266 ---------------------------------------------------------------------------- */
76267
76276#define SPDIF_SCR_USRC_SEL_MASK (0x3U)
76277#define SPDIF_SCR_USRC_SEL_SHIFT (0U)
76284#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
76285
76286#define SPDIF_SCR_TXSEL_MASK (0x1CU)
76287#define SPDIF_SCR_TXSEL_SHIFT (2U)
76293#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
76294
76295#define SPDIF_SCR_VALCTRL_MASK (0x20U)
76296#define SPDIF_SCR_VALCTRL_SHIFT (5U)
76301#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
76302
76303#define SPDIF_SCR_INPUTSRCSEL_MASK (0xC0U)
76304#define SPDIF_SCR_INPUTSRCSEL_SHIFT (6U)
76309#define SPDIF_SCR_INPUTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_INPUTSRCSEL_SHIFT)) & SPDIF_SCR_INPUTSRCSEL_MASK)
76310
76311#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U)
76312#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U)
76315#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
76316
76317#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U)
76318#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U)
76321#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
76322
76323#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)
76324#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)
76331#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
76332
76333#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U)
76334#define SPDIF_SCR_SOFT_RESET_SHIFT (12U)
76337#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
76338
76339#define SPDIF_SCR_LOW_POWER_MASK (0x2000U)
76340#define SPDIF_SCR_LOW_POWER_SHIFT (13U)
76343#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
76344
76345#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)
76346#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)
76353#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
76354
76355#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)
76356#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)
76361#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
76362
76363#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)
76364#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)
76369#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
76370
76371#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)
76372#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)
76379#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
76380
76381#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)
76382#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U)
76387#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
76388
76389#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)
76390#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)
76395#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
76396
76397#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)
76398#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)
76403#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
76409#define SPDIF_SRCD_USYNCMODE_MASK (0x2U)
76410#define SPDIF_SRCD_USYNCMODE_SHIFT (1U)
76415#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
76421#define SPDIF_SRPC_GAINSEL_MASK (0x38U)
76422#define SPDIF_SRPC_GAINSEL_SHIFT (3U)
76432#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
76433
76434#define SPDIF_SRPC_LOCK_MASK (0x40U)
76435#define SPDIF_SRPC_LOCK_SHIFT (6U)
76438#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
76439
76440#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)
76441#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)
76450#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
76456#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U)
76457#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U)
76460#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
76461
76462#define SPDIF_SIE_TXEM_MASK (0x2U)
76463#define SPDIF_SIE_TXEM_SHIFT (1U)
76466#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
76467
76468#define SPDIF_SIE_LOCKLOSS_MASK (0x4U)
76469#define SPDIF_SIE_LOCKLOSS_SHIFT (2U)
76472#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
76473
76474#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U)
76475#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U)
76478#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
76479
76480#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)
76481#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)
76484#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
76485
76486#define SPDIF_SIE_UQERR_MASK (0x20U)
76487#define SPDIF_SIE_UQERR_SHIFT (5U)
76490#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
76491
76492#define SPDIF_SIE_UQSYNC_MASK (0x40U)
76493#define SPDIF_SIE_UQSYNC_SHIFT (6U)
76496#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
76497
76498#define SPDIF_SIE_QRXOV_MASK (0x80U)
76499#define SPDIF_SIE_QRXOV_SHIFT (7U)
76502#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
76503
76504#define SPDIF_SIE_QRXFUL_MASK (0x100U)
76505#define SPDIF_SIE_QRXFUL_SHIFT (8U)
76508#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
76509
76510#define SPDIF_SIE_URXOV_MASK (0x200U)
76511#define SPDIF_SIE_URXOV_SHIFT (9U)
76514#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
76515
76516#define SPDIF_SIE_URXFUL_MASK (0x400U)
76517#define SPDIF_SIE_URXFUL_SHIFT (10U)
76520#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
76521
76522#define SPDIF_SIE_BITERR_MASK (0x4000U)
76523#define SPDIF_SIE_BITERR_SHIFT (14U)
76526#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
76527
76528#define SPDIF_SIE_SYMERR_MASK (0x8000U)
76529#define SPDIF_SIE_SYMERR_SHIFT (15U)
76532#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
76533
76534#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U)
76535#define SPDIF_SIE_VALNOGOOD_SHIFT (16U)
76538#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
76539
76540#define SPDIF_SIE_CNEW_MASK (0x20000U)
76541#define SPDIF_SIE_CNEW_SHIFT (17U)
76544#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
76545
76546#define SPDIF_SIE_TXRESYN_MASK (0x40000U)
76547#define SPDIF_SIE_TXRESYN_SHIFT (18U)
76550#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
76551
76552#define SPDIF_SIE_TXUNOV_MASK (0x80000U)
76553#define SPDIF_SIE_TXUNOV_SHIFT (19U)
76556#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
76557
76558#define SPDIF_SIE_LOCK_MASK (0x100000U)
76559#define SPDIF_SIE_LOCK_SHIFT (20U)
76562#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
76568#define SPDIF_SIC_LOCKLOSS_MASK (0x4U)
76569#define SPDIF_SIC_LOCKLOSS_SHIFT (2U)
76572#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
76573
76574#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U)
76575#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U)
76578#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
76579
76580#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)
76581#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)
76584#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
76585
76586#define SPDIF_SIC_UQERR_MASK (0x20U)
76587#define SPDIF_SIC_UQERR_SHIFT (5U)
76590#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
76591
76592#define SPDIF_SIC_UQSYNC_MASK (0x40U)
76593#define SPDIF_SIC_UQSYNC_SHIFT (6U)
76596#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
76597
76598#define SPDIF_SIC_QRXOV_MASK (0x80U)
76599#define SPDIF_SIC_QRXOV_SHIFT (7U)
76602#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
76603
76604#define SPDIF_SIC_URXOV_MASK (0x200U)
76605#define SPDIF_SIC_URXOV_SHIFT (9U)
76608#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
76609
76610#define SPDIF_SIC_BITERR_MASK (0x4000U)
76611#define SPDIF_SIC_BITERR_SHIFT (14U)
76614#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
76615
76616#define SPDIF_SIC_SYMERR_MASK (0x8000U)
76617#define SPDIF_SIC_SYMERR_SHIFT (15U)
76620#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
76621
76622#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U)
76623#define SPDIF_SIC_VALNOGOOD_SHIFT (16U)
76626#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
76627
76628#define SPDIF_SIC_CNEW_MASK (0x20000U)
76629#define SPDIF_SIC_CNEW_SHIFT (17U)
76632#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
76633
76634#define SPDIF_SIC_TXRESYN_MASK (0x40000U)
76635#define SPDIF_SIC_TXRESYN_SHIFT (18U)
76638#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
76639
76640#define SPDIF_SIC_TXUNOV_MASK (0x80000U)
76641#define SPDIF_SIC_TXUNOV_SHIFT (19U)
76644#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
76645
76646#define SPDIF_SIC_LOCK_MASK (0x100000U)
76647#define SPDIF_SIC_LOCK_SHIFT (20U)
76650#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
76656#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U)
76657#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U)
76660#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
76661
76662#define SPDIF_SIS_TXEM_MASK (0x2U)
76663#define SPDIF_SIS_TXEM_SHIFT (1U)
76666#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
76667
76668#define SPDIF_SIS_LOCKLOSS_MASK (0x4U)
76669#define SPDIF_SIS_LOCKLOSS_SHIFT (2U)
76672#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
76673
76674#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U)
76675#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U)
76678#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
76679
76680#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)
76681#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)
76684#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
76685
76686#define SPDIF_SIS_UQERR_MASK (0x20U)
76687#define SPDIF_SIS_UQERR_SHIFT (5U)
76690#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
76691
76692#define SPDIF_SIS_UQSYNC_MASK (0x40U)
76693#define SPDIF_SIS_UQSYNC_SHIFT (6U)
76696#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
76697
76698#define SPDIF_SIS_QRXOV_MASK (0x80U)
76699#define SPDIF_SIS_QRXOV_SHIFT (7U)
76702#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
76703
76704#define SPDIF_SIS_QRXFUL_MASK (0x100U)
76705#define SPDIF_SIS_QRXFUL_SHIFT (8U)
76708#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
76709
76710#define SPDIF_SIS_URXOV_MASK (0x200U)
76711#define SPDIF_SIS_URXOV_SHIFT (9U)
76714#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
76715
76716#define SPDIF_SIS_URXFUL_MASK (0x400U)
76717#define SPDIF_SIS_URXFUL_SHIFT (10U)
76720#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
76721
76722#define SPDIF_SIS_BITERR_MASK (0x4000U)
76723#define SPDIF_SIS_BITERR_SHIFT (14U)
76726#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
76727
76728#define SPDIF_SIS_SYMERR_MASK (0x8000U)
76729#define SPDIF_SIS_SYMERR_SHIFT (15U)
76732#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
76733
76734#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U)
76735#define SPDIF_SIS_VALNOGOOD_SHIFT (16U)
76738#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
76739
76740#define SPDIF_SIS_CNEW_MASK (0x20000U)
76741#define SPDIF_SIS_CNEW_SHIFT (17U)
76744#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
76745
76746#define SPDIF_SIS_TXRESYN_MASK (0x40000U)
76747#define SPDIF_SIS_TXRESYN_SHIFT (18U)
76750#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
76751
76752#define SPDIF_SIS_TXUNOV_MASK (0x80000U)
76753#define SPDIF_SIS_TXUNOV_SHIFT (19U)
76756#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
76757
76758#define SPDIF_SIS_LOCK_MASK (0x100000U)
76759#define SPDIF_SIS_LOCK_SHIFT (20U)
76762#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
76768#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)
76769#define SPDIF_SRL_RXDATALEFT_SHIFT (0U)
76772#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
76778#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)
76779#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U)
76782#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
76788#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)
76789#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)
76792#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
76798#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)
76799#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)
76802#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
76808#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)
76809#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U)
76812#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
76818#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)
76819#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)
76822#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
76828#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)
76829#define SPDIF_STL_TXDATALEFT_SHIFT (0U)
76832#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
76838#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)
76839#define SPDIF_STR_TXDATARIGHT_SHIFT (0U)
76842#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
76848#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)
76849#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)
76852#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
76858#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)
76859#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)
76862#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
76868#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)
76869#define SPDIF_SRFM_FREQMEAS_SHIFT (0U)
76872#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
76878#define SPDIF_STC_TXCLK_DF_MASK (0x7FU)
76879#define SPDIF_STC_TXCLK_DF_SHIFT (0U)
76885#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
76886
76887#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)
76888#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)
76893#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
76894
76895#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)
76896#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)
76903#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
76904
76905#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)
76906#define SPDIF_STC_SYSCLK_DF_SHIFT (11U)
76912#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) /* end of group SPDIF_Register_Masks */
76919
76920
76921/* SPDIF - Peripheral instance base addresses */
76923#define SPDIF_BASE (0x40400000u)
76925#define SPDIF ((SPDIF_Type *)SPDIF_BASE)
76927#define SPDIF_BASE_ADDRS { SPDIF_BASE }
76929#define SPDIF_BASE_PTRS { SPDIF }
76931#define SPDIF_IRQS { SPDIF_IRQn }
76932 /* end of group SPDIF_Peripheral_Access_Layer */
76936
76937
76938/* ----------------------------------------------------------------------------
76939 -- SRAM Peripheral Access Layer
76940 ---------------------------------------------------------------------------- */
76941
76948typedef struct {
76949 uint8_t RESERVED_0[12288];
76950 __IO uint32_t CTRL;
76951} SRAM_Type;
76952
76953/* ----------------------------------------------------------------------------
76954 -- SRAM Register Masks
76955 ---------------------------------------------------------------------------- */
76956
76965#define SRAM_CTRL_RAM_RD_EN_MASK (0x1U)
76966#define SRAM_CTRL_RAM_RD_EN_SHIFT (0U)
76971#define SRAM_CTRL_RAM_RD_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)
76972
76973#define SRAM_CTRL_RAM_WR_EN_MASK (0x2U)
76974#define SRAM_CTRL_RAM_WR_EN_SHIFT (1U)
76979#define SRAM_CTRL_RAM_WR_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)
76980
76981#define SRAM_CTRL_PWR_EN_MASK (0x3CU)
76982#define SRAM_CTRL_PWR_EN_SHIFT (2U)
76985#define SRAM_CTRL_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)
76986
76987#define SRAM_CTRL_TAMPER_BLOCK_EN_MASK (0x40U)
76988#define SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT (6U)
76993#define SRAM_CTRL_TAMPER_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)
76994
76995#define SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK (0x80U)
76996#define SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT (7U)
77001#define SRAM_CTRL_TAMPER_PWR_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)
77002
77003#define SRAM_CTRL_LOCK_BIT_MASK (0xFF0000U)
77004#define SRAM_CTRL_LOCK_BIT_SHIFT (16U)
77007#define SRAM_CTRL_LOCK_BIT(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK) /* end of group SRAM_Register_Masks */
77014
77015
77016/* SRAM - Peripheral instance base addresses */
77018#define SRAM_BASE (0x40C9C000u)
77020#define SRAM ((SRAM_Type *)SRAM_BASE)
77022#define SRAM_BASE_ADDRS { SRAM_BASE }
77024#define SRAM_BASE_PTRS { SRAM }
77025 /* end of group SRAM_Peripheral_Access_Layer */
77029
77030
77031/* ----------------------------------------------------------------------------
77032 -- SRC Peripheral Access Layer
77033 ---------------------------------------------------------------------------- */
77034
77041typedef struct {
77042 __IO uint32_t SCR;
77043 __IO uint32_t SRMR;
77044 __I uint32_t SBMR1;
77045 __I uint32_t SBMR2;
77046 __IO uint32_t SRSR;
77047 __IO uint32_t GPR[20];
77048 uint8_t RESERVED_0[412];
77049 __IO uint32_t AUTHEN_MEGA;
77050 __IO uint32_t CTRL_MEGA;
77051 __IO uint32_t SETPOINT_MEGA;
77052 __IO uint32_t DOMAIN_MEGA;
77053 __IO uint32_t STAT_MEGA;
77054 uint8_t RESERVED_1[12];
77055 __IO uint32_t AUTHEN_DISPLAY;
77056 __IO uint32_t CTRL_DISPLAY;
77057 __IO uint32_t SETPOINT_DISPLAY;
77058 __IO uint32_t DOMAIN_DISPLAY;
77059 __IO uint32_t STAT_DISPLAY;
77060 uint8_t RESERVED_2[12];
77061 __IO uint32_t AUTHEN_WAKEUP;
77062 __IO uint32_t CTRL_WAKEUP;
77063 __IO uint32_t SETPOINT_WAKEUP;
77064 __IO uint32_t DOMAIN_WAKEUP;
77065 __IO uint32_t STAT_WAKEUP;
77066 uint8_t RESERVED_3[44];
77067 __IO uint32_t AUTHEN_M4CORE;
77068 __IO uint32_t CTRL_M4CORE;
77069 __IO uint32_t SETPOINT_M4CORE;
77070 __IO uint32_t DOMAIN_M4CORE;
77071 __IO uint32_t STAT_M4CORE;
77072 uint8_t RESERVED_4[12];
77073 __IO uint32_t AUTHEN_M7CORE;
77074 __IO uint32_t CTRL_M7CORE;
77075 __IO uint32_t SETPOINT_M7CORE;
77076 __IO uint32_t DOMAIN_M7CORE;
77077 __IO uint32_t STAT_M7CORE;
77078 uint8_t RESERVED_5[12];
77079 __IO uint32_t AUTHEN_M4DEBUG;
77080 __IO uint32_t CTRL_M4DEBUG;
77081 __IO uint32_t SETPOINT_M4DEBUG;
77082 __IO uint32_t DOMAIN_M4DEBUG;
77083 __IO uint32_t STAT_M4DEBUG;
77084 uint8_t RESERVED_6[12];
77085 __IO uint32_t AUTHEN_M7DEBUG;
77086 __IO uint32_t CTRL_M7DEBUG;
77087 __IO uint32_t SETPOINT_M7DEBUG;
77088 __IO uint32_t DOMAIN_M7DEBUG;
77089 __IO uint32_t STAT_M7DEBUG;
77090 uint8_t RESERVED_7[12];
77091 __IO uint32_t AUTHEN_USBPHY1;
77092 __IO uint32_t CTRL_USBPHY1;
77093 __IO uint32_t SETPOINT_USBPHY1;
77094 __IO uint32_t DOMAIN_USBPHY1;
77095 __IO uint32_t STAT_USBPHY1;
77096 uint8_t RESERVED_8[12];
77097 __IO uint32_t AUTHEN_USBPHY2;
77098 __IO uint32_t CTRL_USBPHY2;
77099 __IO uint32_t SETPOINT_USBPHY2;
77100 __IO uint32_t DOMAIN_USBPHY2;
77101 __IO uint32_t STAT_USBPHY2;
77102} SRC_Type;
77103
77104/* ----------------------------------------------------------------------------
77105 -- SRC Register Masks
77106 ---------------------------------------------------------------------------- */
77107
77116#define SRC_SCR_BT_RELEASE_M4_MASK (0x1U)
77117#define SRC_SCR_BT_RELEASE_M4_SHIFT (0U)
77122#define SRC_SCR_BT_RELEASE_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M4_SHIFT)) & SRC_SCR_BT_RELEASE_M4_MASK)
77123
77124#define SRC_SCR_BT_RELEASE_M7_MASK (0x2U)
77125#define SRC_SCR_BT_RELEASE_M7_SHIFT (1U)
77130#define SRC_SCR_BT_RELEASE_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M7_SHIFT)) & SRC_SCR_BT_RELEASE_M7_MASK)
77136#define SRC_SRMR_WDOG_RESET_MODE_MASK (0x3U)
77137#define SRC_SRMR_WDOG_RESET_MODE_SHIFT (0U)
77144#define SRC_SRMR_WDOG_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG_RESET_MODE_MASK)
77145
77146#define SRC_SRMR_WDOG3_RESET_MODE_MASK (0xCU)
77147#define SRC_SRMR_WDOG3_RESET_MODE_SHIFT (2U)
77154#define SRC_SRMR_WDOG3_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG3_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG3_RESET_MODE_MASK)
77155
77156#define SRC_SRMR_WDOG4_RESET_MODE_MASK (0x30U)
77157#define SRC_SRMR_WDOG4_RESET_MODE_SHIFT (4U)
77164#define SRC_SRMR_WDOG4_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG4_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG4_RESET_MODE_MASK)
77165
77166#define SRC_SRMR_M4LOCKUP_RESET_MODE_MASK (0xC0U)
77167#define SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT (6U)
77174#define SRC_SRMR_M4LOCKUP_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M4LOCKUP_RESET_MODE_MASK)
77175
77176#define SRC_SRMR_M7LOCKUP_RESET_MODE_MASK (0x300U)
77177#define SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT (8U)
77184#define SRC_SRMR_M7LOCKUP_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M7LOCKUP_RESET_MODE_MASK)
77185
77186#define SRC_SRMR_M4REQ_RESET_MODE_MASK (0xC00U)
77187#define SRC_SRMR_M4REQ_RESET_MODE_SHIFT (10U)
77194#define SRC_SRMR_M4REQ_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M4REQ_RESET_MODE_MASK)
77195
77196#define SRC_SRMR_M7REQ_RESET_MODE_MASK (0x3000U)
77197#define SRC_SRMR_M7REQ_RESET_MODE_SHIFT (12U)
77204#define SRC_SRMR_M7REQ_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M7REQ_RESET_MODE_MASK)
77205
77206#define SRC_SRMR_TEMPSENSE_RESET_MODE_MASK (0xC000U)
77207#define SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT (14U)
77214#define SRC_SRMR_TEMPSENSE_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_SRMR_TEMPSENSE_RESET_MODE_MASK)
77215
77216#define SRC_SRMR_CSU_RESET_MODE_MASK (0x30000U)
77217#define SRC_SRMR_CSU_RESET_MODE_SHIFT (16U)
77224#define SRC_SRMR_CSU_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_CSU_RESET_MODE_SHIFT)) & SRC_SRMR_CSU_RESET_MODE_MASK)
77225
77226#define SRC_SRMR_JTAGSW_RESET_MODE_MASK (0xC0000U)
77227#define SRC_SRMR_JTAGSW_RESET_MODE_SHIFT (18U)
77234#define SRC_SRMR_JTAGSW_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_JTAGSW_RESET_MODE_SHIFT)) & SRC_SRMR_JTAGSW_RESET_MODE_MASK)
77235
77236#define SRC_SRMR_OVERVOLT_RESET_MODE_MASK (0x300000U)
77237#define SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT (20U)
77244#define SRC_SRMR_OVERVOLT_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT)) & SRC_SRMR_OVERVOLT_RESET_MODE_MASK)
77250#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)
77251#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U)
77252#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
77253
77254#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)
77255#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U)
77256#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
77257
77258#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)
77259#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U)
77260#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
77261
77262#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)
77263#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U)
77264#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
77270#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
77271#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
77272#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
77273
77274#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
77275#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
77276#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
77277
77278#define SRC_SBMR2_BMOD_MASK (0x3000000U)
77279#define SRC_SBMR2_BMOD_SHIFT (24U)
77280#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
77286#define SRC_SRSR_IPP_RESET_B_M7_MASK (0x1U)
77287#define SRC_SRSR_IPP_RESET_B_M7_SHIFT (0U)
77292#define SRC_SRSR_IPP_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_RESET_B_M7_MASK)
77293
77294#define SRC_SRSR_M7_REQUEST_M7_MASK (0x2U)
77295#define SRC_SRSR_M7_REQUEST_M7_SHIFT (1U)
77300#define SRC_SRSR_M7_REQUEST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M7_SHIFT)) & SRC_SRSR_M7_REQUEST_M7_MASK)
77301
77302#define SRC_SRSR_M7_LOCKUP_M7_MASK (0x4U)
77303#define SRC_SRSR_M7_LOCKUP_M7_SHIFT (2U)
77308#define SRC_SRSR_M7_LOCKUP_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M7_SHIFT)) & SRC_SRSR_M7_LOCKUP_M7_MASK)
77309
77310#define SRC_SRSR_CSU_RESET_B_M7_MASK (0x8U)
77311#define SRC_SRSR_CSU_RESET_B_M7_SHIFT (3U)
77316#define SRC_SRSR_CSU_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M7_SHIFT)) & SRC_SRSR_CSU_RESET_B_M7_MASK)
77317
77318#define SRC_SRSR_IPP_USER_RESET_B_M7_MASK (0x10U)
77319#define SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT (4U)
77324#define SRC_SRSR_IPP_USER_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M7_MASK)
77325
77326#define SRC_SRSR_WDOG_RST_B_M7_MASK (0x20U)
77327#define SRC_SRSR_WDOG_RST_B_M7_SHIFT (5U)
77332#define SRC_SRSR_WDOG_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG_RST_B_M7_MASK)
77333
77334#define SRC_SRSR_JTAG_RST_B_M7_MASK (0x40U)
77335#define SRC_SRSR_JTAG_RST_B_M7_SHIFT (6U)
77340#define SRC_SRSR_JTAG_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M7_SHIFT)) & SRC_SRSR_JTAG_RST_B_M7_MASK)
77341
77342#define SRC_SRSR_JTAG_SW_RST_M7_MASK (0x80U)
77343#define SRC_SRSR_JTAG_SW_RST_M7_SHIFT (7U)
77348#define SRC_SRSR_JTAG_SW_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M7_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M7_MASK)
77349
77350#define SRC_SRSR_WDOG3_RST_B_M7_MASK (0x100U)
77351#define SRC_SRSR_WDOG3_RST_B_M7_SHIFT (8U)
77356#define SRC_SRSR_WDOG3_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M7_MASK)
77357
77358#define SRC_SRSR_WDOG4_RST_B_M7_MASK (0x200U)
77359#define SRC_SRSR_WDOG4_RST_B_M7_SHIFT (9U)
77364#define SRC_SRSR_WDOG4_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M7_MASK)
77365
77366#define SRC_SRSR_TEMPSENSE_RST_B_M7_MASK (0x400U)
77367#define SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT (10U)
77372#define SRC_SRSR_TEMPSENSE_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M7_MASK)
77373
77374#define SRC_SRSR_M4_REQUEST_M7_MASK (0x800U)
77375#define SRC_SRSR_M4_REQUEST_M7_SHIFT (11U)
77380#define SRC_SRSR_M4_REQUEST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M7_SHIFT)) & SRC_SRSR_M4_REQUEST_M7_MASK)
77381
77382#define SRC_SRSR_M4_LOCKUP_M7_MASK (0x1000U)
77383#define SRC_SRSR_M4_LOCKUP_M7_SHIFT (12U)
77388#define SRC_SRSR_M4_LOCKUP_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M7_SHIFT)) & SRC_SRSR_M4_LOCKUP_M7_MASK)
77389
77390#define SRC_SRSR_OVERVOLT_RST_M7_MASK (0x2000U)
77391#define SRC_SRSR_OVERVOLT_RST_M7_SHIFT (13U)
77396#define SRC_SRSR_OVERVOLT_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M7_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M7_MASK)
77397
77398#define SRC_SRSR_CDOG_RST_M7_MASK (0x4000U)
77399#define SRC_SRSR_CDOG_RST_M7_SHIFT (14U)
77404#define SRC_SRSR_CDOG_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M7_SHIFT)) & SRC_SRSR_CDOG_RST_M7_MASK)
77405
77406#define SRC_SRSR_IPP_RESET_B_M4_MASK (0x10000U)
77407#define SRC_SRSR_IPP_RESET_B_M4_SHIFT (16U)
77412#define SRC_SRSR_IPP_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_RESET_B_M4_MASK)
77413
77414#define SRC_SRSR_M4_REQUEST_M4_MASK (0x20000U)
77415#define SRC_SRSR_M4_REQUEST_M4_SHIFT (17U)
77420#define SRC_SRSR_M4_REQUEST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M4_SHIFT)) & SRC_SRSR_M4_REQUEST_M4_MASK)
77421
77422#define SRC_SRSR_M4_LOCKUP_M4_MASK (0x40000U)
77423#define SRC_SRSR_M4_LOCKUP_M4_SHIFT (18U)
77428#define SRC_SRSR_M4_LOCKUP_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M4_SHIFT)) & SRC_SRSR_M4_LOCKUP_M4_MASK)
77429
77430#define SRC_SRSR_CSU_RESET_B_M4_MASK (0x80000U)
77431#define SRC_SRSR_CSU_RESET_B_M4_SHIFT (19U)
77436#define SRC_SRSR_CSU_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M4_SHIFT)) & SRC_SRSR_CSU_RESET_B_M4_MASK)
77437
77438#define SRC_SRSR_IPP_USER_RESET_B_M4_MASK (0x100000U)
77439#define SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT (20U)
77444#define SRC_SRSR_IPP_USER_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M4_MASK)
77445
77446#define SRC_SRSR_WDOG_RST_B_M4_MASK (0x200000U)
77447#define SRC_SRSR_WDOG_RST_B_M4_SHIFT (21U)
77452#define SRC_SRSR_WDOG_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG_RST_B_M4_MASK)
77453
77454#define SRC_SRSR_JTAG_RST_B_M4_MASK (0x400000U)
77455#define SRC_SRSR_JTAG_RST_B_M4_SHIFT (22U)
77460#define SRC_SRSR_JTAG_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M4_SHIFT)) & SRC_SRSR_JTAG_RST_B_M4_MASK)
77461
77462#define SRC_SRSR_JTAG_SW_RST_M4_MASK (0x800000U)
77463#define SRC_SRSR_JTAG_SW_RST_M4_SHIFT (23U)
77468#define SRC_SRSR_JTAG_SW_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M4_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M4_MASK)
77469
77470#define SRC_SRSR_WDOG3_RST_B_M4_MASK (0x1000000U)
77471#define SRC_SRSR_WDOG3_RST_B_M4_SHIFT (24U)
77476#define SRC_SRSR_WDOG3_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M4_MASK)
77477
77478#define SRC_SRSR_WDOG4_RST_B_M4_MASK (0x2000000U)
77479#define SRC_SRSR_WDOG4_RST_B_M4_SHIFT (25U)
77484#define SRC_SRSR_WDOG4_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M4_MASK)
77485
77486#define SRC_SRSR_TEMPSENSE_RST_B_M4_MASK (0x4000000U)
77487#define SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT (26U)
77492#define SRC_SRSR_TEMPSENSE_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M4_MASK)
77493
77494#define SRC_SRSR_M7_REQUEST_M4_MASK (0x8000000U)
77495#define SRC_SRSR_M7_REQUEST_M4_SHIFT (27U)
77500#define SRC_SRSR_M7_REQUEST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M4_SHIFT)) & SRC_SRSR_M7_REQUEST_M4_MASK)
77501
77502#define SRC_SRSR_M7_LOCKUP_M4_MASK (0x10000000U)
77503#define SRC_SRSR_M7_LOCKUP_M4_SHIFT (28U)
77508#define SRC_SRSR_M7_LOCKUP_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M4_SHIFT)) & SRC_SRSR_M7_LOCKUP_M4_MASK)
77509
77510#define SRC_SRSR_OVERVOLT_RST_M4_MASK (0x20000000U)
77511#define SRC_SRSR_OVERVOLT_RST_M4_SHIFT (29U)
77516#define SRC_SRSR_OVERVOLT_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M4_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M4_MASK)
77517
77518#define SRC_SRSR_CDOG_RST_M4_MASK (0x40000000U)
77519#define SRC_SRSR_CDOG_RST_M4_SHIFT (30U)
77524#define SRC_SRSR_CDOG_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M4_SHIFT)) & SRC_SRSR_CDOG_RST_M4_MASK)
77530#define SRC_GPR_GPR_MASK (0xFFFFFFFFU)
77531#define SRC_GPR_GPR_SHIFT (0U)
77534#define SRC_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_GPR_SHIFT)) & SRC_GPR_GPR_MASK)
77537/* The count of SRC_GPR */
77538#define SRC_GPR_COUNT (20U)
77539
77543#define SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK (0x1U)
77544#define SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT (0U)
77549#define SRC_AUTHEN_MEGA_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK)
77550
77551#define SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK (0x2U)
77552#define SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT (1U)
77557#define SRC_AUTHEN_MEGA_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK)
77558
77559#define SRC_AUTHEN_MEGA_LOCK_MODE_MASK (0x80U)
77560#define SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT (7U)
77563#define SRC_AUTHEN_MEGA_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_MODE_MASK)
77564
77565#define SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK (0xF00U)
77566#define SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT (8U)
77567#define SRC_AUTHEN_MEGA_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK)
77568
77569#define SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK (0x8000U)
77570#define SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT (15U)
77573#define SRC_AUTHEN_MEGA_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK)
77574
77575#define SRC_AUTHEN_MEGA_WHITE_LIST_MASK (0xF0000U)
77576#define SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT (16U)
77579#define SRC_AUTHEN_MEGA_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT)) & SRC_AUTHEN_MEGA_WHITE_LIST_MASK)
77580
77581#define SRC_AUTHEN_MEGA_LOCK_LIST_MASK (0x800000U)
77582#define SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT (23U)
77585#define SRC_AUTHEN_MEGA_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_LIST_MASK)
77586
77587#define SRC_AUTHEN_MEGA_USER_MASK (0x1000000U)
77588#define SRC_AUTHEN_MEGA_USER_SHIFT (24U)
77591#define SRC_AUTHEN_MEGA_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_USER_SHIFT)) & SRC_AUTHEN_MEGA_USER_MASK)
77592
77593#define SRC_AUTHEN_MEGA_NONSECURE_MASK (0x2000000U)
77594#define SRC_AUTHEN_MEGA_NONSECURE_SHIFT (25U)
77597#define SRC_AUTHEN_MEGA_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_NONSECURE_SHIFT)) & SRC_AUTHEN_MEGA_NONSECURE_MASK)
77598
77599#define SRC_AUTHEN_MEGA_LOCK_SETTING_MASK (0x80000000U)
77600#define SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT (31U)
77603#define SRC_AUTHEN_MEGA_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_SETTING_MASK)
77609#define SRC_CTRL_MEGA_SW_RESET_MASK (0x1U)
77610#define SRC_CTRL_MEGA_SW_RESET_SHIFT (0U)
77615#define SRC_CTRL_MEGA_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_MEGA_SW_RESET_SHIFT)) & SRC_CTRL_MEGA_SW_RESET_MASK)
77621#define SRC_SETPOINT_MEGA_SETPOINT0_MASK (0x1U)
77622#define SRC_SETPOINT_MEGA_SETPOINT0_SHIFT (0U)
77627#define SRC_SETPOINT_MEGA_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT0_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT0_MASK)
77628
77629#define SRC_SETPOINT_MEGA_SETPOINT1_MASK (0x2U)
77630#define SRC_SETPOINT_MEGA_SETPOINT1_SHIFT (1U)
77635#define SRC_SETPOINT_MEGA_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT1_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT1_MASK)
77636
77637#define SRC_SETPOINT_MEGA_SETPOINT2_MASK (0x4U)
77638#define SRC_SETPOINT_MEGA_SETPOINT2_SHIFT (2U)
77643#define SRC_SETPOINT_MEGA_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT2_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT2_MASK)
77644
77645#define SRC_SETPOINT_MEGA_SETPOINT3_MASK (0x8U)
77646#define SRC_SETPOINT_MEGA_SETPOINT3_SHIFT (3U)
77651#define SRC_SETPOINT_MEGA_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT3_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT3_MASK)
77652
77653#define SRC_SETPOINT_MEGA_SETPOINT4_MASK (0x10U)
77654#define SRC_SETPOINT_MEGA_SETPOINT4_SHIFT (4U)
77659#define SRC_SETPOINT_MEGA_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT4_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT4_MASK)
77660
77661#define SRC_SETPOINT_MEGA_SETPOINT5_MASK (0x20U)
77662#define SRC_SETPOINT_MEGA_SETPOINT5_SHIFT (5U)
77667#define SRC_SETPOINT_MEGA_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT5_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT5_MASK)
77668
77669#define SRC_SETPOINT_MEGA_SETPOINT6_MASK (0x40U)
77670#define SRC_SETPOINT_MEGA_SETPOINT6_SHIFT (6U)
77675#define SRC_SETPOINT_MEGA_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT6_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT6_MASK)
77676
77677#define SRC_SETPOINT_MEGA_SETPOINT7_MASK (0x80U)
77678#define SRC_SETPOINT_MEGA_SETPOINT7_SHIFT (7U)
77683#define SRC_SETPOINT_MEGA_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT7_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT7_MASK)
77684
77685#define SRC_SETPOINT_MEGA_SETPOINT8_MASK (0x100U)
77686#define SRC_SETPOINT_MEGA_SETPOINT8_SHIFT (8U)
77691#define SRC_SETPOINT_MEGA_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT8_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT8_MASK)
77692
77693#define SRC_SETPOINT_MEGA_SETPOINT9_MASK (0x200U)
77694#define SRC_SETPOINT_MEGA_SETPOINT9_SHIFT (9U)
77699#define SRC_SETPOINT_MEGA_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT9_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT9_MASK)
77700
77701#define SRC_SETPOINT_MEGA_SETPOINT10_MASK (0x400U)
77702#define SRC_SETPOINT_MEGA_SETPOINT10_SHIFT (10U)
77707#define SRC_SETPOINT_MEGA_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT10_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT10_MASK)
77708
77709#define SRC_SETPOINT_MEGA_SETPOINT11_MASK (0x800U)
77710#define SRC_SETPOINT_MEGA_SETPOINT11_SHIFT (11U)
77715#define SRC_SETPOINT_MEGA_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT11_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT11_MASK)
77716
77717#define SRC_SETPOINT_MEGA_SETPOINT12_MASK (0x1000U)
77718#define SRC_SETPOINT_MEGA_SETPOINT12_SHIFT (12U)
77723#define SRC_SETPOINT_MEGA_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT12_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT12_MASK)
77724
77725#define SRC_SETPOINT_MEGA_SETPOINT13_MASK (0x2000U)
77726#define SRC_SETPOINT_MEGA_SETPOINT13_SHIFT (13U)
77731#define SRC_SETPOINT_MEGA_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT13_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT13_MASK)
77732
77733#define SRC_SETPOINT_MEGA_SETPOINT14_MASK (0x4000U)
77734#define SRC_SETPOINT_MEGA_SETPOINT14_SHIFT (14U)
77739#define SRC_SETPOINT_MEGA_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT14_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT14_MASK)
77740
77741#define SRC_SETPOINT_MEGA_SETPOINT15_MASK (0x8000U)
77742#define SRC_SETPOINT_MEGA_SETPOINT15_SHIFT (15U)
77747#define SRC_SETPOINT_MEGA_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT15_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT15_MASK)
77753#define SRC_DOMAIN_MEGA_CPU0_RUN_MASK (0x1U)
77754#define SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT (0U)
77759#define SRC_DOMAIN_MEGA_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_RUN_MASK)
77760
77761#define SRC_DOMAIN_MEGA_CPU0_WAIT_MASK (0x2U)
77762#define SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT (1U)
77767#define SRC_DOMAIN_MEGA_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_WAIT_MASK)
77768
77769#define SRC_DOMAIN_MEGA_CPU0_STOP_MASK (0x4U)
77770#define SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT (2U)
77775#define SRC_DOMAIN_MEGA_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_STOP_MASK)
77776
77777#define SRC_DOMAIN_MEGA_CPU0_SUSP_MASK (0x8U)
77778#define SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT (3U)
77783#define SRC_DOMAIN_MEGA_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_SUSP_MASK)
77784
77785#define SRC_DOMAIN_MEGA_CPU1_RUN_MASK (0x10U)
77786#define SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT (4U)
77791#define SRC_DOMAIN_MEGA_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_RUN_MASK)
77792
77793#define SRC_DOMAIN_MEGA_CPU1_WAIT_MASK (0x20U)
77794#define SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT (5U)
77799#define SRC_DOMAIN_MEGA_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_WAIT_MASK)
77800
77801#define SRC_DOMAIN_MEGA_CPU1_STOP_MASK (0x40U)
77802#define SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT (6U)
77807#define SRC_DOMAIN_MEGA_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_STOP_MASK)
77808
77809#define SRC_DOMAIN_MEGA_CPU1_SUSP_MASK (0x80U)
77810#define SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT (7U)
77815#define SRC_DOMAIN_MEGA_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_SUSP_MASK)
77821#define SRC_STAT_MEGA_UNDER_RST_MASK (0x1U)
77822#define SRC_STAT_MEGA_UNDER_RST_SHIFT (0U)
77827#define SRC_STAT_MEGA_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_UNDER_RST_SHIFT)) & SRC_STAT_MEGA_UNDER_RST_MASK)
77828
77829#define SRC_STAT_MEGA_RST_BY_HW_MASK (0x4U)
77830#define SRC_STAT_MEGA_RST_BY_HW_SHIFT (2U)
77835#define SRC_STAT_MEGA_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_HW_SHIFT)) & SRC_STAT_MEGA_RST_BY_HW_MASK)
77836
77837#define SRC_STAT_MEGA_RST_BY_SW_MASK (0x8U)
77838#define SRC_STAT_MEGA_RST_BY_SW_SHIFT (3U)
77843#define SRC_STAT_MEGA_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_SW_SHIFT)) & SRC_STAT_MEGA_RST_BY_SW_MASK)
77849#define SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK (0x1U)
77850#define SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT (0U)
77855#define SRC_AUTHEN_DISPLAY_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK)
77856
77857#define SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK (0x2U)
77858#define SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT (1U)
77863#define SRC_AUTHEN_DISPLAY_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK)
77864
77865#define SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK (0x80U)
77866#define SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT (7U)
77869#define SRC_AUTHEN_DISPLAY_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK)
77870
77871#define SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK (0xF00U)
77872#define SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT (8U)
77873#define SRC_AUTHEN_DISPLAY_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK)
77874
77875#define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK (0x8000U)
77876#define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT (15U)
77879#define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK)
77880
77881#define SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK (0xF0000U)
77882#define SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT (16U)
77885#define SRC_AUTHEN_DISPLAY_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK)
77886
77887#define SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK (0x800000U)
77888#define SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT (23U)
77891#define SRC_AUTHEN_DISPLAY_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK)
77892
77893#define SRC_AUTHEN_DISPLAY_USER_MASK (0x1000000U)
77894#define SRC_AUTHEN_DISPLAY_USER_SHIFT (24U)
77897#define SRC_AUTHEN_DISPLAY_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_USER_SHIFT)) & SRC_AUTHEN_DISPLAY_USER_MASK)
77898
77899#define SRC_AUTHEN_DISPLAY_NONSECURE_MASK (0x2000000U)
77900#define SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT (25U)
77903#define SRC_AUTHEN_DISPLAY_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT)) & SRC_AUTHEN_DISPLAY_NONSECURE_MASK)
77904
77905#define SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK (0x80000000U)
77906#define SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT (31U)
77909#define SRC_AUTHEN_DISPLAY_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK)
77915#define SRC_CTRL_DISPLAY_SW_RESET_MASK (0x1U)
77916#define SRC_CTRL_DISPLAY_SW_RESET_SHIFT (0U)
77921#define SRC_CTRL_DISPLAY_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_DISPLAY_SW_RESET_SHIFT)) & SRC_CTRL_DISPLAY_SW_RESET_MASK)
77927#define SRC_SETPOINT_DISPLAY_SETPOINT0_MASK (0x1U)
77928#define SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT (0U)
77933#define SRC_SETPOINT_DISPLAY_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT0_MASK)
77934
77935#define SRC_SETPOINT_DISPLAY_SETPOINT1_MASK (0x2U)
77936#define SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT (1U)
77941#define SRC_SETPOINT_DISPLAY_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT1_MASK)
77942
77943#define SRC_SETPOINT_DISPLAY_SETPOINT2_MASK (0x4U)
77944#define SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT (2U)
77949#define SRC_SETPOINT_DISPLAY_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT2_MASK)
77950
77951#define SRC_SETPOINT_DISPLAY_SETPOINT3_MASK (0x8U)
77952#define SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT (3U)
77957#define SRC_SETPOINT_DISPLAY_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT3_MASK)
77958
77959#define SRC_SETPOINT_DISPLAY_SETPOINT4_MASK (0x10U)
77960#define SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT (4U)
77965#define SRC_SETPOINT_DISPLAY_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT4_MASK)
77966
77967#define SRC_SETPOINT_DISPLAY_SETPOINT5_MASK (0x20U)
77968#define SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT (5U)
77973#define SRC_SETPOINT_DISPLAY_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT5_MASK)
77974
77975#define SRC_SETPOINT_DISPLAY_SETPOINT6_MASK (0x40U)
77976#define SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT (6U)
77981#define SRC_SETPOINT_DISPLAY_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT6_MASK)
77982
77983#define SRC_SETPOINT_DISPLAY_SETPOINT7_MASK (0x80U)
77984#define SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT (7U)
77989#define SRC_SETPOINT_DISPLAY_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT7_MASK)
77990
77991#define SRC_SETPOINT_DISPLAY_SETPOINT8_MASK (0x100U)
77992#define SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT (8U)
77997#define SRC_SETPOINT_DISPLAY_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT8_MASK)
77998
77999#define SRC_SETPOINT_DISPLAY_SETPOINT9_MASK (0x200U)
78000#define SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT (9U)
78005#define SRC_SETPOINT_DISPLAY_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT9_MASK)
78006
78007#define SRC_SETPOINT_DISPLAY_SETPOINT10_MASK (0x400U)
78008#define SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT (10U)
78013#define SRC_SETPOINT_DISPLAY_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT10_MASK)
78014
78015#define SRC_SETPOINT_DISPLAY_SETPOINT11_MASK (0x800U)
78016#define SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT (11U)
78021#define SRC_SETPOINT_DISPLAY_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT11_MASK)
78022
78023#define SRC_SETPOINT_DISPLAY_SETPOINT12_MASK (0x1000U)
78024#define SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT (12U)
78029#define SRC_SETPOINT_DISPLAY_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT12_MASK)
78030
78031#define SRC_SETPOINT_DISPLAY_SETPOINT13_MASK (0x2000U)
78032#define SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT (13U)
78037#define SRC_SETPOINT_DISPLAY_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT13_MASK)
78038
78039#define SRC_SETPOINT_DISPLAY_SETPOINT14_MASK (0x4000U)
78040#define SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT (14U)
78045#define SRC_SETPOINT_DISPLAY_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT14_MASK)
78046
78047#define SRC_SETPOINT_DISPLAY_SETPOINT15_MASK (0x8000U)
78048#define SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT (15U)
78053#define SRC_SETPOINT_DISPLAY_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT15_MASK)
78059#define SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK (0x1U)
78060#define SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT (0U)
78065#define SRC_DOMAIN_DISPLAY_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK)
78066
78067#define SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK (0x2U)
78068#define SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT (1U)
78073#define SRC_DOMAIN_DISPLAY_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK)
78074
78075#define SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK (0x4U)
78076#define SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT (2U)
78081#define SRC_DOMAIN_DISPLAY_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK)
78082
78083#define SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK (0x8U)
78084#define SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT (3U)
78089#define SRC_DOMAIN_DISPLAY_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK)
78090
78091#define SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK (0x10U)
78092#define SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT (4U)
78097#define SRC_DOMAIN_DISPLAY_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK)
78098
78099#define SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK (0x20U)
78100#define SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT (5U)
78105#define SRC_DOMAIN_DISPLAY_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK)
78106
78107#define SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK (0x40U)
78108#define SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT (6U)
78113#define SRC_DOMAIN_DISPLAY_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK)
78114
78115#define SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK (0x80U)
78116#define SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT (7U)
78121#define SRC_DOMAIN_DISPLAY_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK)
78127#define SRC_STAT_DISPLAY_UNDER_RST_MASK (0x1U)
78128#define SRC_STAT_DISPLAY_UNDER_RST_SHIFT (0U)
78133#define SRC_STAT_DISPLAY_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_UNDER_RST_SHIFT)) & SRC_STAT_DISPLAY_UNDER_RST_MASK)
78134
78135#define SRC_STAT_DISPLAY_RST_BY_HW_MASK (0x4U)
78136#define SRC_STAT_DISPLAY_RST_BY_HW_SHIFT (2U)
78141#define SRC_STAT_DISPLAY_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_HW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_HW_MASK)
78142
78143#define SRC_STAT_DISPLAY_RST_BY_SW_MASK (0x8U)
78144#define SRC_STAT_DISPLAY_RST_BY_SW_SHIFT (3U)
78149#define SRC_STAT_DISPLAY_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_SW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_SW_MASK)
78155#define SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK (0x1U)
78156#define SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT (0U)
78161#define SRC_AUTHEN_WAKEUP_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK)
78162
78163#define SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK (0x2U)
78164#define SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT (1U)
78169#define SRC_AUTHEN_WAKEUP_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK)
78170
78171#define SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK (0x80U)
78172#define SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT (7U)
78175#define SRC_AUTHEN_WAKEUP_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK)
78176
78177#define SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK (0xF00U)
78178#define SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT (8U)
78179#define SRC_AUTHEN_WAKEUP_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK)
78180
78181#define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK (0x8000U)
78182#define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT (15U)
78185#define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK)
78186
78187#define SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK (0xF0000U)
78188#define SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT (16U)
78191#define SRC_AUTHEN_WAKEUP_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK)
78192
78193#define SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK (0x800000U)
78194#define SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT (23U)
78197#define SRC_AUTHEN_WAKEUP_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK)
78198
78199#define SRC_AUTHEN_WAKEUP_USER_MASK (0x1000000U)
78200#define SRC_AUTHEN_WAKEUP_USER_SHIFT (24U)
78203#define SRC_AUTHEN_WAKEUP_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_USER_SHIFT)) & SRC_AUTHEN_WAKEUP_USER_MASK)
78204
78205#define SRC_AUTHEN_WAKEUP_NONSECURE_MASK (0x2000000U)
78206#define SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT (25U)
78209#define SRC_AUTHEN_WAKEUP_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT)) & SRC_AUTHEN_WAKEUP_NONSECURE_MASK)
78210
78211#define SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK (0x80000000U)
78212#define SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT (31U)
78215#define SRC_AUTHEN_WAKEUP_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK)
78221#define SRC_CTRL_WAKEUP_SW_RESET_MASK (0x1U)
78222#define SRC_CTRL_WAKEUP_SW_RESET_SHIFT (0U)
78227#define SRC_CTRL_WAKEUP_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_WAKEUP_SW_RESET_SHIFT)) & SRC_CTRL_WAKEUP_SW_RESET_MASK)
78233#define SRC_SETPOINT_WAKEUP_SETPOINT0_MASK (0x1U)
78234#define SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT (0U)
78239#define SRC_SETPOINT_WAKEUP_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT0_MASK)
78240
78241#define SRC_SETPOINT_WAKEUP_SETPOINT1_MASK (0x2U)
78242#define SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT (1U)
78247#define SRC_SETPOINT_WAKEUP_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT1_MASK)
78248
78249#define SRC_SETPOINT_WAKEUP_SETPOINT2_MASK (0x4U)
78250#define SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT (2U)
78255#define SRC_SETPOINT_WAKEUP_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT2_MASK)
78256
78257#define SRC_SETPOINT_WAKEUP_SETPOINT3_MASK (0x8U)
78258#define SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT (3U)
78263#define SRC_SETPOINT_WAKEUP_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT3_MASK)
78264
78265#define SRC_SETPOINT_WAKEUP_SETPOINT4_MASK (0x10U)
78266#define SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT (4U)
78271#define SRC_SETPOINT_WAKEUP_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT4_MASK)
78272
78273#define SRC_SETPOINT_WAKEUP_SETPOINT5_MASK (0x20U)
78274#define SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT (5U)
78279#define SRC_SETPOINT_WAKEUP_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT5_MASK)
78280
78281#define SRC_SETPOINT_WAKEUP_SETPOINT6_MASK (0x40U)
78282#define SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT (6U)
78287#define SRC_SETPOINT_WAKEUP_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT6_MASK)
78288
78289#define SRC_SETPOINT_WAKEUP_SETPOINT7_MASK (0x80U)
78290#define SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT (7U)
78295#define SRC_SETPOINT_WAKEUP_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT7_MASK)
78296
78297#define SRC_SETPOINT_WAKEUP_SETPOINT8_MASK (0x100U)
78298#define SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT (8U)
78303#define SRC_SETPOINT_WAKEUP_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT8_MASK)
78304
78305#define SRC_SETPOINT_WAKEUP_SETPOINT9_MASK (0x200U)
78306#define SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT (9U)
78311#define SRC_SETPOINT_WAKEUP_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT9_MASK)
78312
78313#define SRC_SETPOINT_WAKEUP_SETPOINT10_MASK (0x400U)
78314#define SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT (10U)
78319#define SRC_SETPOINT_WAKEUP_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT10_MASK)
78320
78321#define SRC_SETPOINT_WAKEUP_SETPOINT11_MASK (0x800U)
78322#define SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT (11U)
78327#define SRC_SETPOINT_WAKEUP_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT11_MASK)
78328
78329#define SRC_SETPOINT_WAKEUP_SETPOINT12_MASK (0x1000U)
78330#define SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT (12U)
78335#define SRC_SETPOINT_WAKEUP_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT12_MASK)
78336
78337#define SRC_SETPOINT_WAKEUP_SETPOINT13_MASK (0x2000U)
78338#define SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT (13U)
78343#define SRC_SETPOINT_WAKEUP_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT13_MASK)
78344
78345#define SRC_SETPOINT_WAKEUP_SETPOINT14_MASK (0x4000U)
78346#define SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT (14U)
78351#define SRC_SETPOINT_WAKEUP_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT14_MASK)
78352
78353#define SRC_SETPOINT_WAKEUP_SETPOINT15_MASK (0x8000U)
78354#define SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT (15U)
78359#define SRC_SETPOINT_WAKEUP_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT15_MASK)
78365#define SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK (0x1U)
78366#define SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT (0U)
78371#define SRC_DOMAIN_WAKEUP_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK)
78372
78373#define SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK (0x2U)
78374#define SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT (1U)
78379#define SRC_DOMAIN_WAKEUP_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK)
78380
78381#define SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK (0x4U)
78382#define SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT (2U)
78387#define SRC_DOMAIN_WAKEUP_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK)
78388
78389#define SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK (0x8U)
78390#define SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT (3U)
78395#define SRC_DOMAIN_WAKEUP_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK)
78396
78397#define SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK (0x10U)
78398#define SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT (4U)
78403#define SRC_DOMAIN_WAKEUP_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK)
78404
78405#define SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK (0x20U)
78406#define SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT (5U)
78411#define SRC_DOMAIN_WAKEUP_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK)
78412
78413#define SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK (0x40U)
78414#define SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT (6U)
78419#define SRC_DOMAIN_WAKEUP_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK)
78420
78421#define SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK (0x80U)
78422#define SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT (7U)
78427#define SRC_DOMAIN_WAKEUP_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK)
78433#define SRC_STAT_WAKEUP_UNDER_RST_MASK (0x1U)
78434#define SRC_STAT_WAKEUP_UNDER_RST_SHIFT (0U)
78439#define SRC_STAT_WAKEUP_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_UNDER_RST_SHIFT)) & SRC_STAT_WAKEUP_UNDER_RST_MASK)
78440
78441#define SRC_STAT_WAKEUP_RST_BY_HW_MASK (0x4U)
78442#define SRC_STAT_WAKEUP_RST_BY_HW_SHIFT (2U)
78447#define SRC_STAT_WAKEUP_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_HW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_HW_MASK)
78448
78449#define SRC_STAT_WAKEUP_RST_BY_SW_MASK (0x8U)
78450#define SRC_STAT_WAKEUP_RST_BY_SW_SHIFT (3U)
78455#define SRC_STAT_WAKEUP_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_SW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_SW_MASK)
78461#define SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK (0x1U)
78462#define SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT (0U)
78467#define SRC_AUTHEN_M4CORE_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK)
78468
78469#define SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK (0x2U)
78470#define SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT (1U)
78475#define SRC_AUTHEN_M4CORE_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK)
78476
78477#define SRC_AUTHEN_M4CORE_LOCK_MODE_MASK (0x80U)
78478#define SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT (7U)
78481#define SRC_AUTHEN_M4CORE_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_MODE_MASK)
78482
78483#define SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK (0xF00U)
78484#define SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT (8U)
78485#define SRC_AUTHEN_M4CORE_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK)
78486
78487#define SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK (0x8000U)
78488#define SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT (15U)
78491#define SRC_AUTHEN_M4CORE_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK)
78492
78493#define SRC_AUTHEN_M4CORE_WHITE_LIST_MASK (0xF0000U)
78494#define SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT (16U)
78497#define SRC_AUTHEN_M4CORE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_WHITE_LIST_MASK)
78498
78499#define SRC_AUTHEN_M4CORE_LOCK_LIST_MASK (0x800000U)
78500#define SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT (23U)
78503#define SRC_AUTHEN_M4CORE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_LIST_MASK)
78504
78505#define SRC_AUTHEN_M4CORE_USER_MASK (0x1000000U)
78506#define SRC_AUTHEN_M4CORE_USER_SHIFT (24U)
78509#define SRC_AUTHEN_M4CORE_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_USER_SHIFT)) & SRC_AUTHEN_M4CORE_USER_MASK)
78510
78511#define SRC_AUTHEN_M4CORE_NONSECURE_MASK (0x2000000U)
78512#define SRC_AUTHEN_M4CORE_NONSECURE_SHIFT (25U)
78515#define SRC_AUTHEN_M4CORE_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M4CORE_NONSECURE_MASK)
78516
78517#define SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK (0x80000000U)
78518#define SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT (31U)
78521#define SRC_AUTHEN_M4CORE_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK)
78527#define SRC_CTRL_M4CORE_SW_RESET_MASK (0x1U)
78528#define SRC_CTRL_M4CORE_SW_RESET_SHIFT (0U)
78533#define SRC_CTRL_M4CORE_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4CORE_SW_RESET_SHIFT)) & SRC_CTRL_M4CORE_SW_RESET_MASK)
78539#define SRC_SETPOINT_M4CORE_SETPOINT0_MASK (0x1U)
78540#define SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT (0U)
78545#define SRC_SETPOINT_M4CORE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT0_MASK)
78546
78547#define SRC_SETPOINT_M4CORE_SETPOINT1_MASK (0x2U)
78548#define SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT (1U)
78553#define SRC_SETPOINT_M4CORE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT1_MASK)
78554
78555#define SRC_SETPOINT_M4CORE_SETPOINT2_MASK (0x4U)
78556#define SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT (2U)
78561#define SRC_SETPOINT_M4CORE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT2_MASK)
78562
78563#define SRC_SETPOINT_M4CORE_SETPOINT3_MASK (0x8U)
78564#define SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT (3U)
78569#define SRC_SETPOINT_M4CORE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT3_MASK)
78570
78571#define SRC_SETPOINT_M4CORE_SETPOINT4_MASK (0x10U)
78572#define SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT (4U)
78577#define SRC_SETPOINT_M4CORE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT4_MASK)
78578
78579#define SRC_SETPOINT_M4CORE_SETPOINT5_MASK (0x20U)
78580#define SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT (5U)
78585#define SRC_SETPOINT_M4CORE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT5_MASK)
78586
78587#define SRC_SETPOINT_M4CORE_SETPOINT6_MASK (0x40U)
78588#define SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT (6U)
78593#define SRC_SETPOINT_M4CORE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT6_MASK)
78594
78595#define SRC_SETPOINT_M4CORE_SETPOINT7_MASK (0x80U)
78596#define SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT (7U)
78601#define SRC_SETPOINT_M4CORE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT7_MASK)
78602
78603#define SRC_SETPOINT_M4CORE_SETPOINT8_MASK (0x100U)
78604#define SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT (8U)
78609#define SRC_SETPOINT_M4CORE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT8_MASK)
78610
78611#define SRC_SETPOINT_M4CORE_SETPOINT9_MASK (0x200U)
78612#define SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT (9U)
78617#define SRC_SETPOINT_M4CORE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT9_MASK)
78618
78619#define SRC_SETPOINT_M4CORE_SETPOINT10_MASK (0x400U)
78620#define SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT (10U)
78625#define SRC_SETPOINT_M4CORE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT10_MASK)
78626
78627#define SRC_SETPOINT_M4CORE_SETPOINT11_MASK (0x800U)
78628#define SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT (11U)
78633#define SRC_SETPOINT_M4CORE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT11_MASK)
78634
78635#define SRC_SETPOINT_M4CORE_SETPOINT12_MASK (0x1000U)
78636#define SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT (12U)
78641#define SRC_SETPOINT_M4CORE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT12_MASK)
78642
78643#define SRC_SETPOINT_M4CORE_SETPOINT13_MASK (0x2000U)
78644#define SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT (13U)
78649#define SRC_SETPOINT_M4CORE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT13_MASK)
78650
78651#define SRC_SETPOINT_M4CORE_SETPOINT14_MASK (0x4000U)
78652#define SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT (14U)
78657#define SRC_SETPOINT_M4CORE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT14_MASK)
78658
78659#define SRC_SETPOINT_M4CORE_SETPOINT15_MASK (0x8000U)
78660#define SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT (15U)
78665#define SRC_SETPOINT_M4CORE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT15_MASK)
78671#define SRC_DOMAIN_M4CORE_CPU0_RUN_MASK (0x1U)
78672#define SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT (0U)
78677#define SRC_DOMAIN_M4CORE_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_RUN_MASK)
78678
78679#define SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK (0x2U)
78680#define SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT (1U)
78685#define SRC_DOMAIN_M4CORE_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK)
78686
78687#define SRC_DOMAIN_M4CORE_CPU0_STOP_MASK (0x4U)
78688#define SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT (2U)
78693#define SRC_DOMAIN_M4CORE_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_STOP_MASK)
78694
78695#define SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK (0x8U)
78696#define SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT (3U)
78701#define SRC_DOMAIN_M4CORE_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK)
78702
78703#define SRC_DOMAIN_M4CORE_CPU1_RUN_MASK (0x10U)
78704#define SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT (4U)
78709#define SRC_DOMAIN_M4CORE_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_RUN_MASK)
78710
78711#define SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK (0x20U)
78712#define SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT (5U)
78717#define SRC_DOMAIN_M4CORE_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK)
78718
78719#define SRC_DOMAIN_M4CORE_CPU1_STOP_MASK (0x40U)
78720#define SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT (6U)
78725#define SRC_DOMAIN_M4CORE_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_STOP_MASK)
78726
78727#define SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK (0x80U)
78728#define SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT (7U)
78733#define SRC_DOMAIN_M4CORE_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK)
78739#define SRC_STAT_M4CORE_UNDER_RST_MASK (0x1U)
78740#define SRC_STAT_M4CORE_UNDER_RST_SHIFT (0U)
78745#define SRC_STAT_M4CORE_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_UNDER_RST_SHIFT)) & SRC_STAT_M4CORE_UNDER_RST_MASK)
78746
78747#define SRC_STAT_M4CORE_RST_BY_HW_MASK (0x4U)
78748#define SRC_STAT_M4CORE_RST_BY_HW_SHIFT (2U)
78753#define SRC_STAT_M4CORE_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_HW_MASK)
78754
78755#define SRC_STAT_M4CORE_RST_BY_SW_MASK (0x8U)
78756#define SRC_STAT_M4CORE_RST_BY_SW_SHIFT (3U)
78761#define SRC_STAT_M4CORE_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_SW_MASK)
78767#define SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK (0x1U)
78768#define SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT (0U)
78773#define SRC_AUTHEN_M7CORE_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK)
78774
78775#define SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK (0x2U)
78776#define SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT (1U)
78781#define SRC_AUTHEN_M7CORE_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK)
78782
78783#define SRC_AUTHEN_M7CORE_LOCK_MODE_MASK (0x80U)
78784#define SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT (7U)
78787#define SRC_AUTHEN_M7CORE_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_MODE_MASK)
78788
78789#define SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK (0xF00U)
78790#define SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT (8U)
78791#define SRC_AUTHEN_M7CORE_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK)
78792
78793#define SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK (0x8000U)
78794#define SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT (15U)
78797#define SRC_AUTHEN_M7CORE_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK)
78798
78799#define SRC_AUTHEN_M7CORE_WHITE_LIST_MASK (0xF0000U)
78800#define SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT (16U)
78803#define SRC_AUTHEN_M7CORE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_WHITE_LIST_MASK)
78804
78805#define SRC_AUTHEN_M7CORE_LOCK_LIST_MASK (0x800000U)
78806#define SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT (23U)
78809#define SRC_AUTHEN_M7CORE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_LIST_MASK)
78810
78811#define SRC_AUTHEN_M7CORE_USER_MASK (0x1000000U)
78812#define SRC_AUTHEN_M7CORE_USER_SHIFT (24U)
78815#define SRC_AUTHEN_M7CORE_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_USER_SHIFT)) & SRC_AUTHEN_M7CORE_USER_MASK)
78816
78817#define SRC_AUTHEN_M7CORE_NONSECURE_MASK (0x2000000U)
78818#define SRC_AUTHEN_M7CORE_NONSECURE_SHIFT (25U)
78821#define SRC_AUTHEN_M7CORE_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M7CORE_NONSECURE_MASK)
78822
78823#define SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK (0x80000000U)
78824#define SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT (31U)
78827#define SRC_AUTHEN_M7CORE_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK)
78833#define SRC_CTRL_M7CORE_SW_RESET_MASK (0x1U)
78834#define SRC_CTRL_M7CORE_SW_RESET_SHIFT (0U)
78839#define SRC_CTRL_M7CORE_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7CORE_SW_RESET_SHIFT)) & SRC_CTRL_M7CORE_SW_RESET_MASK)
78845#define SRC_SETPOINT_M7CORE_SETPOINT0_MASK (0x1U)
78846#define SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT (0U)
78851#define SRC_SETPOINT_M7CORE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT0_MASK)
78852
78853#define SRC_SETPOINT_M7CORE_SETPOINT1_MASK (0x2U)
78854#define SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT (1U)
78859#define SRC_SETPOINT_M7CORE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT1_MASK)
78860
78861#define SRC_SETPOINT_M7CORE_SETPOINT2_MASK (0x4U)
78862#define SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT (2U)
78867#define SRC_SETPOINT_M7CORE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT2_MASK)
78868
78869#define SRC_SETPOINT_M7CORE_SETPOINT3_MASK (0x8U)
78870#define SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT (3U)
78875#define SRC_SETPOINT_M7CORE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT3_MASK)
78876
78877#define SRC_SETPOINT_M7CORE_SETPOINT4_MASK (0x10U)
78878#define SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT (4U)
78883#define SRC_SETPOINT_M7CORE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT4_MASK)
78884
78885#define SRC_SETPOINT_M7CORE_SETPOINT5_MASK (0x20U)
78886#define SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT (5U)
78891#define SRC_SETPOINT_M7CORE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT5_MASK)
78892
78893#define SRC_SETPOINT_M7CORE_SETPOINT6_MASK (0x40U)
78894#define SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT (6U)
78899#define SRC_SETPOINT_M7CORE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT6_MASK)
78900
78901#define SRC_SETPOINT_M7CORE_SETPOINT7_MASK (0x80U)
78902#define SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT (7U)
78907#define SRC_SETPOINT_M7CORE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT7_MASK)
78908
78909#define SRC_SETPOINT_M7CORE_SETPOINT8_MASK (0x100U)
78910#define SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT (8U)
78915#define SRC_SETPOINT_M7CORE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT8_MASK)
78916
78917#define SRC_SETPOINT_M7CORE_SETPOINT9_MASK (0x200U)
78918#define SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT (9U)
78923#define SRC_SETPOINT_M7CORE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT9_MASK)
78924
78925#define SRC_SETPOINT_M7CORE_SETPOINT10_MASK (0x400U)
78926#define SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT (10U)
78931#define SRC_SETPOINT_M7CORE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT10_MASK)
78932
78933#define SRC_SETPOINT_M7CORE_SETPOINT11_MASK (0x800U)
78934#define SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT (11U)
78939#define SRC_SETPOINT_M7CORE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT11_MASK)
78940
78941#define SRC_SETPOINT_M7CORE_SETPOINT12_MASK (0x1000U)
78942#define SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT (12U)
78947#define SRC_SETPOINT_M7CORE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT12_MASK)
78948
78949#define SRC_SETPOINT_M7CORE_SETPOINT13_MASK (0x2000U)
78950#define SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT (13U)
78955#define SRC_SETPOINT_M7CORE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT13_MASK)
78956
78957#define SRC_SETPOINT_M7CORE_SETPOINT14_MASK (0x4000U)
78958#define SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT (14U)
78963#define SRC_SETPOINT_M7CORE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT14_MASK)
78964
78965#define SRC_SETPOINT_M7CORE_SETPOINT15_MASK (0x8000U)
78966#define SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT (15U)
78971#define SRC_SETPOINT_M7CORE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT15_MASK)
78977#define SRC_DOMAIN_M7CORE_CPU0_RUN_MASK (0x1U)
78978#define SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT (0U)
78983#define SRC_DOMAIN_M7CORE_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_RUN_MASK)
78984
78985#define SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK (0x2U)
78986#define SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT (1U)
78991#define SRC_DOMAIN_M7CORE_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK)
78992
78993#define SRC_DOMAIN_M7CORE_CPU0_STOP_MASK (0x4U)
78994#define SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT (2U)
78999#define SRC_DOMAIN_M7CORE_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_STOP_MASK)
79000
79001#define SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK (0x8U)
79002#define SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT (3U)
79007#define SRC_DOMAIN_M7CORE_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK)
79008
79009#define SRC_DOMAIN_M7CORE_CPU1_RUN_MASK (0x10U)
79010#define SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT (4U)
79015#define SRC_DOMAIN_M7CORE_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_RUN_MASK)
79016
79017#define SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK (0x20U)
79018#define SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT (5U)
79023#define SRC_DOMAIN_M7CORE_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK)
79024
79025#define SRC_DOMAIN_M7CORE_CPU1_STOP_MASK (0x40U)
79026#define SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT (6U)
79031#define SRC_DOMAIN_M7CORE_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_STOP_MASK)
79032
79033#define SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK (0x80U)
79034#define SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT (7U)
79039#define SRC_DOMAIN_M7CORE_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK)
79045#define SRC_STAT_M7CORE_UNDER_RST_MASK (0x1U)
79046#define SRC_STAT_M7CORE_UNDER_RST_SHIFT (0U)
79051#define SRC_STAT_M7CORE_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_UNDER_RST_SHIFT)) & SRC_STAT_M7CORE_UNDER_RST_MASK)
79052
79053#define SRC_STAT_M7CORE_RST_BY_HW_MASK (0x4U)
79054#define SRC_STAT_M7CORE_RST_BY_HW_SHIFT (2U)
79059#define SRC_STAT_M7CORE_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_HW_MASK)
79060
79061#define SRC_STAT_M7CORE_RST_BY_SW_MASK (0x8U)
79062#define SRC_STAT_M7CORE_RST_BY_SW_SHIFT (3U)
79067#define SRC_STAT_M7CORE_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_SW_MASK)
79073#define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK (0x1U)
79074#define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT (0U)
79079#define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK)
79080
79081#define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK (0x2U)
79082#define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT (1U)
79087#define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK)
79088
79089#define SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK (0x80U)
79090#define SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT (7U)
79093#define SRC_AUTHEN_M4DEBUG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK)
79094
79095#define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK (0xF00U)
79096#define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT (8U)
79097#define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK)
79098
79099#define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK (0x8000U)
79100#define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT (15U)
79103#define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK)
79104
79105#define SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK (0xF0000U)
79106#define SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT (16U)
79109#define SRC_AUTHEN_M4DEBUG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK)
79110
79111#define SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK (0x800000U)
79112#define SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT (23U)
79115#define SRC_AUTHEN_M4DEBUG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK)
79116
79117#define SRC_AUTHEN_M4DEBUG_USER_MASK (0x1000000U)
79118#define SRC_AUTHEN_M4DEBUG_USER_SHIFT (24U)
79121#define SRC_AUTHEN_M4DEBUG_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_USER_SHIFT)) & SRC_AUTHEN_M4DEBUG_USER_MASK)
79122
79123#define SRC_AUTHEN_M4DEBUG_NONSECURE_MASK (0x2000000U)
79124#define SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT (25U)
79127#define SRC_AUTHEN_M4DEBUG_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M4DEBUG_NONSECURE_MASK)
79128
79129#define SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK (0x80000000U)
79130#define SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT (31U)
79133#define SRC_AUTHEN_M4DEBUG_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK)
79139#define SRC_CTRL_M4DEBUG_SW_RESET_MASK (0x1U)
79140#define SRC_CTRL_M4DEBUG_SW_RESET_SHIFT (0U)
79145#define SRC_CTRL_M4DEBUG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M4DEBUG_SW_RESET_MASK)
79151#define SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK (0x1U)
79152#define SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT (0U)
79157#define SRC_SETPOINT_M4DEBUG_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK)
79158
79159#define SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK (0x2U)
79160#define SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT (1U)
79165#define SRC_SETPOINT_M4DEBUG_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK)
79166
79167#define SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK (0x4U)
79168#define SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT (2U)
79173#define SRC_SETPOINT_M4DEBUG_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK)
79174
79175#define SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK (0x8U)
79176#define SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT (3U)
79181#define SRC_SETPOINT_M4DEBUG_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK)
79182
79183#define SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK (0x10U)
79184#define SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT (4U)
79189#define SRC_SETPOINT_M4DEBUG_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK)
79190
79191#define SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK (0x20U)
79192#define SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT (5U)
79197#define SRC_SETPOINT_M4DEBUG_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK)
79198
79199#define SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK (0x40U)
79200#define SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT (6U)
79205#define SRC_SETPOINT_M4DEBUG_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK)
79206
79207#define SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK (0x80U)
79208#define SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT (7U)
79213#define SRC_SETPOINT_M4DEBUG_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK)
79214
79215#define SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK (0x100U)
79216#define SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT (8U)
79221#define SRC_SETPOINT_M4DEBUG_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK)
79222
79223#define SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK (0x200U)
79224#define SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT (9U)
79229#define SRC_SETPOINT_M4DEBUG_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK)
79230
79231#define SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK (0x400U)
79232#define SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT (10U)
79237#define SRC_SETPOINT_M4DEBUG_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK)
79238
79239#define SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK (0x800U)
79240#define SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT (11U)
79245#define SRC_SETPOINT_M4DEBUG_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK)
79246
79247#define SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK (0x1000U)
79248#define SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT (12U)
79253#define SRC_SETPOINT_M4DEBUG_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK)
79254
79255#define SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK (0x2000U)
79256#define SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT (13U)
79261#define SRC_SETPOINT_M4DEBUG_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK)
79262
79263#define SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK (0x4000U)
79264#define SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT (14U)
79269#define SRC_SETPOINT_M4DEBUG_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK)
79270
79271#define SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK (0x8000U)
79272#define SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT (15U)
79277#define SRC_SETPOINT_M4DEBUG_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK)
79283#define SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK (0x1U)
79284#define SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT (0U)
79289#define SRC_DOMAIN_M4DEBUG_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK)
79290
79291#define SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK (0x2U)
79292#define SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT (1U)
79297#define SRC_DOMAIN_M4DEBUG_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK)
79298
79299#define SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK (0x4U)
79300#define SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT (2U)
79305#define SRC_DOMAIN_M4DEBUG_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK)
79306
79307#define SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK (0x8U)
79308#define SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT (3U)
79313#define SRC_DOMAIN_M4DEBUG_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK)
79314
79315#define SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK (0x10U)
79316#define SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT (4U)
79321#define SRC_DOMAIN_M4DEBUG_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK)
79322
79323#define SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK (0x20U)
79324#define SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT (5U)
79329#define SRC_DOMAIN_M4DEBUG_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK)
79330
79331#define SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK (0x40U)
79332#define SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT (6U)
79337#define SRC_DOMAIN_M4DEBUG_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK)
79338
79339#define SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK (0x80U)
79340#define SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT (7U)
79345#define SRC_DOMAIN_M4DEBUG_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK)
79351#define SRC_STAT_M4DEBUG_UNDER_RST_MASK (0x1U)
79352#define SRC_STAT_M4DEBUG_UNDER_RST_SHIFT (0U)
79357#define SRC_STAT_M4DEBUG_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M4DEBUG_UNDER_RST_MASK)
79358
79359#define SRC_STAT_M4DEBUG_RST_BY_HW_MASK (0x4U)
79360#define SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT (2U)
79365#define SRC_STAT_M4DEBUG_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_HW_MASK)
79366
79367#define SRC_STAT_M4DEBUG_RST_BY_SW_MASK (0x8U)
79368#define SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT (3U)
79373#define SRC_STAT_M4DEBUG_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_SW_MASK)
79379#define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK (0x1U)
79380#define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT (0U)
79385#define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK)
79386
79387#define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK (0x2U)
79388#define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT (1U)
79393#define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK)
79394
79395#define SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK (0x80U)
79396#define SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT (7U)
79399#define SRC_AUTHEN_M7DEBUG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK)
79400
79401#define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK (0xF00U)
79402#define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT (8U)
79403#define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK)
79404
79405#define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK (0x8000U)
79406#define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT (15U)
79409#define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK)
79410
79411#define SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK (0xF0000U)
79412#define SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT (16U)
79415#define SRC_AUTHEN_M7DEBUG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK)
79416
79417#define SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK (0x800000U)
79418#define SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT (23U)
79421#define SRC_AUTHEN_M7DEBUG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK)
79422
79423#define SRC_AUTHEN_M7DEBUG_USER_MASK (0x1000000U)
79424#define SRC_AUTHEN_M7DEBUG_USER_SHIFT (24U)
79427#define SRC_AUTHEN_M7DEBUG_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_USER_SHIFT)) & SRC_AUTHEN_M7DEBUG_USER_MASK)
79428
79429#define SRC_AUTHEN_M7DEBUG_NONSECURE_MASK (0x2000000U)
79430#define SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT (25U)
79433#define SRC_AUTHEN_M7DEBUG_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M7DEBUG_NONSECURE_MASK)
79434
79435#define SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK (0x80000000U)
79436#define SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT (31U)
79439#define SRC_AUTHEN_M7DEBUG_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK)
79445#define SRC_CTRL_M7DEBUG_SW_RESET_MASK (0x1U)
79446#define SRC_CTRL_M7DEBUG_SW_RESET_SHIFT (0U)
79451#define SRC_CTRL_M7DEBUG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M7DEBUG_SW_RESET_MASK)
79457#define SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK (0x1U)
79458#define SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT (0U)
79463#define SRC_SETPOINT_M7DEBUG_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK)
79464
79465#define SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK (0x2U)
79466#define SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT (1U)
79471#define SRC_SETPOINT_M7DEBUG_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK)
79472
79473#define SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK (0x4U)
79474#define SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT (2U)
79479#define SRC_SETPOINT_M7DEBUG_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK)
79480
79481#define SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK (0x8U)
79482#define SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT (3U)
79487#define SRC_SETPOINT_M7DEBUG_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK)
79488
79489#define SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK (0x10U)
79490#define SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT (4U)
79495#define SRC_SETPOINT_M7DEBUG_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK)
79496
79497#define SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK (0x20U)
79498#define SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT (5U)
79503#define SRC_SETPOINT_M7DEBUG_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK)
79504
79505#define SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK (0x40U)
79506#define SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT (6U)
79511#define SRC_SETPOINT_M7DEBUG_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK)
79512
79513#define SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK (0x80U)
79514#define SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT (7U)
79519#define SRC_SETPOINT_M7DEBUG_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK)
79520
79521#define SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK (0x100U)
79522#define SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT (8U)
79527#define SRC_SETPOINT_M7DEBUG_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK)
79528
79529#define SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK (0x200U)
79530#define SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT (9U)
79535#define SRC_SETPOINT_M7DEBUG_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK)
79536
79537#define SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK (0x400U)
79538#define SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT (10U)
79543#define SRC_SETPOINT_M7DEBUG_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK)
79544
79545#define SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK (0x800U)
79546#define SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT (11U)
79551#define SRC_SETPOINT_M7DEBUG_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK)
79552
79553#define SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK (0x1000U)
79554#define SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT (12U)
79559#define SRC_SETPOINT_M7DEBUG_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK)
79560
79561#define SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK (0x2000U)
79562#define SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT (13U)
79567#define SRC_SETPOINT_M7DEBUG_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK)
79568
79569#define SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK (0x4000U)
79570#define SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT (14U)
79575#define SRC_SETPOINT_M7DEBUG_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK)
79576
79577#define SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK (0x8000U)
79578#define SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT (15U)
79583#define SRC_SETPOINT_M7DEBUG_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK)
79589#define SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK (0x1U)
79590#define SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT (0U)
79595#define SRC_DOMAIN_M7DEBUG_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK)
79596
79597#define SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK (0x2U)
79598#define SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT (1U)
79603#define SRC_DOMAIN_M7DEBUG_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK)
79604
79605#define SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK (0x4U)
79606#define SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT (2U)
79611#define SRC_DOMAIN_M7DEBUG_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK)
79612
79613#define SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK (0x8U)
79614#define SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT (3U)
79619#define SRC_DOMAIN_M7DEBUG_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK)
79620
79621#define SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK (0x10U)
79622#define SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT (4U)
79627#define SRC_DOMAIN_M7DEBUG_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK)
79628
79629#define SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK (0x20U)
79630#define SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT (5U)
79635#define SRC_DOMAIN_M7DEBUG_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK)
79636
79637#define SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK (0x40U)
79638#define SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT (6U)
79643#define SRC_DOMAIN_M7DEBUG_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK)
79644
79645#define SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK (0x80U)
79646#define SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT (7U)
79651#define SRC_DOMAIN_M7DEBUG_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK)
79657#define SRC_STAT_M7DEBUG_UNDER_RST_MASK (0x1U)
79658#define SRC_STAT_M7DEBUG_UNDER_RST_SHIFT (0U)
79663#define SRC_STAT_M7DEBUG_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M7DEBUG_UNDER_RST_MASK)
79664
79665#define SRC_STAT_M7DEBUG_RST_BY_HW_MASK (0x4U)
79666#define SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT (2U)
79671#define SRC_STAT_M7DEBUG_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_HW_MASK)
79672
79673#define SRC_STAT_M7DEBUG_RST_BY_SW_MASK (0x8U)
79674#define SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT (3U)
79679#define SRC_STAT_M7DEBUG_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_SW_MASK)
79685#define SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK (0x1U)
79686#define SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT (0U)
79691#define SRC_AUTHEN_USBPHY1_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK)
79692
79693#define SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK (0x2U)
79694#define SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT (1U)
79699#define SRC_AUTHEN_USBPHY1_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK)
79700
79701#define SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK (0x80U)
79702#define SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT (7U)
79705#define SRC_AUTHEN_USBPHY1_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK)
79706
79707#define SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK (0xF00U)
79708#define SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT (8U)
79709#define SRC_AUTHEN_USBPHY1_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK)
79710
79711#define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK (0x8000U)
79712#define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT (15U)
79715#define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK)
79716
79717#define SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK (0xF0000U)
79718#define SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT (16U)
79721#define SRC_AUTHEN_USBPHY1_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK)
79722
79723#define SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK (0x800000U)
79724#define SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT (23U)
79727#define SRC_AUTHEN_USBPHY1_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK)
79728
79729#define SRC_AUTHEN_USBPHY1_USER_MASK (0x1000000U)
79730#define SRC_AUTHEN_USBPHY1_USER_SHIFT (24U)
79733#define SRC_AUTHEN_USBPHY1_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_USER_SHIFT)) & SRC_AUTHEN_USBPHY1_USER_MASK)
79734
79735#define SRC_AUTHEN_USBPHY1_NONSECURE_MASK (0x2000000U)
79736#define SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT (25U)
79739#define SRC_AUTHEN_USBPHY1_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY1_NONSECURE_MASK)
79740
79741#define SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK (0x80000000U)
79742#define SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT (31U)
79745#define SRC_AUTHEN_USBPHY1_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK)
79751#define SRC_CTRL_USBPHY1_SW_RESET_MASK (0x1U)
79752#define SRC_CTRL_USBPHY1_SW_RESET_SHIFT (0U)
79757#define SRC_CTRL_USBPHY1_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY1_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY1_SW_RESET_MASK)
79763#define SRC_SETPOINT_USBPHY1_SETPOINT0_MASK (0x1U)
79764#define SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT (0U)
79769#define SRC_SETPOINT_USBPHY1_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT0_MASK)
79770
79771#define SRC_SETPOINT_USBPHY1_SETPOINT1_MASK (0x2U)
79772#define SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT (1U)
79777#define SRC_SETPOINT_USBPHY1_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT1_MASK)
79778
79779#define SRC_SETPOINT_USBPHY1_SETPOINT2_MASK (0x4U)
79780#define SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT (2U)
79785#define SRC_SETPOINT_USBPHY1_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT2_MASK)
79786
79787#define SRC_SETPOINT_USBPHY1_SETPOINT3_MASK (0x8U)
79788#define SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT (3U)
79793#define SRC_SETPOINT_USBPHY1_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT3_MASK)
79794
79795#define SRC_SETPOINT_USBPHY1_SETPOINT4_MASK (0x10U)
79796#define SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT (4U)
79801#define SRC_SETPOINT_USBPHY1_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT4_MASK)
79802
79803#define SRC_SETPOINT_USBPHY1_SETPOINT5_MASK (0x20U)
79804#define SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT (5U)
79809#define SRC_SETPOINT_USBPHY1_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT5_MASK)
79810
79811#define SRC_SETPOINT_USBPHY1_SETPOINT6_MASK (0x40U)
79812#define SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT (6U)
79817#define SRC_SETPOINT_USBPHY1_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT6_MASK)
79818
79819#define SRC_SETPOINT_USBPHY1_SETPOINT7_MASK (0x80U)
79820#define SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT (7U)
79825#define SRC_SETPOINT_USBPHY1_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT7_MASK)
79826
79827#define SRC_SETPOINT_USBPHY1_SETPOINT8_MASK (0x100U)
79828#define SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT (8U)
79833#define SRC_SETPOINT_USBPHY1_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT8_MASK)
79834
79835#define SRC_SETPOINT_USBPHY1_SETPOINT9_MASK (0x200U)
79836#define SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT (9U)
79841#define SRC_SETPOINT_USBPHY1_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT9_MASK)
79842
79843#define SRC_SETPOINT_USBPHY1_SETPOINT10_MASK (0x400U)
79844#define SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT (10U)
79849#define SRC_SETPOINT_USBPHY1_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT10_MASK)
79850
79851#define SRC_SETPOINT_USBPHY1_SETPOINT11_MASK (0x800U)
79852#define SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT (11U)
79857#define SRC_SETPOINT_USBPHY1_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT11_MASK)
79858
79859#define SRC_SETPOINT_USBPHY1_SETPOINT12_MASK (0x1000U)
79860#define SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT (12U)
79865#define SRC_SETPOINT_USBPHY1_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT12_MASK)
79866
79867#define SRC_SETPOINT_USBPHY1_SETPOINT13_MASK (0x2000U)
79868#define SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT (13U)
79873#define SRC_SETPOINT_USBPHY1_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT13_MASK)
79874
79875#define SRC_SETPOINT_USBPHY1_SETPOINT14_MASK (0x4000U)
79876#define SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT (14U)
79881#define SRC_SETPOINT_USBPHY1_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT14_MASK)
79882
79883#define SRC_SETPOINT_USBPHY1_SETPOINT15_MASK (0x8000U)
79884#define SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT (15U)
79889#define SRC_SETPOINT_USBPHY1_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT15_MASK)
79895#define SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK (0x1U)
79896#define SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT (0U)
79901#define SRC_DOMAIN_USBPHY1_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK)
79902
79903#define SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK (0x2U)
79904#define SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT (1U)
79909#define SRC_DOMAIN_USBPHY1_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK)
79910
79911#define SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK (0x4U)
79912#define SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT (2U)
79917#define SRC_DOMAIN_USBPHY1_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK)
79918
79919#define SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK (0x8U)
79920#define SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT (3U)
79925#define SRC_DOMAIN_USBPHY1_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK)
79926
79927#define SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK (0x10U)
79928#define SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT (4U)
79933#define SRC_DOMAIN_USBPHY1_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK)
79934
79935#define SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK (0x20U)
79936#define SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT (5U)
79941#define SRC_DOMAIN_USBPHY1_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK)
79942
79943#define SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK (0x40U)
79944#define SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT (6U)
79949#define SRC_DOMAIN_USBPHY1_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK)
79950
79951#define SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK (0x80U)
79952#define SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT (7U)
79957#define SRC_DOMAIN_USBPHY1_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK)
79963#define SRC_STAT_USBPHY1_UNDER_RST_MASK (0x1U)
79964#define SRC_STAT_USBPHY1_UNDER_RST_SHIFT (0U)
79969#define SRC_STAT_USBPHY1_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY1_UNDER_RST_MASK)
79970
79971#define SRC_STAT_USBPHY1_RST_BY_HW_MASK (0x4U)
79972#define SRC_STAT_USBPHY1_RST_BY_HW_SHIFT (2U)
79977#define SRC_STAT_USBPHY1_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_HW_MASK)
79978
79979#define SRC_STAT_USBPHY1_RST_BY_SW_MASK (0x8U)
79980#define SRC_STAT_USBPHY1_RST_BY_SW_SHIFT (3U)
79985#define SRC_STAT_USBPHY1_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_SW_MASK)
79991#define SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK (0x1U)
79992#define SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT (0U)
79997#define SRC_AUTHEN_USBPHY2_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK)
79998
79999#define SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK (0x2U)
80000#define SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT (1U)
80005#define SRC_AUTHEN_USBPHY2_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK)
80006
80007#define SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK (0x80U)
80008#define SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT (7U)
80011#define SRC_AUTHEN_USBPHY2_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK)
80012
80013#define SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK (0xF00U)
80014#define SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT (8U)
80015#define SRC_AUTHEN_USBPHY2_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK)
80016
80017#define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK (0x8000U)
80018#define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT (15U)
80021#define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK)
80022
80023#define SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK (0xF0000U)
80024#define SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT (16U)
80027#define SRC_AUTHEN_USBPHY2_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK)
80028
80029#define SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK (0x800000U)
80030#define SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT (23U)
80033#define SRC_AUTHEN_USBPHY2_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK)
80034
80035#define SRC_AUTHEN_USBPHY2_USER_MASK (0x1000000U)
80036#define SRC_AUTHEN_USBPHY2_USER_SHIFT (24U)
80039#define SRC_AUTHEN_USBPHY2_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_USER_SHIFT)) & SRC_AUTHEN_USBPHY2_USER_MASK)
80040
80041#define SRC_AUTHEN_USBPHY2_NONSECURE_MASK (0x2000000U)
80042#define SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT (25U)
80045#define SRC_AUTHEN_USBPHY2_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY2_NONSECURE_MASK)
80046
80047#define SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK (0x80000000U)
80048#define SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT (31U)
80051#define SRC_AUTHEN_USBPHY2_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK)
80057#define SRC_CTRL_USBPHY2_SW_RESET_MASK (0x1U)
80058#define SRC_CTRL_USBPHY2_SW_RESET_SHIFT (0U)
80063#define SRC_CTRL_USBPHY2_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY2_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY2_SW_RESET_MASK)
80069#define SRC_SETPOINT_USBPHY2_SETPOINT0_MASK (0x1U)
80070#define SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT (0U)
80075#define SRC_SETPOINT_USBPHY2_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT0_MASK)
80076
80077#define SRC_SETPOINT_USBPHY2_SETPOINT1_MASK (0x2U)
80078#define SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT (1U)
80083#define SRC_SETPOINT_USBPHY2_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT1_MASK)
80084
80085#define SRC_SETPOINT_USBPHY2_SETPOINT2_MASK (0x4U)
80086#define SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT (2U)
80091#define SRC_SETPOINT_USBPHY2_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT2_MASK)
80092
80093#define SRC_SETPOINT_USBPHY2_SETPOINT3_MASK (0x8U)
80094#define SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT (3U)
80099#define SRC_SETPOINT_USBPHY2_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT3_MASK)
80100
80101#define SRC_SETPOINT_USBPHY2_SETPOINT4_MASK (0x10U)
80102#define SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT (4U)
80107#define SRC_SETPOINT_USBPHY2_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT4_MASK)
80108
80109#define SRC_SETPOINT_USBPHY2_SETPOINT5_MASK (0x20U)
80110#define SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT (5U)
80115#define SRC_SETPOINT_USBPHY2_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT5_MASK)
80116
80117#define SRC_SETPOINT_USBPHY2_SETPOINT6_MASK (0x40U)
80118#define SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT (6U)
80123#define SRC_SETPOINT_USBPHY2_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT6_MASK)
80124
80125#define SRC_SETPOINT_USBPHY2_SETPOINT7_MASK (0x80U)
80126#define SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT (7U)
80131#define SRC_SETPOINT_USBPHY2_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT7_MASK)
80132
80133#define SRC_SETPOINT_USBPHY2_SETPOINT8_MASK (0x100U)
80134#define SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT (8U)
80139#define SRC_SETPOINT_USBPHY2_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT8_MASK)
80140
80141#define SRC_SETPOINT_USBPHY2_SETPOINT9_MASK (0x200U)
80142#define SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT (9U)
80147#define SRC_SETPOINT_USBPHY2_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT9_MASK)
80148
80149#define SRC_SETPOINT_USBPHY2_SETPOINT10_MASK (0x400U)
80150#define SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT (10U)
80155#define SRC_SETPOINT_USBPHY2_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT10_MASK)
80156
80157#define SRC_SETPOINT_USBPHY2_SETPOINT11_MASK (0x800U)
80158#define SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT (11U)
80163#define SRC_SETPOINT_USBPHY2_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT11_MASK)
80164
80165#define SRC_SETPOINT_USBPHY2_SETPOINT12_MASK (0x1000U)
80166#define SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT (12U)
80171#define SRC_SETPOINT_USBPHY2_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT12_MASK)
80172
80173#define SRC_SETPOINT_USBPHY2_SETPOINT13_MASK (0x2000U)
80174#define SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT (13U)
80179#define SRC_SETPOINT_USBPHY2_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT13_MASK)
80180
80181#define SRC_SETPOINT_USBPHY2_SETPOINT14_MASK (0x4000U)
80182#define SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT (14U)
80187#define SRC_SETPOINT_USBPHY2_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT14_MASK)
80188
80189#define SRC_SETPOINT_USBPHY2_SETPOINT15_MASK (0x8000U)
80190#define SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT (15U)
80195#define SRC_SETPOINT_USBPHY2_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT15_MASK)
80201#define SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK (0x1U)
80202#define SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT (0U)
80207#define SRC_DOMAIN_USBPHY2_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK)
80208
80209#define SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK (0x2U)
80210#define SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT (1U)
80215#define SRC_DOMAIN_USBPHY2_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK)
80216
80217#define SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK (0x4U)
80218#define SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT (2U)
80223#define SRC_DOMAIN_USBPHY2_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK)
80224
80225#define SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK (0x8U)
80226#define SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT (3U)
80231#define SRC_DOMAIN_USBPHY2_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK)
80232
80233#define SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK (0x10U)
80234#define SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT (4U)
80239#define SRC_DOMAIN_USBPHY2_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK)
80240
80241#define SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK (0x20U)
80242#define SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT (5U)
80247#define SRC_DOMAIN_USBPHY2_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK)
80248
80249#define SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK (0x40U)
80250#define SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT (6U)
80255#define SRC_DOMAIN_USBPHY2_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK)
80256
80257#define SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK (0x80U)
80258#define SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT (7U)
80263#define SRC_DOMAIN_USBPHY2_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK)
80269#define SRC_STAT_USBPHY2_UNDER_RST_MASK (0x1U)
80270#define SRC_STAT_USBPHY2_UNDER_RST_SHIFT (0U)
80275#define SRC_STAT_USBPHY2_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY2_UNDER_RST_MASK)
80276
80277#define SRC_STAT_USBPHY2_RST_BY_HW_MASK (0x4U)
80278#define SRC_STAT_USBPHY2_RST_BY_HW_SHIFT (2U)
80283#define SRC_STAT_USBPHY2_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_HW_MASK)
80284
80285#define SRC_STAT_USBPHY2_RST_BY_SW_MASK (0x8U)
80286#define SRC_STAT_USBPHY2_RST_BY_SW_SHIFT (3U)
80291#define SRC_STAT_USBPHY2_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_SW_MASK) /* end of group SRC_Register_Masks */
80298
80299
80300/* SRC - Peripheral instance base addresses */
80302#define SRC_BASE (0x40C04000u)
80304#define SRC ((SRC_Type *)SRC_BASE)
80306#define SRC_BASE_ADDRS { SRC_BASE }
80308#define SRC_BASE_PTRS { SRC }
80309 /* end of group SRC_Peripheral_Access_Layer */
80313
80314
80315/* ----------------------------------------------------------------------------
80316 -- SSARC_HP Peripheral Access Layer
80317 ---------------------------------------------------------------------------- */
80318
80325typedef struct {
80326 struct { /* offset: 0x0, array step: 0x10 */
80327 __IO uint32_t SRAM0;
80328 __IO uint32_t SRAM1;
80329 __IO uint32_t SRAM2;
80330 uint8_t RESERVED_0[4];
80331 } DESC[1024];
80333
80334/* ----------------------------------------------------------------------------
80335 -- SSARC_HP Register Masks
80336 ---------------------------------------------------------------------------- */
80337
80346#define SSARC_HP_SRAM0_ADDR_MASK (0xFFFFFFFFU)
80347#define SSARC_HP_SRAM0_ADDR_SHIFT (0U)
80350#define SSARC_HP_SRAM0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM0_ADDR_SHIFT)) & SSARC_HP_SRAM0_ADDR_MASK)
80353/* The count of SSARC_HP_SRAM0 */
80354#define SSARC_HP_SRAM0_COUNT (1024U)
80355
80359#define SSARC_HP_SRAM1_DATA_MASK (0xFFFFFFFFU)
80360#define SSARC_HP_SRAM1_DATA_SHIFT (0U)
80363#define SSARC_HP_SRAM1_DATA(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM1_DATA_SHIFT)) & SSARC_HP_SRAM1_DATA_MASK)
80366/* The count of SSARC_HP_SRAM1 */
80367#define SSARC_HP_SRAM1_COUNT (1024U)
80368
80372#define SSARC_HP_SRAM2_TYPE_MASK (0x7U)
80373#define SSARC_HP_SRAM2_TYPE_SHIFT (0U)
80384#define SSARC_HP_SRAM2_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_TYPE_SHIFT)) & SSARC_HP_SRAM2_TYPE_MASK)
80385
80386#define SSARC_HP_SRAM2_SV_EN_MASK (0x10U)
80387#define SSARC_HP_SRAM2_SV_EN_SHIFT (4U)
80392#define SSARC_HP_SRAM2_SV_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SV_EN_SHIFT)) & SSARC_HP_SRAM2_SV_EN_MASK)
80393
80394#define SSARC_HP_SRAM2_RT_EN_MASK (0x20U)
80395#define SSARC_HP_SRAM2_RT_EN_SHIFT (5U)
80400#define SSARC_HP_SRAM2_RT_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_RT_EN_SHIFT)) & SSARC_HP_SRAM2_RT_EN_MASK)
80401
80402#define SSARC_HP_SRAM2_SIZE_MASK (0xC0U)
80403#define SSARC_HP_SRAM2_SIZE_SHIFT (6U)
80410#define SSARC_HP_SRAM2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SIZE_SHIFT)) & SSARC_HP_SRAM2_SIZE_MASK)
80413/* The count of SSARC_HP_SRAM2 */
80414#define SSARC_HP_SRAM2_COUNT (1024U)
80415
80416 /* end of group SSARC_HP_Register_Masks */
80420
80421
80422/* SSARC_HP - Peripheral instance base addresses */
80424#define SSARC_HP_BASE (0x40CB4000u)
80426#define SSARC_HP ((SSARC_HP_Type *)SSARC_HP_BASE)
80428#define SSARC_HP_BASE_ADDRS { SSARC_HP_BASE }
80430#define SSARC_HP_BASE_PTRS { SSARC_HP }
80431 /* end of group SSARC_HP_Peripheral_Access_Layer */
80435
80436
80437/* ----------------------------------------------------------------------------
80438 -- SSARC_LP Peripheral Access Layer
80439 ---------------------------------------------------------------------------- */
80440
80447typedef struct {
80448 struct { /* offset: 0x0, array step: 0x20 */
80449 __IO uint32_t DESC_CTRL0;
80450 __IO uint32_t DESC_CTRL1;
80453 uint8_t RESERVED_0[16];
80454 } GROUPS[16];
80455 __IO uint32_t CTRL;
80456 __IO uint32_t INT_STATUS;
80457 uint8_t RESERVED_0[4];
80458 __IO uint32_t HP_TIMEOUT;
80459 uint8_t RESERVED_1[12];
80460 __I uint32_t HW_GROUP_PENDING;
80461 __I uint32_t SW_GROUP_PENDING;
80463
80464/* ----------------------------------------------------------------------------
80465 -- SSARC_LP Register Masks
80466 ---------------------------------------------------------------------------- */
80467
80476#define SSARC_LP_DESC_CTRL0_START_MASK (0x3FFU)
80477#define SSARC_LP_DESC_CTRL0_START_SHIFT (0U)
80480#define SSARC_LP_DESC_CTRL0_START(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_START_SHIFT)) & SSARC_LP_DESC_CTRL0_START_MASK)
80481
80482#define SSARC_LP_DESC_CTRL0_END_MASK (0xFFC00U)
80483#define SSARC_LP_DESC_CTRL0_END_SHIFT (10U)
80486#define SSARC_LP_DESC_CTRL0_END(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_END_SHIFT)) & SSARC_LP_DESC_CTRL0_END_MASK)
80487
80488#define SSARC_LP_DESC_CTRL0_SV_ORDER_MASK (0x100000U)
80489#define SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT (20U)
80494#define SSARC_LP_DESC_CTRL0_SV_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_SV_ORDER_MASK)
80495
80496#define SSARC_LP_DESC_CTRL0_RT_ORDER_MASK (0x200000U)
80497#define SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT (21U)
80502#define SSARC_LP_DESC_CTRL0_RT_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_RT_ORDER_MASK)
80505/* The count of SSARC_LP_DESC_CTRL0 */
80506#define SSARC_LP_DESC_CTRL0_COUNT (16U)
80507
80511#define SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK (0x1U)
80512#define SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT (0U)
80517#define SSARC_LP_DESC_CTRL1_SW_TRIG_SV(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK)
80518
80519#define SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK (0x2U)
80520#define SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT (1U)
80525#define SSARC_LP_DESC_CTRL1_SW_TRIG_RT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK)
80526
80527#define SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK (0x70U)
80528#define SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT (4U)
80539#define SSARC_LP_DESC_CTRL1_POWER_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT)) & SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK)
80540
80541#define SSARC_LP_DESC_CTRL1_GP_EN_MASK (0x80U)
80542#define SSARC_LP_DESC_CTRL1_GP_EN_SHIFT (7U)
80547#define SSARC_LP_DESC_CTRL1_GP_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_GP_EN_SHIFT)) & SSARC_LP_DESC_CTRL1_GP_EN_MASK)
80548
80549#define SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK (0xF00U)
80550#define SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT (8U)
80553#define SSARC_LP_DESC_CTRL1_SV_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK)
80554
80555#define SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK (0xF000U)
80556#define SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT (12U)
80559#define SSARC_LP_DESC_CTRL1_RT_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK)
80560
80561#define SSARC_LP_DESC_CTRL1_CPUD_MASK (0x30000U)
80562#define SSARC_LP_DESC_CTRL1_CPUD_SHIFT (16U)
80565#define SSARC_LP_DESC_CTRL1_CPUD(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_CPUD_SHIFT)) & SSARC_LP_DESC_CTRL1_CPUD_MASK)
80566
80567#define SSARC_LP_DESC_CTRL1_RL_MASK (0x40000U)
80568#define SSARC_LP_DESC_CTRL1_RL_SHIFT (18U)
80573#define SSARC_LP_DESC_CTRL1_RL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RL_SHIFT)) & SSARC_LP_DESC_CTRL1_RL_MASK)
80574
80575#define SSARC_LP_DESC_CTRL1_WL_MASK (0x80000U)
80576#define SSARC_LP_DESC_CTRL1_WL_SHIFT (19U)
80581#define SSARC_LP_DESC_CTRL1_WL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_WL_SHIFT)) & SSARC_LP_DESC_CTRL1_WL_MASK)
80582
80583#define SSARC_LP_DESC_CTRL1_DL_MASK (0x100000U)
80584#define SSARC_LP_DESC_CTRL1_DL_SHIFT (20U)
80589#define SSARC_LP_DESC_CTRL1_DL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_DL_SHIFT)) & SSARC_LP_DESC_CTRL1_DL_MASK)
80592/* The count of SSARC_LP_DESC_CTRL1 */
80593#define SSARC_LP_DESC_CTRL1_COUNT (16U)
80594
80598#define SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK (0xFFFFFFFFU)
80599#define SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT (0U)
80602#define SSARC_LP_DESC_ADDR_UP_ADDR_UP(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT)) & SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK)
80605/* The count of SSARC_LP_DESC_ADDR_UP */
80606#define SSARC_LP_DESC_ADDR_UP_COUNT (16U)
80607
80611#define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK (0xFFFFFFFFU)
80612#define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT (0U)
80615#define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT)) & SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK)
80618/* The count of SSARC_LP_DESC_ADDR_DOWN */
80619#define SSARC_LP_DESC_ADDR_DOWN_COUNT (16U)
80620
80624#define SSARC_LP_CTRL_DIS_HW_REQ_MASK (0x8000000U)
80625#define SSARC_LP_CTRL_DIS_HW_REQ_SHIFT (27U)
80630#define SSARC_LP_CTRL_DIS_HW_REQ(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK)
80631
80632#define SSARC_LP_CTRL_SW_RESET_MASK (0x80000000U)
80633#define SSARC_LP_CTRL_SW_RESET_SHIFT (31U)
80636#define SSARC_LP_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK)
80642#define SSARC_LP_INT_STATUS_ERR_INDEX_MASK (0x3FFU)
80643#define SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT (0U)
80646#define SSARC_LP_INT_STATUS_ERR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT)) & SSARC_LP_INT_STATUS_ERR_INDEX_MASK)
80647
80648#define SSARC_LP_INT_STATUS_AHB_RESP_MASK (0xC00U)
80649#define SSARC_LP_INT_STATUS_AHB_RESP_SHIFT (10U)
80652#define SSARC_LP_INT_STATUS_AHB_RESP(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_RESP_SHIFT)) & SSARC_LP_INT_STATUS_AHB_RESP_MASK)
80653
80654#define SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK (0x8000000U)
80655#define SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT (27U)
80660#define SSARC_LP_INT_STATUS_GROUP_CONFLICT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT)) & SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK)
80661
80662#define SSARC_LP_INT_STATUS_TIMEOUT_MASK (0x10000000U)
80663#define SSARC_LP_INT_STATUS_TIMEOUT_SHIFT (28U)
80668#define SSARC_LP_INT_STATUS_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_TIMEOUT_SHIFT)) & SSARC_LP_INT_STATUS_TIMEOUT_MASK)
80669
80670#define SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK (0x20000000U)
80671#define SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT (29U)
80676#define SSARC_LP_INT_STATUS_SW_REQ_DONE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT)) & SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK)
80677
80678#define SSARC_LP_INT_STATUS_AHB_ERR_MASK (0x40000000U)
80679#define SSARC_LP_INT_STATUS_AHB_ERR_SHIFT (30U)
80684#define SSARC_LP_INT_STATUS_AHB_ERR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_ERR_SHIFT)) & SSARC_LP_INT_STATUS_AHB_ERR_MASK)
80685
80686#define SSARC_LP_INT_STATUS_ADDR_ERR_MASK (0x80000000U)
80687#define SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT (31U)
80692#define SSARC_LP_INT_STATUS_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT)) & SSARC_LP_INT_STATUS_ADDR_ERR_MASK)
80698#define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK (0xFFFFFFFFU)
80699#define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT (0U)
80702#define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT)) & SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK)
80708#define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK (0xFFFFU)
80709#define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT (0U)
80712#define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK)
80713
80714#define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK (0xFFFF0000U)
80715#define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT (16U)
80718#define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK)
80724#define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK (0xFFFFU)
80725#define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT (0U)
80728#define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK)
80729
80730#define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK (0xFFFF0000U)
80731#define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT (16U)
80734#define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK) /* end of group SSARC_LP_Register_Masks */
80741
80742
80743/* SSARC_LP - Peripheral instance base addresses */
80745#define SSARC_LP_BASE (0x40CB8000u)
80747#define SSARC_LP ((SSARC_LP_Type *)SSARC_LP_BASE)
80749#define SSARC_LP_BASE_ADDRS { SSARC_LP_BASE }
80751#define SSARC_LP_BASE_PTRS { SSARC_LP }
80752 /* end of group SSARC_LP_Peripheral_Access_Layer */
80756
80757
80758/* ----------------------------------------------------------------------------
80759 -- TMPSNS Peripheral Access Layer
80760 ---------------------------------------------------------------------------- */
80761
80768typedef struct {
80769 __IO uint32_t CTRL0;
80770 __IO uint32_t CTRL0_SET;
80771 __IO uint32_t CTRL0_CLR;
80772 __IO uint32_t CTRL0_TOG;
80773 __IO uint32_t CTRL1;
80774 __IO uint32_t CTRL1_SET;
80775 __IO uint32_t CTRL1_CLR;
80776 __IO uint32_t CTRL1_TOG;
80777 __IO uint32_t RANGE0;
80778 __IO uint32_t RANGE0_SET;
80779 __IO uint32_t RANGE0_CLR;
80780 __IO uint32_t RANGE0_TOG;
80781 __IO uint32_t RANGE1;
80782 __IO uint32_t RANGE1_SET;
80783 __IO uint32_t RANGE1_CLR;
80784 __IO uint32_t RANGE1_TOG;
80785 uint8_t RESERVED_0[16];
80786 __IO uint32_t STATUS0;
80787} TMPSNS_Type;
80788
80789/* ----------------------------------------------------------------------------
80790 -- TMPSNS Register Masks
80791 ---------------------------------------------------------------------------- */
80792
80801#define TMPSNS_CTRL0_SLOPE_CAL_MASK (0x3FU)
80802#define TMPSNS_CTRL0_SLOPE_CAL_SHIFT (0U)
80805#define TMPSNS_CTRL0_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SLOPE_CAL_MASK)
80806
80807#define TMPSNS_CTRL0_V_SEL_MASK (0x300U)
80808#define TMPSNS_CTRL0_V_SEL_SHIFT (8U)
80813#define TMPSNS_CTRL0_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_V_SEL_SHIFT)) & TMPSNS_CTRL0_V_SEL_MASK)
80814
80815#define TMPSNS_CTRL0_IBIAS_TRIM_MASK (0xF000U)
80816#define TMPSNS_CTRL0_IBIAS_TRIM_SHIFT (12U)
80819#define TMPSNS_CTRL0_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_IBIAS_TRIM_MASK)
80825#define TMPSNS_CTRL0_SET_SLOPE_CAL_MASK (0x3FU)
80826#define TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT (0U)
80829#define TMPSNS_CTRL0_SET_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SET_SLOPE_CAL_MASK)
80830
80831#define TMPSNS_CTRL0_SET_V_SEL_MASK (0x300U)
80832#define TMPSNS_CTRL0_SET_V_SEL_SHIFT (8U)
80835#define TMPSNS_CTRL0_SET_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_V_SEL_SHIFT)) & TMPSNS_CTRL0_SET_V_SEL_MASK)
80836
80837#define TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK (0xF000U)
80838#define TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT (12U)
80841#define TMPSNS_CTRL0_SET_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK)
80847#define TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK (0x3FU)
80848#define TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT (0U)
80851#define TMPSNS_CTRL0_CLR_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK)
80852
80853#define TMPSNS_CTRL0_CLR_V_SEL_MASK (0x300U)
80854#define TMPSNS_CTRL0_CLR_V_SEL_SHIFT (8U)
80857#define TMPSNS_CTRL0_CLR_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_V_SEL_SHIFT)) & TMPSNS_CTRL0_CLR_V_SEL_MASK)
80858
80859#define TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK (0xF000U)
80860#define TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT (12U)
80863#define TMPSNS_CTRL0_CLR_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK)
80869#define TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK (0x3FU)
80870#define TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT (0U)
80873#define TMPSNS_CTRL0_TOG_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK)
80874
80875#define TMPSNS_CTRL0_TOG_V_SEL_MASK (0x300U)
80876#define TMPSNS_CTRL0_TOG_V_SEL_SHIFT (8U)
80879#define TMPSNS_CTRL0_TOG_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_V_SEL_SHIFT)) & TMPSNS_CTRL0_TOG_V_SEL_MASK)
80880
80881#define TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK (0xF000U)
80882#define TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT (12U)
80885#define TMPSNS_CTRL0_TOG_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK)
80891#define TMPSNS_CTRL1_FREQ_MASK (0xFFFFU)
80892#define TMPSNS_CTRL1_FREQ_SHIFT (0U)
80897#define TMPSNS_CTRL1_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FREQ_SHIFT)) & TMPSNS_CTRL1_FREQ_MASK)
80898
80899#define TMPSNS_CTRL1_FINISH_IE_MASK (0x10000U)
80900#define TMPSNS_CTRL1_FINISH_IE_SHIFT (16U)
80905#define TMPSNS_CTRL1_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_FINISH_IE_MASK)
80906
80907#define TMPSNS_CTRL1_LOW_TEMP_IE_MASK (0x20000U)
80908#define TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT (17U)
80913#define TMPSNS_CTRL1_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_LOW_TEMP_IE_MASK)
80914
80915#define TMPSNS_CTRL1_HIGH_TEMP_IE_MASK (0x40000U)
80916#define TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT (18U)
80921#define TMPSNS_CTRL1_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_HIGH_TEMP_IE_MASK)
80922
80923#define TMPSNS_CTRL1_PANIC_TEMP_IE_MASK (0x80000U)
80924#define TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT (19U)
80929#define TMPSNS_CTRL1_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_PANIC_TEMP_IE_MASK)
80930
80931#define TMPSNS_CTRL1_START_MASK (0x400000U)
80932#define TMPSNS_CTRL1_START_SHIFT (22U)
80937#define TMPSNS_CTRL1_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK)
80938
80939#define TMPSNS_CTRL1_PWD_MASK (0x800000U)
80940#define TMPSNS_CTRL1_PWD_SHIFT (23U)
80945#define TMPSNS_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_SHIFT)) & TMPSNS_CTRL1_PWD_MASK)
80946
80947#define TMPSNS_CTRL1_RFU_MASK (0x7F000000U)
80948#define TMPSNS_CTRL1_RFU_SHIFT (24U)
80951#define TMPSNS_CTRL1_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_RFU_SHIFT)) & TMPSNS_CTRL1_RFU_MASK)
80952
80953#define TMPSNS_CTRL1_PWD_FULL_MASK (0x80000000U)
80954#define TMPSNS_CTRL1_PWD_FULL_SHIFT (31U)
80959#define TMPSNS_CTRL1_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_PWD_FULL_MASK)
80965#define TMPSNS_CTRL1_SET_FREQ_MASK (0xFFFFU)
80966#define TMPSNS_CTRL1_SET_FREQ_SHIFT (0U)
80969#define TMPSNS_CTRL1_SET_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FREQ_SHIFT)) & TMPSNS_CTRL1_SET_FREQ_MASK)
80970
80971#define TMPSNS_CTRL1_SET_FINISH_IE_MASK (0x10000U)
80972#define TMPSNS_CTRL1_SET_FINISH_IE_SHIFT (16U)
80975#define TMPSNS_CTRL1_SET_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_SET_FINISH_IE_MASK)
80976
80977#define TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK (0x20000U)
80978#define TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT (17U)
80981#define TMPSNS_CTRL1_SET_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK)
80982
80983#define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK (0x40000U)
80984#define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT (18U)
80987#define TMPSNS_CTRL1_SET_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK)
80988
80989#define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK (0x80000U)
80990#define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT (19U)
80993#define TMPSNS_CTRL1_SET_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK)
80994
80995#define TMPSNS_CTRL1_SET_START_MASK (0x400000U)
80996#define TMPSNS_CTRL1_SET_START_SHIFT (22U)
80999#define TMPSNS_CTRL1_SET_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK)
81000
81001#define TMPSNS_CTRL1_SET_PWD_MASK (0x800000U)
81002#define TMPSNS_CTRL1_SET_PWD_SHIFT (23U)
81005#define TMPSNS_CTRL1_SET_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_SHIFT)) & TMPSNS_CTRL1_SET_PWD_MASK)
81006
81007#define TMPSNS_CTRL1_SET_RFU_MASK (0x7F000000U)
81008#define TMPSNS_CTRL1_SET_RFU_SHIFT (24U)
81011#define TMPSNS_CTRL1_SET_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_RFU_SHIFT)) & TMPSNS_CTRL1_SET_RFU_MASK)
81012
81013#define TMPSNS_CTRL1_SET_PWD_FULL_MASK (0x80000000U)
81014#define TMPSNS_CTRL1_SET_PWD_FULL_SHIFT (31U)
81017#define TMPSNS_CTRL1_SET_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_SET_PWD_FULL_MASK)
81023#define TMPSNS_CTRL1_CLR_FREQ_MASK (0xFFFFU)
81024#define TMPSNS_CTRL1_CLR_FREQ_SHIFT (0U)
81027#define TMPSNS_CTRL1_CLR_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FREQ_SHIFT)) & TMPSNS_CTRL1_CLR_FREQ_MASK)
81028
81029#define TMPSNS_CTRL1_CLR_FINISH_IE_MASK (0x10000U)
81030#define TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT (16U)
81033#define TMPSNS_CTRL1_CLR_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_CLR_FINISH_IE_MASK)
81034
81035#define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK (0x20000U)
81036#define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT (17U)
81039#define TMPSNS_CTRL1_CLR_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK)
81040
81041#define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK (0x40000U)
81042#define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT (18U)
81045#define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK)
81046
81047#define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK (0x80000U)
81048#define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT (19U)
81051#define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK)
81052
81053#define TMPSNS_CTRL1_CLR_START_MASK (0x400000U)
81054#define TMPSNS_CTRL1_CLR_START_SHIFT (22U)
81057#define TMPSNS_CTRL1_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK)
81058
81059#define TMPSNS_CTRL1_CLR_PWD_MASK (0x800000U)
81060#define TMPSNS_CTRL1_CLR_PWD_SHIFT (23U)
81063#define TMPSNS_CTRL1_CLR_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_MASK)
81064
81065#define TMPSNS_CTRL1_CLR_RFU_MASK (0x7F000000U)
81066#define TMPSNS_CTRL1_CLR_RFU_SHIFT (24U)
81069#define TMPSNS_CTRL1_CLR_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_RFU_SHIFT)) & TMPSNS_CTRL1_CLR_RFU_MASK)
81070
81071#define TMPSNS_CTRL1_CLR_PWD_FULL_MASK (0x80000000U)
81072#define TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT (31U)
81075#define TMPSNS_CTRL1_CLR_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_FULL_MASK)
81081#define TMPSNS_CTRL1_TOG_FREQ_MASK (0xFFFFU)
81082#define TMPSNS_CTRL1_TOG_FREQ_SHIFT (0U)
81085#define TMPSNS_CTRL1_TOG_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FREQ_SHIFT)) & TMPSNS_CTRL1_TOG_FREQ_MASK)
81086
81087#define TMPSNS_CTRL1_TOG_FINISH_IE_MASK (0x10000U)
81088#define TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT (16U)
81091#define TMPSNS_CTRL1_TOG_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_TOG_FINISH_IE_MASK)
81092
81093#define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK (0x20000U)
81094#define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT (17U)
81097#define TMPSNS_CTRL1_TOG_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK)
81098
81099#define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK (0x40000U)
81100#define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT (18U)
81103#define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK)
81104
81105#define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK (0x80000U)
81106#define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT (19U)
81109#define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK)
81110
81111#define TMPSNS_CTRL1_TOG_START_MASK (0x400000U)
81112#define TMPSNS_CTRL1_TOG_START_SHIFT (22U)
81115#define TMPSNS_CTRL1_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK)
81116
81117#define TMPSNS_CTRL1_TOG_PWD_MASK (0x800000U)
81118#define TMPSNS_CTRL1_TOG_PWD_SHIFT (23U)
81121#define TMPSNS_CTRL1_TOG_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_MASK)
81122
81123#define TMPSNS_CTRL1_TOG_RFU_MASK (0x7F000000U)
81124#define TMPSNS_CTRL1_TOG_RFU_SHIFT (24U)
81127#define TMPSNS_CTRL1_TOG_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_RFU_SHIFT)) & TMPSNS_CTRL1_TOG_RFU_MASK)
81128
81129#define TMPSNS_CTRL1_TOG_PWD_FULL_MASK (0x80000000U)
81130#define TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT (31U)
81133#define TMPSNS_CTRL1_TOG_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_FULL_MASK)
81139#define TMPSNS_RANGE0_LOW_TEMP_VAL_MASK (0xFFFU)
81140#define TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT (0U)
81143#define TMPSNS_RANGE0_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_LOW_TEMP_VAL_MASK)
81144
81145#define TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK (0xFFF0000U)
81146#define TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT (16U)
81149#define TMPSNS_RANGE0_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK)
81155#define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK (0xFFFU)
81156#define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT (0U)
81159#define TMPSNS_RANGE0_SET_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK)
81160
81161#define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK (0xFFF0000U)
81162#define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT (16U)
81165#define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK)
81171#define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK (0xFFFU)
81172#define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT (0U)
81175#define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK)
81176
81177#define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK (0xFFF0000U)
81178#define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT (16U)
81181#define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK)
81187#define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK (0xFFFU)
81188#define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT (0U)
81191#define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK)
81192
81193#define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK (0xFFF0000U)
81194#define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT (16U)
81197#define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK)
81203#define TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK (0xFFFU)
81204#define TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT (0U)
81207#define TMPSNS_RANGE1_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK)
81213#define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK (0xFFFU)
81214#define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT (0U)
81217#define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK)
81223#define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK (0xFFFU)
81224#define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT (0U)
81227#define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK)
81233#define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK (0xFFFU)
81234#define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT (0U)
81237#define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK)
81243#define TMPSNS_STATUS0_TEMP_VAL_MASK (0xFFFU)
81244#define TMPSNS_STATUS0_TEMP_VAL_SHIFT (0U)
81247#define TMPSNS_STATUS0_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_TEMP_VAL_SHIFT)) & TMPSNS_STATUS0_TEMP_VAL_MASK)
81248
81249#define TMPSNS_STATUS0_FINISH_MASK (0x10000U)
81250#define TMPSNS_STATUS0_FINISH_SHIFT (16U)
81255#define TMPSNS_STATUS0_FINISH(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_FINISH_SHIFT)) & TMPSNS_STATUS0_FINISH_MASK)
81256
81257#define TMPSNS_STATUS0_LOW_TEMP_MASK (0x20000U)
81258#define TMPSNS_STATUS0_LOW_TEMP_SHIFT (17U)
81263#define TMPSNS_STATUS0_LOW_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_LOW_TEMP_SHIFT)) & TMPSNS_STATUS0_LOW_TEMP_MASK)
81264
81265#define TMPSNS_STATUS0_HIGH_TEMP_MASK (0x40000U)
81266#define TMPSNS_STATUS0_HIGH_TEMP_SHIFT (18U)
81271#define TMPSNS_STATUS0_HIGH_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_HIGH_TEMP_SHIFT)) & TMPSNS_STATUS0_HIGH_TEMP_MASK)
81272
81273#define TMPSNS_STATUS0_PANIC_TEMP_MASK (0x80000U)
81274#define TMPSNS_STATUS0_PANIC_TEMP_SHIFT (19U)
81279#define TMPSNS_STATUS0_PANIC_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_PANIC_TEMP_SHIFT)) & TMPSNS_STATUS0_PANIC_TEMP_MASK) /* end of group TMPSNS_Register_Masks */
81286
81287
81288/* TMPSNS - Peripheral instance base addresses */
81290#define TMPSNS_BASE (0u)
81292#define TMPSNS ((TMPSNS_Type *)TMPSNS_BASE)
81294#define TMPSNS_BASE_ADDRS { TMPSNS_BASE }
81296#define TMPSNS_BASE_PTRS { TMPSNS }
81297 /* end of group TMPSNS_Peripheral_Access_Layer */
81301
81302
81303/* ----------------------------------------------------------------------------
81304 -- TMR Peripheral Access Layer
81305 ---------------------------------------------------------------------------- */
81306
81313typedef struct {
81314 struct { /* offset: 0x0, array step: 0x20 */
81315 __IO uint16_t COMP1;
81316 __IO uint16_t COMP2;
81317 __IO uint16_t CAPT;
81318 __IO uint16_t LOAD;
81319 __IO uint16_t HOLD;
81320 __IO uint16_t CNTR;
81321 __IO uint16_t CTRL;
81322 __IO uint16_t SCTRL;
81323 __IO uint16_t CMPLD1;
81324 __IO uint16_t CMPLD2;
81325 __IO uint16_t CSCTRL;
81326 __IO uint16_t FILT;
81327 __IO uint16_t DMA;
81328 uint8_t RESERVED_0[4];
81329 __IO uint16_t ENBL;
81330 } CHANNEL[4];
81331} TMR_Type;
81332
81333/* ----------------------------------------------------------------------------
81334 -- TMR Register Masks
81335 ---------------------------------------------------------------------------- */
81336
81345#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)
81346#define TMR_COMP1_COMPARISON_1_SHIFT (0U)
81349#define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
81352/* The count of TMR_COMP1 */
81353#define TMR_COMP1_COUNT (4U)
81354
81358#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)
81359#define TMR_COMP2_COMPARISON_2_SHIFT (0U)
81362#define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
81365/* The count of TMR_COMP2 */
81366#define TMR_COMP2_COUNT (4U)
81367
81371#define TMR_CAPT_CAPTURE_MASK (0xFFFFU)
81372#define TMR_CAPT_CAPTURE_SHIFT (0U)
81375#define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
81378/* The count of TMR_CAPT */
81379#define TMR_CAPT_COUNT (4U)
81380
81384#define TMR_LOAD_LOAD_MASK (0xFFFFU)
81385#define TMR_LOAD_LOAD_SHIFT (0U)
81388#define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
81391/* The count of TMR_LOAD */
81392#define TMR_LOAD_COUNT (4U)
81393
81397#define TMR_HOLD_HOLD_MASK (0xFFFFU)
81398#define TMR_HOLD_HOLD_SHIFT (0U)
81401#define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
81404/* The count of TMR_HOLD */
81405#define TMR_HOLD_COUNT (4U)
81406
81410#define TMR_CNTR_COUNTER_MASK (0xFFFFU)
81411#define TMR_CNTR_COUNTER_SHIFT (0U)
81414#define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
81417/* The count of TMR_CNTR */
81418#define TMR_CNTR_COUNT (4U)
81419
81423#define TMR_CTRL_OUTMODE_MASK (0x7U)
81424#define TMR_CTRL_OUTMODE_SHIFT (0U)
81435#define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
81436
81437#define TMR_CTRL_COINIT_MASK (0x8U)
81438#define TMR_CTRL_COINIT_SHIFT (3U)
81443#define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
81444
81445#define TMR_CTRL_DIR_MASK (0x10U)
81446#define TMR_CTRL_DIR_SHIFT (4U)
81451#define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
81452
81453#define TMR_CTRL_LENGTH_MASK (0x20U)
81454#define TMR_CTRL_LENGTH_SHIFT (5U)
81463#define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
81464
81465#define TMR_CTRL_ONCE_MASK (0x40U)
81466#define TMR_CTRL_ONCE_SHIFT (6U)
81474#define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
81475
81476#define TMR_CTRL_SCS_MASK (0x180U)
81477#define TMR_CTRL_SCS_SHIFT (7U)
81484#define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
81485
81486#define TMR_CTRL_PCS_MASK (0x1E00U)
81487#define TMR_CTRL_PCS_SHIFT (9U)
81506#define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
81507
81508#define TMR_CTRL_CM_MASK (0xE000U)
81509#define TMR_CTRL_CM_SHIFT (13U)
81523#define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
81526/* The count of TMR_CTRL */
81527#define TMR_CTRL_COUNT (4U)
81528
81532#define TMR_SCTRL_OEN_MASK (0x1U)
81533#define TMR_SCTRL_OEN_SHIFT (0U)
81539#define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
81540
81541#define TMR_SCTRL_OPS_MASK (0x2U)
81542#define TMR_SCTRL_OPS_SHIFT (1U)
81547#define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
81548
81549#define TMR_SCTRL_FORCE_MASK (0x4U)
81550#define TMR_SCTRL_FORCE_SHIFT (2U)
81553#define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
81554
81555#define TMR_SCTRL_VAL_MASK (0x8U)
81556#define TMR_SCTRL_VAL_SHIFT (3U)
81559#define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
81560
81561#define TMR_SCTRL_EEOF_MASK (0x10U)
81562#define TMR_SCTRL_EEOF_SHIFT (4U)
81565#define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
81566
81567#define TMR_SCTRL_MSTR_MASK (0x20U)
81568#define TMR_SCTRL_MSTR_SHIFT (5U)
81571#define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
81572
81573#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)
81574#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)
81581#define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
81582
81583#define TMR_SCTRL_INPUT_MASK (0x100U)
81584#define TMR_SCTRL_INPUT_SHIFT (8U)
81587#define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
81588
81589#define TMR_SCTRL_IPS_MASK (0x200U)
81590#define TMR_SCTRL_IPS_SHIFT (9U)
81593#define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
81594
81595#define TMR_SCTRL_IEFIE_MASK (0x400U)
81596#define TMR_SCTRL_IEFIE_SHIFT (10U)
81599#define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
81600
81601#define TMR_SCTRL_IEF_MASK (0x800U)
81602#define TMR_SCTRL_IEF_SHIFT (11U)
81605#define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
81606
81607#define TMR_SCTRL_TOFIE_MASK (0x1000U)
81608#define TMR_SCTRL_TOFIE_SHIFT (12U)
81611#define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
81612
81613#define TMR_SCTRL_TOF_MASK (0x2000U)
81614#define TMR_SCTRL_TOF_SHIFT (13U)
81617#define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
81618
81619#define TMR_SCTRL_TCFIE_MASK (0x4000U)
81620#define TMR_SCTRL_TCFIE_SHIFT (14U)
81623#define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
81624
81625#define TMR_SCTRL_TCF_MASK (0x8000U)
81626#define TMR_SCTRL_TCF_SHIFT (15U)
81629#define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
81632/* The count of TMR_SCTRL */
81633#define TMR_SCTRL_COUNT (4U)
81634
81638#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)
81639#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)
81642#define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
81645/* The count of TMR_CMPLD1 */
81646#define TMR_CMPLD1_COUNT (4U)
81647
81651#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)
81652#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)
81655#define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
81658/* The count of TMR_CMPLD2 */
81659#define TMR_CMPLD2_COUNT (4U)
81660
81664#define TMR_CSCTRL_CL1_MASK (0x3U)
81665#define TMR_CSCTRL_CL1_SHIFT (0U)
81672#define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
81673
81674#define TMR_CSCTRL_CL2_MASK (0xCU)
81675#define TMR_CSCTRL_CL2_SHIFT (2U)
81682#define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
81683
81684#define TMR_CSCTRL_TCF1_MASK (0x10U)
81685#define TMR_CSCTRL_TCF1_SHIFT (4U)
81688#define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
81689
81690#define TMR_CSCTRL_TCF2_MASK (0x20U)
81691#define TMR_CSCTRL_TCF2_SHIFT (5U)
81694#define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
81695
81696#define TMR_CSCTRL_TCF1EN_MASK (0x40U)
81697#define TMR_CSCTRL_TCF1EN_SHIFT (6U)
81700#define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
81701
81702#define TMR_CSCTRL_TCF2EN_MASK (0x80U)
81703#define TMR_CSCTRL_TCF2EN_SHIFT (7U)
81706#define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
81707
81708#define TMR_CSCTRL_UP_MASK (0x200U)
81709#define TMR_CSCTRL_UP_SHIFT (9U)
81714#define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
81715
81716#define TMR_CSCTRL_TCI_MASK (0x400U)
81717#define TMR_CSCTRL_TCI_SHIFT (10U)
81722#define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
81723
81724#define TMR_CSCTRL_ROC_MASK (0x800U)
81725#define TMR_CSCTRL_ROC_SHIFT (11U)
81730#define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
81731
81732#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)
81733#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U)
81738#define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
81739
81740#define TMR_CSCTRL_FAULT_MASK (0x2000U)
81741#define TMR_CSCTRL_FAULT_SHIFT (13U)
81746#define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
81747
81748#define TMR_CSCTRL_DBG_EN_MASK (0xC000U)
81749#define TMR_CSCTRL_DBG_EN_SHIFT (14U)
81756#define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
81759/* The count of TMR_CSCTRL */
81760#define TMR_CSCTRL_COUNT (4U)
81761
81765#define TMR_FILT_FILT_PER_MASK (0xFFU)
81766#define TMR_FILT_FILT_PER_SHIFT (0U)
81769#define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
81770
81771#define TMR_FILT_FILT_CNT_MASK (0x700U)
81772#define TMR_FILT_FILT_CNT_SHIFT (8U)
81775#define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
81778/* The count of TMR_FILT */
81779#define TMR_FILT_COUNT (4U)
81780
81784#define TMR_DMA_IEFDE_MASK (0x1U)
81785#define TMR_DMA_IEFDE_SHIFT (0U)
81788#define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
81789
81790#define TMR_DMA_CMPLD1DE_MASK (0x2U)
81791#define TMR_DMA_CMPLD1DE_SHIFT (1U)
81794#define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
81795
81796#define TMR_DMA_CMPLD2DE_MASK (0x4U)
81797#define TMR_DMA_CMPLD2DE_SHIFT (2U)
81800#define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
81803/* The count of TMR_DMA */
81804#define TMR_DMA_COUNT (4U)
81805
81809#define TMR_ENBL_ENBL_MASK (0xFU)
81810#define TMR_ENBL_ENBL_SHIFT (0U)
81815#define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
81818/* The count of TMR_ENBL */
81819#define TMR_ENBL_COUNT (4U)
81820
81821 /* end of group TMR_Register_Masks */
81825
81826
81827/* TMR - Peripheral instance base addresses */
81829#define TMR1_BASE (0x4015C000u)
81831#define TMR1 ((TMR_Type *)TMR1_BASE)
81833#define TMR2_BASE (0x40160000u)
81835#define TMR2 ((TMR_Type *)TMR2_BASE)
81837#define TMR3_BASE (0x40164000u)
81839#define TMR3 ((TMR_Type *)TMR3_BASE)
81841#define TMR4_BASE (0x40168000u)
81843#define TMR4 ((TMR_Type *)TMR4_BASE)
81845#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
81847#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
81849#define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
81850 /* end of group TMR_Peripheral_Access_Layer */
81854
81855
81856/* ----------------------------------------------------------------------------
81857 -- USB Peripheral Access Layer
81858 ---------------------------------------------------------------------------- */
81859
81866typedef struct {
81867 __I uint32_t ID;
81868 __I uint32_t HWGENERAL;
81869 __I uint32_t HWHOST;
81870 __I uint32_t HWDEVICE;
81871 __I uint32_t HWTXBUF;
81872 __I uint32_t HWRXBUF;
81873 uint8_t RESERVED_0[104];
81874 __IO uint32_t GPTIMER0LD;
81875 __IO uint32_t GPTIMER0CTRL;
81876 __IO uint32_t GPTIMER1LD;
81877 __IO uint32_t GPTIMER1CTRL;
81878 __IO uint32_t SBUSCFG;
81879 uint8_t RESERVED_1[108];
81880 __I uint8_t CAPLENGTH;
81881 uint8_t RESERVED_2[1];
81882 __I uint16_t HCIVERSION;
81883 __I uint32_t HCSPARAMS;
81884 __I uint32_t HCCPARAMS;
81885 uint8_t RESERVED_3[20];
81886 __I uint16_t DCIVERSION;
81887 uint8_t RESERVED_4[2];
81888 __I uint32_t DCCPARAMS;
81889 uint8_t RESERVED_5[24];
81890 __IO uint32_t USBCMD;
81891 __IO uint32_t USBSTS;
81892 __IO uint32_t USBINTR;
81893 __IO uint32_t FRINDEX;
81894 uint8_t RESERVED_6[4];
81895 union { /* offset: 0x154 */
81896 __IO uint32_t DEVICEADDR;
81898 };
81899 union { /* offset: 0x158 */
81902 };
81903 uint8_t RESERVED_7[4];
81904 __IO uint32_t BURSTSIZE;
81905 __IO uint32_t TXFILLTUNING;
81906 uint8_t RESERVED_8[16];
81907 __IO uint32_t ENDPTNAK;
81908 __IO uint32_t ENDPTNAKEN;
81909 __I uint32_t CONFIGFLAG;
81910 __IO uint32_t PORTSC1;
81911 uint8_t RESERVED_9[28];
81912 __IO uint32_t OTGSC;
81913 __IO uint32_t USBMODE;
81914 __IO uint32_t ENDPTSETUPSTAT;
81915 __IO uint32_t ENDPTPRIME;
81916 __IO uint32_t ENDPTFLUSH;
81917 __I uint32_t ENDPTSTAT;
81918 __IO uint32_t ENDPTCOMPLETE;
81919 __IO uint32_t ENDPTCTRL0;
81920 __IO uint32_t ENDPTCTRL[7];
81921} USB_Type;
81922
81923/* ----------------------------------------------------------------------------
81924 -- USB Register Masks
81925 ---------------------------------------------------------------------------- */
81926
81935#define USB_ID_ID_MASK (0x3FU)
81936#define USB_ID_ID_SHIFT (0U)
81939#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
81940
81941#define USB_ID_NID_MASK (0x3F00U)
81942#define USB_ID_NID_SHIFT (8U)
81945#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
81946
81947#define USB_ID_REVISION_MASK (0xFF0000U)
81948#define USB_ID_REVISION_SHIFT (16U)
81951#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
81957#define USB_HWGENERAL_PHYW_MASK (0x30U)
81958#define USB_HWGENERAL_PHYW_SHIFT (4U)
81965#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
81966
81967#define USB_HWGENERAL_PHYM_MASK (0x1C0U)
81968#define USB_HWGENERAL_PHYM_SHIFT (6U)
81979#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
81980
81981#define USB_HWGENERAL_SM_MASK (0x600U)
81982#define USB_HWGENERAL_SM_SHIFT (9U)
81989#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
81995#define USB_HWHOST_HC_MASK (0x1U)
81996#define USB_HWHOST_HC_SHIFT (0U)
82001#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
82002
82003#define USB_HWHOST_NPORT_MASK (0xEU)
82004#define USB_HWHOST_NPORT_SHIFT (1U)
82007#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
82013#define USB_HWDEVICE_DC_MASK (0x1U)
82014#define USB_HWDEVICE_DC_SHIFT (0U)
82019#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
82020
82021#define USB_HWDEVICE_DEVEP_MASK (0x3EU)
82022#define USB_HWDEVICE_DEVEP_SHIFT (1U)
82025#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
82031#define USB_HWTXBUF_TXBURST_MASK (0xFFU)
82032#define USB_HWTXBUF_TXBURST_SHIFT (0U)
82035#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
82036
82037#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
82038#define USB_HWTXBUF_TXCHANADD_SHIFT (16U)
82041#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
82047#define USB_HWRXBUF_RXBURST_MASK (0xFFU)
82048#define USB_HWRXBUF_RXBURST_SHIFT (0U)
82051#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
82052
82053#define USB_HWRXBUF_RXADD_MASK (0xFF00U)
82054#define USB_HWRXBUF_RXADD_SHIFT (8U)
82057#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
82063#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
82064#define USB_GPTIMER0LD_GPTLD_SHIFT (0U)
82067#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
82073#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)
82074#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)
82077#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
82078
82079#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)
82080#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)
82085#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
82086
82087#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)
82088#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)
82093#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
82094
82095#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)
82096#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)
82101#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
82107#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
82108#define USB_GPTIMER1LD_GPTLD_SHIFT (0U)
82111#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
82117#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)
82118#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)
82121#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
82122
82123#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)
82124#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)
82129#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
82130
82131#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)
82132#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)
82137#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
82138
82139#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)
82140#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)
82145#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
82151#define USB_SBUSCFG_AHBBRST_MASK (0x7U)
82152#define USB_SBUSCFG_AHBBRST_SHIFT (0U)
82163#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
82169#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
82170#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)
82173#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
82179#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)
82180#define USB_HCIVERSION_HCIVERSION_SHIFT (0U)
82183#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
82189#define USB_HCSPARAMS_N_PORTS_MASK (0xFU)
82190#define USB_HCSPARAMS_N_PORTS_SHIFT (0U)
82193#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
82194
82195#define USB_HCSPARAMS_PPC_MASK (0x10U)
82196#define USB_HCSPARAMS_PPC_SHIFT (4U)
82199#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
82200
82201#define USB_HCSPARAMS_N_PCC_MASK (0xF00U)
82202#define USB_HCSPARAMS_N_PCC_SHIFT (8U)
82205#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
82206
82207#define USB_HCSPARAMS_N_CC_MASK (0xF000U)
82208#define USB_HCSPARAMS_N_CC_SHIFT (12U)
82213#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
82214
82215#define USB_HCSPARAMS_PI_MASK (0x10000U)
82216#define USB_HCSPARAMS_PI_SHIFT (16U)
82219#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
82220
82221#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U)
82222#define USB_HCSPARAMS_N_PTT_SHIFT (20U)
82225#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
82226
82227#define USB_HCSPARAMS_N_TT_MASK (0xF000000U)
82228#define USB_HCSPARAMS_N_TT_SHIFT (24U)
82231#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
82237#define USB_HCCPARAMS_ADC_MASK (0x1U)
82238#define USB_HCCPARAMS_ADC_SHIFT (0U)
82241#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
82242
82243#define USB_HCCPARAMS_PFL_MASK (0x2U)
82244#define USB_HCCPARAMS_PFL_SHIFT (1U)
82247#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
82248
82249#define USB_HCCPARAMS_ASP_MASK (0x4U)
82250#define USB_HCCPARAMS_ASP_SHIFT (2U)
82253#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
82254
82255#define USB_HCCPARAMS_IST_MASK (0xF0U)
82256#define USB_HCCPARAMS_IST_SHIFT (4U)
82259#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
82260
82261#define USB_HCCPARAMS_EECP_MASK (0xFF00U)
82262#define USB_HCCPARAMS_EECP_SHIFT (8U)
82265#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
82271#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
82272#define USB_DCIVERSION_DCIVERSION_SHIFT (0U)
82275#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
82281#define USB_DCCPARAMS_DEN_MASK (0x1FU)
82282#define USB_DCCPARAMS_DEN_SHIFT (0U)
82285#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
82286
82287#define USB_DCCPARAMS_DC_MASK (0x80U)
82288#define USB_DCCPARAMS_DC_SHIFT (7U)
82291#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
82292
82293#define USB_DCCPARAMS_HC_MASK (0x100U)
82294#define USB_DCCPARAMS_HC_SHIFT (8U)
82297#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
82303#define USB_USBCMD_RS_MASK (0x1U)
82304#define USB_USBCMD_RS_SHIFT (0U)
82307#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
82308
82309#define USB_USBCMD_RST_MASK (0x2U)
82310#define USB_USBCMD_RST_SHIFT (1U)
82313#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
82314
82315#define USB_USBCMD_FS_1_MASK (0xCU)
82316#define USB_USBCMD_FS_1_SHIFT (2U)
82319#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
82320
82321#define USB_USBCMD_PSE_MASK (0x10U)
82322#define USB_USBCMD_PSE_SHIFT (4U)
82327#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
82328
82329#define USB_USBCMD_ASE_MASK (0x20U)
82330#define USB_USBCMD_ASE_SHIFT (5U)
82335#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
82336
82337#define USB_USBCMD_IAA_MASK (0x40U)
82338#define USB_USBCMD_IAA_SHIFT (6U)
82341#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
82342
82343#define USB_USBCMD_ASP_MASK (0x300U)
82344#define USB_USBCMD_ASP_SHIFT (8U)
82347#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
82348
82349#define USB_USBCMD_ASPE_MASK (0x800U)
82350#define USB_USBCMD_ASPE_SHIFT (11U)
82353#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
82354
82355#define USB_USBCMD_SUTW_MASK (0x2000U)
82356#define USB_USBCMD_SUTW_SHIFT (13U)
82359#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
82360
82361#define USB_USBCMD_ATDTW_MASK (0x4000U)
82362#define USB_USBCMD_ATDTW_SHIFT (14U)
82365#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
82366
82367#define USB_USBCMD_FS_2_MASK (0x8000U)
82368#define USB_USBCMD_FS_2_SHIFT (15U)
82371#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
82372
82373#define USB_USBCMD_ITC_MASK (0xFF0000U)
82374#define USB_USBCMD_ITC_SHIFT (16U)
82385#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
82391#define USB_USBSTS_UI_MASK (0x1U)
82392#define USB_USBSTS_UI_SHIFT (0U)
82395#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
82396
82397#define USB_USBSTS_UEI_MASK (0x2U)
82398#define USB_USBSTS_UEI_SHIFT (1U)
82401#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
82402
82403#define USB_USBSTS_PCI_MASK (0x4U)
82404#define USB_USBSTS_PCI_SHIFT (2U)
82407#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
82408
82409#define USB_USBSTS_FRI_MASK (0x8U)
82410#define USB_USBSTS_FRI_SHIFT (3U)
82413#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
82414
82415#define USB_USBSTS_SEI_MASK (0x10U)
82416#define USB_USBSTS_SEI_SHIFT (4U)
82419#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
82420
82421#define USB_USBSTS_AAI_MASK (0x20U)
82422#define USB_USBSTS_AAI_SHIFT (5U)
82425#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
82426
82427#define USB_USBSTS_URI_MASK (0x40U)
82428#define USB_USBSTS_URI_SHIFT (6U)
82431#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
82432
82433#define USB_USBSTS_SRI_MASK (0x80U)
82434#define USB_USBSTS_SRI_SHIFT (7U)
82437#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
82438
82439#define USB_USBSTS_SLI_MASK (0x100U)
82440#define USB_USBSTS_SLI_SHIFT (8U)
82443#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
82444
82445#define USB_USBSTS_ULPII_MASK (0x400U)
82446#define USB_USBSTS_ULPII_SHIFT (10U)
82449#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
82450
82451#define USB_USBSTS_HCH_MASK (0x1000U)
82452#define USB_USBSTS_HCH_SHIFT (12U)
82455#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
82456
82457#define USB_USBSTS_RCL_MASK (0x2000U)
82458#define USB_USBSTS_RCL_SHIFT (13U)
82461#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
82462
82463#define USB_USBSTS_PS_MASK (0x4000U)
82464#define USB_USBSTS_PS_SHIFT (14U)
82467#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
82468
82469#define USB_USBSTS_AS_MASK (0x8000U)
82470#define USB_USBSTS_AS_SHIFT (15U)
82473#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
82474
82475#define USB_USBSTS_NAKI_MASK (0x10000U)
82476#define USB_USBSTS_NAKI_SHIFT (16U)
82479#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
82480
82481#define USB_USBSTS_TI0_MASK (0x1000000U)
82482#define USB_USBSTS_TI0_SHIFT (24U)
82485#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
82486
82487#define USB_USBSTS_TI1_MASK (0x2000000U)
82488#define USB_USBSTS_TI1_SHIFT (25U)
82491#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
82497#define USB_USBINTR_UE_MASK (0x1U)
82498#define USB_USBINTR_UE_SHIFT (0U)
82501#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
82502
82503#define USB_USBINTR_UEE_MASK (0x2U)
82504#define USB_USBINTR_UEE_SHIFT (1U)
82507#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
82508
82509#define USB_USBINTR_PCE_MASK (0x4U)
82510#define USB_USBINTR_PCE_SHIFT (2U)
82513#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
82514
82515#define USB_USBINTR_FRE_MASK (0x8U)
82516#define USB_USBINTR_FRE_SHIFT (3U)
82519#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
82520
82521#define USB_USBINTR_SEE_MASK (0x10U)
82522#define USB_USBINTR_SEE_SHIFT (4U)
82525#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
82526
82527#define USB_USBINTR_AAE_MASK (0x20U)
82528#define USB_USBINTR_AAE_SHIFT (5U)
82531#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
82532
82533#define USB_USBINTR_URE_MASK (0x40U)
82534#define USB_USBINTR_URE_SHIFT (6U)
82537#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
82538
82539#define USB_USBINTR_SRE_MASK (0x80U)
82540#define USB_USBINTR_SRE_SHIFT (7U)
82543#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
82544
82545#define USB_USBINTR_SLE_MASK (0x100U)
82546#define USB_USBINTR_SLE_SHIFT (8U)
82549#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
82550
82551#define USB_USBINTR_ULPIE_MASK (0x400U)
82552#define USB_USBINTR_ULPIE_SHIFT (10U)
82555#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
82556
82557#define USB_USBINTR_NAKE_MASK (0x10000U)
82558#define USB_USBINTR_NAKE_SHIFT (16U)
82561#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
82562
82563#define USB_USBINTR_UAIE_MASK (0x40000U)
82564#define USB_USBINTR_UAIE_SHIFT (18U)
82567#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
82568
82569#define USB_USBINTR_UPIE_MASK (0x80000U)
82570#define USB_USBINTR_UPIE_SHIFT (19U)
82573#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
82574
82575#define USB_USBINTR_TIE0_MASK (0x1000000U)
82576#define USB_USBINTR_TIE0_SHIFT (24U)
82579#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
82580
82581#define USB_USBINTR_TIE1_MASK (0x2000000U)
82582#define USB_USBINTR_TIE1_SHIFT (25U)
82585#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
82591#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU)
82592#define USB_FRINDEX_FRINDEX_SHIFT (0U)
82603#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
82609#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U)
82610#define USB_DEVICEADDR_USBADRA_SHIFT (24U)
82613#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
82614
82615#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U)
82616#define USB_DEVICEADDR_USBADR_SHIFT (25U)
82619#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
82625#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)
82626#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)
82629#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
82635#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
82636#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
82639#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
82645#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)
82646#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)
82649#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
82655#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU)
82656#define USB_BURSTSIZE_RXPBURST_SHIFT (0U)
82659#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
82660
82661#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)
82662#define USB_BURSTSIZE_TXPBURST_SHIFT (8U)
82665#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
82671#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)
82672#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)
82675#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
82676
82677#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
82678#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
82681#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
82682
82683#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
82684#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
82687#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
82693#define USB_ENDPTNAK_EPRN_MASK (0xFFU)
82694#define USB_ENDPTNAK_EPRN_SHIFT (0U)
82697#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
82698
82699#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U)
82700#define USB_ENDPTNAK_EPTN_SHIFT (16U)
82703#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
82709#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)
82710#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U)
82713#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
82714
82715#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)
82716#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U)
82719#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
82725#define USB_CONFIGFLAG_CF_MASK (0x1U)
82726#define USB_CONFIGFLAG_CF_SHIFT (0U)
82731#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
82737#define USB_PORTSC1_CCS_MASK (0x1U)
82738#define USB_PORTSC1_CCS_SHIFT (0U)
82741#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
82742
82743#define USB_PORTSC1_CSC_MASK (0x2U)
82744#define USB_PORTSC1_CSC_SHIFT (1U)
82747#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
82748
82749#define USB_PORTSC1_PE_MASK (0x4U)
82750#define USB_PORTSC1_PE_SHIFT (2U)
82753#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
82754
82755#define USB_PORTSC1_PEC_MASK (0x8U)
82756#define USB_PORTSC1_PEC_SHIFT (3U)
82759#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
82760
82761#define USB_PORTSC1_OCA_MASK (0x10U)
82762#define USB_PORTSC1_OCA_SHIFT (4U)
82767#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
82768
82769#define USB_PORTSC1_OCC_MASK (0x20U)
82770#define USB_PORTSC1_OCC_SHIFT (5U)
82773#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
82774
82775#define USB_PORTSC1_FPR_MASK (0x40U)
82776#define USB_PORTSC1_FPR_SHIFT (6U)
82779#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
82780
82781#define USB_PORTSC1_SUSP_MASK (0x80U)
82782#define USB_PORTSC1_SUSP_SHIFT (7U)
82785#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
82786
82787#define USB_PORTSC1_PR_MASK (0x100U)
82788#define USB_PORTSC1_PR_SHIFT (8U)
82791#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
82792
82793#define USB_PORTSC1_HSP_MASK (0x200U)
82794#define USB_PORTSC1_HSP_SHIFT (9U)
82797#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
82798
82799#define USB_PORTSC1_LS_MASK (0xC00U)
82800#define USB_PORTSC1_LS_SHIFT (10U)
82807#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
82808
82809#define USB_PORTSC1_PP_MASK (0x1000U)
82810#define USB_PORTSC1_PP_SHIFT (12U)
82813#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
82814
82815#define USB_PORTSC1_PO_MASK (0x2000U)
82816#define USB_PORTSC1_PO_SHIFT (13U)
82819#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
82820
82821#define USB_PORTSC1_PIC_MASK (0xC000U)
82822#define USB_PORTSC1_PIC_SHIFT (14U)
82829#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
82830
82831#define USB_PORTSC1_PTC_MASK (0xF0000U)
82832#define USB_PORTSC1_PTC_SHIFT (16U)
82844#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
82845
82846#define USB_PORTSC1_WKCN_MASK (0x100000U)
82847#define USB_PORTSC1_WKCN_SHIFT (20U)
82850#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
82851
82852#define USB_PORTSC1_WKDC_MASK (0x200000U)
82853#define USB_PORTSC1_WKDC_SHIFT (21U)
82856#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
82857
82858#define USB_PORTSC1_WKOC_MASK (0x400000U)
82859#define USB_PORTSC1_WKOC_SHIFT (22U)
82862#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
82863
82864#define USB_PORTSC1_PHCD_MASK (0x800000U)
82865#define USB_PORTSC1_PHCD_SHIFT (23U)
82870#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
82871
82872#define USB_PORTSC1_PFSC_MASK (0x1000000U)
82873#define USB_PORTSC1_PFSC_SHIFT (24U)
82878#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
82879
82880#define USB_PORTSC1_PTS_2_MASK (0x2000000U)
82881#define USB_PORTSC1_PTS_2_SHIFT (25U)
82884#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
82885
82886#define USB_PORTSC1_PSPD_MASK (0xC000000U)
82887#define USB_PORTSC1_PSPD_SHIFT (26U)
82894#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
82895
82896#define USB_PORTSC1_PTW_MASK (0x10000000U)
82897#define USB_PORTSC1_PTW_SHIFT (28U)
82902#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
82903
82904#define USB_PORTSC1_STS_MASK (0x20000000U)
82905#define USB_PORTSC1_STS_SHIFT (29U)
82908#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
82909
82910#define USB_PORTSC1_PTS_1_MASK (0xC0000000U)
82911#define USB_PORTSC1_PTS_1_SHIFT (30U)
82914#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
82920#define USB_OTGSC_VD_MASK (0x1U)
82921#define USB_OTGSC_VD_SHIFT (0U)
82924#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
82925
82926#define USB_OTGSC_VC_MASK (0x2U)
82927#define USB_OTGSC_VC_SHIFT (1U)
82930#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
82931
82932#define USB_OTGSC_OT_MASK (0x8U)
82933#define USB_OTGSC_OT_SHIFT (3U)
82936#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
82937
82938#define USB_OTGSC_DP_MASK (0x10U)
82939#define USB_OTGSC_DP_SHIFT (4U)
82942#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
82943
82944#define USB_OTGSC_IDPU_MASK (0x20U)
82945#define USB_OTGSC_IDPU_SHIFT (5U)
82948#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
82949
82950#define USB_OTGSC_ID_MASK (0x100U)
82951#define USB_OTGSC_ID_SHIFT (8U)
82954#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
82955
82956#define USB_OTGSC_AVV_MASK (0x200U)
82957#define USB_OTGSC_AVV_SHIFT (9U)
82960#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
82961
82962#define USB_OTGSC_ASV_MASK (0x400U)
82963#define USB_OTGSC_ASV_SHIFT (10U)
82966#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
82967
82968#define USB_OTGSC_BSV_MASK (0x800U)
82969#define USB_OTGSC_BSV_SHIFT (11U)
82972#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
82973
82974#define USB_OTGSC_BSE_MASK (0x1000U)
82975#define USB_OTGSC_BSE_SHIFT (12U)
82978#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
82979
82980#define USB_OTGSC_TOG_1MS_MASK (0x2000U)
82981#define USB_OTGSC_TOG_1MS_SHIFT (13U)
82984#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
82985
82986#define USB_OTGSC_DPS_MASK (0x4000U)
82987#define USB_OTGSC_DPS_SHIFT (14U)
82990#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
82991
82992#define USB_OTGSC_IDIS_MASK (0x10000U)
82993#define USB_OTGSC_IDIS_SHIFT (16U)
82996#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
82997
82998#define USB_OTGSC_AVVIS_MASK (0x20000U)
82999#define USB_OTGSC_AVVIS_SHIFT (17U)
83002#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
83003
83004#define USB_OTGSC_ASVIS_MASK (0x40000U)
83005#define USB_OTGSC_ASVIS_SHIFT (18U)
83008#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
83009
83010#define USB_OTGSC_BSVIS_MASK (0x80000U)
83011#define USB_OTGSC_BSVIS_SHIFT (19U)
83014#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
83015
83016#define USB_OTGSC_BSEIS_MASK (0x100000U)
83017#define USB_OTGSC_BSEIS_SHIFT (20U)
83020#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
83021
83022#define USB_OTGSC_STATUS_1MS_MASK (0x200000U)
83023#define USB_OTGSC_STATUS_1MS_SHIFT (21U)
83026#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
83027
83028#define USB_OTGSC_DPIS_MASK (0x400000U)
83029#define USB_OTGSC_DPIS_SHIFT (22U)
83032#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
83033
83034#define USB_OTGSC_IDIE_MASK (0x1000000U)
83035#define USB_OTGSC_IDIE_SHIFT (24U)
83038#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
83039
83040#define USB_OTGSC_AVVIE_MASK (0x2000000U)
83041#define USB_OTGSC_AVVIE_SHIFT (25U)
83044#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
83045
83046#define USB_OTGSC_ASVIE_MASK (0x4000000U)
83047#define USB_OTGSC_ASVIE_SHIFT (26U)
83050#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
83051
83052#define USB_OTGSC_BSVIE_MASK (0x8000000U)
83053#define USB_OTGSC_BSVIE_SHIFT (27U)
83056#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
83057
83058#define USB_OTGSC_BSEIE_MASK (0x10000000U)
83059#define USB_OTGSC_BSEIE_SHIFT (28U)
83062#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
83063
83064#define USB_OTGSC_EN_1MS_MASK (0x20000000U)
83065#define USB_OTGSC_EN_1MS_SHIFT (29U)
83068#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
83069
83070#define USB_OTGSC_DPIE_MASK (0x40000000U)
83071#define USB_OTGSC_DPIE_SHIFT (30U)
83074#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
83080#define USB_USBMODE_CM_MASK (0x3U)
83081#define USB_USBMODE_CM_SHIFT (0U)
83088#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
83089
83090#define USB_USBMODE_ES_MASK (0x4U)
83091#define USB_USBMODE_ES_SHIFT (2U)
83096#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
83097
83098#define USB_USBMODE_SLOM_MASK (0x8U)
83099#define USB_USBMODE_SLOM_SHIFT (3U)
83104#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
83105
83106#define USB_USBMODE_SDIS_MASK (0x10U)
83107#define USB_USBMODE_SDIS_SHIFT (4U)
83110#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
83116#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
83117#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
83120#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
83126#define USB_ENDPTPRIME_PERB_MASK (0xFFU)
83127#define USB_ENDPTPRIME_PERB_SHIFT (0U)
83130#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
83131
83132#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U)
83133#define USB_ENDPTPRIME_PETB_SHIFT (16U)
83136#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
83142#define USB_ENDPTFLUSH_FERB_MASK (0xFFU)
83143#define USB_ENDPTFLUSH_FERB_SHIFT (0U)
83146#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
83147
83148#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)
83149#define USB_ENDPTFLUSH_FETB_SHIFT (16U)
83152#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
83158#define USB_ENDPTSTAT_ERBR_MASK (0xFFU)
83159#define USB_ENDPTSTAT_ERBR_SHIFT (0U)
83162#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
83163
83164#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)
83165#define USB_ENDPTSTAT_ETBR_SHIFT (16U)
83168#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
83174#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)
83175#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)
83178#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
83179
83180#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)
83181#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)
83184#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
83190#define USB_ENDPTCTRL0_RXS_MASK (0x1U)
83191#define USB_ENDPTCTRL0_RXS_SHIFT (0U)
83194#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
83195
83196#define USB_ENDPTCTRL0_RXT_MASK (0xCU)
83197#define USB_ENDPTCTRL0_RXT_SHIFT (2U)
83200#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
83201
83202#define USB_ENDPTCTRL0_RXE_MASK (0x80U)
83203#define USB_ENDPTCTRL0_RXE_SHIFT (7U)
83206#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
83207
83208#define USB_ENDPTCTRL0_TXS_MASK (0x10000U)
83209#define USB_ENDPTCTRL0_TXS_SHIFT (16U)
83212#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
83213
83214#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U)
83215#define USB_ENDPTCTRL0_TXT_SHIFT (18U)
83218#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
83219
83220#define USB_ENDPTCTRL0_TXE_MASK (0x800000U)
83221#define USB_ENDPTCTRL0_TXE_SHIFT (23U)
83224#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
83230#define USB_ENDPTCTRL_RXS_MASK (0x1U)
83231#define USB_ENDPTCTRL_RXS_SHIFT (0U)
83234#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
83235
83236#define USB_ENDPTCTRL_RXD_MASK (0x2U)
83237#define USB_ENDPTCTRL_RXD_SHIFT (1U)
83240#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
83241
83242#define USB_ENDPTCTRL_RXT_MASK (0xCU)
83243#define USB_ENDPTCTRL_RXT_SHIFT (2U)
83246#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
83247
83248#define USB_ENDPTCTRL_RXI_MASK (0x20U)
83249#define USB_ENDPTCTRL_RXI_SHIFT (5U)
83252#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
83253
83254#define USB_ENDPTCTRL_RXR_MASK (0x40U)
83255#define USB_ENDPTCTRL_RXR_SHIFT (6U)
83258#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
83259
83260#define USB_ENDPTCTRL_RXE_MASK (0x80U)
83261#define USB_ENDPTCTRL_RXE_SHIFT (7U)
83264#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
83265
83266#define USB_ENDPTCTRL_TXS_MASK (0x10000U)
83267#define USB_ENDPTCTRL_TXS_SHIFT (16U)
83270#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
83271
83272#define USB_ENDPTCTRL_TXD_MASK (0x20000U)
83273#define USB_ENDPTCTRL_TXD_SHIFT (17U)
83276#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
83277
83278#define USB_ENDPTCTRL_TXT_MASK (0xC0000U)
83279#define USB_ENDPTCTRL_TXT_SHIFT (18U)
83282#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
83283
83284#define USB_ENDPTCTRL_TXI_MASK (0x200000U)
83285#define USB_ENDPTCTRL_TXI_SHIFT (21U)
83288#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
83289
83290#define USB_ENDPTCTRL_TXR_MASK (0x400000U)
83291#define USB_ENDPTCTRL_TXR_SHIFT (22U)
83294#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
83295
83296#define USB_ENDPTCTRL_TXE_MASK (0x800000U)
83297#define USB_ENDPTCTRL_TXE_SHIFT (23U)
83300#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
83303/* The count of USB_ENDPTCTRL */
83304#define USB_ENDPTCTRL_COUNT (7U)
83305
83306 /* end of group USB_Register_Masks */
83310
83311
83312/* USB - Peripheral instance base addresses */
83314#define USB_OTG1_BASE (0x40430000u)
83316#define USB_OTG1 ((USB_Type *)USB_OTG1_BASE)
83318#define USB_OTG2_BASE (0x4042C000u)
83320#define USB_OTG2 ((USB_Type *)USB_OTG2_BASE)
83322#define USB_BASE_ADDRS { 0u, USB_OTG1_BASE, USB_OTG2_BASE }
83324#define USB_BASE_PTRS { (USB_Type *)0u, USB_OTG1, USB_OTG2 }
83326#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
83327/* Backward compatibility */
83328#define GPTIMER0CTL GPTIMER0CTRL
83329#define GPTIMER1CTL GPTIMER1CTRL
83330#define USB_SBUSCFG SBUSCFG
83331#define EPLISTADDR ENDPTLISTADDR
83332#define EPSETUPSR ENDPTSETUPSTAT
83333#define EPPRIME ENDPTPRIME
83334#define EPFLUSH ENDPTFLUSH
83335#define EPSR ENDPTSTAT
83336#define EPCOMPLETE ENDPTCOMPLETE
83337#define EPCR ENDPTCTRL
83338#define EPCR0 ENDPTCTRL0
83339#define USBHS_ID_ID_MASK USB_ID_ID_MASK
83340#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT
83341#define USBHS_ID_ID(x) USB_ID_ID(x)
83342#define USBHS_ID_NID_MASK USB_ID_NID_MASK
83343#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT
83344#define USBHS_ID_NID(x) USB_ID_NID(x)
83345#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK
83346#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT
83347#define USBHS_ID_REVISION(x) USB_ID_REVISION(x)
83348#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK
83349#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT
83350#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)
83351#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK
83352#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT
83353#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)
83354#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK
83355#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT
83356#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)
83357#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK
83358#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT
83359#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x)
83360#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK
83361#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT
83362#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)
83363#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK
83364#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT
83365#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)
83366#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK
83367#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT
83368#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)
83369#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK
83370#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT
83371#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)
83372#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK
83373#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT
83374#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)
83375#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK
83376#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT
83377#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)
83378#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK
83379#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT
83380#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)
83381#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK
83382#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT
83383#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)
83384#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK
83385#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT
83386#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)
83387#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK
83388#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT
83389#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)
83390#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK
83391#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT
83392#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)
83393#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK
83394#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT
83395#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)
83396#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK
83397#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT
83398#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)
83399#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK
83400#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT
83401#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)
83402#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK
83403#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT
83404#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)
83405#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK
83406#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT
83407#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)
83408#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK
83409#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT
83410#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)
83411#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK
83412#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT
83413#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)
83414#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)
83415#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK
83416#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT
83417#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)
83418#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK
83419#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT
83420#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)
83421#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK
83422#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT
83423#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)
83424#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK
83425#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT
83426#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)
83427#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK
83428#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT
83429#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)
83430#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK
83431#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT
83432#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)
83433#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK
83434#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT
83435#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)
83436#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK
83437#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT
83438#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)
83439#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK
83440#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT
83441#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)
83442#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK
83443#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT
83444#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)
83445#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK
83446#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT
83447#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)
83448#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK
83449#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT
83450#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)
83451#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK
83452#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT
83453#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)
83454#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK
83455#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT
83456#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)
83457#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK
83458#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT
83459#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)
83460#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK
83461#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT
83462#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)
83463#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK
83464#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT
83465#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)
83466#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK
83467#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT
83468#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x)
83469#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK
83470#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT
83471#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x)
83472#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK
83473#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT
83474#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)
83475#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK
83476#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT
83477#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)
83478#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK
83479#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT
83480#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)
83481#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK
83482#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT
83483#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)
83484#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK
83485#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT
83486#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)
83487#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK
83488#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT
83489#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)
83490#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK
83491#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT
83492#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)
83493#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK
83494#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT
83495#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)
83496#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK
83497#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT
83498#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)
83499#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK
83500#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT
83501#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)
83502#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK
83503#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT
83504#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x)
83505#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK
83506#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT
83507#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)
83508#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK
83509#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT
83510#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)
83511#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK
83512#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT
83513#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)
83514#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK
83515#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT
83516#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)
83517#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK
83518#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT
83519#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)
83520#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK
83521#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT
83522#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x)
83523#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK
83524#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT
83525#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)
83526#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK
83527#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT
83528#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)
83529#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK
83530#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT
83531#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)
83532#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK
83533#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT
83534#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)
83535#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK
83536#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT
83537#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)
83538#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK
83539#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT
83540#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x)
83541#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK
83542#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT
83543#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x)
83544#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK
83545#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT
83546#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)
83547#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK
83548#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT
83549#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)
83550#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK
83551#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT
83552#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)
83553#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK
83554#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT
83555#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x)
83556#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK
83557#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT
83558#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)
83559#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK
83560#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT
83561#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)
83562#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK
83563#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT
83564#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)
83565#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK
83566#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT
83567#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)
83568#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK
83569#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT
83570#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)
83571#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK
83572#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT
83573#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x)
83574#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK
83575#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT
83576#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)
83577#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK
83578#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT
83579#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)
83580#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK
83581#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT
83582#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)
83583#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK
83584#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT
83585#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)
83586#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK
83587#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT
83588#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)
83589#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK
83590#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT
83591#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)
83592#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK
83593#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT
83594#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)
83595#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK
83596#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT
83597#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)
83598#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK
83599#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT
83600#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)
83601#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK
83602#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT
83603#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)
83604#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK
83605#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT
83606#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)
83607#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK
83608#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT
83609#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)
83610#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK
83611#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT
83612#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)
83613#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK
83614#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT
83615#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)
83616#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK
83617#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT
83618#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)
83619#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK
83620#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT
83621#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)
83622#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK
83623#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT
83624#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)
83625#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK
83626#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
83627#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)
83628#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK
83629#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
83630#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)
83631#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK
83632#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT
83633#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)
83634#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK
83635#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT
83636#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)
83637#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK
83638#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT
83639#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)
83640#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK
83641#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT
83642#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)
83643#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK
83644#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT
83645#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)
83646#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK
83647#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT
83648#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)
83649#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK
83650#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT
83651#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)
83652#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK
83653#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT
83654#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)
83655#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK
83656#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT
83657#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)
83658#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK
83659#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT
83660#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)
83661#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK
83662#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT
83663#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)
83664#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK
83665#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT
83666#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)
83667#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK
83668#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT
83669#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)
83670#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK
83671#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT
83672#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)
83673#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK
83674#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT
83675#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)
83676#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK
83677#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT
83678#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)
83679#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK
83680#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT
83681#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)
83682#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK
83683#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT
83684#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)
83685#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK
83686#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT
83687#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)
83688#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK
83689#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT
83690#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)
83691#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK
83692#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT
83693#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)
83694#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK
83695#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT
83696#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)
83697#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK
83698#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT
83699#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)
83700#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK
83701#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT
83702#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)
83703#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK
83704#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT
83705#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)
83706#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK
83707#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT
83708#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)
83709#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK
83710#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT
83711#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)
83712#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK
83713#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT
83714#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)
83715#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK
83716#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT
83717#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)
83718#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK
83719#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT
83720#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)
83721#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK
83722#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT
83723#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x)
83724#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK
83725#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT
83726#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x)
83727#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK
83728#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT
83729#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x)
83730#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK
83731#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT
83732#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x)
83733#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK
83734#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT
83735#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)
83736#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK
83737#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT
83738#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x)
83739#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK
83740#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT
83741#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)
83742#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK
83743#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT
83744#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)
83745#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK
83746#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT
83747#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)
83748#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK
83749#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT
83750#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)
83751#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK
83752#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT
83753#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)
83754#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK
83755#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT
83756#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)
83757#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK
83758#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT
83759#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)
83760#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK
83761#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT
83762#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)
83763#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK
83764#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT
83765#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)
83766#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK
83767#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT
83768#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)
83769#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK
83770#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT
83771#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)
83772#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK
83773#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT
83774#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)
83775#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK
83776#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT
83777#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)
83778#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK
83779#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT
83780#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)
83781#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK
83782#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT
83783#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)
83784#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK
83785#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT
83786#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)
83787#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK
83788#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT
83789#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)
83790#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK
83791#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT
83792#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)
83793#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK
83794#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT
83795#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)
83796#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK
83797#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT
83798#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)
83799#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK
83800#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT
83801#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x)
83802#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK
83803#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT
83804#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x)
83805#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK
83806#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT
83807#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)
83808#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK
83809#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT
83810#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)
83811#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
83812#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
83813#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
83814#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK
83815#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT
83816#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)
83817#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK
83818#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT
83819#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)
83820#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK
83821#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT
83822#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)
83823#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK
83824#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT
83825#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)
83826#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK
83827#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT
83828#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)
83829#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK
83830#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT
83831#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)
83832#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK
83833#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT
83834#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)
83835#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK
83836#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT
83837#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)
83838#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK
83839#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT
83840#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)
83841#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK
83842#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT
83843#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)
83844#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK
83845#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT
83846#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)
83847#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK
83848#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT
83849#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)
83850#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK
83851#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT
83852#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)
83853#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK
83854#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT
83855#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)
83856#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK
83857#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT
83858#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)
83859#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK
83860#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT
83861#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)
83862#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK
83863#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT
83864#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)
83865#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK
83866#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT
83867#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)
83868#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK
83869#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT
83870#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)
83871#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK
83872#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT
83873#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)
83874#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK
83875#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT
83876#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)
83877#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK
83878#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT
83879#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)
83880#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK
83881#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT
83882#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)
83883#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK
83884#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT
83885#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)
83886#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK
83887#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT
83888#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)
83889#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK
83890#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT
83891#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)
83892#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT
83893#define USBHS_Type USB_Type
83894#define USBHS_BASE_ADDRS USB_BASE_ADDRS
83895#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn }
83896#define USBHS_IRQHandler USB_OTG1_IRQHandler
83897#define USBHS_STACK_BASE_ADDRS { USB_OTG1_BASE, USB_OTG2_BASE }
83898
83899 /* end of group USB_Peripheral_Access_Layer */
83903
83904
83905/* ----------------------------------------------------------------------------
83906 -- USBHSDCD Peripheral Access Layer
83907 ---------------------------------------------------------------------------- */
83908
83915typedef struct {
83916 __IO uint32_t CONTROL;
83917 __IO uint32_t CLOCK;
83918 __I uint32_t STATUS;
83919 __IO uint32_t SIGNAL_OVERRIDE;
83920 __IO uint32_t TIMER0;
83921 __IO uint32_t TIMER1;
83922 union { /* offset: 0x18 */
83925 };
83927
83928/* ----------------------------------------------------------------------------
83929 -- USBHSDCD Register Masks
83930 ---------------------------------------------------------------------------- */
83931
83940#define USBHSDCD_CONTROL_IACK_MASK (0x1U)
83941#define USBHSDCD_CONTROL_IACK_SHIFT (0U)
83946#define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
83947
83948#define USBHSDCD_CONTROL_IF_MASK (0x100U)
83949#define USBHSDCD_CONTROL_IF_SHIFT (8U)
83954#define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
83955
83956#define USBHSDCD_CONTROL_IE_MASK (0x10000U)
83957#define USBHSDCD_CONTROL_IE_SHIFT (16U)
83962#define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
83963
83964#define USBHSDCD_CONTROL_BC12_MASK (0x20000U)
83965#define USBHSDCD_CONTROL_BC12_SHIFT (17U)
83970#define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
83971
83972#define USBHSDCD_CONTROL_START_MASK (0x1000000U)
83973#define USBHSDCD_CONTROL_START_SHIFT (24U)
83978#define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
83979
83980#define USBHSDCD_CONTROL_SR_MASK (0x2000000U)
83981#define USBHSDCD_CONTROL_SR_SHIFT (25U)
83986#define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
83992#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
83993#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
83998#define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
83999
84000#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
84001#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
84004#define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
84010#define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U)
84011#define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U)
84020#define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
84021
84022#define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
84023#define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U)
84030#define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
84031
84032#define USBHSDCD_STATUS_ERR_MASK (0x100000U)
84033#define USBHSDCD_STATUS_ERR_SHIFT (20U)
84038#define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
84039
84040#define USBHSDCD_STATUS_TO_MASK (0x200000U)
84041#define USBHSDCD_STATUS_TO_SHIFT (21U)
84046#define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
84047
84048#define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U)
84049#define USBHSDCD_STATUS_ACTIVE_SHIFT (22U)
84054#define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
84060#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
84061#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
84069#define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
84075#define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU)
84076#define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U)
84079#define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
84080
84081#define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
84082#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
84086#define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
84092#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
84093#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
84097#define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
84098
84099#define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
84100#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
84104#define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
84110#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
84111#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
84115#define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
84116
84117#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
84118#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
84122#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
84128#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
84129#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
84133#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
84134
84135#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
84136#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
84140#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) /* end of group USBHSDCD_Register_Masks */
84147
84148
84149/* USBHSDCD - Peripheral instance base addresses */
84151#define USBHSDCD1_BASE (0x40434800u)
84153#define USBHSDCD1 ((USBHSDCD_Type *)USBHSDCD1_BASE)
84155#define USBHSDCD2_BASE (0x40438800u)
84157#define USBHSDCD2 ((USBHSDCD_Type *)USBHSDCD2_BASE)
84159#define USBHSDCD_BASE_ADDRS { 0u, USBHSDCD1_BASE, USBHSDCD2_BASE }
84161#define USBHSDCD_BASE_PTRS { (USBHSDCD_Type *)0u, USBHSDCD1, USBHSDCD2 }
84162/* Backward compatibility */
84163#define USBHSDCD_STACK_BASE_ADDRS { USBHSDCD1_BASE, USBHSDCD2_BASE }
84164
84165 /* end of group USBHSDCD_Peripheral_Access_Layer */
84169
84170
84171/* ----------------------------------------------------------------------------
84172 -- USBNC Peripheral Access Layer
84173 ---------------------------------------------------------------------------- */
84174
84181typedef struct {
84182 __IO uint32_t CTRL1;
84183 __IO uint32_t CTRL2;
84184 uint8_t RESERVED_0[8];
84185 __IO uint32_t HSIC_CTRL;
84186} USBNC_Type;
84187
84188/* ----------------------------------------------------------------------------
84189 -- USBNC Register Masks
84190 ---------------------------------------------------------------------------- */
84191
84200#define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U)
84201#define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U)
84206#define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)
84207
84208#define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U)
84209#define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U)
84214#define USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)
84215
84216#define USBNC_CTRL1_PWR_POL_MASK (0x200U)
84217#define USBNC_CTRL1_PWR_POL_SHIFT (9U)
84222#define USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)
84223
84224#define USBNC_CTRL1_WIE_MASK (0x400U)
84225#define USBNC_CTRL1_WIE_SHIFT (10U)
84230#define USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)
84231
84232#define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U)
84233#define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U)
84238#define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)
84239
84240#define USBNC_CTRL1_WKUP_SW_MASK (0x8000U)
84241#define USBNC_CTRL1_WKUP_SW_SHIFT (15U)
84246#define USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)
84247
84248#define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U)
84249#define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U)
84254#define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK)
84255
84256#define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U)
84257#define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U)
84262#define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)
84263
84264#define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U)
84265#define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U)
84270#define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)
84271
84272#define USBNC_CTRL1_WIR_MASK (0x80000000U)
84273#define USBNC_CTRL1_WIR_SHIFT (31U)
84278#define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)
84284#define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U)
84285#define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U)
84292#define USBNC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)
84293
84294#define USBNC_CTRL2_AUTURESUME_EN_MASK (0x4U)
84295#define USBNC_CTRL2_AUTURESUME_EN_SHIFT (2U)
84299#define USBNC_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK)
84300
84301#define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U)
84302#define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U)
84306#define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK)
84307
84308#define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U)
84309#define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U)
84313#define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)
84319#define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK (0x800U)
84320#define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT (11U)
84325#define USBNC_HSIC_CTRL_HSIC_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK)
84326
84327#define USBNC_HSIC_CTRL_HSIC_EN_MASK (0x1000U)
84328#define USBNC_HSIC_CTRL_HSIC_EN_SHIFT (12U)
84333#define USBNC_HSIC_CTRL_HSIC_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK)
84334
84335#define USBNC_HSIC_CTRL_CLK_VLD_MASK (0x80000000U)
84336#define USBNC_HSIC_CTRL_CLK_VLD_SHIFT (31U)
84341#define USBNC_HSIC_CTRL_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK) /* end of group USBNC_Register_Masks */
84348
84349
84350/* USBNC - Peripheral instance base addresses */
84352#define USBNC_OTG1_BASE (0x40430200u)
84354#define USBNC_OTG1 ((USBNC_Type *)USBNC_OTG1_BASE)
84356#define USBNC_OTG2_BASE (0x4042C200u)
84358#define USBNC_OTG2 ((USBNC_Type *)USBNC_OTG2_BASE)
84360#define USBNC_BASE_ADDRS { 0u, USBNC_OTG1_BASE, USBNC_OTG2_BASE }
84362#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC_OTG1, USBNC_OTG2 }
84363/* Backward compatibility */
84364#define USB_OTGn_CTRL CTRL1
84365#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK USBNC_CTRL1_OVER_CUR_DIS_MASK
84366#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT USBNC_CTRL1_OVER_CUR_DIS_SHIFT
84367#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) USBNC_CTRL1_OVER_CUR_DIS(x)
84368#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK USBNC_CTRL1_OVER_CUR_POL_MASK
84369#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT USBNC_CTRL1_OVER_CUR_POL_SHIFT
84370#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) USBNC_CTRL1_OVER_CUR_POL(x)
84371#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK USBNC_CTRL1_PWR_POL_MASK
84372#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT USBNC_CTRL1_PWR_POL_SHIFT
84373#define USBNC_USB_OTGn_CTRL_PWR_POL(x) USBNC_CTRL1_PWR_POL(x)
84374#define USBNC_USB_OTGn_CTRL_WIE_MASK USBNC_CTRL1_WIE_MASK
84375#define USBNC_USB_OTGn_CTRL_WIE_SHIFT USBNC_CTRL1_WIE_SHIFT
84376#define USBNC_USB_OTGn_CTRL_WIE(x) USBNC_CTRL1_WIE(x)
84377#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK USBNC_CTRL1_WKUP_SW_EN_MASK
84378#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT USBNC_CTRL1_WKUP_SW_EN_SHIFT
84379#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) USBNC_CTRL1_WKUP_SW_EN(x)
84380#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK USBNC_CTRL1_WKUP_SW_MASK
84381#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT USBNC_CTRL1_WKUP_SW_SHIFT
84382#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) USBNC_CTRL1_WKUP_SW(x)
84383#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK USBNC_CTRL1_WKUP_ID_EN_MASK
84384#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT USBNC_CTRL1_WKUP_ID_EN_SHIFT
84385#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) USBNC_CTRL1_WKUP_ID_EN(x)
84386#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK USBNC_CTRL1_WKUP_VBUS_EN_MASK
84387#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT USBNC_CTRL1_WKUP_VBUS_EN_SHIFT
84388#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) USBNC_CTRL1_WKUP_VBUS_EN(x)
84389#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK USBNC_CTRL1_WKUP_DPDM_EN_MASK
84390#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT USBNC_CTRL1_WKUP_DPDM_EN_SHIFT
84391#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) USBNC_CTRL1_WKUP_DPDM_EN(x)
84392#define USBNC_USB_OTGn_CTRL_WIR_MASK USBNC_CTRL1_WIR_MASK
84393#define USBNC_USB_OTGn_CTRL_WIR_SHIFT USBNC_CTRL1_WIR_SHIFT
84394#define USBNC_USB_OTGn_CTRL_WIR(x) USBNC_CTRL1_WIR(x)
84395#define USBNC_STACK_BASE_ADDRS { USBNC_OTG1_BASE, USBNC_OTG2_BASE }
84396
84397 /* end of group USBNC_Peripheral_Access_Layer */
84401
84402
84403/* ----------------------------------------------------------------------------
84404 -- USBPHY Peripheral Access Layer
84405 ---------------------------------------------------------------------------- */
84406
84413typedef struct {
84414 __IO uint32_t PWD;
84415 __IO uint32_t PWD_SET;
84416 __IO uint32_t PWD_CLR;
84417 __IO uint32_t PWD_TOG;
84418 __IO uint32_t TX;
84419 __IO uint32_t TX_SET;
84420 __IO uint32_t TX_CLR;
84421 __IO uint32_t TX_TOG;
84422 __IO uint32_t RX;
84423 __IO uint32_t RX_SET;
84424 __IO uint32_t RX_CLR;
84425 __IO uint32_t RX_TOG;
84426 __IO uint32_t CTRL;
84427 __IO uint32_t CTRL_SET;
84428 __IO uint32_t CTRL_CLR;
84429 __IO uint32_t CTRL_TOG;
84430 __IO uint32_t STATUS;
84431 uint8_t RESERVED_0[12];
84432 __IO uint32_t DEBUGr;
84433 __IO uint32_t DEBUG_SET;
84434 __IO uint32_t DEBUG_CLR;
84435 __IO uint32_t DEBUG_TOG;
84436 __I uint32_t DEBUG0_STATUS;
84437 uint8_t RESERVED_1[12];
84438 __IO uint32_t DEBUG1;
84439 __IO uint32_t DEBUG1_SET;
84440 __IO uint32_t DEBUG1_CLR;
84441 __IO uint32_t DEBUG1_TOG;
84442 __I uint32_t VERSION;
84443 uint8_t RESERVED_2[28];
84444 __IO uint32_t PLL_SIC;
84445 __IO uint32_t PLL_SIC_SET;
84446 __IO uint32_t PLL_SIC_CLR;
84447 __IO uint32_t PLL_SIC_TOG;
84448 uint8_t RESERVED_3[16];
84449 __IO uint32_t USB1_VBUS_DETECT;
84450 __IO uint32_t USB1_VBUS_DETECT_SET;
84451 __IO uint32_t USB1_VBUS_DETECT_CLR;
84452 __IO uint32_t USB1_VBUS_DETECT_TOG;
84453 __I uint32_t USB1_VBUS_DET_STAT;
84454 uint8_t RESERVED_4[12];
84455 __IO uint32_t USB1_CHRG_DETECT;
84456 __IO uint32_t USB1_CHRG_DETECT_SET;
84457 __IO uint32_t USB1_CHRG_DETECT_CLR;
84458 __IO uint32_t USB1_CHRG_DETECT_TOG;
84459 __I uint32_t USB1_CHRG_DET_STAT;
84460 uint8_t RESERVED_5[12];
84461 __IO uint32_t ANACTRL;
84462 __IO uint32_t ANACTRL_SET;
84463 __IO uint32_t ANACTRL_CLR;
84464 __IO uint32_t ANACTRL_TOG;
84465 __IO uint32_t USB1_LOOPBACK;
84466 __IO uint32_t USB1_LOOPBACK_SET;
84467 __IO uint32_t USB1_LOOPBACK_CLR;
84468 __IO uint32_t USB1_LOOPBACK_TOG;
84469 __IO uint32_t USB1_LOOPBACK_HSFSCNT;
84470 __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET;
84471 __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR;
84472 __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG;
84473 __IO uint32_t TRIM_OVERRIDE_EN;
84474 __IO uint32_t TRIM_OVERRIDE_EN_SET;
84475 __IO uint32_t TRIM_OVERRIDE_EN_CLR;
84476 __IO uint32_t TRIM_OVERRIDE_EN_TOG;
84477} USBPHY_Type;
84478
84479/* ----------------------------------------------------------------------------
84480 -- USBPHY Register Masks
84481 ---------------------------------------------------------------------------- */
84482
84491#define USBPHY_PWD_TXPWDFS_MASK (0x400U)
84492#define USBPHY_PWD_TXPWDFS_SHIFT (10U)
84497#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
84498
84499#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
84500#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
84506#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
84507
84508#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
84509#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
84514#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
84515
84516#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
84517#define USBPHY_PWD_RXPWDENV_SHIFT (17U)
84522#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
84523
84524#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
84525#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
84530#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
84531
84532#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
84533#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
84538#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
84539
84540#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
84541#define USBPHY_PWD_RXPWDRX_SHIFT (20U)
84546#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
84552#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
84553#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
84556#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
84557
84558#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
84559#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
84562#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
84563
84564#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
84565#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
84568#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
84569
84570#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
84571#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
84574#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
84575
84576#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
84577#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
84580#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
84581
84582#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
84583#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
84586#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
84587
84588#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
84589#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
84592#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
84598#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
84599#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
84602#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
84603
84604#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
84605#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
84608#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
84609
84610#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
84611#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
84614#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
84615
84616#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
84617#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
84620#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
84621
84622#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
84623#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
84626#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
84627
84628#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
84629#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
84632#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
84633
84634#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
84635#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
84638#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
84644#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
84645#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
84648#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
84649
84650#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
84651#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
84654#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
84655
84656#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
84657#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
84660#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
84661
84662#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
84663#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
84666#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
84667
84668#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
84669#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
84672#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
84673
84674#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
84675#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
84678#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
84679
84680#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
84681#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
84684#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
84690#define USBPHY_TX_D_CAL_MASK (0xFU)
84691#define USBPHY_TX_D_CAL_SHIFT (0U)
84697#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
84698
84699#define USBPHY_TX_TXCAL45DN_MASK (0xF00U)
84700#define USBPHY_TX_TXCAL45DN_SHIFT (8U)
84703#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
84704
84705#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
84706#define USBPHY_TX_TXCAL45DP_SHIFT (16U)
84709#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
84715#define USBPHY_TX_SET_D_CAL_MASK (0xFU)
84716#define USBPHY_TX_SET_D_CAL_SHIFT (0U)
84719#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
84720
84721#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)
84722#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)
84725#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
84726
84727#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
84728#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
84731#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
84737#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
84738#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
84741#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
84742
84743#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)
84744#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)
84747#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
84748
84749#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
84750#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
84753#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
84759#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
84760#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
84763#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
84764
84765#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)
84766#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)
84769#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
84770
84771#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
84772#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
84775#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
84781#define USBPHY_RX_ENVADJ_MASK (0x7U)
84782#define USBPHY_RX_ENVADJ_SHIFT (0U)
84790#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
84791
84792#define USBPHY_RX_DISCONADJ_MASK (0x70U)
84793#define USBPHY_RX_DISCONADJ_SHIFT (4U)
84801#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
84802
84803#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
84804#define USBPHY_RX_RXDBYPASS_SHIFT (22U)
84809#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
84815#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
84816#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
84819#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
84820
84821#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
84822#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
84825#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
84826
84827#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
84828#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
84831#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
84837#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
84838#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
84841#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
84842
84843#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
84844#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
84847#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
84848
84849#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
84850#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
84853#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
84859#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
84860#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
84863#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
84864
84865#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
84866#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
84869#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
84870
84871#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
84872#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
84875#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
84881#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)
84882#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)
84885#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
84886
84887#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
84888#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
84891#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
84892
84893#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)
84894#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)
84897#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
84898
84899#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
84900#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
84903#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
84904
84905#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)
84906#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)
84911#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
84912
84913#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)
84914#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)
84917#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
84918
84919#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)
84920#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)
84923#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
84924
84925#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)
84926#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)
84929#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
84930
84931#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)
84932#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)
84935#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
84936
84937#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)
84938#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)
84941#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
84942
84943#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)
84944#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)
84947#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
84948
84949#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)
84950#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)
84953#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
84954
84955#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
84956#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
84959#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
84960
84961#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
84962#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
84965#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
84966
84967#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
84968#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
84971#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
84972
84973#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)
84974#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)
84977#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
84978
84979#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)
84980#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)
84983#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
84984
84985#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U)
84986#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U)
84989#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
84990
84991#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
84992#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
84995#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
84996
84997#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
84998#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
85001#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
85002
85003#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)
85004#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)
85007#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
85008
85009#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)
85010#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)
85013#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
85014
85015#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)
85016#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)
85019#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
85020
85021#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
85022#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
85025#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
85026
85027#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
85028#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
85031#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
85032
85033#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
85034#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
85037#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
85038
85039#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
85040#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
85043#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
85044
85045#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
85046#define USBPHY_CTRL_CLKGATE_SHIFT (30U)
85049#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
85050
85051#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
85052#define USBPHY_CTRL_SFTRST_SHIFT (31U)
85055#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
85061#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)
85062#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)
85065#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
85066
85067#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
85068#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
85071#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
85072
85073#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)
85074#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)
85077#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
85078
85079#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
85080#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
85083#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
85084
85085#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)
85086#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)
85089#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
85090
85091#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)
85092#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
85095#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
85096
85097#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)
85098#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)
85101#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
85102
85103#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)
85104#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)
85107#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
85108
85109#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)
85110#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)
85113#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
85114
85115#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)
85116#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)
85119#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
85120
85121#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)
85122#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)
85125#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
85126
85127#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)
85128#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)
85131#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
85132
85133#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
85134#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
85137#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
85138
85139#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
85140#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
85143#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
85144
85145#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
85146#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
85149#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
85150
85151#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)
85152#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)
85155#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
85156
85157#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)
85158#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)
85161#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
85162
85163#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U)
85164#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U)
85167#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
85168
85169#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
85170#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
85173#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
85174
85175#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
85176#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
85179#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
85180
85181#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)
85182#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)
85185#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
85186
85187#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)
85188#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)
85191#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
85192
85193#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)
85194#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)
85197#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
85198
85199#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
85200#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
85203#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
85204
85205#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
85206#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
85209#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
85210
85211#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
85212#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
85215#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
85216
85217#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
85218#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
85221#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
85222
85223#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
85224#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
85227#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
85228
85229#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
85230#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
85233#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
85239#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)
85240#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)
85243#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
85244
85245#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
85246#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
85249#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
85250
85251#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)
85252#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)
85255#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
85256
85257#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
85258#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
85261#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
85262
85263#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)
85264#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)
85267#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
85268
85269#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)
85270#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
85273#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
85274
85275#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)
85276#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)
85279#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
85280
85281#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)
85282#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)
85285#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
85286
85287#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)
85288#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)
85291#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
85292
85293#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)
85294#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)
85297#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
85298
85299#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)
85300#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)
85303#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
85304
85305#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)
85306#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)
85309#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
85310
85311#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
85312#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
85315#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
85316
85317#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
85318#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
85321#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
85322
85323#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
85324#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
85327#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
85328
85329#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)
85330#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)
85333#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
85334
85335#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)
85336#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)
85339#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
85340
85341#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U)
85342#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U)
85345#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
85346
85347#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
85348#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
85351#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
85352
85353#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
85354#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
85357#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
85358
85359#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)
85360#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)
85363#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
85364
85365#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)
85366#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)
85369#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
85370
85371#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)
85372#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)
85375#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
85376
85377#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
85378#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
85381#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
85382
85383#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
85384#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
85387#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
85388
85389#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
85390#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
85393#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
85394
85395#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
85396#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
85399#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
85400
85401#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
85402#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
85405#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
85406
85407#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
85408#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
85411#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
85417#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)
85418#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)
85421#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
85422
85423#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
85424#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
85427#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
85428
85429#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)
85430#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)
85433#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
85434
85435#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
85436#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
85439#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
85440
85441#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)
85442#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)
85445#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
85446
85447#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)
85448#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
85451#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
85452
85453#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)
85454#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)
85457#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
85458
85459#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)
85460#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)
85463#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
85464
85465#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)
85466#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)
85469#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
85470
85471#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)
85472#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)
85475#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
85476
85477#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)
85478#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)
85481#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
85482
85483#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)
85484#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)
85487#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
85488
85489#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
85490#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
85493#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
85494
85495#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
85496#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
85499#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
85500
85501#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
85502#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
85505#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
85506
85507#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)
85508#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)
85511#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
85512
85513#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)
85514#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)
85517#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
85518
85519#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U)
85520#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U)
85523#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
85524
85525#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
85526#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
85529#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
85530
85531#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
85532#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
85535#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
85536
85537#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)
85538#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)
85541#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
85542
85543#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)
85544#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)
85547#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
85548
85549#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)
85550#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)
85553#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
85554
85555#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
85556#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
85559#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
85560
85561#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
85562#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
85565#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
85566
85567#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
85568#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
85571#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
85572
85573#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
85574#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
85577#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
85578
85579#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
85580#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
85583#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
85584
85585#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
85586#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
85589#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
85595#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
85596#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
85601#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
85602
85603#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
85604#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
85609#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
85610
85611#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
85612#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
85615#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
85616
85617#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
85618#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
85621#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
85627#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
85628#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
85631#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
85632
85633#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
85634#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
85637#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
85638
85639#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
85640#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
85643#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
85644
85645#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
85646#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
85649#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
85650
85651#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
85652#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
85655#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
85656
85657#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
85658#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
85661#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
85662
85663#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
85664#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
85667#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
85668
85669#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
85670#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
85673#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
85674
85675#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
85676#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
85679#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
85680
85681#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
85682#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
85685#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
85686
85687#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
85688#define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
85691#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
85697#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
85698#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
85701#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
85702
85703#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
85704#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
85707#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
85708
85709#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
85710#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
85713#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
85714
85715#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
85716#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
85719#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
85720
85721#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
85722#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
85725#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
85726
85727#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
85728#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
85731#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
85732
85733#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
85734#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
85737#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
85738
85739#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
85740#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
85743#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
85744
85745#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
85746#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
85749#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
85750
85751#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
85752#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
85755#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
85756
85757#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
85758#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
85761#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
85767#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
85768#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
85771#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
85772
85773#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
85774#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
85777#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
85778
85779#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
85780#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
85783#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
85784
85785#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
85786#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
85789#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
85790
85791#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
85792#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
85795#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
85796
85797#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
85798#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
85801#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
85802
85803#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
85804#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
85807#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
85808
85809#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
85810#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
85813#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
85814
85815#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
85816#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
85819#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
85820
85821#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
85822#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
85825#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
85826
85827#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
85828#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
85831#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
85837#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
85838#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
85841#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
85842
85843#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
85844#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
85847#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
85848
85849#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
85850#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
85853#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
85854
85855#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
85856#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
85859#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
85860
85861#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
85862#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
85865#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
85866
85867#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
85868#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
85871#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
85872
85873#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
85874#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
85877#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
85878
85879#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
85880#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
85883#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
85884
85885#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
85886#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
85889#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
85890
85891#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
85892#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
85895#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
85896
85897#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
85898#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
85901#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
85907#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
85908#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
85911#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
85912
85913#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
85914#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
85917#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
85918
85919#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
85920#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
85923#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
85929#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
85930#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
85937#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
85938
85939#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
85940#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
85943#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK)
85944
85945#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
85946#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
85949#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK)
85950
85951#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
85952#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT (17U)
85955#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK)
85956
85957#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
85958#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U)
85961#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK)
85962
85963#define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U)
85964#define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U)
85967#define USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK)
85973#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
85974#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
85977#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
85978
85979#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
85980#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
85983#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK)
85984
85985#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
85986#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
85989#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK)
85990
85991#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
85992#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT (17U)
85995#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK)
85996
85997#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
85998#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U)
86001#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK)
86002
86003#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U)
86004#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U)
86007#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK)
86013#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
86014#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
86017#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
86018
86019#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
86020#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
86023#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK)
86024
86025#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
86026#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
86029#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK)
86030
86031#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
86032#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT (17U)
86035#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK)
86036
86037#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
86038#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U)
86041#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK)
86042
86043#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U)
86044#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U)
86047#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK)
86053#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
86054#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
86057#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
86058
86059#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
86060#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
86063#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK)
86064
86065#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
86066#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
86069#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK)
86070
86071#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
86072#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT (17U)
86075#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK)
86076
86077#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
86078#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U)
86081#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK)
86082
86083#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U)
86084#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U)
86087#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK)
86093#define USBPHY_VERSION_STEP_MASK (0xFFFFU)
86094#define USBPHY_VERSION_STEP_SHIFT (0U)
86097#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
86098
86099#define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
86100#define USBPHY_VERSION_MINOR_SHIFT (16U)
86103#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
86104
86105#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
86106#define USBPHY_VERSION_MAJOR_SHIFT (24U)
86109#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
86115#define USBPHY_PLL_SIC_PLL_POSTDIV_MASK (0x1CU)
86116#define USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT (2U)
86119#define USBPHY_PLL_SIC_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_POSTDIV_MASK)
86120
86121#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U)
86122#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U)
86125#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
86126
86127#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U)
86128#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U)
86131#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
86132
86133#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U)
86134#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U)
86137#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
86138
86139#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U)
86140#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U)
86143#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
86144
86145#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U)
86146#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U)
86151#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)
86152
86153#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U)
86154#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U)
86157#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)
86158
86159#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U)
86160#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U)
86163#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)
86164
86165#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U)
86166#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U)
86177#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
86178
86179#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U)
86180#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U)
86185#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
86191#define USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK (0x1CU)
86192#define USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT (2U)
86195#define USBPHY_PLL_SIC_SET_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK)
86196
86197#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U)
86198#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
86201#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
86202
86203#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U)
86204#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U)
86207#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
86208
86209#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U)
86210#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U)
86213#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
86214
86215#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U)
86216#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U)
86219#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
86220
86221#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U)
86222#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)
86225#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)
86226
86227#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U)
86228#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U)
86231#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)
86232
86233#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U)
86234#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U)
86237#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)
86238
86239#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U)
86240#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U)
86243#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
86244
86245#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U)
86246#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U)
86249#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
86255#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK (0x1CU)
86256#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT (2U)
86259#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK)
86260
86261#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U)
86262#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
86265#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
86266
86267#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U)
86268#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U)
86271#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
86272
86273#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U)
86274#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U)
86277#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
86278
86279#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U)
86280#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U)
86283#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
86284
86285#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U)
86286#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)
86289#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)
86290
86291#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U)
86292#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U)
86295#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)
86296
86297#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U)
86298#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U)
86301#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)
86302
86303#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U)
86304#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U)
86307#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
86308
86309#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U)
86310#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U)
86313#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
86319#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK (0x1CU)
86320#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT (2U)
86323#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK)
86324
86325#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U)
86326#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
86329#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
86330
86331#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U)
86332#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U)
86335#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
86336
86337#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U)
86338#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U)
86341#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
86342
86343#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U)
86344#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U)
86347#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
86348
86349#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U)
86350#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)
86353#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)
86354
86355#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U)
86356#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U)
86359#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)
86360
86361#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U)
86362#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U)
86365#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)
86366
86367#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U)
86368#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U)
86371#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
86372
86373#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U)
86374#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U)
86377#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
86383#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
86384#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
86395#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
86396
86397#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
86398#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
86403#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
86404
86405#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
86406#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
86409#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
86410
86411#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
86412#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
86415#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
86416
86417#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
86418#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
86421#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
86422
86423#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
86424#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
86427#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
86428
86429#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
86430#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
86435#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
86436
86437#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
86438#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
86445#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
86446
86447#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U)
86448#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U)
86451#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK)
86452
86453#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U)
86454#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U)
86457#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK)
86458
86459#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
86460#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
86465#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
86466
86467#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U)
86468#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
86474#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
86475
86476#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
86477#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
86482#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
86483
86484#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
86485#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
86490#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
86496#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
86497#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
86500#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
86501
86502#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
86503#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
86506#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
86507
86508#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
86509#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
86512#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
86513
86514#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
86515#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
86518#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
86519
86520#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
86521#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
86524#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
86525
86526#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
86527#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
86530#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
86531
86532#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
86533#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
86536#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
86537
86538#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
86539#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
86542#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
86543
86544#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U)
86545#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U)
86548#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK)
86549
86550#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U)
86551#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U)
86554#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK)
86555
86556#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
86557#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
86560#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
86561
86562#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U)
86563#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
86566#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
86567
86568#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
86569#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
86572#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
86573
86574#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
86575#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
86578#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
86584#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
86585#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
86588#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
86589
86590#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
86591#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
86594#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
86595
86596#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
86597#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
86600#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
86601
86602#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
86603#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
86606#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
86607
86608#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
86609#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
86612#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
86613
86614#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
86615#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
86618#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
86619
86620#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
86621#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
86624#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
86625
86626#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
86627#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
86630#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
86631
86632#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U)
86633#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U)
86636#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK)
86637
86638#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U)
86639#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U)
86642#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK)
86643
86644#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
86645#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
86648#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
86649
86650#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U)
86651#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
86654#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
86655
86656#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
86657#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
86660#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
86661
86662#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
86663#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
86666#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
86672#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
86673#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
86676#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
86677
86678#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
86679#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
86682#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
86683
86684#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
86685#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
86688#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
86689
86690#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
86691#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
86694#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
86695
86696#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
86697#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
86700#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
86701
86702#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
86703#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
86706#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
86707
86708#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
86709#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
86712#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
86713
86714#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
86715#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
86718#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
86719
86720#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U)
86721#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U)
86724#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK)
86725
86726#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U)
86727#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U)
86730#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK)
86731
86732#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
86733#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
86736#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
86737
86738#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U)
86739#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
86742#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
86743
86744#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
86745#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
86748#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
86749
86750#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
86751#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
86754#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
86760#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U)
86761#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U)
86766#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
86767
86768#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U)
86769#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U)
86774#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
86775
86776#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U)
86777#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U)
86782#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
86783
86784#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
86785#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
86790#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
86791
86792#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
86793#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
86798#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
86804#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U)
86805#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U)
86808#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK)
86809
86810#define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK (0x800000U)
86811#define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT (23U)
86816#define USBPHY_USB1_CHRG_DETECT_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK)
86822#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U)
86823#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U)
86826#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK)
86827
86828#define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK (0x800000U)
86829#define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT (23U)
86832#define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK)
86838#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U)
86839#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U)
86842#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK)
86843
86844#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK (0x800000U)
86845#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT (23U)
86848#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK)
86854#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U)
86855#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U)
86858#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK)
86859
86860#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK (0x800000U)
86861#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT (23U)
86864#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK)
86870#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
86871#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
86876#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
86877
86878#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
86879#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
86884#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
86885
86886#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK (0x4U)
86887#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT (2U)
86892#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK)
86893
86894#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U)
86895#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
86900#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
86901
86902#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
86903#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
86908#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
86914#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U)
86915#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U)
86920#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
86926#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U)
86927#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U)
86930#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
86936#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U)
86937#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U)
86940#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
86946#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U)
86947#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U)
86950#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
86956#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
86957#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
86960#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
86961
86962#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK (0x2U)
86963#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
86966#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
86967
86968#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK (0x4U)
86969#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
86972#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
86973
86974#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
86975#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
86978#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
86979
86980#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
86981#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
86984#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
86985
86986#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK (0x20U)
86987#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT (5U)
86990#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
86991
86992#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK (0x40U)
86993#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT (6U)
86996#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
86997
86998#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK (0x80U)
86999#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
87002#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
87003
87004#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK (0x100U)
87005#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
87008#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
87009
87010#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
87011#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
87014#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
87015
87016#define USBPHY_USB1_LOOPBACK_TSTPKT_MASK (0xFF0000U)
87017#define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT (16U)
87020#define USBPHY_USB1_LOOPBACK_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
87026#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
87027#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
87030#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
87031
87032#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
87033#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
87036#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
87037
87038#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
87039#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
87042#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
87043
87044#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
87045#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
87048#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
87049
87050#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
87051#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
87054#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
87055
87056#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
87057#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
87060#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
87061
87062#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
87063#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
87066#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
87067
87068#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
87069#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
87072#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
87073
87074#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
87075#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
87078#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
87079
87080#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
87081#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
87084#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
87085
87086#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK (0xFF0000U)
87087#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT (16U)
87090#define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
87096#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
87097#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
87100#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
87101
87102#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
87103#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
87106#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
87107
87108#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
87109#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
87112#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
87113
87114#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
87115#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
87118#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
87119
87120#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
87121#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
87124#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
87125
87126#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
87127#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
87130#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
87131
87132#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
87133#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
87136#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
87137
87138#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
87139#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
87142#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
87143
87144#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
87145#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
87148#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
87149
87150#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
87151#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
87154#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
87155
87156#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK (0xFF0000U)
87157#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT (16U)
87160#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
87166#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
87167#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
87170#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
87171
87172#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
87173#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
87176#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
87177
87178#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
87179#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
87182#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
87183
87184#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
87185#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
87188#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
87189
87190#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
87191#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
87194#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
87195
87196#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
87197#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
87200#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
87201
87202#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
87203#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
87206#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
87207
87208#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
87209#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
87212#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
87213
87214#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
87215#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
87218#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
87219
87220#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
87221#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
87224#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
87225
87226#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK (0xFF0000U)
87227#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT (16U)
87230#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
87236#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
87237#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
87240#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
87241
87242#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
87243#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
87246#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
87252#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
87253#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
87256#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
87257
87258#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
87259#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
87262#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
87268#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
87269#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
87272#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
87273
87274#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
87275#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
87278#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
87284#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
87285#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
87288#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
87289
87290#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
87291#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
87294#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
87300#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
87301#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
87304#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)
87305
87306#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
87307#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
87310#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
87311
87312#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
87313#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
87316#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)
87317
87318#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
87319#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
87322#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)
87323
87324#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
87325#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
87328#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK)
87329
87330#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
87331#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
87334#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
87335
87336#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
87337#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
87340#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK)
87341
87342#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
87343#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
87346#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK)
87347
87348#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
87349#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
87352#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK)
87353
87354#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
87355#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
87358#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)
87359
87360#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
87361#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
87364#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
87365
87366#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
87367#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
87370#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)
87371
87372#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
87373#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
87376#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)
87377
87378#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
87379#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
87382#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK)
87388#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
87389#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
87392#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)
87393
87394#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
87395#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
87398#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
87399
87400#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
87401#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
87404#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)
87405
87406#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
87407#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
87410#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)
87411
87412#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
87413#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
87416#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK)
87417
87418#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
87419#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
87422#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
87423
87424#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
87425#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
87428#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK)
87429
87430#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
87431#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
87434#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK)
87435
87436#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
87437#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
87440#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK)
87441
87442#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
87443#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
87446#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)
87447
87448#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
87449#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
87452#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
87453
87454#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
87455#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
87458#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)
87459
87460#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
87461#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
87464#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)
87465
87466#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
87467#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
87470#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK)
87476#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
87477#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
87480#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)
87481
87482#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
87483#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
87486#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
87487
87488#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
87489#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
87492#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)
87493
87494#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
87495#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
87498#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)
87499
87500#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
87501#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
87504#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK)
87505
87506#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
87507#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
87510#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
87511
87512#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
87513#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
87516#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK)
87517
87518#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
87519#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
87522#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK)
87523
87524#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
87525#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
87528#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK)
87529
87530#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
87531#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
87534#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)
87535
87536#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
87537#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
87540#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
87541
87542#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
87543#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
87546#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)
87547
87548#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
87549#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
87552#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)
87553
87554#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
87555#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
87558#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK)
87564#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
87565#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
87568#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)
87569
87570#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
87571#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
87574#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
87575
87576#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
87577#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
87580#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)
87581
87582#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
87583#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
87586#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)
87587
87588#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
87589#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
87592#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK)
87593
87594#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
87595#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
87598#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
87599
87600#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
87601#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
87604#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK)
87605
87606#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
87607#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
87610#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK)
87611
87612#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
87613#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
87616#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK)
87617
87618#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
87619#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
87622#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)
87623
87624#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
87625#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
87628#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
87629
87630#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
87631#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
87634#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)
87635
87636#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
87637#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
87640#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)
87641
87642#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
87643#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
87646#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK) /* end of group USBPHY_Register_Masks */
87653
87654
87655/* USBPHY - Peripheral instance base addresses */
87657#define USBPHY1_BASE (0x40434000u)
87659#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE)
87661#define USBPHY2_BASE (0x40438000u)
87663#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE)
87665#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE }
87667#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
87669#define USBPHY_IRQS { NotAvail_IRQn, USBPHY1_IRQn, USBPHY2_IRQn }
87670/* Backward compatibility */
87671#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
87672#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
87673#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)
87674#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK
87675#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT
87676#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)
87677#define USBPHY_STACK_BASE_ADDRS { USBPHY1_BASE, USBPHY2_BASE }
87678
87679 /* end of group USBPHY_Peripheral_Access_Layer */
87683
87684
87685/* ----------------------------------------------------------------------------
87686 -- USDHC Peripheral Access Layer
87687 ---------------------------------------------------------------------------- */
87688
87695typedef struct {
87696 __IO uint32_t DS_ADDR;
87697 __IO uint32_t BLK_ATT;
87698 __IO uint32_t CMD_ARG;
87699 __IO uint32_t CMD_XFR_TYP;
87700 __I uint32_t CMD_RSP0;
87701 __I uint32_t CMD_RSP1;
87702 __I uint32_t CMD_RSP2;
87703 __I uint32_t CMD_RSP3;
87704 __IO uint32_t DATA_BUFF_ACC_PORT;
87705 __I uint32_t PRES_STATE;
87706 __IO uint32_t PROT_CTRL;
87707 __IO uint32_t SYS_CTRL;
87708 __IO uint32_t INT_STATUS;
87709 __IO uint32_t INT_STATUS_EN;
87710 __IO uint32_t INT_SIGNAL_EN;
87711 __IO uint32_t AUTOCMD12_ERR_STATUS;
87712 __IO uint32_t HOST_CTRL_CAP;
87713 __IO uint32_t WTMK_LVL;
87714 __IO uint32_t MIX_CTRL;
87715 uint8_t RESERVED_0[4];
87716 __O uint32_t FORCE_EVENT;
87717 __I uint32_t ADMA_ERR_STATUS;
87718 __IO uint32_t ADMA_SYS_ADDR;
87719 uint8_t RESERVED_1[4];
87720 __IO uint32_t DLL_CTRL;
87721 __I uint32_t DLL_STATUS;
87722 __IO uint32_t CLK_TUNE_CTRL_STATUS;
87723 uint8_t RESERVED_2[4];
87724 __IO uint32_t STROBE_DLL_CTRL;
87725 __I uint32_t STROBE_DLL_STATUS;
87726 uint8_t RESERVED_3[72];
87727 __IO uint32_t VEND_SPEC;
87728 __IO uint32_t MMC_BOOT;
87729 __IO uint32_t VEND_SPEC2;
87730 __IO uint32_t TUNING_CTRL;
87731} USDHC_Type;
87732
87733/* ----------------------------------------------------------------------------
87734 -- USDHC Register Masks
87735 ---------------------------------------------------------------------------- */
87736
87745#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
87746#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
87749#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
87755#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
87756#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
87768#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
87769
87770#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
87771#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
87778#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
87784#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
87785#define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
87788#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
87794#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
87795#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
87802#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
87803
87804#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
87805#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
87810#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
87811
87812#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
87813#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
87818#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
87819
87820#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
87821#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
87826#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
87827
87828#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
87829#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
87836#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
87837
87838#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
87839#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
87842#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
87848#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
87849#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
87852#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
87858#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
87859#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
87862#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
87868#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
87869#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
87872#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
87878#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
87879#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
87882#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
87888#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
87889#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
87892#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
87898#define USDHC_PRES_STATE_CIHB_MASK (0x1U)
87899#define USDHC_PRES_STATE_CIHB_SHIFT (0U)
87904#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
87905
87906#define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
87907#define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
87912#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
87913
87914#define USDHC_PRES_STATE_DLA_MASK (0x4U)
87915#define USDHC_PRES_STATE_DLA_SHIFT (2U)
87920#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
87921
87922#define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
87923#define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
87928#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
87929
87930#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
87931#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
87936#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
87937
87938#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
87939#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
87944#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
87945
87946#define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
87947#define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
87952#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
87953
87954#define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
87955#define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
87960#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
87961
87962#define USDHC_PRES_STATE_WTA_MASK (0x100U)
87963#define USDHC_PRES_STATE_WTA_SHIFT (8U)
87968#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
87969
87970#define USDHC_PRES_STATE_RTA_MASK (0x200U)
87971#define USDHC_PRES_STATE_RTA_SHIFT (9U)
87976#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
87977
87978#define USDHC_PRES_STATE_BWEN_MASK (0x400U)
87979#define USDHC_PRES_STATE_BWEN_SHIFT (10U)
87984#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
87985
87986#define USDHC_PRES_STATE_BREN_MASK (0x800U)
87987#define USDHC_PRES_STATE_BREN_SHIFT (11U)
87992#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
87993
87994#define USDHC_PRES_STATE_RTR_MASK (0x1000U)
87995#define USDHC_PRES_STATE_RTR_SHIFT (12U)
88000#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
88001
88002#define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
88003#define USDHC_PRES_STATE_TSCD_SHIFT (15U)
88008#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
88009
88010#define USDHC_PRES_STATE_CINST_MASK (0x10000U)
88011#define USDHC_PRES_STATE_CINST_SHIFT (16U)
88016#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
88017
88018#define USDHC_PRES_STATE_CDPL_MASK (0x40000U)
88019#define USDHC_PRES_STATE_CDPL_SHIFT (18U)
88024#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
88025
88026#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
88027#define USDHC_PRES_STATE_WPSPL_SHIFT (19U)
88032#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
88033
88034#define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
88035#define USDHC_PRES_STATE_CLSL_SHIFT (23U)
88038#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
88039
88040#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
88041#define USDHC_PRES_STATE_DLSL_SHIFT (24U)
88052#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
88058#define USDHC_PROT_CTRL_DTW_MASK (0x6U)
88059#define USDHC_PROT_CTRL_DTW_SHIFT (1U)
88066#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
88067
88068#define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
88069#define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
88074#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
88075
88076#define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
88077#define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
88084#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
88085
88086#define USDHC_PROT_CTRL_CDTL_MASK (0x40U)
88087#define USDHC_PROT_CTRL_CDTL_SHIFT (6U)
88092#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
88093
88094#define USDHC_PROT_CTRL_CDSS_MASK (0x80U)
88095#define USDHC_PROT_CTRL_CDSS_SHIFT (7U)
88100#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
88101
88102#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
88103#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
88110#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
88111
88112#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
88113#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
88118#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
88119
88120#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
88121#define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
88126#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
88127
88128#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
88129#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
88134#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
88135
88136#define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
88137#define USDHC_PROT_CTRL_IABG_SHIFT (19U)
88142#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
88143
88144#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
88145#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
88148#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
88149
88150#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
88151#define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
88156#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
88157
88158#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
88159#define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
88164#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
88165
88166#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
88167#define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
88172#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
88173
88174#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
88175#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
88180#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
88186#define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
88187#define USDHC_SYS_CTRL_DVS_SHIFT (4U)
88194#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
88195
88196#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
88197#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
88200#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
88201
88202#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
88203#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
88222#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
88223
88224#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
88225#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
88228#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
88229
88230#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
88231#define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
88236#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
88237
88238#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
88239#define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
88244#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
88245
88246#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
88247#define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
88252#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
88253
88254#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
88255#define USDHC_SYS_CTRL_INITA_SHIFT (27U)
88258#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
88259
88260#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
88261#define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
88264#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
88270#define USDHC_INT_STATUS_CC_MASK (0x1U)
88271#define USDHC_INT_STATUS_CC_SHIFT (0U)
88276#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
88277
88278#define USDHC_INT_STATUS_TC_MASK (0x2U)
88279#define USDHC_INT_STATUS_TC_SHIFT (1U)
88284#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
88285
88286#define USDHC_INT_STATUS_BGE_MASK (0x4U)
88287#define USDHC_INT_STATUS_BGE_SHIFT (2U)
88292#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
88293
88294#define USDHC_INT_STATUS_DINT_MASK (0x8U)
88295#define USDHC_INT_STATUS_DINT_SHIFT (3U)
88300#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
88301
88302#define USDHC_INT_STATUS_BWR_MASK (0x10U)
88303#define USDHC_INT_STATUS_BWR_SHIFT (4U)
88308#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
88309
88310#define USDHC_INT_STATUS_BRR_MASK (0x20U)
88311#define USDHC_INT_STATUS_BRR_SHIFT (5U)
88316#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
88317
88318#define USDHC_INT_STATUS_CINS_MASK (0x40U)
88319#define USDHC_INT_STATUS_CINS_SHIFT (6U)
88324#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
88325
88326#define USDHC_INT_STATUS_CRM_MASK (0x80U)
88327#define USDHC_INT_STATUS_CRM_SHIFT (7U)
88332#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
88333
88334#define USDHC_INT_STATUS_CINT_MASK (0x100U)
88335#define USDHC_INT_STATUS_CINT_SHIFT (8U)
88340#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
88341
88342#define USDHC_INT_STATUS_RTE_MASK (0x1000U)
88343#define USDHC_INT_STATUS_RTE_SHIFT (12U)
88348#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
88349
88350#define USDHC_INT_STATUS_TP_MASK (0x4000U)
88351#define USDHC_INT_STATUS_TP_SHIFT (14U)
88354#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
88355
88356#define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
88357#define USDHC_INT_STATUS_CTOE_SHIFT (16U)
88362#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
88363
88364#define USDHC_INT_STATUS_CCE_MASK (0x20000U)
88365#define USDHC_INT_STATUS_CCE_SHIFT (17U)
88370#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
88371
88372#define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
88373#define USDHC_INT_STATUS_CEBE_SHIFT (18U)
88378#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
88379
88380#define USDHC_INT_STATUS_CIE_MASK (0x80000U)
88381#define USDHC_INT_STATUS_CIE_SHIFT (19U)
88386#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
88387
88388#define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
88389#define USDHC_INT_STATUS_DTOE_SHIFT (20U)
88394#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
88395
88396#define USDHC_INT_STATUS_DCE_MASK (0x200000U)
88397#define USDHC_INT_STATUS_DCE_SHIFT (21U)
88402#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
88403
88404#define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
88405#define USDHC_INT_STATUS_DEBE_SHIFT (22U)
88410#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
88411
88412#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
88413#define USDHC_INT_STATUS_AC12E_SHIFT (24U)
88418#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
88419
88420#define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
88421#define USDHC_INT_STATUS_TNE_SHIFT (26U)
88424#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
88425
88426#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
88427#define USDHC_INT_STATUS_DMAE_SHIFT (28U)
88432#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
88438#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
88439#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
88444#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
88445
88446#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
88447#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
88452#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
88453
88454#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
88455#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
88460#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
88461
88462#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
88463#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
88468#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
88469
88470#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
88471#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
88476#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
88477
88478#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
88479#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
88484#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
88485
88486#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
88487#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
88492#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
88493
88494#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
88495#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
88500#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
88501
88502#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
88503#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
88508#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
88509
88510#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
88511#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
88516#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
88517
88518#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
88519#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
88524#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
88525
88526#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
88527#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
88532#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
88533
88534#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
88535#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
88540#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
88541
88542#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
88543#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
88548#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
88549
88550#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
88551#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
88556#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
88557
88558#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
88559#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
88564#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
88565
88566#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
88567#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
88572#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
88573
88574#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
88575#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
88580#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
88581
88582#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
88583#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
88588#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
88589
88590#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
88591#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
88596#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
88597
88598#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
88599#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
88604#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
88610#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
88611#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
88616#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
88617
88618#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
88619#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
88624#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
88625
88626#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
88627#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
88632#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
88633
88634#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
88635#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
88640#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
88641
88642#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
88643#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
88648#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
88649
88650#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
88651#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
88656#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
88657
88658#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
88659#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
88664#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
88665
88666#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
88667#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
88672#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
88673
88674#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
88675#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
88680#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
88681
88682#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
88683#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
88688#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
88689
88690#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
88691#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
88696#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
88697
88698#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
88699#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
88704#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
88705
88706#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
88707#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
88712#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
88713
88714#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
88715#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
88720#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
88721
88722#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
88723#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
88728#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
88729
88730#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
88731#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
88736#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
88737
88738#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
88739#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
88744#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
88745
88746#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
88747#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
88752#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
88753
88754#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
88755#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
88760#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
88761
88762#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
88763#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
88768#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
88769
88770#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
88771#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
88776#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
88782#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
88783#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
88788#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
88789
88790#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
88791#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
88796#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
88797
88798#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
88799#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
88804#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
88805
88806#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
88807#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
88812#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
88813
88814#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
88815#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
88820#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
88821
88822#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
88823#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
88828#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
88829
88830#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
88831#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
88836#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
88837
88838#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
88839#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
88844#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
88850#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
88851#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
88854#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
88855
88856#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
88857#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
88860#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
88861
88862#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
88863#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
88866#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
88867
88868#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
88869#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
88874#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
88875
88876#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
88877#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
88884#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
88885
88886#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
88887#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
88892#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
88893
88894#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
88895#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
88900#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
88901
88902#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
88903#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
88908#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
88909
88910#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
88911#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
88916#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
88917
88918#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
88919#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
88924#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
88925
88926#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
88927#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
88932#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
88933
88934#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
88935#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
88940#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
88946#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
88947#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
88950#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
88951
88952#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
88953#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
88956#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
88962#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
88963#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
88968#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
88969
88970#define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
88971#define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
88976#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
88977
88978#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
88979#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
88984#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
88985
88986#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
88987#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
88990#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
88991
88992#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
88993#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
88998#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
88999
89000#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
89001#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
89006#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
89007
89008#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
89009#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
89012#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
89013
89014#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
89015#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
89018#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
89019
89020#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
89021#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
89026#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
89027
89028#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
89029#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
89034#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
89035
89036#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
89037#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
89042#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
89043
89044#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
89045#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
89050#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
89051
89052#define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U)
89053#define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U)
89056#define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
89062#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
89063#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
89066#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
89067
89068#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
89069#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
89072#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
89073
89074#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
89075#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
89078#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
89079
89080#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
89081#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
89084#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
89085
89086#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
89087#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
89090#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
89091
89092#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
89093#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
89096#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
89097
89098#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
89099#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
89102#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
89103
89104#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
89105#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
89108#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
89109
89110#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
89111#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
89114#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
89115
89116#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
89117#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
89120#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
89121
89122#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
89123#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
89126#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
89127
89128#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
89129#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
89132#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
89133
89134#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
89135#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
89138#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
89139
89140#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
89141#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
89144#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
89145
89146#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
89147#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
89150#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
89151
89152#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
89153#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
89156#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
89157
89158#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
89159#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
89162#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
89168#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
89169#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
89172#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
89173
89174#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
89175#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
89180#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
89181
89182#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
89183#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
89188#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
89194#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
89195#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
89198#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
89204#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
89205#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
89208#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
89209
89210#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
89211#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
89214#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
89215
89216#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
89217#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
89220#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
89221
89222#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
89223#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
89226#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
89227
89228#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
89229#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
89232#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
89233
89234#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
89235#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
89238#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
89239
89240#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
89241#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
89244#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
89245
89246#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
89247#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
89250#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
89251
89252#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
89253#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
89256#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
89257
89258#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
89259#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
89262#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
89268#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
89269#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
89272#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
89273
89274#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
89275#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
89278#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
89279
89280#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
89281#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
89284#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
89285
89286#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
89287#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
89290#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
89296#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
89297#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
89300#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
89301
89302#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
89303#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
89306#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
89307
89308#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
89309#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
89312#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
89313
89314#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
89315#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
89318#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
89319
89320#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
89321#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
89324#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
89325
89326#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
89327#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
89330#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
89331
89332#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
89333#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
89336#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
89337
89338#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
89339#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
89342#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
89348#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
89349#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
89352#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
89353
89354#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
89355#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
89358#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
89359
89360#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
89361#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
89364#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
89365
89366#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
89367#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
89370#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
89371
89372#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
89373#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
89376#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)
89377
89378#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
89379#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
89382#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
89383
89384#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
89385#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
89388#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
89389
89390#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
89391#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
89394#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
89395
89396#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
89397#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
89400#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
89406#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
89407#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
89410#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
89411
89412#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
89413#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
89416#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
89417
89418#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
89419#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
89422#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
89423
89424#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
89425#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
89428#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
89434#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
89435#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
89440#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
89441
89442#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
89443#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
89448#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
89449
89450#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
89451#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
89456#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
89457
89458#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
89459#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
89464#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
89465
89466#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
89467#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
89472#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
89473
89474#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
89475#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
89480#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
89486#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
89487#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
89500#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
89501
89502#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
89503#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
89508#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
89509
89510#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
89511#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
89516#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
89517
89518#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
89519#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
89524#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
89525
89526#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
89527#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
89530#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
89531
89532#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
89533#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
89538#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
89539
89540#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
89541#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
89544#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
89550#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
89551#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
89556#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
89557
89558#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
89559#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
89562#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
89563
89564#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
89565#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
89568#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
89569
89570#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
89571#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
89576#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
89577
89578#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
89579#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
89582#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
89583
89584#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
89585#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
89588#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
89589
89590#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
89591#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
89596#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
89602#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0x7FU)
89603#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
89606#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
89607
89608#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)
89609#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)
89612#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)
89613
89614#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
89615#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
89618#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
89619
89620#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
89621#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
89624#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
89625
89626#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
89627#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
89630#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
89631
89632#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
89633#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
89636#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) /* end of group USDHC_Register_Masks */
89643
89644
89645/* USDHC - Peripheral instance base addresses */
89647#define USDHC1_BASE (0x40418000u)
89649#define USDHC1 ((USDHC_Type *)USDHC1_BASE)
89651#define USDHC2_BASE (0x4041C000u)
89653#define USDHC2 ((USDHC_Type *)USDHC2_BASE)
89655#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }
89657#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }
89659#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
89660 /* end of group USDHC_Peripheral_Access_Layer */
89664
89665
89666/* ----------------------------------------------------------------------------
89667 -- VIDEO_MUX Peripheral Access Layer
89668 ---------------------------------------------------------------------------- */
89669
89676typedef struct {
89677 struct { /* offset: 0x0 */
89678 __IO uint32_t RW;
89679 __IO uint32_t SET;
89680 __IO uint32_t CLR;
89681 __IO uint32_t TOG;
89682 } VID_MUX_CTRL;
89683 uint8_t RESERVED_0[16];
89684 struct { /* offset: 0x20 */
89685 __IO uint32_t RW;
89686 __IO uint32_t SET;
89687 __IO uint32_t CLR;
89688 __IO uint32_t TOG;
89689 } PLM_CTRL;
89690 struct { /* offset: 0x30 */
89691 __IO uint32_t RW;
89692 __IO uint32_t SET;
89693 __IO uint32_t CLR;
89694 __IO uint32_t TOG;
89695 } YUV420_CTRL;
89696 uint8_t RESERVED_1[16];
89697 struct { /* offset: 0x50 */
89698 __IO uint32_t RW;
89699 __IO uint32_t SET;
89700 __IO uint32_t CLR;
89701 __IO uint32_t TOG;
89702 } CFG_DT_DISABLE;
89703 uint8_t RESERVED_2[16];
89704 struct { /* offset: 0x70 */
89705 __IO uint32_t RW;
89706 __IO uint32_t SET;
89707 __IO uint32_t CLR;
89708 __IO uint32_t TOG;
89709 } MIPI_DSI_CTRL;
89711
89712/* ----------------------------------------------------------------------------
89713 -- VIDEO_MUX Register Masks
89714 ---------------------------------------------------------------------------- */
89715
89724#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK (0x1U)
89725#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT (0U)
89730#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK)
89731
89732#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK (0x2U)
89733#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT (1U)
89738#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK)
89739
89740#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK (0x4U)
89741#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT (2U)
89746#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK)
89747
89748#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK (0x8U)
89749#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT (3U)
89754#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK)
89760#define VIDEO_MUX_PLM_CTRL_ENABLE_MASK (0x1U)
89761#define VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT (0U)
89766#define VIDEO_MUX_PLM_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT)) & VIDEO_MUX_PLM_CTRL_ENABLE_MASK)
89767
89768#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK (0x2U)
89769#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT (1U)
89774#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK)
89775
89776#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK (0x4U)
89777#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT (2U)
89782#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK)
89783
89784#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK (0x8U)
89785#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT (3U)
89790#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK)
89791
89792#define VIDEO_MUX_PLM_CTRL_POLARITY_MASK (0x10U)
89793#define VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT (4U)
89798#define VIDEO_MUX_PLM_CTRL_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT)) & VIDEO_MUX_PLM_CTRL_POLARITY_MASK)
89804#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK (0x1U)
89805#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT (0U)
89810#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT)) & VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK)
89816#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK (0xFFFFFFU)
89817#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT (0U)
89820#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT)) & VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK)
89826#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK (0x1U)
89827#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT (0U)
89832#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK)
89833
89834#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK (0x2U)
89835#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT (1U)
89840#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK) /* end of group VIDEO_MUX_Register_Masks */
89847
89848
89849/* VIDEO_MUX - Peripheral instance base addresses */
89851#define VIDEO_MUX_BASE (0x40818000u)
89853#define VIDEO_MUX ((VIDEO_MUX_Type *)VIDEO_MUX_BASE)
89855#define VIDEO_MUX_BASE_ADDRS { VIDEO_MUX_BASE }
89857#define VIDEO_MUX_BASE_PTRS { VIDEO_MUX }
89858 /* end of group VIDEO_MUX_Peripheral_Access_Layer */
89862
89863
89864/* ----------------------------------------------------------------------------
89865 -- VIDEO_PLL Peripheral Access Layer
89866 ---------------------------------------------------------------------------- */
89867
89874typedef struct {
89875 struct { /* offset: 0x0 */
89876 __IO uint32_t RW;
89877 __IO uint32_t SET;
89878 __IO uint32_t CLR;
89879 __IO uint32_t TOG;
89880 } CTRL0;
89881 struct { /* offset: 0x10 */
89882 __IO uint32_t RW;
89883 __IO uint32_t SET;
89884 __IO uint32_t CLR;
89885 __IO uint32_t TOG;
89886 } SPREAD_SPECTRUM;
89887 struct { /* offset: 0x20 */
89888 __IO uint32_t RW;
89889 __IO uint32_t SET;
89890 __IO uint32_t CLR;
89891 __IO uint32_t TOG;
89892 } NUMERATOR;
89893 struct { /* offset: 0x30 */
89894 __IO uint32_t RW;
89895 __IO uint32_t SET;
89896 __IO uint32_t CLR;
89897 __IO uint32_t TOG;
89898 } DENOMINATOR;
89900
89901/* ----------------------------------------------------------------------------
89902 -- VIDEO_PLL Register Masks
89903 ---------------------------------------------------------------------------- */
89904
89913#define VIDEO_PLL_CTRL0_DIV_SELECT_MASK (0x7FU)
89914#define VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT (0U)
89917#define VIDEO_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_DIV_SELECT_MASK)
89918
89919#define VIDEO_PLL_CTRL0_ENABLE_ALT_MASK (0x100U)
89920#define VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT (8U)
89925#define VIDEO_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_ALT_MASK)
89926
89927#define VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U)
89928#define VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U)
89933#define VIDEO_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK)
89934
89935#define VIDEO_PLL_CTRL0_POWERUP_MASK (0x4000U)
89936#define VIDEO_PLL_CTRL0_POWERUP_SHIFT (14U)
89941#define VIDEO_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POWERUP_SHIFT)) & VIDEO_PLL_CTRL0_POWERUP_MASK)
89942
89943#define VIDEO_PLL_CTRL0_ENABLE_MASK (0x8000U)
89944#define VIDEO_PLL_CTRL0_ENABLE_SHIFT (15U)
89949#define VIDEO_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_MASK)
89950
89951#define VIDEO_PLL_CTRL0_BYPASS_MASK (0x10000U)
89952#define VIDEO_PLL_CTRL0_BYPASS_SHIFT (16U)
89957#define VIDEO_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BYPASS_SHIFT)) & VIDEO_PLL_CTRL0_BYPASS_MASK)
89958
89959#define VIDEO_PLL_CTRL0_DITHER_EN_MASK (0x20000U)
89960#define VIDEO_PLL_CTRL0_DITHER_EN_SHIFT (17U)
89965#define VIDEO_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DITHER_EN_SHIFT)) & VIDEO_PLL_CTRL0_DITHER_EN_MASK)
89966
89967#define VIDEO_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U)
89968#define VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT (19U)
89971#define VIDEO_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_TRIM_MASK)
89972
89973#define VIDEO_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U)
89974#define VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT (22U)
89977#define VIDEO_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & VIDEO_PLL_CTRL0_PLL_REG_EN_MASK)
89978
89979#define VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U)
89980#define VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U)
89989#define VIDEO_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK)
89990
89991#define VIDEO_PLL_CTRL0_BIAS_SELECT_MASK (0x20000000U)
89992#define VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT (29U)
89997#define VIDEO_PLL_CTRL0_BIAS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_SELECT_MASK)
90003#define VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU)
90004#define VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U)
90007#define VIDEO_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK)
90008
90009#define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U)
90010#define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U)
90013#define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
90014
90015#define VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U)
90016#define VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U)
90019#define VIDEO_PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK)
90025#define VIDEO_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
90026#define VIDEO_PLL_NUMERATOR_NUM_SHIFT (0U)
90029#define VIDEO_PLL_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_NUMERATOR_NUM_SHIFT)) & VIDEO_PLL_NUMERATOR_NUM_MASK)
90035#define VIDEO_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
90036#define VIDEO_PLL_DENOMINATOR_DENOM_SHIFT (0U)
90039#define VIDEO_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_DENOMINATOR_DENOM_SHIFT)) & VIDEO_PLL_DENOMINATOR_DENOM_MASK) /* end of group VIDEO_PLL_Register_Masks */
90046
90047
90048/* VIDEO_PLL - Peripheral instance base addresses */
90050#define VIDEO_PLL_BASE (0u)
90052#define VIDEO_PLL ((VIDEO_PLL_Type *)VIDEO_PLL_BASE)
90054#define VIDEO_PLL_BASE_ADDRS { VIDEO_PLL_BASE }
90056#define VIDEO_PLL_BASE_PTRS { VIDEO_PLL }
90057 /* end of group VIDEO_PLL_Peripheral_Access_Layer */
90061
90062
90063/* ----------------------------------------------------------------------------
90064 -- VMBANDGAP Peripheral Access Layer
90065 ---------------------------------------------------------------------------- */
90066
90073typedef struct {
90074 struct { /* offset: 0x0 */
90075 __IO uint32_t RW;
90076 __IO uint32_t SET;
90077 __IO uint32_t CLR;
90078 __IO uint32_t TOG;
90079 } CTRL0;
90080 uint8_t RESERVED_0[64];
90081 struct { /* offset: 0x50 */
90082 __I uint32_t RW;
90083 __I uint32_t SET;
90084 __I uint32_t CLR;
90085 __I uint32_t TOG;
90086 } STAT0;
90088
90089/* ----------------------------------------------------------------------------
90090 -- VMBANDGAP Register Masks
90091 ---------------------------------------------------------------------------- */
90092
90101#define VMBANDGAP_CTRL0_REFTOP_PWD_MASK (0x1U)
90102#define VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT (0U)
90105#define VMBANDGAP_CTRL0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWD_MASK)
90106
90107#define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U)
90108#define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U)
90111#define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK)
90112
90113#define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK (0x4U)
90114#define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT (2U)
90117#define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK)
90118
90119#define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK (0x8U)
90120#define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT (3U)
90123#define VMBANDGAP_CTRL0_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK)
90124
90125#define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U)
90126#define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U)
90129#define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK)
90135#define VMBANDGAP_STAT0_REFTOP_VBGUP_MASK (0x1U)
90136#define VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT (0U)
90139#define VMBANDGAP_STAT0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & VMBANDGAP_STAT0_REFTOP_VBGUP_MASK)
90140
90141#define VMBANDGAP_STAT0_VDD1_PORB_MASK (0x2U)
90142#define VMBANDGAP_STAT0_VDD1_PORB_SHIFT (1U)
90145#define VMBANDGAP_STAT0_VDD1_PORB(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD1_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD1_PORB_MASK)
90146
90147#define VMBANDGAP_STAT0_VDD2_PORB_MASK (0x4U)
90148#define VMBANDGAP_STAT0_VDD2_PORB_SHIFT (2U)
90151#define VMBANDGAP_STAT0_VDD2_PORB(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD2_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD2_PORB_MASK)
90152
90153#define VMBANDGAP_STAT0_VDD3_PORB_MASK (0x8U)
90154#define VMBANDGAP_STAT0_VDD3_PORB_SHIFT (3U)
90157#define VMBANDGAP_STAT0_VDD3_PORB(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD3_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD3_PORB_MASK) /* end of group VMBANDGAP_Register_Masks */
90164
90165
90166/* VMBANDGAP - Peripheral instance base addresses */
90168#define VMBANDGAP_BASE (0u)
90170#define VMBANDGAP ((VMBANDGAP_Type *)VMBANDGAP_BASE)
90172#define VMBANDGAP_BASE_ADDRS { VMBANDGAP_BASE }
90174#define VMBANDGAP_BASE_PTRS { VMBANDGAP }
90175 /* end of group VMBANDGAP_Peripheral_Access_Layer */
90179
90180
90181/* ----------------------------------------------------------------------------
90182 -- WDOG Peripheral Access Layer
90183 ---------------------------------------------------------------------------- */
90184
90191typedef struct {
90192 __IO uint16_t WCR;
90193 __IO uint16_t WSR;
90194 __I uint16_t WRSR;
90195 __IO uint16_t WICR;
90196 __IO uint16_t WMCR;
90197} WDOG_Type;
90198
90199/* ----------------------------------------------------------------------------
90200 -- WDOG Register Masks
90201 ---------------------------------------------------------------------------- */
90202
90211#define WDOG_WCR_WDZST_MASK (0x1U)
90212#define WDOG_WCR_WDZST_SHIFT (0U)
90217#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
90218
90219#define WDOG_WCR_WDBG_MASK (0x2U)
90220#define WDOG_WCR_WDBG_SHIFT (1U)
90225#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
90226
90227#define WDOG_WCR_WDE_MASK (0x4U)
90228#define WDOG_WCR_WDE_SHIFT (2U)
90233#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
90234
90235#define WDOG_WCR_WDT_MASK (0x8U)
90236#define WDOG_WCR_WDT_SHIFT (3U)
90241#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
90242
90243#define WDOG_WCR_SRS_MASK (0x10U)
90244#define WDOG_WCR_SRS_SHIFT (4U)
90249#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
90250
90251#define WDOG_WCR_WDA_MASK (0x20U)
90252#define WDOG_WCR_WDA_SHIFT (5U)
90257#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
90258
90259#define WDOG_WCR_SRE_MASK (0x40U)
90260#define WDOG_WCR_SRE_SHIFT (6U)
90265#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
90266
90267#define WDOG_WCR_WDW_MASK (0x80U)
90268#define WDOG_WCR_WDW_SHIFT (7U)
90273#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
90274
90275#define WDOG_WCR_WT_MASK (0xFF00U)
90276#define WDOG_WCR_WT_SHIFT (8U)
90284#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
90290#define WDOG_WSR_WSR_MASK (0xFFFFU)
90291#define WDOG_WSR_WSR_SHIFT (0U)
90296#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
90302#define WDOG_WRSR_SFTW_MASK (0x1U)
90303#define WDOG_WRSR_SFTW_SHIFT (0U)
90308#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
90309
90310#define WDOG_WRSR_TOUT_MASK (0x2U)
90311#define WDOG_WRSR_TOUT_SHIFT (1U)
90316#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
90317
90318#define WDOG_WRSR_POR_MASK (0x10U)
90319#define WDOG_WRSR_POR_SHIFT (4U)
90324#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
90330#define WDOG_WICR_WICT_MASK (0xFFU)
90331#define WDOG_WICR_WICT_SHIFT (0U)
90338#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
90339
90340#define WDOG_WICR_WTIS_MASK (0x4000U)
90341#define WDOG_WICR_WTIS_SHIFT (14U)
90346#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
90347
90348#define WDOG_WICR_WIE_MASK (0x8000U)
90349#define WDOG_WICR_WIE_SHIFT (15U)
90354#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
90360#define WDOG_WMCR_PDE_MASK (0x1U)
90361#define WDOG_WMCR_PDE_SHIFT (0U)
90366#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) /* end of group WDOG_Register_Masks */
90373
90374
90375/* WDOG - Peripheral instance base addresses */
90377#define WDOG1_BASE (0x40030000u)
90379#define WDOG1 ((WDOG_Type *)WDOG1_BASE)
90381#define WDOG2_BASE (0x40034000u)
90383#define WDOG2 ((WDOG_Type *)WDOG2_BASE)
90385#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }
90387#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }
90389#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
90390 /* end of group WDOG_Peripheral_Access_Layer */
90394
90395
90396/* ----------------------------------------------------------------------------
90397 -- XBARA Peripheral Access Layer
90398 ---------------------------------------------------------------------------- */
90399
90406typedef struct {
90407 __IO uint16_t SEL0;
90408 __IO uint16_t SEL1;
90409 __IO uint16_t SEL2;
90410 __IO uint16_t SEL3;
90411 __IO uint16_t SEL4;
90412 __IO uint16_t SEL5;
90413 __IO uint16_t SEL6;
90414 __IO uint16_t SEL7;
90415 __IO uint16_t SEL8;
90416 __IO uint16_t SEL9;
90417 __IO uint16_t SEL10;
90418 __IO uint16_t SEL11;
90419 __IO uint16_t SEL12;
90420 __IO uint16_t SEL13;
90421 __IO uint16_t SEL14;
90422 __IO uint16_t SEL15;
90423 __IO uint16_t SEL16;
90424 __IO uint16_t SEL17;
90425 __IO uint16_t SEL18;
90426 __IO uint16_t SEL19;
90427 __IO uint16_t SEL20;
90428 __IO uint16_t SEL21;
90429 __IO uint16_t SEL22;
90430 __IO uint16_t SEL23;
90431 __IO uint16_t SEL24;
90432 __IO uint16_t SEL25;
90433 __IO uint16_t SEL26;
90434 __IO uint16_t SEL27;
90435 __IO uint16_t SEL28;
90436 __IO uint16_t SEL29;
90437 __IO uint16_t SEL30;
90438 __IO uint16_t SEL31;
90439 __IO uint16_t SEL32;
90440 __IO uint16_t SEL33;
90441 __IO uint16_t SEL34;
90442 __IO uint16_t SEL35;
90443 __IO uint16_t SEL36;
90444 __IO uint16_t SEL37;
90445 __IO uint16_t SEL38;
90446 __IO uint16_t SEL39;
90447 __IO uint16_t SEL40;
90448 __IO uint16_t SEL41;
90449 __IO uint16_t SEL42;
90450 __IO uint16_t SEL43;
90451 __IO uint16_t SEL44;
90452 __IO uint16_t SEL45;
90453 __IO uint16_t SEL46;
90454 __IO uint16_t SEL47;
90455 __IO uint16_t SEL48;
90456 __IO uint16_t SEL49;
90457 __IO uint16_t SEL50;
90458 __IO uint16_t SEL51;
90459 __IO uint16_t SEL52;
90460 __IO uint16_t SEL53;
90461 __IO uint16_t SEL54;
90462 __IO uint16_t SEL55;
90463 __IO uint16_t SEL56;
90464 __IO uint16_t SEL57;
90465 __IO uint16_t SEL58;
90466 __IO uint16_t SEL59;
90467 __IO uint16_t SEL60;
90468 __IO uint16_t SEL61;
90469 __IO uint16_t SEL62;
90470 __IO uint16_t SEL63;
90471 __IO uint16_t SEL64;
90472 __IO uint16_t SEL65;
90473 __IO uint16_t SEL66;
90474 __IO uint16_t SEL67;
90475 __IO uint16_t SEL68;
90476 __IO uint16_t SEL69;
90477 __IO uint16_t SEL70;
90478 __IO uint16_t SEL71;
90479 __IO uint16_t SEL72;
90480 __IO uint16_t SEL73;
90481 __IO uint16_t SEL74;
90482 __IO uint16_t SEL75;
90483 __IO uint16_t SEL76;
90484 __IO uint16_t SEL77;
90485 __IO uint16_t SEL78;
90486 __IO uint16_t SEL79;
90487 __IO uint16_t SEL80;
90488 __IO uint16_t SEL81;
90489 __IO uint16_t SEL82;
90490 __IO uint16_t SEL83;
90491 __IO uint16_t SEL84;
90492 __IO uint16_t SEL85;
90493 __IO uint16_t SEL86;
90494 __IO uint16_t SEL87;
90495 __IO uint16_t CTRL0;
90496 __IO uint16_t CTRL1;
90497} XBARA_Type;
90498
90499/* ----------------------------------------------------------------------------
90500 -- XBARA Register Masks
90501 ---------------------------------------------------------------------------- */
90502
90511#define XBARA_SEL0_SEL0_MASK (0xFFU)
90512#define XBARA_SEL0_SEL0_SHIFT (0U)
90513#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
90514
90515#define XBARA_SEL0_SEL1_MASK (0xFF00U)
90516#define XBARA_SEL0_SEL1_SHIFT (8U)
90517#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
90523#define XBARA_SEL1_SEL2_MASK (0xFFU)
90524#define XBARA_SEL1_SEL2_SHIFT (0U)
90525#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
90526
90527#define XBARA_SEL1_SEL3_MASK (0xFF00U)
90528#define XBARA_SEL1_SEL3_SHIFT (8U)
90529#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
90535#define XBARA_SEL2_SEL4_MASK (0xFFU)
90536#define XBARA_SEL2_SEL4_SHIFT (0U)
90537#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
90538
90539#define XBARA_SEL2_SEL5_MASK (0xFF00U)
90540#define XBARA_SEL2_SEL5_SHIFT (8U)
90541#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
90547#define XBARA_SEL3_SEL6_MASK (0xFFU)
90548#define XBARA_SEL3_SEL6_SHIFT (0U)
90549#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
90550
90551#define XBARA_SEL3_SEL7_MASK (0xFF00U)
90552#define XBARA_SEL3_SEL7_SHIFT (8U)
90553#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
90559#define XBARA_SEL4_SEL8_MASK (0xFFU)
90560#define XBARA_SEL4_SEL8_SHIFT (0U)
90561#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
90562
90563#define XBARA_SEL4_SEL9_MASK (0xFF00U)
90564#define XBARA_SEL4_SEL9_SHIFT (8U)
90565#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
90571#define XBARA_SEL5_SEL10_MASK (0xFFU)
90572#define XBARA_SEL5_SEL10_SHIFT (0U)
90573#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
90574
90575#define XBARA_SEL5_SEL11_MASK (0xFF00U)
90576#define XBARA_SEL5_SEL11_SHIFT (8U)
90577#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
90583#define XBARA_SEL6_SEL12_MASK (0xFFU)
90584#define XBARA_SEL6_SEL12_SHIFT (0U)
90585#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
90586
90587#define XBARA_SEL6_SEL13_MASK (0xFF00U)
90588#define XBARA_SEL6_SEL13_SHIFT (8U)
90589#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
90595#define XBARA_SEL7_SEL14_MASK (0xFFU)
90596#define XBARA_SEL7_SEL14_SHIFT (0U)
90597#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
90598
90599#define XBARA_SEL7_SEL15_MASK (0xFF00U)
90600#define XBARA_SEL7_SEL15_SHIFT (8U)
90601#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
90607#define XBARA_SEL8_SEL16_MASK (0xFFU)
90608#define XBARA_SEL8_SEL16_SHIFT (0U)
90609#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
90610
90611#define XBARA_SEL8_SEL17_MASK (0xFF00U)
90612#define XBARA_SEL8_SEL17_SHIFT (8U)
90613#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
90619#define XBARA_SEL9_SEL18_MASK (0xFFU)
90620#define XBARA_SEL9_SEL18_SHIFT (0U)
90621#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
90622
90623#define XBARA_SEL9_SEL19_MASK (0xFF00U)
90624#define XBARA_SEL9_SEL19_SHIFT (8U)
90625#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
90631#define XBARA_SEL10_SEL20_MASK (0xFFU)
90632#define XBARA_SEL10_SEL20_SHIFT (0U)
90633#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
90634
90635#define XBARA_SEL10_SEL21_MASK (0xFF00U)
90636#define XBARA_SEL10_SEL21_SHIFT (8U)
90637#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
90643#define XBARA_SEL11_SEL22_MASK (0xFFU)
90644#define XBARA_SEL11_SEL22_SHIFT (0U)
90645#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
90646
90647#define XBARA_SEL11_SEL23_MASK (0xFF00U)
90648#define XBARA_SEL11_SEL23_SHIFT (8U)
90649#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
90655#define XBARA_SEL12_SEL24_MASK (0xFFU)
90656#define XBARA_SEL12_SEL24_SHIFT (0U)
90657#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
90658
90659#define XBARA_SEL12_SEL25_MASK (0xFF00U)
90660#define XBARA_SEL12_SEL25_SHIFT (8U)
90661#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
90667#define XBARA_SEL13_SEL26_MASK (0xFFU)
90668#define XBARA_SEL13_SEL26_SHIFT (0U)
90669#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
90670
90671#define XBARA_SEL13_SEL27_MASK (0xFF00U)
90672#define XBARA_SEL13_SEL27_SHIFT (8U)
90673#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
90679#define XBARA_SEL14_SEL28_MASK (0xFFU)
90680#define XBARA_SEL14_SEL28_SHIFT (0U)
90681#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
90682
90683#define XBARA_SEL14_SEL29_MASK (0xFF00U)
90684#define XBARA_SEL14_SEL29_SHIFT (8U)
90685#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
90691#define XBARA_SEL15_SEL30_MASK (0xFFU)
90692#define XBARA_SEL15_SEL30_SHIFT (0U)
90693#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
90694
90695#define XBARA_SEL15_SEL31_MASK (0xFF00U)
90696#define XBARA_SEL15_SEL31_SHIFT (8U)
90697#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
90703#define XBARA_SEL16_SEL32_MASK (0xFFU)
90704#define XBARA_SEL16_SEL32_SHIFT (0U)
90705#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
90706
90707#define XBARA_SEL16_SEL33_MASK (0xFF00U)
90708#define XBARA_SEL16_SEL33_SHIFT (8U)
90709#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
90715#define XBARA_SEL17_SEL34_MASK (0xFFU)
90716#define XBARA_SEL17_SEL34_SHIFT (0U)
90717#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
90718
90719#define XBARA_SEL17_SEL35_MASK (0xFF00U)
90720#define XBARA_SEL17_SEL35_SHIFT (8U)
90721#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
90727#define XBARA_SEL18_SEL36_MASK (0xFFU)
90728#define XBARA_SEL18_SEL36_SHIFT (0U)
90729#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
90730
90731#define XBARA_SEL18_SEL37_MASK (0xFF00U)
90732#define XBARA_SEL18_SEL37_SHIFT (8U)
90733#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
90739#define XBARA_SEL19_SEL38_MASK (0xFFU)
90740#define XBARA_SEL19_SEL38_SHIFT (0U)
90741#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
90742
90743#define XBARA_SEL19_SEL39_MASK (0xFF00U)
90744#define XBARA_SEL19_SEL39_SHIFT (8U)
90745#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
90751#define XBARA_SEL20_SEL40_MASK (0xFFU)
90752#define XBARA_SEL20_SEL40_SHIFT (0U)
90753#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
90754
90755#define XBARA_SEL20_SEL41_MASK (0xFF00U)
90756#define XBARA_SEL20_SEL41_SHIFT (8U)
90757#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
90763#define XBARA_SEL21_SEL42_MASK (0xFFU)
90764#define XBARA_SEL21_SEL42_SHIFT (0U)
90765#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
90766
90767#define XBARA_SEL21_SEL43_MASK (0xFF00U)
90768#define XBARA_SEL21_SEL43_SHIFT (8U)
90769#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
90775#define XBARA_SEL22_SEL44_MASK (0xFFU)
90776#define XBARA_SEL22_SEL44_SHIFT (0U)
90777#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
90778
90779#define XBARA_SEL22_SEL45_MASK (0xFF00U)
90780#define XBARA_SEL22_SEL45_SHIFT (8U)
90781#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
90787#define XBARA_SEL23_SEL46_MASK (0xFFU)
90788#define XBARA_SEL23_SEL46_SHIFT (0U)
90789#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
90790
90791#define XBARA_SEL23_SEL47_MASK (0xFF00U)
90792#define XBARA_SEL23_SEL47_SHIFT (8U)
90793#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
90799#define XBARA_SEL24_SEL48_MASK (0xFFU)
90800#define XBARA_SEL24_SEL48_SHIFT (0U)
90801#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
90802
90803#define XBARA_SEL24_SEL49_MASK (0xFF00U)
90804#define XBARA_SEL24_SEL49_SHIFT (8U)
90805#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
90811#define XBARA_SEL25_SEL50_MASK (0xFFU)
90812#define XBARA_SEL25_SEL50_SHIFT (0U)
90813#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
90814
90815#define XBARA_SEL25_SEL51_MASK (0xFF00U)
90816#define XBARA_SEL25_SEL51_SHIFT (8U)
90817#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
90823#define XBARA_SEL26_SEL52_MASK (0xFFU)
90824#define XBARA_SEL26_SEL52_SHIFT (0U)
90825#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
90826
90827#define XBARA_SEL26_SEL53_MASK (0xFF00U)
90828#define XBARA_SEL26_SEL53_SHIFT (8U)
90829#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
90835#define XBARA_SEL27_SEL54_MASK (0xFFU)
90836#define XBARA_SEL27_SEL54_SHIFT (0U)
90837#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
90838
90839#define XBARA_SEL27_SEL55_MASK (0xFF00U)
90840#define XBARA_SEL27_SEL55_SHIFT (8U)
90841#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
90847#define XBARA_SEL28_SEL56_MASK (0xFFU)
90848#define XBARA_SEL28_SEL56_SHIFT (0U)
90849#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
90850
90851#define XBARA_SEL28_SEL57_MASK (0xFF00U)
90852#define XBARA_SEL28_SEL57_SHIFT (8U)
90853#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
90859#define XBARA_SEL29_SEL58_MASK (0xFFU)
90860#define XBARA_SEL29_SEL58_SHIFT (0U)
90861#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
90862
90863#define XBARA_SEL29_SEL59_MASK (0xFF00U)
90864#define XBARA_SEL29_SEL59_SHIFT (8U)
90865#define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
90871#define XBARA_SEL30_SEL60_MASK (0xFFU)
90872#define XBARA_SEL30_SEL60_SHIFT (0U)
90873#define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
90874
90875#define XBARA_SEL30_SEL61_MASK (0xFF00U)
90876#define XBARA_SEL30_SEL61_SHIFT (8U)
90877#define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
90883#define XBARA_SEL31_SEL62_MASK (0xFFU)
90884#define XBARA_SEL31_SEL62_SHIFT (0U)
90885#define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
90886
90887#define XBARA_SEL31_SEL63_MASK (0xFF00U)
90888#define XBARA_SEL31_SEL63_SHIFT (8U)
90889#define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
90895#define XBARA_SEL32_SEL64_MASK (0xFFU)
90896#define XBARA_SEL32_SEL64_SHIFT (0U)
90897#define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
90898
90899#define XBARA_SEL32_SEL65_MASK (0xFF00U)
90900#define XBARA_SEL32_SEL65_SHIFT (8U)
90901#define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
90907#define XBARA_SEL33_SEL66_MASK (0xFFU)
90908#define XBARA_SEL33_SEL66_SHIFT (0U)
90909#define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
90910
90911#define XBARA_SEL33_SEL67_MASK (0xFF00U)
90912#define XBARA_SEL33_SEL67_SHIFT (8U)
90913#define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
90919#define XBARA_SEL34_SEL68_MASK (0xFFU)
90920#define XBARA_SEL34_SEL68_SHIFT (0U)
90921#define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
90922
90923#define XBARA_SEL34_SEL69_MASK (0xFF00U)
90924#define XBARA_SEL34_SEL69_SHIFT (8U)
90925#define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
90931#define XBARA_SEL35_SEL70_MASK (0xFFU)
90932#define XBARA_SEL35_SEL70_SHIFT (0U)
90933#define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
90934
90935#define XBARA_SEL35_SEL71_MASK (0xFF00U)
90936#define XBARA_SEL35_SEL71_SHIFT (8U)
90937#define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
90943#define XBARA_SEL36_SEL72_MASK (0xFFU)
90944#define XBARA_SEL36_SEL72_SHIFT (0U)
90945#define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
90946
90947#define XBARA_SEL36_SEL73_MASK (0xFF00U)
90948#define XBARA_SEL36_SEL73_SHIFT (8U)
90949#define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
90955#define XBARA_SEL37_SEL74_MASK (0xFFU)
90956#define XBARA_SEL37_SEL74_SHIFT (0U)
90957#define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
90958
90959#define XBARA_SEL37_SEL75_MASK (0xFF00U)
90960#define XBARA_SEL37_SEL75_SHIFT (8U)
90961#define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
90967#define XBARA_SEL38_SEL76_MASK (0xFFU)
90968#define XBARA_SEL38_SEL76_SHIFT (0U)
90969#define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
90970
90971#define XBARA_SEL38_SEL77_MASK (0xFF00U)
90972#define XBARA_SEL38_SEL77_SHIFT (8U)
90973#define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
90979#define XBARA_SEL39_SEL78_MASK (0xFFU)
90980#define XBARA_SEL39_SEL78_SHIFT (0U)
90981#define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
90982
90983#define XBARA_SEL39_SEL79_MASK (0xFF00U)
90984#define XBARA_SEL39_SEL79_SHIFT (8U)
90985#define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
90991#define XBARA_SEL40_SEL80_MASK (0xFFU)
90992#define XBARA_SEL40_SEL80_SHIFT (0U)
90993#define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
90994
90995#define XBARA_SEL40_SEL81_MASK (0xFF00U)
90996#define XBARA_SEL40_SEL81_SHIFT (8U)
90997#define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
91003#define XBARA_SEL41_SEL82_MASK (0xFFU)
91004#define XBARA_SEL41_SEL82_SHIFT (0U)
91005#define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
91006
91007#define XBARA_SEL41_SEL83_MASK (0xFF00U)
91008#define XBARA_SEL41_SEL83_SHIFT (8U)
91009#define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
91015#define XBARA_SEL42_SEL84_MASK (0xFFU)
91016#define XBARA_SEL42_SEL84_SHIFT (0U)
91017#define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
91018
91019#define XBARA_SEL42_SEL85_MASK (0xFF00U)
91020#define XBARA_SEL42_SEL85_SHIFT (8U)
91021#define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
91027#define XBARA_SEL43_SEL86_MASK (0xFFU)
91028#define XBARA_SEL43_SEL86_SHIFT (0U)
91029#define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
91030
91031#define XBARA_SEL43_SEL87_MASK (0xFF00U)
91032#define XBARA_SEL43_SEL87_SHIFT (8U)
91033#define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
91039#define XBARA_SEL44_SEL88_MASK (0xFFU)
91040#define XBARA_SEL44_SEL88_SHIFT (0U)
91041#define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
91042
91043#define XBARA_SEL44_SEL89_MASK (0xFF00U)
91044#define XBARA_SEL44_SEL89_SHIFT (8U)
91045#define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
91051#define XBARA_SEL45_SEL90_MASK (0xFFU)
91052#define XBARA_SEL45_SEL90_SHIFT (0U)
91053#define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
91054
91055#define XBARA_SEL45_SEL91_MASK (0xFF00U)
91056#define XBARA_SEL45_SEL91_SHIFT (8U)
91057#define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
91063#define XBARA_SEL46_SEL92_MASK (0xFFU)
91064#define XBARA_SEL46_SEL92_SHIFT (0U)
91065#define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
91066
91067#define XBARA_SEL46_SEL93_MASK (0xFF00U)
91068#define XBARA_SEL46_SEL93_SHIFT (8U)
91069#define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
91075#define XBARA_SEL47_SEL94_MASK (0xFFU)
91076#define XBARA_SEL47_SEL94_SHIFT (0U)
91077#define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
91078
91079#define XBARA_SEL47_SEL95_MASK (0xFF00U)
91080#define XBARA_SEL47_SEL95_SHIFT (8U)
91081#define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
91087#define XBARA_SEL48_SEL96_MASK (0xFFU)
91088#define XBARA_SEL48_SEL96_SHIFT (0U)
91089#define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
91090
91091#define XBARA_SEL48_SEL97_MASK (0xFF00U)
91092#define XBARA_SEL48_SEL97_SHIFT (8U)
91093#define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
91099#define XBARA_SEL49_SEL98_MASK (0xFFU)
91100#define XBARA_SEL49_SEL98_SHIFT (0U)
91101#define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
91102
91103#define XBARA_SEL49_SEL99_MASK (0xFF00U)
91104#define XBARA_SEL49_SEL99_SHIFT (8U)
91105#define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
91111#define XBARA_SEL50_SEL100_MASK (0xFFU)
91112#define XBARA_SEL50_SEL100_SHIFT (0U)
91113#define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
91114
91115#define XBARA_SEL50_SEL101_MASK (0xFF00U)
91116#define XBARA_SEL50_SEL101_SHIFT (8U)
91117#define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
91123#define XBARA_SEL51_SEL102_MASK (0xFFU)
91124#define XBARA_SEL51_SEL102_SHIFT (0U)
91125#define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
91126
91127#define XBARA_SEL51_SEL103_MASK (0xFF00U)
91128#define XBARA_SEL51_SEL103_SHIFT (8U)
91129#define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
91135#define XBARA_SEL52_SEL104_MASK (0xFFU)
91136#define XBARA_SEL52_SEL104_SHIFT (0U)
91137#define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
91138
91139#define XBARA_SEL52_SEL105_MASK (0xFF00U)
91140#define XBARA_SEL52_SEL105_SHIFT (8U)
91141#define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
91147#define XBARA_SEL53_SEL106_MASK (0xFFU)
91148#define XBARA_SEL53_SEL106_SHIFT (0U)
91149#define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
91150
91151#define XBARA_SEL53_SEL107_MASK (0xFF00U)
91152#define XBARA_SEL53_SEL107_SHIFT (8U)
91153#define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
91159#define XBARA_SEL54_SEL108_MASK (0xFFU)
91160#define XBARA_SEL54_SEL108_SHIFT (0U)
91161#define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
91162
91163#define XBARA_SEL54_SEL109_MASK (0xFF00U)
91164#define XBARA_SEL54_SEL109_SHIFT (8U)
91165#define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
91171#define XBARA_SEL55_SEL110_MASK (0xFFU)
91172#define XBARA_SEL55_SEL110_SHIFT (0U)
91173#define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
91174
91175#define XBARA_SEL55_SEL111_MASK (0xFF00U)
91176#define XBARA_SEL55_SEL111_SHIFT (8U)
91177#define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
91183#define XBARA_SEL56_SEL112_MASK (0xFFU)
91184#define XBARA_SEL56_SEL112_SHIFT (0U)
91185#define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
91186
91187#define XBARA_SEL56_SEL113_MASK (0xFF00U)
91188#define XBARA_SEL56_SEL113_SHIFT (8U)
91189#define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
91195#define XBARA_SEL57_SEL114_MASK (0xFFU)
91196#define XBARA_SEL57_SEL114_SHIFT (0U)
91197#define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
91198
91199#define XBARA_SEL57_SEL115_MASK (0xFF00U)
91200#define XBARA_SEL57_SEL115_SHIFT (8U)
91201#define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
91207#define XBARA_SEL58_SEL116_MASK (0xFFU)
91208#define XBARA_SEL58_SEL116_SHIFT (0U)
91209#define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
91210
91211#define XBARA_SEL58_SEL117_MASK (0xFF00U)
91212#define XBARA_SEL58_SEL117_SHIFT (8U)
91213#define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
91219#define XBARA_SEL59_SEL118_MASK (0xFFU)
91220#define XBARA_SEL59_SEL118_SHIFT (0U)
91221#define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
91222
91223#define XBARA_SEL59_SEL119_MASK (0xFF00U)
91224#define XBARA_SEL59_SEL119_SHIFT (8U)
91225#define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
91231#define XBARA_SEL60_SEL120_MASK (0xFFU)
91232#define XBARA_SEL60_SEL120_SHIFT (0U)
91233#define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
91234
91235#define XBARA_SEL60_SEL121_MASK (0xFF00U)
91236#define XBARA_SEL60_SEL121_SHIFT (8U)
91237#define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
91243#define XBARA_SEL61_SEL122_MASK (0xFFU)
91244#define XBARA_SEL61_SEL122_SHIFT (0U)
91245#define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
91246
91247#define XBARA_SEL61_SEL123_MASK (0xFF00U)
91248#define XBARA_SEL61_SEL123_SHIFT (8U)
91249#define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
91255#define XBARA_SEL62_SEL124_MASK (0xFFU)
91256#define XBARA_SEL62_SEL124_SHIFT (0U)
91257#define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
91258
91259#define XBARA_SEL62_SEL125_MASK (0xFF00U)
91260#define XBARA_SEL62_SEL125_SHIFT (8U)
91261#define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
91267#define XBARA_SEL63_SEL126_MASK (0xFFU)
91268#define XBARA_SEL63_SEL126_SHIFT (0U)
91269#define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
91270
91271#define XBARA_SEL63_SEL127_MASK (0xFF00U)
91272#define XBARA_SEL63_SEL127_SHIFT (8U)
91273#define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
91279#define XBARA_SEL64_SEL128_MASK (0xFFU)
91280#define XBARA_SEL64_SEL128_SHIFT (0U)
91281#define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
91282
91283#define XBARA_SEL64_SEL129_MASK (0xFF00U)
91284#define XBARA_SEL64_SEL129_SHIFT (8U)
91285#define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
91291#define XBARA_SEL65_SEL130_MASK (0xFFU)
91292#define XBARA_SEL65_SEL130_SHIFT (0U)
91293#define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
91294
91295#define XBARA_SEL65_SEL131_MASK (0xFF00U)
91296#define XBARA_SEL65_SEL131_SHIFT (8U)
91297#define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
91303#define XBARA_SEL66_SEL132_MASK (0xFFU)
91304#define XBARA_SEL66_SEL132_SHIFT (0U)
91305#define XBARA_SEL66_SEL132(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL132_SHIFT)) & XBARA_SEL66_SEL132_MASK)
91306
91307#define XBARA_SEL66_SEL133_MASK (0xFF00U)
91308#define XBARA_SEL66_SEL133_SHIFT (8U)
91309#define XBARA_SEL66_SEL133(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL133_SHIFT)) & XBARA_SEL66_SEL133_MASK)
91315#define XBARA_SEL67_SEL134_MASK (0xFFU)
91316#define XBARA_SEL67_SEL134_SHIFT (0U)
91317#define XBARA_SEL67_SEL134(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL134_SHIFT)) & XBARA_SEL67_SEL134_MASK)
91318
91319#define XBARA_SEL67_SEL135_MASK (0xFF00U)
91320#define XBARA_SEL67_SEL135_SHIFT (8U)
91321#define XBARA_SEL67_SEL135(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL135_SHIFT)) & XBARA_SEL67_SEL135_MASK)
91327#define XBARA_SEL68_SEL136_MASK (0xFFU)
91328#define XBARA_SEL68_SEL136_SHIFT (0U)
91329#define XBARA_SEL68_SEL136(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL136_SHIFT)) & XBARA_SEL68_SEL136_MASK)
91330
91331#define XBARA_SEL68_SEL137_MASK (0xFF00U)
91332#define XBARA_SEL68_SEL137_SHIFT (8U)
91333#define XBARA_SEL68_SEL137(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL137_SHIFT)) & XBARA_SEL68_SEL137_MASK)
91339#define XBARA_SEL69_SEL138_MASK (0xFFU)
91340#define XBARA_SEL69_SEL138_SHIFT (0U)
91341#define XBARA_SEL69_SEL138(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL138_SHIFT)) & XBARA_SEL69_SEL138_MASK)
91342
91343#define XBARA_SEL69_SEL139_MASK (0xFF00U)
91344#define XBARA_SEL69_SEL139_SHIFT (8U)
91345#define XBARA_SEL69_SEL139(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL139_SHIFT)) & XBARA_SEL69_SEL139_MASK)
91351#define XBARA_SEL70_SEL140_MASK (0xFFU)
91352#define XBARA_SEL70_SEL140_SHIFT (0U)
91353#define XBARA_SEL70_SEL140(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL140_SHIFT)) & XBARA_SEL70_SEL140_MASK)
91354
91355#define XBARA_SEL70_SEL141_MASK (0xFF00U)
91356#define XBARA_SEL70_SEL141_SHIFT (8U)
91357#define XBARA_SEL70_SEL141(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL141_SHIFT)) & XBARA_SEL70_SEL141_MASK)
91363#define XBARA_SEL71_SEL142_MASK (0xFFU)
91364#define XBARA_SEL71_SEL142_SHIFT (0U)
91365#define XBARA_SEL71_SEL142(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL142_SHIFT)) & XBARA_SEL71_SEL142_MASK)
91366
91367#define XBARA_SEL71_SEL143_MASK (0xFF00U)
91368#define XBARA_SEL71_SEL143_SHIFT (8U)
91369#define XBARA_SEL71_SEL143(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL143_SHIFT)) & XBARA_SEL71_SEL143_MASK)
91375#define XBARA_SEL72_SEL144_MASK (0xFFU)
91376#define XBARA_SEL72_SEL144_SHIFT (0U)
91377#define XBARA_SEL72_SEL144(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL144_SHIFT)) & XBARA_SEL72_SEL144_MASK)
91378
91379#define XBARA_SEL72_SEL145_MASK (0xFF00U)
91380#define XBARA_SEL72_SEL145_SHIFT (8U)
91381#define XBARA_SEL72_SEL145(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL145_SHIFT)) & XBARA_SEL72_SEL145_MASK)
91387#define XBARA_SEL73_SEL146_MASK (0xFFU)
91388#define XBARA_SEL73_SEL146_SHIFT (0U)
91389#define XBARA_SEL73_SEL146(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL146_SHIFT)) & XBARA_SEL73_SEL146_MASK)
91390
91391#define XBARA_SEL73_SEL147_MASK (0xFF00U)
91392#define XBARA_SEL73_SEL147_SHIFT (8U)
91393#define XBARA_SEL73_SEL147(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL147_SHIFT)) & XBARA_SEL73_SEL147_MASK)
91399#define XBARA_SEL74_SEL148_MASK (0xFFU)
91400#define XBARA_SEL74_SEL148_SHIFT (0U)
91401#define XBARA_SEL74_SEL148(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL148_SHIFT)) & XBARA_SEL74_SEL148_MASK)
91402
91403#define XBARA_SEL74_SEL149_MASK (0xFF00U)
91404#define XBARA_SEL74_SEL149_SHIFT (8U)
91405#define XBARA_SEL74_SEL149(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL149_SHIFT)) & XBARA_SEL74_SEL149_MASK)
91411#define XBARA_SEL75_SEL150_MASK (0xFFU)
91412#define XBARA_SEL75_SEL150_SHIFT (0U)
91413#define XBARA_SEL75_SEL150(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL150_SHIFT)) & XBARA_SEL75_SEL150_MASK)
91414
91415#define XBARA_SEL75_SEL151_MASK (0xFF00U)
91416#define XBARA_SEL75_SEL151_SHIFT (8U)
91417#define XBARA_SEL75_SEL151(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL151_SHIFT)) & XBARA_SEL75_SEL151_MASK)
91423#define XBARA_SEL76_SEL152_MASK (0xFFU)
91424#define XBARA_SEL76_SEL152_SHIFT (0U)
91425#define XBARA_SEL76_SEL152(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL152_SHIFT)) & XBARA_SEL76_SEL152_MASK)
91426
91427#define XBARA_SEL76_SEL153_MASK (0xFF00U)
91428#define XBARA_SEL76_SEL153_SHIFT (8U)
91429#define XBARA_SEL76_SEL153(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL153_SHIFT)) & XBARA_SEL76_SEL153_MASK)
91435#define XBARA_SEL77_SEL154_MASK (0xFFU)
91436#define XBARA_SEL77_SEL154_SHIFT (0U)
91437#define XBARA_SEL77_SEL154(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL154_SHIFT)) & XBARA_SEL77_SEL154_MASK)
91438
91439#define XBARA_SEL77_SEL155_MASK (0xFF00U)
91440#define XBARA_SEL77_SEL155_SHIFT (8U)
91441#define XBARA_SEL77_SEL155(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL155_SHIFT)) & XBARA_SEL77_SEL155_MASK)
91447#define XBARA_SEL78_SEL156_MASK (0xFFU)
91448#define XBARA_SEL78_SEL156_SHIFT (0U)
91449#define XBARA_SEL78_SEL156(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL156_SHIFT)) & XBARA_SEL78_SEL156_MASK)
91450
91451#define XBARA_SEL78_SEL157_MASK (0xFF00U)
91452#define XBARA_SEL78_SEL157_SHIFT (8U)
91453#define XBARA_SEL78_SEL157(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL157_SHIFT)) & XBARA_SEL78_SEL157_MASK)
91459#define XBARA_SEL79_SEL158_MASK (0xFFU)
91460#define XBARA_SEL79_SEL158_SHIFT (0U)
91461#define XBARA_SEL79_SEL158(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL158_SHIFT)) & XBARA_SEL79_SEL158_MASK)
91462
91463#define XBARA_SEL79_SEL159_MASK (0xFF00U)
91464#define XBARA_SEL79_SEL159_SHIFT (8U)
91465#define XBARA_SEL79_SEL159(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL159_SHIFT)) & XBARA_SEL79_SEL159_MASK)
91471#define XBARA_SEL80_SEL160_MASK (0xFFU)
91472#define XBARA_SEL80_SEL160_SHIFT (0U)
91473#define XBARA_SEL80_SEL160(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL160_SHIFT)) & XBARA_SEL80_SEL160_MASK)
91474
91475#define XBARA_SEL80_SEL161_MASK (0xFF00U)
91476#define XBARA_SEL80_SEL161_SHIFT (8U)
91477#define XBARA_SEL80_SEL161(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL161_SHIFT)) & XBARA_SEL80_SEL161_MASK)
91483#define XBARA_SEL81_SEL162_MASK (0xFFU)
91484#define XBARA_SEL81_SEL162_SHIFT (0U)
91485#define XBARA_SEL81_SEL162(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL162_SHIFT)) & XBARA_SEL81_SEL162_MASK)
91486
91487#define XBARA_SEL81_SEL163_MASK (0xFF00U)
91488#define XBARA_SEL81_SEL163_SHIFT (8U)
91489#define XBARA_SEL81_SEL163(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL163_SHIFT)) & XBARA_SEL81_SEL163_MASK)
91495#define XBARA_SEL82_SEL164_MASK (0xFFU)
91496#define XBARA_SEL82_SEL164_SHIFT (0U)
91497#define XBARA_SEL82_SEL164(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL164_SHIFT)) & XBARA_SEL82_SEL164_MASK)
91498
91499#define XBARA_SEL82_SEL165_MASK (0xFF00U)
91500#define XBARA_SEL82_SEL165_SHIFT (8U)
91501#define XBARA_SEL82_SEL165(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL165_SHIFT)) & XBARA_SEL82_SEL165_MASK)
91507#define XBARA_SEL83_SEL166_MASK (0xFFU)
91508#define XBARA_SEL83_SEL166_SHIFT (0U)
91509#define XBARA_SEL83_SEL166(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL166_SHIFT)) & XBARA_SEL83_SEL166_MASK)
91510
91511#define XBARA_SEL83_SEL167_MASK (0xFF00U)
91512#define XBARA_SEL83_SEL167_SHIFT (8U)
91513#define XBARA_SEL83_SEL167(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL167_SHIFT)) & XBARA_SEL83_SEL167_MASK)
91519#define XBARA_SEL84_SEL168_MASK (0xFFU)
91520#define XBARA_SEL84_SEL168_SHIFT (0U)
91521#define XBARA_SEL84_SEL168(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL168_SHIFT)) & XBARA_SEL84_SEL168_MASK)
91522
91523#define XBARA_SEL84_SEL169_MASK (0xFF00U)
91524#define XBARA_SEL84_SEL169_SHIFT (8U)
91525#define XBARA_SEL84_SEL169(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL169_SHIFT)) & XBARA_SEL84_SEL169_MASK)
91531#define XBARA_SEL85_SEL170_MASK (0xFFU)
91532#define XBARA_SEL85_SEL170_SHIFT (0U)
91533#define XBARA_SEL85_SEL170(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL170_SHIFT)) & XBARA_SEL85_SEL170_MASK)
91534
91535#define XBARA_SEL85_SEL171_MASK (0xFF00U)
91536#define XBARA_SEL85_SEL171_SHIFT (8U)
91537#define XBARA_SEL85_SEL171(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL171_SHIFT)) & XBARA_SEL85_SEL171_MASK)
91543#define XBARA_SEL86_SEL172_MASK (0xFFU)
91544#define XBARA_SEL86_SEL172_SHIFT (0U)
91545#define XBARA_SEL86_SEL172(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL172_SHIFT)) & XBARA_SEL86_SEL172_MASK)
91546
91547#define XBARA_SEL86_SEL173_MASK (0xFF00U)
91548#define XBARA_SEL86_SEL173_SHIFT (8U)
91549#define XBARA_SEL86_SEL173(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL173_SHIFT)) & XBARA_SEL86_SEL173_MASK)
91555#define XBARA_SEL87_SEL174_MASK (0xFFU)
91556#define XBARA_SEL87_SEL174_SHIFT (0U)
91557#define XBARA_SEL87_SEL174(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL174_SHIFT)) & XBARA_SEL87_SEL174_MASK)
91558
91559#define XBARA_SEL87_SEL175_MASK (0xFF00U)
91560#define XBARA_SEL87_SEL175_SHIFT (8U)
91561#define XBARA_SEL87_SEL175(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL175_SHIFT)) & XBARA_SEL87_SEL175_MASK)
91567#define XBARA_CTRL0_DEN0_MASK (0x1U)
91568#define XBARA_CTRL0_DEN0_SHIFT (0U)
91573#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
91574
91575#define XBARA_CTRL0_IEN0_MASK (0x2U)
91576#define XBARA_CTRL0_IEN0_SHIFT (1U)
91581#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
91582
91583#define XBARA_CTRL0_EDGE0_MASK (0xCU)
91584#define XBARA_CTRL0_EDGE0_SHIFT (2U)
91591#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
91592
91593#define XBARA_CTRL0_STS0_MASK (0x10U)
91594#define XBARA_CTRL0_STS0_SHIFT (4U)
91599#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
91600
91601#define XBARA_CTRL0_DEN1_MASK (0x100U)
91602#define XBARA_CTRL0_DEN1_SHIFT (8U)
91607#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
91608
91609#define XBARA_CTRL0_IEN1_MASK (0x200U)
91610#define XBARA_CTRL0_IEN1_SHIFT (9U)
91615#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
91616
91617#define XBARA_CTRL0_EDGE1_MASK (0xC00U)
91618#define XBARA_CTRL0_EDGE1_SHIFT (10U)
91625#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
91626
91627#define XBARA_CTRL0_STS1_MASK (0x1000U)
91628#define XBARA_CTRL0_STS1_SHIFT (12U)
91633#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
91639#define XBARA_CTRL1_DEN2_MASK (0x1U)
91640#define XBARA_CTRL1_DEN2_SHIFT (0U)
91645#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
91646
91647#define XBARA_CTRL1_IEN2_MASK (0x2U)
91648#define XBARA_CTRL1_IEN2_SHIFT (1U)
91653#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
91654
91655#define XBARA_CTRL1_EDGE2_MASK (0xCU)
91656#define XBARA_CTRL1_EDGE2_SHIFT (2U)
91663#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
91664
91665#define XBARA_CTRL1_STS2_MASK (0x10U)
91666#define XBARA_CTRL1_STS2_SHIFT (4U)
91671#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
91672
91673#define XBARA_CTRL1_DEN3_MASK (0x100U)
91674#define XBARA_CTRL1_DEN3_SHIFT (8U)
91679#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
91680
91681#define XBARA_CTRL1_IEN3_MASK (0x200U)
91682#define XBARA_CTRL1_IEN3_SHIFT (9U)
91687#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
91688
91689#define XBARA_CTRL1_EDGE3_MASK (0xC00U)
91690#define XBARA_CTRL1_EDGE3_SHIFT (10U)
91697#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
91698
91699#define XBARA_CTRL1_STS3_MASK (0x1000U)
91700#define XBARA_CTRL1_STS3_SHIFT (12U)
91705#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) /* end of group XBARA_Register_Masks */
91712
91713
91714/* XBARA - Peripheral instance base addresses */
91716#define XBARA1_BASE (0x4003C000u)
91718#define XBARA1 ((XBARA_Type *)XBARA1_BASE)
91720#define XBARA_BASE_ADDRS { 0u, XBARA1_BASE }
91722#define XBARA_BASE_PTRS { (XBARA_Type *)0u, XBARA1 }
91723 /* end of group XBARA_Peripheral_Access_Layer */
91727
91728
91729/* ----------------------------------------------------------------------------
91730 -- XBARB Peripheral Access Layer
91731 ---------------------------------------------------------------------------- */
91732
91739typedef struct {
91740 __IO uint16_t SEL0;
91741 __IO uint16_t SEL1;
91742 __IO uint16_t SEL2;
91743 __IO uint16_t SEL3;
91744 __IO uint16_t SEL4;
91745 __IO uint16_t SEL5;
91746 __IO uint16_t SEL6;
91747 __IO uint16_t SEL7;
91748} XBARB_Type;
91749
91750/* ----------------------------------------------------------------------------
91751 -- XBARB Register Masks
91752 ---------------------------------------------------------------------------- */
91753
91762#define XBARB_SEL0_SEL0_MASK (0x7FU)
91763#define XBARB_SEL0_SEL0_SHIFT (0U)
91764#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
91765
91766#define XBARB_SEL0_SEL1_MASK (0x7F00U)
91767#define XBARB_SEL0_SEL1_SHIFT (8U)
91768#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
91774#define XBARB_SEL1_SEL2_MASK (0x7FU)
91775#define XBARB_SEL1_SEL2_SHIFT (0U)
91776#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
91777
91778#define XBARB_SEL1_SEL3_MASK (0x7F00U)
91779#define XBARB_SEL1_SEL3_SHIFT (8U)
91780#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
91786#define XBARB_SEL2_SEL4_MASK (0x7FU)
91787#define XBARB_SEL2_SEL4_SHIFT (0U)
91788#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
91789
91790#define XBARB_SEL2_SEL5_MASK (0x7F00U)
91791#define XBARB_SEL2_SEL5_SHIFT (8U)
91792#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
91798#define XBARB_SEL3_SEL6_MASK (0x7FU)
91799#define XBARB_SEL3_SEL6_SHIFT (0U)
91800#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
91801
91802#define XBARB_SEL3_SEL7_MASK (0x7F00U)
91803#define XBARB_SEL3_SEL7_SHIFT (8U)
91804#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
91810#define XBARB_SEL4_SEL8_MASK (0x7FU)
91811#define XBARB_SEL4_SEL8_SHIFT (0U)
91812#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
91813
91814#define XBARB_SEL4_SEL9_MASK (0x7F00U)
91815#define XBARB_SEL4_SEL9_SHIFT (8U)
91816#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
91822#define XBARB_SEL5_SEL10_MASK (0x7FU)
91823#define XBARB_SEL5_SEL10_SHIFT (0U)
91824#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
91825
91826#define XBARB_SEL5_SEL11_MASK (0x7F00U)
91827#define XBARB_SEL5_SEL11_SHIFT (8U)
91828#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
91834#define XBARB_SEL6_SEL12_MASK (0x7FU)
91835#define XBARB_SEL6_SEL12_SHIFT (0U)
91836#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
91837
91838#define XBARB_SEL6_SEL13_MASK (0x7F00U)
91839#define XBARB_SEL6_SEL13_SHIFT (8U)
91840#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
91846#define XBARB_SEL7_SEL14_MASK (0x7FU)
91847#define XBARB_SEL7_SEL14_SHIFT (0U)
91848#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
91849
91850#define XBARB_SEL7_SEL15_MASK (0x7F00U)
91851#define XBARB_SEL7_SEL15_SHIFT (8U)
91852#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) /* end of group XBARB_Register_Masks */
91859
91860
91861/* XBARB - Peripheral instance base addresses */
91863#define XBARB2_BASE (0x40040000u)
91865#define XBARB2 ((XBARB_Type *)XBARB2_BASE)
91867#define XBARB3_BASE (0x40044000u)
91869#define XBARB3 ((XBARB_Type *)XBARB3_BASE)
91871#define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
91873#define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
91874 /* end of group XBARB_Peripheral_Access_Layer */
91878
91879
91880/* ----------------------------------------------------------------------------
91881 -- XECC Peripheral Access Layer
91882 ---------------------------------------------------------------------------- */
91883
91890typedef struct {
91891 __IO uint32_t ECC_CTRL;
91892 __IO uint32_t ERR_STATUS;
91893 __IO uint32_t ERR_STAT_EN;
91894 __IO uint32_t ERR_SIG_EN;
91895 __IO uint32_t ERR_DATA_INJ;
91896 __IO uint32_t ERR_ECC_INJ;
91897 __I uint32_t SINGLE_ERR_ADDR;
91898 __I uint32_t SINGLE_ERR_DATA;
91899 __I uint32_t SINGLE_ERR_ECC;
91900 __I uint32_t SINGLE_ERR_POS;
91901 __I uint32_t SINGLE_ERR_BIT_FIELD;
91902 __I uint32_t MULTI_ERR_ADDR;
91903 __I uint32_t MULTI_ERR_DATA;
91904 __I uint32_t MULTI_ERR_ECC;
91905 __I uint32_t MULTI_ERR_BIT_FIELD;
91906 __IO uint32_t ECC_BASE_ADDR0;
91907 __IO uint32_t ECC_END_ADDR0;
91908 __IO uint32_t ECC_BASE_ADDR1;
91909 __IO uint32_t ECC_END_ADDR1;
91910 __IO uint32_t ECC_BASE_ADDR2;
91911 __IO uint32_t ECC_END_ADDR2;
91912 __IO uint32_t ECC_BASE_ADDR3;
91913 __IO uint32_t ECC_END_ADDR3;
91914} XECC_Type;
91915
91916/* ----------------------------------------------------------------------------
91917 -- XECC Register Masks
91918 ---------------------------------------------------------------------------- */
91919
91928#define XECC_ECC_CTRL_ECC_EN_MASK (0x1U)
91929#define XECC_ECC_CTRL_ECC_EN_SHIFT (0U)
91934#define XECC_ECC_CTRL_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_ECC_EN_SHIFT)) & XECC_ECC_CTRL_ECC_EN_MASK)
91935
91936#define XECC_ECC_CTRL_WECC_EN_MASK (0x2U)
91937#define XECC_ECC_CTRL_WECC_EN_SHIFT (1U)
91942#define XECC_ECC_CTRL_WECC_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_WECC_EN_SHIFT)) & XECC_ECC_CTRL_WECC_EN_MASK)
91943
91944#define XECC_ECC_CTRL_RECC_EN_MASK (0x4U)
91945#define XECC_ECC_CTRL_RECC_EN_SHIFT (2U)
91950#define XECC_ECC_CTRL_RECC_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_RECC_EN_SHIFT)) & XECC_ECC_CTRL_RECC_EN_MASK)
91951
91952#define XECC_ECC_CTRL_SWAP_EN_MASK (0x8U)
91953#define XECC_ECC_CTRL_SWAP_EN_SHIFT (3U)
91958#define XECC_ECC_CTRL_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_SWAP_EN_SHIFT)) & XECC_ECC_CTRL_SWAP_EN_MASK)
91964#define XECC_ERR_STATUS_SINGLE_ERR_MASK (0x1U)
91965#define XECC_ERR_STATUS_SINGLE_ERR_SHIFT (0U)
91970#define XECC_ERR_STATUS_SINGLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_SINGLE_ERR_SHIFT)) & XECC_ERR_STATUS_SINGLE_ERR_MASK)
91971
91972#define XECC_ERR_STATUS_MULTI_ERR_MASK (0x2U)
91973#define XECC_ERR_STATUS_MULTI_ERR_SHIFT (1U)
91978#define XECC_ERR_STATUS_MULTI_ERR(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_MULTI_ERR_SHIFT)) & XECC_ERR_STATUS_MULTI_ERR_MASK)
91979
91980#define XECC_ERR_STATUS_Reserved1_MASK (0xFFFFFFFCU)
91981#define XECC_ERR_STATUS_Reserved1_SHIFT (2U)
91984#define XECC_ERR_STATUS_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_Reserved1_SHIFT)) & XECC_ERR_STATUS_Reserved1_MASK)
91990#define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK (0x1U)
91991#define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT (0U)
91996#define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK)
91997
91998#define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK (0x2U)
91999#define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT (1U)
92004#define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK)
92005
92006#define XECC_ERR_STAT_EN_Reserved1_MASK (0xFFFFFFFCU)
92007#define XECC_ERR_STAT_EN_Reserved1_SHIFT (2U)
92010#define XECC_ERR_STAT_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_Reserved1_SHIFT)) & XECC_ERR_STAT_EN_Reserved1_MASK)
92016#define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK (0x1U)
92017#define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT (0U)
92022#define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK)
92023
92024#define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK (0x2U)
92025#define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT (1U)
92030#define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK)
92031
92032#define XECC_ERR_SIG_EN_Reserved1_MASK (0xFFFFFFFCU)
92033#define XECC_ERR_SIG_EN_Reserved1_SHIFT (2U)
92036#define XECC_ERR_SIG_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_Reserved1_SHIFT)) & XECC_ERR_SIG_EN_Reserved1_MASK)
92042#define XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
92043#define XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT (0U)
92046#define XECC_ERR_DATA_INJ_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT)) & XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK)
92052#define XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK (0xFFFFFFFFU)
92053#define XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT (0U)
92056#define XECC_ERR_ECC_INJ_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT)) & XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK)
92062#define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK (0xFFFFFFFFU)
92063#define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT (0U)
92066#define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT)) & XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK)
92072#define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
92073#define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT (0U)
92076#define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT)) & XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK)
92082#define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK (0xFFFFFFFFU)
92083#define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT (0U)
92086#define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT)) & XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK)
92092#define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
92093#define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT (0U)
92096#define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT)) & XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK)
92102#define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK (0xFFU)
92103#define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT (0U)
92106#define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK)
92107
92108#define XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK (0xFFFFFF00U)
92109#define XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT (8U)
92112#define XECC_SINGLE_ERR_BIT_FIELD_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK)
92118#define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK (0xFFFFFFFFU)
92119#define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT (0U)
92122#define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT)) & XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK)
92128#define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
92129#define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT (0U)
92132#define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT)) & XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK)
92138#define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK (0xFFFFFFFFU)
92139#define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT (0U)
92142#define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT)) & XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK)
92148#define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK (0xFFU)
92149#define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT (0U)
92152#define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK)
92153
92154#define XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK (0xFFFFFF00U)
92155#define XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT (8U)
92158#define XECC_MULTI_ERR_BIT_FIELD_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK)
92164#define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK (0xFFFFFFFFU)
92165#define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT (0U)
92168#define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT)) & XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK)
92174#define XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK (0xFFFFFFFFU)
92175#define XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT (0U)
92178#define XECC_ECC_END_ADDR0_ECC_END_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT)) & XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK)
92184#define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK (0xFFFFFFFFU)
92185#define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT (0U)
92188#define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT)) & XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK)
92194#define XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK (0xFFFFFFFFU)
92195#define XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT (0U)
92198#define XECC_ECC_END_ADDR1_ECC_END_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT)) & XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK)
92204#define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK (0xFFFFFFFFU)
92205#define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT (0U)
92208#define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT)) & XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK)
92214#define XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK (0xFFFFFFFFU)
92215#define XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT (0U)
92218#define XECC_ECC_END_ADDR2_ECC_END_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT)) & XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK)
92224#define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK (0xFFFFFFFFU)
92225#define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT (0U)
92228#define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT)) & XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK)
92234#define XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK (0xFFFFFFFFU)
92235#define XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT (0U)
92238#define XECC_ECC_END_ADDR3_ECC_END_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT)) & XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK) /* end of group XECC_Register_Masks */
92245
92246
92247/* XECC - Peripheral instance base addresses */
92249#define XECC_FLEXSPI1_BASE (0x4001C000u)
92251#define XECC_FLEXSPI1 ((XECC_Type *)XECC_FLEXSPI1_BASE)
92253#define XECC_FLEXSPI2_BASE (0x40020000u)
92255#define XECC_FLEXSPI2 ((XECC_Type *)XECC_FLEXSPI2_BASE)
92257#define XECC_SEMC_BASE (0x40024000u)
92259#define XECC_SEMC ((XECC_Type *)XECC_SEMC_BASE)
92261#define XECC_BASE_ADDRS { 0u, XECC_FLEXSPI1_BASE, XECC_FLEXSPI2_BASE, XECC_SEMC_BASE }
92263#define XECC_BASE_PTRS { (XECC_Type *)0u, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC }
92264 /* end of group XECC_Peripheral_Access_Layer */
92268
92269
92270/* ----------------------------------------------------------------------------
92271 -- XRDC2 Peripheral Access Layer
92272 ---------------------------------------------------------------------------- */
92273
92280typedef struct {
92281 __IO uint32_t MCR;
92282 __I uint32_t SR;
92283 uint8_t RESERVED_0[4088];
92284 struct { /* offset: 0x1000, array step: 0x8 */
92287 } MSCI_MSAC_WK[128];
92288 uint8_t RESERVED_1[3072];
92289 struct { /* offset: 0x2000, array step: index*0x100, index2*0x8 */
92292 } MDACI_MDAJ[32][32];
92293 struct { /* offset: 0x4000, array step: index*0x800, index2*0x8 */
92296 } PACI_PDACJ[8][256];
92297 struct { /* offset: 0x8000, array step: index*0x400, index2*0x20 */
92302 uint8_t RESERVED_0[4];
92305 uint8_t RESERVED_1[4];
92306 } MRCI_MRGDJ[32][32];
92307} XRDC2_Type;
92308
92309/* ----------------------------------------------------------------------------
92310 -- XRDC2 Register Masks
92311 ---------------------------------------------------------------------------- */
92312
92321#define XRDC2_MCR_GVLDM_MASK (0x1U)
92322#define XRDC2_MCR_GVLDM_SHIFT (0U)
92327#define XRDC2_MCR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK)
92328
92329#define XRDC2_MCR_GVLDC_MASK (0x2U)
92330#define XRDC2_MCR_GVLDC_SHIFT (1U)
92335#define XRDC2_MCR_GVLDC(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK)
92336
92337#define XRDC2_MCR_GCL_MASK (0x30U)
92338#define XRDC2_MCR_GCL_SHIFT (4U)
92345#define XRDC2_MCR_GCL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK)
92351#define XRDC2_SR_DIN_MASK (0xFU)
92352#define XRDC2_SR_DIN_SHIFT (0U)
92355#define XRDC2_SR_DIN(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)
92356
92357#define XRDC2_SR_HRL_MASK (0xF0U)
92358#define XRDC2_SR_HRL_SHIFT (4U)
92361#define XRDC2_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)
92362
92363#define XRDC2_SR_GCLO_MASK (0xF00U)
92364#define XRDC2_SR_GCLO_SHIFT (8U)
92367#define XRDC2_SR_GCLO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)
92373#define XRDC2_MSC_MSAC_W0_D0ACP_MASK (0x7U)
92374#define XRDC2_MSC_MSAC_W0_D0ACP_SHIFT (0U)
92377#define XRDC2_MSC_MSAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D0ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D0ACP_MASK)
92378
92379#define XRDC2_MSC_MSAC_W0_D1ACP_MASK (0x38U)
92380#define XRDC2_MSC_MSAC_W0_D1ACP_SHIFT (3U)
92383#define XRDC2_MSC_MSAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D1ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D1ACP_MASK)
92384
92385#define XRDC2_MSC_MSAC_W0_D2ACP_MASK (0x1C0U)
92386#define XRDC2_MSC_MSAC_W0_D2ACP_SHIFT (6U)
92389#define XRDC2_MSC_MSAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D2ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D2ACP_MASK)
92390
92391#define XRDC2_MSC_MSAC_W0_D3ACP_MASK (0xE00U)
92392#define XRDC2_MSC_MSAC_W0_D3ACP_SHIFT (9U)
92395#define XRDC2_MSC_MSAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D3ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D3ACP_MASK)
92396
92397#define XRDC2_MSC_MSAC_W0_D4ACP_MASK (0x7000U)
92398#define XRDC2_MSC_MSAC_W0_D4ACP_SHIFT (12U)
92401#define XRDC2_MSC_MSAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D4ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D4ACP_MASK)
92402
92403#define XRDC2_MSC_MSAC_W0_D5ACP_MASK (0x38000U)
92404#define XRDC2_MSC_MSAC_W0_D5ACP_SHIFT (15U)
92407#define XRDC2_MSC_MSAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D5ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D5ACP_MASK)
92408
92409#define XRDC2_MSC_MSAC_W0_D6ACP_MASK (0x1C0000U)
92410#define XRDC2_MSC_MSAC_W0_D6ACP_SHIFT (18U)
92413#define XRDC2_MSC_MSAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D6ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D6ACP_MASK)
92414
92415#define XRDC2_MSC_MSAC_W0_D7ACP_MASK (0xE00000U)
92416#define XRDC2_MSC_MSAC_W0_D7ACP_SHIFT (21U)
92419#define XRDC2_MSC_MSAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D7ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D7ACP_MASK)
92420
92421#define XRDC2_MSC_MSAC_W0_EALO_MASK (0xF000000U)
92422#define XRDC2_MSC_MSAC_W0_EALO_SHIFT (24U)
92425#define XRDC2_MSC_MSAC_W0_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_EALO_SHIFT)) & XRDC2_MSC_MSAC_W0_EALO_MASK)
92428/* The count of XRDC2_MSC_MSAC_W0 */
92429#define XRDC2_MSC_MSAC_W0_COUNT (128U)
92430
92434#define XRDC2_MSC_MSAC_W1_D8ACP_MASK (0x7U)
92435#define XRDC2_MSC_MSAC_W1_D8ACP_SHIFT (0U)
92438#define XRDC2_MSC_MSAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D8ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D8ACP_MASK)
92439
92440#define XRDC2_MSC_MSAC_W1_D9ACP_MASK (0x38U)
92441#define XRDC2_MSC_MSAC_W1_D9ACP_SHIFT (3U)
92444#define XRDC2_MSC_MSAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D9ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D9ACP_MASK)
92445
92446#define XRDC2_MSC_MSAC_W1_D10ACP_MASK (0x1C0U)
92447#define XRDC2_MSC_MSAC_W1_D10ACP_SHIFT (6U)
92450#define XRDC2_MSC_MSAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D10ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D10ACP_MASK)
92451
92452#define XRDC2_MSC_MSAC_W1_D11ACP_MASK (0xE00U)
92453#define XRDC2_MSC_MSAC_W1_D11ACP_SHIFT (9U)
92456#define XRDC2_MSC_MSAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D11ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D11ACP_MASK)
92457
92458#define XRDC2_MSC_MSAC_W1_D12ACP_MASK (0x7000U)
92459#define XRDC2_MSC_MSAC_W1_D12ACP_SHIFT (12U)
92462#define XRDC2_MSC_MSAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D12ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D12ACP_MASK)
92463
92464#define XRDC2_MSC_MSAC_W1_D13ACP_MASK (0x38000U)
92465#define XRDC2_MSC_MSAC_W1_D13ACP_SHIFT (15U)
92468#define XRDC2_MSC_MSAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D13ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D13ACP_MASK)
92469
92470#define XRDC2_MSC_MSAC_W1_D14ACP_MASK (0x1C0000U)
92471#define XRDC2_MSC_MSAC_W1_D14ACP_SHIFT (18U)
92474#define XRDC2_MSC_MSAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D14ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D14ACP_MASK)
92475
92476#define XRDC2_MSC_MSAC_W1_D15ACP_MASK (0xE00000U)
92477#define XRDC2_MSC_MSAC_W1_D15ACP_SHIFT (21U)
92480#define XRDC2_MSC_MSAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D15ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D15ACP_MASK)
92481
92482#define XRDC2_MSC_MSAC_W1_EAL_MASK (0x3000000U)
92483#define XRDC2_MSC_MSAC_W1_EAL_SHIFT (24U)
92490#define XRDC2_MSC_MSAC_W1_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_EAL_SHIFT)) & XRDC2_MSC_MSAC_W1_EAL_MASK)
92491
92492#define XRDC2_MSC_MSAC_W1_DL2_MASK (0x60000000U)
92493#define XRDC2_MSC_MSAC_W1_DL2_SHIFT (29U)
92500#define XRDC2_MSC_MSAC_W1_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_DL2_SHIFT)) & XRDC2_MSC_MSAC_W1_DL2_MASK)
92501
92502#define XRDC2_MSC_MSAC_W1_VLD_MASK (0x80000000U)
92503#define XRDC2_MSC_MSAC_W1_VLD_SHIFT (31U)
92508#define XRDC2_MSC_MSAC_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_VLD_SHIFT)) & XRDC2_MSC_MSAC_W1_VLD_MASK)
92511/* The count of XRDC2_MSC_MSAC_W1 */
92512#define XRDC2_MSC_MSAC_W1_COUNT (128U)
92513
92517#define XRDC2_MDAC_MDA_W0_MASK_MASK (0xFFFFU)
92518#define XRDC2_MDAC_MDA_W0_MASK_SHIFT (0U)
92521#define XRDC2_MDAC_MDA_W0_MASK(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MASK_SHIFT)) & XRDC2_MDAC_MDA_W0_MASK_MASK)
92522
92523#define XRDC2_MDAC_MDA_W0_MATCH_MASK (0xFFFF0000U)
92524#define XRDC2_MDAC_MDA_W0_MATCH_SHIFT (16U)
92527#define XRDC2_MDAC_MDA_W0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MATCH_SHIFT)) & XRDC2_MDAC_MDA_W0_MATCH_MASK)
92530/* The count of XRDC2_MDAC_MDA_W0 */
92531#define XRDC2_MDAC_MDA_W0_COUNT (32U)
92532
92533/* The count of XRDC2_MDAC_MDA_W0 */
92534#define XRDC2_MDAC_MDA_W0_COUNT2 (32U)
92535
92539#define XRDC2_MDAC_MDA_W1_DID_MASK (0xF0000U)
92540#define XRDC2_MDAC_MDA_W1_DID_SHIFT (16U)
92543#define XRDC2_MDAC_MDA_W1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DID_SHIFT)) & XRDC2_MDAC_MDA_W1_DID_MASK)
92544
92545#define XRDC2_MDAC_MDA_W1_PA_MASK (0x3000000U)
92546#define XRDC2_MDAC_MDA_W1_PA_SHIFT (24U)
92553#define XRDC2_MDAC_MDA_W1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_PA_SHIFT)) & XRDC2_MDAC_MDA_W1_PA_MASK)
92554
92555#define XRDC2_MDAC_MDA_W1_SA_MASK (0xC000000U)
92556#define XRDC2_MDAC_MDA_W1_SA_SHIFT (26U)
92563#define XRDC2_MDAC_MDA_W1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SA_SHIFT)) & XRDC2_MDAC_MDA_W1_SA_MASK)
92564
92565#define XRDC2_MDAC_MDA_W1_DL_MASK (0x40000000U)
92566#define XRDC2_MDAC_MDA_W1_DL_SHIFT (30U)
92571#define XRDC2_MDAC_MDA_W1_DL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DL_SHIFT)) & XRDC2_MDAC_MDA_W1_DL_MASK)
92572
92573#define XRDC2_MDAC_MDA_W1_VLD_MASK (0x80000000U)
92574#define XRDC2_MDAC_MDA_W1_VLD_SHIFT (31U)
92579#define XRDC2_MDAC_MDA_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_VLD_SHIFT)) & XRDC2_MDAC_MDA_W1_VLD_MASK)
92582/* The count of XRDC2_MDAC_MDA_W1 */
92583#define XRDC2_MDAC_MDA_W1_COUNT (32U)
92584
92585/* The count of XRDC2_MDAC_MDA_W1 */
92586#define XRDC2_MDAC_MDA_W1_COUNT2 (32U)
92587
92591#define XRDC2_PAC_PDAC_W0_D0ACP_MASK (0x7U)
92592#define XRDC2_PAC_PDAC_W0_D0ACP_SHIFT (0U)
92595#define XRDC2_PAC_PDAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D0ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D0ACP_MASK)
92596
92597#define XRDC2_PAC_PDAC_W0_D1ACP_MASK (0x38U)
92598#define XRDC2_PAC_PDAC_W0_D1ACP_SHIFT (3U)
92601#define XRDC2_PAC_PDAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D1ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D1ACP_MASK)
92602
92603#define XRDC2_PAC_PDAC_W0_D2ACP_MASK (0x1C0U)
92604#define XRDC2_PAC_PDAC_W0_D2ACP_SHIFT (6U)
92607#define XRDC2_PAC_PDAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D2ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D2ACP_MASK)
92608
92609#define XRDC2_PAC_PDAC_W0_D3ACP_MASK (0xE00U)
92610#define XRDC2_PAC_PDAC_W0_D3ACP_SHIFT (9U)
92613#define XRDC2_PAC_PDAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D3ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D3ACP_MASK)
92614
92615#define XRDC2_PAC_PDAC_W0_D4ACP_MASK (0x7000U)
92616#define XRDC2_PAC_PDAC_W0_D4ACP_SHIFT (12U)
92619#define XRDC2_PAC_PDAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D4ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D4ACP_MASK)
92620
92621#define XRDC2_PAC_PDAC_W0_D5ACP_MASK (0x38000U)
92622#define XRDC2_PAC_PDAC_W0_D5ACP_SHIFT (15U)
92625#define XRDC2_PAC_PDAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D5ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D5ACP_MASK)
92626
92627#define XRDC2_PAC_PDAC_W0_D6ACP_MASK (0x1C0000U)
92628#define XRDC2_PAC_PDAC_W0_D6ACP_SHIFT (18U)
92631#define XRDC2_PAC_PDAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D6ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D6ACP_MASK)
92632
92633#define XRDC2_PAC_PDAC_W0_D7ACP_MASK (0xE00000U)
92634#define XRDC2_PAC_PDAC_W0_D7ACP_SHIFT (21U)
92637#define XRDC2_PAC_PDAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D7ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D7ACP_MASK)
92638
92639#define XRDC2_PAC_PDAC_W0_EALO_MASK (0xF000000U)
92640#define XRDC2_PAC_PDAC_W0_EALO_SHIFT (24U)
92643#define XRDC2_PAC_PDAC_W0_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_EALO_SHIFT)) & XRDC2_PAC_PDAC_W0_EALO_MASK)
92646/* The count of XRDC2_PAC_PDAC_W0 */
92647#define XRDC2_PAC_PDAC_W0_COUNT (8U)
92648
92649/* The count of XRDC2_PAC_PDAC_W0 */
92650#define XRDC2_PAC_PDAC_W0_COUNT2 (256U)
92651
92655#define XRDC2_PAC_PDAC_W1_D8ACP_MASK (0x7U)
92656#define XRDC2_PAC_PDAC_W1_D8ACP_SHIFT (0U)
92659#define XRDC2_PAC_PDAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D8ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D8ACP_MASK)
92660
92661#define XRDC2_PAC_PDAC_W1_D9ACP_MASK (0x38U)
92662#define XRDC2_PAC_PDAC_W1_D9ACP_SHIFT (3U)
92665#define XRDC2_PAC_PDAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D9ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D9ACP_MASK)
92666
92667#define XRDC2_PAC_PDAC_W1_D10ACP_MASK (0x1C0U)
92668#define XRDC2_PAC_PDAC_W1_D10ACP_SHIFT (6U)
92671#define XRDC2_PAC_PDAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D10ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D10ACP_MASK)
92672
92673#define XRDC2_PAC_PDAC_W1_D11ACP_MASK (0xE00U)
92674#define XRDC2_PAC_PDAC_W1_D11ACP_SHIFT (9U)
92677#define XRDC2_PAC_PDAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D11ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D11ACP_MASK)
92678
92679#define XRDC2_PAC_PDAC_W1_D12ACP_MASK (0x7000U)
92680#define XRDC2_PAC_PDAC_W1_D12ACP_SHIFT (12U)
92683#define XRDC2_PAC_PDAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D12ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D12ACP_MASK)
92684
92685#define XRDC2_PAC_PDAC_W1_D13ACP_MASK (0x38000U)
92686#define XRDC2_PAC_PDAC_W1_D13ACP_SHIFT (15U)
92689#define XRDC2_PAC_PDAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D13ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D13ACP_MASK)
92690
92691#define XRDC2_PAC_PDAC_W1_D14ACP_MASK (0x1C0000U)
92692#define XRDC2_PAC_PDAC_W1_D14ACP_SHIFT (18U)
92695#define XRDC2_PAC_PDAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D14ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D14ACP_MASK)
92696
92697#define XRDC2_PAC_PDAC_W1_D15ACP_MASK (0xE00000U)
92698#define XRDC2_PAC_PDAC_W1_D15ACP_SHIFT (21U)
92701#define XRDC2_PAC_PDAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D15ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D15ACP_MASK)
92702
92703#define XRDC2_PAC_PDAC_W1_EAL_MASK (0x3000000U)
92704#define XRDC2_PAC_PDAC_W1_EAL_SHIFT (24U)
92711#define XRDC2_PAC_PDAC_W1_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_EAL_SHIFT)) & XRDC2_PAC_PDAC_W1_EAL_MASK)
92712
92713#define XRDC2_PAC_PDAC_W1_DL2_MASK (0x60000000U)
92714#define XRDC2_PAC_PDAC_W1_DL2_SHIFT (29U)
92721#define XRDC2_PAC_PDAC_W1_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_DL2_SHIFT)) & XRDC2_PAC_PDAC_W1_DL2_MASK)
92722
92723#define XRDC2_PAC_PDAC_W1_VLD_MASK (0x80000000U)
92724#define XRDC2_PAC_PDAC_W1_VLD_SHIFT (31U)
92729#define XRDC2_PAC_PDAC_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_VLD_SHIFT)) & XRDC2_PAC_PDAC_W1_VLD_MASK)
92732/* The count of XRDC2_PAC_PDAC_W1 */
92733#define XRDC2_PAC_PDAC_W1_COUNT (8U)
92734
92735/* The count of XRDC2_PAC_PDAC_W1 */
92736#define XRDC2_PAC_PDAC_W1_COUNT2 (256U)
92737
92741#define XRDC2_MRC_MRGD_W0_SRTADDR_MASK (0xFFFFF000U)
92742#define XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT (12U)
92745#define XRDC2_MRC_MRGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W0_SRTADDR_MASK)
92748/* The count of XRDC2_MRC_MRGD_W0 */
92749#define XRDC2_MRC_MRGD_W0_COUNT (32U)
92750
92751/* The count of XRDC2_MRC_MRGD_W0 */
92752#define XRDC2_MRC_MRGD_W0_COUNT2 (32U)
92753
92757#define XRDC2_MRC_MRGD_W1_SRTADDR_MASK (0xFU)
92758#define XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT (0U)
92761#define XRDC2_MRC_MRGD_W1_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W1_SRTADDR_MASK)
92764/* The count of XRDC2_MRC_MRGD_W1 */
92765#define XRDC2_MRC_MRGD_W1_COUNT (32U)
92766
92767/* The count of XRDC2_MRC_MRGD_W1 */
92768#define XRDC2_MRC_MRGD_W1_COUNT2 (32U)
92769
92773#define XRDC2_MRC_MRGD_W2_ENDADDR_MASK (0xFFFFF000U)
92774#define XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT (12U)
92777#define XRDC2_MRC_MRGD_W2_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W2_ENDADDR_MASK)
92780/* The count of XRDC2_MRC_MRGD_W2 */
92781#define XRDC2_MRC_MRGD_W2_COUNT (32U)
92782
92783/* The count of XRDC2_MRC_MRGD_W2 */
92784#define XRDC2_MRC_MRGD_W2_COUNT2 (32U)
92785
92789#define XRDC2_MRC_MRGD_W3_ENDADDR_MASK (0xFU)
92790#define XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT (0U)
92793#define XRDC2_MRC_MRGD_W3_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W3_ENDADDR_MASK)
92796/* The count of XRDC2_MRC_MRGD_W3 */
92797#define XRDC2_MRC_MRGD_W3_COUNT (32U)
92798
92799/* The count of XRDC2_MRC_MRGD_W3 */
92800#define XRDC2_MRC_MRGD_W3_COUNT2 (32U)
92801
92805#define XRDC2_MRC_MRGD_W5_D0ACP_MASK (0x7U)
92806#define XRDC2_MRC_MRGD_W5_D0ACP_SHIFT (0U)
92809#define XRDC2_MRC_MRGD_W5_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D0ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D0ACP_MASK)
92810
92811#define XRDC2_MRC_MRGD_W5_D1ACP_MASK (0x38U)
92812#define XRDC2_MRC_MRGD_W5_D1ACP_SHIFT (3U)
92815#define XRDC2_MRC_MRGD_W5_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D1ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D1ACP_MASK)
92816
92817#define XRDC2_MRC_MRGD_W5_D2ACP_MASK (0x1C0U)
92818#define XRDC2_MRC_MRGD_W5_D2ACP_SHIFT (6U)
92821#define XRDC2_MRC_MRGD_W5_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D2ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D2ACP_MASK)
92822
92823#define XRDC2_MRC_MRGD_W5_D3ACP_MASK (0xE00U)
92824#define XRDC2_MRC_MRGD_W5_D3ACP_SHIFT (9U)
92827#define XRDC2_MRC_MRGD_W5_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D3ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D3ACP_MASK)
92828
92829#define XRDC2_MRC_MRGD_W5_D4ACP_MASK (0x7000U)
92830#define XRDC2_MRC_MRGD_W5_D4ACP_SHIFT (12U)
92833#define XRDC2_MRC_MRGD_W5_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D4ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D4ACP_MASK)
92834
92835#define XRDC2_MRC_MRGD_W5_D5ACP_MASK (0x38000U)
92836#define XRDC2_MRC_MRGD_W5_D5ACP_SHIFT (15U)
92839#define XRDC2_MRC_MRGD_W5_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D5ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D5ACP_MASK)
92840
92841#define XRDC2_MRC_MRGD_W5_D6ACP_MASK (0x1C0000U)
92842#define XRDC2_MRC_MRGD_W5_D6ACP_SHIFT (18U)
92845#define XRDC2_MRC_MRGD_W5_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D6ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D6ACP_MASK)
92846
92847#define XRDC2_MRC_MRGD_W5_D7ACP_MASK (0xE00000U)
92848#define XRDC2_MRC_MRGD_W5_D7ACP_SHIFT (21U)
92851#define XRDC2_MRC_MRGD_W5_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D7ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D7ACP_MASK)
92852
92853#define XRDC2_MRC_MRGD_W5_EALO_MASK (0xF000000U)
92854#define XRDC2_MRC_MRGD_W5_EALO_SHIFT (24U)
92857#define XRDC2_MRC_MRGD_W5_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_EALO_SHIFT)) & XRDC2_MRC_MRGD_W5_EALO_MASK)
92860/* The count of XRDC2_MRC_MRGD_W5 */
92861#define XRDC2_MRC_MRGD_W5_COUNT (32U)
92862
92863/* The count of XRDC2_MRC_MRGD_W5 */
92864#define XRDC2_MRC_MRGD_W5_COUNT2 (32U)
92865
92869#define XRDC2_MRC_MRGD_W6_D8ACP_MASK (0x7U)
92870#define XRDC2_MRC_MRGD_W6_D8ACP_SHIFT (0U)
92873#define XRDC2_MRC_MRGD_W6_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D8ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D8ACP_MASK)
92874
92875#define XRDC2_MRC_MRGD_W6_D9ACP_MASK (0x38U)
92876#define XRDC2_MRC_MRGD_W6_D9ACP_SHIFT (3U)
92879#define XRDC2_MRC_MRGD_W6_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D9ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D9ACP_MASK)
92880
92881#define XRDC2_MRC_MRGD_W6_D10ACP_MASK (0x1C0U)
92882#define XRDC2_MRC_MRGD_W6_D10ACP_SHIFT (6U)
92885#define XRDC2_MRC_MRGD_W6_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D10ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D10ACP_MASK)
92886
92887#define XRDC2_MRC_MRGD_W6_D11ACP_MASK (0xE00U)
92888#define XRDC2_MRC_MRGD_W6_D11ACP_SHIFT (9U)
92891#define XRDC2_MRC_MRGD_W6_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D11ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D11ACP_MASK)
92892
92893#define XRDC2_MRC_MRGD_W6_D12ACP_MASK (0x7000U)
92894#define XRDC2_MRC_MRGD_W6_D12ACP_SHIFT (12U)
92897#define XRDC2_MRC_MRGD_W6_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D12ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D12ACP_MASK)
92898
92899#define XRDC2_MRC_MRGD_W6_D13ACP_MASK (0x38000U)
92900#define XRDC2_MRC_MRGD_W6_D13ACP_SHIFT (15U)
92903#define XRDC2_MRC_MRGD_W6_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D13ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D13ACP_MASK)
92904
92905#define XRDC2_MRC_MRGD_W6_D14ACP_MASK (0x1C0000U)
92906#define XRDC2_MRC_MRGD_W6_D14ACP_SHIFT (18U)
92909#define XRDC2_MRC_MRGD_W6_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D14ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D14ACP_MASK)
92910
92911#define XRDC2_MRC_MRGD_W6_D15ACP_MASK (0xE00000U)
92912#define XRDC2_MRC_MRGD_W6_D15ACP_SHIFT (21U)
92915#define XRDC2_MRC_MRGD_W6_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D15ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D15ACP_MASK)
92916
92917#define XRDC2_MRC_MRGD_W6_EAL_MASK (0x3000000U)
92918#define XRDC2_MRC_MRGD_W6_EAL_SHIFT (24U)
92925#define XRDC2_MRC_MRGD_W6_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_EAL_SHIFT)) & XRDC2_MRC_MRGD_W6_EAL_MASK)
92926
92927#define XRDC2_MRC_MRGD_W6_DL2_MASK (0x60000000U)
92928#define XRDC2_MRC_MRGD_W6_DL2_SHIFT (29U)
92935#define XRDC2_MRC_MRGD_W6_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_DL2_SHIFT)) & XRDC2_MRC_MRGD_W6_DL2_MASK)
92936
92937#define XRDC2_MRC_MRGD_W6_VLD_MASK (0x80000000U)
92938#define XRDC2_MRC_MRGD_W6_VLD_SHIFT (31U)
92943#define XRDC2_MRC_MRGD_W6_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_VLD_SHIFT)) & XRDC2_MRC_MRGD_W6_VLD_MASK)
92946/* The count of XRDC2_MRC_MRGD_W6 */
92947#define XRDC2_MRC_MRGD_W6_COUNT (32U)
92948
92949/* The count of XRDC2_MRC_MRGD_W6 */
92950#define XRDC2_MRC_MRGD_W6_COUNT2 (32U)
92951
92952 /* end of group XRDC2_Register_Masks */
92956
92957
92958/* XRDC2 - Peripheral instance base addresses */
92960#define XRDC2_D0_BASE (0x40CE0000u)
92962#define XRDC2_D0 ((XRDC2_Type *)XRDC2_D0_BASE)
92964#define XRDC2_D1_BASE (0x40CD0000u)
92966#define XRDC2_D1 ((XRDC2_Type *)XRDC2_D1_BASE)
92968#define XRDC2_BASE_ADDRS { XRDC2_D0_BASE, XRDC2_D1_BASE }
92970#define XRDC2_BASE_PTRS { XRDC2_D0, XRDC2_D1 }
92971 /* end of group XRDC2_Peripheral_Access_Layer */
92975
92976
92977/*
92978** End of section using anonymous unions
92979*/
92980
92981#if defined(__ARMCC_VERSION)
92982 #if (__ARMCC_VERSION >= 6010050)
92983 #pragma clang diagnostic pop
92984 #else
92985 #pragma pop
92986 #endif
92987#elif defined(__CWCC__)
92988 #pragma pop
92989#elif defined(__GNUC__)
92990 /* leave anonymous unions enabled */
92991#elif defined(__IAR_SYSTEMS_ICC__)
92992 #pragma language=default
92993#else
92994 #error Not supported compiler type
92995#endif
92996 /* end of group Peripheral_access_layer */
93000
93001
93002/* ----------------------------------------------------------------------------
93003 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
93004 ---------------------------------------------------------------------------- */
93005
93011#if defined(__ARMCC_VERSION)
93012 #if (__ARMCC_VERSION >= 6010050)
93013 #pragma clang system_header
93014 #endif
93015#elif defined(__IAR_SYSTEMS_ICC__)
93016 #pragma system_include
93017#endif
93018
93025#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
93032#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
93033 /* end of group Bit_Field_Generic_Macros */
93037
93038
93039/* ----------------------------------------------------------------------------
93040 -- SDK Compatibility
93041 ---------------------------------------------------------------------------- */
93042
93048/* No SDK compatibility issues. */
93049 /* end of group SDK_Compatibility_Symbols */
93053
93054
93055#endif /* _MIMXRT1166_CM7_H_ */
93056
#define __O
Definition: core_cm4.h:238
#define __IO
Definition: core_cm4.h:239
#define __I
Definition: core_cm4.h:236
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
@ GPIO6_Combined_16_31_IRQn
Definition: MIMXRT1166_cm7.h:158
@ ASRC_IRQn
Definition: MIMXRT1166_cm7.h:193
@ PWM2_2_IRQn
Definition: MIMXRT1166_cm7.h:275
@ PendSV_IRQn
Definition: MIMXRT1166_cm7.h:92
@ XECC_FLEXSPI2_FATAL_INT_IRQn
Definition: MIMXRT1166_cm7.h:309
@ LPI2C1_IRQn
Definition: MIMXRT1166_cm7.h:128
@ Reserved178_IRQn
Definition: MIMXRT1166_cm7.h:258
@ CAN3_ERROR_IRQn
Definition: MIMXRT1166_cm7.h:145
@ PWM1_0_IRQn
Definition: MIMXRT1166_cm7.h:221
@ LPSPI5_IRQn
Definition: MIMXRT1166_cm7.h:138
@ GPIO4_Combined_16_31_IRQn
Definition: MIMXRT1166_cm7.h:203
@ USBPHY1_IRQn
Definition: MIMXRT1166_cm7.h:186
@ ADC_ETC_ERROR_IRQ_IRQn
Definition: MIMXRT1166_cm7.h:245
@ SEMA4_CP0_IRQn
Definition: MIMXRT1166_cm7.h:271
@ GPIO3_Combined_0_15_IRQn
Definition: MIMXRT1166_cm7.h:200
@ DMA0_DMA16_IRQn
Definition: MIMXRT1166_cm7.h:96
@ CAAM_IRQ1_IRQn
Definition: MIMXRT1166_cm7.h:166
@ MECC2_FATAL_INT_IRQn
Definition: MIMXRT1166_cm7.h:305
@ DMA14_DMA30_IRQn
Definition: MIMXRT1166_cm7.h:110
@ FLEXSPI2_IRQn
Definition: MIMXRT1166_cm7.h:227
@ OCOTP_READ_FUSE_ERROR_IRQn
Definition: MIMXRT1166_cm7.h:211
@ NotAvail_IRQn
Definition: MIMXRT1166_cm7.h:82
@ Reserved233_IRQn
Definition: MIMXRT1166_cm7.h:313
@ GPT6_IRQn
Definition: MIMXRT1166_cm7.h:220
@ DMA13_DMA29_IRQn
Definition: MIMXRT1166_cm7.h:109
@ USDHC1_IRQn
Definition: MIMXRT1166_cm7.h:229
@ GPT3_IRQn
Definition: MIMXRT1166_cm7.h:217
@ CORE_IRQn
Definition: MIMXRT1166_cm7.h:115
@ KPP_IRQn
Definition: MIMXRT1166_cm7.h:147
@ RDC_IRQn
Definition: MIMXRT1166_cm7.h:188
@ PWM4_2_IRQn
Definition: MIMXRT1166_cm7.h:285
@ ENET_1G_1588_Timer_IRQn
Definition: MIMXRT1166_cm7.h:238
@ SEMA4_CP1_IRQn
Definition: MIMXRT1166_cm7.h:272
@ Reserved211_IRQn
Definition: MIMXRT1166_cm7.h:291
@ SEMC_IRQn
Definition: MIMXRT1166_cm7.h:228
@ FLEXIO2_IRQn
Definition: MIMXRT1166_cm7.h:207
@ CAAM_RTIC_IRQn
Definition: MIMXRT1166_cm7.h:170
@ ACMP3_IRQn
Definition: MIMXRT1166_cm7.h:255
@ PWM2_1_IRQn
Definition: MIMXRT1166_cm7.h:274
@ Reserved209_IRQn
Definition: MIMXRT1166_cm7.h:289
@ MemoryManagement_IRQn
Definition: MIMXRT1166_cm7.h:87
@ GPIO5_Combined_0_15_IRQn
Definition: MIMXRT1166_cm7.h:204
@ ADC1_IRQn
Definition: MIMXRT1166_cm7.h:184
@ SAI1_IRQn
Definition: MIMXRT1166_cm7.h:172
@ LPUART2_IRQn
Definition: MIMXRT1166_cm7.h:117
@ GPT1_IRQn
Definition: MIMXRT1166_cm7.h:215
@ LPI2C4_IRQn
Definition: MIMXRT1166_cm7.h:131
@ DMA15_DMA31_IRQn
Definition: MIMXRT1166_cm7.h:111
@ ENET_1G_IRQn
Definition: MIMXRT1166_cm7.h:237
@ Reserved208_IRQn
Definition: MIMXRT1166_cm7.h:288
@ LPUART12_IRQn
Definition: MIMXRT1166_cm7.h:127
@ ACMP1_IRQn
Definition: MIMXRT1166_cm7.h:253
@ TMR4_IRQn
Definition: MIMXRT1166_cm7.h:270
@ PWM1_1_IRQn
Definition: MIMXRT1166_cm7.h:222
@ CAAM_RECORVE_ERRPR_IRQn
Definition: MIMXRT1166_cm7.h:169
@ PDM_HWVAD_ERROR_IRQn
Definition: MIMXRT1166_cm7.h:297
@ Reserved68_IRQn
Definition: MIMXRT1166_cm7.h:148
@ PWM2_3_IRQn
Definition: MIMXRT1166_cm7.h:276
@ LPSPI6_IRQn
Definition: MIMXRT1166_cm7.h:139
@ GPIO13_Combined_0_31_IRQn
Definition: MIMXRT1166_cm7.h:189
@ LPUART9_IRQn
Definition: MIMXRT1166_cm7.h:124
@ XECC_SEMC_FATAL_INT_IRQn
Definition: MIMXRT1166_cm7.h:311
@ FLEXSPI1_IRQn
Definition: MIMXRT1166_cm7.h:226
@ SAI4_TX_IRQn
Definition: MIMXRT1166_cm7.h:177
@ CAAM_IRQ2_IRQn
Definition: MIMXRT1166_cm7.h:167
@ PWM1_FAULT_IRQn
Definition: MIMXRT1166_cm7.h:225
@ PWM4_0_IRQn
Definition: MIMXRT1166_cm7.h:283
@ PWM4_1_IRQn
Definition: MIMXRT1166_cm7.h:284
@ SNVS_HP_NON_TZ_IRQn
Definition: MIMXRT1166_cm7.h:162
@ ENET_1G_MAC0_Tx_Rx_1_IRQn
Definition: MIMXRT1166_cm7.h:235
@ SVCall_IRQn
Definition: MIMXRT1166_cm7.h:90
@ DMA_ERROR_IRQn
Definition: MIMXRT1166_cm7.h:112
@ eLCDIF_IRQn
Definition: MIMXRT1166_cm7.h:150
@ DMA10_DMA26_IRQn
Definition: MIMXRT1166_cm7.h:106
@ PDM_ERROR_IRQn
Definition: MIMXRT1166_cm7.h:299
@ GPU2D_IRQn
Definition: MIMXRT1166_cm7.h:156
@ LPUART7_IRQn
Definition: MIMXRT1166_cm7.h:122
@ SAI3_RX_IRQn
Definition: MIMXRT1166_cm7.h:174
@ DMA5_DMA21_IRQn
Definition: MIMXRT1166_cm7.h:101
@ CTI_TRIGGER_OUT0_IRQn
Definition: MIMXRT1166_cm7.h:113
@ LCDIFv2_IRQn
Definition: MIMXRT1166_cm7.h:151
@ LPI2C3_IRQn
Definition: MIMXRT1166_cm7.h:130
@ TMPSNS_LOW_HIGH_IRQn
Definition: MIMXRT1166_cm7.h:180
@ GPIO2_Combined_0_15_IRQn
Definition: MIMXRT1166_cm7.h:198
@ Reserved170_IRQn
Definition: MIMXRT1166_cm7.h:250
@ ENC3_IRQn
Definition: MIMXRT1166_cm7.h:263
@ PWM3_0_IRQn
Definition: MIMXRT1166_cm7.h:278
@ USB_OTG1_IRQn
Definition: MIMXRT1166_cm7.h:232
@ DMA3_DMA19_IRQn
Definition: MIMXRT1166_cm7.h:99
@ MIPI_DSI_IRQn
Definition: MIMXRT1166_cm7.h:155
@ Reserved110_IRQn
Definition: MIMXRT1166_cm7.h:190
@ CAAM_IRQ3_IRQn
Definition: MIMXRT1166_cm7.h:168
@ EMVSIM2_IRQn
Definition: MIMXRT1166_cm7.h:301
@ USDHC2_IRQn
Definition: MIMXRT1166_cm7.h:230
@ UsageFault_IRQn
Definition: MIMXRT1166_cm7.h:89
@ XBAR1_IRQ_2_3_IRQn
Definition: MIMXRT1166_cm7.h:240
@ LPUART5_IRQn
Definition: MIMXRT1166_cm7.h:120
@ Reserved213_IRQn
Definition: MIMXRT1166_cm7.h:293
@ CAAM_IRQ0_IRQn
Definition: MIMXRT1166_cm7.h:165
@ GPC_IRQn
Definition: MIMXRT1166_cm7.h:213
@ Reserved214_IRQn
Definition: MIMXRT1166_cm7.h:294
@ SysTick_IRQn
Definition: MIMXRT1166_cm7.h:93
@ CSI_IRQn
Definition: MIMXRT1166_cm7.h:152
@ SNVS_PULSE_EVENT_IRQn
Definition: MIMXRT1166_cm7.h:164
@ LPUART10_IRQn
Definition: MIMXRT1166_cm7.h:125
@ Reserved215_IRQn
Definition: MIMXRT1166_cm7.h:295
@ DMA4_DMA20_IRQn
Definition: MIMXRT1166_cm7.h:100
@ LPSPI3_IRQn
Definition: MIMXRT1166_cm7.h:136
@ USBPHY2_IRQn
Definition: MIMXRT1166_cm7.h:187
@ GPT5_IRQn
Definition: MIMXRT1166_cm7.h:219
@ CAN1_IRQn
Definition: MIMXRT1166_cm7.h:140
@ MIPI_CSI_IRQn
Definition: MIMXRT1166_cm7.h:154
@ LPUART4_IRQn
Definition: MIMXRT1166_cm7.h:119
@ LPUART11_IRQn
Definition: MIMXRT1166_cm7.h:126
@ TMR1_IRQn
Definition: MIMXRT1166_cm7.h:267
@ BusFault_IRQn
Definition: MIMXRT1166_cm7.h:88
@ PWM4_3_IRQn
Definition: MIMXRT1166_cm7.h:286
@ ADC_ETC_IRQ2_IRQn
Definition: MIMXRT1166_cm7.h:243
@ Reserved168_IRQn
Definition: MIMXRT1166_cm7.h:248
@ LPUART8_IRQn
Definition: MIMXRT1166_cm7.h:123
@ OCOTP_READ_DONE_ERROR_IRQn
Definition: MIMXRT1166_cm7.h:212
@ ACMP2_IRQn
Definition: MIMXRT1166_cm7.h:254
@ DMA7_DMA23_IRQn
Definition: MIMXRT1166_cm7.h:103
@ DebugMonitor_IRQn
Definition: MIMXRT1166_cm7.h:91
@ ADC2_IRQn
Definition: MIMXRT1166_cm7.h:185
@ TMR2_IRQn
Definition: MIMXRT1166_cm7.h:268
@ LPI2C2_IRQn
Definition: MIMXRT1166_cm7.h:129
@ ADC_ETC_IRQ0_IRQn
Definition: MIMXRT1166_cm7.h:241
@ EWM_IRQn
Definition: MIMXRT1166_cm7.h:210
@ GPR_IRQ_IRQn
Definition: MIMXRT1166_cm7.h:149
@ DMA8_DMA24_IRQn
Definition: MIMXRT1166_cm7.h:104
@ GPIO4_Combined_0_15_IRQn
Definition: MIMXRT1166_cm7.h:202
@ MUA_IRQn
Definition: MIMXRT1166_cm7.h:214
@ EMVSIM1_IRQn
Definition: MIMXRT1166_cm7.h:300
@ Reserved167_IRQn
Definition: MIMXRT1166_cm7.h:247
@ XECC_FLEXSPI2_INT_IRQn
Definition: MIMXRT1166_cm7.h:308
@ MECC1_INT_IRQn
Definition: MIMXRT1166_cm7.h:302
@ LPSR_LP8_BROWNOUT_IRQn
Definition: MIMXRT1166_cm7.h:182
@ Reserved185_IRQn
Definition: MIMXRT1166_cm7.h:265
@ PDM_HWVAD_EVENT_IRQn
Definition: MIMXRT1166_cm7.h:296
@ PWM3_3_IRQn
Definition: MIMXRT1166_cm7.h:281
@ LPSR_LP0_BROWNOUT_IRQn
Definition: MIMXRT1166_cm7.h:183
@ DMA6_DMA22_IRQn
Definition: MIMXRT1166_cm7.h:102
@ TMPSNS_INT_IRQn
Definition: MIMXRT1166_cm7.h:179
@ Reserved210_IRQn
Definition: MIMXRT1166_cm7.h:290
@ ADC_ETC_IRQ1_IRQn
Definition: MIMXRT1166_cm7.h:242
@ WDOG2_IRQn
Definition: MIMXRT1166_cm7.h:161
@ CM7_GPIO2_3_IRQn
Definition: MIMXRT1166_cm7.h:195
@ PWM2_0_IRQn
Definition: MIMXRT1166_cm7.h:273
@ DCIC2_IRQn
Definition: MIMXRT1166_cm7.h:192
@ Reserved177_IRQn
Definition: MIMXRT1166_cm7.h:257
@ XBAR1_IRQ_0_1_IRQn
Definition: MIMXRT1166_cm7.h:239
@ HardFault_IRQn
Definition: MIMXRT1166_cm7.h:86
@ CAN2_ERROR_IRQn
Definition: MIMXRT1166_cm7.h:143
@ MECC2_INT_IRQn
Definition: MIMXRT1166_cm7.h:304
@ ENC2_IRQn
Definition: MIMXRT1166_cm7.h:262
@ Reserved186_IRQn
Definition: MIMXRT1166_cm7.h:266
@ CTI_TRIGGER_OUT1_IRQn
Definition: MIMXRT1166_cm7.h:114
@ TMPSNS_PANIC_IRQn
Definition: MIMXRT1166_cm7.h:181
@ ACMP4_IRQn
Definition: MIMXRT1166_cm7.h:256
@ WDOG1_IRQn
Definition: MIMXRT1166_cm7.h:208
@ USB_OTG2_IRQn
Definition: MIMXRT1166_cm7.h:231
@ PWM1_2_IRQn
Definition: MIMXRT1166_cm7.h:223
@ ENET_1588_Timer_IRQn
Definition: MIMXRT1166_cm7.h:234
@ FLEXRAM_IRQn
Definition: MIMXRT1166_cm7.h:146
@ LPSPI1_IRQn
Definition: MIMXRT1166_cm7.h:134
@ SAI2_IRQn
Definition: MIMXRT1166_cm7.h:173
@ DMA11_DMA27_IRQn
Definition: MIMXRT1166_cm7.h:107
@ GPIO5_Combined_16_31_IRQn
Definition: MIMXRT1166_cm7.h:205
@ SAI3_TX_IRQn
Definition: MIMXRT1166_cm7.h:175
@ RTWDOG3_IRQn
Definition: MIMXRT1166_cm7.h:209
@ Reserved169_IRQn
Definition: MIMXRT1166_cm7.h:249
@ LPUART3_IRQn
Definition: MIMXRT1166_cm7.h:118
@ GPIO6_Combined_0_15_IRQn
Definition: MIMXRT1166_cm7.h:157
@ GPT2_IRQn
Definition: MIMXRT1166_cm7.h:216
@ CAN2_IRQn
Definition: MIMXRT1166_cm7.h:142
@ MECC1_FATAL_INT_IRQn
Definition: MIMXRT1166_cm7.h:303
@ SAI4_RX_IRQn
Definition: MIMXRT1166_cm7.h:176
@ FLEXIO1_IRQn
Definition: MIMXRT1166_cm7.h:206
@ PWM3_FAULT_IRQn
Definition: MIMXRT1166_cm7.h:282
@ CAN3_IRQn
Definition: MIMXRT1166_cm7.h:144
@ Reserved166_IRQn
Definition: MIMXRT1166_cm7.h:246
@ XECC_SEMC_INT_IRQn
Definition: MIMXRT1166_cm7.h:310
@ XECC_FLEXSPI1_FATAL_INT_IRQn
Definition: MIMXRT1166_cm7.h:307
@ ENET_1G_MAC0_Tx_Rx_2_IRQn
Definition: MIMXRT1166_cm7.h:236
@ ENC1_IRQn
Definition: MIMXRT1166_cm7.h:261
@ FLEXRAM_ECC_IRQn
Definition: MIMXRT1166_cm7.h:194
@ DMA2_DMA18_IRQn
Definition: MIMXRT1166_cm7.h:98
@ LPI2C5_IRQn
Definition: MIMXRT1166_cm7.h:132
@ PXP_IRQn
Definition: MIMXRT1166_cm7.h:153
@ DCIC1_IRQn
Definition: MIMXRT1166_cm7.h:191
@ LPI2C6_IRQn
Definition: MIMXRT1166_cm7.h:133
@ GPIO2_Combined_16_31_IRQn
Definition: MIMXRT1166_cm7.h:199
@ NonMaskableInt_IRQn
Definition: MIMXRT1166_cm7.h:85
@ TMR3_IRQn
Definition: MIMXRT1166_cm7.h:269
@ XECC_FLEXSPI1_INT_IRQn
Definition: MIMXRT1166_cm7.h:306
@ GPIO3_Combined_16_31_IRQn
Definition: MIMXRT1166_cm7.h:201
@ Reserved180_IRQn
Definition: MIMXRT1166_cm7.h:260
@ LPSPI2_IRQn
Definition: MIMXRT1166_cm7.h:135
@ PWM3_1_IRQn
Definition: MIMXRT1166_cm7.h:279
@ KEY_MANAGER_IRQn
Definition: MIMXRT1166_cm7.h:160
@ PWM4_FAULT_IRQn
Definition: MIMXRT1166_cm7.h:287
@ ENC4_IRQn
Definition: MIMXRT1166_cm7.h:264
@ Reserved232_IRQn
Definition: MIMXRT1166_cm7.h:312
@ PWM1_3_IRQn
Definition: MIMXRT1166_cm7.h:224
@ PIT1_IRQn
Definition: MIMXRT1166_cm7.h:251
@ LPUART6_IRQn
Definition: MIMXRT1166_cm7.h:121
@ PDM_EVENT_IRQn
Definition: MIMXRT1166_cm7.h:298
@ DMA9_DMA25_IRQn
Definition: MIMXRT1166_cm7.h:105
@ CDOG_IRQn
Definition: MIMXRT1166_cm7.h:171
@ CAN1_ERROR_IRQn
Definition: MIMXRT1166_cm7.h:141
@ SNVS_HP_TZ_IRQn
Definition: MIMXRT1166_cm7.h:163
@ Reserved212_IRQn
Definition: MIMXRT1166_cm7.h:292
@ SPDIF_IRQn
Definition: MIMXRT1166_cm7.h:178
@ ADC_ETC_IRQ3_IRQn
Definition: MIMXRT1166_cm7.h:244
@ ENET_IRQn
Definition: MIMXRT1166_cm7.h:233
@ DMA12_DMA28_IRQn
Definition: MIMXRT1166_cm7.h:108
@ LPSPI4_IRQn
Definition: MIMXRT1166_cm7.h:137
@ GPT4_IRQn
Definition: MIMXRT1166_cm7.h:218
@ LPUART1_IRQn
Definition: MIMXRT1166_cm7.h:116
@ GPIO1_Combined_0_15_IRQn
Definition: MIMXRT1166_cm7.h:196
@ Reserved179_IRQn
Definition: MIMXRT1166_cm7.h:259
@ PWM2_FAULT_IRQn
Definition: MIMXRT1166_cm7.h:277
@ PIT2_IRQn
Definition: MIMXRT1166_cm7.h:252
@ DAC_IRQn
Definition: MIMXRT1166_cm7.h:159
@ PWM3_2_IRQn
Definition: MIMXRT1166_cm7.h:280
@ DMA1_DMA17_IRQn
Definition: MIMXRT1166_cm7.h:97
@ GPIO1_Combined_16_31_IRQn
Definition: MIMXRT1166_cm7.h:197
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h723xx.h:49
_asrc_clock_source
The ASRC clock source.
Definition: MIMXRT1166_cm4.h:1859
enum _asrc_clock_source asrc_clock_source_t
The ASRC clock source.
@ kASRC_ClockSourceBitClock9_SPDIF_RX
Definition: MIMXRT1166_cm7.h:1689
@ kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT
Definition: MIMXRT1166_cm7.h:1693
@ kASRC_ClockSourceBitClock1_SAI1_RX
Definition: MIMXRT1166_cm7.h:1681
@ kASRC_ClockSourceBitClock3_SAI2_RX
Definition: MIMXRT1166_cm7.h:1683
@ kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT
Definition: MIMXRT1166_cm7.h:1690
@ kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT
Definition: MIMXRT1166_cm7.h:1692
@ kASRC_ClockSourceBitClock7_SAI4_RX
Definition: MIMXRT1166_cm7.h:1687
@ kASRC_ClockSourceNotAvalible
Definition: MIMXRT1166_cm7.h:1679
@ kASRC_ClockSourceBitClock2_SAI2_TX
Definition: MIMXRT1166_cm7.h:1682
@ kASRC_ClockSourceBitClock5_SAI3_RX
Definition: MIMXRT1166_cm7.h:1685
@ kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT
Definition: MIMXRT1166_cm7.h:1691
@ kASRC_ClockSourceBitClock4_SAI3_TX
Definition: MIMXRT1166_cm7.h:1684
@ kASRC_ClockSourceBitClock0_SAI1_TX
Definition: MIMXRT1166_cm7.h:1680
@ kASRC_ClockSourceBitClock6_SAI4_TX
Definition: MIMXRT1166_cm7.h:1686
@ kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT
Definition: MIMXRT1166_cm7.h:1694
@ kASRC_ClockSourceBitClock8_SPDIF_TX
Definition: MIMXRT1166_cm7.h:1688
enum _dma_request_source dma_request_source_t
Structure for the DMA hardware request.
_dma_request_source
Structure for the DMA hardware request.
Definition: MIMXRT1052.h:1131
@ kDmaRequestMuxSai3Rx
Definition: MIMXRT1166_cm7.h:1772
@ kDmaRequestMuxFlexSPI2Tx
Definition: MIMXRT1166_cm7.h:1789
@ kDmaRequestMuxFlexIO2Request4Request5
Definition: MIMXRT1166_cm7.h:1720
@ kDmaRequestMuxQTIMER3CaptTimer3
Definition: MIMXRT1166_cm7.h:1845
@ kDmaRequestMuxFlexPWM3CaptureSub0
Definition: MIMXRT1166_cm7.h:1810
@ kDmaRequestMuxFlexPWM4ValueSub1
Definition: MIMXRT1166_cm7.h:1823
@ kDmaRequestMuxLPUART9Tx
Definition: MIMXRT1166_cm7.h:1738
@ kDmaRequestMuxFlexPWM1ValueSub0
Definition: MIMXRT1166_cm7.h:1798
@ kDmaRequestMuxLPUART3Rx
Definition: MIMXRT1166_cm7.h:1727
@ kDmaRequestMuxLPUART7Rx
Definition: MIMXRT1166_cm7.h:1735
@ kDmaRequestMuxFlexPWM1CaptureSub0
Definition: MIMXRT1166_cm7.h:1794
@ kDmaRequestMuxFlexPWM3ValueSub3
Definition: MIMXRT1166_cm7.h:1817
@ kDmaRequestMuxFlexPWM3CaptureSub2
Definition: MIMXRT1166_cm7.h:1812
@ kDmaRequestMuxLPUART11Rx
Definition: MIMXRT1166_cm7.h:1743
@ kDmaRequestMuxLPSPI3Rx
Definition: MIMXRT1166_cm7.h:1754
@ kDmaRequestMuxSai4Rx
Definition: MIMXRT1166_cm7.h:1774
@ kDmaRequestMuxFlexSPI1Rx
Definition: MIMXRT1166_cm7.h:1786
@ kDmaRequestMuxFlexPWM3CaptureSub3
Definition: MIMXRT1166_cm7.h:1813
@ kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1166_cm7.h:1831
@ kDmaRequestMuxLPI2C1
Definition: MIMXRT1166_cm7.h:1762
@ kDmaRequestMuxLPSPI6Rx
Definition: MIMXRT1166_cm7.h:1760
@ kDmaRequestMuxLPUART5Tx
Definition: MIMXRT1166_cm7.h:1730
@ kDmaRequestMuxLPUART8Rx
Definition: MIMXRT1166_cm7.h:1737
@ kDmaRequestMuxACMP2
Definition: MIMXRT1166_cm7.h:1783
@ kDmaRequestMuxFlexPWM2CaptureSub1
Definition: MIMXRT1166_cm7.h:1803
@ kDmaRequestMuxFlexPWM1ValueSub3
Definition: MIMXRT1166_cm7.h:1801
@ kDmaRequestMuxEmvsim1Rx
Definition: MIMXRT1166_cm7.h:1874
@ kDmaRequestMuxFlexPWM1ValueSub1
Definition: MIMXRT1166_cm7.h:1799
@ kDmaRequestMuxLPSPI4Rx
Definition: MIMXRT1166_cm7.h:1756
@ kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1166_cm7.h:1841
@ kDmaRequestMuxPdm
Definition: MIMXRT1166_cm7.h:1858
@ kDmaRequestMuxXBAR1Request1
Definition: MIMXRT1166_cm7.h:1791
@ kDmaRequestMuxQTIMER1CaptTimer0
Definition: MIMXRT1166_cm7.h:1826
@ kDmaRequestMuxLPSPI5Tx
Definition: MIMXRT1166_cm7.h:1759
@ kDmaRequestMuxFlexIO1Request2Request3
Definition: MIMXRT1166_cm7.h:1715
@ kDmaRequestMuxSai1Rx
Definition: MIMXRT1166_cm7.h:1768
@ kDmaRequestMuxLPUART2Tx
Definition: MIMXRT1166_cm7.h:1724
@ kDmaRequestMuxADC1
Definition: MIMXRT1166_cm7.h:1780
@ kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1166_cm7.h:1839
@ kDmaRequestMuxQTIMER3Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1166_cm7.h:1847
@ kDmaRequestMuxQTIMER1CaptTimer2
Definition: MIMXRT1166_cm7.h:1828
@ kDmaRequestMuxFlexSPI1Tx
Definition: MIMXRT1166_cm7.h:1787
@ kDmaRequestMuxQTIMER2CaptTimer1
Definition: MIMXRT1166_cm7.h:1835
@ kDmaRequestMuxQTIMER4CaptTimer2
Definition: MIMXRT1166_cm7.h:1852
@ kDmaRequestMuxSai2Tx
Definition: MIMXRT1166_cm7.h:1771
@ kDmaRequestMuxQTIMER1CaptTimer3
Definition: MIMXRT1166_cm7.h:1829
@ kDmaRequestMuxSpdifRx
Definition: MIMXRT1166_cm7.h:1776
@ kDmaRequestMuxACMP1
Definition: MIMXRT1166_cm7.h:1782
@ kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1166_cm7.h:1830
@ kDmaRequestMuxQTIMER3CaptTimer1
Definition: MIMXRT1166_cm7.h:1843
@ kDmaRequestMuxeLCDIF
Definition: MIMXRT1166_cm7.h:1748
@ kDmaRequestMuxLPUART12Tx
Definition: MIMXRT1166_cm7.h:1744
@ kDmaRequestMuxLPUART3Tx
Definition: MIMXRT1166_cm7.h:1726
@ kDmaRequestMuxFlexPWM2CaptureSub3
Definition: MIMXRT1166_cm7.h:1805
@ kDmaRequestMuxQTIMER2CaptTimer3
Definition: MIMXRT1166_cm7.h:1837
@ kDmaRequestMuxLPSPI1Rx
Definition: MIMXRT1166_cm7.h:1750
@ kDmaRequestMuxQTIMER3Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1166_cm7.h:1846
@ kDmaRequestMuxLPI2C6
Definition: MIMXRT1166_cm7.h:1767
@ kDmaRequestMuxLPUART1Rx
Definition: MIMXRT1166_cm7.h:1723
@ kDmaRequestMuxEmvsim2Rx
Definition: MIMXRT1166_cm7.h:1876
@ kDmaRequestMuxQTIMER4CaptTimer1
Definition: MIMXRT1166_cm7.h:1851
@ kDmaRequestMuxEmvsim2Tx
Definition: MIMXRT1166_cm7.h:1875
@ kDmaRequestMuxFlexIO1Request0Request1
Definition: MIMXRT1166_cm7.h:1779
@ kDmaRequestMuxQTIMER1CaptTimer1
Definition: MIMXRT1166_cm7.h:1827
@ kDmaRequestMuxLPSPI6Tx
Definition: MIMXRT1166_cm7.h:1761
@ kDmaRequestMuxFlexPWM3ValueSub2
Definition: MIMXRT1166_cm7.h:1816
@ kDmaRequestMuxXBAR1Request0
Definition: MIMXRT1166_cm7.h:1790
@ kDmaRequestMuxQTIMER3Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1166_cm7.h:1849
@ kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1166_cm7.h:1840
@ kDmaRequestMuxXBAR1Request3
Definition: MIMXRT1166_cm7.h:1793
@ kDmaRequestMuxEnet1GTimer0
Definition: MIMXRT1166_cm7.h:1861
@ kDmaRequestMuxDAC
Definition: MIMXRT1166_cm7.h:1866
@ kDmaRequestMuxLPUART11Tx
Definition: MIMXRT1166_cm7.h:1742
@ kDmaRequestMuxEnetTimer0
Definition: MIMXRT1166_cm7.h:1859
@ kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1166_cm7.h:1833
@ kDmaRequestMuxLPUART2Rx
Definition: MIMXRT1166_cm7.h:1725
@ kDmaRequestMuxLPSPI2Rx
Definition: MIMXRT1166_cm7.h:1752
@ kDmaRequestMuxFlexIO2Request0Request1
Definition: MIMXRT1166_cm7.h:1718
@ kDmaRequestMuxFlexPWM4CaptureSub0
Definition: MIMXRT1166_cm7.h:1818
@ kDmaRequestMuxLPI2C3
Definition: MIMXRT1166_cm7.h:1764
@ kDmaRequestMuxASRCRequest3
Definition: MIMXRT1166_cm7.h:1869
@ kDmaRequestMuxASRCRequest4
Definition: MIMXRT1166_cm7.h:1870
@ kDmaRequestMuxASRCRequest6
Definition: MIMXRT1166_cm7.h:1872
@ kDmaRequestMuxFlexPWM4CaptureSub1
Definition: MIMXRT1166_cm7.h:1819
@ kDmaRequestMuxLPUART10Tx
Definition: MIMXRT1166_cm7.h:1740
@ kDmaRequestMuxCAN1
Definition: MIMXRT1166_cm7.h:1863
@ kDmaRequestMuxEmvsim1Tx
Definition: MIMXRT1166_cm7.h:1873
@ kDmaRequestMuxQTIMER4Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1166_cm7.h:1857
@ kDmaRequestMuxCAN3
Definition: MIMXRT1166_cm7.h:1865
@ kDmaRequestMuxASRCRequest1
Definition: MIMXRT1166_cm7.h:1867
@ kDmaRequestMuxCSI
Definition: MIMXRT1166_cm7.h:1746
@ kDmaRequestMuxFlexIO2Request6Request7
Definition: MIMXRT1166_cm7.h:1721
@ kDmaRequestMuxASRCRequest5
Definition: MIMXRT1166_cm7.h:1871
@ kDmaRequestMuxQTIMER4Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1166_cm7.h:1856
@ kDmaRequestMuxQTIMER3Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1166_cm7.h:1848
@ kDmaRequestMuxCAN2
Definition: MIMXRT1166_cm7.h:1864
@ kDmaRequestMuxFlexPWM2ValueSub0
Definition: MIMXRT1166_cm7.h:1806
@ kDmaRequestMuxQTIMER4Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1166_cm7.h:1854
@ kDmaRequestMuxQTIMER4CaptTimer3
Definition: MIMXRT1166_cm7.h:1853
@ kDmaRequestMuxASRCRequest2
Definition: MIMXRT1166_cm7.h:1868
@ kDmaRequestMuxLPUART5Rx
Definition: MIMXRT1166_cm7.h:1731
@ kDmaRequestMuxLPUART1Tx
Definition: MIMXRT1166_cm7.h:1722
@ kDmaRequestMuxLPUART4Rx
Definition: MIMXRT1166_cm7.h:1729
@ kDmaRequestMuxLPUART12Rx
Definition: MIMXRT1166_cm7.h:1745
@ kDmaRequestMuxSai1Tx
Definition: MIMXRT1166_cm7.h:1769
@ kDmaRequestMuxADC2
Definition: MIMXRT1166_cm7.h:1781
@ kDmaRequestMuxQTIMER3CaptTimer0
Definition: MIMXRT1166_cm7.h:1842
@ kDmaRequestMuxLCDIFv2
Definition: MIMXRT1166_cm7.h:1749
@ kDmaRequestMuxFlexPWM4ValueSub3
Definition: MIMXRT1166_cm7.h:1825
@ kDmaRequestMuxQTIMER2CaptTimer0
Definition: MIMXRT1166_cm7.h:1834
@ kDmaRequestMuxFlexPWM4CaptureSub2
Definition: MIMXRT1166_cm7.h:1820
@ kDmaRequestMuxEnetTimer1
Definition: MIMXRT1166_cm7.h:1860
@ kDmaRequestMuxQTIMER4CaptTimer0
Definition: MIMXRT1166_cm7.h:1850
@ kDmaRequestMuxFlexPWM4ValueSub0
Definition: MIMXRT1166_cm7.h:1822
@ kDmaRequestMuxSpdifTx
Definition: MIMXRT1166_cm7.h:1777
@ kDmaRequestMuxFlexPWM1CaptureSub2
Definition: MIMXRT1166_cm7.h:1796
@ kDmaRequestMuxEnet1GTimer1
Definition: MIMXRT1166_cm7.h:1862
@ kDmaRequestMuxLPUART10Rx
Definition: MIMXRT1166_cm7.h:1741
@ kDmaRequestMuxLPUART4Tx
Definition: MIMXRT1166_cm7.h:1728
@ kDmaRequestMuxFlexPWM3CaptureSub1
Definition: MIMXRT1166_cm7.h:1811
@ kDmaRequestMuxLPI2C5
Definition: MIMXRT1166_cm7.h:1766
@ kDmaRequestMuxFlexPWM2ValueSub1
Definition: MIMXRT1166_cm7.h:1807
@ kDmaRequestMuxFlexPWM2CaptureSub2
Definition: MIMXRT1166_cm7.h:1804
@ kDmaRequestMuxFlexPWM4ValueSub2
Definition: MIMXRT1166_cm7.h:1824
@ kDmaRequestMuxQTIMER2CaptTimer2
Definition: MIMXRT1166_cm7.h:1836
@ kDmaRequestMuxXBAR1Request2
Definition: MIMXRT1166_cm7.h:1792
@ kDmaRequestMuxLPSPI2Tx
Definition: MIMXRT1166_cm7.h:1753
@ kDmaRequestMuxFlexIO1Request6Request7
Definition: MIMXRT1166_cm7.h:1717
@ kDmaRequestMuxFlexPWM1ValueSub2
Definition: MIMXRT1166_cm7.h:1800
@ kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1166_cm7.h:1838
@ kDmaRequestMuxQTIMER4Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1166_cm7.h:1855
@ kDmaRequestMuxPxp
Definition: MIMXRT1166_cm7.h:1747
@ kDmaRequestMuxLPUART8Tx
Definition: MIMXRT1166_cm7.h:1736
@ kDmaRequestMuxFlexPWM3ValueSub1
Definition: MIMXRT1166_cm7.h:1815
@ kDmaRequestMuxLPUART7Tx
Definition: MIMXRT1166_cm7.h:1734
@ kDmaRequestMuxACMP4
Definition: MIMXRT1166_cm7.h:1785
@ kDmaRequestMuxLPSPI1Tx
Definition: MIMXRT1166_cm7.h:1751
@ kDmaRequestMuxADC_ETC
Definition: MIMXRT1166_cm7.h:1778
@ kDmaRequestMuxFlexPWM1CaptureSub1
Definition: MIMXRT1166_cm7.h:1795
@ kDmaRequestMuxFlexSPI2Rx
Definition: MIMXRT1166_cm7.h:1788
@ kDmaRequestMuxLPI2C2
Definition: MIMXRT1166_cm7.h:1763
@ kDmaRequestMuxSai3Tx
Definition: MIMXRT1166_cm7.h:1773
@ kDmaRequestMuxLPUART9Rx
Definition: MIMXRT1166_cm7.h:1739
@ kDmaRequestMuxFlexIO2Request2Request3
Definition: MIMXRT1166_cm7.h:1719
@ kDmaRequestMuxQTIMER3CaptTimer2
Definition: MIMXRT1166_cm7.h:1844
@ kDmaRequestMuxLPSPI5Rx
Definition: MIMXRT1166_cm7.h:1758
@ kDmaRequestMuxFlexPWM1CaptureSub3
Definition: MIMXRT1166_cm7.h:1797
@ kDmaRequestMuxFlexPWM2ValueSub3
Definition: MIMXRT1166_cm7.h:1809
@ kDmaRequestMuxFlexPWM3ValueSub0
Definition: MIMXRT1166_cm7.h:1814
@ kDmaRequestMuxFlexIO1Request4Request5
Definition: MIMXRT1166_cm7.h:1716
@ kDmaRequestMuxSai4Tx
Definition: MIMXRT1166_cm7.h:1775
@ kDmaRequestMuxLPUART6Tx
Definition: MIMXRT1166_cm7.h:1732
@ kDmaRequestMuxFlexPWM2ValueSub2
Definition: MIMXRT1166_cm7.h:1808
@ kDmaRequestMuxLPSPI4Tx
Definition: MIMXRT1166_cm7.h:1757
@ kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1166_cm7.h:1832
@ kDmaRequestMuxFlexPWM2CaptureSub0
Definition: MIMXRT1166_cm7.h:1802
@ kDmaRequestMuxFlexPWM4CaptureSub3
Definition: MIMXRT1166_cm7.h:1821
@ kDmaRequestMuxSai2Rx
Definition: MIMXRT1166_cm7.h:1770
@ kDmaRequestMuxLPUART6Rx
Definition: MIMXRT1166_cm7.h:1733
@ kDmaRequestMuxLPSPI3Tx
Definition: MIMXRT1166_cm7.h:1755
@ kDmaRequestMuxACMP3
Definition: MIMXRT1166_cm7.h:1784
@ kDmaRequestMuxLPI2C4
Definition: MIMXRT1166_cm7.h:1765
#define SCR
Scratch register.
Definition: uart.h:94
#define MCR
Modem Control Register.
Definition: uart.h:91
#define MSR
Modem Status Register.
Definition: uart.h:93
_iomuxc_lpsr_sw_pad_ctl_pad
Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD.
Definition: MIMXRT1166_cm4.h:1380
enum _iomuxc_lpsr_sw_mux_ctl_pad iomuxc_lpsr_sw_mux_ctl_pad_t
Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD.
_iomuxc_lpsr_select_input
Enumeration for the IOMUXC_LPSR select input.
Definition: MIMXRT1166_cm4.h:1407
_iomuxc_lpsr_sw_mux_ctl_pad
Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD.
Definition: MIMXRT1166_cm4.h:1345
enum _iomuxc_lpsr_sw_pad_ctl_pad iomuxc_lpsr_sw_pad_ctl_pad_t
Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD.
enum _iomuxc_lpsr_select_input iomuxc_lpsr_select_input_t
Enumeration for the IOMUXC_LPSR select input.
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08
Definition: MIMXRT1166_cm7.h:1208
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10
Definition: MIMXRT1166_cm7.h:1210
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00
Definition: MIMXRT1166_cm7.h:1200
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06
Definition: MIMXRT1166_cm7.h:1206
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07
Definition: MIMXRT1166_cm7.h:1207
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05
Definition: MIMXRT1166_cm7.h:1205
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15
Definition: MIMXRT1166_cm7.h:1215
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03
Definition: MIMXRT1166_cm7.h:1203
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13
Definition: MIMXRT1166_cm7.h:1213
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12
Definition: MIMXRT1166_cm7.h:1212
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11
Definition: MIMXRT1166_cm7.h:1211
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02
Definition: MIMXRT1166_cm7.h:1202
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09
Definition: MIMXRT1166_cm7.h:1209
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04
Definition: MIMXRT1166_cm7.h:1204
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01
Definition: MIMXRT1166_cm7.h:1201
@ kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14
Definition: MIMXRT1166_cm7.h:1214
@ kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1228
@ kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1245
@ kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1227
@ kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1250
@ kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:1240
@ kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1230
@ kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1244
@ kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:1247
@ kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1235
@ kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1229
@ kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1237
@ kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1249
@ kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:1241
@ kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1236
@ kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1239
@ kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1248
@ kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3
Definition: MIMXRT1166_cm7.h:1243
@ kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1231
@ kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1234
@ kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1233
@ kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1238
@ kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2
Definition: MIMXRT1166_cm7.h:1242
@ kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:1232
@ kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:1246
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11
Definition: MIMXRT1166_cm7.h:1176
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07
Definition: MIMXRT1166_cm7.h:1172
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06
Definition: MIMXRT1166_cm7.h:1171
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00
Definition: MIMXRT1166_cm7.h:1165
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15
Definition: MIMXRT1166_cm7.h:1180
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02
Definition: MIMXRT1166_cm7.h:1167
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12
Definition: MIMXRT1166_cm7.h:1177
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01
Definition: MIMXRT1166_cm7.h:1166
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05
Definition: MIMXRT1166_cm7.h:1170
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09
Definition: MIMXRT1166_cm7.h:1174
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08
Definition: MIMXRT1166_cm7.h:1173
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04
Definition: MIMXRT1166_cm7.h:1169
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10
Definition: MIMXRT1166_cm7.h:1175
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03
Definition: MIMXRT1166_cm7.h:1168
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13
Definition: MIMXRT1166_cm7.h:1178
@ kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14
Definition: MIMXRT1166_cm7.h:1179
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:37461
__I uint32_t DDDR_MS
Definition: MIMXRT1166_cm7.h:11334
__IO uint16_t CAPTCOMPX
Definition: MIMXRT1166_cm7.h:68007
__I uint16_t CVAL5
Definition: MIMXRT1166_cm7.h:68018
__IO uint16_t FRACVAL4
Definition: MIMXRT1166_cm7.h:67988
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:37453
__IO uint32_t PX_SMAPR_PG0
Definition: MIMXRT1166_cm7.h:11057
__I uint32_t PX_SDID_PG0
Definition: MIMXRT1166_cm7.h:11056
__I uint32_t CONFIG
Definition: MIMXRT1166_cm7.h:20576
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:89691
__IO uint32_t LDVAL
Definition: MIMXRT1166_cm7.h:66839
__I uint32_t JRSTAR_JR
Definition: MIMXRT1166_cm7.h:11133
__IO uint16_t COMP1
Definition: MIMXRT1166_cm7.h:81315
__I uint32_t SMPO_JR
Definition: MIMXRT1166_cm7.h:11173
__IO uint32_t AUTHEN_SET
Definition: MIMXRT1166_cm7.h:20478
__IO uint32_t CONTROL_SET
Definition: MIMXRT1166_cm7.h:24454
__I uint32_t REIR4JR
Definition: MIMXRT1166_cm7.h:11163
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:37459
__I uint16_t CVAL3CYC
Definition: MIMXRT1166_cm7.h:68015
__I uint32_t RTFRQCNT
Definition: MIMXRT1166_cm7.h:11015
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:10723
__IO uint32_t SETPOINT
Definition: MIMXRT1166_cm7.h:20583
__IO uint32_t CPKNSZR
Definition: MIMXRT1166_cm7.h:11270
__IO uint16_t ATTR
Definition: MIMXRT1166_cm7.h:29221
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:10736
__I uint32_t RTSCR5C
Definition: MIMXRT1166_cm7.h:11021
__IO uint32_t CONTROL_CLR
Definition: MIMXRT1166_cm7.h:20487
__IO uint32_t AUTHEN_CLR
Definition: MIMXRT1166_cm7.h:24462
__IO uint16_t FRCTRL
Definition: MIMXRT1166_cm7.h:67992
__IO uint32_t DGTR_1
Definition: MIMXRT1166_cm7.h:11316
__IO uint16_t BITER_ELINKYES
Definition: MIMXRT1166_cm7.h:29238
__I uint16_t CVAL3
Definition: MIMXRT1166_cm7.h:68014
__IO uint32_t AUTHEN_TOG
Definition: MIMXRT1166_cm7.h:20480
__IO uint32_t ID
Definition: MIMXRT1166_cm7.h:17924
__IO uint32_t DESC_CTRL0
Definition: MIMXRT1166_cm7.h:80449
__I uint32_t CONFIG
Definition: MIMXRT1166_cm7.h:20476
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:89705
__IO uint32_t PAC_PDAC_W0
Definition: MIMXRT1166_cm7.h:92294
__IO uint32_t RTSCR2L
Definition: MIMXRT1166_cm7.h:11028
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:64111
__IO uint16_t CPINE
Definition: MIMXRT1166_cm7.h:71984
__IO uint32_t TRIGn_CHAIN_7_6
Definition: MIMXRT1166_cm7.h:3139
__IO uint32_t CTRLDESCL6
Definition: MIMXRT1166_cm7.h:57767
__IO uint32_t AUTHEN
Definition: MIMXRT1166_cm7.h:20506
__I uint32_t CAAMVID_MS_JR
Definition: MIMXRT1166_cm7.h:11187
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:89882
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:64103
__I uint32_t DMA_AIDL_MAP_LS
Definition: MIMXRT1166_cm7.h:10956
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:66732
__IO uint16_t CMPLD2
Definition: MIMXRT1166_cm7.h:81324
__I uint32_t RW
Definition: MIMXRT1166_cm7.h:64128
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:10727
__IO uint32_t IRSR_JR
Definition: MIMXRT1166_cm7.h:11120
__IO uint32_t RTSCR3L
Definition: MIMXRT1166_cm7.h:11029
__IO uint32_t MRC_MRGD_W1
Definition: MIMXRT1166_cm7.h:92299
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:89681
__I uint32_t FREQUENCY_MAX
Definition: MIMXRT1166_cm7.h:24466
__I uint32_t CRNR_LS_JR
Definition: MIMXRT1166_cm7.h:11167
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:66729
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:89896
__IO uint16_t CAPTCOMPB
Definition: MIMXRT1166_cm7.h:68005
__IO uint32_t JRCFGR_JR_LS
Definition: MIMXRT1166_cm7.h:11137
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:64098
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:10722
__IO uint16_t LOAD
Definition: MIMXRT1166_cm7.h:81318
__IO uint16_t FILT
Definition: MIMXRT1166_cm7.h:81326
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:89708
__IO uint32_t DADDR
Definition: MIMXRT1166_cm7.h:29228
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:66731
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:64110
__I uint32_t HT_JQ_CTRL_LS
Definition: MIMXRT1166_cm7.h:11078
__I uint32_t TRIGn_RESULT_5_4
Definition: MIMXRT1166_cm7.h:3142
__IO uint32_t RTSBLIM
Definition: MIMXRT1166_cm7.h:11009
__I uint16_t CVAL5CYC
Definition: MIMXRT1166_cm7.h:68019
__I uint32_t CHANUM_MS_JR
Definition: MIMXRT1166_cm7.h:11185
__I uint32_t DODIDSR
Definition: MIMXRT1166_cm7.h:11307
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:89707
__IO uint32_t RTIC_DID
Definition: MIMXRT1166_cm7.h:10932
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:37464
__I uint32_t TOG
Definition: MIMXRT1166_cm7.h:64137
__I uint32_t DOPSTA_LS
Definition: MIMXRT1166_cm7.h:11304
__IO uint32_t AUTHEN_TOG
Definition: MIMXRT1166_cm7.h:20509
__IO uint16_t BFCRT01
Definition: MIMXRT1166_cm7.h:9118
__I uint32_t CFIFOSTA
Definition: MIMXRT1166_cm7.h:11289
__I uint16_t CVAL2
Definition: MIMXRT1166_cm7.h:68012
__IO uint32_t SRAM1
Definition: MIMXRT1166_cm7.h:80328
__I uint32_t SET
Definition: MIMXRT1166_cm7.h:64129
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:37458
__I uint32_t STATUS0
Definition: MIMXRT1166_cm7.h:20574
__IO uint32_t AUTHEN_CLR
Definition: MIMXRT1166_cm7.h:20479
__IO uint32_t AUTHEN
Definition: MIMXRT1166_cm7.h:20577
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:66730
__I uint32_t RTSCR4C
Definition: MIMXRT1166_cm7.h:11020
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:37466
__I uint32_t RTSCR2C
Definition: MIMXRT1166_cm7.h:11018
__I uint32_t DJQCR_LS
Definition: MIMXRT1166_cm7.h:11301
__IO uint16_t STS
Definition: MIMXRT1166_cm7.h:67994
__IO uint32_t MDAC_MDA_W0
Definition: MIMXRT1166_cm7.h:92290
__I uint16_t CVAL2CYC
Definition: MIMXRT1166_cm7.h:68013
__IO uint16_t CNTR
Definition: MIMXRT1166_cm7.h:81320
__I uint32_t STATUS1
Definition: MIMXRT1166_cm7.h:20491
__IO uint32_t TRIGn_CHAIN_1_0
Definition: MIMXRT1166_cm7.h:3136
__IO uint32_t MRC_MRGD_W3
Definition: MIMXRT1166_cm7.h:92301
__IO uint32_t CS
Definition: MIMXRT1166_cm7.h:17930
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:89883
__IO uint32_t PIGEON_2
Definition: MIMXRT1166_cm7.h:55899
__IO uint32_t PAC_PDAC_W1
Definition: MIMXRT1166_cm7.h:92295
__IO uint32_t INT_ENABLE
Definition: MIMXRT1166_cm7.h:57756
__I uint32_t DCICRCS
Definition: MIMXRT1166_cm7.h:28937
__IO uint16_t VAL3
Definition: MIMXRT1166_cm7.h:67987
__I uint32_t SET
Definition: MIMXRT1166_cm7.h:66737
__IO uint32_t ID
Definition: MIMXRT1166_cm7.h:17918
__IO uint16_t DMA
Definition: MIMXRT1166_cm7.h:81327
__I uint32_t TRIGn_RESULT_7_6
Definition: MIMXRT1166_cm7.h:3143
__I uint16_t CNT
Definition: MIMXRT1166_cm7.h:67976
__IO uint32_t UVSOL
Definition: MIMXRT1166_cm7.h:11341
__I uint32_t CONFIG
Definition: MIMXRT1166_cm7.h:20493
__IO uint32_t AUTHEN
Definition: MIMXRT1166_cm7.h:20477
__I uint32_t TOG
Definition: MIMXRT1166_cm7.h:66739
__I uint32_t SMCSR_JR
Definition: MIMXRT1166_cm7.h:11158
__IO uint32_t DPOVRD
Definition: MIMXRT1166_cm7.h:11340
__IO uint16_t CAPTCTRLA
Definition: MIMXRT1166_cm7.h:68002
__IO uint32_t WORD0
Definition: MIMXRT1166_cm7.h:17944
__I uint64_t HT_SD_ADDR
Definition: MIMXRT1166_cm7.h:11076
__IO uint32_t AUTHEN
Definition: MIMXRT1166_cm7.h:20588
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:89879
__IO uint32_t AUTHEN_TOG
Definition: MIMXRT1166_cm7.h:24463
__IO uint16_t CSCTRL
Definition: MIMXRT1166_cm7.h:81325
__IO uint32_t CPKESZR
Definition: MIMXRT1166_cm7.h:11272
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:89895
__IO uint32_t CONTROL_CLR
Definition: MIMXRT1166_cm7.h:24455
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:89692
__IO uint32_t AUTHEN_CLR
Definition: MIMXRT1166_cm7.h:20508
__IO uint32_t CC1AADSZR
Definition: MIMXRT1166_cm7.h:11262
enum _iomuxc_select_input iomuxc_select_input_t
Enumeration for the IOMUXC select input.
__IO uint32_t VSOL
Definition: MIMXRT1166_cm7.h:11337
__I uint32_t CONFIG
Definition: MIMXRT1166_cm7.h:20587
__IO uint16_t DMAEN
Definition: MIMXRT1166_cm7.h:67996
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:64116
__I uint32_t RTSCR6PC
Definition: MIMXRT1166_cm7.h:11022
__IO uint32_t RTSCR6PL
Definition: MIMXRT1166_cm7.h:11032
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:20505
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:89885
__IO uint64_t CC2DSR
Definition: MIMXRT1166_cm7.h:11281
__IO uint32_t DEVICEADDR
Definition: MIMXRT1166_cm7.h:81896
__I uint64_t DDAR
Definition: MIMXRT1166_cm7.h:11302
__I uint16_t CVAL0
Definition: MIMXRT1166_cm7.h:68008
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:90078
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:64105
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:20504
__I uint32_t STATUS0
Definition: MIMXRT1166_cm7.h:24458
__IO uint32_t CTRLDESCL2
Definition: MIMXRT1166_cm7.h:57763
__IO uint32_t SETPOINT
Definition: MIMXRT1166_cm7.h:20572
__IO uint16_t INTEN
Definition: MIMXRT1166_cm7.h:67995
__IO uint32_t SIL
Definition: MIMXRT1166_cm7.h:11338
__I uint32_t CLR
Definition: MIMXRT1166_cm7.h:64136
__I uint32_t CVAL
Definition: MIMXRT1166_cm7.h:66840
__IO uint32_t NBYTES_MLOFFYES
Definition: MIMXRT1166_cm7.h:29225
__IO uint32_t JRSMVBAR
Definition: MIMXRT1166_cm7.h:10948
__IO uint32_t PX_SMAG1_JR
Definition: MIMXRT1166_cm7.h:11153
__I uint32_t FADR_JR
Definition: MIMXRT1166_cm7.h:11176
__I uint32_t DDDR
Definition: MIMXRT1166_cm7.h:11331
__I uint32_t RW
Definition: MIMXRT1166_cm7.h:90082
__IO uint64_t CC1DSR
Definition: MIMXRT1166_cm7.h:11250
_xbar_input_signal
Definition: MIMXRT1052.h:740
__IO uint32_t AUTHEN_SET
Definition: MIMXRT1166_cm7.h:20507
__IO uint32_t INT_STATUS
Definition: MIMXRT1166_cm7.h:57755
__I uint32_t JRAAV
Definition: MIMXRT1166_cm7.h:11145
__IO uint32_t ORWIR_JR
Definition: MIMXRT1166_cm7.h:11141
__I uint32_t CRNR_MS_JR
Definition: MIMXRT1166_cm7.h:11166
__IO uint32_t CONTROL_CLR
Definition: MIMXRT1166_cm7.h:20470
__IO uint32_t ENDPTLISTADDR
Definition: MIMXRT1166_cm7.h:81901
__IO uint32_t DIRECT
Definition: MIMXRT1166_cm7.h:20570
__IO uint32_t PX_SMAG1_PG0
Definition: MIMXRT1166_cm7.h:11059
__IO uint32_t DECODID_MS
Definition: MIMXRT1166_cm7.h:10940
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:37465
__I uint32_t CHAVID_MS_JR
Definition: MIMXRT1166_cm7.h:11183
__I uint32_t FREQUENCY_MIN
Definition: MIMXRT1166_cm7.h:24465
__IO uint32_t AUTHEN
Definition: MIMXRT1166_cm7.h:20494
__I uint32_t RTSCR1C
Definition: MIMXRT1166_cm7.h:11017
__I uint64_t DDJP
Definition: MIMXRT1166_cm7.h:11332
__IO uint32_t CONTROL
Definition: MIMXRT1166_cm7.h:20468
__IO uint32_t TIMER2_BC12
Definition: MIMXRT1166_cm7.h:83924
__IO int32_t DLAST_SGA
Definition: MIMXRT1166_cm7.h:29234
__I uint32_t RTSCMC
Definition: MIMXRT1166_cm7.h:11016
__IO uint32_t MRC_MRGD_W2
Definition: MIMXRT1166_cm7.h:92300
__IO uint16_t VAL1
Definition: MIMXRT1166_cm7.h:67983
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:89884
__I uint32_t TRIGn_RESULT_3_2
Definition: MIMXRT1166_cm7.h:3141
__IO uint32_t TCSR
Definition: MIMXRT1166_cm7.h:35283
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:89687
__IO uint32_t CS
Definition: MIMXRT1166_cm7.h:17917
__IO uint16_t CAPTCTRLB
Definition: MIMXRT1166_cm7.h:68004
__IO uint32_t CC1IVSZR
Definition: MIMXRT1166_cm7.h:11264
__IO uint16_t OCTRL
Definition: MIMXRT1166_cm7.h:67993
__O uint32_t CNFIFO
Definition: MIMXRT1166_cm7.h:11292
__IO uint16_t CAPTCTRLX
Definition: MIMXRT1166_cm7.h:68006
enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
__IO uint16_t VAL0
Definition: MIMXRT1166_cm7.h:67981
__IO uint32_t TRIGn_COUNTER
Definition: MIMXRT1166_cm7.h:3135
__I uint32_t RW
Definition: MIMXRT1166_cm7.h:66736
__IO uint16_t HOLD
Definition: MIMXRT1166_cm7.h:81319
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:37471
__IO uint32_t AUTHEN
Definition: MIMXRT1166_cm7.h:24460
__IO uint32_t AUTHEN_SET
Definition: MIMXRT1166_cm7.h:24461
__IO uint64_t IRBAR_JR
Definition: MIMXRT1166_cm7.h:11118
__IO uint32_t DOMAINr
Definition: MIMXRT1166_cm7.h:20571
_xbar_output_signal
Definition: MIMXRT1052.h:948
__IO uint32_t SRAM0
Definition: MIMXRT1166_cm7.h:80327
_iomuxc_sw_pad_ctl_pad
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
Definition: MIMXRT1052.h:447
__IO uint32_t RTSCR4L
Definition: MIMXRT1166_cm7.h:11030
__O uint32_t CIFIFO
Definition: MIMXRT1166_cm7.h:11296
__IO uint32_t TIMER2_BC11
Definition: MIMXRT1166_cm7.h:83923
__I uint32_t FUSE
Definition: MIMXRT1166_cm7.h:63312
__IO uint32_t DCICRC
Definition: MIMXRT1166_cm7.h:28934
__IO uint32_t DGTR_0
Definition: MIMXRT1166_cm7.h:11315
__IO uint32_t DESC_ADDR_UP
Definition: MIMXRT1166_cm7.h:80451
__IO uint16_t VAL4
Definition: MIMXRT1166_cm7.h:67989
__IO int32_t SLAST
Definition: MIMXRT1166_cm7.h:29227
__IO uint32_t ID
Definition: MIMXRT1166_cm7.h:17931
__IO uint32_t MRSA
Definition: MIMXRT1166_cm7.h:71321
__IO uint32_t TCTRL
Definition: MIMXRT1166_cm7.h:66841
__IO uint64_t RMA
Definition: MIMXRT1166_cm7.h:11205
__IO uint32_t ORSFR_JR
Definition: MIMXRT1166_cm7.h:11131
__IO uint32_t SADDR
Definition: MIMXRT1166_cm7.h:29219
__IO uint32_t RTFRQMAX
Definition: MIMXRT1166_cm7.h:11025
__IO uint32_t CC1ICVSR
Definition: MIMXRT1166_cm7.h:11252
__IO uint32_t CC1KSR
Definition: MIMXRT1166_cm7.h:11249
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:89894
__IO uint32_t CC1MR
Definition: MIMXRT1166_cm7.h:11244
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:10740
__I uint32_t SET
Definition: MIMXRT1166_cm7.h:64123
__I uint16_t CVAL1CYC
Definition: MIMXRT1166_cm7.h:68011
__IO uint32_t CC1MR_PK
Definition: MIMXRT1166_cm7.h:11245
__IO uint16_t CTRL
Definition: MIMXRT1166_cm7.h:67979
__IO uint32_t DSTR_2
Definition: MIMXRT1166_cm7.h:11324
__IO uint16_t CAPT
Definition: MIMXRT1166_cm7.h:81317
__IO uint32_t IRRIR_JR
Definition: MIMXRT1166_cm7.h:11139
__IO uint32_t SRAM2
Definition: MIMXRT1166_cm7.h:80329
__IO uint32_t CS
Definition: MIMXRT1166_cm7.h:17910
__IO uint32_t DCICRRS
Definition: MIMXRT1166_cm7.h:28936
__IO uint32_t CONTROL
Definition: MIMXRT1166_cm7.h:20485
__IO uint32_t CSC_COEF1
Definition: MIMXRT1166_cm7.h:57769
__I uint32_t RTPKRSQ
Definition: MIMXRT1166_cm7.h:11005
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:89889
enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
__IO uint32_t CONTROL_TOG
Definition: MIMXRT1166_cm7.h:20471
__IO uint32_t REGPO
Definition: MIMXRT1166_cm7.h:45635
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:89678
__I uint64_t FAR_JR
Definition: MIMXRT1166_cm7.h:11174
__IO uint32_t CONTROL_TOG
Definition: MIMXRT1166_cm7.h:24456
__I uint16_t CPNTF
Definition: MIMXRT1166_cm7.h:71989
_iomuxc_select_input
Enumeration for the IOMUXC select input.
Definition: MIMXRT1052.h:582
__IO uint32_t JRCFGR_JR_MS
Definition: MIMXRT1166_cm7.h:11136
__IO uint32_t CTRLDESCL4
Definition: MIMXRT1166_cm7.h:57765
__I uint32_t HT_STATUS
Definition: MIMXRT1166_cm7.h:11080
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:90075
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:37467
__O uint32_t CCCTRL
Definition: MIMXRT1166_cm7.h:11254
__I uint32_t FADID_JR
Definition: MIMXRT1166_cm7.h:11175
__IO uint16_t CTRL
Definition: MIMXRT1166_cm7.h:81321
__IO uint32_t DGTR_2
Definition: MIMXRT1166_cm7.h:11317
__IO uint32_t TRIGn_CHAIN_5_4
Definition: MIMXRT1166_cm7.h:3138
__I uint32_t RTTOTSAM
Definition: MIMXRT1166_cm7.h:11010
__IO uint32_t JRDID_MS
Definition: MIMXRT1166_cm7.h:10924
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:10728
__IO uint16_t BITER_ELINKNO
Definition: MIMXRT1166_cm7.h:29237
__O uint32_t SIC
Definition: MIMXRT1166_cm7.h:76245
__IO uint32_t AUTHEN_CLR
Definition: MIMXRT1166_cm7.h:20496
__I uint32_t SIS
Definition: MIMXRT1166_cm7.h:76246
__IO uint32_t DIRECT
Definition: MIMXRT1166_cm7.h:20581
__IO uint32_t CPKBSZR
Definition: MIMXRT1166_cm7.h:11268
__I uint16_t CVAL4
Definition: MIMXRT1166_cm7.h:68016
__IO uint32_t DCICRS
Definition: MIMXRT1166_cm7.h:28935
__I uint32_t CLR
Definition: MIMXRT1166_cm7.h:90084
__IO uint16_t COMP2
Definition: MIMXRT1166_cm7.h:81316
__IO uint32_t DECODID_LS
Definition: MIMXRT1166_cm7.h:10941
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:64109
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:89688
__I uint32_t CLR
Definition: MIMXRT1166_cm7.h:64130
__I uint32_t CTPR_LS_JR
Definition: MIMXRT1166_cm7.h:11169
__IO uint16_t SOFF
Definition: MIMXRT1166_cm7.h:29220
__IO uint32_t CTRLDESCL5
Definition: MIMXRT1166_cm7.h:57766
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:64100
__IO uint16_t SCTRL
Definition: MIMXRT1166_cm7.h:81322
__I uint32_t DDDR_LS
Definition: MIMXRT1166_cm7.h:11335
__I uint32_t FREQUENCY_CURRENT
Definition: MIMXRT1166_cm7.h:24464
__IO uint32_t ORSR_JR
Definition: MIMXRT1166_cm7.h:11127
__IO uint32_t CS
Definition: MIMXRT1166_cm7.h:17923
__IO uint32_t IRSAR_JR
Definition: MIMXRT1166_cm7.h:11122
__I uint32_t STATUS1
Definition: MIMXRT1166_cm7.h:20586
__IO uint32_t DESC_ADDR_DOWN
Definition: MIMXRT1166_cm7.h:80452
__O uint32_t SMCR_JR
Definition: MIMXRT1166_cm7.h:11156
__IO uint32_t CS
Definition: MIMXRT1166_cm7.h:17942
__I uint32_t CCBVID_JR
Definition: MIMXRT1166_cm7.h:11182
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:10741
__IO uint32_t REGATTR
Definition: MIMXRT1166_cm7.h:45633
__IO uint16_t CITER_ELINKNO
Definition: MIMXRT1166_cm7.h:29231
__O uint32_t CNFIFO_2
Definition: MIMXRT1166_cm7.h:11293
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:37454
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:89699
__IO uint16_t CAPTCOMPA
Definition: MIMXRT1166_cm7.h:68003
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:89680
__IO uint32_t AUTHEN_TOG
Definition: MIMXRT1166_cm7.h:20497
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:10721
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:37460
__I uint32_t CTPR_MS_JR
Definition: MIMXRT1166_cm7.h:11168
__IO uint32_t RGD_W1
Definition: MIMXRT1166_cm7.h:64322
__I uint32_t CHAVID_LS_JR
Definition: MIMXRT1166_cm7.h:11184
__IO uint32_t MREA
Definition: MIMXRT1166_cm7.h:71322
__IO uint32_t RTSCR1L
Definition: MIMXRT1166_cm7.h:11027
__O uint32_t JRCR_JR
Definition: MIMXRT1166_cm7.h:11143
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:37455
__IO uint32_t CSC_COEF2
Definition: MIMXRT1166_cm7.h:57770
__IO uint32_t TRIGn_CHAIN_3_2
Definition: MIMXRT1166_cm7.h:3137
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:64117
__IO uint16_t FRACVAL2
Definition: MIMXRT1166_cm7.h:67984
__I uint32_t TRIGn_RESULT_1_0
Definition: MIMXRT1166_cm7.h:3140
__IO uint32_t CS
Definition: MIMXRT1166_cm7.h:17936
__O uint32_t CCWR
Definition: MIMXRT1166_cm7.h:11258
__IO uint16_t VAL5
Definition: MIMXRT1166_cm7.h:67991
__IO uint32_t ID
Definition: MIMXRT1166_cm7.h:17937
__IO uint32_t MRC_MRGD_W0
Definition: MIMXRT1166_cm7.h:92298
__IO uint32_t MSC_MSAC_W0
Definition: MIMXRT1166_cm7.h:92285
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:37472
__IO uint16_t BFCRT23
Definition: MIMXRT1166_cm7.h:9119
__IO uint16_t RSTGT_R
Definition: MIMXRT1166_cm7.h:71634
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:10729
__IO uint32_t ID
Definition: MIMXRT1166_cm7.h:17911
__IO uint32_t TRIGn_CTRL
Definition: MIMXRT1166_cm7.h:3134
__I uint64_t COFIFO
Definition: MIMXRT1166_cm7.h:11298
__I uint32_t CLR
Definition: MIMXRT1166_cm7.h:66738
__IO uint32_t DJQCR_MS
Definition: MIMXRT1166_cm7.h:11300
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:10742
__IO uint32_t DSTR_3
Definition: MIMXRT1166_cm7.h:11325
__IO uint32_t ORJRR_JR
Definition: MIMXRT1166_cm7.h:11129
__IO uint32_t READ_FUSE_DATA
Definition: MIMXRT1166_cm7.h:63294
__I uint16_t CVAL4CYC
Definition: MIMXRT1166_cm7.h:68017
__IO uint32_t TFLG
Definition: MIMXRT1166_cm7.h:66842
__IO uint64_t ORBAR_JR
Definition: MIMXRT1166_cm7.h:11125
__IO uint16_t FRACVAL3
Definition: MIMXRT1166_cm7.h:67986
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:89890
__IO uint32_t RTPKRMAX
Definition: MIMXRT1166_cm7.h:11004
__IO uint32_t DOMAINr
Definition: MIMXRT1166_cm7.h:20582
__IO uint32_t CTRLDESCL3
Definition: MIMXRT1166_cm7.h:57764
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:89706
__I uint32_t DMA_AIDM_MAP_MS
Definition: MIMXRT1166_cm7.h:10957
__I uint32_t RTSCR3C
Definition: MIMXRT1166_cm7.h:11019
__IO uint16_t VAL2
Definition: MIMXRT1166_cm7.h:67985
__I uint32_t STATUS1
Definition: MIMXRT1166_cm7.h:20575
__IO uint32_t AUTHEN_SET
Definition: MIMXRT1166_cm7.h:20495
__I uint32_t DMA_AIDM_MAP_LS
Definition: MIMXRT1166_cm7.h:10958
__I uint32_t HT_JQ_CTRL_MS
Definition: MIMXRT1166_cm7.h:11077
__I uint32_t RW
Definition: MIMXRT1166_cm7.h:64134
__IO uint16_t DTCNT0
Definition: MIMXRT1166_cm7.h:68000
__I uint32_t CHANUM_LS_JR
Definition: MIMXRT1166_cm7.h:11186
__I uint32_t SMVID_MS_JR
Definition: MIMXRT1166_cm7.h:11179
__I uint32_t CCSTA_MS
Definition: MIMXRT1166_cm7.h:11259
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:64099
__I uint32_t DOPSTA_MS
Definition: MIMXRT1166_cm7.h:11303
__IO uint32_t CC2ICVSZR
Definition: MIMXRT1166_cm7.h:11283
__IO uint32_t RGD_W0
Definition: MIMXRT1166_cm7.h:64321
__IO uint32_t UVSIL
Definition: MIMXRT1166_cm7.h:11342
__IO uint16_t CSR
Definition: MIMXRT1166_cm7.h:29235
__IO uint32_t PERIODICLISTBASE
Definition: MIMXRT1166_cm7.h:81897
__IO uint32_t MDAC_MDA_W1
Definition: MIMXRT1166_cm7.h:92291
__I uint32_t SET
Definition: MIMXRT1166_cm7.h:90083
__IO uint32_t CC1MR_RNG
Definition: MIMXRT1166_cm7.h:11246
__I uint32_t DDJR
Definition: MIMXRT1166_cm7.h:11330
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:37470
__IO uint32_t DMTH_MS
Definition: MIMXRT1166_cm7.h:11310
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:89686
__IO uint16_t ENBL
Definition: MIMXRT1166_cm7.h:81329
__IO uint32_t PX_SMAG2_PG0
Definition: MIMXRT1166_cm7.h:11058
__I uint32_t RW
Definition: MIMXRT1166_cm7.h:64122
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:89700
__IO uint32_t NBYTES_MLNO
Definition: MIMXRT1166_cm7.h:29223
__IO uint32_t CS
Definition: MIMXRT1166_cm7.h:17898
__IO uint32_t VSIL
Definition: MIMXRT1166_cm7.h:11339
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:90076
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:89888
__IO uint32_t ID
Definition: MIMXRT1166_cm7.h:17905
__IO uint32_t DSTR_1
Definition: MIMXRT1166_cm7.h:11323
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:64118
__I uint16_t CVAL1
Definition: MIMXRT1166_cm7.h:68010
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:89698
__IO uint16_t CMPLD1
Definition: MIMXRT1166_cm7.h:81323
__I uint32_t SMVID_LS_JR
Definition: MIMXRT1166_cm7.h:11180
__IO uint32_t CICTL
Definition: MIMXRT1166_cm7.h:11256
__I uint32_t TOG
Definition: MIMXRT1166_cm7.h:64125
__I uint16_t CVAL0CYC
Definition: MIMXRT1166_cm7.h:68009
__IO uint32_t ID
Definition: MIMXRT1166_cm7.h:17899
__IO uint32_t CS
Definition: MIMXRT1166_cm7.h:17904
__I uint32_t CAAMVID_LS_JR
Definition: MIMXRT1166_cm7.h:11188
__IO uint32_t MRC_MRGD_W5
Definition: MIMXRT1166_cm7.h:92303
__IO uint32_t CC2MR
Definition: MIMXRT1166_cm7.h:11278
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:10733
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:90077
__IO uint32_t PX_SMAPR_JR
Definition: MIMXRT1166_cm7.h:11151
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:10735
__IO uint32_t CSC_COEF0
Definition: MIMXRT1166_cm7.h:57768
__IO uint16_t CTRL2
Definition: MIMXRT1166_cm7.h:67978
__IO uint32_t ID
Definition: MIMXRT1166_cm7.h:17943
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:89685
__IO uint32_t MSC_MSAC_W1
Definition: MIMXRT1166_cm7.h:92286
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:64104
__IO uint32_t GPR_SHARED
Definition: MIMXRT1166_cm7.h:20502
__I uint64_t DSDP
Definition: MIMXRT1166_cm7.h:11333
__I uint32_t TOG
Definition: MIMXRT1166_cm7.h:64131
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:10739
__IO uint32_t CONTROL_SET
Definition: MIMXRT1166_cm7.h:20486
__IO uint32_t CONTROL_TOG
Definition: MIMXRT1166_cm7.h:20488
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:89878
__IO uint32_t CPKASZR
Definition: MIMXRT1166_cm7.h:11266
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:89877
__I uint32_t DPDIDSR
Definition: MIMXRT1166_cm7.h:11306
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:64115
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:37452
__IO uint16_t INIT
Definition: MIMXRT1166_cm7.h:67977
__IO uint32_t RTSCR5L
Definition: MIMXRT1166_cm7.h:11031
__I uint32_t CCSTA_LS
Definition: MIMXRT1166_cm7.h:11260
__IO uint16_t CITER_ELINKYES
Definition: MIMXRT1166_cm7.h:29232
__IO uint16_t FRACVAL1
Definition: MIMXRT1166_cm7.h:67982
__IO uint16_t TCTRL
Definition: MIMXRT1166_cm7.h:67997
__I uint32_t SMSTA_JR
Definition: MIMXRT1166_cm7.h:11171
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:64112
__I uint32_t TOG
Definition: MIMXRT1166_cm7.h:90085
__IO uint32_t DSTR_0
Definition: MIMXRT1166_cm7.h:11322
__IO uint32_t SOL
Definition: MIMXRT1166_cm7.h:11336
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:64106
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:89897
__I uint32_t STATUS1
Definition: MIMXRT1166_cm7.h:20474
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:37473
__IO uint32_t PX_SMAG2_JR
Definition: MIMXRT1166_cm7.h:11152
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:20503
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:64097
__IO uint32_t CONTROL_SET
Definition: MIMXRT1166_cm7.h:20469
__I uint32_t DMA_AIDL_MAP_MS
Definition: MIMXRT1166_cm7.h:10955
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:89694
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:10724
__IO uint32_t IRJAR_JR
Definition: MIMXRT1166_cm7.h:11124
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:10730
__I uint32_t REIR5JR
Definition: MIMXRT1166_cm7.h:11164
__IO uint32_t JRINTR_JR
Definition: MIMXRT1166_cm7.h:11135
__I uint32_t RVID_JR
Definition: MIMXRT1166_cm7.h:11181
__IO uint32_t CMDH
Definition: MIMXRT1166_cm7.h:2431
__IO uint32_t MRC_MRGD_W6
Definition: MIMXRT1166_cm7.h:92304
__IO uint32_t DGTR_3
Definition: MIMXRT1166_cm7.h:11318
__I uint32_t SET
Definition: MIMXRT1166_cm7.h:64135
__I uint32_t STATUS0
Definition: MIMXRT1166_cm7.h:20585
__I uint64_t HT_JD_ADDR
Definition: MIMXRT1166_cm7.h:11075
__IO uint32_t CC2KSR
Definition: MIMXRT1166_cm7.h:11280
__IO uint32_t NBYTES_MLOFFNO
Definition: MIMXRT1166_cm7.h:29224
__IO uint32_t JRDID_LS
Definition: MIMXRT1166_cm7.h:10925
__IO uint32_t DESC_CTRL1
Definition: MIMXRT1166_cm7.h:80450
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:89701
__IO uint32_t RTSCML
Definition: MIMXRT1166_cm7.h:11026
__IO uint16_t FRACVAL5
Definition: MIMXRT1166_cm7.h:67990
__IO uint32_t CLR
Definition: MIMXRT1166_cm7.h:89693
__IO uint32_t RW
Definition: MIMXRT1166_cm7.h:89876
__IO uint32_t ASYNCLISTADDR
Definition: MIMXRT1166_cm7.h:81900
__IO uint16_t DTCNT1
Definition: MIMXRT1166_cm7.h:68001
__IO uint32_t MRC
Definition: MIMXRT1166_cm7.h:71323
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:10734
__IO uint32_t MRVS
Definition: MIMXRT1166_cm7.h:71324
__I uint32_t CLR
Definition: MIMXRT1166_cm7.h:64124
__IO uint32_t STATUS0
Definition: MIMXRT1166_cm7.h:20490
__I uint32_t STATUS0
Definition: MIMXRT1166_cm7.h:20473
__IO uint32_t CTRLDESCL1
Definition: MIMXRT1166_cm7.h:57762
__I uint32_t REIR0JR
Definition: MIMXRT1166_cm7.h:11160
__IO uint16_t RSTGT_W
Definition: MIMXRT1166_cm7.h:71635
__I uint32_t CSTA_JR
Definition: MIMXRT1166_cm7.h:11178
__IO uint32_t WORD1
Definition: MIMXRT1166_cm7.h:17945
__I uint64_t REIR2JR
Definition: MIMXRT1166_cm7.h:11162
__IO uint32_t CMDL
Definition: MIMXRT1166_cm7.h:2430
__IO uint32_t TOG
Definition: MIMXRT1166_cm7.h:89891
__IO uint32_t DMTH_LS
Definition: MIMXRT1166_cm7.h:11311
__IO uint32_t TCCR
Definition: MIMXRT1166_cm7.h:35284
__IO uint32_t PIGEON_1
Definition: MIMXRT1166_cm7.h:55897
__IO uint32_t SLOT_CTRL
Definition: MIMXRT1166_cm7.h:55242
_iomuxc_sw_mux_ctl_pad
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
Definition: MIMXRT1052.h:304
__IO uint32_t CONTROL
Definition: MIMXRT1166_cm7.h:24453
__IO uint16_t DOFF
Definition: MIMXRT1166_cm7.h:29229
__IO uint32_t PIGEON_0
Definition: MIMXRT1166_cm7.h:55895
__IO uint32_t SET
Definition: MIMXRT1166_cm7.h:89679
__IO uint32_t RML
Definition: MIMXRT1166_cm7.h:11207
__I uint32_t PX_SDID_JR
Definition: MIMXRT1166_cm7.h:11150
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06
Definition: MIMXRT1166_cm7.h:2066
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05
Definition: MIMXRT1166_cm7.h:2170
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03
Definition: MIMXRT1166_cm7.h:2105
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04
Definition: MIMXRT1166_cm7.h:2181
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06
Definition: MIMXRT1166_cm7.h:2129
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07
Definition: MIMXRT1166_cm7.h:2067
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14
Definition: MIMXRT1166_cm7.h:2137
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07
Definition: MIMXRT1166_cm7.h:2184
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09
Definition: MIMXRT1166_cm7.h:2132
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16
Definition: MIMXRT1166_cm7.h:2139
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19
Definition: MIMXRT1166_cm7.h:2121
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09
Definition: MIMXRT1166_cm7.h:2198
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13
Definition: MIMXRT1166_cm7.h:2115
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17
Definition: MIMXRT1166_cm7.h:2119
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27
Definition: MIMXRT1166_cm7.h:2150
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10
Definition: MIMXRT1166_cm7.h:2133
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09
Definition: MIMXRT1166_cm7.h:2069
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34
Definition: MIMXRT1166_cm7.h:2157
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12
Definition: MIMXRT1166_cm7.h:2114
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25
Definition: MIMXRT1166_cm7.h:2148
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13
Definition: MIMXRT1166_cm7.h:2136
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27
Definition: MIMXRT1166_cm7.h:2087
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00
Definition: MIMXRT1166_cm7.h:2123
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13
Definition: MIMXRT1166_cm7.h:2073
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09
Definition: MIMXRT1166_cm7.h:2174
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11
Definition: MIMXRT1166_cm7.h:2188
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20
Definition: MIMXRT1166_cm7.h:2143
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01
Definition: MIMXRT1166_cm7.h:2061
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21
Definition: MIMXRT1166_cm7.h:2081
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23
Definition: MIMXRT1166_cm7.h:2083
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01
Definition: MIMXRT1166_cm7.h:2190
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17
Definition: MIMXRT1166_cm7.h:2077
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06
Definition: MIMXRT1166_cm7.h:2171
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07
Definition: MIMXRT1166_cm7.h:2130
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04
Definition: MIMXRT1166_cm7.h:2169
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16
Definition: MIMXRT1166_cm7.h:2076
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00
Definition: MIMXRT1166_cm7.h:2102
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37
Definition: MIMXRT1166_cm7.h:2097
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31
Definition: MIMXRT1166_cm7.h:2154
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10
Definition: MIMXRT1166_cm7.h:2187
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04
Definition: MIMXRT1166_cm7.h:2064
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01
Definition: MIMXRT1166_cm7.h:2178
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01
Definition: MIMXRT1166_cm7.h:2124
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35
Definition: MIMXRT1166_cm7.h:2095
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30
Definition: MIMXRT1166_cm7.h:2090
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20
Definition: MIMXRT1166_cm7.h:2080
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25
Definition: MIMXRT1166_cm7.h:2085
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02
Definition: MIMXRT1166_cm7.h:2179
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19
Definition: MIMXRT1166_cm7.h:2079
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09
Definition: MIMXRT1166_cm7.h:2186
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40
Definition: MIMXRT1166_cm7.h:2100
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30
Definition: MIMXRT1166_cm7.h:2153
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08
Definition: MIMXRT1166_cm7.h:2173
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01
Definition: MIMXRT1166_cm7.h:2103
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04
Definition: MIMXRT1166_cm7.h:2163
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14
Definition: MIMXRT1166_cm7.h:2116
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08
Definition: MIMXRT1166_cm7.h:2068
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02
Definition: MIMXRT1166_cm7.h:2191
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18
Definition: MIMXRT1166_cm7.h:2120
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02
Definition: MIMXRT1166_cm7.h:2062
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00
Definition: MIMXRT1166_cm7.h:2177
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14
Definition: MIMXRT1166_cm7.h:2074
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33
Definition: MIMXRT1166_cm7.h:2156
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04
Definition: MIMXRT1166_cm7.h:2193
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05
Definition: MIMXRT1166_cm7.h:2107
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26
Definition: MIMXRT1166_cm7.h:2086
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15
Definition: MIMXRT1166_cm7.h:2138
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15
Definition: MIMXRT1166_cm7.h:2117
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13
Definition: MIMXRT1166_cm7.h:2202
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15
Definition: MIMXRT1166_cm7.h:2204
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00
Definition: MIMXRT1166_cm7.h:2159
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21
Definition: MIMXRT1166_cm7.h:2144
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26
Definition: MIMXRT1166_cm7.h:2149
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05
Definition: MIMXRT1166_cm7.h:2194
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24
Definition: MIMXRT1166_cm7.h:2147
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05
Definition: MIMXRT1166_cm7.h:2164
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08
Definition: MIMXRT1166_cm7.h:2185
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31
Definition: MIMXRT1166_cm7.h:2091
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06
Definition: MIMXRT1166_cm7.h:2183
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28
Definition: MIMXRT1166_cm7.h:2151
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07
Definition: MIMXRT1166_cm7.h:2196
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02
Definition: MIMXRT1166_cm7.h:2125
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05
Definition: MIMXRT1166_cm7.h:2065
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41
Definition: MIMXRT1166_cm7.h:2101
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11
Definition: MIMXRT1166_cm7.h:2134
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20
Definition: MIMXRT1166_cm7.h:2122
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11
Definition: MIMXRT1166_cm7.h:2113
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11
Definition: MIMXRT1166_cm7.h:2176
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16
Definition: MIMXRT1166_cm7.h:2118
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29
Definition: MIMXRT1166_cm7.h:2152
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00
Definition: MIMXRT1166_cm7.h:2165
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17
Definition: MIMXRT1166_cm7.h:2140
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01
Definition: MIMXRT1166_cm7.h:2166
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32
Definition: MIMXRT1166_cm7.h:2092
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10
Definition: MIMXRT1166_cm7.h:2112
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33
Definition: MIMXRT1166_cm7.h:2093
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35
Definition: MIMXRT1166_cm7.h:2158
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12
Definition: MIMXRT1166_cm7.h:2072
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07
Definition: MIMXRT1166_cm7.h:2172
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08
Definition: MIMXRT1166_cm7.h:2197
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39
Definition: MIMXRT1166_cm7.h:2099
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11
Definition: MIMXRT1166_cm7.h:2071
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06
Definition: MIMXRT1166_cm7.h:2108
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10
Definition: MIMXRT1166_cm7.h:2199
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22
Definition: MIMXRT1166_cm7.h:2082
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18
Definition: MIMXRT1166_cm7.h:2078
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07
Definition: MIMXRT1166_cm7.h:2109
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01
Definition: MIMXRT1166_cm7.h:2160
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00
Definition: MIMXRT1166_cm7.h:2060
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05
Definition: MIMXRT1166_cm7.h:2128
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23
Definition: MIMXRT1166_cm7.h:2146
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04
Definition: MIMXRT1166_cm7.h:2127
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32
Definition: MIMXRT1166_cm7.h:2155
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12
Definition: MIMXRT1166_cm7.h:2135
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02
Definition: MIMXRT1166_cm7.h:2161
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03
Definition: MIMXRT1166_cm7.h:2192
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28
Definition: MIMXRT1166_cm7.h:2088
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03
Definition: MIMXRT1166_cm7.h:2168
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18
Definition: MIMXRT1166_cm7.h:2141
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34
Definition: MIMXRT1166_cm7.h:2094
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19
Definition: MIMXRT1166_cm7.h:2142
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10
Definition: MIMXRT1166_cm7.h:2070
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14
Definition: MIMXRT1166_cm7.h:2203
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10
Definition: MIMXRT1166_cm7.h:2175
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22
Definition: MIMXRT1166_cm7.h:2145
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08
Definition: MIMXRT1166_cm7.h:2131
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05
Definition: MIMXRT1166_cm7.h:2182
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04
Definition: MIMXRT1166_cm7.h:2106
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03
Definition: MIMXRT1166_cm7.h:2063
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03
Definition: MIMXRT1166_cm7.h:2180
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38
Definition: MIMXRT1166_cm7.h:2098
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12
Definition: MIMXRT1166_cm7.h:2201
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03
Definition: MIMXRT1166_cm7.h:2126
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11
Definition: MIMXRT1166_cm7.h:2200
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02
Definition: MIMXRT1166_cm7.h:2104
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00
Definition: MIMXRT1166_cm7.h:2189
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09
Definition: MIMXRT1166_cm7.h:2111
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24
Definition: MIMXRT1166_cm7.h:2084
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06
Definition: MIMXRT1166_cm7.h:2195
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36
Definition: MIMXRT1166_cm7.h:2096
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03
Definition: MIMXRT1166_cm7.h:2162
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02
Definition: MIMXRT1166_cm7.h:2167
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29
Definition: MIMXRT1166_cm7.h:2089
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08
Definition: MIMXRT1166_cm7.h:2110
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15
Definition: MIMXRT1166_cm7.h:2075
@ kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2306
@ kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2266
@ kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2315
@ kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2331
@ kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2
Definition: MIMXRT1166_cm7.h:2258
@ kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:2242
@ kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2288
@ kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2314
@ kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2324
@ kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2299
@ kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3
Definition: MIMXRT1166_cm7.h:2298
@ kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2230
@ kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2
Definition: MIMXRT1166_cm7.h:2240
@ kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2312
@ kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2225
@ kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:2291
@ kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:2236
@ kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:2267
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_32
Definition: MIMXRT1166_cm7.h:2359
@ kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2300
@ kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:2252
@ kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3
Definition: MIMXRT1166_cm7.h:2259
@ kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2316
@ kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2
Definition: MIMXRT1166_cm7.h:2237
@ kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2282
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_24
Definition: MIMXRT1166_cm7.h:2351
@ kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2
Definition: MIMXRT1166_cm7.h:2262
@ kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2304
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_20
Definition: MIMXRT1166_cm7.h:2347
@ kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2
Definition: MIMXRT1166_cm7.h:2246
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_28
Definition: MIMXRT1166_cm7.h:2355
@ kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2283
@ kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2286
@ kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2327
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_22
Definition: MIMXRT1166_cm7.h:2349
@ kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2346
@ kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2313
@ kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2228
@ kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2
Definition: MIMXRT1166_cm7.h:2297
@ kIOMUXC_FLEXCAN2_RX_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2217
@ kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:2261
@ kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2307
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_23
Definition: MIMXRT1166_cm7.h:2350
@ kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2310
@ kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2270
@ kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:2239
@ kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2218
@ kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2222
@ kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2322
@ kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2279
@ kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2226
@ kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2235
@ kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2325
@ kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3
Definition: MIMXRT1166_cm7.h:2263
@ kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2238
@ kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2
Definition: MIMXRT1166_cm7.h:2243
@ kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2341
@ kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2
Definition: MIMXRT1166_cm7.h:2253
@ kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2234
@ kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2290
@ kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2294
@ kIOMUXC_GPT3_CAPIN1_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2271
@ kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2295
@ kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:2296
@ kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2251
@ kIOMUXC_FLEXCAN1_RX_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2216
@ kIOMUXC_USB_OTG_OC_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2340
@ kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2336
@ kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2301
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_21
Definition: MIMXRT1166_cm7.h:2348
@ kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2338
@ kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:2245
@ kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2311
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_25
Definition: MIMXRT1166_cm7.h:2352
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_26
Definition: MIMXRT1166_cm7.h:2353
@ kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2318
@ kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3
Definition: MIMXRT1166_cm7.h:2269
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_35
Definition: MIMXRT1166_cm7.h:2362
@ kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2302
@ kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2219
@ kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2329
@ kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2233
@ kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2241
@ kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2
Definition: MIMXRT1166_cm7.h:2249
@ kIOMUXC_GPT3_CLKIN_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2273
@ kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2260
@ kIOMUXC_EMVSIM2_SIO_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2335
@ kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2320
@ kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:2248
@ kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2278
@ kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2303
@ kIOMUXC_KPP_ROW_SELECT_INPUT_6
Definition: MIMXRT1166_cm7.h:2276
@ kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:2257
@ kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2330
@ kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2309
@ kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2220
@ kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1
Definition: MIMXRT1166_cm7.h:2221
@ kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2284
@ kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2343
@ kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2292
@ kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2333
@ kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2255
@ kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2231
@ kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2308
@ kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2232
@ kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2227
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_30
Definition: MIMXRT1166_cm7.h:2357
@ kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2342
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_29
Definition: MIMXRT1166_cm7.h:2356
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_27
Definition: MIMXRT1166_cm7.h:2354
@ kIOMUXC_KPP_ROW_SELECT_INPUT_7
Definition: MIMXRT1166_cm7.h:2277
@ kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2293
@ kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2317
@ kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2280
@ kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2326
@ kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2289
@ kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2229
@ kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2334
@ kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2244
@ kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2337
@ kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2223
@ kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3
Definition: MIMXRT1166_cm7.h:2250
@ kIOMUXC_GPT3_CAPIN2_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2272
@ kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2
Definition: MIMXRT1166_cm7.h:2268
@ kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2224
@ kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2321
@ kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2319
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_33
Definition: MIMXRT1166_cm7.h:2360
@ kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2281
@ kIOMUXC_USB_OTG2_OC_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2339
@ kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2328
@ kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2344
@ kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2285
@ kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2287
@ kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2264
@ kIOMUXC_EMVSIM1_SIO_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2332
@ kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2345
@ kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2265
@ kIOMUXC_KPP_COL_SELECT_INPUT_7
Definition: MIMXRT1166_cm7.h:2275
@ kIOMUXC_KPP_COL_SELECT_INPUT_6
Definition: MIMXRT1166_cm7.h:2274
@ kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2247
@ kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2323
@ kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3
Definition: MIMXRT1166_cm7.h:2254
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_31
Definition: MIMXRT1166_cm7.h:2358
@ kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0
Definition: MIMXRT1166_cm7.h:2256
@ kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT
Definition: MIMXRT1166_cm7.h:2305
@ kIOMUXC_XBAR1_IN_SELECT_INPUT_34
Definition: MIMXRT1166_cm7.h:2361
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14
Definition: MIMXRT1166_cm7.h:1952
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34
Definition: MIMXRT1166_cm7.h:1930
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00
Definition: MIMXRT1166_cm7.h:2025
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14
Definition: MIMXRT1166_cm7.h:2039
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00
Definition: MIMXRT1166_cm7.h:2001
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09
Definition: MIMXRT1166_cm7.h:2034
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04
Definition: MIMXRT1166_cm7.h:2005
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25
Definition: MIMXRT1166_cm7.h:1921
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08
Definition: MIMXRT1166_cm7.h:1967
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10
Definition: MIMXRT1166_cm7.h:1969
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12
Definition: MIMXRT1166_cm7.h:1971
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17
Definition: MIMXRT1166_cm7.h:1955
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12
Definition: MIMXRT1166_cm7.h:1950
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15
Definition: MIMXRT1166_cm7.h:1953
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01
Definition: MIMXRT1166_cm7.h:2026
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13
Definition: MIMXRT1166_cm7.h:1972
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29
Definition: MIMXRT1166_cm7.h:1925
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09
Definition: MIMXRT1166_cm7.h:1968
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03
Definition: MIMXRT1166_cm7.h:2028
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26
Definition: MIMXRT1166_cm7.h:1922
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33
Definition: MIMXRT1166_cm7.h:1992
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19
Definition: MIMXRT1166_cm7.h:1957
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10
Definition: MIMXRT1166_cm7.h:1906
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27
Definition: MIMXRT1166_cm7.h:1923
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18
Definition: MIMXRT1166_cm7.h:1977
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27
Definition: MIMXRT1166_cm7.h:1986
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15
Definition: MIMXRT1166_cm7.h:1974
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00
Definition: MIMXRT1166_cm7.h:1938
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06
Definition: MIMXRT1166_cm7.h:2031
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08
Definition: MIMXRT1166_cm7.h:2033
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32
Definition: MIMXRT1166_cm7.h:1928
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10
Definition: MIMXRT1166_cm7.h:1948
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06
Definition: MIMXRT1166_cm7.h:1902
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05
Definition: MIMXRT1166_cm7.h:2018
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08
Definition: MIMXRT1166_cm7.h:1904
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28
Definition: MIMXRT1166_cm7.h:1924
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29
Definition: MIMXRT1166_cm7.h:1988
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35
Definition: MIMXRT1166_cm7.h:1931
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10
Definition: MIMXRT1166_cm7.h:2023
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24
Definition: MIMXRT1166_cm7.h:1920
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15
Definition: MIMXRT1166_cm7.h:2040
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15
Definition: MIMXRT1166_cm7.h:1911
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11
Definition: MIMXRT1166_cm7.h:1970
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04
Definition: MIMXRT1166_cm7.h:2017
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03
Definition: MIMXRT1166_cm7.h:1998
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06
Definition: MIMXRT1166_cm7.h:2007
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02
Definition: MIMXRT1166_cm7.h:2015
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03
Definition: MIMXRT1166_cm7.h:1962
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10
Definition: MIMXRT1166_cm7.h:2035
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03
Definition: MIMXRT1166_cm7.h:1899
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07
Definition: MIMXRT1166_cm7.h:1966
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31
Definition: MIMXRT1166_cm7.h:1927
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11
Definition: MIMXRT1166_cm7.h:1907
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17
Definition: MIMXRT1166_cm7.h:1913
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06
Definition: MIMXRT1166_cm7.h:1944
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06
Definition: MIMXRT1166_cm7.h:1965
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19
Definition: MIMXRT1166_cm7.h:1978
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00
Definition: MIMXRT1166_cm7.h:2013
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18
Definition: MIMXRT1166_cm7.h:1914
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05
Definition: MIMXRT1166_cm7.h:2030
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16
Definition: MIMXRT1166_cm7.h:1975
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18
Definition: MIMXRT1166_cm7.h:1956
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02
Definition: MIMXRT1166_cm7.h:2003
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04
Definition: MIMXRT1166_cm7.h:1963
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01
Definition: MIMXRT1166_cm7.h:1939
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00
Definition: MIMXRT1166_cm7.h:1995
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12
Definition: MIMXRT1166_cm7.h:2037
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30
Definition: MIMXRT1166_cm7.h:1926
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07
Definition: MIMXRT1166_cm7.h:1945
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09
Definition: MIMXRT1166_cm7.h:2010
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05
Definition: MIMXRT1166_cm7.h:1901
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20
Definition: MIMXRT1166_cm7.h:1916
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11
Definition: MIMXRT1166_cm7.h:1949
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21
Definition: MIMXRT1166_cm7.h:1980
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35
Definition: MIMXRT1166_cm7.h:1994
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26
Definition: MIMXRT1166_cm7.h:1985
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20
Definition: MIMXRT1166_cm7.h:1958
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11
Definition: MIMXRT1166_cm7.h:2036
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01
Definition: MIMXRT1166_cm7.h:1897
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36
Definition: MIMXRT1166_cm7.h:1932
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21
Definition: MIMXRT1166_cm7.h:1917
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22
Definition: MIMXRT1166_cm7.h:1981
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04
Definition: MIMXRT1166_cm7.h:1999
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17
Definition: MIMXRT1166_cm7.h:1976
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23
Definition: MIMXRT1166_cm7.h:1982
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02
Definition: MIMXRT1166_cm7.h:2027
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09
Definition: MIMXRT1166_cm7.h:1947
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00
Definition: MIMXRT1166_cm7.h:1896
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33
Definition: MIMXRT1166_cm7.h:1929
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23
Definition: MIMXRT1166_cm7.h:1919
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24
Definition: MIMXRT1166_cm7.h:1983
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34
Definition: MIMXRT1166_cm7.h:1993
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01
Definition: MIMXRT1166_cm7.h:1960
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05
Definition: MIMXRT1166_cm7.h:1964
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07
Definition: MIMXRT1166_cm7.h:2008
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25
Definition: MIMXRT1166_cm7.h:1984
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05
Definition: MIMXRT1166_cm7.h:2006
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32
Definition: MIMXRT1166_cm7.h:1991
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31
Definition: MIMXRT1166_cm7.h:1990
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01
Definition: MIMXRT1166_cm7.h:2002
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14
Definition: MIMXRT1166_cm7.h:1910
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04
Definition: MIMXRT1166_cm7.h:1900
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07
Definition: MIMXRT1166_cm7.h:2020
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38
Definition: MIMXRT1166_cm7.h:1934
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20
Definition: MIMXRT1166_cm7.h:1979
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16
Definition: MIMXRT1166_cm7.h:1912
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07
Definition: MIMXRT1166_cm7.h:1903
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40
Definition: MIMXRT1166_cm7.h:1936
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16
Definition: MIMXRT1166_cm7.h:1954
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14
Definition: MIMXRT1166_cm7.h:1973
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13
Definition: MIMXRT1166_cm7.h:2038
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22
Definition: MIMXRT1166_cm7.h:1918
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03
Definition: MIMXRT1166_cm7.h:2016
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03
Definition: MIMXRT1166_cm7.h:1941
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01
Definition: MIMXRT1166_cm7.h:1996
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11
Definition: MIMXRT1166_cm7.h:2024
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41
Definition: MIMXRT1166_cm7.h:1937
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08
Definition: MIMXRT1166_cm7.h:1946
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07
Definition: MIMXRT1166_cm7.h:2032
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04
Definition: MIMXRT1166_cm7.h:1942
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05
Definition: MIMXRT1166_cm7.h:1943
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08
Definition: MIMXRT1166_cm7.h:2009
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05
Definition: MIMXRT1166_cm7.h:2000
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02
Definition: MIMXRT1166_cm7.h:1997
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30
Definition: MIMXRT1166_cm7.h:1989
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09
Definition: MIMXRT1166_cm7.h:1905
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12
Definition: MIMXRT1166_cm7.h:1908
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11
Definition: MIMXRT1166_cm7.h:2012
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13
Definition: MIMXRT1166_cm7.h:1951
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19
Definition: MIMXRT1166_cm7.h:1915
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02
Definition: MIMXRT1166_cm7.h:1940
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06
Definition: MIMXRT1166_cm7.h:2019
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03
Definition: MIMXRT1166_cm7.h:2004
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01
Definition: MIMXRT1166_cm7.h:2014
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10
Definition: MIMXRT1166_cm7.h:2011
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00
Definition: MIMXRT1166_cm7.h:1959
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13
Definition: MIMXRT1166_cm7.h:1909
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02
Definition: MIMXRT1166_cm7.h:1898
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28
Definition: MIMXRT1166_cm7.h:1987
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08
Definition: MIMXRT1166_cm7.h:2021
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04
Definition: MIMXRT1166_cm7.h:2029
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39
Definition: MIMXRT1166_cm7.h:1935
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02
Definition: MIMXRT1166_cm7.h:1961
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09
Definition: MIMXRT1166_cm7.h:2022
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37
Definition: MIMXRT1166_cm7.h:1933
_rdc_periph
Definition: MIMXRT1166_cm4.h:455
enum _rdc_master rdc_master_t
Structure for the RDC mapping.
_rdc_master
Structure for the RDC mapping.
Definition: MIMXRT1166_cm4.h:377
@ kRDC_Periph_WDOG1
Definition: MIMXRT1166_cm7.h:467
@ kRDC_Periph_LPI2C2
Definition: MIMXRT1166_cm7.h:505
@ kRDC_Periph_ENC1
Definition: MIMXRT1166_cm7.h:520
@ kRDC_Periph_OCOTP_CTRL_WRAPPER
Definition: MIMXRT1166_cm7.h:585
@ kRDC_Periph_ENET
Definition: MIMXRT1166_cm7.h:543
@ kRDC_Periph_USDHC1
Definition: MIMXRT1166_cm7.h:540
@ kRDC_Periph_GPT3
Definition: MIMXRT1166_cm7.h:500
@ kRDC_Periph_WDOG3
Definition: MIMXRT1166_cm7.h:469
@ kRDC_Periph_CAAM_2
Definition: MIMXRT1166_cm7.h:528
@ kRDC_Periph_EWM
Definition: MIMXRT1166_cm7.h:466
@ kRDC_Periph_ADC2
Definition: MIMXRT1166_cm7.h:474
@ kRDC_Periph_LPI2C1
Definition: MIMXRT1166_cm7.h:504
@ kRDC_Periph_LPUART7
Definition: MIMXRT1166_cm7.h:486
@ kRDC_Periph_QTIMER2
Definition: MIMXRT1166_cm7.h:517
@ kRDC_Periph_LPSPI2
Definition: MIMXRT1166_cm7.h:509
@ kRDC_Periph_LPUART1
Definition: MIMXRT1166_cm7.h:480
@ kRDC_Periph_GPT1
Definition: MIMXRT1166_cm7.h:498
@ kRDC_Periph_CAAM_5
Definition: MIMXRT1166_cm7.h:550
@ kRDC_Periph_QTIMER1
Definition: MIMXRT1166_cm7.h:516
@ kRDC_Periph_GPIO_1_6
Definition: MIMXRT1166_cm7.h:512
@ kRDC_Periph_TSC_DIG
Definition: MIMXRT1166_cm7.h:475
@ kRDC_Periph_IOMUXC
Definition: MIMXRT1166_cm7.h:497
@ kRDC_Periph_USBPHY1
Definition: MIMXRT1166_cm7.h:547
@ kRDC_Periph_FLEXSPI2
Definition: MIMXRT1166_cm7.h:463
@ kRDC_Periph_SAI1
Definition: MIMXRT1166_cm7.h:536
@ kRDC_Periph_IOMUXC_SNVS_GPR
Definition: MIMXRT1166_cm7.h:580
@ kRDC_Periph_ADC1
Definition: MIMXRT1166_cm7.h:473
@ kRDC_Periph_KEY_MANAGER
Definition: MIMXRT1166_cm7.h:576
@ kRDC_Periph_CAAM_3
Definition: MIMXRT1166_cm7.h:529
@ kRDC_Periph_ROMCP
Definition: MIMXRT1166_cm7.h:583
@ kRDC_Periph_LPSPI4
Definition: MIMXRT1166_cm7.h:511
@ kRDC_Periph_PXP
Definition: MIMXRT1166_cm7.h:556
@ kRDC_Periph_ACMP4
Definition: MIMXRT1166_cm7.h:533
@ kRDC_Periph_ENET_QOS
Definition: MIMXRT1166_cm7.h:549
@ kRDC_Periph_CAN3
Definition: MIMXRT1166_cm7.h:572
@ kRDC_Periph_VIDEO_MUX
Definition: MIMXRT1166_cm7.h:557
@ kRDC_Periph_USDHC2
Definition: MIMXRT1166_cm7.h:541
@ kRDC_Periph_SIM2
Definition: MIMXRT1166_cm7.h:515
@ kRDC_Periph_SEMA1
Definition: MIMXRT1166_cm7.h:574
@ kRDC_Periph_ACMP3
Definition: MIMXRT1166_cm7.h:532
@ kRDC_Periph_ADC_ETC
Definition: MIMXRT1166_cm7.h:471
@ kRDC_Periph_IOMUXC_LPSR
Definition: MIMXRT1166_cm7.h:559
@ kRDC_Periph_LPUART12
Definition: MIMXRT1166_cm7.h:567
@ kRDC_Periph_AOI_XBAR
Definition: MIMXRT1166_cm7.h:470
@ kRDC_Periph_LPSPI3
Definition: MIMXRT1166_cm7.h:510
@ kRDC_Periph_GPT2
Definition: MIMXRT1166_cm7.h:499
@ kRDC_Periph_CAAM
Definition: MIMXRT1166_cm7.h:534
@ kRDC_Periph_ENC4
Definition: MIMXRT1166_cm7.h:523
@ kRDC_Periph_SPDIF
Definition: MIMXRT1166_cm7.h:535
@ kRDC_Periph_WDOG4
Definition: MIMXRT1166_cm7.h:561
@ kRDC_Periph_LPI2C6
Definition: MIMXRT1166_cm7.h:571
@ kRDC_Periph_LPUART11
Definition: MIMXRT1166_cm7.h:566
@ kRDC_Periph_CCM_OBS
Definition: MIMXRT1166_cm7.h:513
@ kRDC_Periph_LCDIF1
Definition: MIMXRT1166_cm7.h:552
@ kRDC_Periph_LPI2C5
Definition: MIMXRT1166_cm7.h:570
@ kRDC_Periph_CAAM_1
Definition: MIMXRT1166_cm7.h:472
@ kRDC_Periph_ENC2
Definition: MIMXRT1166_cm7.h:521
@ kRDC_Periph_DAC
Definition: MIMXRT1166_cm7.h:476
@ kRDC_Periph_QTIMER3
Definition: MIMXRT1166_cm7.h:518
@ kRDC_Periph_FLEXPWM4
Definition: MIMXRT1166_cm7.h:527
@ kRDC_Periph_IOMUXC_LPSR_GPR
Definition: MIMXRT1166_cm7.h:560
@ kRDC_Periph_FLEXPWM3
Definition: MIMXRT1166_cm7.h:526
@ kRDC_Periph_ACMP1
Definition: MIMXRT1166_cm7.h:530
@ kRDC_Periph_CM7_IMXRT
Definition: MIMXRT1166_cm7.h:465
@ kRDC_Periph_USBPHY2
Definition: MIMXRT1166_cm7.h:545
@ kRDC_Periph_FLEXPWM1
Definition: MIMXRT1166_cm7.h:524
@ kRDC_Periph_LPI2C3
Definition: MIMXRT1166_cm7.h:506
@ kRDC_Periph_CAN2
Definition: MIMXRT1166_cm7.h:493
@ kRDC_Periph_GPIO_7_12
Definition: MIMXRT1166_cm7.h:575
@ kRDC_Periph_GPT5
Definition: MIMXRT1166_cm7.h:502
@ kRDC_Periph_SAI2
Definition: MIMXRT1166_cm7.h:537
@ kRDC_Periph_LPI2C4
Definition: MIMXRT1166_cm7.h:507
@ kRDC_Periph_LCDIF2
Definition: MIMXRT1166_cm7.h:553
@ kRDC_Periph_QTIMER4
Definition: MIMXRT1166_cm7.h:519
@ kRDC_Periph_GPT4
Definition: MIMXRT1166_cm7.h:501
@ kRDC_Periph_MTR
Definition: MIMXRT1166_cm7.h:459
@ kRDC_Periph_CAAM_6
Definition: MIMXRT1166_cm7.h:589
@ kRDC_Periph_KPP
Definition: MIMXRT1166_cm7.h:495
@ kRDC_Periph_LPUART6
Definition: MIMXRT1166_cm7.h:485
@ kRDC_Periph_LPSPI5
Definition: MIMXRT1166_cm7.h:568
@ kRDC_Periph_DMAMUX
Definition: MIMXRT1166_cm7.h:478
@ kRDC_Periph_LPUART8
Definition: MIMXRT1166_cm7.h:487
@ kRDC_Periph_PIT2
Definition: MIMXRT1166_cm7.h:586
@ kRDC_Periph_ENET_1G
Definition: MIMXRT1166_cm7.h:542
@ kRDC_Periph_DMAMUX_LPSR
Definition: MIMXRT1166_cm7.h:562
@ kRDC_Periph_LPUART10
Definition: MIMXRT1166_cm7.h:489
@ kRDC_Periph_WDOG2
Definition: MIMXRT1166_cm7.h:468
@ kRDC_Periph_LPSPI1
Definition: MIMXRT1166_cm7.h:508
@ kRDC_Periph_DCDC
Definition: MIMXRT1166_cm7.h:584
@ kRDC_Periph_USB_PL301
Definition: MIMXRT1166_cm7.h:544
@ kRDC_Periph_MIC
Definition: MIMXRT1166_cm7.h:565
@ kRDC_Periph_MIPI_CSI
Definition: MIMXRT1166_cm7.h:555
@ kRDC_Periph_USB_OTG2
Definition: MIMXRT1166_cm7.h:546
@ kRDC_Periph_PIT1
Definition: MIMXRT1166_cm7.h:494
@ kRDC_Periph_ACMP2
Definition: MIMXRT1166_cm7.h:531
@ kRDC_Periph_FLEXPWM2
Definition: MIMXRT1166_cm7.h:525
@ kRDC_Periph_EDMA
Definition: MIMXRT1166_cm7.h:479
@ kRDC_Periph_SAI4
Definition: MIMXRT1166_cm7.h:573
@ kRDC_Periph_LPUART9
Definition: MIMXRT1166_cm7.h:488
@ kRDC_Periph_GPT6
Definition: MIMXRT1166_cm7.h:503
@ kRDC_Periph_SAI3
Definition: MIMXRT1166_cm7.h:538
@ kRDC_Periph_USB_OTG1
Definition: MIMXRT1166_cm7.h:548
@ kRDC_Periph_LPUART4
Definition: MIMXRT1166_cm7.h:483
@ kRDC_Periph_FLEXIO2
Definition: MIMXRT1166_cm7.h:491
@ kRDC_Periph_SSARC
Definition: MIMXRT1166_cm7.h:587
@ kRDC_Periph_IOMUXC_GPR
Definition: MIMXRT1166_cm7.h:496
@ kRDC_Periph_GPIO13
Definition: MIMXRT1166_cm7.h:582
@ kRDC_Periph_CSI
Definition: MIMXRT1166_cm7.h:551
@ kRDC_Periph_CCM
Definition: MIMXRT1166_cm7.h:588
@ kRDC_Periph_Reserved
Definition: MIMXRT1166_cm7.h:564
@ kRDC_Periph_IOMUXC_SNVS
Definition: MIMXRT1166_cm7.h:579
@ kRDC_Periph_SNVS_HP_WRAPPER
Definition: MIMXRT1166_cm7.h:578
@ kRDC_Periph_IEE
Definition: MIMXRT1166_cm7.h:477
@ kRDC_Periph_MIPI_DSI
Definition: MIMXRT1166_cm7.h:554
@ kRDC_Periph_PGMC_SRC_GPC
Definition: MIMXRT1166_cm7.h:558
@ kRDC_Periph_CAAM_7
Definition: MIMXRT1166_cm7.h:590
@ kRDC_Periph_ENC3
Definition: MIMXRT1166_cm7.h:522
@ kRDC_Periph_EDMA_LPSR
Definition: MIMXRT1166_cm7.h:563
@ kRDC_Periph_FLEXSPI1
Definition: MIMXRT1166_cm7.h:462
@ kRDC_Periph_CAN1
Definition: MIMXRT1166_cm7.h:492
@ kRDC_Periph_LPUART3
Definition: MIMXRT1166_cm7.h:482
@ kRDC_Periph_LPUART5
Definition: MIMXRT1166_cm7.h:484
@ kRDC_Periph_ANATOP
Definition: MIMXRT1166_cm7.h:577
@ kRDC_Periph_MECC2
Definition: MIMXRT1166_cm7.h:461
@ kRDC_Periph_MECC1
Definition: MIMXRT1166_cm7.h:460
@ kRDC_Periph_SIM1
Definition: MIMXRT1166_cm7.h:514
@ kRDC_Periph_FLEXIO1
Definition: MIMXRT1166_cm7.h:490
@ kRDC_Periph_ASRC
Definition: MIMXRT1166_cm7.h:539
@ kRDC_Periph_SNVS_SRAM
Definition: MIMXRT1166_cm7.h:581
@ kRDC_Periph_SEMC
Definition: MIMXRT1166_cm7.h:464
@ kRDC_Periph_LPUART2
Definition: MIMXRT1166_cm7.h:481
@ kRDC_Periph_LPSPI6
Definition: MIMXRT1166_cm7.h:569
@ kXBARB2_InputAcmp1Out
Definition: MIMXRT1166_cm7.h:743
@ kXBARB2_InputQtimer4Timer3
Definition: MIMXRT1166_cm7.h:766
@ kXBARA1_InputDmaDone7
Definition: MIMXRT1166_cm7.h:716
@ kXBARA1_InputDmaDone6
Definition: MIMXRT1166_cm7.h:715
@ kXBARB2_InputRESERVED69
Definition: MIMXRT1166_cm7.h:810
@ kXBARA1_InputIomuxXbarInout33
Definition: MIMXRT1166_cm7.h:630
@ kXBARB2_InputPit1Trigger0
Definition: MIMXRT1166_cm7.h:799
@ kXBARB3_InputDmaDone3
Definition: MIMXRT1166_cm7.h:924
@ kXBARA1_InputDmaLpsrDone5
Definition: MIMXRT1166_cm7.h:722
@ kXBARB2_InputQtimer1Timer2
Definition: MIMXRT1166_cm7.h:753
@ kXBARB2_InputRESERVED52
Definition: MIMXRT1166_cm7.h:793
@ kXBARB2_InputDmaDone4
Definition: MIMXRT1166_cm7.h:827
@ kXBARB2_InputDmaLpsrDone1
Definition: MIMXRT1166_cm7.h:832
@ kXBARA1_InputAoi2Out1
Definition: MIMXRT1166_cm7.h:730
@ kXBARB3_InputFlexpwm4Pwm3OutTrig01
Definition: MIMXRT1166_cm7.h:888
@ kXBARA1_InputRESERVED71
Definition: MIMXRT1166_cm7.h:668
@ kXBARB3_InputRESERVED29
Definition: MIMXRT1166_cm7.h:868
@ kXBARB3_InputDec3PosMatch
Definition: MIMXRT1166_cm7.h:917
@ kXBARB3_InputRESERVED54
Definition: MIMXRT1166_cm7.h:893
@ kXBARB2_InputDec2PosMatch
Definition: MIMXRT1166_cm7.h:818
@ kXBARA1_InputIomuxXbarInout14
Definition: MIMXRT1166_cm7.h:611
@ kXBARB3_InputFlexpwm3Pwm0OutTrig01
Definition: MIMXRT1166_cm7.h:881
@ kXBARB2_InputAdcEtc0Coco2
Definition: MIMXRT1166_cm7.h:803
@ kXBARA1_InputDec1PosMatch
Definition: MIMXRT1166_cm7.h:703
@ kXBARB2_InputRESERVED70
Definition: MIMXRT1166_cm7.h:811
@ kXBARA1_InputPit1Trigger3
Definition: MIMXRT1166_cm7.h:702
@ kXBARA1_InputAdcEtc0Coco0
Definition: MIMXRT1166_cm7.h:733
@ kXBARB2_InputAdcEtc0Coco3
Definition: MIMXRT1166_cm7.h:804
@ kXBARA1_InputFlexpwm1Pwm0OutTrig1
Definition: MIMXRT1166_cm7.h:672
@ kXBARB3_InputDmaLpsrDone0
Definition: MIMXRT1166_cm7.h:929
@ kXBARB2_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1166_cm7.h:782
@ kXBARB2_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1166_cm7.h:776
@ kXBARB3_InputQtimer3Timer2
Definition: MIMXRT1166_cm7.h:859
@ kXBARB3_InputRESERVED30
Definition: MIMXRT1166_cm7.h:869
@ kXBARA1_InputFlexpwm1Pwm3OutTrig0
Definition: MIMXRT1166_cm7.h:677
@ kXBARA1_InputAdcEtc1Coco2
Definition: MIMXRT1166_cm7.h:739
@ kXBARA1_InputQtimer4Timer1
Definition: MIMXRT1166_cm7.h:660
@ kXBARA1_InputQtimer2Timer0
Definition: MIMXRT1166_cm7.h:651
@ kXBARB3_InputRESERVED75
Definition: MIMXRT1166_cm7.h:914
@ kXBARB3_InputQtimer3Timer3
Definition: MIMXRT1166_cm7.h:860
@ kXBARB2_InputRESERVED80
Definition: MIMXRT1166_cm7.h:821
@ kXBARA1_InputIomuxXbarInout05
Definition: MIMXRT1166_cm7.h:602
@ kXBARB2_InputRESERVED9
Definition: MIMXRT1166_cm7.h:750
@ kXBARB2_InputDmaLpsrDone7
Definition: MIMXRT1166_cm7.h:838
@ kXBARB3_InputAcmp1Out
Definition: MIMXRT1166_cm7.h:841
@ kXBARB3_InputPit1Trigger0
Definition: MIMXRT1166_cm7.h:897
@ kXBARB3_InputAcmp2Out
Definition: MIMXRT1166_cm7.h:842
@ kXBARB3_InputRESERVED33
Definition: MIMXRT1166_cm7.h:872
@ kXBARA1_InputIomuxXbarInout29
Definition: MIMXRT1166_cm7.h:626
@ kXBARA1_InputDmaDone0
Definition: MIMXRT1166_cm7.h:709
@ kXBARB2_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1166_cm7.h:778
@ kXBARA1_InputIomuxXbarInout17
Definition: MIMXRT1166_cm7.h:614
@ kXBARA1_InputFlexpwm1Pwm2OutTrig1
Definition: MIMXRT1166_cm7.h:676
@ kXBARA1_InputAoi2Out0
Definition: MIMXRT1166_cm7.h:729
@ kXBARB3_InputRESERVED57
Definition: MIMXRT1166_cm7.h:896
@ kXBARA1_InputIomuxXbarInout06
Definition: MIMXRT1166_cm7.h:603
@ kXBARB2_InputQtimer3Timer2
Definition: MIMXRT1166_cm7.h:761
@ kXBARA1_InputDmaLpsrDone6
Definition: MIMXRT1166_cm7.h:723
@ kXBARB2_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1166_cm7.h:781
@ kXBARA1_InputIomuxXbarInout28
Definition: MIMXRT1166_cm7.h:625
@ kXBARB2_InputRESERVED73
Definition: MIMXRT1166_cm7.h:814
@ kXBARB2_InputPit1Trigger1
Definition: MIMXRT1166_cm7.h:800
@ kXBARA1_InputAoi1Out0
Definition: MIMXRT1166_cm7.h:725
@ kXBARB3_InputDmaDone1
Definition: MIMXRT1166_cm7.h:922
@ kXBARA1_InputIomuxXbarInout11
Definition: MIMXRT1166_cm7.h:608
@ kXBARA1_InputFlexpwm1Pwm3OutTrig1
Definition: MIMXRT1166_cm7.h:678
@ kXBARB2_InputFlexpwm3Pwm3OutTrig01
Definition: MIMXRT1166_cm7.h:786
@ kXBARB3_InputDmaLpsrDone7
Definition: MIMXRT1166_cm7.h:936
@ kXBARA1_InputIomuxXbarInout18
Definition: MIMXRT1166_cm7.h:615
@ kXBARA1_InputFlexpwm3Pwm1OutTrig01
Definition: MIMXRT1166_cm7.h:684
@ kXBARA1_InputRESERVED98
Definition: MIMXRT1166_cm7.h:695
@ kXBARA1_InputIomuxXbarInout22
Definition: MIMXRT1166_cm7.h:619
@ kXBARA1_InputRESERVED69
Definition: MIMXRT1166_cm7.h:666
@ kXBARB2_InputAdcEtc0Coco1
Definition: MIMXRT1166_cm7.h:802
@ kXBARB2_InputDmaDone3
Definition: MIMXRT1166_cm7.h:826
@ kXBARA1_InputIomuxXbarInout26
Definition: MIMXRT1166_cm7.h:623
@ kXBARB2_InputRESERVED57
Definition: MIMXRT1166_cm7.h:798
@ kXBARB3_InputDec1PosMatch
Definition: MIMXRT1166_cm7.h:915
@ kXBARB2_InputRESERVED33
Definition: MIMXRT1166_cm7.h:774
@ kXBARB2_InputAdcEtc1Coco3
Definition: MIMXRT1166_cm7.h:808
@ kXBARB3_InputFlexpwm3Pwm1OutTrig01
Definition: MIMXRT1166_cm7.h:882
@ kXBARA1_InputIomuxXbarInout21
Definition: MIMXRT1166_cm7.h:618
@ kXBARB2_InputRESERVED81
Definition: MIMXRT1166_cm7.h:822
@ kXBARB3_InputDmaLpsrDone6
Definition: MIMXRT1166_cm7.h:935
@ kXBARA1_InputQtimer2Timer1
Definition: MIMXRT1166_cm7.h:652
@ kXBARB3_InputRESERVED31
Definition: MIMXRT1166_cm7.h:870
@ kXBARA1_InputIomuxXbarInout36
Definition: MIMXRT1166_cm7.h:633
@ kXBARB2_InputDmaDone7
Definition: MIMXRT1166_cm7.h:830
@ kXBARA1_InputQtimer4Timer3
Definition: MIMXRT1166_cm7.h:662
@ kXBARB2_InputRESERVED8
Definition: MIMXRT1166_cm7.h:749
@ kXBARB2_InputQtimer2Timer0
Definition: MIMXRT1166_cm7.h:755
@ kXBARB2_InputAcmp2Out
Definition: MIMXRT1166_cm7.h:744
@ kXBARA1_InputPit1Trigger2
Definition: MIMXRT1166_cm7.h:701
@ kXBARB2_InputRESERVED68
Definition: MIMXRT1166_cm7.h:809
@ kXBARB2_InputQtimer2Timer1
Definition: MIMXRT1166_cm7.h:756
@ kXBARB2_InputFlexpwm3Pwm2OutTrig01
Definition: MIMXRT1166_cm7.h:785
@ kXBARA1_InputIomuxXbarInout34
Definition: MIMXRT1166_cm7.h:631
@ kXBARB2_InputRESERVED7
Definition: MIMXRT1166_cm7.h:748
@ kXBARA1_InputAdcEtc0Coco2
Definition: MIMXRT1166_cm7.h:735
@ kXBARB2_InputRESERVED55
Definition: MIMXRT1166_cm7.h:796
@ kXBARB3_InputQtimer2Timer3
Definition: MIMXRT1166_cm7.h:856
@ kXBARB2_InputDmaDone2
Definition: MIMXRT1166_cm7.h:825
@ kXBARB2_InputRESERVED71
Definition: MIMXRT1166_cm7.h:812
@ kXBARB3_InputLogicLow
Definition: MIMXRT1166_cm7.h:839
@ kXBARB2_InputQtimer4Timer1
Definition: MIMXRT1166_cm7.h:764
@ kXBARB3_InputDec2PosMatch
Definition: MIMXRT1166_cm7.h:916
@ kXBARB2_InputQtimer4Timer2
Definition: MIMXRT1166_cm7.h:765
@ kXBARB3_InputDmaLpsrDone3
Definition: MIMXRT1166_cm7.h:932
@ kXBARB2_InputDmaDone5
Definition: MIMXRT1166_cm7.h:828
@ kXBARA1_InputRESERVED3
Definition: MIMXRT1166_cm7.h:600
@ kXBARA1_InputAoi2Out3
Definition: MIMXRT1166_cm7.h:732
@ kXBARB2_InputDmaLpsrDone5
Definition: MIMXRT1166_cm7.h:836
@ kXBARB3_InputAdcEtc1Coco2
Definition: MIMXRT1166_cm7.h:905
@ kXBARB3_InputFlexpwm4Pwm0OutTrig01
Definition: MIMXRT1166_cm7.h:885
@ kXBARB3_InputRESERVED80
Definition: MIMXRT1166_cm7.h:919
@ kXBARA1_InputIomuxXbarInout30
Definition: MIMXRT1166_cm7.h:627
@ kXBARA1_InputLogicLow
Definition: MIMXRT1166_cm7.h:597
@ kXBARA1_InputQtimer4Timer0
Definition: MIMXRT1166_cm7.h:659
@ kXBARA1_InputIomuxXbarInout16
Definition: MIMXRT1166_cm7.h:613
@ kXBARB3_InputRESERVED50
Definition: MIMXRT1166_cm7.h:889
@ kXBARB3_InputDmaLpsrDone4
Definition: MIMXRT1166_cm7.h:933
@ kXBARB3_InputRESERVED26
Definition: MIMXRT1166_cm7.h:865
@ kXBARA1_InputFlexpwm1Pwm2OutTrig0
Definition: MIMXRT1166_cm7.h:675
@ kXBARB3_InputDmaDone7
Definition: MIMXRT1166_cm7.h:928
@ kXBARB3_InputDmaDone0
Definition: MIMXRT1166_cm7.h:921
@ kXBARA1_InputQtimer1Timer3
Definition: MIMXRT1166_cm7.h:650
@ kXBARB3_InputRESERVED81
Definition: MIMXRT1166_cm7.h:920
@ kXBARB2_InputRESERVED51
Definition: MIMXRT1166_cm7.h:792
@ kXBARB3_InputRESERVED71
Definition: MIMXRT1166_cm7.h:910
@ kXBARB2_InputDec4PosMatch
Definition: MIMXRT1166_cm7.h:820
@ kXBARA1_InputRESERVED68
Definition: MIMXRT1166_cm7.h:665
@ kXBARA1_InputIomuxXbarInout24
Definition: MIMXRT1166_cm7.h:621
@ kXBARB3_InputRESERVED32
Definition: MIMXRT1166_cm7.h:871
@ kXBARA1_InputAcmp4Out
Definition: MIMXRT1166_cm7.h:642
@ kXBARB3_InputRESERVED74
Definition: MIMXRT1166_cm7.h:913
@ kXBARB2_InputRESERVED26
Definition: MIMXRT1166_cm7.h:767
@ kXBARA1_InputAdcEtc1Coco3
Definition: MIMXRT1166_cm7.h:740
@ kXBARA1_InputIomuxXbarInout07
Definition: MIMXRT1166_cm7.h:604
@ kXBARA1_InputDec3PosMatch
Definition: MIMXRT1166_cm7.h:705
@ kXBARA1_InputIomuxXbarInout38
Definition: MIMXRT1166_cm7.h:635
@ kXBARB3_InputAdcEtc0Coco2
Definition: MIMXRT1166_cm7.h:901
@ kXBARB2_InputQtimer1Timer0
Definition: MIMXRT1166_cm7.h:751
@ kXBARA1_InputRESERVED48
Definition: MIMXRT1166_cm7.h:645
@ kXBARB2_InputRESERVED31
Definition: MIMXRT1166_cm7.h:772
@ kXBARB2_InputAdcEtc1Coco2
Definition: MIMXRT1166_cm7.h:807
@ kXBARA1_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1166_cm7.h:682
@ kXBARB2_InputRESERVED56
Definition: MIMXRT1166_cm7.h:797
@ kXBARA1_InputFlexpwm3Pwm2OutTrig01
Definition: MIMXRT1166_cm7.h:685
@ kXBARA1_InputDmaDone4
Definition: MIMXRT1166_cm7.h:713
@ kXBARA1_InputDmaLpsrDone1
Definition: MIMXRT1166_cm7.h:718
@ kXBARB3_InputDmaDone6
Definition: MIMXRT1166_cm7.h:927
@ kXBARA1_InputRESERVED47
Definition: MIMXRT1166_cm7.h:644
@ kXBARA1_InputPit1Trigger0
Definition: MIMXRT1166_cm7.h:699
@ kXBARA1_InputQtimer1Timer1
Definition: MIMXRT1166_cm7.h:648
@ kXBARB2_InputDmaDone0
Definition: MIMXRT1166_cm7.h:823
@ kXBARB3_InputDmaLpsrDone1
Definition: MIMXRT1166_cm7.h:930
@ kXBARB3_InputFlexpwm4Pwm1OutTrig01
Definition: MIMXRT1166_cm7.h:886
@ kXBARB2_InputQtimer3Timer3
Definition: MIMXRT1166_cm7.h:762
@ kXBARB2_InputDmaLpsrDone0
Definition: MIMXRT1166_cm7.h:831
@ kXBARA1_InputFlexpwm4Pwm2OutTrig01
Definition: MIMXRT1166_cm7.h:689
@ kXBARA1_InputIomuxXbarInout39
Definition: MIMXRT1166_cm7.h:636
@ kXBARA1_InputFlexpwm4Pwm0OutTrig01
Definition: MIMXRT1166_cm7.h:687
@ kXBARA1_InputRESERVED94
Definition: MIMXRT1166_cm7.h:691
@ kXBARB3_InputRESERVED9
Definition: MIMXRT1166_cm7.h:848
@ kXBARB2_InputRESERVED54
Definition: MIMXRT1166_cm7.h:795
@ kXBARB2_InputDmaDone6
Definition: MIMXRT1166_cm7.h:829
@ kXBARA1_InputAcmp2Out
Definition: MIMXRT1166_cm7.h:640
@ kXBARB2_InputFlexpwm3Pwm1OutTrig01
Definition: MIMXRT1166_cm7.h:784
@ kXBARA1_InputRESERVED66
Definition: MIMXRT1166_cm7.h:663
@ kXBARB3_InputLogicHigh
Definition: MIMXRT1166_cm7.h:840
@ kXBARA1_InputDmaLpsrDone2
Definition: MIMXRT1166_cm7.h:719
@ kXBARB3_InputRESERVED28
Definition: MIMXRT1166_cm7.h:867
@ kXBARA1_InputIomuxXbarInout37
Definition: MIMXRT1166_cm7.h:634
@ kXBARA1_InputRESERVED95
Definition: MIMXRT1166_cm7.h:692
@ kXBARA1_InputAcmp3Out
Definition: MIMXRT1166_cm7.h:641
@ kXBARB2_InputFlexpwm4Pwm0OutTrig01
Definition: MIMXRT1166_cm7.h:787
@ kXBARB3_InputAdcEtc1Coco0
Definition: MIMXRT1166_cm7.h:903
@ kXBARA1_InputIomuxXbarInout32
Definition: MIMXRT1166_cm7.h:629
@ kXBARA1_InputFlexpwm3Pwm0OutTrig01
Definition: MIMXRT1166_cm7.h:683
@ kXBARA1_InputQtimer4Timer2
Definition: MIMXRT1166_cm7.h:661
@ kXBARB3_InputQtimer4Timer0
Definition: MIMXRT1166_cm7.h:861
@ kXBARB2_InputFlexpwm4Pwm3OutTrig01
Definition: MIMXRT1166_cm7.h:790
@ kXBARB3_InputQtimer2Timer1
Definition: MIMXRT1166_cm7.h:854
@ kXBARB2_InputFlexpwm4Pwm2OutTrig01
Definition: MIMXRT1166_cm7.h:789
@ kXBARB2_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1166_cm7.h:780
@ kXBARA1_InputAdcEtc1Coco1
Definition: MIMXRT1166_cm7.h:738
@ kXBARB2_InputFlexpwm1Pwm0OutTrig01
Definition: MIMXRT1166_cm7.h:775
@ kXBARA1_InputAoi1Out3
Definition: MIMXRT1166_cm7.h:728
@ kXBARB3_InputQtimer3Timer1
Definition: MIMXRT1166_cm7.h:858
@ kXBARB2_InputAcmp4Out
Definition: MIMXRT1166_cm7.h:746
@ kXBARA1_InputAdcEtc0Coco3
Definition: MIMXRT1166_cm7.h:736
@ kXBARB3_InputDec4PosMatch
Definition: MIMXRT1166_cm7.h:918
@ kXBARB2_InputDmaLpsrDone6
Definition: MIMXRT1166_cm7.h:837
@ kXBARB3_InputDmaLpsrDone2
Definition: MIMXRT1166_cm7.h:931
@ kXBARB3_InputRESERVED56
Definition: MIMXRT1166_cm7.h:895
@ kXBARB2_InputRESERVED32
Definition: MIMXRT1166_cm7.h:773
@ kXBARB2_InputRESERVED6
Definition: MIMXRT1166_cm7.h:747
@ kXBARB2_InputQtimer1Timer3
Definition: MIMXRT1166_cm7.h:754
@ kXBARB3_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1166_cm7.h:874
@ kXBARB3_InputRESERVED8
Definition: MIMXRT1166_cm7.h:847
@ kXBARB3_InputRESERVED6
Definition: MIMXRT1166_cm7.h:845
@ kXBARB2_InputRESERVED50
Definition: MIMXRT1166_cm7.h:791
@ kXBARA1_InputAcmp1Out
Definition: MIMXRT1166_cm7.h:639
@ kXBARA1_InputIomuxXbarInout10
Definition: MIMXRT1166_cm7.h:607
@ kXBARA1_InputDec4PosMatch
Definition: MIMXRT1166_cm7.h:706
@ kXBARB3_InputAdcEtc1Coco3
Definition: MIMXRT1166_cm7.h:906
@ kXBARB3_InputAdcEtc0Coco1
Definition: MIMXRT1166_cm7.h:900
@ kXBARA1_InputAdcEtc1Coco0
Definition: MIMXRT1166_cm7.h:737
@ kXBARB3_InputRESERVED52
Definition: MIMXRT1166_cm7.h:891
@ kXBARB2_InputQtimer2Timer2
Definition: MIMXRT1166_cm7.h:757
@ kXBARB2_InputDmaLpsrDone4
Definition: MIMXRT1166_cm7.h:835
@ kXBARA1_InputQtimer1Timer2
Definition: MIMXRT1166_cm7.h:649
@ kXBARB3_InputPit1Trigger1
Definition: MIMXRT1166_cm7.h:898
@ kXBARB3_InputRESERVED7
Definition: MIMXRT1166_cm7.h:846
@ kXBARB2_InputRESERVED28
Definition: MIMXRT1166_cm7.h:769
@ kXBARB3_InputQtimer1Timer3
Definition: MIMXRT1166_cm7.h:852
@ kXBARB3_InputFlexpwm3Pwm2OutTrig01
Definition: MIMXRT1166_cm7.h:883
@ kXBARA1_InputRESERVED46
Definition: MIMXRT1166_cm7.h:643
@ kXBARB2_InputRESERVED72
Definition: MIMXRT1166_cm7.h:813
@ kXBARA1_InputFlexpwm1Pwm1OutTrig1
Definition: MIMXRT1166_cm7.h:674
@ kXBARB3_InputFlexpwm2Pwm0OutTrig01
Definition: MIMXRT1166_cm7.h:877
@ kXBARB3_InputFlexpwm1Pwm0OutTrig01
Definition: MIMXRT1166_cm7.h:873
@ kXBARB2_InputRESERVED53
Definition: MIMXRT1166_cm7.h:794
@ kXBARA1_InputIomuxXbarInout12
Definition: MIMXRT1166_cm7.h:609
@ kXBARA1_InputQtimer2Timer3
Definition: MIMXRT1166_cm7.h:654
@ kXBARB2_InputAdcEtc1Coco0
Definition: MIMXRT1166_cm7.h:805
@ kXBARA1_InputRESERVED97
Definition: MIMXRT1166_cm7.h:694
@ kXBARA1_InputIomuxXbarInout27
Definition: MIMXRT1166_cm7.h:624
@ kXBARA1_InputRESERVED101
Definition: MIMXRT1166_cm7.h:698
@ kXBARB2_InputDec3PosMatch
Definition: MIMXRT1166_cm7.h:819
@ kXBARB3_InputQtimer3Timer0
Definition: MIMXRT1166_cm7.h:857
@ kXBARA1_InputIomuxXbarInout31
Definition: MIMXRT1166_cm7.h:628
@ kXBARA1_InputRESERVED67
Definition: MIMXRT1166_cm7.h:664
@ kXBARA1_InputIomuxXbarInout35
Definition: MIMXRT1166_cm7.h:632
@ kXBARB2_InputAdcEtc1Coco1
Definition: MIMXRT1166_cm7.h:806
@ kXBARA1_InputQtimer3Timer3
Definition: MIMXRT1166_cm7.h:658
@ kXBARB2_InputAcmp3Out
Definition: MIMXRT1166_cm7.h:745
@ kXBARA1_InputRESERVED49
Definition: MIMXRT1166_cm7.h:646
@ kXBARB3_InputAdcEtc0Coco0
Definition: MIMXRT1166_cm7.h:899
@ kXBARB2_InputFlexpwm3Pwm0OutTrig01
Definition: MIMXRT1166_cm7.h:783
@ kXBARB3_InputRESERVED27
Definition: MIMXRT1166_cm7.h:866
@ kXBARB3_InputFlexpwm3Pwm3OutTrig01
Definition: MIMXRT1166_cm7.h:884
@ kXBARB3_InputFlexpwm4Pwm2OutTrig01
Definition: MIMXRT1166_cm7.h:887
@ kXBARB2_InputDmaLpsrDone2
Definition: MIMXRT1166_cm7.h:833
@ kXBARB2_InputRESERVED74
Definition: MIMXRT1166_cm7.h:815
@ kXBARA1_InputAdcEtc0Coco1
Definition: MIMXRT1166_cm7.h:734
@ kXBARB3_InputRESERVED73
Definition: MIMXRT1166_cm7.h:912
@ kXBARB3_InputQtimer1Timer1
Definition: MIMXRT1166_cm7.h:850
@ kXBARB3_InputRESERVED53
Definition: MIMXRT1166_cm7.h:892
@ kXBARA1_InputIomuxXbarInout40
Definition: MIMXRT1166_cm7.h:637
@ kXBARB3_InputDmaDone4
Definition: MIMXRT1166_cm7.h:925
@ kXBARA1_InputDmaDone5
Definition: MIMXRT1166_cm7.h:714
@ kXBARB3_InputQtimer2Timer2
Definition: MIMXRT1166_cm7.h:855
@ kXBARB2_InputLogicLow
Definition: MIMXRT1166_cm7.h:741
@ kXBARA1_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1166_cm7.h:681
@ kXBARB2_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1166_cm7.h:777
@ kXBARA1_InputAoi1Out1
Definition: MIMXRT1166_cm7.h:726
@ kXBARA1_InputRESERVED110
Definition: MIMXRT1166_cm7.h:707
@ kXBARA1_InputRESERVED41
Definition: MIMXRT1166_cm7.h:638
@ kXBARB2_InputDmaLpsrDone3
Definition: MIMXRT1166_cm7.h:834
@ kXBARB2_InputDec1PosMatch
Definition: MIMXRT1166_cm7.h:817
@ kXBARA1_InputRESERVED70
Definition: MIMXRT1166_cm7.h:667
@ kXBARA1_InputAoi1Out2
Definition: MIMXRT1166_cm7.h:727
@ kXBARB2_InputQtimer1Timer1
Definition: MIMXRT1166_cm7.h:752
@ kXBARA1_InputDmaDone3
Definition: MIMXRT1166_cm7.h:712
@ kXBARA1_InputFlexpwm4Pwm3OutTrig01
Definition: MIMXRT1166_cm7.h:690
@ kXBARA1_InputIomuxXbarInout08
Definition: MIMXRT1166_cm7.h:605
@ kXBARB3_InputAcmp4Out
Definition: MIMXRT1166_cm7.h:844
@ kXBARA1_InputIomuxXbarInout13
Definition: MIMXRT1166_cm7.h:610
@ kXBARB2_InputRESERVED30
Definition: MIMXRT1166_cm7.h:771
@ kXBARA1_InputRESERVED99
Definition: MIMXRT1166_cm7.h:696
@ kXBARA1_InputPit1Trigger1
Definition: MIMXRT1166_cm7.h:700
@ kXBARB3_InputRESERVED51
Definition: MIMXRT1166_cm7.h:890
@ kXBARB3_InputRESERVED69
Definition: MIMXRT1166_cm7.h:908
@ kXBARB3_InputQtimer4Timer2
Definition: MIMXRT1166_cm7.h:863
@ kXBARB3_InputAdcEtc0Coco3
Definition: MIMXRT1166_cm7.h:902
@ kXBARB3_InputDmaDone2
Definition: MIMXRT1166_cm7.h:923
@ kXBARB2_InputQtimer3Timer0
Definition: MIMXRT1166_cm7.h:759
@ kXBARB2_InputAdcEtc0Coco0
Definition: MIMXRT1166_cm7.h:801
@ kXBARB3_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1166_cm7.h:880
@ kXBARB3_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1166_cm7.h:878
@ kXBARA1_InputDec2PosMatch
Definition: MIMXRT1166_cm7.h:704
@ kXBARB2_InputQtimer3Timer1
Definition: MIMXRT1166_cm7.h:760
@ kXBARA1_InputDmaLpsrDone4
Definition: MIMXRT1166_cm7.h:721
@ kXBARA1_InputRESERVED73
Definition: MIMXRT1166_cm7.h:670
@ kXBARA1_InputIomuxXbarInout20
Definition: MIMXRT1166_cm7.h:617
@ kXBARA1_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1166_cm7.h:680
@ kXBARA1_InputLogicHigh
Definition: MIMXRT1166_cm7.h:598
@ kXBARB3_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1166_cm7.h:876
@ kXBARA1_InputIomuxXbarInout04
Definition: MIMXRT1166_cm7.h:601
@ kXBARB3_InputRESERVED72
Definition: MIMXRT1166_cm7.h:911
@ kXBARB3_InputRESERVED55
Definition: MIMXRT1166_cm7.h:894
@ kXBARB2_InputFlexpwm4Pwm1OutTrig01
Definition: MIMXRT1166_cm7.h:788
@ kXBARA1_InputFlexpwm4Pwm1OutTrig01
Definition: MIMXRT1166_cm7.h:688
@ kXBARA1_InputDmaLpsrDone3
Definition: MIMXRT1166_cm7.h:720
@ kXBARB2_InputLogicHigh
Definition: MIMXRT1166_cm7.h:742
@ kXBARB2_InputFlexpwm2Pwm0OutTrig01
Definition: MIMXRT1166_cm7.h:779
@ kXBARA1_InputDmaLpsrDone7
Definition: MIMXRT1166_cm7.h:724
@ kXBARB3_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1166_cm7.h:875
@ kXBARB3_InputRESERVED68
Definition: MIMXRT1166_cm7.h:907
@ kXBARA1_InputIomuxXbarInout19
Definition: MIMXRT1166_cm7.h:616
@ kXBARB3_InputRESERVED70
Definition: MIMXRT1166_cm7.h:909
@ kXBARA1_InputDmaLpsrDone0
Definition: MIMXRT1166_cm7.h:717
@ kXBARA1_InputFlexpwm1Pwm1OutTrig0
Definition: MIMXRT1166_cm7.h:673
@ kXBARB2_InputRESERVED27
Definition: MIMXRT1166_cm7.h:768
@ kXBARB3_InputQtimer4Timer3
Definition: MIMXRT1166_cm7.h:864
@ kXBARB3_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1166_cm7.h:879
@ kXBARB2_InputQtimer2Timer3
Definition: MIMXRT1166_cm7.h:758
@ kXBARB2_InputRESERVED75
Definition: MIMXRT1166_cm7.h:816
@ kXBARA1_InputRESERVED96
Definition: MIMXRT1166_cm7.h:693
@ kXBARA1_InputRESERVED72
Definition: MIMXRT1166_cm7.h:669
@ kXBARB2_InputRESERVED29
Definition: MIMXRT1166_cm7.h:770
@ kXBARB3_InputQtimer4Timer1
Definition: MIMXRT1166_cm7.h:862
@ kXBARB3_InputQtimer1Timer2
Definition: MIMXRT1166_cm7.h:851
@ kXBARA1_InputRESERVED111
Definition: MIMXRT1166_cm7.h:708
@ kXBARA1_InputFlexpwm3Pwm3OutTrig01
Definition: MIMXRT1166_cm7.h:686
@ kXBARA1_InputFlexpwm1Pwm0OutTrig0
Definition: MIMXRT1166_cm7.h:671
@ kXBARB3_InputAdcEtc1Coco1
Definition: MIMXRT1166_cm7.h:904
@ kXBARA1_InputDmaDone2
Definition: MIMXRT1166_cm7.h:711
@ kXBARA1_InputAoi2Out2
Definition: MIMXRT1166_cm7.h:731
@ kXBARA1_InputQtimer3Timer2
Definition: MIMXRT1166_cm7.h:657
@ kXBARB3_InputQtimer2Timer0
Definition: MIMXRT1166_cm7.h:853
@ kXBARA1_InputIomuxXbarInout09
Definition: MIMXRT1166_cm7.h:606
@ kXBARA1_InputIomuxXbarInout15
Definition: MIMXRT1166_cm7.h:612
@ kXBARA1_InputQtimer3Timer1
Definition: MIMXRT1166_cm7.h:656
@ kXBARB3_InputQtimer1Timer0
Definition: MIMXRT1166_cm7.h:849
@ kXBARA1_InputIomuxXbarInout23
Definition: MIMXRT1166_cm7.h:620
@ kXBARA1_InputRESERVED2
Definition: MIMXRT1166_cm7.h:599
@ kXBARB3_InputDmaLpsrDone5
Definition: MIMXRT1166_cm7.h:934
@ kXBARA1_InputQtimer1Timer0
Definition: MIMXRT1166_cm7.h:647
@ kXBARA1_InputQtimer2Timer2
Definition: MIMXRT1166_cm7.h:653
@ kXBARA1_InputFlexpwm2Pwm0OutTrig01
Definition: MIMXRT1166_cm7.h:679
@ kXBARA1_InputQtimer3Timer0
Definition: MIMXRT1166_cm7.h:655
@ kXBARA1_InputRESERVED100
Definition: MIMXRT1166_cm7.h:697
@ kXBARA1_InputIomuxXbarInout25
Definition: MIMXRT1166_cm7.h:622
@ kXBARB2_InputDmaDone1
Definition: MIMXRT1166_cm7.h:824
@ kXBARB2_InputQtimer4Timer0
Definition: MIMXRT1166_cm7.h:763
@ kXBARA1_InputDmaDone1
Definition: MIMXRT1166_cm7.h:710
@ kXBARB3_InputDmaDone5
Definition: MIMXRT1166_cm7.h:926
@ kXBARB3_InputAcmp3Out
Definition: MIMXRT1166_cm7.h:843
@ kXBARA1_OutputFlexpwm1ExtForce
Definition: MIMXRT1166_cm7.h:1003
@ kXBARA1_OutputFlexpwm34Pwm1Exta
Definition: MIMXRT1166_cm7.h:1017
@ kXBARA1_OutputRESERVED48
Definition: MIMXRT1166_cm7.h:989
@ kXBARB3_OutputAoi2In15
Definition: MIMXRT1166_cm7.h:1147
@ kXBARA1_OutputRESERVED131
Definition: MIMXRT1166_cm7.h:1072
@ kXBARA1_OutputIomuxXbarInout20
Definition: MIMXRT1166_cm7.h:961
@ kXBARA1_OutputFlexpwm4Pwm1ExtSync
Definition: MIMXRT1166_cm7.h:1029
@ kXBARA1_OutputRESERVED103
Definition: MIMXRT1166_cm7.h:1044
@ kXBARA1_OutputFlexpwm3Fault1
Definition: MIMXRT1166_cm7.h:1026
@ kXBARA1_OutputAdcEtc0Coco2
Definition: MIMXRT1166_cm7.h:1098
@ kXBARA1_OutputQtimer1Timer0
Definition: MIMXRT1166_cm7.h:1079
@ kXBARA1_OutputQtimer1Timer3
Definition: MIMXRT1166_cm7.h:1082
@ kXBARA1_OutputIomuxXbarInout13
Definition: MIMXRT1166_cm7.h:954
@ kXBARA1_OutputFlexio2TrigIn0
Definition: MIMXRT1166_cm7.h:1114
@ kXBARA1_OutputAdcEtc1Coco1
Definition: MIMXRT1166_cm7.h:1101
@ kXBARB3_OutputAoi2In08
Definition: MIMXRT1166_cm7.h:1140
@ kXBARA1_OutputIomuxXbarInout35
Definition: MIMXRT1166_cm7.h:976
@ kXBARA1_OutputIomuxXbarInout27
Definition: MIMXRT1166_cm7.h:968
@ kXBARA1_OutputIomuxXbarInout31
Definition: MIMXRT1166_cm7.h:972
@ kXBARA1_OutputAdcEtc0Coco1
Definition: MIMXRT1166_cm7.h:1097
@ kXBARA1_OutputFlexpwm1234Fault3
Definition: MIMXRT1166_cm7.h:1002
@ kXBARA1_OutputFlexpwm2ExtForce
Definition: MIMXRT1166_cm7.h:1015
@ kXBARA1_OutputIomuxXbarInout04
Definition: MIMXRT1166_cm7.h:945
@ kXBARA1_OutputQtimer1Timer1
Definition: MIMXRT1166_cm7.h:1080
@ kXBARB3_OutputAoi2In10
Definition: MIMXRT1166_cm7.h:1142
@ kXBARA1_OutputIomuxXbarInout16
Definition: MIMXRT1166_cm7.h:957
@ kXBARA1_OutputDec4Trigger
Definition: MIMXRT1166_cm7.h:1068
@ kXBARA1_OutputRESERVED166
Definition: MIMXRT1166_cm7.h:1107
@ kXBARB2_OutputAoi1In09
Definition: MIMXRT1166_cm7.h:1125
@ kXBARA1_OutputDmaChMuxReq84
Definition: MIMXRT1166_cm7.h:944
@ kXBARA1_OutputAcmp1Sample
Definition: MIMXRT1166_cm7.h:982
@ kXBARA1_OutputQtimer2Timer1
Definition: MIMXRT1166_cm7.h:1084
@ kXBARA1_OutputDmaChMuxReq83
Definition: MIMXRT1166_cm7.h:943
@ kXBARA1_OutputDec1Phaseb
Definition: MIMXRT1166_cm7.h:1050
@ kXBARA1_OutputIomuxXbarInout30
Definition: MIMXRT1166_cm7.h:971
@ kXBARB3_OutputAoi2In01
Definition: MIMXRT1166_cm7.h:1133
@ kXBARA1_OutputRESERVED135
Definition: MIMXRT1166_cm7.h:1076
@ kXBARA1_OutputFlexpwm4Fault1
Definition: MIMXRT1166_cm7.h:1033
@ kXBARA1_OutputIomuxXbarInout15
Definition: MIMXRT1166_cm7.h:956
@ kXBARB3_OutputAoi2In04
Definition: MIMXRT1166_cm7.h:1136
@ kXBARA1_OutputDec2Home
Definition: MIMXRT1166_cm7.h:1057
@ kXBARA1_OutputFlexpwm1ExtClk
Definition: MIMXRT1166_cm7.h:998
@ kXBARB3_OutputAoi2In00
Definition: MIMXRT1166_cm7.h:1132
@ kXBARA1_OutputDec2Index
Definition: MIMXRT1166_cm7.h:1056
@ kXBARB2_OutputAoi1In13
Definition: MIMXRT1166_cm7.h:1129
@ kXBARA1_OutputRESERVED130
Definition: MIMXRT1166_cm7.h:1071
@ kXBARA1_OutputRESERVED46
Definition: MIMXRT1166_cm7.h:987
@ kXBARA1_OutputIomuxXbarInout10
Definition: MIMXRT1166_cm7.h:951
@ kXBARA1_OutputFlexpwm3Pwm2ExtSync
Definition: MIMXRT1166_cm7.h:1023
@ kXBARB3_OutputAoi2In09
Definition: MIMXRT1166_cm7.h:1141
@ kXBARA1_OutputRESERVED104
Definition: MIMXRT1166_cm7.h:1045
@ kXBARA1_OutputIomuxXbarInout17
Definition: MIMXRT1166_cm7.h:958
@ kXBARA1_OutputIomuxXbarInout19
Definition: MIMXRT1166_cm7.h:960
@ kXBARA1_OutputFlexpwm2Pwm2ExtSync
Definition: MIMXRT1166_cm7.h:1010
@ kXBARA1_OutputRESERVED45
Definition: MIMXRT1166_cm7.h:986
@ kXBARA1_OutputFlexpwm3Fault0
Definition: MIMXRT1166_cm7.h:1025
@ kXBARA1_OutputIomuxXbarInout38
Definition: MIMXRT1166_cm7.h:979
@ kXBARB3_OutputAoi2In11
Definition: MIMXRT1166_cm7.h:1143
@ kXBARA1_OutputIomuxXbarInout40
Definition: MIMXRT1166_cm7.h:981
@ kXBARA1_OutputIomuxXbarInout32
Definition: MIMXRT1166_cm7.h:973
@ kXBARB3_OutputAoi2In06
Definition: MIMXRT1166_cm7.h:1138
@ kXBARA1_OutputRESERVED134
Definition: MIMXRT1166_cm7.h:1075
@ kXBARB2_OutputAoi1In08
Definition: MIMXRT1166_cm7.h:1124
@ kXBARA1_OutputDec1Trigger
Definition: MIMXRT1166_cm7.h:1053
@ kXBARA1_OutputQtimer4Timer0
Definition: MIMXRT1166_cm7.h:1091
@ kXBARA1_OutputDmaChMuxReq82
Definition: MIMXRT1166_cm7.h:942
@ kXBARA1_OutputFlexpwm3Pwm3ExtSync
Definition: MIMXRT1166_cm7.h:1024
@ kXBARA1_OutputFlexpwm1Pwm1Exta
Definition: MIMXRT1166_cm7.h:991
@ kXBARA1_OutputIomuxXbarInout36
Definition: MIMXRT1166_cm7.h:977
@ kXBARB3_OutputAoi2In14
Definition: MIMXRT1166_cm7.h:1146
@ kXBARA1_OutputFlexio1TrigIn0
Definition: MIMXRT1166_cm7.h:1112
@ kXBARA1_OutputRESERVED164
Definition: MIMXRT1166_cm7.h:1105
@ kXBARB2_OutputAoi1In04
Definition: MIMXRT1166_cm7.h:1120
@ kXBARA1_OutputEwmEwmIn
Definition: MIMXRT1166_cm7.h:1095
@ kXBARA1_OutputFlexpwm1Pwm2Exta
Definition: MIMXRT1166_cm7.h:992
@ kXBARA1_OutputRESERVED128
Definition: MIMXRT1166_cm7.h:1069
@ kXBARA1_OutputQtimer3Timer3
Definition: MIMXRT1166_cm7.h:1090
@ kXBARB2_OutputAoi1In12
Definition: MIMXRT1166_cm7.h:1128
@ kXBARA1_OutputFlexpwm4Fault0
Definition: MIMXRT1166_cm7.h:1032
@ kXBARA1_OutputIomuxXbarInout08
Definition: MIMXRT1166_cm7.h:949
@ kXBARA1_OutputDec4Home
Definition: MIMXRT1166_cm7.h:1067
@ kXBARA1_OutputIomuxXbarInout06
Definition: MIMXRT1166_cm7.h:947
@ kXBARA1_OutputIomuxXbarInout23
Definition: MIMXRT1166_cm7.h:964
@ kXBARA1_OutputDmaChMuxReq81
Definition: MIMXRT1166_cm7.h:941
@ kXBARA1_OutputFlexpwm1Pwm2ExtSync
Definition: MIMXRT1166_cm7.h:996
@ kXBARA1_OutputFlexpwm1Fault0
Definition: MIMXRT1166_cm7.h:999
@ kXBARA1_OutputIomuxXbarInout05
Definition: MIMXRT1166_cm7.h:946
@ kXBARB2_OutputAoi1In07
Definition: MIMXRT1166_cm7.h:1123
@ kXBARA1_OutputIomuxXbarInout28
Definition: MIMXRT1166_cm7.h:969
@ kXBARB3_OutputAoi2In03
Definition: MIMXRT1166_cm7.h:1135
@ kXBARA1_OutputIomuxXbarInout25
Definition: MIMXRT1166_cm7.h:966
@ kXBARA1_OutputDec1Index
Definition: MIMXRT1166_cm7.h:1051
@ kXBARA1_OutputIomuxXbarInout07
Definition: MIMXRT1166_cm7.h:948
@ kXBARA1_OutputRESERVED105
Definition: MIMXRT1166_cm7.h:1046
@ kXBARA1_OutputFlexpwm34Pwm3Exta
Definition: MIMXRT1166_cm7.h:1019
@ kXBARA1_OutputAdcEtc1Coco2
Definition: MIMXRT1166_cm7.h:1102
@ kXBARA1_OutputRESERVED101
Definition: MIMXRT1166_cm7.h:1042
@ kXBARA1_OutputDec2Phaseb
Definition: MIMXRT1166_cm7.h:1055
@ kXBARB2_OutputAoi1In00
Definition: MIMXRT1166_cm7.h:1116
@ kXBARA1_OutputIomuxXbarInout26
Definition: MIMXRT1166_cm7.h:967
@ kXBARA1_OutputQtimer3Timer1
Definition: MIMXRT1166_cm7.h:1088
@ kXBARA1_OutputFlexpwm3Pwm0ExtSync
Definition: MIMXRT1166_cm7.h:1021
@ kXBARA1_OutputAcmp2Sample
Definition: MIMXRT1166_cm7.h:983
@ kXBARA1_OutputIomuxXbarInout12
Definition: MIMXRT1166_cm7.h:953
@ kXBARB3_OutputAoi2In12
Definition: MIMXRT1166_cm7.h:1144
@ kXBARA1_OutputFlexpwm2Pwm3Exta
Definition: MIMXRT1166_cm7.h:1007
@ kXBARA1_OutputDec1Phasea
Definition: MIMXRT1166_cm7.h:1049
@ kXBARA1_OutputFlexpwm2Pwm2Exta
Definition: MIMXRT1166_cm7.h:1006
@ kXBARA1_OutputQtimer1Timer2
Definition: MIMXRT1166_cm7.h:1081
@ kXBARA1_OutputFlexpwm34ExtClk
Definition: MIMXRT1166_cm7.h:1020
@ kXBARB2_OutputAoi1In15
Definition: MIMXRT1166_cm7.h:1131
@ kXBARA1_OutputAdcEtc1Coco0
Definition: MIMXRT1166_cm7.h:1100
@ kXBARA1_OutputQtimer2Timer0
Definition: MIMXRT1166_cm7.h:1083
@ kXBARA1_OutputIomuxXbarInout33
Definition: MIMXRT1166_cm7.h:974
@ kXBARA1_OutputDec4Phasea
Definition: MIMXRT1166_cm7.h:1064
@ kXBARA1_OutputFlexpwm2Fault1
Definition: MIMXRT1166_cm7.h:1014
@ kXBARA1_OutputDec3Phaseb
Definition: MIMXRT1166_cm7.h:1060
@ kXBARA1_OutputFlexpwm2Fault0
Definition: MIMXRT1166_cm7.h:1013
@ kXBARA1_OutputRESERVED163
Definition: MIMXRT1166_cm7.h:1104
@ kXBARA1_OutputAdcEtc0Coco3
Definition: MIMXRT1166_cm7.h:1099
@ kXBARA1_OutputFlexpwm1Pwm0ExtSync
Definition: MIMXRT1166_cm7.h:994
@ kXBARB2_OutputAoi1In14
Definition: MIMXRT1166_cm7.h:1130
@ kXBARA1_OutputFlexpwm2Pwm0ExtSync
Definition: MIMXRT1166_cm7.h:1008
@ kXBARA1_OutputFlexpwm3ExtForce
Definition: MIMXRT1166_cm7.h:1027
@ kXBARA1_OutputFlexpwm1Fault1
Definition: MIMXRT1166_cm7.h:1000
@ kXBARB3_OutputAoi2In13
Definition: MIMXRT1166_cm7.h:1145
@ kXBARA1_OutputRESERVED94
Definition: MIMXRT1166_cm7.h:1035
@ kXBARA1_OutputQtimer2Timer3
Definition: MIMXRT1166_cm7.h:1086
@ kXBARB2_OutputAoi1In10
Definition: MIMXRT1166_cm7.h:1126
@ kXBARA1_OutputFlexpwm2ExtClk
Definition: MIMXRT1166_cm7.h:1012
@ kXBARA1_OutputAdcEtc0Coco0
Definition: MIMXRT1166_cm7.h:1096
@ kXBARA1_OutputFlexpwm1234Fault2
Definition: MIMXRT1166_cm7.h:1001
@ kXBARA1_OutputDec2Trigger
Definition: MIMXRT1166_cm7.h:1058
@ kXBARA1_OutputRESERVED106
Definition: MIMXRT1166_cm7.h:1047
@ kXBARA1_OutputIomuxXbarInout22
Definition: MIMXRT1166_cm7.h:963
@ kXBARA1_OutputCan1
Definition: MIMXRT1166_cm7.h:1073
@ kXBARA1_OutputIomuxXbarInout14
Definition: MIMXRT1166_cm7.h:955
@ kXBARA1_OutputRESERVED47
Definition: MIMXRT1166_cm7.h:988
@ kXBARA1_OutputQtimer4Timer3
Definition: MIMXRT1166_cm7.h:1094
@ kXBARA1_OutputFlexpwm2Pwm1ExtSync
Definition: MIMXRT1166_cm7.h:1009
@ kXBARA1_OutputRESERVED107
Definition: MIMXRT1166_cm7.h:1048
@ kXBARA1_OutputFlexpwm2Pwm0Exta
Definition: MIMXRT1166_cm7.h:1004
@ kXBARA1_OutputRESERVED168
Definition: MIMXRT1166_cm7.h:1109
@ kXBARA1_OutputRESERVED95
Definition: MIMXRT1166_cm7.h:1036
@ kXBARA1_OutputIomuxXbarInout09
Definition: MIMXRT1166_cm7.h:950
@ kXBARA1_OutputFlexpwm4Pwm3ExtSync
Definition: MIMXRT1166_cm7.h:1031
@ kXBARA1_OutputIomuxXbarInout21
Definition: MIMXRT1166_cm7.h:962
@ kXBARA1_OutputQtimer4Timer1
Definition: MIMXRT1166_cm7.h:1092
@ kXBARB2_OutputAoi1In06
Definition: MIMXRT1166_cm7.h:1122
@ kXBARB2_OutputAoi1In03
Definition: MIMXRT1166_cm7.h:1119
@ kXBARB3_OutputAoi2In07
Definition: MIMXRT1166_cm7.h:1139
@ kXBARA1_OutputFlexpwm4Pwm2ExtSync
Definition: MIMXRT1166_cm7.h:1030
@ kXBARB3_OutputAoi2In05
Definition: MIMXRT1166_cm7.h:1137
@ kXBARB3_OutputAoi2In02
Definition: MIMXRT1166_cm7.h:1134
@ kXBARA1_OutputQtimer3Timer2
Definition: MIMXRT1166_cm7.h:1089
@ kXBARA1_OutputRESERVED165
Definition: MIMXRT1166_cm7.h:1106
@ kXBARA1_OutputIomuxXbarInout24
Definition: MIMXRT1166_cm7.h:965
@ kXBARA1_OutputFlexpwm2Pwm1Exta
Definition: MIMXRT1166_cm7.h:1005
@ kXBARA1_OutputIomuxXbarInout18
Definition: MIMXRT1166_cm7.h:959
@ kXBARA1_OutputFlexpwm1Pwm1ExtSync
Definition: MIMXRT1166_cm7.h:995
@ kXBARA1_OutputFlexpwm34Pwm0Exta
Definition: MIMXRT1166_cm7.h:1016
@ kXBARA1_OutputDec3Trigger
Definition: MIMXRT1166_cm7.h:1063
@ kXBARA1_OutputFlexpwm1Pwm0Exta
Definition: MIMXRT1166_cm7.h:990
@ kXBARA1_OutputDec4Phaseb
Definition: MIMXRT1166_cm7.h:1065
@ kXBARA1_OutputQtimer2Timer2
Definition: MIMXRT1166_cm7.h:1085
@ kXBARA1_OutputFlexpwm1Pwm3ExtSync
Definition: MIMXRT1166_cm7.h:997
@ kXBARA1_OutputDec2Phasea
Definition: MIMXRT1166_cm7.h:1054
@ kXBARA1_OutputRESERVED102
Definition: MIMXRT1166_cm7.h:1043
@ kXBARB2_OutputAoi1In05
Definition: MIMXRT1166_cm7.h:1121
@ kXBARA1_OutputIomuxXbarInout34
Definition: MIMXRT1166_cm7.h:975
@ kXBARA1_OutputDec4Index
Definition: MIMXRT1166_cm7.h:1066
@ kXBARA1_OutputRESERVED169
Definition: MIMXRT1166_cm7.h:1110
@ kXBARA1_OutputFlexpwm34Pwm2Exta
Definition: MIMXRT1166_cm7.h:1018
@ kXBARA1_OutputRESERVED170
Definition: MIMXRT1166_cm7.h:1111
@ kXBARA1_OutputDec1Home
Definition: MIMXRT1166_cm7.h:1052
@ kXBARA1_OutputDec3Home
Definition: MIMXRT1166_cm7.h:1062
@ kXBARA1_OutputFlexio1TrigIn1
Definition: MIMXRT1166_cm7.h:1113
@ kXBARA1_OutputRESERVED97
Definition: MIMXRT1166_cm7.h:1038
@ kXBARA1_OutputAcmp3Sample
Definition: MIMXRT1166_cm7.h:984
@ kXBARA1_OutputFlexpwm4Pwm0ExtSync
Definition: MIMXRT1166_cm7.h:1028
@ kXBARA1_OutputFlexpwm4ExtForce
Definition: MIMXRT1166_cm7.h:1034
@ kXBARA1_OutputIomuxXbarInout39
Definition: MIMXRT1166_cm7.h:980
@ kXBARA1_OutputRESERVED137
Definition: MIMXRT1166_cm7.h:1078
@ kXBARA1_OutputRESERVED99
Definition: MIMXRT1166_cm7.h:1040
@ kXBARA1_OutputIomuxXbarInout11
Definition: MIMXRT1166_cm7.h:952
@ kXBARA1_OutputAdcEtc1Coco3
Definition: MIMXRT1166_cm7.h:1103
@ kXBARA1_OutputRESERVED136
Definition: MIMXRT1166_cm7.h:1077
@ kXBARA1_OutputDec3Index
Definition: MIMXRT1166_cm7.h:1061
@ kXBARA1_OutputFlexio2TrigIn1
Definition: MIMXRT1166_cm7.h:1115
@ kXBARA1_OutputIomuxXbarInout29
Definition: MIMXRT1166_cm7.h:970
@ kXBARB2_OutputAoi1In02
Definition: MIMXRT1166_cm7.h:1118
@ kXBARA1_OutputFlexpwm3Pwm1ExtSync
Definition: MIMXRT1166_cm7.h:1022
@ kXBARA1_OutputRESERVED129
Definition: MIMXRT1166_cm7.h:1070
@ kXBARB2_OutputAoi1In01
Definition: MIMXRT1166_cm7.h:1117
@ kXBARA1_OutputDec3Phasea
Definition: MIMXRT1166_cm7.h:1059
@ kXBARA1_OutputRESERVED167
Definition: MIMXRT1166_cm7.h:1108
@ kXBARA1_OutputFlexpwm1Pwm3Exta
Definition: MIMXRT1166_cm7.h:993
@ kXBARA1_OutputQtimer3Timer0
Definition: MIMXRT1166_cm7.h:1087
@ kXBARA1_OutputRESERVED100
Definition: MIMXRT1166_cm7.h:1041
@ kXBARA1_OutputFlexpwm2Pwm3ExtSync
Definition: MIMXRT1166_cm7.h:1011
@ kXBARA1_OutputQtimer4Timer2
Definition: MIMXRT1166_cm7.h:1093
@ kXBARA1_OutputIomuxXbarInout37
Definition: MIMXRT1166_cm7.h:978
@ kXBARA1_OutputRESERVED96
Definition: MIMXRT1166_cm7.h:1037
@ kXBARA1_OutputAcmp4Sample
Definition: MIMXRT1166_cm7.h:985
@ kXBARA1_OutputRESERVED98
Definition: MIMXRT1166_cm7.h:1039
@ kXBARA1_OutputCan2
Definition: MIMXRT1166_cm7.h:1074
@ kXBARB2_OutputAoi1In11
Definition: MIMXRT1166_cm7.h:1127
@ kRDC_Master_ENET_1G_RX
Definition: MIMXRT1166_cm7.h:382
@ kRDC_Master_LCDIF
Definition: MIMXRT1166_cm7.h:390
@ kRDC_Master_GPU
Definition: MIMXRT1166_cm7.h:388
@ kRDC_Master_USDHC2
Definition: MIMXRT1166_cm7.h:386
@ kRDC_Master_PXP
Definition: MIMXRT1166_cm7.h:389
@ kRDC_Master_ENET
Definition: MIMXRT1166_cm7.h:383
@ kRDC_Master_USB
Definition: MIMXRT1166_cm7.h:387
@ kRDC_Master_CSI
Definition: MIMXRT1166_cm7.h:391
@ kRDC_Master_ENET_1G_TX
Definition: MIMXRT1166_cm7.h:381
@ kRDC_Master_ENET_QOS
Definition: MIMXRT1166_cm7.h:384
@ kRDC_Master_USDHC1
Definition: MIMXRT1166_cm7.h:385
_ssarc_power_domain_name
Structure for the SSARC mapping.
Definition: MIMXRT1166_cm4.h:1450
_ssarc_cpu_domain_name
Definition: MIMXRT1166_cm4.h:1465
enum _ssarc_power_domain_name ssarc_power_domain_name_t
Structure for the SSARC mapping.
@ kSSARC_PowerDomain7
Definition: MIMXRT1166_cm7.h:1277
@ kSSARC_PowerDomain5
Definition: MIMXRT1166_cm7.h:1275
@ kSSARC_DISPLAYMIXPowerDomain
Definition: MIMXRT1166_cm7.h:1271
@ kSSARC_PowerDomain4
Definition: MIMXRT1166_cm7.h:1274
@ kSSARC_MEGAMIXPowerDomain
Definition: MIMXRT1166_cm7.h:1270
@ kSSARC_WAKEUPMIXPowerDomain
Definition: MIMXRT1166_cm7.h:1272
@ kSSARC_PowerDomain6
Definition: MIMXRT1166_cm7.h:1276
@ kSSARC_LPSRMIXPowerDomain
Definition: MIMXRT1166_cm7.h:1273
@ kSSARC_CM4Core
Definition: MIMXRT1166_cm7.h:1286
@ kSSARC_CM7Core
Definition: MIMXRT1166_cm7.h:1285
enum _xrdc2_master xrdc2_master_t
Structure for the XRDC2 mapping.
_xrdc2_mem_slot
Definition: MIMXRT1166_cm4.h:1644
_xrdc2_master
Structure for the XRDC2 mapping.
Definition: MIMXRT1166_cm4.h:1488
_xrdc2_periph
Definition: MIMXRT1166_cm4.h:1652
_xrdc2_mem
Definition: MIMXRT1166_cm4.h:1512
@ kXRDC2_MemSlot_ROMCP
Definition: MIMXRT1166_cm7.h:1467
@ kXRDC2_MemSlot_GPV2
Definition: MIMXRT1166_cm7.h:1466
@ kXRDC2_MemSlot_GPV0
Definition: MIMXRT1166_cm7.h:1464
@ kXRDC2_MemSlot_GPV1
Definition: MIMXRT1166_cm7.h:1465
@ kXRDC2_Master_M7_AXI
Definition: MIMXRT1166_cm7.h:1310
@ kXRDC2_Master_USDHC1
Definition: MIMXRT1166_cm7.h:1326
@ kXRDC2_Master_PXP
Definition: MIMXRT1166_cm7.h:1323
@ kXRDC2_Master_M4_EDMA
Definition: MIMXRT1166_cm7.h:1315
@ kXRDC2_Master_LCDIFV2
Definition: MIMXRT1166_cm7.h:1322
@ kXRDC2_Master_ENET_QOS
Definition: MIMXRT1166_cm7.h:1319
@ kXRDC2_Master_M7_EDMA
Definition: MIMXRT1166_cm7.h:1314
@ kXRDC2_Master_USDHC2
Definition: MIMXRT1166_cm7.h:1327
@ kXRDC2_Master_ENET_1G_RX
Definition: MIMXRT1166_cm7.h:1317
@ kXRDC2_Master_CAAM
Definition: MIMXRT1166_cm7.h:1312
@ kXRDC2_Master_LCDIF
Definition: MIMXRT1166_cm7.h:1321
@ kXRDC2_Master_CSI
Definition: MIMXRT1166_cm7.h:1313
@ kXRDC2_Master_GPU
Definition: MIMXRT1166_cm7.h:1320
@ kXRDC2_Master_SSARC
Definition: MIMXRT1166_cm7.h:1324
@ kXRDC2_Master_ENET
Definition: MIMXRT1166_cm7.h:1316
@ kXRDC2_Master_USB
Definition: MIMXRT1166_cm7.h:1325
@ kXRDC2_Master_ENET_1G_TX
Definition: MIMXRT1166_cm7.h:1318
@ kXRDC2_Master_M7_AHB
Definition: MIMXRT1166_cm7.h:1308
@ kXRDC2_Master_M4_AHBS
Definition: MIMXRT1166_cm7.h:1311
@ kXRDC2_Master_M4_AHBC
Definition: MIMXRT1166_cm7.h:1309
@ kXRDC2_Periph_USBPHY2
Definition: MIMXRT1166_cm7.h:1586
@ kXRDC2_Periph_SAI4
Definition: MIMXRT1166_cm7.h:1643
@ kXRDC2_Periph_USB_OTG2
Definition: MIMXRT1166_cm7.h:1589
@ kXRDC2_Periph_GPIO2
Definition: MIMXRT1166_cm7.h:1495
@ kXRDC2_Periph_IOMUXC_GPR
Definition: MIMXRT1166_cm7.h:1512
@ kXRDC2_Periph_LPSPI1
Definition: MIMXRT1166_cm7.h:1500
@ kXRDC2_Periph_GPIO13
Definition: MIMXRT1166_cm7.h:1625
@ kXRDC2_Periph_SAI1
Definition: MIMXRT1166_cm7.h:1598
@ kXRDC2_Periph_CAAM_JR2_3
Definition: MIMXRT1166_cm7.h:1569
@ kXRDC2_Periph_XRDC2_MGR_M4_2
Definition: MIMXRT1166_cm7.h:1612
@ kXRDC2_Periph_CAAM_GENERAL_2
Definition: MIMXRT1166_cm7.h:1582
@ kXRDC2_Periph_LCDIF
Definition: MIMXRT1166_cm7.h:1605
@ kXRDC2_Periph_LPSPI3
Definition: MIMXRT1166_cm7.h:1498
@ kXRDC2_Periph_FLEXRAM
Definition: MIMXRT1166_cm7.h:1549
@ kXRDC2_Periph_SNVS_HP_WRAPPER
Definition: MIMXRT1166_cm7.h:1629
@ kXRDC2_Periph_ACMP1
Definition: MIMXRT1166_cm7.h:1475
@ kXRDC2_Periph_SEMA_HS
Definition: MIMXRT1166_cm7.h:1616
@ kXRDC2_Periph_IOMUXC_SNVS_GPR
Definition: MIMXRT1166_cm7.h:1627
@ kXRDC2_Periph_MIPI_DSI
Definition: MIMXRT1166_cm7.h:1603
@ kXRDC2_Periph_GPIO4
Definition: MIMXRT1166_cm7.h:1493
@ kXRDC2_Periph_LPSPI2
Definition: MIMXRT1166_cm7.h:1499
@ kXRDC2_Periph_SAI2
Definition: MIMXRT1166_cm7.h:1597
@ kXRDC2_Periph_AOI1
Definition: MIMXRT1166_cm7.h:1521
@ kXRDC2_Periph_MIC
Definition: MIMXRT1166_cm7.h:1651
@ kXRDC2_Periph_CAAM_JR2_0
Definition: MIMXRT1166_cm7.h:1572
@ kXRDC2_Periph_SIM2
Definition: MIMXRT1166_cm7.h:1488
@ kXRDC2_Periph_XRDC2_MGR_M7_0
Definition: MIMXRT1166_cm7.h:1610
@ kXRDC2_Periph_SEMA1
Definition: MIMXRT1166_cm7.h:1642
@ kXRDC2_Periph_GPIO7
Definition: MIMXRT1166_cm7.h:1639
@ kXRDC2_Periph_GPIO11
Definition: MIMXRT1166_cm7.h:1635
@ kXRDC2_Periph_CAAM_JR0_3
Definition: MIMXRT1166_cm7.h:1577
@ kXRDC2_Periph_CAAM_JR0_0
Definition: MIMXRT1166_cm7.h:1580
@ kXRDC2_Periph_GPIO8
Definition: MIMXRT1166_cm7.h:1638
@ kXRDC2_Periph_SRC
Definition: MIMXRT1166_cm7.h:1657
@ kXRDC2_Periph_WDOG2
Definition: MIMXRT1166_cm7.h:1546
@ kXRDC2_Periph_ENET_1G
Definition: MIMXRT1166_cm7.h:1592
@ kXRDC2_Periph_GPT1
Definition: MIMXRT1166_cm7.h:1510
@ kXRDC2_Periph_CAAM_GENERAL_0
Definition: MIMXRT1166_cm7.h:1584
@ kXRDC2_Periph_WDOG1
Definition: MIMXRT1166_cm7.h:1547
@ kXRDC2_Periph_GPIO10
Definition: MIMXRT1166_cm7.h:1636
@ kXRDC2_Periph_XRDC2_MGR_M4_0
Definition: MIMXRT1166_cm7.h:1614
@ kXRDC2_Periph_SEMC
Definition: MIMXRT1166_cm7.h:1515
@ kXRDC2_Periph_USDHC1
Definition: MIMXRT1166_cm7.h:1594
@ kXRDC2_Periph_CAAM_JR3_2
Definition: MIMXRT1166_cm7.h:1566
@ kXRDC2_Periph_CAAM_JR0_1
Definition: MIMXRT1166_cm7.h:1579
@ kXRDC2_Periph_ACMP2
Definition: MIMXRT1166_cm7.h:1474
@ kXRDC2_Periph_DAC
Definition: MIMXRT1166_cm7.h:1537
@ kXRDC2_Periph_KPP
Definition: MIMXRT1166_cm7.h:1513
@ kXRDC2_Periph_FLEXIO2
Definition: MIMXRT1166_cm7.h:1522
@ kXRDC2_Periph_GPC
Definition: MIMXRT1166_cm7.h:1658
@ kXRDC2_Periph_TSC_DIG
Definition: MIMXRT1166_cm7.h:1538
@ kXRDC2_Periph_IOMUXC_SNVS
Definition: MIMXRT1166_cm7.h:1628
@ kXRDC2_Periph_FLEXIO1
Definition: MIMXRT1166_cm7.h:1523
@ kXRDC2_Periph_GPT4
Definition: MIMXRT1166_cm7.h:1507
@ kXRDC2_Periph_LPUART6
Definition: MIMXRT1166_cm7.h:1528
@ kXRDC2_Periph_XECC_SEMC
Definition: MIMXRT1166_cm7.h:1550
@ kXRDC2_Periph_ENC4
Definition: MIMXRT1166_cm7.h:1480
@ kXRDC2_Periph_GPIO6
Definition: MIMXRT1166_cm7.h:1491
@ kXRDC2_Periph_RDC
Definition: MIMXRT1166_cm7.h:1633
@ kXRDC2_Periph_ACMP4
Definition: MIMXRT1166_cm7.h:1472
@ kXRDC2_Periph_GPT5
Definition: MIMXRT1166_cm7.h:1506
@ kXRDC2_Periph_FLEXPWM4
Definition: MIMXRT1166_cm7.h:1476
@ kXRDC2_Periph_LPUART7
Definition: MIMXRT1166_cm7.h:1527
@ kXRDC2_Periph_CAAM_JR1_1
Definition: MIMXRT1166_cm7.h:1575
@ kXRDC2_Periph_CAAM_DEBUG_1
Definition: MIMXRT1166_cm7.h:1559
@ kXRDC2_Periph_SPDIF
Definition: MIMXRT1166_cm7.h:1599
@ kXRDC2_Periph_MIPI_CSI
Definition: MIMXRT1166_cm7.h:1602
@ kXRDC2_Periph_LPI2C6
Definition: MIMXRT1166_cm7.h:1645
@ kXRDC2_Periph_XRDC2_MGR_M7_2
Definition: MIMXRT1166_cm7.h:1608
@ kXRDC2_Periph_XBAR3
Definition: MIMXRT1166_cm7.h:1542
@ kXRDC2_Periph_XBAR1
Definition: MIMXRT1166_cm7.h:1544
@ kXRDC2_Periph_LPUART4
Definition: MIMXRT1166_cm7.h:1530
@ kXRDC2_Periph_LPI2C4
Definition: MIMXRT1166_cm7.h:1501
@ kXRDC2_Periph_CAAM_DEBUG_0
Definition: MIMXRT1166_cm7.h:1560
@ kXRDC2_Periph_CAAM_JR0_2
Definition: MIMXRT1166_cm7.h:1578
@ kXRDC2_Periph_CSI
Definition: MIMXRT1166_cm7.h:1606
@ kXRDC2_Periph_GPT2
Definition: MIMXRT1166_cm7.h:1509
@ kXRDC2_Periph_LPSPI5
Definition: MIMXRT1166_cm7.h:1648
@ kXRDC2_Periph_CAAM_JR3_1
Definition: MIMXRT1166_cm7.h:1567
@ kXRDC2_Periph_SSARC_LP
Definition: MIMXRT1166_cm7.h:1619
@ kXRDC2_Periph_LCDIFV2
Definition: MIMXRT1166_cm7.h:1604
@ kXRDC2_Periph_PXP
Definition: MIMXRT1166_cm7.h:1601
@ kXRDC2_Periph_EDMA
Definition: MIMXRT1166_cm7.h:1535
@ kXRDC2_Periph_ROMCP
Definition: MIMXRT1166_cm7.h:1624
@ kXRDC2_Periph_LPI2C2
Definition: MIMXRT1166_cm7.h:1503
@ kXRDC2_Periph_CAAM_RTIC_2
Definition: MIMXRT1166_cm7.h:1562
@ kXRDC2_Periph_LPI2C1
Definition: MIMXRT1166_cm7.h:1504
@ kXRDC2_Periph_LPUART10
Definition: MIMXRT1166_cm7.h:1524
@ kXRDC2_Periph_ENC2
Definition: MIMXRT1166_cm7.h:1482
@ kXRDC2_Periph_LPI2C3
Definition: MIMXRT1166_cm7.h:1502
@ kXRDC2_Periph_XBAR2
Definition: MIMXRT1166_cm7.h:1543
@ kXRDC2_Periph_XRDC2_MGR_M7_3
Definition: MIMXRT1166_cm7.h:1607
@ kXRDC2_Periph_GPT3
Definition: MIMXRT1166_cm7.h:1508
@ kXRDC2_Periph_LPUART9
Definition: MIMXRT1166_cm7.h:1525
@ kXRDC2_Periph_DCDC
Definition: MIMXRT1166_cm7.h:1623
@ kXRDC2_Periph_ADC2
Definition: MIMXRT1166_cm7.h:1539
@ kXRDC2_Periph_LPUART5
Definition: MIMXRT1166_cm7.h:1529
@ kXRDC2_Periph_ENET
Definition: MIMXRT1166_cm7.h:1591
@ kXRDC2_Periph_XRDC2_MGR_M4_1
Definition: MIMXRT1166_cm7.h:1613
@ kXRDC2_Periph_CAN1
Definition: MIMXRT1166_cm7.h:1519
@ kXRDC2_Periph_CCM_1
Definition: MIMXRT1166_cm7.h:1617
@ kXRDC2_Periph_XECC_FLEXSPI1
Definition: MIMXRT1166_cm7.h:1552
@ kXRDC2_Periph_GPIO3
Definition: MIMXRT1166_cm7.h:1494
@ kXRDC2_Periph_LPSPI4
Definition: MIMXRT1166_cm7.h:1497
@ kXRDC2_Periph_CAAM_GENERAL_1
Definition: MIMXRT1166_cm7.h:1583
@ kXRDC2_Periph_ANATOP
Definition: MIMXRT1166_cm7.h:1631
@ kXRDC2_Periph_SSARC_HP
Definition: MIMXRT1166_cm7.h:1620
@ kXRDC2_Periph_SFA
Definition: MIMXRT1166_cm7.h:1556
@ kXRDC2_Periph_ACMP3
Definition: MIMXRT1166_cm7.h:1473
@ kXRDC2_Periph_VIDEO_MUX
Definition: MIMXRT1166_cm7.h:1600
@ kXRDC2_Periph_MECC2
Definition: MIMXRT1166_cm7.h:1553
@ kXRDC2_Periph_DMA_CH_MUX
Definition: MIMXRT1166_cm7.h:1534
@ kXRDC2_Periph_USDHC2
Definition: MIMXRT1166_cm7.h:1593
@ kXRDC2_Periph_KEY_MANAGER
Definition: MIMXRT1166_cm7.h:1632
@ kXRDC2_Periph_FLEXSPI1
Definition: MIMXRT1166_cm7.h:1517
@ kXRDC2_Periph_MU_B
Definition: MIMXRT1166_cm7.h:1640
@ kXRDC2_Periph_CAAM_JR1_3
Definition: MIMXRT1166_cm7.h:1573
@ kXRDC2_Periph_LPSPI6
Definition: MIMXRT1166_cm7.h:1647
@ kXRDC2_Periph_ASRC
Definition: MIMXRT1166_cm7.h:1595
@ kXRDC2_Periph_PIT2
Definition: MIMXRT1166_cm7.h:1621
@ kXRDC2_Periph_AOI2
Definition: MIMXRT1166_cm7.h:1520
@ kXRDC2_Periph_ENET_QOS
Definition: MIMXRT1166_cm7.h:1585
@ kXRDC2_Periph_LPUART2
Definition: MIMXRT1166_cm7.h:1532
@ kXRDC2_Periph_USB_PL301
Definition: MIMXRT1166_cm7.h:1590
@ kXRDC2_Periph_IOMUXC
Definition: MIMXRT1166_cm7.h:1511
@ kXRDC2_Periph_CCM_OBS
Definition: MIMXRT1166_cm7.h:1490
@ kXRDC2_Periph_CAAM_JR1_0
Definition: MIMXRT1166_cm7.h:1576
@ kXRDC2_Periph_CAAM_RTIC_3
Definition: MIMXRT1166_cm7.h:1561
@ kXRDC2_Periph_LPUART11
Definition: MIMXRT1166_cm7.h:1650
@ kXRDC2_Periph_ADC_ETC
Definition: MIMXRT1166_cm7.h:1541
@ kXRDC2_Periph_ADC1
Definition: MIMXRT1166_cm7.h:1540
@ kXRDC2_Periph_CCM_0
Definition: MIMXRT1166_cm7.h:1618
@ kXRDC2_Periph_CAAM_RTIC_1
Definition: MIMXRT1166_cm7.h:1563
@ kXRDC2_Periph_CAAM_JR2_2
Definition: MIMXRT1166_cm7.h:1570
@ kXRDC2_Periph_LPI2C5
Definition: MIMXRT1166_cm7.h:1646
@ kXRDC2_Periph_USB_OTG
Definition: MIMXRT1166_cm7.h:1588
@ kXRDC2_Periph_XRDC2_MGR_M7_1
Definition: MIMXRT1166_cm7.h:1609
@ kXRDC2_Periph_ENC1
Definition: MIMXRT1166_cm7.h:1483
@ kXRDC2_Periph_GPIO1
Definition: MIMXRT1166_cm7.h:1496
@ kXRDC2_Periph_MU_A
Definition: MIMXRT1166_cm7.h:1641
@ kXRDC2_Periph_LPUART8
Definition: MIMXRT1166_cm7.h:1526
@ kXRDC2_Periph_LPUART3
Definition: MIMXRT1166_cm7.h:1531
@ kXRDC2_Periph_GPIO12
Definition: MIMXRT1166_cm7.h:1634
@ kXRDC2_Periph_FLEXPWM1
Definition: MIMXRT1166_cm7.h:1479
@ kXRDC2_Periph_GPIO5
Definition: MIMXRT1166_cm7.h:1492
@ kXRDC2_Periph_FLEXSPI2
Definition: MIMXRT1166_cm7.h:1516
@ kXRDC2_Periph_EDMA_LPSR
Definition: MIMXRT1166_cm7.h:1653
@ kXRDC2_Periph_FLEXPWM3
Definition: MIMXRT1166_cm7.h:1477
@ kXRDC2_Periph_USBPHY1
Definition: MIMXRT1166_cm7.h:1587
@ kXRDC2_Periph_CAN3
Definition: MIMXRT1166_cm7.h:1644
@ kXRDC2_Periph_CAAM_DEBUG_2
Definition: MIMXRT1166_cm7.h:1558
@ kXRDC2_Periph_CAAM_GENERAL_3
Definition: MIMXRT1166_cm7.h:1581
@ kXRDC2_Periph_QTIMER3
Definition: MIMXRT1166_cm7.h:1485
@ kXRDC2_Periph_MTR
Definition: MIMXRT1166_cm7.h:1555
@ kXRDC2_Periph_CAAM_JR3_0
Definition: MIMXRT1166_cm7.h:1568
@ kXRDC2_Periph_IOMUXC_LPSR_GPR
Definition: MIMXRT1166_cm7.h:1655
@ kXRDC2_Periph_IOMUXC_LPSR
Definition: MIMXRT1166_cm7.h:1656
@ kXRDC2_Periph_CAAM_DEBUG_3
Definition: MIMXRT1166_cm7.h:1557
@ kXRDC2_Periph_DMA_CH_MUX_LPSR
Definition: MIMXRT1166_cm7.h:1652
@ kXRDC2_Periph_SAI3
Definition: MIMXRT1166_cm7.h:1596
@ kXRDC2_Periph_CAAM_JR1_2
Definition: MIMXRT1166_cm7.h:1574
@ kXRDC2_Periph_EWM
Definition: MIMXRT1166_cm7.h:1548
@ kXRDC2_Periph_PGMC
Definition: MIMXRT1166_cm7.h:1630
@ kXRDC2_Periph_QTIMER1
Definition: MIMXRT1166_cm7.h:1487
@ kXRDC2_Periph_CAAM_RTIC_0
Definition: MIMXRT1166_cm7.h:1564
@ kXRDC2_Periph_CAAM_JR3_3
Definition: MIMXRT1166_cm7.h:1565
@ kXRDC2_Periph_ENC3
Definition: MIMXRT1166_cm7.h:1481
@ kXRDC2_Periph_GPIO9
Definition: MIMXRT1166_cm7.h:1637
@ kXRDC2_Periph_CAAM_JR2_1
Definition: MIMXRT1166_cm7.h:1571
@ kXRDC2_Periph_CAN2
Definition: MIMXRT1166_cm7.h:1518
@ kXRDC2_Periph_OCOTP_CTRL_WRAPPER
Definition: MIMXRT1166_cm7.h:1622
@ kXRDC2_Periph_WDOG4
Definition: MIMXRT1166_cm7.h:1654
@ kXRDC2_Periph_GPU
Definition: MIMXRT1166_cm7.h:1659
@ kXRDC2_Periph_XECC_FLEXSPI2
Definition: MIMXRT1166_cm7.h:1551
@ kXRDC2_Periph_XRDC2_MGR_M4_3
Definition: MIMXRT1166_cm7.h:1611
@ kXRDC2_Periph_WDOG3
Definition: MIMXRT1166_cm7.h:1545
@ kXRDC2_Periph_SEMA2
Definition: MIMXRT1166_cm7.h:1615
@ kXRDC2_Periph_LPUART1
Definition: MIMXRT1166_cm7.h:1533
@ kXRDC2_Periph_SIM1
Definition: MIMXRT1166_cm7.h:1489
@ kXRDC2_Periph_MECC1
Definition: MIMXRT1166_cm7.h:1554
@ kXRDC2_Periph_PIT1
Definition: MIMXRT1166_cm7.h:1514
@ kXRDC2_Periph_QTIMER2
Definition: MIMXRT1166_cm7.h:1486
@ kXRDC2_Periph_SNVS_SRAM
Definition: MIMXRT1166_cm7.h:1626
@ kXRDC2_Periph_IEE
Definition: MIMXRT1166_cm7.h:1536
@ kXRDC2_Periph_QTIMER4
Definition: MIMXRT1166_cm7.h:1484
@ kXRDC2_Periph_GPT6
Definition: MIMXRT1166_cm7.h:1505
@ kXRDC2_Periph_FLEXPWM2
Definition: MIMXRT1166_cm7.h:1478
@ kXRDC2_Periph_LPUART12
Definition: MIMXRT1166_cm7.h:1649
@ kXRDC2_Mem_M7OC_Region11
Definition: MIMXRT1166_cm7.h:1407
@ kXRDC2_Mem_MECC2_Region2
Definition: MIMXRT1166_cm7.h:1430
@ kXRDC2_Mem_CAAM_Region6
Definition: MIMXRT1166_cm7.h:1338
@ kXRDC2_Mem_FLEXSPI2_Region10
Definition: MIMXRT1166_cm7.h:1374
@ kXRDC2_Mem_CAAM_Region2
Definition: MIMXRT1166_cm7.h:1334
@ kXRDC2_Mem_FLEXSPI1_Region7
Definition: MIMXRT1166_cm7.h:1355
@ kXRDC2_Mem_MECC1_Region15
Definition: MIMXRT1166_cm7.h:1427
@ kXRDC2_Mem_CAAM_Region5
Definition: MIMXRT1166_cm7.h:1337
@ kXRDC2_Mem_FLEXSPI1_Region3
Definition: MIMXRT1166_cm7.h:1351
@ kXRDC2_Mem_MECC1_Region13
Definition: MIMXRT1166_cm7.h:1425
@ kXRDC2_Mem_FLEXSPI1_Region8
Definition: MIMXRT1166_cm7.h:1356
@ kXRDC2_Mem_FLEXSPI2_Region4
Definition: MIMXRT1166_cm7.h:1368
@ kXRDC2_Mem_M4LMEM_Region15
Definition: MIMXRT1166_cm7.h:1395
@ kXRDC2_Mem_SEMC_Region10
Definition: MIMXRT1166_cm7.h:1454
@ kXRDC2_Mem_MECC2_Region7
Definition: MIMXRT1166_cm7.h:1435
@ kXRDC2_Mem_MECC1_Region8
Definition: MIMXRT1166_cm7.h:1420
@ kXRDC2_Mem_FLEXSPI1_Region1
Definition: MIMXRT1166_cm7.h:1349
@ kXRDC2_Mem_MECC2_Region13
Definition: MIMXRT1166_cm7.h:1441
@ kXRDC2_Mem_MECC2_Region11
Definition: MIMXRT1166_cm7.h:1439
@ kXRDC2_Mem_M4LMEM_Region11
Definition: MIMXRT1166_cm7.h:1391
@ kXRDC2_Mem_MECC1_Region5
Definition: MIMXRT1166_cm7.h:1417
@ kXRDC2_Mem_M7OC_Region0
Definition: MIMXRT1166_cm7.h:1396
@ kXRDC2_Mem_MECC2_Region8
Definition: MIMXRT1166_cm7.h:1436
@ kXRDC2_Mem_FLEXSPI2_Region2
Definition: MIMXRT1166_cm7.h:1366
@ kXRDC2_Mem_CAAM_Region8
Definition: MIMXRT1166_cm7.h:1340
@ kXRDC2_Mem_FLEXSPI1_Region10
Definition: MIMXRT1166_cm7.h:1358
@ kXRDC2_Mem_CAAM_Region12
Definition: MIMXRT1166_cm7.h:1344
@ kXRDC2_Mem_MECC2_Region12
Definition: MIMXRT1166_cm7.h:1440
@ kXRDC2_Mem_FLEXSPI2_Region1
Definition: MIMXRT1166_cm7.h:1365
@ kXRDC2_Mem_M7OC_Region3
Definition: MIMXRT1166_cm7.h:1399
@ kXRDC2_Mem_CAAM_Region3
Definition: MIMXRT1166_cm7.h:1335
@ kXRDC2_Mem_FLEXSPI1_Region4
Definition: MIMXRT1166_cm7.h:1352
@ kXRDC2_Mem_MECC2_Region3
Definition: MIMXRT1166_cm7.h:1431
@ kXRDC2_Mem_SEMC_Region1
Definition: MIMXRT1166_cm7.h:1445
@ kXRDC2_Mem_M4LMEM_Region14
Definition: MIMXRT1166_cm7.h:1394
@ kXRDC2_Mem_M4LMEM_Region1
Definition: MIMXRT1166_cm7.h:1381
@ kXRDC2_Mem_M4LMEM_Region6
Definition: MIMXRT1166_cm7.h:1386
@ kXRDC2_Mem_MECC2_Region14
Definition: MIMXRT1166_cm7.h:1442
@ kXRDC2_Mem_M7OC_Region12
Definition: MIMXRT1166_cm7.h:1408
@ kXRDC2_Mem_MECC1_Region2
Definition: MIMXRT1166_cm7.h:1414
@ kXRDC2_Mem_CAAM_Region7
Definition: MIMXRT1166_cm7.h:1339
@ kXRDC2_Mem_FLEXSPI2_Region0
Definition: MIMXRT1166_cm7.h:1364
@ kXRDC2_Mem_CAAM_Region0
Definition: MIMXRT1166_cm7.h:1332
@ kXRDC2_Mem_MECC2_Region10
Definition: MIMXRT1166_cm7.h:1438
@ kXRDC2_Mem_MECC2_Region15
Definition: MIMXRT1166_cm7.h:1443
@ kXRDC2_Mem_MECC1_Region12
Definition: MIMXRT1166_cm7.h:1424
@ kXRDC2_Mem_MECC1_Region3
Definition: MIMXRT1166_cm7.h:1415
@ kXRDC2_Mem_M4LMEM_Region8
Definition: MIMXRT1166_cm7.h:1388
@ kXRDC2_Mem_M4LMEM_Region7
Definition: MIMXRT1166_cm7.h:1387
@ kXRDC2_Mem_FLEXSPI2_Region5
Definition: MIMXRT1166_cm7.h:1369
@ kXRDC2_Mem_FLEXSPI1_Region11
Definition: MIMXRT1166_cm7.h:1359
@ kXRDC2_Mem_FLEXSPI1_Region9
Definition: MIMXRT1166_cm7.h:1357
@ kXRDC2_Mem_CAAM_Region4
Definition: MIMXRT1166_cm7.h:1336
@ kXRDC2_Mem_MECC1_Region9
Definition: MIMXRT1166_cm7.h:1421
@ kXRDC2_Mem_MECC2_Region4
Definition: MIMXRT1166_cm7.h:1432
@ kXRDC2_Mem_FLEXSPI1_Region2
Definition: MIMXRT1166_cm7.h:1350
@ kXRDC2_Mem_CAAM_Region10
Definition: MIMXRT1166_cm7.h:1342
@ kXRDC2_Mem_MECC1_Region1
Definition: MIMXRT1166_cm7.h:1413
@ kXRDC2_Mem_M4LMEM_Region9
Definition: MIMXRT1166_cm7.h:1389
@ kXRDC2_Mem_SEMC_Region11
Definition: MIMXRT1166_cm7.h:1455
@ kXRDC2_Mem_FLEXSPI2_Region9
Definition: MIMXRT1166_cm7.h:1373
@ kXRDC2_Mem_M4LMEM_Region13
Definition: MIMXRT1166_cm7.h:1393
@ kXRDC2_Mem_M7OC_Region10
Definition: MIMXRT1166_cm7.h:1406
@ kXRDC2_Mem_FLEXSPI1_Region6
Definition: MIMXRT1166_cm7.h:1354
@ kXRDC2_Mem_M4LMEM_Region2
Definition: MIMXRT1166_cm7.h:1382
@ kXRDC2_Mem_MECC1_Region0
Definition: MIMXRT1166_cm7.h:1412
@ kXRDC2_Mem_MECC1_Region7
Definition: MIMXRT1166_cm7.h:1419
@ kXRDC2_Mem_CAAM_Region11
Definition: MIMXRT1166_cm7.h:1343
@ kXRDC2_Mem_M4LMEM_Region10
Definition: MIMXRT1166_cm7.h:1390
@ kXRDC2_Mem_FLEXSPI1_Region5
Definition: MIMXRT1166_cm7.h:1353
@ kXRDC2_Mem_M7OC_Region2
Definition: MIMXRT1166_cm7.h:1398
@ kXRDC2_Mem_MECC2_Region5
Definition: MIMXRT1166_cm7.h:1433
@ kXRDC2_Mem_MECC1_Region14
Definition: MIMXRT1166_cm7.h:1426
@ kXRDC2_Mem_MECC1_Region4
Definition: MIMXRT1166_cm7.h:1416
@ kXRDC2_Mem_SEMC_Region3
Definition: MIMXRT1166_cm7.h:1447
@ kXRDC2_Mem_MECC1_Region6
Definition: MIMXRT1166_cm7.h:1418
@ kXRDC2_Mem_CAAM_Region1
Definition: MIMXRT1166_cm7.h:1333
@ kXRDC2_Mem_FLEXSPI2_Region12
Definition: MIMXRT1166_cm7.h:1376
@ kXRDC2_Mem_MECC2_Region1
Definition: MIMXRT1166_cm7.h:1429
@ kXRDC2_Mem_FLEXSPI2_Region15
Definition: MIMXRT1166_cm7.h:1379
@ kXRDC2_Mem_SEMC_Region13
Definition: MIMXRT1166_cm7.h:1457
@ kXRDC2_Mem_SEMC_Region9
Definition: MIMXRT1166_cm7.h:1453
@ kXRDC2_Mem_CAAM_Region9
Definition: MIMXRT1166_cm7.h:1341
@ kXRDC2_Mem_MECC2_Region6
Definition: MIMXRT1166_cm7.h:1434
@ kXRDC2_Mem_MECC2_Region0
Definition: MIMXRT1166_cm7.h:1428
@ kXRDC2_Mem_M7OC_Region7
Definition: MIMXRT1166_cm7.h:1403
@ kXRDC2_Mem_MECC2_Region9
Definition: MIMXRT1166_cm7.h:1437
@ kXRDC2_Mem_M7OC_Region1
Definition: MIMXRT1166_cm7.h:1397
@ kXRDC2_Mem_SEMC_Region7
Definition: MIMXRT1166_cm7.h:1451
@ kXRDC2_Mem_M7OC_Region13
Definition: MIMXRT1166_cm7.h:1409
@ kXRDC2_Mem_MECC1_Region11
Definition: MIMXRT1166_cm7.h:1423
@ kXRDC2_Mem_FLEXSPI2_Region7
Definition: MIMXRT1166_cm7.h:1371
@ kXRDC2_Mem_M7OC_Region15
Definition: MIMXRT1166_cm7.h:1411
@ kXRDC2_Mem_FLEXSPI1_Region14
Definition: MIMXRT1166_cm7.h:1362
@ kXRDC2_Mem_SEMC_Region5
Definition: MIMXRT1166_cm7.h:1449
@ kXRDC2_Mem_M4LMEM_Region3
Definition: MIMXRT1166_cm7.h:1383
@ kXRDC2_Mem_SEMC_Region2
Definition: MIMXRT1166_cm7.h:1446
@ kXRDC2_Mem_SEMC_Region14
Definition: MIMXRT1166_cm7.h:1458
@ kXRDC2_Mem_M7OC_Region9
Definition: MIMXRT1166_cm7.h:1405
@ kXRDC2_Mem_FLEXSPI1_Region0
Definition: MIMXRT1166_cm7.h:1348
@ kXRDC2_Mem_FLEXSPI2_Region13
Definition: MIMXRT1166_cm7.h:1377
@ kXRDC2_Mem_M7OC_Region14
Definition: MIMXRT1166_cm7.h:1410
@ kXRDC2_Mem_M7OC_Region4
Definition: MIMXRT1166_cm7.h:1400
@ kXRDC2_Mem_FLEXSPI2_Region11
Definition: MIMXRT1166_cm7.h:1375
@ kXRDC2_Mem_FLEXSPI1_Region12
Definition: MIMXRT1166_cm7.h:1360
@ kXRDC2_Mem_CAAM_Region15
Definition: MIMXRT1166_cm7.h:1347
@ kXRDC2_Mem_SEMC_Region8
Definition: MIMXRT1166_cm7.h:1452
@ kXRDC2_Mem_FLEXSPI1_Region13
Definition: MIMXRT1166_cm7.h:1361
@ kXRDC2_Mem_SEMC_Region15
Definition: MIMXRT1166_cm7.h:1459
@ kXRDC2_Mem_FLEXSPI2_Region3
Definition: MIMXRT1166_cm7.h:1367
@ kXRDC2_Mem_M7OC_Region6
Definition: MIMXRT1166_cm7.h:1402
@ kXRDC2_Mem_M4LMEM_Region5
Definition: MIMXRT1166_cm7.h:1385
@ kXRDC2_Mem_M7OC_Region8
Definition: MIMXRT1166_cm7.h:1404
@ kXRDC2_Mem_SEMC_Region12
Definition: MIMXRT1166_cm7.h:1456
@ kXRDC2_Mem_FLEXSPI2_Region14
Definition: MIMXRT1166_cm7.h:1378
@ kXRDC2_Mem_SEMC_Region0
Definition: MIMXRT1166_cm7.h:1444
@ kXRDC2_Mem_CAAM_Region13
Definition: MIMXRT1166_cm7.h:1345
@ kXRDC2_Mem_FLEXSPI1_Region15
Definition: MIMXRT1166_cm7.h:1363
@ kXRDC2_Mem_SEMC_Region6
Definition: MIMXRT1166_cm7.h:1450
@ kXRDC2_Mem_M4LMEM_Region12
Definition: MIMXRT1166_cm7.h:1392
@ kXRDC2_Mem_FLEXSPI2_Region6
Definition: MIMXRT1166_cm7.h:1370
@ kXRDC2_Mem_M7OC_Region5
Definition: MIMXRT1166_cm7.h:1401
@ kXRDC2_Mem_MECC1_Region10
Definition: MIMXRT1166_cm7.h:1422
@ kXRDC2_Mem_M4LMEM_Region4
Definition: MIMXRT1166_cm7.h:1384
@ kXRDC2_Mem_M4LMEM_Region0
Definition: MIMXRT1166_cm7.h:1380
@ kXRDC2_Mem_FLEXSPI2_Region8
Definition: MIMXRT1166_cm7.h:1372
@ kXRDC2_Mem_SEMC_Region4
Definition: MIMXRT1166_cm7.h:1448
@ kXRDC2_Mem_CAAM_Region14
Definition: MIMXRT1166_cm7.h:1346
Definition: MIMXRT1052.h:1683
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Definition: MIMXRT1166_cm4.h:4541
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Definition: MIMXRT1052.h:3550
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Definition: MIMXRT1166_cm4.h:33651
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Definition: MIMXRT1166_cm4.h:61880
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Definition: MIMXRT1166_cm4.h:67290
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Definition: MIMXRT1166_cm4.h:72538
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Definition: MIMXRT1166_cm4.h:72888
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Definition: MIMXRT1052.h:42276
Definition: MIMXRT1166_cm4.h:77856
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Definition: MIMXRT1166_cm4.h:81233
Definition: MIMXRT1166_cm4.h:81355
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Definition: MIMXRT1052.h:49060
Definition: MIMXRT1166_cm4.h:90584
Definition: MIMXRT1166_cm4.h:90782
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Definition: MIMXRT1052.h:50962
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Definition: MIMXRT1052.h:52224
Definition: MIMXRT1166_cm4.h:92798
Definition: MIMXRT1166_cm4.h:93188
Definition: hexdump.h:39