RTEMS 6.1-rc2
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xreg_cortexr5.h
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1/******************************************************************************
2* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved.
3* SPDX-License-Identifier: MIT
4******************************************************************************/
5
6/*****************************************************************************/
32#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */
33#define XREG_CORTEXR5_H /* by using protection macros */
34
35#ifdef __cplusplus
36extern "C" {
37#endif /* __cplusplus */
38
39/* GPRs */
40#define XREG_GPR0 r0
41#define XREG_GPR1 r1
42#define XREG_GPR2 r2
43#define XREG_GPR3 r3
44#define XREG_GPR4 r4
45#define XREG_GPR5 r5
46#define XREG_GPR6 r6
47#define XREG_GPR7 r7
48#define XREG_GPR8 r8
49#define XREG_GPR9 r9
50#define XREG_GPR10 r10
51#define XREG_GPR11 r11
52#define XREG_GPR12 r12
53#define XREG_GPR13 r13
54#define XREG_GPR14 r14
55#define XREG_GPR15 r15
56#define XREG_CPSR cpsr
57
58/* Coprocessor number defines */
59#define XREG_CP0 0
60#define XREG_CP1 1
61#define XREG_CP2 2
62#define XREG_CP3 3
63#define XREG_CP4 4
64#define XREG_CP5 5
65#define XREG_CP6 6
66#define XREG_CP7 7
67#define XREG_CP8 8
68#define XREG_CP9 9
69#define XREG_CP10 10
70#define XREG_CP11 11
71#define XREG_CP12 12
72#define XREG_CP13 13
73#define XREG_CP14 14
74#define XREG_CP15 15
75
76/* Coprocessor control register defines */
77#define XREG_CR0 cr0
78#define XREG_CR1 cr1
79#define XREG_CR2 cr2
80#define XREG_CR3 cr3
81#define XREG_CR4 cr4
82#define XREG_CR5 cr5
83#define XREG_CR6 cr6
84#define XREG_CR7 cr7
85#define XREG_CR8 cr8
86#define XREG_CR9 cr9
87#define XREG_CR10 cr10
88#define XREG_CR11 cr11
89#define XREG_CR12 cr12
90#define XREG_CR13 cr13
91#define XREG_CR14 cr14
92#define XREG_CR15 cr15
93
94/* Current Processor Status Register (CPSR) Bits */
95#define XREG_CPSR_THUMB_MODE 0x20U
96#define XREG_CPSR_MODE_BITS 0x1FU
97#define XREG_CPSR_SYSTEM_MODE 0x1FU
98#define XREG_CPSR_UNDEFINED_MODE 0x1BU
99#define XREG_CPSR_DATA_ABORT_MODE 0x17U
100#define XREG_CPSR_SVC_MODE 0x13U
101#define XREG_CPSR_IRQ_MODE 0x12U
102#define XREG_CPSR_FIQ_MODE 0x11U
103#define XREG_CPSR_USER_MODE 0x10U
104
105#define XREG_CPSR_IRQ_ENABLE 0x80U
106#define XREG_CPSR_FIQ_ENABLE 0x40U
107
108#define XREG_CPSR_N_BIT 0x80000000U
109#define XREG_CPSR_Z_BIT 0x40000000U
110#define XREG_CPSR_C_BIT 0x20000000U
111#define XREG_CPSR_V_BIT 0x10000000U
112
113/*MPU region definitions*/
114#define REGION_32B 0x00000004U
115#define REGION_64B 0x00000005U
116#define REGION_128B 0x00000006U
117#define REGION_256B 0x00000007U
118#define REGION_512B 0x00000008U
119#define REGION_1K 0x00000009U
120#define REGION_2K 0x0000000AU
121#define REGION_4K 0x0000000BU
122#define REGION_8K 0x0000000CU
123#define REGION_16K 0x0000000DU
124#define REGION_32K 0x0000000EU
125#define REGION_64K 0x0000000FU
126#define REGION_128K 0x00000010U
127#define REGION_256K 0x00000011U
128#define REGION_512K 0x00000012U
129#define REGION_1M 0x00000013U
130#define REGION_2M 0x00000014U
131#define REGION_4M 0x00000015U
132#define REGION_8M 0x00000016U
133#define REGION_16M 0x00000017U
134#define REGION_32M 0x00000018U
135#define REGION_64M 0x00000019U
136#define REGION_128M 0x0000001AU
137#define REGION_256M 0x0000001BU
138#define REGION_512M 0x0000001CU
139#define REGION_1G 0x0000001DU
140#define REGION_2G 0x0000001EU
141#define REGION_4G 0x0000001FU
142
143#define REGION_EN 0x00000001U
144
145
146
147#define SHAREABLE 0x00000004U /*shareable */
148#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/
149
150#define DEVICE_SHARED 0x00000001U /*device, shareable*/
151#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/
152
153#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/
154#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/
155
156#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/
157#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/
158
159#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/
160#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/
161
162#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/
163#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/
164
165/* inner and outer cache policies can be combined for different combinations */
166
167#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/
168#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/
169#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/
170#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/
171
172#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/
173#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/
174#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/
175#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/
176
177#define NO_ACCESS (0x00000000U<<8U) /*No access*/
178#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/
179#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/
180#define PRIV_RW_USER_RW (0x00000003UL<<8U) /*Full Access*/
181#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/
182#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/
183
184#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/
185
186
187/* CP15 defines */
188
189/* C0 Register defines */
190#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
191#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
192#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
193#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
194#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4"
195#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
196
197#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
198#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
199#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
200#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
201#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
202#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
203#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
204
205#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
206#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
207#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
208#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
209#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
210#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5"
211
212#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
213#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
214#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
215
216#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
217
218/* C1 Register Defines */
219#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
220#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
221#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
222
223
224/* XREG_CP15_CONTROL bit defines */
225#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
226#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
227#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
228#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
229#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
230#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
231#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
232#define XREG_CP15_CONTROL_V_BIT 0x00002000U
233#define XREG_CP15_CONTROL_I_BIT 0x00001000U
234#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
235#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
236#define XREG_CP15_CONTROL_B_BIT 0x00000080U
237#define XREG_CP15_CONTROL_C_BIT 0x00000004U
238#define XREG_CP15_CONTROL_A_BIT 0x00000002U
239#define XREG_CP15_CONTROL_M_BIT 0x00000001U
240/* C2 Register Defines */
241/* Not Used */
242
243/* C3 Register Defines */
244/* Not Used */
245
246/* C4 Register Defines */
247/* Not Used */
248
249/* C5 Register Defines */
250#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
251#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
252
253#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
254#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
255
256/* C6 Register Defines */
257#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
258#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
259
260#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0"
261#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2"
262#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4"
263
264#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0"
265
266/* C7 Register Defines */
267#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
268
269#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
270#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
271
272/* The CP15 register access below has been deprecated in favor of the new
273 * isb instruction in Cortex R5.
274 */
275#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
276#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
277#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7"
278
279#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
280#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
281
282
283#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
284#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
285
286#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0"
287/* The next two CP15 register accesses below have been deprecated in favor
288 * of the new dsb and dmb instructions in Cortex R5.
289 */
290#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
291#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
292
293#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
294
295#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
296
297#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
298#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
299
300/* C8 Register Defines */
301/* Not Used */
302
303
304/* C9 Register Defines */
305
306#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1"
307#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0"
308#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0"
309
310#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
311#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
312#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
313#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
314#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
315#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
316
317#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
318#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
319#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
320
321#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
322#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
323#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
324
325/* C10 Register Defines */
326/* Not used */
327
328/* C11 Register Defines */
329/* Not used */
330
331/* C12 Register Defines */
332/* Not used */
333
334/* C13 Register Defines */
335#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
336#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
337#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
338#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
339
340/* C14 Register Defines */
341/* not used */
342
343/* C15 Register Defines */
344#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0"
345
346
347
348
349/* MPE register definitions */
350#define XREG_FPSID c0
351#define XREG_FPSCR c1
352#define XREG_MVFR1 c6
353#define XREG_MVFR0 c7
354#define XREG_FPEXC c8
355#define XREG_FPINST c9
356#define XREG_FPINST2 c10
357
358/* FPSID bits */
359#define XREG_FPSID_IMPLEMENTER_BIT (24U)
360#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT)
361#define XREG_FPSID_SOFTWARE (0X00000001U << 23U)
362#define XREG_FPSID_ARCH_BIT (16U)
363#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT)
364#define XREG_FPSID_PART_BIT (8U)
365#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT)
366#define XREG_FPSID_VARIANT_BIT (4U)
367#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT)
368#define XREG_FPSID_REV_BIT (0U)
369#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT)
370
371/* FPSCR bits */
372#define XREG_FPSCR_N_BIT (0X00000001U << 31U)
373#define XREG_FPSCR_Z_BIT (0X00000001U << 30U)
374#define XREG_FPSCR_C_BIT (0X00000001U << 29U)
375#define XREG_FPSCR_V_BIT (0X00000001U << 28U)
376#define XREG_FPSCR_QC (0X00000001U << 27U)
377#define XREG_FPSCR_AHP (0X00000001U << 26U)
378#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U)
379#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U)
380#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U)
381#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U)
382#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U)
383#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U)
384#define XREG_FPSCR_RMODE_BIT (22U)
385#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT)
386#define XREG_FPSCR_STRIDE_BIT (20U)
387#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT)
388#define XREG_FPSCR_LENGTH_BIT (16U)
389#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT)
390#define XREG_FPSCR_IDC (0X00000001U << 7U)
391#define XREG_FPSCR_IXC (0X00000001U << 4U)
392#define XREG_FPSCR_UFC (0X00000001U << 3U)
393#define XREG_FPSCR_OFC (0X00000001U << 2U)
394#define XREG_FPSCR_DZC (0X00000001U << 1U)
395#define XREG_FPSCR_IOC (0X00000001U << 0U)
396
397/* MVFR0 bits */
398#define XREG_MVFR0_RMODE_BIT (28U)
399#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT)
400#define XREG_MVFR0_SHORT_VEC_BIT (24U)
401#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
402#define XREG_MVFR0_SQRT_BIT (20U)
403#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT)
404#define XREG_MVFR0_DIVIDE_BIT (16U)
405#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
406#define XREG_MVFR0_EXEC_TRAP_BIT (12U)
407#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
408#define XREG_MVFR0_DP_BIT (8U)
409#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT)
410#define XREG_MVFR0_SP_BIT (4U)
411#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT)
412#define XREG_MVFR0_A_SIMD_BIT (0U)
413#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT)
414
415/* FPEXC bits */
416#define XREG_FPEXC_EX (0X00000001U << 31U)
417#define XREG_FPEXC_EN (0X00000001U << 30U)
418#define XREG_FPEXC_DEX (0X00000001U << 29U)
419
420
421#ifdef __cplusplus
422}
423#endif /* __cplusplus */
424
425#endif /* XREG_CORTEXR5_H */
426