RTEMS 6.1-rc2
Loading...
Searching...
No Matches
raspberrypi.h
Go to the documentation of this file.
1
9/*
10 * Copyright (c) 2022 Mohd Noor Aman
11 *
12 * The license and distribution terms for this file may be
13 * found in the file LICENSE in this distribution or at
14 *
15 * http://www.rtems.org/license/LICENSE
16 *
17 */
18
19
20#ifndef LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
21#define LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
22
23
24#include <bspopts.h>
25#include <stdint.h>
26#include <bsp/utility.h>
27
28
45#define BCM2711_REG(x) (*(volatile uint64_t *)(x))
46#define BCM2711_BIT(n) (1 << (n))
47
56#define RPI_PERIPHERAL_BASE 0xFE000000
57#define BASE_OFFSET 0xFE000000
58#define RPI_PERIPHERAL_SIZE 0x01800000
59
65#define BUS_TO_PHY(x) ((x) - BASE_OFFSET)
66
75#define BCM2711_CLOCK_FREQ 250000000
76
77#define BCM2711_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400)
78
79#define BCM2711_TIMER_LOD (BCM2711_TIMER_BASE + 0x00)
80#define BCM2711_TIMER_VAL (BCM2711_TIMER_BASE + 0x04)
81#define BCM2711_TIMER_CTL (BCM2711_TIMER_BASE + 0x08)
82#define BCM2711_TIMER_CLI (BCM2711_TIMER_BASE + 0x0C)
83#define BCM2711_TIMER_RIS (BCM2711_TIMER_BASE + 0x10)
84#define BCM2711_TIMER_MIS (BCM2711_TIMER_BASE + 0x14)
85#define BCM2711_TIMER_RLD (BCM2711_TIMER_BASE + 0x18)
86#define BCM2711_TIMER_DIV (BCM2711_TIMER_BASE + 0x1C)
87#define BCM2711_TIMER_CNT (BCM2711_TIMER_BASE + 0x20)
88
89#define BCM2711_TIMER_PRESCALE 0xF9
90
99#define BCM2711_PM_PASSWD_MAGIC 0x5a000000
100
101#define BCM2711_PM_BASE (RPI_PERIPHERAL_BASE + 0x100000)
102
103#define BCM2711_PM_GNRIC (BCM2711_PM_BASE + 0x00)
104#define BCM2711_PM_GNRIC_POWUP 0x00000001
105#define BCM2711_PM_GNRIC_POWOK 0x00000002
106#define BCM2711_PM_GNRIC_ISPOW 0x00000004
107#define BCM2711_PM_GNRIC_MEMREP 0x00000008
108#define BCM2711_PM_GNRIC_MRDONE 0x00000010
109#define BCM2711_PM_GNRIC_ISFUNC 0x00000020
110#define BCM2711_PM_GNRIC_RSTN 0x00000fc0
111#define BCM2711_PM_GNRIC_ENAB 0x00001000
112#define BCM2711_PM_GNRIC_CFG 0x007f0000
113
114#define BCM2711_PM_AUDIO (BCM2711_PM_BASE + 0x04)
115#define BCM2711_PM_AUDIO_APSM 0x000fffff
116#define BCM2711_PM_AUDIO_CTRLEN 0x00100000
117#define BCM2711_PM_AUDIO_RSTN 0x00200000
118
119#define BCM2711_PM_STATUS (BCM2711_PM_BASE + 0x18)
120
121#define BCM2711_PM_RSTC (BCM2711_PM_BASE + 0x1c)
122#define BCM2711_PM_RSTC_DRCFG 0x00000003
123#define BCM2711_PM_RSTC_WRCFG 0x00000030
124#define BCM2711_PM_RSTC_WRCFG_FULL 0x00000020
125#define BCM2711_PM_RSTC_SRCFG 0x00000300
126#define BCM2711_PM_RSTC_QRCFG 0x00003000
127#define BCM2711_PM_RSTC_FRCFG 0x00030000
128#define BCM2711_PM_RSTC_HRCFG 0x00300000
129
130#define BCM2711_PM_RSTS (BCM2711_PM_BASE + 0x20)
131#define BCM2711_PM_RSTS_HADDRQ 0x00000001
132#define BCM2711_PM_RSTS_HADDRF 0x00000002
133#define BCM2711_PM_RSTS_HADDRH 0x00000004
134#define BCM2711_PM_RSTS_HADWRQ 0x00000010
135#define BCM2711_PM_RSTS_HADWRF 0x0000002
136#define BCM2711_PM_RSTS_HADWRH 0x00000040
137#define BCM2711_PM_RSTS_HADSRQ 0x00000100
138#define BCM2711_PM_RSTS_HADSRF 0x00000200
139#define BCM2711_PM_RSTS_HADSRH 0x00000400
140#define BCM2711_PM_RSTS_HADPOR 0x00001000
141
142#define BCM2711_PM_WDOG (BCM2711_PM_BASE + 0x24)
143
155#define BCM2711_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000)
156
157#define AUX_ENABLES (BCM2711_AUX_BASE + 0x04)
158#define AUX_MU_IO_REG (BCM2711_AUX_BASE + 0x40)
159#define AUX_MU_IER_REG (BCM2711_AUX_BASE + 0x44)
160#define AUX_MU_IIR_REG (BCM2711_AUX_BASE + 0x48)
161#define AUX_MU_LCR_REG (BCM2711_AUX_BASE + 0x4C)
162#define AUX_MU_MCR_REG (BCM2711_AUX_BASE + 0x50)
163#define AUX_MU_LSR_REG (BCM2711_AUX_BASE + 0x54)
164#define AUX_MU_MSR_REG (BCM2711_AUX_BASE + 0x58)
165#define AUX_MU_SCRATCH (BCM2711_AUX_BASE + 0x5C)
166#define AUX_MU_CNTL_REG (BCM2711_AUX_BASE + 0x60)
167#define AUX_MU_STAT_REG (BCM2711_AUX_BASE + 0x64)
168#define AUX_MU_BAUD_REG (BCM2711_AUX_BASE + 0x68)
169
187#define BCM2711_GPU_TIMER_BASE (RPI_PERIPHERAL_BASE + 0x3000)
188
189#define BCM2711_GPU_TIMER_CS (BCM2711_GPU_TIMER_BASE + 0x00)
190#define BCM2711_GPU_TIMER_CS_M0 0x00000001
191#define BCM2711_GPU_TIMER_CS_M1 0x00000002
192#define BCM2711_GPU_TIMER_CS_M2 0x00000004
193#define BCM2711_GPU_TIMER_CS_M3 0x00000008
194#define BCM2711_GPU_TIMER_CLO (BCM2711_GPU_TIMER_BASE + 0x04)
195#define BCM2711_GPU_TIMER_CHI (BCM2711_GPU_TIMER_BASE + 0x08)
196#define BCM2711_GPU_TIMER_C0 (BCM2711_GPU_TIMER_BASE + 0x0C)
197#define BCM2711_GPU_TIMER_C1 (BCM2711_GPU_TIMER_BASE + 0x10)
198#define BCM2711_GPU_TIMER_C2 (BCM2711_GPU_TIMER_BASE + 0x14)
199#define BCM2711_GPU_TIMER_C3 (BCM2711_GPU_TIMER_BASE + 0x18)
200
214#define BCM2711_EMMC_BASE (RPI_PERIPHERAL_BASE + 0x300000)
215
224#define BCM2711_MBOX_BASE (RPI_PERIPHERAL_BASE+0xB880)
225
226#define BCM2711_MBOX_READ (BCM2711_MBOX_BASE+0x00)
227#define BCM2711_MBOX_PEEK (BCM2711_MBOX_BASE+0x10)
228#define BCM2711_MBOX_SENDER (BCM2711_MBOX_BASE+0x14)
229#define BCM2711_MBOX_STATUS (BCM2711_MBOX_BASE+0x18)
230#define BCM2711_MBOX_WRITE (BCM2711_MBOX_BASE+0x20)
231#define BCM2711_MBOX_CONFIG (BCM2711_MBOX_BASE+0x1C)
232
233#define BCM2711_MBOX_RESPONSE 0x80000000
234#define BCM2711_MBOX_FULL 0x80000000
235#define BCM2711_MBOX_EMPTY 0x40000000
236
245/* Power Manager channel */
246#define BCM2711_MBOX_CHANNEL_PM 0
247/* Framebuffer channel */
248#define BCM2711_MBOX_CHANNEL_FB 1
249 /* Virtual UART channel */
250#define BCM2711_MBOX_CHANNEL_VUART 2
251 /* VCHIQ channel */
252#define BCM2711_MBOX_CHANNEL_VCHIQ 3
253 /* LEDs channel */
254#define BCM2711_MBOX_CHANNEL_LED 4
255 /* Button channel */
256#define BCM2711_MBOX_CHANNEL_BUTTON 5
257 /* Touch screen channel */
258#define BCM2711_MBOX_CHANNEL_TOUCHS 6
259
260#define BCM2711_MBOX_CHANNEL_COUNT 7
261/* Property tags (ARM <-> VC) channel */
262#define BCM2711_MBOX_CHANNEL_PROP_AVC 8
263 /* Property tags (VC <-> ARM) channel */
264#define BCM2711_MBOX_CHANNEL_PROP_VCA 9
265
276/* Timers interrupt control registers */
277#define BCM2711_CORE0_TIMER_IRQ_CTRL_BASE 0xFF800040
278#define BCM2711_CORE1_TIMER_IRQ_CTRL_BASE 0xFF800044
279#define BCM2711_CORE2_TIMER_IRQ_CTRL_BASE 0xFF800048
280#define BCM2711_CORE3_TIMER_IRQ_CTRL_BASE 0xFF80004C
281
282#define BCM2711_CORE_TIMER_IRQ_CTRL(cpuidx) \
283 (BCM2711_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))
284
285
292#define BCM2711_LOCAL_REGS_BASE 0x4C0000000
293#define BCM2711_LOCAL_REGS_SIZE 0x100
294
295#define BCM2711_LOCAL_ARM_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x00)
296#define BCM2711_LOCAL_CORE_IRQ_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x0c)
297#define BCM2711_LOCAL_PMU_CONTROL_SET (BCM2711_LOCAL_REGS_BASE + 0x10)
298#define BCM2711_LOCAL_PMU_CONTROL_CLR (BCM2711_LOCAL_REGS_BASE + 0x14)
299#define BCM2711_LOCAL_PERI_IRQ_ROUTE0 (BCM2711_LOCAL_REGS_BASE + 0x24)
300#define BCM2711_LOCAL_AXI_QUIET_TIME (BCM2711_LOCAL_REGS_BASE + 0x30)
301#define BCM2711_LOCAL_LOCAL_TIMER_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x34)
302#define BCM2711_LOCAL_LOCAL_TIMER_IRQ (BCM2711_LOCAL_REGS_BASE + 0x38)
303
304#define BCM2711_LOCAL_TIMER_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x40)
305#define BCM2711_LOCAL_TIMER_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x44)
306#define BCM2711_LOCAL_TIMER_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x48)
307#define BCM2711_LOCAL_TIMER_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x4c)
308
309#define BCM2711_LOCAL_MAILBOX_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x50)
310#define BCM2711_LOCAL_MAILBOX_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x54)
311#define BCM2711_LOCAL_MAILBOX_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x58)
312#define BCM2711_LOCAL_MAILBOX_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x5c)
313
314#define BCM2711_LOCAL_IRQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x60)
315#define BCM2711_LOCAL_IRQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x64)
316#define BCM2711_LOCAL_IRQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x68)
317#define BCM2711_LOCAL_IRQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x6c)
318
319#define BCM2711_LOCAL_FIQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x70)
320#define BCM2711_LOCAL_FIQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x74)
321#define BCM2711_LOCAL_FIQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x78)
322#define BCM2711_LOCAL_FIQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x7c)
323
332#define BCM2711_MAILBOX_00_WRITE_SET_BASE 0x4C000080
333#define BCM2711_MAILBOX_01_WRITE_SET_BASE 0x4C000084
334#define BCM2711_MAILBOX_02_WRITE_SET_BASE 0x4C000088
335#define BCM2711_MAILBOX_03_WRITE_SET_BASE 0x4C00008C
336#define BCM2711_MAILBOX_04_WRITE_SET_BASE 0x4C000090
337#define BCM2711_MAILBOX_05_WRITE_SET_BASE 0x4C000094
338#define BCM2711_MAILBOX_06_WRITE_SET_BASE 0x4C000098
339#define BCM2711_MAILBOX_07_WRITE_SET_BASE 0x4C00009C
340#define BCM2711_MAILBOX_08_WRITE_SET_BASE 0x4C0000A0
341#define BCM2711_MAILBOX_09_WRITE_SET_BASE 0x4C0000A4
342#define BCM2711_MAILBOX_10_WRITE_SET_BASE 0x4C0000A8
343#define BCM2711_MAILBOX_11_WRITE_SET_BASE 0x4C0000AC
344#define BCM2711_MAILBOX_12_WRITE_SET_BASE 0x4C0000B0
345#define BCM2711_MAILBOX_13_WRITE_SET_BASE 0x4C0000B4
346#define BCM2711_MAILBOX_14_WRITE_SET_BASE 0x4C0000B8
347#define BCM2711_MAILBOX_15_WRITE_SET_BASE 0x4C0000BC
348
349#define BCM2711_MAILBOX_00_READ_CLEAR_BASE 0x4C0000C0
350#define BCM2711_MAILBOX_01_READ_CLEAR_BASE 0x4C0000C4
351#define BCM2711_MAILBOX_02_READ_CLEAR_BASE 0x4C0000C8
352#define BCM2711_MAILBOX_03_READ_CLEAR_BASE 0x4C0000CC
353#define BCM2711_MAILBOX_04_READ_CLEAR_BASE 0x4C0000D0
354#define BCM2711_MAILBOX_05_READ_CLEAR_BASE 0x4C0000D4
355#define BCM2711_MAILBOX_06_READ_CLEAR_BASE 0x4C0000D8
356#define BCM2711_MAILBOX_07_READ_CLEAR_BASE 0x4C0000DC
357#define BCM2711_MAILBOX_08_READ_CLEAR_BASE 0x4C0000E0
358#define BCM2711_MAILBOX_09_READ_CLEAR_BASE 0x4C0000E4
359#define BCM2711_MAILBOX_10_READ_CLEAR_BASE 0x4C0000E8
360#define BCM2711_MAILBOX_11_READ_CLEAR_BASE 0x4C0000EC
361#define BCM2711_MAILBOX_12_READ_CLEAR_BASE 0x4C0000F0
362#define BCM2711_MAILBOX_13_READ_CLEAR_BASE 0x4C0000F4
363#define BCM2711_MAILBOX_14_READ_CLEAR_BASE 0x4C0000F8
364#define BCM2711_MAILBOX_15_READ_CLEAR_BASE 0x4C0000FC
365
366
373#define BCM2711_ARMC_REGS_BASE (RPI_PERIPHERAL_BASE + 0xB200)
374#define BCM2711_ARMC_REGS_SIZE 0x200
375
376#define BCM2711_ARMC_IRQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x00)
377#define BCM2711_ARMC_IRQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x04)
378#define BCM2711_ARMC_IRQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x08)
379#define BCM2711_ARMC_IRQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x10)
380#define BCM2711_ARMC_IRQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x14)
381#define BCM2711_ARMC_IRQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x18)
382#define BCM2711_ARMC_IRQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x20)
383#define BCM2711_ARMC_IRQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x24)
384#define BCM2711_ARMC_IRQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x28)
385
386#define BCM2711_ARMC_IRQ_STATUS0 (BCM2711_ARMC_REGS_BASE + 0x30)
387#define BCM2711_ARMC_IRQ_STATUS1 (BCM2711_ARMC_REGS_BASE + 0x34)
388#define BCM2711_ARMC_IRQ_STATUS2 (BCM2711_ARMC_REGS_BASE + 0x38)
389
390#define BCM2711_ARMC_IRQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x40)
391#define BCM2711_ARMC_IRQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x44)
392#define BCM2711_ARMC_IRQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x48)
393#define BCM2711_ARMC_IRQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x50)
394#define BCM2711_ARMC_IRQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x54)
395#define BCM2711_ARMC_IRQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x58)
396#define BCM2711_ARMC_IRQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x60)
397#define BCM2711_ARMC_IRQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x64)
398#define BCM2711_ARMC_IRQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x68)
399
400#define BCM2711_ARMC_IRQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x80)
401#define BCM2711_ARMC_IRQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x84)
402#define BCM2711_ARMC_IRQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x88)
403#define BCM2711_ARMC_IRQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x90)
404#define BCM2711_ARMC_IRQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x94)
405#define BCM2711_ARMC_IRQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x98)
406#define BCM2711_ARMC_IRQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xA0)
407#define BCM2711_ARMC_IRQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xA4)
408#define BCM2711_ARMC_IRQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xA8)
409
410#define BCM2711_ARMC_IRQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0xC0)
411#define BCM2711_ARMC_IRQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0xC4)
412#define BCM2711_ARMC_IRQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0xC8)
413#define BCM2711_ARMC_IRQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0xD0)
414#define BCM2711_ARMC_IRQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0xD4)
415#define BCM2711_ARMC_IRQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0xD8)
416#define BCM2711_ARMC_IRQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xE0)
417#define BCM2711_ARMC_IRQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xE4)
418#define BCM2711_ARMC_IRQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xE8)
419
420
421
422#define BCM2711_ARMC_FIQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x100)
423#define BCM2711_ARMC_FIQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x104)
424#define BCM2711_ARMC_FIQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x108)
425#define BCM2711_ARMC_FIQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x110)
426#define BCM2711_ARMC_FIQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x114)
427#define BCM2711_ARMC_FIQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x118)
428#define BCM2711_ARMC_FIQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x120)
429#define BCM2711_ARMC_FIQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x124)
430#define BCM2711_ARMC_FIQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x128)
431
432#define BCM2711_ARMC_FIQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x140)
433#define BCM2711_ARMC_FIQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x144)
434#define BCM2711_ARMC_FIQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x148)
435#define BCM2711_ARMC_FIQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x150)
436#define BCM2711_ARMC_FIQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x154)
437#define BCM2711_ARMC_FIQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x158)
438#define BCM2711_ARMC_FIQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x160)
439#define BCM2711_ARMC_FIQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x164)
440#define BCM2711_ARMC_FIQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x168)
441
442#define BCM2711_ARMC_FIQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x180)
443#define BCM2711_ARMC_FIQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x184)
444#define BCM2711_ARMC_FIQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x188)
445#define BCM2711_ARMC_FIQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x190)
446#define BCM2711_ARMC_FIQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x194)
447#define BCM2711_ARMC_FIQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x198)
448#define BCM2711_ARMC_FIQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1A0)
449#define BCM2711_ARMC_FIQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1A4)
450#define BCM2711_ARMC_FIQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1A8)
451
452#define BCM2711_ARMC_FIQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x1C0)
453#define BCM2711_ARMC_FIQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x1C4)
454#define BCM2711_ARMC_FIQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x1C8)
455#define BCM2711_ARMC_FIQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1D0)
456#define BCM2711_ARMC_FIQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1D4)
457#define BCM2711_ARMC_FIQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1D8)
458#define BCM2711_ARMC_FIQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1E0)
459#define BCM2711_ARMC_FIQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1E4)
460#define BCM2711_ARMC_FIQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1E8)
461
462#define BCM2711_ARMC_SWIRQ_SET (BCM2711_ARMC_REGS_BASE + 0x1F0)
463#define BCM2711_ARMC_SWIRQ_CLEAR (BCM2711_ARMC_REGS_BASE + 0x1F4)
464
465
466
467
468
471#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */
This header file provides utility macros for BSPs.