RTEMS 6.1-rc2
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xil_exception.h
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1/******************************************************************************
2* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved.
3* SPDX-License-Identifier: MIT
4******************************************************************************/
5
6/*****************************************************************************/
61#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
62#define XIL_EXCEPTION_H /* by using protection macros */
63
64/***************************** Include Files ********************************/
65
66#include "xil_types.h"
67#include "xpseudo_asm.h"
68#include "bspconfig.h"
69#include "xparameters.h"
70
71#ifdef __cplusplus
72extern "C" {
73#endif
74
75/************************** Constant Definitions ****************************/
76
77#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
78#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
79#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
80
81#define XIL_EXCEPTION_ID_FIRST 0U
82#if defined (__aarch64__)
83#define XIL_EXCEPTION_ID_SYNC_INT 1U
84#define XIL_EXCEPTION_ID_IRQ_INT 2U
85#define XIL_EXCEPTION_ID_FIQ_INT 3U
86#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
87#define XIL_EXCEPTION_ID_LAST 5U
88#else
89#define XIL_EXCEPTION_ID_RESET 0U
90#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
91#define XIL_EXCEPTION_ID_SWI_INT 2U
92#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
93#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
94#define XIL_EXCEPTION_ID_IRQ_INT 5U
95#define XIL_EXCEPTION_ID_FIQ_INT 6U
96#define XIL_EXCEPTION_ID_LAST 6U
97#endif
98
99/*
100 * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
101 */
102#if defined (versal) && !defined(ARMR5) && EL3
103#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
104#else
105#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
106#endif
107
108/**************************** Type Definitions ******************************/
109
113typedef void (*Xil_ExceptionHandler)(void *data);
114typedef void (*Xil_InterruptHandler)(void *data);
115
116typedef struct {
117 Xil_ExceptionHandler Handler;
118 void *Data;
119} XExc_VectorTableEntry;
120
121extern XExc_VectorTableEntry XExc_VectorTable[];
122
127/***************** Macros (Inline Functions) Definitions ********************/
128
129/****************************************************************************/
141#if defined (versal) && !defined(ARMR5) && EL3
142/*
143 * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
144 * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
145 * ignoring argument passed by user.
146 */
147#define Xil_ExceptionEnableMask(Mask) \
148 mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
149#elif defined (__GNUC__) || defined (__ICCARM__)
150#define Xil_ExceptionEnableMask(Mask) \
151 mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
152#else
153#define Xil_ExceptionEnableMask(Mask) \
154 { \
155 register u32 Reg __asm("cpsr"); \
156 mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
157 }
158#endif
159/****************************************************************************/
168#if defined (versal) && !defined(ARMR5) && EL3
169#define Xil_ExceptionEnable() \
170 Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
171#else
172#define Xil_ExceptionEnable() \
173 Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
174#endif
175
176/****************************************************************************/
188#if defined (versal) && !defined(ARMR5) && EL3
189/*
190 * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
191 * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
192 * ignoring argument passed by user.
193 */
194#define Xil_ExceptionDisableMask(Mask) \
195 mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
196#elif defined (__GNUC__) || defined (__ICCARM__)
197#define Xil_ExceptionDisableMask(Mask) \
198 mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
199#else
200#define Xil_ExceptionDisableMask(Mask) \
201 { \
202 register u32 Reg __asm("cpsr"); \
203 mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
204 }
205#endif
206/****************************************************************************/
215#define Xil_ExceptionDisable() \
216 Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
217
218#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) )
219/****************************************************************************/
241#define Xil_EnableNestedInterrupts() \
242 __asm__ __volatile__ ("mrs X1, ELR_EL3"); \
243 __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \
244 __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
245 __asm__ __volatile__ ("mrs X1, DAIF"); \
246 __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
247 __asm__ __volatile__ ("msr DAIF, X1"); \
248
249/****************************************************************************/
266#define Xil_DisableNestedInterrupts() \
267 __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
268 __asm__ __volatile__ ("msr ELR_EL3, X1"); \
269 __asm__ __volatile__ ("msr SPSR_EL3, X2"); \
270 __asm__ __volatile__ ("mrs X1, DAIF"); \
271 __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
272 __asm__ __volatile__ ("msr DAIF, X1"); \
273
274#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1))
275/****************************************************************************/
295#define Xil_EnableNestedInterrupts() \
296 __asm__ __volatile__ ("mrs X1, ELR_EL1"); \
297 __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \
298 __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
299 __asm__ __volatile__ ("mrs X1, DAIF"); \
300 __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
301 __asm__ __volatile__ ("msr DAIF, X1"); \
302
303/****************************************************************************/
320#define Xil_DisableNestedInterrupts() \
321 __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
322 __asm__ __volatile__ ("msr ELR_EL1, X1"); \
323 __asm__ __volatile__ ("msr SPSR_EL1, X2"); \
324 __asm__ __volatile__ ("mrs X1, DAIF"); \
325 __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
326 __asm__ __volatile__ ("msr DAIF, X1"); \
327
328#elif (!defined (__aarch64__) && !defined (ARMA53_32))
329/****************************************************************************/
349#define Xil_EnableNestedInterrupts() \
350 __asm__ __volatile__ ("stmfd sp!, {lr}"); \
351 __asm__ __volatile__ ("mrs lr, spsr"); \
352 __asm__ __volatile__ ("stmfd sp!, {lr}"); \
353 __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
354 __asm__ __volatile__ ("stmfd sp!, {lr}");
355/****************************************************************************/
371#define Xil_DisableNestedInterrupts() \
372 __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
373 __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
374 __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
375 __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
376 __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
377
378#endif
379/************************** Variable Definitions ****************************/
380
381/************************** Function Prototypes *****************************/
382
383extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
384 Xil_ExceptionHandler Handler,
385 void *Data);
386
387extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
388extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
389 Xil_ExceptionHandler *Handler, void **Data);
390
391extern void Xil_ExceptionInit(void);
392#if defined (__aarch64__)
393void Xil_SyncAbortHandler(void *CallBackRef);
394void Xil_SErrorAbortHandler(void *CallBackRef);
395#else
396extern void Xil_DataAbortHandler(void *CallBackRef);
397extern void Xil_PrefetchAbortHandler(void *CallBackRef);
398extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
399#endif
400
401#ifdef __cplusplus
402}
403#endif /* __cplusplus */
404
405#endif /* XIL_EXCEPTION_H */