RTEMS 6.1-rc2
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xil_cache.h
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1/******************************************************************************
2* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
3* SPDX-License-Identifier: MIT
4******************************************************************************/
5
6/*****************************************************************************/
29#ifndef XIL_CACHE_H
30#define XIL_CACHE_H
31
32#include "xil_types.h"
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
42#if defined (__GNUC__)
43#define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
44 XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param))
45
46#define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
47 XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param))
48
49#define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
50 XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param))
51
52#define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
53 XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
54#elif defined (__ICCARM__)
55#define asm_inval_dc_line_mva_poc(param) __asm volatile("mcr " \
56 XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param))
57
58#define asm_clean_inval_dc_line_sw(param) __asm volatile("mcr " \
59 XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param))
60
61#define asm_clean_inval_dc_line_mva_poc(param) __asm volatile("mcr " \
62 XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param))
63
64#define asm_inval_ic_line_mva_pou(param) __asm volatile("mcr " \
65 XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
66#endif
67
72void Xil_DCacheEnable(void);
73void Xil_DCacheDisable(void);
74void Xil_DCacheInvalidate(void);
75void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
76void Xil_DCacheFlush(void);
77void Xil_DCacheFlushRange(INTPTR adr, u32 len);
78void Xil_DCacheInvalidateLine(INTPTR adr);
79void Xil_DCacheFlushLine(INTPTR adr);
80void Xil_DCacheStoreLine(INTPTR adr);
81
82void Xil_ICacheEnable(void);
83void Xil_ICacheDisable(void);
84void Xil_ICacheInvalidate(void);
85void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
86void Xil_ICacheInvalidateLine(INTPTR adr);
87
88#ifdef __cplusplus
89}
90#endif
91
92#endif
void Xil_ICacheInvalidate(void)
Invalidate the entire instruction cache.
Definition: xil_cache.c:627
void Xil_DCacheEnable(void)
Enable the Data cache.
Definition: xil_cache.c:90
void Xil_ICacheInvalidateLine(INTPTR adr)
Invalidate an instruction cache line. If the instruction specified by the parameter adr is cached by ...
Definition: xil_cache.c:654
void Xil_ICacheDisable(void)
Disable the instruction cache.
Definition: xil_cache.c:594
void Xil_DCacheDisable(void)
Disable the Data cache.
Definition: xil_cache.c:127
void Xil_DCacheInvalidate(void)
Invalidate the Data cache. The contents present in the cache are cleaned and invalidated.
Definition: xil_cache.c:257
void Xil_ICacheEnable(void)
Enable the instruction cache.
Definition: xil_cache.c:558
void Xil_DCacheFlush(void)
Flush the Data cache.
Definition: xil_cache.c:429
void Xil_DCacheFlushLine(INTPTR adr)
Flush a Data cache line. If the byte specified by the address (adr) is cached by the Data cache,...
Definition: xil_cache.c:533
void Xil_DCacheInvalidateLine(INTPTR adr)
Invalidate a Data cache line. The cacheline is cleaned and invalidated.
Definition: xil_cache.c:364
#define Xil_ICacheInvalidateRange(Addr, Len)
Invalidate the instruction cache for the given address range. If the bytes specified by the address (...
Definition: xil_cache.h:376
#define Xil_DCacheInvalidateRange(Addr, Len)
Invalidate the Data cache for the given address range. If the bytes specified by the address (adr) ar...
Definition: xil_cache.h:313
void Xil_DCacheStoreLine(INTPTR adr)
Store a Data cache line. If the byte specified by the address (adr) is cached by the Data cache and t...
Definition: xil_cache.c:390