RTEMS 6.1-rc2
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cpuimpl.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _RTEMS_SCORE_CPUIMPL_H
38#define _RTEMS_SCORE_CPUIMPL_H
39
40#include <rtems/score/cpu.h>
41
52#define CPU_PER_CPU_CONTROL_SIZE 0
53
54#ifdef ARM_MULTILIB_ARCH_V4
55
56#if defined(ARM_MULTILIB_VFP_D32)
57#define CPU_INTERRUPT_FRAME_SIZE 240
58#elif defined(ARM_MULTILIB_VFP)
59#define CPU_INTERRUPT_FRAME_SIZE 112
60#else
61#define CPU_INTERRUPT_FRAME_SIZE 40
62#endif
63
64#endif /* ARM_MULTILIB_ARCH_V4 */
65
66#define CPU_THREAD_LOCAL_STORAGE_VARIANT 11
67
68#ifndef ASM
69
70#ifdef __cplusplus
71extern "C" {
72#endif
73
74#ifdef ARM_MULTILIB_ARCH_V4
75
76typedef struct {
77#ifdef ARM_MULTILIB_VFP
78 uint32_t fpscr;
79#ifdef ARM_MULTILIB_VFP_D32
80 double d16;
81 double d17;
82 double d18;
83 double d19;
84 double d20;
85 double d21;
86 double d22;
87 double d23;
88 double d24;
89 double d25;
90 double d26;
91 double d27;
92 double d28;
93 double d29;
94 double d30;
95 double d31;
96#endif /* ARM_MULTILIB_VFP_D32 */
97 double d0;
98 double d1;
99 double d2;
100 double d3;
101 double d4;
102 double d5;
103 double d6;
104 double d7;
105#endif /* ARM_MULTILIB_VFP */
106#ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE
107 uint32_t r0;
108 uint32_t r1;
109 uint32_t r2;
110 uint32_t r3;
111 uint32_t r7;
112 uint32_t r9;
113 uint32_t r12;
114 uint32_t lr;
115 uint32_t return_pc;
116 uint32_t return_cpsr;
117#else /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
118 uint32_t r9;
119 uint32_t lr;
120 uint32_t r0;
121 uint32_t r1;
122 uint32_t r2;
123 uint32_t r3;
124 uint32_t return_pc;
125 uint32_t return_cpsr;
126 uint32_t r7;
127 uint32_t r12;
128#endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
130
131#ifdef RTEMS_SMP
132
133static inline struct Per_CPU_Control *_ARM_Get_current_per_CPU_control( void )
134{
135 struct Per_CPU_Control *cpu_self;
136
137 /* Use PL1 only Thread ID Register (TPIDRPRW) */
138 __asm__ volatile (
139 "mrc p15, 0, %0, c13, c0, 4"
140 : "=r" ( cpu_self )
141 );
142
143 return cpu_self;
144}
145
146#define _CPU_Get_current_per_CPU_control() _ARM_Get_current_per_CPU_control()
147
148#endif /* RTEMS_SMP */
149
150#endif /* ARM_MULTILIB_ARCH_V4 */
151
152RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
153
154void _CPU_Context_volatile_clobber( uintptr_t pattern );
155
156void _CPU_Context_validate( uintptr_t pattern );
157
158static inline void _CPU_Instruction_illegal( void )
159{
160 __asm__ volatile ( "udf" );
161}
162
163static inline void _CPU_Instruction_no_operation( void )
164{
165 __asm__ volatile ( "nop" );
166}
167
168static inline void _CPU_Use_thread_local_storage(
170)
171{
172#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
173 __asm__ volatile (
174 "mcr p15, 0, %0, c13, c0, 3" : : "r" ( context->thread_id ) : "memory"
175 );
176#else
177 (void) context;
178#endif
179}
180
181static inline void *_CPU_Get_TLS_thread_pointer(
183)
184{
185 return (void *) context->thread_id;
186}
187
188#ifdef __cplusplus
189}
190#endif
191
192#endif /* ASM */
193
196#endif /* _RTEMS_SCORE_CPUIMPL_H */
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
rtems_termios_device_context * context
Definition: console-config.c:62
Interrupt stack frame (ISF).
Definition: cpuimpl.h:66
Thread register context.
Definition: cpu.h:169
Per CPU Core Structure.
Definition: percpu.h:384