RTEMS 6.1-rc2
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tx4938.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
9/*
10 * COPYRIGHT (c) 1989-2012.
11 * On-Line Applications Research Corporation (OAR).
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __TX4938_h
36#define __TX4938_h
37
38#define TX4938_REG_BASE 0xFF1F0000
39
40/* PCI1 Registers */
41#define TX4938_PCI1_PCIID 0x7000
42#define TX4938_PCI1_PCISTATUS 0x7004
43#define TX4938_PCI1_PCICFG1 0x700c
44#define TX4938_PCI1_P2GM1PLBASE 0x7018
45#define TX4938_PCI1_P2GCFG 0x7090
46#define TX4938_PCI1_PBAREQPORT 0x7100
47#define TX4938_PCI1_PBACFG 0x7104
48#define TX4938_PCI1_G2PM0GBASE 0x7120
49#define TX4938_PCI1_G2PIOGBASE 0x7138
50#define TX4938_PCI1_G2PM0MASK 0x7140
51#define TX4938_PCI1_G2PIOMASK 0x714c
52#define TX4938_PCI1_G2PM0PBASE 0x7150
53#define TX4938_PCI1_G2PIOPBASE 0x7168
54#define TX4938_PCI1_PCICCFG 0x7170
55#define TX4938_PCI1_PCICSTATUS 0x7174
56#define TX4938_PCI1_P2GM1GBASE 0x7188
57#define TX4938_PCI1_G2PCFGADRS 0x71a0
58#define TX4938_PCI1_G2PCFGDATA 0x71a4
59
60/*
61 * Configuration Registers
62 */
63#define TX4938_CFG_CCFG 0xE000 /* Chip Configuration Register */
64#define TX4938_CFG_REVID 0xE008 /* Chip Revision ID Register */
65#define TX4938_CFG_PCFG 0xE010 /* Pin Configuration Register */
66#define TX4938_CFG_TOEA 0xE018 /* TimeOut Error Access Address Register */
67#define TX4938_CFG_CLKCTR 0xE020 /* Clock Control Register */
68#define TX4938_CFG_GARBC 0xE030 /* GBUS Arbiter Control Register */
69#define TX4938_CFG_RAMP 0xE048 /* Register Address Mapping Register */
70
71/* Pin Configuration register bits */
72#define SELCHI 0x00100000
73#define SELTMR0 0x00000200
74
75
76/*
77 * Timer Registers
78 */
79
80#define TX4938_TIMER0_BASE 0xF000
81#define TX4938_TIMER1_BASE 0xF100
82#define TX4938_TIMER2_BASE 0xF200
83
84#define TX4938_TIMER_TCR 0x00 /* Timer Control Register */
85#define TX4938_TIMER_TISR 0x04 /* Timer Interrupt Status Register */
86#define TX4938_TIMER_CPRA 0x08 /* Compare Register A */
87#define TX4938_TIMER_CPRB 0x0C /* Compare Register B */
88#define TX4938_TIMER_ITMR 0x10 /* Interval Timer Mode Register */
89#define TX4938_TIMER_CCDR 0x20 /* Divide Cycle Register */
90#define TX4938_TIMER_PGMR 0x30 /* Pulse Generator Mode Register */
91#define TX4938_TIMER_WTMR 0x40 /* Reserved Register */
92#define TX4938_TIMER_TRR 0xF0 /* Timer Read Register */
93
94/* ITMR register bits */
95#define TIMER_CLEAR_ENABLE_MASK 0x1
96#define TIMER_INT_ENABLE_MASK 0x8000
97
98/* PGMR register bits */
99#define FFI 0x1
100#define TPIAE 0x4000
101#define TPIBE 0x8000
102
103/* TISR register bits */
104#define TIIS 0x1
105#define TPIAS 0x2
106#define TPIBS 0x4
107#define TWIS 0x8
108
109
110/*
111 * Interrupt Controller Registers
112 */
113#define TX4938_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */
114#define TX4938_IRQCTL_DM0 0xF604 /* Interrupt Detection Mode Register 0 */
115#define TX4938_IRQCTL_DM1 0xF608 /* Interrupt Detection Mode Register 1 */
116#define TX4938_IRQCTL_LVL0 0xF610 /* Interrupt Level Register 0 */
117#define TX4938_IRQCTL_LVL1 0xF614 /* Interrupt Level Register 1 */
118#define TX4938_IRQCTL_LVL2 0xF618 /* Interrupt Level Register 2 */
119#define TX4938_IRQCTL_LVL3 0xF61C /* Interrupt Level Register 3 */
120#define TX4938_IRQCTL_LVL4 0xF620 /* Interrupt Level Register 4 */
121#define TX4938_IRQCTL_LVL5 0xF624 /* Interrupt Level Register 5 */
122#define TX4938_IRQCTL_LVL6 0xF628 /* Interrupt Level Register 6 */
123#define TX4938_IRQCTL_LVL7 0xF62C /* Interrupt Level Register 7 */
124#define TX4938_IRQCTL_MSK 0xF640 /* Interrupt Mask Register */
125#define TX4938_IRQCTL_EDC 0xF660 /* Interrupt Edge Detection Clear Register */
126#define TX4938_IRQCTL_PND 0xF680 /* Interrupt Pending Register */
127#define TX4938_IRQCTL_CS 0xF6A0 /* Interrupt Current Status Register */
128#define TX4938_IRQCTL_FLAG0 0xF510 /* Interrupt Request Flag Register 0 */
129#define TX4938_IRQCTL_FLAG1 0xF514 /* Interrupt Request Flag Register 1 */
130#define TX4938_IRQCTL_POL 0xF518 /* Interrupt Request Polarity Control Register */
131#define TX4938_IRQCTL_RCNT 0xF51C /* Interrupt Request Control Register */
132#define TX4938_IRQCTL_MASKINT 0xF520 /* Interrupt Request Internal Interrupt Mask Register */
133#define TX4938_IRQCTL_MASKEXT 0xF524 /* Interrupt Request External Interrupt Mask Register */
134
135#define TX4938_REG_READ( _base, _register ) \
136 *((volatile uint32_t *)((_base) + (_register)))
137
138#define TX4938_REG_WRITE( _base, _register, _value ) \
139 *((volatile uint32_t *)((_base) + (_register))) = (_value)
140
141/************************************************************************
142 * TX49 Register field encodings
143*************************************************************************/
144/******** reg: CCFG ********/
145/* field: PCIDIVMODE */
146#define TX4938_CCFG_SYSSP_SHF 6
147#define TX4938_CCFG_SYSSP_MSK (MSK(2) << TX4938_CCFG_SYSSP_SHF)
148
149/* field: PCI1DMD */
150#define TX4938_CCFG_PCI1DMD_SHF 8
151#define TX4938_CCFG_PCI1DMD_MSK (MSK(1) << TX4938_CCFG_PCI1DMD_SHF)
152
153/* field: PCIDIVMODE */
154#define TX4938_CCFG_PCIDIVMODE_SHF 10
155#define TX4938_CCFG_PCIDIVMODE_MSK (MSK(3) << TX4938_CCFG_PCIDIVMODE_SHF)
156
157/* field: PCI1-66 */
158#define TX4938_CCFG_PCI166_SHF 21
159#define TX4938_CCFG_PCI166_MSK ((UINT64)MSK(1) << TX4938_CCFG_PCI166_SHF)
160
161/* field: PCIMODE */
162#define TX4938_CCFG_PCIMODE_SHF 22
163#define TX4938_CCFG_PCIMODE_MSK ((UINT64)MSK(1) << TX4938_CCFG_PCIMODE_SHF)
164
165/* field: BRDTY */
166#define TX4938_CCFG_BRDTY_SHF 36
167#define TX4938_CCFG_RRDTY_MSK ((UINT64)MSK(4) << TX4938_CCFG_BRDTY_SHF)
168
169/* field: BRDRV */
170#define TX4938_CCFG_BRDRV_SHF 32
171#define TX4938_CCFG_BRDRV_MSK ((UINT64)MSK(4) << TX4938_CCFG_BRDRV_SHF)
172
173/******** reg: CLKCTR ********/
174/* field: PCIC1RST */
175#define TX4938_CLKCTR_PCIC1RST_SHF 11
176#define TX4938_CLKCTR_PCIC1RST_MSK (MSK(1) << TX4938_CLKCTR_PCIC1RST_SHF)
177
178/******** reg: PCISTATUS ********/
179/* field: MEMSP */
180#define TX4938_PCI_PCISTATUS_MEMSP_SHF 1
181#define TX4938_PCI_PCISTATUS_MEMSP_MSK (MSK(1) << TX4938_PCI_PCISTATUS_MEMSP_SHF)
182
183/* field: BM */
184#define TX4938_PCI_PCISTATUS_BM_SHF 2
185#define TX4938_PCI_PCISTATUS_BM_MSK (MSK(1) << TX4938_PCI_PCISTATUS_BM_SHF)
186
187/******** reg: PBACFG ********/
188/* field: RPBA */
189#define TX4938_PCI_PBACFG_RPBA_SHF 2
190#define TX4938_PCI_PBACFG_RPBA_MSK (MSK(1) << TX4938_PCI_PBACFG_RPBA_SHF)
191
192/* field: PBAEN */
193#define TX4938_PCI_PBACFG_PBAEN_SHF 1
194#define TX4938_PCI_PBACFG_PBAEN_MSK (MSK(1) << TX4938_PCI_PBACFG_PBAEN_SHF)
195
196/******** reg: PCICFG ********/
197/* field: G2PM0EN */
198#define TX4938_PCI_PCICFG_G2PM0EN_SHF 6
199#define TX4938_PCI_PCICFG_G2PM0EN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PM0EN_SHF)
200
201/* field: G2PIOEN */
202#define TX4938_PCI_PCICFG_G2PIOEN_SHF 5
203#define TX4938_PCI_PCICFG_G2PIOEN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PIOEN_SHF)
204
205/* field: TCAR */
206#define TX4938_PCI_PCICFG_TCAR_SHF 4
207#define TX4938_PCI_PCICFG_TCAR_MSK (MSK(1) << TX4938_PCI_PCICFG_TCAR_SHF)
208
209
210#endif
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