RTEMS 6.1-rc2
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stm32h7xx_ll_system.h
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1
33/* Define to prevent recursive inclusion -------------------------------------*/
34#ifndef __STM32H7xx_LL_SYSTEM_H
35#define __STM32H7xx_LL_SYSTEM_H
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
41/* Includes ------------------------------------------------------------------*/
42#include "stm32h7xx.h"
43
48#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
49
55/* Private types -------------------------------------------------------------*/
56/* Private variables ---------------------------------------------------------*/
57
58/* Private constants ---------------------------------------------------------*/
67#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U
68#define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U
69#define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U
70#define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U
71#define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U
72#define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U
73#define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U
74#define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U
83#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U
84#define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U
85#define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U
86#define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U
87#define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U
88#define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U
89#define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U
90#define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U
98/* Private macros ------------------------------------------------------------*/
99
100/* Exported types ------------------------------------------------------------*/
101/* Exported constants --------------------------------------------------------*/
111#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP
112#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP
113#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP
114#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP
115#if defined(I2C5)
116#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP
117#endif /*I2C5*/
118#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP
119#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP
120#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP
121#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP
130#if defined(SYSCFG_PMCR_BOOSTEN)
131#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN
132#endif /*SYSCFG_PMCR_BOOSTEN*/
133#define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO
134#define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO
135#define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO
136#define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO
141#if defined(SYSCFG_PMCR_EPIS_SEL)
146#define LL_SYSCFG_ETH_MII 0x00000000U
147#define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2
151#endif /* SYSCFG_PMCR_EPIS_SEL */
152
157#define LL_SYSCFG_EXTI_PORTA 0U
158#define LL_SYSCFG_EXTI_PORTB 1U
159#define LL_SYSCFG_EXTI_PORTC 2U
160#define LL_SYSCFG_EXTI_PORTD 3U
161#define LL_SYSCFG_EXTI_PORTE 4U
162#define LL_SYSCFG_EXTI_PORTF 5U
163#define LL_SYSCFG_EXTI_PORTG 6U
164#define LL_SYSCFG_EXTI_PORTH 7U
165#if defined(GPIOI)
166#define LL_SYSCFG_EXTI_PORTI 8U
167#endif /*GPIOI*/
168#define LL_SYSCFG_EXTI_PORTJ 9U
169#define LL_SYSCFG_EXTI_PORTK 10U
178#define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U)
179#define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U)
180#define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U)
181#define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U)
182#define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U)
183#define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U)
184#define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U)
185#define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U)
186#define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U)
187#define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U)
188#define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U)
189#define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U)
190#define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U)
191#define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U)
192#define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U)
193#define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U)
202#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML
205#define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML
208#define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML
211#define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L
214#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L
217#if defined(SYSCFG_CFGR_SRAM3L)
218#define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L
220#endif /*SYSCFG_CFGR_SRAM3L*/
221
222#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L
225#define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML
228#define LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L
231#define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL
234#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL
237#if defined(DUAL_CORE)
238#define LL_SYSCFG_TIMBREAK_CM4_LOCKUP SYSCFG_CFGR_CM4L
240#endif /* DUAL_CORE */
249#define LL_SYSCFG_CELL_CODE 0U
250#define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS
259#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U
260#define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M
265#if defined (DUAL_CORE)
270#define LL_SYSCFG_IWDG2_SW_CONTROL_MODE 0U
271#define LL_SYSCFG_IWDG2_HW_CONTROL_MODE SYSCFG_UR12_IWDG2M
275#endif /* DUAL_CORE */
276
281#define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U
282#define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U
283#define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U
284#define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U
288#ifdef SYSCFG_UR17_TCM_AXI_CFG
293#define LL_SYSCFG_ITCM_AXI_64KB_320KB 0U
294#define LL_SYSCFG_ITCM_AXI_128KB_256KB 1U
295#define LL_SYSCFG_ITCM_AXI_192KB_192KB 2U
296#define LL_SYSCFG_ITCM_AXI_256KB_128KB 3U
300#endif /* #ifdef SYSCFG_UR17_TCM_AXI_CFG */
301#if defined(SYSCFG_PKGR_PKG)
306#if (STM32H7_DEV_ID == 0x450UL)
307#define LL_SYSCFG_LQFP100_PACKAGE 0U
308#define LL_SYSCFG_TQFP144_PACKAGE 2U
309#define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U
310#define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U
311#elif (STM32H7_DEV_ID == 0x483UL)
312#define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE 0U
313#define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE 1U
314#define LL_SYSCFG_LQFP100_INDUS_PACKAGE 2U
315#define LL_SYSCFG_TFBGA100_INDUS_PACKAGE 3U
316#define LL_SYSCFG_WLCSP115_INDUS_PACKAGE 4U
317#define LL_SYSCFG_LQFP144_PACKAGE 5U
318#define LL_SYSCFG_UFBGA144_PACKAGE 6U
319#define LL_SYSCFG_LQFP144_INDUS_PACKAGE 7U
320#define LL_SYSCFG_UFBGA169_INDUS_PACKAGE 8U
321#define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U
322#define LL_SYSCFG_LQFP176_INDUS_PACKAGE 10U
323#endif /* STM32H7_DEV_ID == 0x450UL */
327#endif /* SYSCFG_PKGR_PKG */
328
333#define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U
334#define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0
335#define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1
336#define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH
337
346#define LL_DBGMCU_TRACE_NONE 0x00000000U
347#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
348#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
349#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
350#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)
359#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2
360#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3
361#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4
362#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5
363#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6
364#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7
365#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12
366#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13
367#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14
368#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1
369#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1
370#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2
371#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3
372#if defined(I2C5)
373#define LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1LFZ1_DBG_I2C5
374#endif /*I2C5*/
384#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)
385#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN
386#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
387#if defined(TIM23)
388#define LL_DBGMCU_APB1_GRP2_TIM23_STOP DBGMCU_APB1HFZ1_DBG_TIM23
389#endif /*TIM23*/
390#if defined(TIM24)
391#define LL_DBGMCU_APB1_GRP2_TIM24_STOP DBGMCU_APB1HFZ1_DBG_TIM24
392#endif /*TIM24*/
401#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1
402#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8
403#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15
404#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16
405#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17
406#if defined(HRTIM1)
407#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM
408#endif /*HRTIM1*/
417#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1
426#define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4
427#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2
428#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3
429#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4
430#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5
431#define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC
432#define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1
441#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
442#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
443#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
444#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
445#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
446#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
447#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
448#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
457/* Exported macro ------------------------------------------------------------*/
458
459/* Exported functions --------------------------------------------------------*/
470#if defined(SYSCFG_PMCR_EPIS_SEL)
479__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
480{
481 MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);
482}
483
491__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
492{
493 return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));
494}
495
496#endif /* SYSCFG_PMCR_EPIS_SEL */
510__STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
511{
512 SET_BIT(SYSCFG->PMCR, AnalogSwitch);
513}
514
528__STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
529{
530 CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);
531}
532#ifdef SYSCFG_PMCR_BOOSTEN
542__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
543{
544 SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
545}
546
555__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
556{
557 CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
558}
559#endif /*SYSCFG_PMCR_BOOSTEN*/
578__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
579{
580 SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);
581}
582
601__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
602{
603 CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);
604}
605
645__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
646{
647 MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));
648}
649
687__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
688{
689 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));
690}
691
723__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
724{
725#if defined(DUAL_CORE)
726 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
727 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
728 SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L, Break);
729#elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
730 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
731 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
732 SYSCFG_CFGR_PVDL, Break);
733#elif defined(SYSCFG_CFGR_AXISRAML)
734 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
735 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\
736 Break);
737#else
738 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML |\
739 SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
740 SYSCFG_CFGR_PVDL, Break);
741#endif /* DUAL_CORE */
742}
743
774__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
775{
776#if defined(DUAL_CORE)
777 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
778 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
779 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
780 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L));
781#elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
782 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
783 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
784 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
785 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
786#elif defined (SYSCFG_CFGR_AXISRAML)
787 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
788 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
789 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
790 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
791#else
792 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_CM7L | \
793 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
794#endif /* DUAL_CORE */
795}
796
804__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
805{
806 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
807}
808
816__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
817{
818 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
819}
820
826__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
827{
828 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);
829}
830
836__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
837{
838 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);
839}
840
849__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)
850{
851#if defined(SYSCFG_CCCSR_HSLV)
852 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
853#else
854 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
855#endif /* SYSCFG_CCCSR_HSLV */
856}
857
858#if defined(SYSCFG_CCCSR_HSLV1)
867__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void)
868{
869 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
870}
871
880__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void)
881{
882 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
883}
884
893__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void)
894{
895 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
896}
897#endif /*SYSCFG_CCCSR_HSLV1*/
898
899
908__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)
909{
910#if defined(SYSCFG_CCCSR_HSLV)
911 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
912#else
913 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
914#endif /* SYSCFG_CCCSR_HSLV */
915}
916
917#if defined(SYSCFG_CCCSR_HSLV1)
926__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void)
927{
928 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
929}
930
939__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void)
940{
941 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
942}
943
952__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void)
953{
954 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
955}
956#endif /*SYSCFG_CCCSR_HSLV1*/
957
963__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)
964{
965#if defined(SYSCFG_CCCSR_HSLV)
966 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);
967#else
968 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL);
969#endif /*SYSCFG_CCCSR_HSLV*/
970}
971
972#if defined(SYSCFG_CCCSR_HSLV1)
978__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)
979{
980 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL);
981}
982
988__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)
989{
990 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL);
991}
992
998__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)
999{
1000 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL);
1001}
1002#endif /*SYSCFG_CCCSR_HSLV1*/
1003
1013__STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
1014{
1015 SET_BIT(SYSCFG->CCCSR, CompCode);
1016}
1017
1025__STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
1026{
1027 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));
1028}
1029
1030#ifdef SYSCFG_CCCSR_CS_MMC
1031
1039__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void)
1040{
1041 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC));
1042}
1043#endif /*SYSCFG_CCCSR_CS_MMC*/
1044
1050__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
1051{
1052 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));
1053}
1054
1060__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
1061{
1062 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));
1063}
1064
1073__STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
1074{
1075 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);
1076}
1077
1083__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
1084{
1085 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));
1086}
1087
1088#ifdef SYSCFG_CCCR_PCC_MMC
1089
1098__STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)
1099{
1100 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode);
1101}
1102
1108__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void)
1109{
1110 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC));
1111}
1112#endif /* SYSCFG_CCCR_PCC_MMC */
1113
1122__STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
1123{
1124 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);
1125}
1126
1132__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
1133{
1134 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));
1135}
1136
1137#ifdef SYSCFG_CCCR_NCC_MMC
1138
1147__STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)
1148{
1149 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode);
1150}
1151
1157__STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)
1158{
1159 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC));
1160}
1161#endif /*SYSCFG_CCCR_NCC_MMC*/
1162
1163#ifdef SYSCFG_PKGR_PKG
1187__STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
1188{
1189 return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));
1190}
1191#endif /*SYSCFG_PKGR_PKG*/
1192
1193#ifdef SYSCFG_UR0_RDP
1202__STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)
1203{
1204 return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
1205}
1206#ifdef SYSCFG_UR0_BKS
1212__STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)
1213{
1214 return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
1215}
1216#endif /*SYSCFG_UR0_BKS*/
1217
1227__STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)
1228{
1229 return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));
1230}
1237__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)
1238{
1239 /* Configure CM7 BOOT ADD0 */
1240#if defined(DUAL_CORE)
1241 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos));
1242#else
1243 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));
1244#endif /*DUAL_CORE*/
1245
1246}
1247
1253__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)
1254{
1255 /* Get CM7 BOOT ADD0 */
1256#if defined(DUAL_CORE)
1257 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos);
1258#else
1259 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);
1260#endif /*DUAL_CORE*/
1261}
1262
1269__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)
1270{
1271 /* Configure CM7 BOOT ADD1 */
1272#if defined(DUAL_CORE)
1273 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress);
1274#else
1275 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);
1276#endif /*DUAL_CORE*/
1277}
1278
1284__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)
1285{
1286 /* Get CM7 BOOT ADD0 */
1287#if defined(DUAL_CORE)
1288 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1));
1289#else
1290 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));
1291#endif /* DUAL_CORE */
1292}
1293
1294#if defined(DUAL_CORE)
1301__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)
1302{
1303 /* Configure CM4 BOOT ADD0 */
1304 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos));
1305}
1306
1312__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void)
1313{
1314 /* Get CM4 BOOT ADD0 */
1315 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos);
1316}
1317
1324__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)
1325{
1326 /* Configure CM4 BOOT ADD1 */
1327 MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress);
1328}
1329
1335__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void)
1336{
1337 /* Get CM4 BOOT ADD0 */
1338 return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1));
1339}
1340#endif /*DUAL_CORE*/
1341
1347__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)
1348{
1349 return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);
1350}
1351
1357__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)
1358{
1359 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);
1360}
1361
1367__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)
1368{
1369 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
1370}
1371
1377__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)
1378{
1379 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
1380}
1381
1387__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)
1388{
1389 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
1390}
1391
1397__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)
1398{
1399 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
1400}
1401
1407__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)
1408{
1409 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
1410}
1411
1417__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)
1418{
1419 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
1420}
1421
1427__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)
1428{
1429 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
1430}
1431
1437__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)
1438{
1439 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
1440}
1441
1447__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)
1448{
1449 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));
1450}
1451
1457__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)
1458{
1459 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));
1460}
1461
1467__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)
1468{
1469 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));
1470}
1471
1477__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)
1478{
1479 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
1480}
1481
1482#ifdef SYSCFG_UR8_MEPAD_BANK2
1488__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)
1489{
1490 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);
1491}
1492
1498__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)
1499{
1500 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
1501}
1502#endif /*SYSCFG_UR8_MEPAD_BANK2*/
1503
1504#ifdef SYSCFG_UR9_WRPN_BANK2
1510__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)
1511{
1512 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
1513}
1514
1520__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)
1521{
1522 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
1523}
1524
1530__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)
1531{
1532 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
1533}
1534
1540__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)
1541{
1542 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
1543}
1544
1550__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)
1551{
1552 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
1553}
1554
1560__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)
1561{
1562 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
1563}
1564
1570__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)
1571{
1572 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
1573}
1574
1580__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)
1581{
1582 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
1583}
1584
1590__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)
1591{
1592 return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
1593}
1594#endif /*SYSCFG_UR9_WRPN_BANK2*/
1595
1596#ifdef SYSCFG_UR10_PAEND_BANK2
1602__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)
1603{
1604 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));
1605}
1606
1612__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)
1613{
1614 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
1615}
1616#endif /*SYSCFG_UR10_PAEND_BANK2*/
1617
1618#ifdef SYSCFG_UR11_SAEND_BANK2
1624__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)
1625{
1626 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
1627}
1628#endif /*SYSCFG_UR11_SAEND_BANK2*/
1629
1637__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)
1638{
1639 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));
1640}
1641
1642#if defined (DUAL_CORE)
1650__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void)
1651{
1652 return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M));
1653}
1654#endif /* DUAL_CORE */
1655
1661__STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)
1662{
1663 return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);
1664}
1665
1671__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)
1672{
1673 return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);
1674}
1675
1685__STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)
1686{
1687 return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));
1688}
1689
1695__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)
1696{
1697 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);
1698}
1699
1700#if defined (DUAL_CORE)
1706__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void)
1707{
1708 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL);
1709}
1710
1716__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void)
1717{
1718 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL);
1719}
1720#endif /* DUAL_CORE */
1721
1727__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)
1728{
1729 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);
1730}
1731
1737__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)
1738{
1739 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);
1740}
1741
1747__STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)
1748{
1749 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);
1750}
1751
1760__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)
1761{
1762 return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
1763}
1764
1765#ifdef SYSCFG_UR17_TCM_AXI_CFG
1775__STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void)
1776{
1777 return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG));
1778}
1779#endif /*SYSCFG_UR17_TCM_AXI_CFG*/
1780
1781#ifdef SYSCFG_UR18_CPU_FREQ_BOOST
1787__STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void)
1788{
1789 return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL);
1790}
1791#endif /*SYSCFG_UR18_CPU_FREQ_BOOST*/
1792
1793#endif /*SYSCFG_UR0_RDP*/
1794
1809__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1810{
1811 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1812}
1813
1821__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1822{
1823 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1824}
1825
1831__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)
1832{
1833 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
1834}
1835
1841__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)
1842{
1843 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
1844}
1845
1851__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)
1852{
1853 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
1854}
1855
1861__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)
1862{
1863 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
1864}
1865
1871__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)
1872{
1873 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
1874}
1875
1881__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)
1882{
1883 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
1884}
1885
1886#if defined (DUAL_CORE)
1892__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void)
1893{
1894 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
1895}
1896
1902__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void)
1903{
1904 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
1905}
1906
1912__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void)
1913{
1914 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
1915}
1916
1922__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void)
1923{
1924 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
1925}
1926
1932__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void)
1933{
1934 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1935}
1936
1942__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void)
1943{
1944 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1945}
1946#endif /* DUAL_CORE */
1947
1948
1949#if defined(DBGMCU_CR_DBG_STOPD3)
1955__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)
1956{
1957 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1958}
1959
1965__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)
1966{
1967 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1968}
1969#endif /*DBGMCU_CR_DBG_STOPD3*/
1970
1971#if defined(DBGMCU_CR_DBG_STANDBYD3)
1977__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)
1978{
1979 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1980}
1981
1987__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)
1988{
1989 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1990}
1991#endif /*DBGMCU_CR_DBG_STANDBYD3*/
1992
1998__STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)
1999{
2000 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
2001}
2002
2008__STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)
2009{
2010 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
2011}
2012
2018__STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)
2019{
2020 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
2021}
2022
2028__STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)
2029{
2030 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
2031}
2032
2038__STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)
2039{
2040 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
2041}
2042
2048__STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)
2049{
2050 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
2051}
2052
2053#define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U
2054#define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN
2063__STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
2064{
2065 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
2066}
2067
2075__STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
2076{
2077 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
2078}
2079
2115__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
2116{
2117 SET_BIT(DBGMCU->APB1LFZ1, Periphs);
2118}
2119
2155__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
2156{
2157 CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
2158}
2159
2160#ifdef DBGMCU_APB1HFZ1_DBG_FDCAN
2168__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
2169{
2170 SET_BIT(DBGMCU->APB1HFZ1, Periphs);
2171}
2172
2180__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
2181{
2182 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
2183}
2184#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
2185
2186#if defined(TIM23) || defined(TIM24)
2196__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
2197{
2198 SET_BIT(DBGMCU->APB1HFZ1, Periphs);
2199}
2200
2210__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
2211{
2212 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
2213}
2214#endif /* TIM23 || TIM24 */
2215
2235__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
2236{
2237 SET_BIT(DBGMCU->APB2FZ1, Periphs);
2238}
2239
2259__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
2260{
2261 CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);
2262}
2263
2271__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
2272{
2273 SET_BIT(DBGMCU->APB3FZ1, Periphs);
2274}
2275
2283__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
2284{
2285 CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);
2286}
2287
2309__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
2310{
2311 SET_BIT(DBGMCU->APB4FZ1, Periphs);
2312}
2313
2335__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
2336{
2337 CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);
2338}
2362__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
2363{
2364 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
2365}
2366
2380__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
2381{
2382 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
2383}
2384
2389#if defined(DUAL_CORE)
2400__STATIC_INLINE void LL_ART_Enable(void)
2401{
2402 SET_BIT(ART->CTR, ART_CTR_EN);
2403}
2404
2410__STATIC_INLINE void LL_ART_Disable(void)
2411{
2412 CLEAR_BIT(ART->CTR, ART_CTR_EN);
2413}
2414
2420__STATIC_INLINE uint32_t LL_ART_IsEnabled(void)
2421{
2422 return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);
2423}
2424
2432__STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)
2433{
2434 MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));
2435}
2436
2443__STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
2444{
2445 return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);
2446}
2447#endif /* DUAL_CORE */
2448
2461#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
2462
2467#ifdef __cplusplus
2468}
2469#endif
2470
2471#endif /* __STM32H7xx_LL_SYSTEM_H */
2472
SYSCFG_UR15_D2STPRST
#define SYSCFG_UR15_D2STPRST
Definition: stm32h745xg.h:19917
SYSCFG_CCCSR_READY
#define SYSCFG_CCCSR_READY
Definition: stm32h723xx.h:18935
SYSCFG_CCCSR_HSLV3
#define SYSCFG_CCCSR_HSLV3
Definition: stm32h7a3xx.h:17375
SYSCFG_CFGR_SRAM4L
#define SYSCFG_CFGR_SRAM4L
Definition: stm32h723xx.h:18909
SYSCFG_UR5_WRPN_BANK1
#define SYSCFG_UR5_WRPN_BANK1
Definition: stm32h723xx.h:18999
SYSCFG_CCCSR_HSLV
#define SYSCFG_CCCSR_HSLV
Definition: stm32h723xx.h:18938
SYSCFG_CCVR_PCV
#define SYSCFG_CCVR_PCV
Definition: stm32h723xx.h:18946
SYSCFG_PMCR_BOOSTEN
#define SYSCFG_PMCR_BOOSTEN
Definition: stm32h723xx.h:18594
SYSCFG_CFGR_BKRAML
#define SYSCFG_CFGR_BKRAML
Definition: stm32h723xx.h:18906
SYSCFG_UR12_SECURE
#define SYSCFG_UR12_SECURE
Definition: stm32h723xx.h:19027
SYSCFG_CFGR_CM4L
#define SYSCFG_CFGR_CM4L
Definition: stm32h745xg.h:19716
SYSCFG_UR5_MESAD_BANK1
#define SYSCFG_UR5_MESAD_BANK1
Definition: stm32h723xx.h:18996
SYSCFG_CCCSR_EN
#define SYSCFG_CCCSR_EN
Definition: stm32h723xx.h:18929
SYSCFG_UR8_MESAD_BANK2
#define SYSCFG_UR8_MESAD_BANK2
Definition: stm32h742xx.h:18562
SYSCFG_UR12_IWDG2M
#define SYSCFG_UR12_IWDG2M
Definition: stm32h745xg.h:19892
SYSCFG_UR10_PAEND_BANK2
#define SYSCFG_UR10_PAEND_BANK2
Definition: stm32h742xx.h:18575
SYSCFG_CFGR_DTCML
#define SYSCFG_CFGR_DTCML
Definition: stm32h723xx.h:18918
SYSCFG_UR2_BCM7_ADD0
#define SYSCFG_UR2_BCM7_ADD0
Definition: stm32h745xg.h:19813
SYSCFG_UR14_D2SBRST
#define SYSCFG_UR14_D2SBRST
Definition: stm32h745xg.h:19912
SYSCFG_CCCSR_HSLV0
#define SYSCFG_CCCSR_HSLV0
Definition: stm32h7a3xx.h:17366
SYSCFG_UR6_PAEND_BANK1
#define SYSCFG_UR6_PAEND_BANK1
Definition: stm32h723xx.h:19007
SYSCFG_UR13_SDRS
#define SYSCFG_UR13_SDRS
Definition: stm32h723xx.h:19032
SYSCFG_CFGR_AXISRAML
#define SYSCFG_CFGR_AXISRAML
Definition: stm32h723xx.h:18924
SYSCFG_CCCSR_CS
#define SYSCFG_CCCSR_CS
Definition: stm32h723xx.h:18932
SYSCFG_CFGR_CM7L
#define SYSCFG_CFGR_CM7L
Definition: stm32h723xx.h:18903
SYSCFG_UR8_MEPAD_BANK2
#define SYSCFG_UR8_MEPAD_BANK2
Definition: stm32h742xx.h:18559
SYSCFG_UR2_BOOT_ADD0
#define SYSCFG_UR2_BOOT_ADD0
Definition: stm32h723xx.h:18981
SYSCFG_UR11_SAEND_BANK2
#define SYSCFG_UR11_SAEND_BANK2
Definition: stm32h742xx.h:18583
SYSCFG_UR14_D1STPRST
#define SYSCFG_UR14_D1STPRST
Definition: stm32h723xx.h:19040
SYSCFG_UR9_WRPN_BANK2
#define SYSCFG_UR9_WRPN_BANK2
Definition: stm32h742xx.h:18567
SYSCFG_UR0_BKS
#define SYSCFG_UR0_BKS
Definition: stm32h742xx.h:18507
SYSCFG_CCCSR_CS_MMC
#define SYSCFG_CCCSR_CS_MMC
Definition: stm32h7a3xx.h:17360
SYSCFG_PMCR_EPIS_SEL
#define SYSCFG_PMCR_EPIS_SEL
Definition: stm32h723xx.h:18606
SYSCFG_UR17_IOHSLV
#define SYSCFG_UR17_IOHSLV
Definition: stm32h723xx.h:19058
SYSCFG_CFGR_ITCML
#define SYSCFG_CFGR_ITCML
Definition: stm32h723xx.h:18921
SYSCFG_CCCR_PCC_MMC
#define SYSCFG_CCCR_PCC_MMC
Definition: stm32h7a3xx.h:17396
SYSCFG_CCCR_NCC
#define SYSCFG_CCCR_NCC
Definition: stm32h723xx.h:18951
SYSCFG_UR3_BCM4_ADD0
#define SYSCFG_UR3_BCM4_ADD0
Definition: stm32h745xg.h:19821
SYSCFG_UR9_PABEG_BANK2
#define SYSCFG_UR9_PABEG_BANK2
Definition: stm32h742xx.h:18570
SYSCFG_UR4_BCM4_ADD1
#define SYSCFG_UR4_BCM4_ADD1
Definition: stm32h745xg.h:19827
SYSCFG_UR6_PABEG_BANK1
#define SYSCFG_UR6_PABEG_BANK1
Definition: stm32h723xx.h:19004
SYSCFG_CCCR_NCC_MMC
#define SYSCFG_CCCR_NCC_MMC
Definition: stm32h7a3xx.h:17393
SYSCFG_UR18_CPU_FREQ_BOOST
#define SYSCFG_UR18_CPU_FREQ_BOOST
Definition: stm32h723xx.h:19066
ART_CTR_EN
#define ART_CTR_EN
Definition: stm32h745xg.h:4108
SYSCFG_CFGR_SRAM2L
#define SYSCFG_CFGR_SRAM2L
Definition: stm32h723xx.h:18912
SYSCFG_CFGR_FLASHL
#define SYSCFG_CFGR_FLASHL
Definition: stm32h723xx.h:18900
SYSCFG_UR0_RDP
#define SYSCFG_UR0_RDP
Definition: stm32h723xx.h:18971
SYSCFG_CFGR_SRAM1L
#define SYSCFG_CFGR_SRAM1L
Definition: stm32h723xx.h:18915
SYSCFG_UR3_BCM7_ADD1
#define SYSCFG_UR3_BCM7_ADD1
Definition: stm32h745xg.h:19817
SYSCFG_CCCR_PCC
#define SYSCFG_CCCR_PCC
Definition: stm32h723xx.h:18954
SYSCFG_UR11_IWDG1M
#define SYSCFG_UR11_IWDG1M
Definition: stm32h723xx.h:19021
SYSCFG_UR17_TCM_AXI_CFG
#define SYSCFG_UR17_TCM_AXI_CFG
Definition: stm32h723xx.h:19061
SYSCFG_UR2_BORH
#define SYSCFG_UR2_BORH
Definition: stm32h723xx.h:18976
SYSCFG_UR7_SAEND_BANK1
#define SYSCFG_UR7_SAEND_BANK1
Definition: stm32h723xx.h:19015
ART_CTR_PCACHEADDR
#define ART_CTR_PCACHEADDR
Definition: stm32h745xg.h:4112
SYSCFG_CFGR_PVDL
#define SYSCFG_CFGR_PVDL
Definition: stm32h723xx.h:18897
SYSCFG_UR3_BOOT_ADD1
#define SYSCFG_UR3_BOOT_ADD1
Definition: stm32h723xx.h:18985
SYSCFG_CCVR_NCV
#define SYSCFG_CCVR_NCV
Definition: stm32h723xx.h:18943
SYSCFG_UR16_FZIWDGSTP
#define SYSCFG_UR16_FZIWDGSTP
Definition: stm32h723xx.h:19050
SYSCFG_UR4_MEPAD_BANK1
#define SYSCFG_UR4_MEPAD_BANK1
Definition: stm32h723xx.h:18991
SYSCFG_UR7_SABEG_BANK1
#define SYSCFG_UR7_SABEG_BANK1
Definition: stm32h723xx.h:19012
SYSCFG_UR10_SABEG_BANK2
#define SYSCFG_UR10_SABEG_BANK2
Definition: stm32h742xx.h:18578
SYSCFG_PKGR_PKG
#define SYSCFG_PKGR_PKG
Definition: stm32h723xx.h:18966
SYSCFG_UR13_D1SBRST
#define SYSCFG_UR13_D1SBRST
Definition: stm32h723xx.h:19035
SYSCFG_CFGR_SRAM3L
#define SYSCFG_CFGR_SRAM3L
Definition: stm32h742xx.h:18448
FLASH_ACR_LATENCY
#define FLASH_ACR_LATENCY
Definition: stm32h723xx.h:10818
SYSCFG_CCCSR_HSLV1
#define SYSCFG_CCCSR_HSLV1
Definition: stm32h7a3xx.h:17369
SYSCFG_UR16_PKP
#define SYSCFG_UR16_PKP
Definition: stm32h723xx.h:19053
SYSCFG_CCCSR_HSLV2
#define SYSCFG_CCCSR_HSLV2
Definition: stm32h7a3xx.h:17372
SYSCFG_UR15_FZIWDGSTB
#define SYSCFG_UR15_FZIWDGSTB
Definition: stm32h723xx.h:19045
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
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