RTEMS 6.1-rc2
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stm32h7xx_ll_spi.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_SPI_H
21#define STM32H7xx_LL_SPI_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
34#if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
35
41/* Private variables ---------------------------------------------------------*/
42
43/* Private constants ---------------------------------------------------------*/
44
45/* Private macros ------------------------------------------------------------*/
54/* Exported types ------------------------------------------------------------*/
55#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
64typedef struct
65{
66 uint32_t TransferDirection;
72 uint32_t Mode;
78 uint32_t DataWidth;
84 uint32_t ClockPolarity;
90 uint32_t ClockPhase;
96 uint32_t NSS;
104 uint32_t BaudRate;
113 uint32_t BitOrder;
119 uint32_t CRCCalculation;
125 uint32_t CRCPoly;
132} LL_SPI_InitTypeDef;
133
137#endif /*USE_FULL_LL_DRIVER*/
138
139/* Exported types ------------------------------------------------------------*/
140
141/* Exported constants --------------------------------------------------------*/
152#define LL_SPI_SR_RXP (SPI_SR_RXP)
153#define LL_SPI_SR_TXP (SPI_SR_TXP)
154#define LL_SPI_SR_DXP (SPI_SR_DXP)
155#define LL_SPI_SR_EOT (SPI_SR_EOT)
156#define LL_SPI_SR_TXTF (SPI_SR_TXTF)
157#define LL_SPI_SR_UDR (SPI_SR_UDR)
158#define LL_SPI_SR_CRCE (SPI_SR_CRCE)
159#define LL_SPI_SR_MODF (SPI_SR_MODF)
160#define LL_SPI_SR_OVR (SPI_SR_OVR)
161#define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
162#define LL_SPI_SR_TSERF (SPI_SR_TSERF)
163#define LL_SPI_SR_SUSP (SPI_SR_SUSP)
164#define LL_SPI_SR_TXC (SPI_SR_TXC)
165#define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
175#define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
176#define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
177#define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
178#define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
179#define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
180#define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
181#define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
182#define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
183#define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
184#define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
185#define LL_SPI_IER_TSERFIE (SPI_IER_TSERFIE)
194#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
195#define LL_SPI_MODE_SLAVE (0x00000000UL)
204#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
205#define LL_SPI_SS_LEVEL_LOW (0x00000000UL)
214#define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
215#define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
216#define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
217#define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
218#define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
219#define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
220#define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
221#define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
222#define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
223#define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
224#define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
225#define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
226#define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
227#define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
228#define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
229#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\
230 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
239#define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
240#define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
241#define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
242#define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
243#define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
244#define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
245#define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
246#define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
247#define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
248#define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
249#define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
250#define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
251#define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
252#define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
253#define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
254#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\
255 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
264#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
265#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
274#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
275#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
284#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
285#define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG_0)
286#define LL_SPI_UDR_CONFIG_LAST_TRANSMITTED (SPI_CFG1_UDRCFG_1)
295#define LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
296#define LL_SPI_UDR_DETECT_END_DATA_FRAME (SPI_CFG1_UDRDET_0)
297#define LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS (SPI_CFG1_UDRDET_1)
306#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
307#define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
316#define LL_SPI_PHASE_1EDGE (0x00000000UL)
317#define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
326#define LL_SPI_POLARITY_LOW (0x00000000UL)
327#define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
336#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
337#define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
346#define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
347#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
348#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
349#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
350#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
351#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
352#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
353#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
362#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
363#define LL_SPI_MSB_FIRST (0x00000000UL)
372#define LL_SPI_FULL_DUPLEX (0x00000000UL)
373#define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
374#define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
375#define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
376#define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
385#define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
386#define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
387#define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
388#define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
389#define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
390#define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
391#define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
392#define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
393#define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
394#define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
395#define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
396#define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
397#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\
398 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
399#define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
400#define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
401#define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
402#define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
403#define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
404#define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
405#define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
406#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\
407 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
408#define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
409#define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
410#define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
411#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\
412 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
413#define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
414#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\
415 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
416#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\
417 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
418#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
419 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
428#define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
429#define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
430#define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
431#define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
432#define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
433#define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
434#define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
435#define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
436#define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
437#define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
438#define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
439#define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
440#define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
441#define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
442#define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
443#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\
444 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
449#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
450
455#define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL)
456#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN)
460#endif /* USE_FULL_LL_DRIVER */
461
466#define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
467#define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
468#define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
469#define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
470#define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
471#define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
472#define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
473#define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
474#define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
475#define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
476#define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
477#define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
478#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\
479 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
480#define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
481#define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
482#define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
483#define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
484#define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
485#define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
486#define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
487#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\
488 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
489#define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
490#define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
491#define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
492#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\
493 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
494#define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
495#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\
496 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
497#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\
498 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
499#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
500 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
509#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
510#define LL_SPI_NSS_HARD_INPUT (0x00000000UL)
511#define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
520#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
521#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
522#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
523#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
532/* Exported macro ------------------------------------------------------------*/
550#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
551
558#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
568/* Exported functions --------------------------------------------------------*/
569
586__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
587{
588 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
589}
590
598__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
599{
600 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
601}
602
609__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
610{
611 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
612}
613
621__STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
622{
623 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
624}
625
633__STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
634{
635 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
636}
637
644__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx)
645{
646 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
647}
648
656__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
657{
658 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
659}
660
668__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
669{
670 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
671}
672
679__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
680{
681 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
682}
683
694__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
695{
696 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
697}
698
707__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
708{
709 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
710}
711
735__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
736{
737 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
738}
739
762__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx)
763{
764 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
765}
766
790__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
791{
792 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
793}
794
817__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx)
818{
819 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
820}
821
830__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
831{
832 MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
833}
834
842__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx)
843{
844 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
845}
846
855__STATIC_INLINE void LL_SPI_SetReloadSize(SPI_TypeDef *SPIx, uint32_t Count)
856{
857 MODIFY_REG(SPIx->CR2, SPI_CR2_TSER, Count << SPI_CR2_TSER_Pos);
858}
859
867__STATIC_INLINE uint32_t LL_SPI_GetReloadSize(SPI_TypeDef *SPIx)
868{
869 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSER) >> SPI_CR2_TSER_Pos);
870}
871
880__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
881{
882 SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
883}
884
891__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
892{
893 return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
894}
895
905__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
906{
907 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
908}
909
918__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx)
919{
920 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
921}
922
932__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
933{
934 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
935}
936
945__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx)
946{
947 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
948}
949
960__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
961{
962 MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
963}
964
973__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx)
974{
975 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
976}
977
984__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
985{
986 SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
987}
988
995__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
996{
997 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
998}
999
1006__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx)
1007{
1008 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
1009}
1010
1017__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
1018{
1019 SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
1020}
1021
1028__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
1029{
1030 SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
1031}
1032
1039__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx)
1040{
1041 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
1042}
1043
1050__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1051{
1052 SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
1053}
1054
1061__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1062{
1063 CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
1064}
1065
1072__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1073{
1074 return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
1075}
1076
1088__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
1089{
1090 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
1091}
1092
1102__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx)
1103{
1104 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
1105}
1106
1118__STATIC_INLINE void LL_SPI_SetUDRDetection(SPI_TypeDef *SPIx, uint32_t UDRDetection)
1119{
1120 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRDET, UDRDetection);
1121}
1122
1132__STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(SPI_TypeDef *SPIx)
1133{
1134 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET));
1135}
1136
1147__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1148{
1149 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
1150}
1151
1160__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
1161{
1162 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
1163}
1164
1176__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
1177{
1178 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
1179}
1180
1189__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
1190{
1191 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
1192}
1193
1205__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1206{
1207 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
1208}
1209
1218__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
1219{
1220 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
1221}
1222
1234__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
1235{
1236 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
1237}
1238
1247__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx)
1248{
1249 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
1250}
1251
1269__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
1270{
1271 MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR, Baudrate);
1272}
1273
1288__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
1289{
1290 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR));
1291}
1292
1304__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
1305{
1306 MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
1307}
1308
1317__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
1318{
1319 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
1320}
1321
1337__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
1338{
1339 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR);
1340 MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
1341}
1342
1355__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
1356{
1357 uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
1358 uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
1359 return (Hddir | Comm);
1360}
1361
1372__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
1373{
1374 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
1375}
1376
1386__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)
1387{
1388 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
1389}
1390
1428__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
1429{
1430 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
1431}
1432
1468__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
1469{
1470 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
1471}
1472
1497__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
1498{
1499 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
1500}
1501
1524__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx)
1525{
1526 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
1527}
1528
1536__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
1537{
1538 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1539}
1540
1547__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
1548{
1549 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1550}
1551
1558__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
1559{
1560 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
1561}
1562
1600__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
1601{
1602 MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
1603}
1604
1640__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
1641{
1642 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
1643}
1644
1658__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
1659{
1660 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
1661}
1662
1673__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
1674{
1675 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
1676}
1677
1686__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
1687{
1688 SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1689}
1690
1699__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
1700{
1701 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1702}
1703
1710__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
1711{
1712 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
1713}
1714
1730__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
1731{
1732 return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
1733}
1734
1741__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
1742{
1743 return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
1744}
1745
1752__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
1753{
1754 return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
1755}
1756
1763__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
1764{
1765 return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
1766}
1767
1774__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
1775{
1776 return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
1777}
1778
1785__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1786{
1787 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1788}
1789
1796__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
1797{
1798 return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
1799}
1800
1807__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
1808{
1809 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
1810}
1811
1818__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1819{
1820 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
1821}
1822
1829__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
1830{
1831 return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
1832}
1833
1840__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(SPI_TypeDef *SPIx)
1841{
1842 return ((READ_BIT(SPIx->SR, SPI_SR_TSERF) == (SPI_SR_TSERF)) ? 1UL : 0UL);
1843}
1844
1851__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
1852{
1853 return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
1854}
1855
1862__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
1863{
1864 return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
1865}
1866
1873__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
1874{
1875 return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
1876}
1877
1884__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
1885{
1886 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
1887}
1888
1899__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx)
1900{
1901 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
1902}
1903
1910__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
1911{
1912 SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
1913}
1914
1921__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
1922{
1923 SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
1924}
1925
1932__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
1933{
1934 SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
1935}
1936
1943__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
1944{
1945 SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
1946}
1947
1954__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
1955{
1956 SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
1957}
1958
1965__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
1966{
1967 SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
1968}
1969
1976__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
1977{
1978 SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
1979}
1980
1987__STATIC_INLINE void LL_SPI_ClearFlag_TSER(SPI_TypeDef *SPIx)
1988{
1989 SET_BIT(SPIx->IFCR, SPI_IFCR_TSERFC);
1990}
1991
1998__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
1999{
2000 SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
2001}
2002
2018__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
2019{
2020 SET_BIT(SPIx->IER, SPI_IER_RXPIE);
2021}
2022
2029__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
2030{
2031 SET_BIT(SPIx->IER, SPI_IER_TXPIE);
2032}
2033
2040__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
2041{
2042 SET_BIT(SPIx->IER, SPI_IER_DXPIE);
2043}
2044
2051__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
2052{
2053 SET_BIT(SPIx->IER, SPI_IER_EOTIE);
2054}
2055
2062__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
2063{
2064 SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
2065}
2066
2073__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
2074{
2075 SET_BIT(SPIx->IER, SPI_IER_UDRIE);
2076}
2077
2084__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
2085{
2086 SET_BIT(SPIx->IER, SPI_IER_OVRIE);
2087}
2088
2095__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
2096{
2097 SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
2098}
2099
2106__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
2107{
2108 SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
2109}
2110
2117__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
2118{
2119 SET_BIT(SPIx->IER, SPI_IER_MODFIE);
2120}
2121
2128__STATIC_INLINE void LL_SPI_EnableIT_TSER(SPI_TypeDef *SPIx)
2129{
2130 SET_BIT(SPIx->IER, SPI_IER_TSERFIE);
2131}
2132
2139__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
2140{
2141 CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
2142}
2143
2150__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
2151{
2152 CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
2153}
2154
2161__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
2162{
2163 CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
2164}
2165
2172__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
2173{
2174 CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
2175}
2176
2183__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
2184{
2185 CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
2186}
2187
2194__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
2195{
2196 CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
2197}
2198
2205__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
2206{
2207 CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
2208}
2209
2216__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
2217{
2218 CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
2219}
2220
2227__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
2228{
2229 CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
2230}
2231
2238__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
2239{
2240 CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
2241}
2242
2249__STATIC_INLINE void LL_SPI_DisableIT_TSER(SPI_TypeDef *SPIx)
2250{
2251 CLEAR_BIT(SPIx->IER, SPI_IER_TSERFIE);
2252}
2253
2260__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
2261{
2262 return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
2263}
2264
2271__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
2272{
2273 return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
2274}
2275
2282__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
2283{
2284 return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
2285}
2286
2293__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
2294{
2295 return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
2296}
2297
2304__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
2305{
2306 return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
2307}
2308
2315__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
2316{
2317 return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
2318}
2319
2326__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
2327{
2328 return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
2329}
2330
2337__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
2338{
2339 return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
2340}
2341
2348__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
2349{
2350 return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
2351}
2352
2359__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
2360{
2361 return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
2362}
2363
2370__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(SPI_TypeDef *SPIx)
2371{
2372 return ((READ_BIT(SPIx->IER, SPI_IER_TSERFIE) == (SPI_IER_TSERFIE)) ? 1UL : 0UL);
2373}
2374
2390__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
2391{
2392 SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2393}
2394
2401__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
2402{
2403 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2404}
2405
2412__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
2413{
2414 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
2415}
2416
2423__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
2424{
2425 SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2426}
2427
2434__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
2435{
2436 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2437}
2438
2445__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
2446{
2447 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
2448}
2455__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(SPI_TypeDef *SPIx)
2456{
2457 return (uint32_t) &(SPIx->TXDR);
2458}
2459
2466__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(SPI_TypeDef *SPIx)
2467{
2468 return (uint32_t) &(SPIx->RXDR);
2469}
2485__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
2486{
2487 return (*((__IO uint8_t *)&SPIx->RXDR));
2488}
2489
2496__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
2497{
2498#if defined (__GNUC__)
2499 __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
2500 return (*spirxdr);
2501#else
2502 return (*((__IO uint16_t *)&SPIx->RXDR));
2503#endif /* __GNUC__ */
2504}
2505
2512__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx)
2513{
2514 return (*((__IO uint32_t *)&SPIx->RXDR));
2515}
2516
2524__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
2525{
2526 *((__IO uint8_t *)&SPIx->TXDR) = TxData;
2527}
2528
2536__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
2537{
2538#if defined (__GNUC__)
2539 __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
2540 *spitxdr = TxData;
2541#else
2542 *((__IO uint16_t *)&SPIx->TXDR) = TxData;
2543#endif /* __GNUC__ */
2544}
2545
2553__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
2554{
2555 *((__IO uint32_t *)&SPIx->TXDR) = TxData;
2556}
2557
2565__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
2566{
2567 WRITE_REG(SPIx->CRCPOLY, CRCPoly);
2568}
2569
2576__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
2577{
2578 return (uint32_t)(READ_REG(SPIx->CRCPOLY));
2579}
2580
2588__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
2589{
2590 WRITE_REG(SPIx->UDRDR, Pattern);
2591}
2592
2599__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
2600{
2601 return (uint32_t)(READ_REG(SPIx->UDRDR));
2602}
2603
2610__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
2611{
2612 return (uint32_t)(READ_REG(SPIx->RXCRC));
2613}
2614
2621__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
2622{
2623 return (uint32_t)(READ_REG(SPIx->TXCRC));
2624}
2625
2630#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
2636ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
2637ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
2638void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
2639
2643#endif /* USE_FULL_LL_DRIVER */
2656/* Private variables ---------------------------------------------------------*/
2657/* Private constants ---------------------------------------------------------*/
2658/* Private macros ------------------------------------------------------------*/
2659
2660/* Exported types ------------------------------------------------------------*/
2661#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
2671typedef struct
2672{
2673 uint32_t Mode;
2679 uint32_t Standard;
2686 uint32_t DataFormat;
2693 uint32_t MCLKOutput;
2700 uint32_t AudioFreq;
2709 uint32_t ClockPolarity;
2715} LL_I2S_InitTypeDef;
2716
2720#endif /*USE_FULL_LL_DRIVER*/
2721
2722/* Exported constants --------------------------------------------------------*/
2732#define LL_I2S_DATAFORMAT_16B (0x00000000UL)
2733#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
2734#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
2735#define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT)
2736#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
2745#define LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL)
2746#define LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH)
2755#define LL_I2S_POLARITY_LOW (0x00000000UL)
2756#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
2765#define LL_I2S_STANDARD_PHILIPS (0x00000000UL)
2766#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
2767#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
2768#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
2769#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
2778#define LL_I2S_MODE_SLAVE_TX (0x00000000UL)
2779#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
2780#define LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2)
2781#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
2782#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0)
2783#define LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
2792#define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL)
2793#define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL)
2802#define LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA)
2803#define LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA)
2804#define LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA)
2805#define LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA)
2806#define LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA)
2807#define LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA)
2808#define LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA)
2809#define LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA)
2818#define LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST)
2819#define LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST)
2824#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
2825
2830#define LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL)
2831#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
2841#define LL_I2S_AUDIOFREQ_192K 192000UL
2842#define LL_I2S_AUDIOFREQ_96K 96000UL
2843#define LL_I2S_AUDIOFREQ_48K 48000UL
2844#define LL_I2S_AUDIOFREQ_44K 44100UL
2845#define LL_I2S_AUDIOFREQ_32K 32000UL
2846#define LL_I2S_AUDIOFREQ_22K 22050UL
2847#define LL_I2S_AUDIOFREQ_16K 16000UL
2848#define LL_I2S_AUDIOFREQ_11K 11025UL
2849#define LL_I2S_AUDIOFREQ_8K 8000UL
2850#define LL_I2S_AUDIOFREQ_DEFAULT 0UL
2854#endif /* USE_FULL_LL_DRIVER */
2855
2860/* Exported macro ------------------------------------------------------------*/
2878#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2879
2886#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2896/* Exported functions --------------------------------------------------------*/
2897
2922__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength)
2923{
2924 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT, DataLength);
2925}
2926
2940__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
2941{
2942 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT));
2943}
2944
2955__STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t ChannelLengthType)
2956{
2957 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH, ChannelLengthType);
2958}
2959
2969__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(SPI_TypeDef *SPIx)
2970{
2971 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));
2972}
2973
2980__STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *SPIx)
2981{
2982 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
2983}
2984
2991__STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx)
2992{
2993 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
2994}
2995
3002__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef *SPIx)
3003{
3004 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);
3005}
3006
3016__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
3017{
3018 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL, ClockPolarity);
3019}
3020
3029__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
3030{
3031 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
3032}
3033
3047__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
3048{
3049 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
3050}
3051
3064__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
3065{
3066 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
3067}
3068
3082__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard)
3083{
3084 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Standard);
3085}
3086
3099__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
3100{
3101 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
3102}
3103
3111__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
3112{
3113 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
3114 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
3115}
3116
3124__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
3125{
3126 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
3127 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
3128}
3129
3137__STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *SPIx)
3138{
3139 LL_SPI_EnableIOSwap(SPIx);
3140}
3141
3149__STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx)
3150{
3151 LL_SPI_DisableIOSwap(SPIx);
3152}
3153
3160__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(SPI_TypeDef *SPIx)
3161{
3162 return LL_SPI_IsEnabledIOSwap(SPIx);
3163}
3164
3172__STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *SPIx)
3173{
3174 LL_SPI_EnableGPIOControl(SPIx);
3175}
3176
3184__STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx)
3185{
3186 LL_SPI_DisableGPIOControl(SPIx);
3187}
3188
3195__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
3196{
3197 return LL_SPI_IsEnabledGPIOControl(SPIx);
3198}
3199
3208__STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx)
3209{
3210 LL_SPI_EnableIOLock(SPIx);
3211}
3212
3219__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(SPI_TypeDef *SPIx)
3220{
3221 return LL_SPI_IsEnabledIOLock(SPIx);
3222}
3223
3234__STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
3235{
3236 LL_SPI_SetTransferBitOrder(SPIx, BitOrder);
3237}
3246__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(SPI_TypeDef *SPIx)
3247{
3248 return LL_SPI_GetTransferBitOrder(SPIx);
3249}
3250
3257__STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx)
3258{
3259 LL_SPI_StartMasterTransfer(SPIx);
3260}
3261
3268__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(SPI_TypeDef *SPIx)
3269{
3270 return LL_SPI_IsActiveMasterTransfer(SPIx);
3271}
3272
3289__STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
3290{
3291 LL_SPI_SetFIFOThreshold(SPIx, Threshold);
3292}
3293
3308__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(SPI_TypeDef *SPIx)
3309{
3310 return LL_SPI_GetFIFOThreshold(SPIx);
3311}
3312
3321__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t PrescalerLinear)
3322{
3323 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos));
3324}
3325
3332__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
3333{
3334 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);
3335}
3336
3346__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
3347{
3348 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_ODD, PrescalerParity << SPI_I2SCFGR_ODD_Pos);
3349}
3350
3359__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
3360{
3361 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);
3362}
3363
3370__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
3371{
3372 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
3373}
3374
3381__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
3382{
3383 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
3384}
3385
3392__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
3393{
3394 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);
3395}
3396
3413__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
3414{
3415 return LL_SPI_IsActiveFlag_RXP(SPIx);
3416}
3417
3424__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
3425{
3426 return LL_SPI_IsActiveFlag_TXP(SPIx);
3427}
3428
3435__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
3436{
3437 return LL_SPI_IsActiveFlag_UDR(SPIx);
3438}
3439
3446__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
3447{
3448 return LL_SPI_IsActiveFlag_OVR(SPIx);
3449}
3450
3457__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
3458{
3459 return LL_SPI_IsActiveFlag_FRE(SPIx);
3460}
3461
3468__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
3469{
3470 LL_SPI_ClearFlag_UDR(SPIx);
3471}
3472
3479__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
3480{
3481 LL_SPI_ClearFlag_OVR(SPIx);
3482}
3483
3490__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
3491{
3492 LL_SPI_ClearFlag_FRE(SPIx);
3493}
3494
3510__STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *SPIx)
3511{
3512 LL_SPI_EnableIT_RXP(SPIx);
3513}
3514
3521__STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *SPIx)
3522{
3523 LL_SPI_EnableIT_TXP(SPIx);
3524}
3525
3532__STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *SPIx)
3533{
3534 LL_SPI_EnableIT_UDR(SPIx);
3535}
3536
3543__STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *SPIx)
3544{
3545 LL_SPI_EnableIT_OVR(SPIx);
3546}
3547
3554__STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *SPIx)
3555{
3556 LL_SPI_EnableIT_FRE(SPIx);
3557}
3558
3565__STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *SPIx)
3566{
3567 LL_SPI_DisableIT_RXP(SPIx);
3568}
3569
3576__STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *SPIx)
3577{
3578 LL_SPI_DisableIT_TXP(SPIx);
3579}
3580
3587__STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *SPIx)
3588{
3589 LL_SPI_DisableIT_UDR(SPIx);
3590}
3591
3598__STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *SPIx)
3599{
3600 LL_SPI_DisableIT_OVR(SPIx);
3601}
3602
3609__STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx)
3610{
3611 LL_SPI_DisableIT_FRE(SPIx);
3612}
3613
3620__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
3621{
3622 return LL_SPI_IsEnabledIT_RXP(SPIx);
3623}
3624
3631__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
3632{
3633 return LL_SPI_IsEnabledIT_TXP(SPIx);
3634}
3635
3642__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
3643{
3644 return LL_SPI_IsEnabledIT_UDR(SPIx);
3645}
3646
3653__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
3654{
3655 return LL_SPI_IsEnabledIT_OVR(SPIx);
3656}
3657
3664__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
3665{
3666 return LL_SPI_IsEnabledIT_FRE(SPIx);
3667}
3668
3684__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
3685{
3686 LL_SPI_EnableDMAReq_RX(SPIx);
3687}
3688
3695__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
3696{
3697 LL_SPI_DisableDMAReq_RX(SPIx);
3698}
3699
3706__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
3707{
3708 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
3709}
3710
3717__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
3718{
3719 LL_SPI_EnableDMAReq_TX(SPIx);
3720}
3721
3728__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
3729{
3730 LL_SPI_DisableDMAReq_TX(SPIx);
3731}
3732
3739__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
3740{
3741 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
3742}
3743
3759__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
3760{
3761 return LL_SPI_ReceiveData16(SPIx);
3762}
3763
3770__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx)
3771{
3772 return LL_SPI_ReceiveData32(SPIx);
3773}
3774
3782__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
3783{
3784 LL_SPI_TransmitData16(SPIx, TxData);
3785}
3786
3794__STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
3795{
3796 LL_SPI_TransmitData32(SPIx, TxData);
3797}
3798
3799
3805#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
3811ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
3812ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
3813void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
3814void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
3815
3819#endif /* USE_FULL_LL_DRIVER */
3820
3829#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
3830
3835#ifdef __cplusplus
3836}
3837#endif
3838
3839#endif /* STM32H7xx_LL_SPI_H */
__IO
#define __IO
Definition: core_cm4.h:239
SPI_IER_TIFREIE
#define SPI_IER_TIFREIE
Definition: stm32h723xx.h:18392
SPI_SR_RXPLVL
#define SPI_SR_RXPLVL
Definition: stm32h723xx.h:18442
SPI_IFCR_EOTC
#define SPI_IFCR_EOTC
Definition: stm32h723xx.h:18455
SPI_CR1_CSTART
#define SPI_CR1_CSTART
Definition: stm32h723xx.h:18212
SPI_IFCR_UDRC
#define SPI_IFCR_UDRC
Definition: stm32h723xx.h:18461
SPI_SR_UDR
#define SPI_SR_UDR
Definition: stm32h723xx.h:18418
SPI_SR_TXC
#define SPI_SR_TXC
Definition: stm32h723xx.h:18439
SPI_IER_TSERFIE
#define SPI_IER_TSERFIE
Definition: stm32h723xx.h:18398
SPI_CFG2_COMM
#define SPI_CFG2_COMM
Definition: stm32h723xx.h:18324
SPI_I2SCFGR_DATFMT
#define SPI_I2SCFGR_DATFMT
Definition: stm32h723xx.h:18548
SPI_CFG1_CRCEN
#define SPI_CFG1_CRCEN
Definition: stm32h723xx.h:18292
SPI_CFG2_CPHA
#define SPI_CFG2_CPHA
Definition: stm32h723xx.h:18343
SPI_IER_CRCEIE
#define SPI_IER_CRCEIE
Definition: stm32h723xx.h:18389
SPI_I2SCFGR_I2SDIV
#define SPI_I2SCFGR_I2SDIV
Definition: stm32h723xx.h:18551
SPI_SR_SUSP
#define SPI_SR_SUSP
Definition: stm32h723xx.h:18436
SPI_IER_UDRIE
#define SPI_IER_UDRIE
Definition: stm32h723xx.h:18383
SPI_IFCR_MODFC
#define SPI_IFCR_MODFC
Definition: stm32h723xx.h:18473
SPI_I2SCFGR_ODD
#define SPI_I2SCFGR_ODD
Definition: stm32h723xx.h:18554
SPI_IER_TXPIE
#define SPI_IER_TXPIE
Definition: stm32h723xx.h:18371
SPI_IFCR_TXTFC
#define SPI_IFCR_TXTFC
Definition: stm32h723xx.h:18458
SPI_CFG1_MBR
#define SPI_CFG1_MBR
Definition: stm32h723xx.h:18296
SPI_SR_CRCE
#define SPI_SR_CRCE
Definition: stm32h723xx.h:18424
SPI_SR_TSERF
#define SPI_SR_TSERF
Definition: stm32h723xx.h:18433
SPI_CFG1_FTHLV
#define SPI_CFG1_FTHLV
Definition: stm32h723xx.h:18255
SPI_I2SCFGR_CKPOL
#define SPI_I2SCFGR_CKPOL
Definition: stm32h723xx.h:18539
SPI_CR1_SSI
#define SPI_CR1_SSI
Definition: stm32h723xx.h:18221
SPI_IER_DXPIE
#define SPI_IER_DXPIE
Definition: stm32h723xx.h:18374
SPI_CFG2_SP
#define SPI_CFG2_SP
Definition: stm32h723xx.h:18330
SPI_IFCR_SUSPC
#define SPI_IFCR_SUSPC
Definition: stm32h723xx.h:18479
SPI_I2SCFGR_PCMSYNC
#define SPI_I2SCFGR_PCMSYNC
Definition: stm32h723xx.h:18528
SPI_CR2_TSER
#define SPI_CR2_TSER
Definition: stm32h723xx.h:18238
SPI_CFG2_IOSWP
#define SPI_CFG2_IOSWP
Definition: stm32h723xx.h:18320
SPI_IER_OVRIE
#define SPI_IER_OVRIE
Definition: stm32h723xx.h:18386
SPI_IER_MODFIE
#define SPI_IER_MODFIE
Definition: stm32h723xx.h:18395
SPI_SR_CTSIZE
#define SPI_SR_CTSIZE
Definition: stm32h723xx.h:18450
SPI_CR1_HDDIR
#define SPI_CR1_HDDIR
Definition: stm32h723xx.h:18218
SPI_SR_DXP
#define SPI_SR_DXP
Definition: stm32h723xx.h:18409
SPI_I2SCFGR_I2SSTD
#define SPI_I2SCFGR_I2SSTD
Definition: stm32h723xx.h:18523
SPI_CFG2_MSSI
#define SPI_CFG2_MSSI
Definition: stm32h723xx.h:18304
SPI_IER_RXPIE
#define SPI_IER_RXPIE
Definition: stm32h723xx.h:18368
SPI_CR1_IOLOCK
#define SPI_CR1_IOLOCK
Definition: stm32h723xx.h:18233
SPI_SR_RXP
#define SPI_SR_RXP
Definition: stm32h723xx.h:18403
SPI_I2SCFGR_CHLEN
#define SPI_I2SCFGR_CHLEN
Definition: stm32h723xx.h:18536
SPI_CFG2_SSOE
#define SPI_CFG2_SSOE
Definition: stm32h723xx.h:18356
SPI_SR_TXP
#define SPI_SR_TXP
Definition: stm32h723xx.h:18406
SPI_CFG2_SSIOP
#define SPI_CFG2_SSIOP
Definition: stm32h723xx.h:18353
SPI_CFG1_RXDMAEN
#define SPI_CFG1_RXDMAEN
Definition: stm32h723xx.h:18276
SPI_IFCR_CRCEC
#define SPI_IFCR_CRCEC
Definition: stm32h723xx.h:18467
SPI_SR_OVR
#define SPI_SR_OVR
Definition: stm32h723xx.h:18421
SPI_CR1_CRC33_17
#define SPI_CR1_CRC33_17
Definition: stm32h723xx.h:18224
SPI_CR1_RCRCINI
#define SPI_CR1_RCRCINI
Definition: stm32h723xx.h:18227
SPI_CR1_TCRCINI
#define SPI_CR1_TCRCINI
Definition: stm32h723xx.h:18230
SPI_CFG2_LSBFRST
#define SPI_CFG2_LSBFRST
Definition: stm32h723xx.h:18340
SPI_SR_RXWNE
#define SPI_SR_RXWNE
Definition: stm32h723xx.h:18447
SPI_CFG2_MIDI
#define SPI_CFG2_MIDI
Definition: stm32h723xx.h:18312
SPI_CFG1_DSIZE
#define SPI_CFG1_DSIZE
Definition: stm32h723xx.h:18246
SPI_CFG1_UDRDET
#define SPI_CFG1_UDRDET
Definition: stm32h723xx.h:18270
SPI_CFG2_SSOM
#define SPI_CFG2_SSOM
Definition: stm32h723xx.h:18359
SPI_I2SCFGR_WSINV
#define SPI_I2SCFGR_WSINV
Definition: stm32h723xx.h:18545
SPI_SR_TXTF
#define SPI_SR_TXTF
Definition: stm32h723xx.h:18415
SPI_CR1_CSUSP
#define SPI_CR1_CSUSP
Definition: stm32h723xx.h:18215
SPI_CFG1_TXDMAEN
#define SPI_CFG1_TXDMAEN
Definition: stm32h723xx.h:18279
SPI_CR1_SPE
#define SPI_CR1_SPE
Definition: stm32h723xx.h:18206
SPI_I2SCFGR_DATLEN
#define SPI_I2SCFGR_DATLEN
Definition: stm32h723xx.h:18531
SPI_I2SCFGR_MCKOE
#define SPI_I2SCFGR_MCKOE
Definition: stm32h723xx.h:18557
SPI_IFCR_TSERFC
#define SPI_IFCR_TSERFC
Definition: stm32h723xx.h:18476
SPI_CFG2_SSM
#define SPI_CFG2_SSM
Definition: stm32h723xx.h:18349
SPI_IER_EOTIE
#define SPI_IER_EOTIE
Definition: stm32h723xx.h:18377
SPI_IFCR_TIFREC
#define SPI_IFCR_TIFREC
Definition: stm32h723xx.h:18470
SPI_SR_EOT
#define SPI_SR_EOT
Definition: stm32h723xx.h:18412
SPI_CFG1_CRCSIZE
#define SPI_CFG1_CRCSIZE
Definition: stm32h723xx.h:18283
SPI_CFG2_MASTER
#define SPI_CFG2_MASTER
Definition: stm32h723xx.h:18337
SPI_CR1_MASRX
#define SPI_CR1_MASRX
Definition: stm32h723xx.h:18209
SPI_I2SCFGR_I2SMOD
#define SPI_I2SCFGR_I2SMOD
Definition: stm32h723xx.h:18514
SPI_I2SCFGR_I2SCFG
#define SPI_I2SCFGR_I2SCFG
Definition: stm32h723xx.h:18517
SPI_CFG2_AFCNTR
#define SPI_CFG2_AFCNTR
Definition: stm32h723xx.h:18363
SPI_IER_TXTFIE
#define SPI_IER_TXTFIE
Definition: stm32h723xx.h:18380
SPI_SR_TIFRE
#define SPI_SR_TIFRE
Definition: stm32h723xx.h:18427
SPI_CR2_TSIZE
#define SPI_CR2_TSIZE
Definition: stm32h723xx.h:18241
SPI_I2SCFGR_FIXCH
#define SPI_I2SCFGR_FIXCH
Definition: stm32h723xx.h:18542
SPI_CFG2_CPOL
#define SPI_CFG2_CPOL
Definition: stm32h723xx.h:18346
SPI_CFG1_UDRCFG
#define SPI_CFG1_UDRCFG
Definition: stm32h723xx.h:18263
SPI_IFCR_OVRC
#define SPI_IFCR_OVRC
Definition: stm32h723xx.h:18464
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32h723xx.h:1479
SPI_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32h723xx.h:1490
SPI_TypeDef::CRCPOLY
__IO uint32_t CRCPOLY
Definition: stm32h723xx.h:1492
SPI_TypeDef::UDRDR
__IO uint32_t UDRDR
Definition: stm32h723xx.h:1495
SPI_TypeDef::CFG1
__IO uint32_t CFG1
Definition: stm32h723xx.h:1482
SPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32h723xx.h:1485
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32h723xx.h:1481
SPI_TypeDef::I2SCFGR
__IO uint32_t I2SCFGR
Definition: stm32h723xx.h:1496
SPI_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32h723xx.h:1488
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32h723xx.h:1480
SPI_TypeDef::TXCRC
__IO uint32_t TXCRC
Definition: stm32h723xx.h:1493
SPI_TypeDef::RXCRC
__IO uint32_t RXCRC
Definition: stm32h723xx.h:1494
SPI_TypeDef::CFG2
__IO uint32_t CFG2
Definition: stm32h723xx.h:1483
SPI_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32h723xx.h:1486
SPI_TypeDef::IER
__IO uint32_t IER
Definition: stm32h723xx.h:1484
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