RTEMS 6.1-rc2
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stm32h7xx_ll_lpuart.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_LPUART_H
21#define STM32H7xx_LL_LPUART_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
34#if defined (LPUART1)
35
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
47/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
48static const uint16_t LPUART_PRESCALER_TAB[] =
49{
50 (uint16_t)1,
51 (uint16_t)2,
52 (uint16_t)4,
53 (uint16_t)6,
54 (uint16_t)8,
55 (uint16_t)10,
56 (uint16_t)12,
57 (uint16_t)16,
58 (uint16_t)32,
59 (uint16_t)64,
60 (uint16_t)128,
61 (uint16_t)256
62};
67/* Private constants ---------------------------------------------------------*/
72/* Defines used in Baud Rate related macros and corresponding register setting computation */
73#define LPUART_LPUARTDIV_FREQ_MUL 256U
74#define LPUART_BRR_MASK 0x000FFFFFU
75#define LPUART_BRR_MIN_VALUE 0x00000300U
81/* Private macros ------------------------------------------------------------*/
82#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
90#endif /*USE_FULL_LL_DRIVER*/
91
92/* Exported types ------------------------------------------------------------*/
93#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
102typedef struct
103{
104 uint32_t PrescalerValue;
110 uint32_t BaudRate;
115 uint32_t DataWidth;
121 uint32_t StopBits;
127 uint32_t Parity;
133 uint32_t TransferDirection;
139 uint32_t HardwareFlowControl;
145} LL_LPUART_InitTypeDef;
146
150#endif /* USE_FULL_LL_DRIVER */
151
152/* Exported constants --------------------------------------------------------*/
163#define LL_LPUART_ICR_PECF USART_ICR_PECF
164#define LL_LPUART_ICR_FECF USART_ICR_FECF
165#define LL_LPUART_ICR_NCF USART_ICR_NECF
166#define LL_LPUART_ICR_ORECF USART_ICR_ORECF
167#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF
168#define LL_LPUART_ICR_TCCF USART_ICR_TCCF
169#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF
170#define LL_LPUART_ICR_CMCF USART_ICR_CMCF
171#define LL_LPUART_ICR_WUCF USART_ICR_WUCF
181#define LL_LPUART_ISR_PE USART_ISR_PE
182#define LL_LPUART_ISR_FE USART_ISR_FE
183#define LL_LPUART_ISR_NE USART_ISR_NE
184#define LL_LPUART_ISR_ORE USART_ISR_ORE
185#define LL_LPUART_ISR_IDLE USART_ISR_IDLE
186#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
187#define LL_LPUART_ISR_TC USART_ISR_TC
188#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
189#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF
190#define LL_LPUART_ISR_CTS USART_ISR_CTS
191#define LL_LPUART_ISR_BUSY USART_ISR_BUSY
192#define LL_LPUART_ISR_CMF USART_ISR_CMF
193#define LL_LPUART_ISR_SBKF USART_ISR_SBKF
194#define LL_LPUART_ISR_RWU USART_ISR_RWU
195#define LL_LPUART_ISR_WUF USART_ISR_WUF
196#define LL_LPUART_ISR_TEACK USART_ISR_TEACK
197#define LL_LPUART_ISR_REACK USART_ISR_REACK
198#define LL_LPUART_ISR_TXFE USART_ISR_TXFE
199#define LL_LPUART_ISR_RXFF USART_ISR_RXFF
200#define LL_LPUART_ISR_RXFT USART_ISR_RXFT
201#define LL_LPUART_ISR_TXFT USART_ISR_TXFT
211#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE
212#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
214#define LL_LPUART_CR1_TCIE USART_CR1_TCIE
215#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
217#define LL_LPUART_CR1_PEIE USART_CR1_PEIE
218#define LL_LPUART_CR1_CMIE USART_CR1_CMIE
219#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE
220#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE
221#define LL_LPUART_CR3_EIE USART_CR3_EIE
222#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE
223#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE
224#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE
225#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE
234#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U
235#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U
236#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U
237#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U
238#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U
239#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U
248#define LL_LPUART_DIRECTION_NONE 0x00000000U
249#define LL_LPUART_DIRECTION_RX USART_CR1_RE
250#define LL_LPUART_DIRECTION_TX USART_CR1_TE
251#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
260#define LL_LPUART_PARITY_NONE 0x00000000U
261#define LL_LPUART_PARITY_EVEN USART_CR1_PCE
262#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
271#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U
272#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
281#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1
282#define LL_LPUART_DATAWIDTH_8B 0x00000000U
283#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0
292#define LL_LPUART_PRESCALER_DIV1 0x00000000U
293#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
294#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
295#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
296 USART_PRESC_PRESCALER_0)
297#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
298#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
299 USART_PRESC_PRESCALER_0)
300#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
301 USART_PRESC_PRESCALER_1)
302#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
303 USART_PRESC_PRESCALER_1 |\
304 USART_PRESC_PRESCALER_0)
305#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
306#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
307 USART_PRESC_PRESCALER_0)
308#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
309 USART_PRESC_PRESCALER_1)
310#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
311 USART_PRESC_PRESCALER_1 |\
312 USART_PRESC_PRESCALER_0)
321#define LL_LPUART_STOPBITS_1 0x00000000U
322#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1
331#define LL_LPUART_TXRX_STANDARD 0x00000000U
332#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)
341#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U
342#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
351#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U
352#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
361#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U
363#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
374#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U
376#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
386#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U
387#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7
396#define LL_LPUART_HWCONTROL_NONE 0x00000000U
397#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE
399#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE
401#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
410#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U
411#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
412#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
421#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U
422#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP
431#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U
432#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U
441/* Exported macro ------------------------------------------------------------*/
459#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
460
467#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
497#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
498 ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
499 * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
500
509/* Exported functions --------------------------------------------------------*/
526__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
527{
528 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
529}
530
545__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
546{
547 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
548}
549
556__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
557{
558 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
559}
560
567__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
568{
569 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
570}
571
578__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
579{
580 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
581}
582
589__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
590{
591 return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
592}
593
607__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
608{
609 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
610}
611
624__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
625{
626 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
627}
628
642__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
643{
644 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
645}
646
659__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
660{
661 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
662}
663
685__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
686{
687 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
688 (RXThreshold << USART_CR3_RXFTCFG_Pos));
689}
690
699__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
700{
701 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
702}
703
711__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
712{
713 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
714}
715
723__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
724{
725 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
726}
727
734__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
735{
736 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
737}
738
745__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
746{
747 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
748}
749
756__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
757{
758 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
759}
760
767__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
768{
769 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
770}
771
785__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
786{
787 ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
788}
789
801__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
802{
803 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
804}
805
820__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
821{
822 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
823}
824
835__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
836{
837 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
838}
839
849__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
850{
851 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
852}
853
862__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
863{
864 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
865}
866
877__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
878{
879 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
880}
881
891__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
892{
893 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
894}
895
902__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
903{
904 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
905}
906
913__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
914{
915 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
916}
917
924__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
925{
926 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
927}
928
948__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
949{
950 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
951}
952
971__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
972{
973 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
974}
975
985__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
986{
987 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
988}
989
998__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
999{
1000 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
1001}
1002
1027__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
1028 uint32_t StopBits)
1029{
1030 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
1031 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
1032}
1033
1043__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
1044{
1045 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
1046}
1047
1056__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
1057{
1058 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
1059}
1060
1070__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1071{
1072 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
1073}
1074
1083__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
1084{
1085 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
1086}
1087
1097__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1098{
1099 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
1100}
1101
1110__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
1111{
1112 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
1113}
1114
1127__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
1128{
1129 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
1130}
1131
1140__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
1141{
1142 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
1143}
1144
1156__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
1157{
1158 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
1159}
1160
1171__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
1172{
1173 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
1174}
1175
1199__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
1200{
1201 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
1202 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
1203}
1204
1215__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
1216{
1217 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
1218}
1219
1228__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
1229{
1230 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
1231}
1232
1239__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1240{
1241 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1242}
1243
1250__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1251{
1252 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1253}
1254
1261__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1262{
1263 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1264}
1265
1272__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1273{
1274 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1275}
1276
1289__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
1290{
1291 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
1292}
1293
1305__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
1306{
1307 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
1308}
1309
1316__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
1317{
1318 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1319}
1320
1327__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
1328{
1329 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1330}
1331
1338__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
1339{
1340 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
1341}
1342
1353__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
1354{
1355 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
1356}
1357
1367__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
1368{
1369 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
1370}
1371
1401__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
1402 uint32_t BaudRate)
1403{
1404 if (BaudRate != 0U)
1405 {
1406 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
1407 }
1408}
1409
1432__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
1433 uint32_t PrescalerValue)
1434{
1435 uint32_t lpuartdiv;
1436 uint32_t brrresult;
1437 uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
1438
1439 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
1440
1441 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
1442 {
1443 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1444 }
1445 else
1446 {
1447 brrresult = 0x0UL;
1448 }
1449
1450 return (brrresult);
1451}
1452
1468__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
1469{
1470 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1471}
1472
1479__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
1480{
1481 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1482}
1483
1490__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
1491{
1492 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
1493}
1494
1511__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1512{
1513 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
1514}
1515
1522__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
1523{
1524 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
1525}
1526
1534__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1535{
1536 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
1537}
1538
1545__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
1546{
1547 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
1548}
1549
1556__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
1557{
1558 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
1559}
1560
1567__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
1568{
1569 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
1570}
1571
1578__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
1579{
1580 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
1581}
1582
1592__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
1593{
1594 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
1595}
1596
1605__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
1606{
1607 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
1608}
1609
1625__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
1626{
1627 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
1628}
1629
1636__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
1637{
1638 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
1639}
1640
1647__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
1648{
1649 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
1650}
1651
1658__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
1659{
1660 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
1661}
1662
1669__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
1670{
1671 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
1672}
1673
1674#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
1675
1682__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
1683{
1684 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
1685}
1686
1693__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
1694{
1695 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
1696}
1697
1698#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
1699
1706__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
1707{
1708 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
1709}
1710
1717__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
1718{
1719 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
1720}
1721
1728__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
1729{
1730 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
1731}
1732
1739__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
1740{
1741 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
1742}
1743
1750__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
1751{
1752 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
1753}
1754
1761__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
1762{
1763 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
1764}
1765
1772__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
1773{
1774 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
1775}
1776
1783__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
1784{
1785 return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
1786}
1787
1794__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
1795{
1796 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
1797}
1798
1805__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
1806{
1807 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
1808}
1809
1816__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
1817{
1818 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
1819}
1820
1827__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
1828{
1829 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
1830}
1831
1838__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
1839{
1840 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
1841}
1842
1849__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
1850{
1851 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
1852}
1853
1860__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
1861{
1862 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
1863}
1864
1871__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
1872{
1873 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
1874}
1875
1882__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
1883{
1884 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
1885}
1886
1893__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
1894{
1895 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
1896}
1897
1904__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
1905{
1906 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
1907}
1908
1915__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
1916{
1917 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
1918}
1919
1926__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
1927{
1928 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
1929}
1930
1937__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
1938{
1939 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
1940}
1941
1948__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
1949{
1950 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
1951}
1952
1968__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
1969{
1970 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
1971}
1972
1973#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
1974
1981__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
1982{
1983 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
1984}
1985
1992__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
1993{
1994 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
1995}
1996
1997#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
1998
2005__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2006{
2007 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2008}
2009
2016__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
2017{
2018 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2019}
2020
2027__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
2028{
2029 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2030}
2031
2038__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
2039{
2040 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2041}
2042
2049__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
2050{
2051 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2052}
2053
2064__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
2065{
2066 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
2067}
2068
2075__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
2076{
2077 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2078}
2079
2086__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
2087{
2088 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2089}
2090
2097__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
2098{
2099 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2100}
2101
2108__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
2109{
2110 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2111}
2112
2119__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
2120{
2121 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2122}
2123
2124#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
2125
2132__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2133{
2134 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2135}
2136
2143__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
2144{
2145 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2146}
2147
2148#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
2149
2156__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2157{
2158 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2159}
2160
2167__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
2168{
2169 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2170}
2171
2178__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
2179{
2180 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2181}
2182
2189__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
2190{
2191 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2192}
2193
2200__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
2201{
2202 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2203}
2204
2215__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
2216{
2217 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
2218}
2219
2226__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
2227{
2228 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2229}
2230
2237__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
2238{
2239 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2240}
2241
2248__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
2249{
2250 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2251}
2252
2259__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
2260{
2261 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2262}
2263
2270__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
2271{
2272 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
2273}
2274
2275#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
2276
2283__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
2284{
2285 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
2286}
2287
2294__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
2295{
2296 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
2297}
2298
2299#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
2300
2307__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
2308{
2309 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
2310}
2311
2318__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
2319{
2320 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
2321}
2322
2329__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
2330{
2331 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
2332}
2333
2340__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
2341{
2342 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
2343}
2344
2351__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
2352{
2353 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
2354}
2355
2362__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
2363{
2364 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
2365}
2366
2373__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
2374{
2375 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
2376}
2377
2384__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
2385{
2386 return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
2387}
2388
2395__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
2396{
2397 return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
2398}
2399
2406__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
2407{
2408 return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
2409}
2410
2426__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
2427{
2428 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2429}
2430
2437__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
2438{
2439 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2440}
2441
2448__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
2449{
2450 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
2451}
2452
2459__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
2460{
2461 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2462}
2463
2470__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
2471{
2472 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2473}
2474
2481__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
2482{
2483 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
2484}
2485
2492__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2493{
2494 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2495}
2496
2503__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2504{
2505 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2506}
2507
2514__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
2515{
2516 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
2517}
2518
2529__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
2530{
2531 uint32_t data_reg_addr;
2532
2533 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
2534 {
2535 /* return address of TDR register */
2536 data_reg_addr = (uint32_t) &(LPUARTx->TDR);
2537 }
2538 else
2539 {
2540 /* return address of RDR register */
2541 data_reg_addr = (uint32_t) &(LPUARTx->RDR);
2542 }
2543
2544 return data_reg_addr;
2545}
2546
2562__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
2563{
2564 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
2565}
2566
2573__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
2574{
2575 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
2576}
2577
2585__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
2586{
2587 LPUARTx->TDR = Value;
2588}
2589
2597__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
2598{
2599 LPUARTx->TDR = Value & 0x1FFUL;
2600}
2601
2617__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
2618{
2619 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
2620}
2621
2628__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
2629{
2630 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
2631}
2632
2641__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
2642{
2643 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
2644}
2645
2650#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
2655ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
2656ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
2657void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
2661#endif /* USE_FULL_LL_DRIVER */
2662
2671#endif /* LPUART1 */
2672
2677#ifdef __cplusplus
2678}
2679#endif
2680
2681#endif /* STM32H7xx_LL_LPUART_H */
2682
#define USART_ICR_WUCF
Definition: stm32h723xx.h:21309
#define USART_ISR_NE
Definition: stm32h723xx.h:21187
#define USART_ISR_RWU
Definition: stm32h723xx.h:21238
#define USART_ISR_TXE_TXFNF
Definition: stm32h723xx.h:21202
#define USART_ISR_TXFT
Definition: stm32h723xx.h:21262
#define USART_CR1_UESM
Definition: stm32h723xx.h:20901
#define USART_CR3_DEP
Definition: stm32h723xx.h:21100
#define USART_PRESC_PRESCALER
Definition: stm32h723xx.h:21324
#define USART_CR1_PEIE
Definition: stm32h723xx.h:20922
#define USART_ISR_FE
Definition: stm32h723xx.h:21184
#define USART_RQR_MMRQ
Definition: stm32h723xx.h:21170
#define USART_CR1_UE
Definition: stm32h723xx.h:20898
#define USART_RQR_SBKRQ
Definition: stm32h723xx.h:21167
#define USART_CR2_ADDM7
Definition: stm32h723xx.h:20995
#define USART_CR1_PS
Definition: stm32h723xx.h:20925
#define USART_CR3_OVRDIS
Definition: stm32h723xx.h:21091
#define USART_ICR_ORECF
Definition: stm32h723xx.h:21276
#define USART_CR2_ADD
Definition: stm32h723xx.h:21050
#define USART_CR3_TXFTCFG
Definition: stm32h723xx.h:21132
#define USART_ICR_PECF
Definition: stm32h723xx.h:21267
#define USART_CR3_RXFTIE
Definition: stm32h723xx.h:21129
#define USART_CR1_MME
Definition: stm32h723xx.h:20940
#define USART_CR2_SWAP
Definition: stm32h723xx.h:21024
#define USART_CR1_IDLEIE
Definition: stm32h723xx.h:20910
#define USART_ICR_CMCF
Definition: stm32h723xx.h:21306
#define USART_CR3_TXFTIE
Definition: stm32h723xx.h:21117
#define USART_CR3_DMAT
Definition: stm32h723xx.h:21076
#define USART_CR1_PCE
Definition: stm32h723xx.h:20928
#define USART_CR3_CTSIE
Definition: stm32h723xx.h:21085
#define USART_CR1_DEAT
Definition: stm32h723xx.h:20957
#define USART_CR1_RXFFIE
Definition: stm32h723xx.h:20980
#define USART_CR2_MSBFIRST
Definition: stm32h723xx.h:21036
#define USART_ISR_SBKF
Definition: stm32h723xx.h:21235
#define USART_CR3_WUS
Definition: stm32h723xx.h:21109
#define USART_RQR_RXFRQ
Definition: stm32h723xx.h:21173
#define USART_CR3_RTSE
Definition: stm32h723xx.h:21079
#define USART_CR3_WUFIE
Definition: stm32h723xx.h:21114
#define USART_ISR_CMF
Definition: stm32h723xx.h:21232
#define USART_CR1_RXNEIE_RXFNEIE
Definition: stm32h723xx.h:20913
#define USART_ICR_FECF
Definition: stm32h723xx.h:21270
#define USART_ISR_CTS
Definition: stm32h723xx.h:21211
#define USART_ICR_CTSCF
Definition: stm32h723xx.h:21294
#define USART_CR2_DATAINV
Definition: stm32h723xx.h:21033
#define USART_CR1_TXEIE_TXFNFIE
Definition: stm32h723xx.h:20919
#define USART_CR1_M
Definition: stm32h723xx.h:20934
#define USART_ICR_IDLECF
Definition: stm32h723xx.h:21279
#define USART_ISR_ORE
Definition: stm32h723xx.h:21190
#define USART_ISR_CTSIF
Definition: stm32h723xx.h:21208
#define USART_ISR_PE
Definition: stm32h723xx.h:21181
#define USART_CR3_CTSE
Definition: stm32h723xx.h:21082
#define USART_CR1_TCIE
Definition: stm32h723xx.h:20916
#define USART_ISR_TC
Definition: stm32h723xx.h:21199
#define USART_ISR_REACK
Definition: stm32h723xx.h:21247
#define USART_ISR_RXFF
Definition: stm32h723xx.h:21253
#define USART_CR1_CMIE
Definition: stm32h723xx.h:20943
#define USART_CR3_EIE
Definition: stm32h723xx.h:21055
#define USART_CR1_DEDT
Definition: stm32h723xx.h:20949
#define USART_CR1_TXFEIE
Definition: stm32h723xx.h:20977
#define USART_CR3_RXFTCFG
Definition: stm32h723xx.h:21123
#define USART_ISR_RXNE_RXFNE
Definition: stm32h723xx.h:21196
#define USART_CR3_HDSEL
Definition: stm32h723xx.h:21064
#define USART_ICR_NECF
Definition: stm32h723xx.h:21273
#define USART_CR3_DEM
Definition: stm32h723xx.h:21097
#define USART_ISR_IDLE
Definition: stm32h723xx.h:21193
#define USART_ICR_TCCF
Definition: stm32h723xx.h:21285
#define USART_CR1_WAKE
Definition: stm32h723xx.h:20931
#define USART_ISR_WUF
Definition: stm32h723xx.h:21241
#define USART_CR1_RE
Definition: stm32h723xx.h:20904
#define USART_CR2_TXINV
Definition: stm32h723xx.h:21030
#define USART_CR1_TE
Definition: stm32h723xx.h:20907
#define USART_CR3_DDRE
Definition: stm32h723xx.h:21094
#define USART_ISR_RXFT
Definition: stm32h723xx.h:21259
#define USART_RDR_RDR
Definition: stm32h723xx.h:21314
#define USART_ISR_TEACK
Definition: stm32h723xx.h:21244
#define USART_ISR_TXFE
Definition: stm32h723xx.h:21250
#define USART_CR2_STOP
Definition: stm32h723xx.h:21016
#define USART_CR1_FIFOEN
Definition: stm32h723xx.h:20974
#define USART_ISR_BUSY
Definition: stm32h723xx.h:21229
#define USART_CR3_DMAR
Definition: stm32h723xx.h:21073
#define USART_CR2_RXINV
Definition: stm32h723xx.h:21027
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32h723xx.h:1596
__IO uint32_t TDR
Definition: stm32h723xx.h:1607
__IO uint32_t CR1
Definition: stm32h723xx.h:1597
__IO uint32_t BRR
Definition: stm32h723xx.h:1600
__IO uint32_t ISR
Definition: stm32h723xx.h:1604
__IO uint32_t RDR
Definition: stm32h723xx.h:1606
__IO uint32_t CR2
Definition: stm32h723xx.h:1598
__IO uint32_t ICR
Definition: stm32h723xx.h:1605
__IO uint32_t PRESC
Definition: stm32h723xx.h:1608
__IO uint32_t RQR
Definition: stm32h723xx.h:1603
__IO uint32_t CR3
Definition: stm32h723xx.h:1599