RTEMS 6.1-rc2
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stm32h7xx_ll_bdma.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_BDMA_H
21#define STM32H7xx_LL_BDMA_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29#include "stm32h7xx_ll_dmamux.h"
30
35#if defined (BDMA) || defined (BDMA1) || defined (BDMA2)
36
42/* Private types -------------------------------------------------------------*/
43/* Private variables ---------------------------------------------------------*/
48/* Array used to get the BDMA channel register offset versus channel index LL_BDMA_CHANNEL_x */
49static const uint8_t LL_BDMA_CH_OFFSET_TAB[] =
50{
51 (uint8_t)(BDMA_Channel0_BASE - BDMA_BASE),
52 (uint8_t)(BDMA_Channel1_BASE - BDMA_BASE),
53 (uint8_t)(BDMA_Channel2_BASE - BDMA_BASE),
54 (uint8_t)(BDMA_Channel3_BASE - BDMA_BASE),
55 (uint8_t)(BDMA_Channel4_BASE - BDMA_BASE),
56 (uint8_t)(BDMA_Channel5_BASE - BDMA_BASE),
57 (uint8_t)(BDMA_Channel6_BASE - BDMA_BASE),
58 (uint8_t)(BDMA_Channel7_BASE - BDMA_BASE)
59};
64/* Private constants ---------------------------------------------------------*/
65/* Private macros ------------------------------------------------------------*/
70#if !defined(UNUSED)
71#define UNUSED(x) ((void)(x))
72#endif
76/* Exported types ------------------------------------------------------------*/
77#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
82typedef struct
83{
84 uint32_t PeriphOrM2MSrcAddress;
89 uint32_t MemoryOrM2MDstAddress;
94 uint32_t Direction;
100 uint32_t Mode;
107 uint32_t PeriphOrM2MSrcIncMode;
113 uint32_t MemoryOrM2MDstIncMode;
119 uint32_t PeriphOrM2MSrcDataSize;
125 uint32_t MemoryOrM2MDstDataSize;
131 uint32_t NbData;
138 uint32_t PeriphRequest;
143 uint32_t Priority;
148} LL_BDMA_InitTypeDef;
152#endif /* USE_FULL_LL_DRIVER */
153
154/* Exported constants --------------------------------------------------------*/
164#define LL_BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1
165#define LL_BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1
166#define LL_BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1
167#define LL_BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1
168#define LL_BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2
169#define LL_BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2
170#define LL_BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2
171#define LL_BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2
172#define LL_BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3
173#define LL_BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3
174#define LL_BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3
175#define LL_BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3
176#define LL_BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4
177#define LL_BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4
178#define LL_BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4
179#define LL_BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4
180#define LL_BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5
181#define LL_BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5
182#define LL_BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5
183#define LL_BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5
184#define LL_BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6
185#define LL_BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6
186#define LL_BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6
187#define LL_BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6
188#define LL_BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7
189#define LL_BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7
190#define LL_BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7
191#define LL_BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7
201#define LL_BDMA_ISR_GIF0 BDMA_ISR_GIF0
202#define LL_BDMA_ISR_TCIF0 BDMA_ISR_TCIF0
203#define LL_BDMA_ISR_HTIF0 BDMA_ISR_HTIF0
204#define LL_BDMA_ISR_TEIF0 BDMA_ISR_TEIF0
205#define LL_BDMA_ISR_GIF1 BDMA_ISR_GIF1
206#define LL_BDMA_ISR_TCIF1 BDMA_ISR_TCIF1
207#define LL_BDMA_ISR_HTIF1 BDMA_ISR_HTIF1
208#define LL_BDMA_ISR_TEIF1 BDMA_ISR_TEIF1
209#define LL_BDMA_ISR_GIF2 BDMA_ISR_GIF2
210#define LL_BDMA_ISR_TCIF2 BDMA_ISR_TCIF2
211#define LL_BDMA_ISR_HTIF2 BDMA_ISR_HTIF2
212#define LL_BDMA_ISR_TEIF2 BDMA_ISR_TEIF2
213#define LL_BDMA_ISR_GIF3 BDMA_ISR_GIF3
214#define LL_BDMA_ISR_TCIF3 BDMA_ISR_TCIF3
215#define LL_BDMA_ISR_HTIF3 BDMA_ISR_HTIF3
216#define LL_BDMA_ISR_TEIF3 BDMA_ISR_TEIF3
217#define LL_BDMA_ISR_GIF4 BDMA_ISR_GIF4
218#define LL_BDMA_ISR_TCIF4 BDMA_ISR_TCIF4
219#define LL_BDMA_ISR_HTIF4 BDMA_ISR_HTIF4
220#define LL_BDMA_ISR_TEIF4 BDMA_ISR_TEIF4
221#define LL_BDMA_ISR_GIF5 BDMA_ISR_GIF5
222#define LL_BDMA_ISR_TCIF5 BDMA_ISR_TCIF5
223#define LL_BDMA_ISR_HTIF5 BDMA_ISR_HTIF5
224#define LL_BDMA_ISR_TEIF5 BDMA_ISR_TEIF5
225#define LL_BDMA_ISR_GIF6 BDMA_ISR_GIF6
226#define LL_BDMA_ISR_TCIF6 BDMA_ISR_TCIF6
227#define LL_BDMA_ISR_HTIF6 BDMA_ISR_HTIF6
228#define LL_BDMA_ISR_TEIF6 BDMA_ISR_TEIF6
229#define LL_BDMA_ISR_GIF7 BDMA_ISR_GIF7
230#define LL_BDMA_ISR_TCIF7 BDMA_ISR_TCIF7
231#define LL_BDMA_ISR_HTIF7 BDMA_ISR_HTIF7
232#define LL_BDMA_ISR_TEIF7 BDMA_ISR_TEIF7
242#define LL_BDMA_CCR_TCIE BDMA_CCR_TCIE
243#define LL_BDMA_CCR_HTIE BDMA_CCR_HTIE
244#define LL_BDMA_CCR_TEIE BDMA_CCR_TEIE
253#define LL_BDMA_CHANNEL_0 0x00000000U
254#define LL_BDMA_CHANNEL_1 0x00000001U
255#define LL_BDMA_CHANNEL_2 0x00000002U
256#define LL_BDMA_CHANNEL_3 0x00000003U
257#define LL_BDMA_CHANNEL_4 0x00000004U
258#define LL_BDMA_CHANNEL_5 0x00000005U
259#define LL_BDMA_CHANNEL_6 0x00000006U
260#define LL_BDMA_CHANNEL_7 0x00000007U
261#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
262#define LL_BDMA_CHANNEL_ALL 0xFFFF0000U
263#endif /*USE_FULL_LL_DRIVER*/
272#define LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
273#define LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR
274#define LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM
283#define LL_BDMA_MODE_NORMAL 0x00000000U
284#define LL_BDMA_MODE_CIRCULAR BDMA_CCR_CIRC
293#define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U
294#define LL_BDMA_DOUBLEBUFFER_MODE_ENABLE BDMA_CCR_DBM
303#define LL_BDMA_PERIPH_INCREMENT BDMA_CCR_PINC
304#define LL_BDMA_PERIPH_NOINCREMENT 0x00000000U
313#define LL_BDMA_MEMORY_INCREMENT BDMA_CCR_MINC
314#define LL_BDMA_MEMORY_NOINCREMENT 0x00000000U
323#define LL_BDMA_PDATAALIGN_BYTE 0x00000000U
324#define LL_BDMA_PDATAALIGN_HALFWORD BDMA_CCR_PSIZE_0
325#define LL_BDMA_PDATAALIGN_WORD BDMA_CCR_PSIZE_1
334#define LL_BDMA_MDATAALIGN_BYTE 0x00000000U
335#define LL_BDMA_MDATAALIGN_HALFWORD BDMA_CCR_MSIZE_0
336#define LL_BDMA_MDATAALIGN_WORD BDMA_CCR_MSIZE_1
345#define LL_BDMA_PRIORITY_LOW 0x00000000U
346#define LL_BDMA_PRIORITY_MEDIUM BDMA_CCR_PL_0
347#define LL_BDMA_PRIORITY_HIGH BDMA_CCR_PL_1
348#define LL_BDMA_PRIORITY_VERYHIGH BDMA_CCR_PL
357#define LL_BDMA_CURRENTTARGETMEM0 0x00000000U
358#define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT
366/* Exported macro ------------------------------------------------------------*/
383#define LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
384
391#define LL_BDMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
405#if defined (BDMA1)
406#define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
407(((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA)
408#else
409#define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (BDMA)
410#endif /* BDMA1 */
411
417#if defined (BDMA1)
418#define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
419(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \
420 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel0)) ? LL_BDMA_CHANNEL_0 : \
421 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \
422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel1)) ? LL_BDMA_CHANNEL_1 : \
423 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \
424 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel2)) ? LL_BDMA_CHANNEL_2 : \
425 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \
426 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel3)) ? LL_BDMA_CHANNEL_3 : \
427 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \
428 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel4)) ? LL_BDMA_CHANNEL_4 : \
429 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \
430 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel5)) ? LL_BDMA_CHANNEL_5 : \
431 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \
432 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel6)) ? LL_BDMA_CHANNEL_6 : \
433 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel7)) ? LL_BDMA_CHANNEL_7 : \
434LL_BDMA_CHANNEL_7)
435#else
436#define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
437(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \
438 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \
439 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \
440 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \
441 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \
442 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \
443 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \
444 LL_BDMA_CHANNEL_7)
445#endif /* BDMA1 */
446
453#if defined (BDMA1)
454#define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \
455((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \
456 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA1_Channel0 : \
457 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \
458 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA1_Channel1 : \
459 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \
460 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA1_Channel2 : \
461 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \
462 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA1_Channel3 : \
463 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \
464 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA1_Channel4 : \
465 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \
466 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA1_Channel5 : \
467 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \
468 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA1_Channel6 : \
469 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_7))) ? BDMA_Channel7 : \
470 BDMA1_Channel7)
471#else
472#define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \
473((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \
474 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \
475 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \
476 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \
477 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \
478 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \
479 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \
480 BDMA_Channel7)
481#endif /* BDMA1 */
490/* Exported functions --------------------------------------------------------*/
515__STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
516{
517 uint32_t bdma_base_addr = (uint32_t)BDMAx;
518
519 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
520}
521
537__STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
538{
539 uint32_t bdma_base_addr = (uint32_t)BDMAx;
540
541 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
542}
543
559__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
560{
561 uint32_t bdma_base_addr = (uint32_t)BDMAx;
562
563 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN) == (BDMA_CCR_EN)) ? 1UL : 0UL);
564}
565
596__STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)
597{
598 uint32_t bdma_base_addr = (uint32_t)BDMAx;
599
600 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
601 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL,
602 Configuration);
603}
604
625__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction)
626{
627 uint32_t bdma_base_addr = (uint32_t)BDMAx;
628
629 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
630 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM, Direction);
631}
632
652__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel)
653{
654 uint32_t bdma_base_addr = (uint32_t)BDMAx;
655
656 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
657 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM));
658}
659
680__STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode)
681{
682 uint32_t bdma_base_addr = (uint32_t)BDMAx;
683
684 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CIRC,
685 Mode);
686}
687
705__STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
706{
707 uint32_t bdma_base_addr = (uint32_t)BDMAx;
708
709 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
710 BDMA_CCR_CIRC));
711}
712
731__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
732{
733 uint32_t bdma_base_addr = (uint32_t)BDMAx;
734
735 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PINC,
736 PeriphOrM2MSrcIncMode);
737}
738
756__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
757{
758 uint32_t bdma_base_addr = (uint32_t)BDMAx;
759
760 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
761 BDMA_CCR_PINC));
762}
763
782__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
783{
784 uint32_t bdma_base_addr = (uint32_t)BDMAx;
785
786 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MINC,
787 MemoryOrM2MDstIncMode);
788}
789
807__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
808{
809 uint32_t bdma_base_addr = (uint32_t)BDMAx;
810
811 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
812 BDMA_CCR_MINC));
813}
814
834__STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
835{
836 uint32_t bdma_base_addr = (uint32_t)BDMAx;
837
838 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PSIZE,
839 PeriphOrM2MSrcDataSize);
840}
841
860__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel)
861{
862 uint32_t bdma_base_addr = (uint32_t)BDMAx;
863
864 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
865 BDMA_CCR_PSIZE));
866}
867
887__STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
888{
889 uint32_t bdma_base_addr = (uint32_t)BDMAx;
890
891 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MSIZE,
892 MemoryOrM2MDstDataSize);
893}
894
913__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel)
914{
915 uint32_t bdma_base_addr = (uint32_t)BDMAx;
916
917 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
918 BDMA_CCR_MSIZE));
919}
920
941__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority)
942{
943 uint32_t bdma_base_addr = (uint32_t)BDMAx;
944
945 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PL,
946 Priority);
947}
948
968__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel)
969{
970 uint32_t bdma_base_addr = (uint32_t)BDMAx;
971
972 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
973 BDMA_CCR_PL));
974}
975
994__STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData)
995{
996 uint32_t bdma_base_addr = (uint32_t)BDMAx;
997
998 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
999 BDMA_CNDTR_NDT, NbData);
1000}
1001
1019__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel)
1020{
1021 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1022
1023 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
1024 BDMA_CNDTR_NDT));
1025}
1026
1045__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory)
1046{
1047 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1048
1049 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT, CurrentMemory);
1050}
1051
1069__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel)
1070{
1071 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1072
1073 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT));
1074}
1075
1091__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
1092{
1093 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1094
1095 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
1096}
1097
1113__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
1114{
1115 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1116
1117 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
1118}
1119
1144__STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress,
1145 uint32_t DstAddress, uint32_t Direction)
1146{
1147 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1148
1149 /* Direction Memory to Periph */
1150 if (Direction == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH)
1151 {
1152 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, SrcAddress);
1153 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, DstAddress);
1154 }
1155 /* Direction Periph to Memory and Memory to Memory */
1156 else
1157 {
1158 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
1159 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, DstAddress);
1160 }
1161}
1162
1181__STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1182{
1183 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1184
1185 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
1186}
1187
1206__STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress)
1207{
1208 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1209
1210 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
1211}
1212
1229__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1230{
1231 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1232
1233 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
1234}
1235
1252__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1253{
1254 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1255
1256 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
1257}
1258
1277__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1278{
1279 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1280
1281 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
1282}
1283
1302__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1303{
1304 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1305
1306 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
1307}
1308
1325__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1326{
1327 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1328
1329 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
1330}
1331
1348__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1349{
1350 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1351
1352 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
1353}
1354
1371__STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address)
1372{
1373 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1374
1375 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR, BDMA_CM1AR_MA, Address);
1376}
1377
1393__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel)
1394{
1395 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1396
1397 return (((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR);
1398}
1399
1439__STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request)
1440{
1441 UNUSED(BDMAx);
1442 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1443}
1444
1483__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel)
1484{
1485 UNUSED(BDMAx);
1486 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
1487}
1488
1504__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx)
1505{
1506 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL);
1507}
1508
1515__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx)
1516{
1517 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL);
1518}
1519
1526__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx)
1527{
1528 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL);
1529}
1530
1537__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx)
1538{
1539 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL);
1540}
1541
1548__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx)
1549{
1550 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL);
1551}
1552
1559__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx)
1560{
1561 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL);
1562}
1563
1570__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx)
1571{
1572 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL);
1573}
1574
1581__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx)
1582{
1583 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL);
1584}
1585
1592__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx)
1593{
1594 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL);
1595}
1602__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx)
1603{
1604 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL);
1605}
1606
1613__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx)
1614{
1615 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL);
1616}
1617
1624__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx)
1625{
1626 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL);
1627}
1628
1635__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx)
1636{
1637 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL);
1638}
1639
1646__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx)
1647{
1648 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL);
1649}
1650
1657__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx)
1658{
1659 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL);
1660}
1661
1668__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx)
1669{
1670 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL);
1671}
1672
1679__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx)
1680{
1681 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL);
1682}
1683
1690__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx)
1691{
1692 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL);
1693}
1694
1701__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx)
1702{
1703 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL);
1704}
1705
1712__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx)
1713{
1714 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL);
1715}
1716
1723__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx)
1724{
1725 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL);
1726}
1727
1734__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx)
1735{
1736 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL);
1737}
1738
1745__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx)
1746{
1747 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL);
1748}
1749
1756__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx)
1757{
1758 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL);
1759}
1760
1767__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx)
1768{
1769 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL);
1770}
1771
1778__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx)
1779{
1780 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL);
1781}
1782
1789__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx)
1790{
1791 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL);
1792}
1793
1800__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx)
1801{
1802 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL);
1803}
1804
1811__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx)
1812{
1813 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL);
1814}
1815
1822__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx)
1823{
1824 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL);
1825}
1826
1833__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx)
1834{
1835 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL);
1836}
1837
1844__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx)
1845{
1846 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL);
1847}
1848
1859__STATIC_INLINE void LL_BDMA_ClearFlag_GI0(BDMA_TypeDef *BDMAx)
1860{
1861 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF0);
1862}
1863
1874__STATIC_INLINE void LL_BDMA_ClearFlag_GI1(BDMA_TypeDef *BDMAx)
1875{
1876 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF1);
1877}
1878
1889__STATIC_INLINE void LL_BDMA_ClearFlag_GI2(BDMA_TypeDef *BDMAx)
1890{
1891 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF2);
1892}
1893
1904__STATIC_INLINE void LL_BDMA_ClearFlag_GI3(BDMA_TypeDef *BDMAx)
1905{
1906 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF3);
1907}
1908
1919__STATIC_INLINE void LL_BDMA_ClearFlag_GI4(BDMA_TypeDef *BDMAx)
1920{
1921 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF4);
1922}
1923
1934__STATIC_INLINE void LL_BDMA_ClearFlag_GI5(BDMA_TypeDef *BDMAx)
1935{
1936 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF5);
1937}
1938
1949__STATIC_INLINE void LL_BDMA_ClearFlag_GI6(BDMA_TypeDef *BDMAx)
1950{
1951 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF6);
1952}
1953
1964__STATIC_INLINE void LL_BDMA_ClearFlag_GI7(BDMA_TypeDef *BDMAx)
1965{
1966 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF7);
1967}
1968
1975__STATIC_INLINE void LL_BDMA_ClearFlag_TC0(BDMA_TypeDef *BDMAx)
1976{
1977 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF0);
1978}
1979
1986__STATIC_INLINE void LL_BDMA_ClearFlag_TC1(BDMA_TypeDef *BDMAx)
1987{
1988 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF1);
1989}
1990
1997__STATIC_INLINE void LL_BDMA_ClearFlag_TC2(BDMA_TypeDef *BDMAx)
1998{
1999 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF2);
2000}
2001
2008__STATIC_INLINE void LL_BDMA_ClearFlag_TC3(BDMA_TypeDef *BDMAx)
2009{
2010 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF3);
2011}
2012
2019__STATIC_INLINE void LL_BDMA_ClearFlag_TC4(BDMA_TypeDef *BDMAx)
2020{
2021 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF4);
2022}
2023
2030__STATIC_INLINE void LL_BDMA_ClearFlag_TC5(BDMA_TypeDef *BDMAx)
2031{
2032 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF5);
2033}
2034
2041__STATIC_INLINE void LL_BDMA_ClearFlag_TC6(BDMA_TypeDef *BDMAx)
2042{
2043 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF6);
2044}
2045
2052__STATIC_INLINE void LL_BDMA_ClearFlag_TC7(BDMA_TypeDef *BDMAx)
2053{
2054 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF7);
2055}
2056
2063__STATIC_INLINE void LL_BDMA_ClearFlag_HT0(BDMA_TypeDef *BDMAx)
2064{
2065 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF0);
2066}
2067
2074__STATIC_INLINE void LL_BDMA_ClearFlag_HT1(BDMA_TypeDef *BDMAx)
2075{
2076 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF1);
2077}
2078
2085__STATIC_INLINE void LL_BDMA_ClearFlag_HT2(BDMA_TypeDef *BDMAx)
2086{
2087 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF2);
2088}
2089
2096__STATIC_INLINE void LL_BDMA_ClearFlag_HT3(BDMA_TypeDef *BDMAx)
2097{
2098 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF3);
2099}
2100
2107__STATIC_INLINE void LL_BDMA_ClearFlag_HT4(BDMA_TypeDef *BDMAx)
2108{
2109 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF4);
2110}
2111
2118__STATIC_INLINE void LL_BDMA_ClearFlag_HT5(BDMA_TypeDef *BDMAx)
2119{
2120 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF5);
2121}
2122
2129__STATIC_INLINE void LL_BDMA_ClearFlag_HT6(BDMA_TypeDef *BDMAx)
2130{
2131 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF6);
2132}
2133
2140__STATIC_INLINE void LL_BDMA_ClearFlag_HT7(BDMA_TypeDef *BDMAx)
2141{
2142 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF7);
2143}
2144
2151__STATIC_INLINE void LL_BDMA_ClearFlag_TE0(BDMA_TypeDef *BDMAx)
2152{
2153 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF0);
2154}
2155
2162__STATIC_INLINE void LL_BDMA_ClearFlag_TE1(BDMA_TypeDef *BDMAx)
2163{
2164 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF1);
2165}
2166
2173__STATIC_INLINE void LL_BDMA_ClearFlag_TE2(BDMA_TypeDef *BDMAx)
2174{
2175 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF2);
2176}
2177
2184__STATIC_INLINE void LL_BDMA_ClearFlag_TE3(BDMA_TypeDef *BDMAx)
2185{
2186 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF3);
2187}
2188
2195__STATIC_INLINE void LL_BDMA_ClearFlag_TE4(BDMA_TypeDef *BDMAx)
2196{
2197 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF4);
2198}
2199
2206__STATIC_INLINE void LL_BDMA_ClearFlag_TE5(BDMA_TypeDef *BDMAx)
2207{
2208 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF5);
2209}
2210
2217__STATIC_INLINE void LL_BDMA_ClearFlag_TE6(BDMA_TypeDef *BDMAx)
2218{
2219 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF6);
2220}
2221
2228__STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx)
2229{
2230 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF7);
2231}
2232
2256__STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
2257{
2258 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2259
2260 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
2261}
2262
2278__STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
2279{
2280 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2281
2282 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
2283}
2284
2300__STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
2301{
2302 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2303
2304 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
2305}
2306
2322__STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
2323{
2324 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2325
2326 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
2327}
2328
2344__STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
2345{
2346 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2347
2348 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
2349}
2350
2366__STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
2367{
2368 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2369
2370 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
2371}
2372
2388__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
2389{
2390 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2391
2392 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE) == (BDMA_CCR_TCIE)) ? 1UL : 0UL);
2393}
2394
2410__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
2411{
2412 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2413
2414 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE) == (BDMA_CCR_HTIE)) ? 1UL : 0UL);
2415}
2416
2432__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
2433{
2434 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2435
2436 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE) == (BDMA_CCR_TEIE)) ? 1UL : 0UL);
2437}
2438
2443#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
2449uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct);
2450uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel);
2451void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct);
2452
2456#endif /* USE_FULL_LL_DRIVER */
2457
2466#endif /* BDMA || BDMA1 || BDMA2 */
2471#ifdef __cplusplus
2472}
2473#endif
2474
2475#endif /* STM32H7xx_LL_BDMA_H */
2476
BDMA_ISR_HTIF1
#define BDMA_ISR_HTIF1
Definition: stm32h723xx.h:6649
BDMA_ISR_HTIF5
#define BDMA_ISR_HTIF5
Definition: stm32h723xx.h:6697
BDMA_ISR_GIF2
#define BDMA_ISR_GIF2
Definition: stm32h723xx.h:6655
BDMA_IFCR_CTEIF2
#define BDMA_IFCR_CTEIF2
Definition: stm32h723xx.h:6762
BDMA_IFCR_CGIF6
#define BDMA_IFCR_CGIF6
Definition: stm32h723xx.h:6801
BDMA_IFCR_CTCIF6
#define BDMA_IFCR_CTCIF6
Definition: stm32h723xx.h:6804
BDMA_CCR_MEM2MEM
#define BDMA_CCR_MEM2MEM
Definition: stm32h723xx.h:6870
BDMA_ISR_TCIF2
#define BDMA_ISR_TCIF2
Definition: stm32h723xx.h:6658
BDMA_CCR_MINC
#define BDMA_CCR_MINC
Definition: stm32h723xx.h:6848
BDMA_CCR_PL
#define BDMA_CCR_PL
Definition: stm32h723xx.h:6864
BDMA_CCR_TCIE
#define BDMA_CCR_TCIE
Definition: stm32h723xx.h:6830
BDMA_CM1AR_MA
#define BDMA_CM1AR_MA
Definition: stm32h723xx.h:6896
BDMA_IFCR_CTCIF0
#define BDMA_IFCR_CTCIF0
Definition: stm32h723xx.h:6732
BDMA_CCR_EN
#define BDMA_CCR_EN
Definition: stm32h723xx.h:6827
BDMA_ISR_TCIF1
#define BDMA_ISR_TCIF1
Definition: stm32h723xx.h:6646
BDMA_ISR_GIF6
#define BDMA_ISR_GIF6
Definition: stm32h723xx.h:6703
BDMA_IFCR_CHTIF3
#define BDMA_IFCR_CHTIF3
Definition: stm32h723xx.h:6771
BDMA_ISR_HTIF6
#define BDMA_ISR_HTIF6
Definition: stm32h723xx.h:6709
BDMA_ISR_HTIF2
#define BDMA_ISR_HTIF2
Definition: stm32h723xx.h:6661
BDMA_ISR_TEIF5
#define BDMA_ISR_TEIF5
Definition: stm32h723xx.h:6700
DMAMUX_CxCR_DMAREQ_ID
#define DMAMUX_CxCR_DMAREQ_ID
Definition: stm32h723xx.h:9150
BDMA_ISR_TCIF6
#define BDMA_ISR_TCIF6
Definition: stm32h723xx.h:6706
BDMA_IFCR_CTEIF6
#define BDMA_IFCR_CTEIF6
Definition: stm32h723xx.h:6810
BDMA_ISR_TCIF0
#define BDMA_ISR_TCIF0
Definition: stm32h723xx.h:6634
BDMA_ISR_TEIF3
#define BDMA_ISR_TEIF3
Definition: stm32h723xx.h:6676
BDMA_ISR_TEIF7
#define BDMA_ISR_TEIF7
Definition: stm32h723xx.h:6724
BDMA_ISR_TEIF0
#define BDMA_ISR_TEIF0
Definition: stm32h723xx.h:6640
BDMA_IFCR_CTCIF1
#define BDMA_IFCR_CTCIF1
Definition: stm32h723xx.h:6744
BDMA_ISR_GIF0
#define BDMA_ISR_GIF0
Definition: stm32h723xx.h:6631
BDMA_ISR_HTIF0
#define BDMA_ISR_HTIF0
Definition: stm32h723xx.h:6637
BDMA_IFCR_CHTIF4
#define BDMA_IFCR_CHTIF4
Definition: stm32h723xx.h:6783
BDMA_IFCR_CTCIF4
#define BDMA_IFCR_CTCIF4
Definition: stm32h723xx.h:6780
BDMA_CNDTR_NDT
#define BDMA_CNDTR_NDT
Definition: stm32h723xx.h:6881
BDMA_IFCR_CTCIF5
#define BDMA_IFCR_CTCIF5
Definition: stm32h723xx.h:6792
BDMA_IFCR_CGIF2
#define BDMA_IFCR_CGIF2
Definition: stm32h723xx.h:6753
BDMA_IFCR_CGIF0
#define BDMA_IFCR_CGIF0
Definition: stm32h723xx.h:6729
BDMA_ISR_TCIF4
#define BDMA_ISR_TCIF4
Definition: stm32h723xx.h:6682
BDMA_IFCR_CTEIF3
#define BDMA_IFCR_CTEIF3
Definition: stm32h723xx.h:6774
BDMA_ISR_TEIF4
#define BDMA_ISR_TEIF4
Definition: stm32h723xx.h:6688
BDMA_IFCR_CTEIF4
#define BDMA_IFCR_CTEIF4
Definition: stm32h723xx.h:6786
BDMA_IFCR_CHTIF0
#define BDMA_IFCR_CHTIF0
Definition: stm32h723xx.h:6735
BDMA_CCR_HTIE
#define BDMA_CCR_HTIE
Definition: stm32h723xx.h:6833
BDMA_CCR_MSIZE
#define BDMA_CCR_MSIZE
Definition: stm32h723xx.h:6858
BDMA_IFCR_CTEIF5
#define BDMA_IFCR_CTEIF5
Definition: stm32h723xx.h:6798
BDMA_ISR_GIF4
#define BDMA_ISR_GIF4
Definition: stm32h723xx.h:6679
BDMA_CCR_DBM
#define BDMA_CCR_DBM
Definition: stm32h723xx.h:6873
BDMA_IFCR_CGIF1
#define BDMA_IFCR_CGIF1
Definition: stm32h723xx.h:6741
BDMA_ISR_TCIF5
#define BDMA_ISR_TCIF5
Definition: stm32h723xx.h:6694
BDMA_CCR_CIRC
#define BDMA_CCR_CIRC
Definition: stm32h723xx.h:6842
BDMA_IFCR_CHTIF6
#define BDMA_IFCR_CHTIF6
Definition: stm32h723xx.h:6807
BDMA_ISR_GIF7
#define BDMA_ISR_GIF7
Definition: stm32h723xx.h:6715
BDMA_IFCR_CTEIF0
#define BDMA_IFCR_CTEIF0
Definition: stm32h723xx.h:6738
BDMA_ISR_HTIF7
#define BDMA_ISR_HTIF7
Definition: stm32h723xx.h:6721
BDMA_ISR_HTIF3
#define BDMA_ISR_HTIF3
Definition: stm32h723xx.h:6673
BDMA_IFCR_CHTIF7
#define BDMA_IFCR_CHTIF7
Definition: stm32h723xx.h:6819
BDMA_CCR_PINC
#define BDMA_CCR_PINC
Definition: stm32h723xx.h:6845
BDMA_IFCR_CGIF7
#define BDMA_IFCR_CGIF7
Definition: stm32h723xx.h:6813
BDMA_IFCR_CHTIF5
#define BDMA_IFCR_CHTIF5
Definition: stm32h723xx.h:6795
BDMA_ISR_HTIF4
#define BDMA_ISR_HTIF4
Definition: stm32h723xx.h:6685
BDMA_IFCR_CTEIF1
#define BDMA_IFCR_CTEIF1
Definition: stm32h723xx.h:6750
BDMA_ISR_GIF1
#define BDMA_ISR_GIF1
Definition: stm32h723xx.h:6643
BDMA_ISR_GIF5
#define BDMA_ISR_GIF5
Definition: stm32h723xx.h:6691
BDMA_IFCR_CTEIF7
#define BDMA_IFCR_CTEIF7
Definition: stm32h723xx.h:6822
BDMA_CCR_CT
#define BDMA_CCR_CT
Definition: stm32h723xx.h:6876
BDMA_IFCR_CHTIF1
#define BDMA_IFCR_CHTIF1
Definition: stm32h723xx.h:6747
BDMA_CCR_PSIZE
#define BDMA_CCR_PSIZE
Definition: stm32h723xx.h:6852
BDMA_IFCR_CTCIF7
#define BDMA_IFCR_CTCIF7
Definition: stm32h723xx.h:6816
BDMA_CCR_DIR
#define BDMA_CCR_DIR
Definition: stm32h723xx.h:6839
BDMA_IFCR_CTCIF2
#define BDMA_IFCR_CTCIF2
Definition: stm32h723xx.h:6756
BDMA_ISR_TEIF1
#define BDMA_ISR_TEIF1
Definition: stm32h723xx.h:6652
BDMA_IFCR_CGIF4
#define BDMA_IFCR_CGIF4
Definition: stm32h723xx.h:6777
BDMA_IFCR_CGIF5
#define BDMA_IFCR_CGIF5
Definition: stm32h723xx.h:6789
BDMA_ISR_TEIF6
#define BDMA_ISR_TEIF6
Definition: stm32h723xx.h:6712
BDMA_CCR_TEIE
#define BDMA_CCR_TEIE
Definition: stm32h723xx.h:6836
BDMA_IFCR_CGIF3
#define BDMA_IFCR_CGIF3
Definition: stm32h723xx.h:6765
BDMA_ISR_TCIF3
#define BDMA_ISR_TCIF3
Definition: stm32h723xx.h:6670
BDMA_ISR_TEIF2
#define BDMA_ISR_TEIF2
Definition: stm32h723xx.h:6664
BDMA_IFCR_CHTIF2
#define BDMA_IFCR_CHTIF2
Definition: stm32h723xx.h:6759
BDMA_ISR_TCIF7
#define BDMA_ISR_TCIF7
Definition: stm32h723xx.h:6718
BDMA_ISR_GIF3
#define BDMA_ISR_GIF3
Definition: stm32h723xx.h:6667
BDMA_IFCR_CTCIF3
#define BDMA_IFCR_CTCIF3
Definition: stm32h723xx.h:6768
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
stm32h7xx_ll_dmamux.h
Header file of DMAMUX LL module.
BDMA_Channel_TypeDef
Definition: stm32h723xx.h:619
BDMA_TypeDef
Definition: stm32h723xx.h:628
BDMA_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32h723xx.h:629
BDMA_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32h723xx.h:630
DMAMUX_Channel_TypeDef
Definition: stm32h723xx.h:634
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