RTEMS 6.1-rc2
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stm32h7xx_ll_adc.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_ADC_H
21#define STM32H7xx_LL_ADC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
34#if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43
44/* Private constants ---------------------------------------------------------*/
50/* Internal mask for ADC calibration: */
51/* Internal register offset for ADC calibration factors configuration */
52
53/* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ... */
54/* the relevant bits for: */
55/* (concatenation of multiple bits used in different registers) */
56/* - ADC calibration configuration: configuration before calibration start */
57/* - ADC calibration factors: register offset */
58#define ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */
59#define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
60#define ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
61#define ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)
62#define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */
63
64
65/* Internal mask for ADC group regular sequencer: */
66/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
67/* - sequencer register offset */
68/* - sequencer rank bits position into the selected register */
69
70/* Internal register offset for ADC group regular sequencer configuration */
71/* (offset placed into a spare area of literal definition) */
72#define ADC_SQR1_REGOFFSET (0x00000000UL)
73#define ADC_SQR2_REGOFFSET (0x00000100UL)
74#define ADC_SQR3_REGOFFSET (0x00000200UL)
75#define ADC_SQR4_REGOFFSET (0x00000300UL)
76
77#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
78#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
79#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
80
81/* Definition of ADC group regular sequencer bits information to be inserted */
82/* into ADC group regular sequencer ranks literals definition. */
83#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
84#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
85#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
86#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
87#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
88#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
89#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
90#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
91#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
92#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
93#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
94#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
95#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
96#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
97#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
98#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
99
100
101
102/* Internal mask for ADC group injected sequencer: */
103/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
104/* - data register offset */
105/* - sequencer rank bits position into the selected register */
106
107/* Internal register offset for ADC group injected data register */
108/* (offset placed into a spare area of literal definition) */
109#define ADC_JDR1_REGOFFSET (0x00000000UL)
110#define ADC_JDR2_REGOFFSET (0x00000100UL)
111#define ADC_JDR3_REGOFFSET (0x00000200UL)
112#define ADC_JDR4_REGOFFSET (0x00000300UL)
113
114#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
115#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
116#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
117
118/* Definition of ADC group injected sequencer bits information to be inserted */
119/* into ADC group injected sequencer ranks literals definition. */
120#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
121#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
122#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
123#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
124
125
126
127/* Internal mask for ADC group regular trigger: */
128/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
129/* - regular trigger source */
130/* - regular trigger edge */
131#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
132
133/* Mask containing trigger source masks for each of possible */
134/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
135/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
136#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
137 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
138 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
139 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
140
141/* Mask containing trigger edge masks for each of possible */
142/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
143/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
144#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
145 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
146 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
147 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
148
149/* Definition of ADC group regular trigger bits information. */
150#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
151#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
152
153
154
155/* Internal mask for ADC group injected trigger: */
156/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
157/* - injected trigger source */
158/* - injected trigger edge */
159#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
160
161/* Mask containing trigger source masks for each of possible */
162/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
163/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
164#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
165 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
166 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
167 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
168
169/* Mask containing trigger edge masks for each of possible */
170/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
171/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
172#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
173 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
174 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
175 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
176
177/* Definition of ADC group injected trigger bits information. */
178#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
179#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
180
181
182
183
184
185
186/* Internal mask for ADC channel: */
187/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
188/* - channel identifier defined by number */
189/* - channel identifier defined by bitfield */
190/* - channel differentiation between external channels (connected to */
191/* GPIO pins) and internal channels (connected to internal paths) */
192/* - channel sampling time defined by SMPRx register offset */
193/* and SMPx bits positions into SMPRx register */
194#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
195#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
196#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
197#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
198/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
199#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
200
201/* Channel differentiation between external and internal channels */
202#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
203#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
204
205/* Internal register offset for ADC channel sampling time configuration */
206/* (offset placed into a spare area of literal definition) */
207#define ADC_SMPR1_REGOFFSET (0x00000000UL)
208#define ADC_SMPR2_REGOFFSET (0x02000000UL)
209#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
210#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
211
212#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
213#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
214
215/* Definition of channels ID number information to be inserted into */
216/* channels literals definition. */
217#define ADC_CHANNEL_0_NUMBER (0x00000000UL)
218#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
219#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
220#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
221#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
222#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
223#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
224#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
225#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
226#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
227#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
228#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
229#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
230#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
231#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
232#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
233#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
234#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
235#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
236#define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
237
238/* Definition of channels ID bitfield information to be inserted into */
239/* channels literals definition. */
240#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
241#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
242#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
243#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
244#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
245#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
246#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
247#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
248#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
249#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
250#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
251#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
252#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
253#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
254#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
255#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
256#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
257#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
258#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
259#define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
260
261/* Definition of channels sampling time information to be inserted into */
262/* channels literals definition. */
263#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
264#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
265#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
266#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
267#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
268#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
269#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
270#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
271#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
272#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
273#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
274#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
275#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
276#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
277#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
278#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
279#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
280#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
281#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
282#define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */
283
284
285/* Internal mask for ADC mode single or differential ended: */
286/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
287/* the relevant bits for: */
288/* (concatenation of multiple bits used in different registers) */
289/* - ADC calibration: calibration start, calibration factor get or set */
290/* - ADC channels: set each ADC channel ending mode */
291#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
292#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
293#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
294#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
295#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
296#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
297#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
298
299/* Internal mask for ADC analog watchdog: */
300/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
301/* (concatenation of multiple bits used in different analog watchdogs, */
302/* (feature of several watchdogs not available on all STM32 families)). */
303/* - analog watchdog 1: monitored channel defined by number, */
304/* selection of ADC group (ADC groups regular and-or injected). */
305/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
306/* selection on groups. */
307
308/* Internal register offset for ADC analog watchdog channel configuration */
309#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
310#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
311#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
312
313/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
314/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
315#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
316#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
317
318#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
319
320#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
321#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
322#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
323
324#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
325
326/* Internal register offset for ADC analog watchdog threshold configuration */
327#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
328#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
329#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
330#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
331#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
332#if defined(ADC_VER_V5_V90)
333#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
334#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
335#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
336#endif /* ADC_VER_V5_V90 */
337
338/* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
339/* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
340#define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
341#define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
342
343/* Legacy literals */
344#define LL_ADC_AWD1_TR LL_ADC_AWD1
345#define LL_ADC_AWD2_TR LL_ADC_AWD2
346#define LL_ADC_AWD3_TR LL_ADC_AWD3
347
348/* Internal mask for ADC offset: */
349/* Internal register offset for ADC offset number configuration */
350#define ADC_OFR1_REGOFFSET (0x00000000UL)
351#define ADC_OFR2_REGOFFSET (0x00000001UL)
352#define ADC_OFR3_REGOFFSET (0x00000002UL)
353#define ADC_OFR4_REGOFFSET (0x00000003UL)
354#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
355
356
357/* ADC registers bits positions */
358#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
359#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
360#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
361#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
362#if defined(ADC_VER_V5_V90)
363#define ADC_CFGR_RES_BITOFFSET_POS_ADC3 (ADC3_CFGR_RES_Pos)
364#endif /* ADC_VER_V5_V90 */
365
366
367/* ADC registers bits groups */
368#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
369
370
371/* ADC internal channels related definitions */
372/* Internal voltage reference VrefInt */
373#if defined(ADC_VER_V5_3)
374#define VREFINT_CAL_ADDR ((uint16_t*) (0x8fff810UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
375 /* Address related to STM32H7A3 */
376#else /* ADC_VER_V5_90 || ADC_VER_V5_X */
377#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
378#endif /* ADC_VER_V5_3 */
379#define VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
380/* Temperature sensor */
381#if defined(ADC_VER_V5_3)
382#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x8fff814UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
383#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x8fff818UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
384 /* Addresses related to STM32H7A3 */
385#else /* ADC_VER_V5_90 || ADC_VER_V5_X */
386#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
387#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
388#endif /* ADC_VER_V5_3 */
389
390#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
391#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
392#define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
393
394/* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */
395#define ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL))
396#define ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL))
397#define ADC_LINEAR_CALIB_REG_3_ADDR ((uint32_t*) (0x1FF1EC08UL))
398#define ADC_LINEAR_CALIB_REG_4_ADDR ((uint32_t*) (0x1FF1EC0CUL))
399#define ADC_LINEAR_CALIB_REG_5_ADDR ((uint32_t*) (0x1FF1EC10UL))
400#define ADC_LINEAR_CALIB_REG_6_ADDR ((uint32_t*) (0x1FF1EC14UL))
401#define ADC_LINEAR_CALIB_REG_COUNT (6UL)
410#define LL_ADC_SetChannelPreSelection LL_ADC_SetChannelPreselection /* Alias of LL_ADC_SetChannelPreselection for backward compatibility. */
411
416/* Private macros ------------------------------------------------------------*/
430#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
431 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
432
438/* Exported types ------------------------------------------------------------*/
439#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
455typedef struct
456{
457 uint32_t CommonClock;
465 uint32_t Multimode;
470 uint32_t MultiDMATransfer;
475 uint32_t MultiTwoSamplingDelay;
480} LL_ADC_CommonInitTypeDef;
481
502typedef struct
503{
504 uint32_t Resolution;
509 uint32_t LeftBitShift;
512 uint32_t LowPowerMode;
517} LL_ADC_InitTypeDef;
518
538typedef struct
539{
540 uint32_t TriggerSource;
548 uint32_t SequencerLength;
553 uint32_t SequencerDiscont;
560 uint32_t ContinuousMode;
566 uint32_t DataTransferMode;
571 uint32_t Overrun;
577} LL_ADC_REG_InitTypeDef;
578
598typedef struct
599{
600 uint32_t TriggerSource;
608 uint32_t SequencerLength;
613 uint32_t SequencerDiscont;
620 uint32_t TrigAuto;
626} LL_ADC_INJ_InitTypeDef;
627
631#endif /* USE_FULL_LL_DRIVER */
632
633/* Exported constants --------------------------------------------------------*/
644#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
645#define LL_ADC_FLAG_EOC ADC_ISR_EOC
646#define LL_ADC_FLAG_EOS ADC_ISR_EOS
647#define LL_ADC_FLAG_OVR ADC_ISR_OVR
648#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
649#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC
650#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS
651#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF
652#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
653#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
654#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
655#define LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY
656#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST
657#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV
658#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST
659#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV
660#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST
661#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV
662#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST
663#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV
664#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST
665#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV
666#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST
667#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV
668#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST
669#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV
670#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST
671#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV
672#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST
673#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV
674#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST
675#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV
676#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST
677#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV
687#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
688#define LL_ADC_IT_EOC ADC_IER_EOCIE
689#define LL_ADC_IT_EOS ADC_IER_EOSIE
690#define LL_ADC_IT_OVR ADC_IER_OVRIE
691#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
692#define LL_ADC_IT_JEOC ADC_IER_JEOCIE
693#define LL_ADC_IT_JEOS ADC_IER_JEOSIE
694#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE
695#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE
696#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE
697#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE
706/* List of ADC registers intended to be used (most commonly) with */
707/* DMA transfer. */
708/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
709#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
710#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
719#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)
720#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )
721#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)
722#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)
723#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
724#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )
725#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
726#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )
727#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
728#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )
729#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
730#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
731#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
732#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
733#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
742/* Note: Other measurement paths to internal channels may be available */
743/* (connections to other peripherals). */
744/* If they are not listed below, they do not require any specific */
745/* path enable. In this case, Access to measurement path is done */
746/* only by selecting the corresponding ADC internal channel. */
747#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)
748#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
749#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)
750#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)
759#define LL_ADC_BOOST_MODE_6MHZ25 (0x00000000UL)
760#define LL_ADC_BOOST_MODE_12MHZ5 ( ADC_CR_BOOST_0)
761#define LL_ADC_BOOST_MODE_20MHZ ( ADC_CR_BOOST_1 )
762#define LL_ADC_BOOST_MODE_25MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 )
763#define LL_ADC_BOOST_MODE_50MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0)
772#define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET)
773#define LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
774#define LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN)
783#define LL_ADC_CALIB_LINEARITY_WORD1 (ADC_CR_LINCALRDYW1)
784#define LL_ADC_CALIB_LINEARITY_WORD2 (ADC_CR_LINCALRDYW2)
785#define LL_ADC_CALIB_LINEARITY_WORD3 (ADC_CR_LINCALRDYW3)
786#define LL_ADC_CALIB_LINEARITY_WORD4 (ADC_CR_LINCALRDYW4)
787#define LL_ADC_CALIB_LINEARITY_WORD5 (ADC_CR_LINCALRDYW5)
788#define LL_ADC_CALIB_LINEARITY_WORD6 (ADC_CR_LINCALRDYW6)
797#define LL_ADC_RESOLUTION_16B (0x00000000UL)
798#define LL_ADC_RESOLUTION_14B ( ADC_CFGR_RES_0)
799#define LL_ADC_RESOLUTION_12B ( ADC_CFGR_RES_1 )
800#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_1 | ADC_CFGR_RES_0)
802#if defined (ADC_VER_V5_X)
803#define LL_ADC_RESOLUTION_14B_OPT (ADC_CFGR_RES_2 | ADC_CFGR_RES_0)
804#define LL_ADC_RESOLUTION_12B_OPT (ADC_CFGR_RES_2 | ADC_CFGR_RES_1 )
805#endif
806
807#if defined (ADC_VER_V5_3) || defined(ADC_VER_V5_V90)
808#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0)
809#else
810#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2 )
814#endif
815#if defined(ADC_VER_V5_V90)
816#define LL_ADC_RESOLUTION_6B (ADC3_CFGR_RES_1 | ADC3_CFGR_RES_0)
817#endif /* ADC_VER_V5_V90 */
822#if defined(ADC_VER_V5_V90)
827#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)
828#define LL_ADC_DATA_ALIGN_LEFT (ADC3_CFGR_ALIGN)
833#endif /* ADC_VER_V5_V90 */
834
839#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL)
840#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0)
841#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1)
842#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
843#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2)
844#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)
845#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)
846#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
847#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3)
848#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0)
849#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1)
850#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
851#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2)
852#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)
853#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)
854#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)
863#define LL_ADC_LP_MODE_NONE (0x00000000UL)
864#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)
873#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET
874#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET
875#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET
876#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET
885#define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL)
886#define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSATE)
895#define LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL)
896#define LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1)
900#if defined(ADC_VER_V5_V90)
905#define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL)
906#define LL_ADC_OFFSET_SATURATION_ENABLE (ADC3_OFR1_SATEN)
915#define LL_ADC_OFFSET_DISABLE (0x00000000UL)
916#define LL_ADC_OFFSET_ENABLE (ADC3_OFR1_OFFSET1_EN)
920#if defined(ADC_VER_V5_V90)
925#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL)
926#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC3_OFR1_OFFSETPOS)
930#endif /* ADC_VER_V5_V90 */
931
932#endif /* ADC_VER_V5_V90 */
933
938#define LL_ADC_GROUP_REGULAR (0x00000001UL)
939#define LL_ADC_GROUP_INJECTED (0x00000002UL)
940#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)
949#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )
950#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )
951#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )
952#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )
953#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )
954#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )
955#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD )
956#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD )
957#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD )
958#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD )
959#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD)
960#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD)
961#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD)
962#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD)
963#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD)
964#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD)
965#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD)
966#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD)
967#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD)
968#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD)
969#if defined(ADC3)
970#if defined(ADC_VER_V5_V90)
971#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
972#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
973#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)
974#else
975#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH)
976#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
977#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
978#endif /* ADC_VER_V5_V90 */
979#else
981#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH)
982#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
983#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)
984#endif
985#define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)
986#define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
987#if defined(DAC2)
989#define LL_ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH)
990#endif
999#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)
1000#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1001#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1002#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1003#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1004#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1005#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1006#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1007#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1008#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1009#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1010#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1011#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1012#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1013#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1014#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1015#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1016#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1017#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1018#define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1019#define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1020#define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1021#if defined (TIM23)
1022#define LL_ADC_REG_TRIG_EXT_TIM23_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1023#endif /* TIM23 */
1024#if defined (TIM24)
1025#define LL_ADC_REG_TRIG_EXT_TIM24_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
1026#endif /* TIM24 */
1035#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)
1036#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )
1037#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)
1041#if defined(ADC_VER_V5_V90)
1046#define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL)
1047#define LL_ADC_REG_SAMPLING_MODE_BULB (ADC3_CFGR2_BULB)
1049#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC3_CFGR2_SMPTRIG)
1055#endif /* ADC_VER_V5_V90 */
1056
1061#define LL_ADC_REG_CONV_SINGLE (0x00000000UL)
1062#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)
1071#define LL_ADC_REG_DR_TRANSFER (0x00000000UL)
1072#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMNGT_0)
1073#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0)
1074#define LL_ADC_REG_DFSDM_TRANSFER (ADC_CFGR_DMNGT_1 )
1079#if defined(ADC_VER_V5_V90)
1085#define LL_ADC3_REG_DMA_TRANSFER_NONE (0x00000000UL)
1086#define LL_ADC3_REG_DMA_TRANSFER_LIMITED ( ADC3_CFGR_DMAEN)
1087#define LL_ADC3_REG_DMA_TRANSFER_UNLIMITED (ADC3_CFGR_DMACFG | ADC3_CFGR_DMAEN)
1091#endif /* ADC_VER_V5_V90 */
1092
1097#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)
1098#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)
1107#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)
1108#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
1109#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
1110#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
1111#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
1112#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
1113#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
1114#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
1115#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
1116#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
1117#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
1118#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
1119#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
1120#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
1121#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
1122#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
1131#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)
1132#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)
1133#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
1134#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
1135#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
1136#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
1137#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
1138#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
1139#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
1148#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
1149#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
1150#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
1151#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
1152#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
1153#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
1154#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
1155#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
1156#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
1157#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
1158#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
1159#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
1160#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
1161#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
1162#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
1163#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)
1172#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)
1173#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1174#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1175#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1176#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1177#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1178#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1179#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1180#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1181#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1182#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1183#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1184#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1185#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1186#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1187#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1188#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1189#if defined(HRTIM1)
1190#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1191#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1192#endif /* HRTIM1 */
1193#define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1194#define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1195#define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1196#define LL_ADC_INJ_TRIG_EXT_TIM23_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1197#define LL_ADC_INJ_TRIG_EXT_TIM24_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
1206#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)
1207#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )
1208#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)
1217#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)
1218#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)
1227#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
1228#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
1229#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
1238#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)
1239#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
1240#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
1241#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)
1250#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)
1251#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)
1260#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
1261#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
1262#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
1263#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)
1272#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL)
1273#define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0)
1274#define LL_ADC_SAMPLINGTIME_8CYCLES_5 ( ADC_SMPR2_SMP10_1 )
1275#define LL_ADC_SAMPLINGTIME_16CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
1276#define LL_ADC_SAMPLINGTIME_32CYCLES_5 (ADC_SMPR2_SMP10_2 )
1277#define LL_ADC_SAMPLINGTIME_64CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)
1278#define LL_ADC_SAMPLINGTIME_387CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )
1279#define LL_ADC_SAMPLINGTIME_810CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
1283#if defined(ADC_VER_V5_V90)
1288#define LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5 (0x00000000UL)
1289#define LL_ADC_SAMPLINGTIME_ADC3_6CYCLES_5 ( ADC_SMPR2_SMP10_0)
1290#define LL_ADC_SAMPLINGTIME_ADC3_12CYCLES_5 ( ADC_SMPR2_SMP10_1 )
1291#define LL_ADC_SAMPLINGTIME_ADC3_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
1292#define LL_ADC_SAMPLINGTIME_ADC3_47CYCLES_5 (ADC_SMPR2_SMP10_2 )
1293#define LL_ADC_SAMPLINGTIME_ADC3_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)
1294#define LL_ADC_SAMPLINGTIME_ADC3_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )
1295#define LL_ADC_SAMPLINGTIME_ADC3_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
1299#endif /* ADC_VER_V5_V90 */
1300
1305#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)
1306#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)
1307#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)
1316#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
1317#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)
1318#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)
1327#define LL_ADC_AWD_DISABLE (0x00000000UL)
1328#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )
1329#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )
1330#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )
1331#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1332#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1333#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1334#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1335#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1336#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1337#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1338#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1339#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1340#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1341#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1342#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1343#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1344#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1345#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1346#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1347#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1348#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1349#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1350#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1351#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1352#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1353#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1354#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1355#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1356#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1357#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1358#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1359#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1360#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1361#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1362#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1363#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1364#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1365#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1366#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1367#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1368#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1369#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1370#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1371#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1372#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1373#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1374#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1375#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1376#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1377#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1378#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1379#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1380#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1381#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1382#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1383#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1384#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1385#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1386#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1387#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1388#define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1389#define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1390#define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1391#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1392#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1393#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1394#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1395#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1396#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1397#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1398#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1399#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1400#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1401#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1402#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1403#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1404#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1405#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1414#define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL)
1415#define LL_ADC_AWD_THRESHOLD_LOW (0x0UL)
1419#if defined(ADC_VER_V5_V90)
1424#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL)
1425#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC3_TR1_AWDFILT_0)
1426#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC3_TR1_AWDFILT_1 )
1427#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)
1428#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC3_TR1_AWDFILT_2 )
1429#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0)
1430#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 )
1431#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)
1435#endif /* ADC_VER_V5_V90 */
1436
1441#define LL_ADC_OVS_DISABLE (0x00000000UL)
1442#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)
1443#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)
1444#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )
1445#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
1454#define LL_ADC_OVS_REG_CONT (0x00000000UL)
1455#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)
1459#if defined(ADC_VER_V5_V90)
1464#define LL_ADC_OVS_RATIO_2 (0x00000000UL)
1465#define LL_ADC_OVS_RATIO_4 ( ADC3_CFGR2_OVSR_0)
1466#define LL_ADC_OVS_RATIO_8 ( ADC3_CFGR2_OVSR_1 )
1467#define LL_ADC_OVS_RATIO_16 ( ADC3_CFGR2_OVSR_1 | ADC3_CFGR2_OVSR_0)
1468#define LL_ADC_OVS_RATIO_32 (ADC3_CFGR2_OVSR_2 )
1469#define LL_ADC_OVS_RATIO_64 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_0)
1470#define LL_ADC_OVS_RATIO_128 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_1 )
1471#define LL_ADC_OVS_RATIO_256 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_1 | ADC3_CFGR2_OVSR_0)
1475#endif /* ADC_VER_V5_V90 */
1476
1481#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL)
1482#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)
1483#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )
1484#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
1485#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )
1486#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
1487#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )
1488#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
1489#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )
1490#define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0)
1491#define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 )
1492#define LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
1501#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL)
1502#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 )
1503#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
1504#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)
1505#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)
1506#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0)
1507#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 )
1508#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
1517#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL)
1518#define LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 )
1519#define LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0)
1528#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL)
1529#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 ( ADC_CCR_DELAY_0)
1530#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 ( ADC_CCR_DELAY_1 )
1531#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1532#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1533#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 ( ADC_CCR_DELAY_2 )
1534#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1535#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_3 )
1536#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)
1537#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1538#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1539#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_3 )
1540#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 )
1549#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST)
1550#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV )
1551#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)
1567/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1568/* not timeout values. */
1569/* Timeout values for ADC operations are dependent to device clock */
1570/* configuration (system clock versus ADC clock), */
1571/* and therefore must be defined in user application. */
1572/* Indications for estimation of ADC timeout delays, for this */
1573/* STM32 series: */
1574/* - ADC calibration time: maximum delay is 16384/fADC. */
1575/* (refer to device datasheet, parameter "tCAL") */
1576/* - ADC enable time: maximum delay is 1 conversion cycle. */
1577/* (refer to device datasheet, parameter "tSTAB") */
1578/* - ADC disable time: maximum delay should be a few ADC clock cycles */
1579/* - ADC stop conversion time: maximum delay should be a few ADC clock */
1580/* cycles */
1581/* - ADC conversion time: duration depending on ADC clock and ADC */
1582/* configuration. */
1583/* (refer to device reference manual, section "Timing") */
1584
1585/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1586/* Delay set to maximum value (refer to device datasheet, */
1587/* parameter "tADCVREG_STUP"). */
1588/* Unit: us */
1589#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)
1591/* Delay for internal voltage reference stabilization time. */
1592/* Delay set to maximum value (refer to device datasheet, */
1593/* parameter "ts_vrefint"). */
1594/* Unit: us */
1595#define LL_ADC_DELAY_VREFINT_STAB_US (5UL)
1597/* Delay for temperature sensor stabilization time. */
1598/* Literal set to maximum value (refer to device datasheet, */
1599/* parameter "tSTART_RUN"). */
1600/* Unit: us */
1601#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL)
1603/* Delay required between ADC end of calibration and ADC enable. */
1604/* Note: On this STM32 series, a minimum number of ADC clock cycles */
1605/* are required between ADC end of calibration and ADC enable. */
1606/* Wait time can be computed in user application by waiting for the */
1607/* equivalent number of CPU cycles, by taking into account */
1608/* ratio of CPU clock versus ADC clock prescalers. */
1609/* Unit: ADC clock cycles. */
1610#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL)
1612/* Fixed timeout value for ADC linearity word bit set/clear delay. */
1613/* Values defined to be higher than worst cases: low clock frequency, */
1614/* maximum prescalers. */
1615/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */
1616/* according to Data sheet), linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB */
1617/* 6 / 4577 = 1,311ms */
1618/* At maximum CPU speed (400 MHz), this means */
1619/* 3.58 * 400 MHz = 524400 CPU cycles */
1620#define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL)
1631/* Exported macro ------------------------------------------------------------*/
1649#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1650
1657#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1667#if defined(ADC_VER_V5_V90)
1684#define __LL_ADC12_RESOLUTION_TO_ADC3(__ADC_RESOLUTION__) \
1685 ( \
1686 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
1687 ?(0x00000000UL) \
1688 : \
1689 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
1690 ?(ADC_CFGR_RES_0) \
1691 : \
1692 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
1693 ?(ADC_CFGR_RES_1) \
1694 : \
1695 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
1696 ?((ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) \
1697 :(0x00000000UL) \
1698 )
1699
1700#endif /* ADC_VER_V5_V90 */
1701
1744#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1745 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
1746 ? ( \
1747 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1748 ) \
1749 : \
1750 ( \
1751 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1752 ) \
1753 )
1754
1797#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1798 (((__DECIMAL_NB__) <= 9UL) \
1799 ? ( \
1800 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1801 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1802 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1803 ) \
1804 : \
1805 ( \
1806 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1807 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1808 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1809 ) \
1810 )
1811
1863#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1864 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1865
1932#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1933 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1934
1961#if defined(ADC3)
1962#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1963 ((((__ADC_INSTANCE__) == ADC2) \
1964 &&( \
1965 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1966 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1967 ) \
1968 ) \
1969 || \
1970 (((__ADC_INSTANCE__) == ADC3) \
1971 &&( \
1972 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1973 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1974 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1975 ) \
1976 ) \
1977 )
1978#else
1979#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1980 ((((__ADC_INSTANCE__) == ADC2) \
1981 &&( \
1982 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1983 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) || \
1984 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1985 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1986 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1987 ) \
1988 ) \
1989 )
1990#endif
1991
2124#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2125 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2126 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2127 : \
2128 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2129 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
2130 : \
2131 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2132 )
2133
2154#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2155 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2156
2177#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) \
2178 ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2179
2193#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2194 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2195
2209#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2210 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2211
2224#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2225 ( ( ((__ADCx__) == ADC2) \
2226 )? \
2227 (ADC1) \
2228 : \
2229 (__ADCx__) \
2230 )
2231
2242#if defined(ADC3_COMMON)
2243#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2244 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
2245 ? ( \
2246 (ADC12_COMMON) \
2247 ) \
2248 : \
2249 ( \
2250 (ADC3_COMMON) \
2251 ) \
2252 )
2253#else
2254#define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
2255#endif
2256
2274#if defined(ADC3_COMMON)
2275#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2276 (((__ADCXY_COMMON__) == ADC12_COMMON) \
2277 ? ( \
2278 (LL_ADC_IsEnabled(ADC1) | \
2279 LL_ADC_IsEnabled(ADC2) ) \
2280 ) \
2281 : \
2282 ( \
2283 (LL_ADC_IsEnabled(ADC3)) \
2284 ) \
2285 )
2286#else
2287#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2288 (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
2289#endif
2290
2305#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2306 (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2307
2308#if defined(ADC_VER_V5_V90)
2322#define __LL_ADC3_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2323 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL)))
2324#endif /* ADC_VER_V5_V90 */
2345#if defined(ADC_VER_V5_X) || defined(ADC_VER_V5_V90)
2346#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2347 __ADC_RESOLUTION_CURRENT__,\
2348 __ADC_RESOLUTION_TARGET__) \
2349( (__ADC_RESOLUTION_CURRENT__ == LL_ADC_RESOLUTION_8B) \
2350 ?( \
2351 ((__DATA__) \
2352 << (((__ADC_RESOLUTION_CURRENT__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2353 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2354 ) \
2355 : \
2356 ( \
2357 (__ADC_RESOLUTION_TARGET__ == LL_ADC_RESOLUTION_8B) \
2358 ? ( \
2359 ((__DATA__) \
2360 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2361 >> (((__ADC_RESOLUTION_TARGET__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2362 ) \
2363 :\
2364 (\
2365 ((__DATA__) \
2366 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2367 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2368 ) \
2369 )\
2370 )
2371
2372
2373#else /* defined(ADC_VER_V5_3) */
2374#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2375 __ADC_RESOLUTION_CURRENT__,\
2376 __ADC_RESOLUTION_TARGET__) \
2377( (__ADC_RESOLUTION_CURRENT__ == LL_ADC_RESOLUTION_8B) \
2378 ?( \
2379 ((__DATA__) \
2380 << (((__ADC_RESOLUTION_CURRENT__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2381 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2382 ) \
2383 : \
2384 ( \
2385 (__ADC_RESOLUTION_TARGET__ == LL_ADC_RESOLUTION_8B) \
2386 ? ( \
2387 ((__DATA__) \
2388 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2389 >> (((__ADC_RESOLUTION_TARGET__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2390 ) \
2391 :\
2392 (\
2393 ((__DATA__) \
2394 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2395 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2396 ) \
2397 )\
2398 )
2399
2400#endif
2401
2402#if defined(ADC_VER_V5_V90)
2421#define __LL_ADC_CONVERT_DATA_RESOLUTION_ADC3(__DATA__,\
2422 __ADC_RESOLUTION_CURRENT__,\
2423 __ADC_RESOLUTION_TARGET__) \
2424 (((__DATA__) \
2425 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL))) \
2426 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL)) \
2427 )
2428#endif /* ADC_VER_V5_V90 */
2446#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2447 __ADC_DATA__,\
2448 __ADC_RESOLUTION__) \
2449 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2450 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2451 )
2452
2479#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2480 __ADC_RESOLUTION__) \
2481 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2482 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2483 (__ADC_RESOLUTION__), \
2484 LL_ADC_RESOLUTION_16B) \
2485 )
2486
2533#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2534 __TEMPSENSOR_ADC_DATA__,\
2535 __ADC_RESOLUTION__) \
2536 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2537 (__ADC_RESOLUTION__), \
2538 LL_ADC_RESOLUTION_16B) \
2539 * (__VREFANALOG_VOLTAGE__)) \
2540 / TEMPSENSOR_CAL_VREFANALOG) \
2541 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2542 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2543 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2544 ) + TEMPSENSOR_CAL1_TEMP \
2545 )
2546
2592#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2593 __TEMPSENSOR_TYP_CALX_V__,\
2594 __TEMPSENSOR_CALX_TEMP__,\
2595 __VREFANALOG_VOLTAGE__,\
2596 __TEMPSENSOR_ADC_DATA__,\
2597 __ADC_RESOLUTION__) \
2598 ((( ( \
2599 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2600 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2601 * 1000UL) \
2602 - \
2603 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2604 * 1000UL) \
2605 ) \
2606 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2607 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2608 )
2609
2619/* Exported functions --------------------------------------------------------*/
2660__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2661{
2662 uint32_t data_reg_addr;
2663
2664 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2665 {
2666 /* Retrieve address of register DR */
2667 data_reg_addr = (uint32_t) & (ADCx->DR);
2668 }
2669 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2670 {
2671 /* Retrieve address of register CDR */
2672 data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2673 }
2674
2675 return data_reg_addr;
2676}
2677
2721__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2722{
2723 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2724}
2725
2749__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2750{
2751 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2752}
2753
2789__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2790{
2791 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
2792}
2793
2811__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2812{
2813 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2814}
2815
2846__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2847{
2848 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
2849}
2850
2870__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2871{
2872 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2873}
2874
2918__STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2919{
2920#if defined(ADC_VER_V5_V90)
2921 MODIFY_REG(ADCx->CALFACT_RES13,
2922 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2923 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2924#else
2925 MODIFY_REG(ADCx->CALFACT,
2926 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2927 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2928#endif /* ADC_VER_V5_V90 */
2929}
2930
2949__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
2950{
2951 /* Retrieve bits with position in register depending on parameter */
2952 /* "SingleDiff". */
2953 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2954 /* containing other bits reserved for other purpose. */
2955#if defined(ADC_VER_V5_V90)
2956 return (uint32_t)(READ_BIT(ADCx->CALFACT_RES13, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2957#else
2958 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2959#endif /* ADC_VER_V5_V90 */
2960}
2961
2984__STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)
2985{
2986#if defined(ADC_VER_V5_V90)
2987 if (ADCx != ADC3)
2988 {
2989 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
2990 MODIFY_REG(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
2991 MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
2992 while ((READ_BIT(ADCx->CR, LinearityWord) == 0UL) && (timeout_cpu_cycles > 0UL))
2993 {
2994 timeout_cpu_cycles--;
2995 }
2996 }
2997#else
2998 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
2999 MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
3000 MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
3001 while ((READ_BIT(ADCx->CR, LinearityWord) == 0UL) && (timeout_cpu_cycles > 0UL))
3002 {
3003 timeout_cpu_cycles--;
3004 }
3005#endif /* ADC_VER_V5_V90 */
3006}
3007
3024__STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
3025{
3026 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
3027 CLEAR_BIT(ADCx->CR, LinearityWord);
3028 while ((READ_BIT(ADCx->CR, LinearityWord) != 0UL) && (timeout_cpu_cycles > 0UL))
3029 {
3030 timeout_cpu_cycles--;
3031 }
3032#if defined(ADC_VER_V5_V90)
3033 return (uint32_t)(READ_BIT(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT));
3034#else
3035 return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));
3036#endif /* ADC_VER_V5_V90 */
3037}
3056__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
3057{
3058#if defined(ADC_VER_V5_3)
3059
3060 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3061
3062#elif defined(ADC_VER_V5_V90)
3063 if (ADCx == ADC3)
3064 {
3065 MODIFY_REG(ADCx->CFGR, ADC3_CFGR_RES, ((__LL_ADC12_RESOLUTION_TO_ADC3(Resolution) & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL));
3066 }
3067 else
3068 {
3069 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
3070 {
3071 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3072 }
3073 else /* Rev.V */
3074 {
3075 if (LL_ADC_RESOLUTION_8B == Resolution)
3076 {
3077 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);
3078 }
3079 else
3080 {
3081 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3082 }
3083 }
3084 }
3085#else /* ADC_VER_V5_V90 */
3086 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
3087 {
3088 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3089 }
3090 else /* Rev.V */
3091 {
3092 if (LL_ADC_RESOLUTION_8B == Resolution)
3093 {
3094 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);
3095 }
3096 else
3097 {
3098 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3099 }
3100 }
3101
3102#endif /* ADC_VER_V5_X*/
3103}
3104
3121__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
3122{
3123#if defined (ADC_VER_V5_3)
3124
3125 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3126
3127#elif defined(ADC_VER_V5_V90)
3128 if (ADCx == ADC3)
3129 {
3130 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC3_CFGR_RES));
3131 }
3132 else
3133 {
3134 if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)
3135 {
3136 return (LL_ADC_RESOLUTION_8B);
3137 }
3138 else
3139 {
3140 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3141 }
3142 }
3143
3144#else /* ADC_VER_V5_V90 */
3145 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
3146 {
3147 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3148 }
3149 else /* Rev.V */
3150 {
3151 if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)
3152 {
3153 return (LL_ADC_RESOLUTION_8B);
3154 }
3155 else
3156 {
3157 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3158 }
3159 }
3160
3161#endif /* ADC_VER_V5_X */
3162}
3163
3215__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
3216{
3217 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
3218}
3219
3266__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
3267{
3268 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
3269}
3270
3302__STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
3303{
3304#if defined(ADC_VER_V5_V90)
3305 if (ADCx != ADC3)
3306 {
3307 /* ADC channels preselection */
3308 ADCx->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL));
3309 }
3310#else
3311 /* ADC channels preselection */
3312 ADCx->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL));
3313#endif /* ADC_VER_V5_V90 */
3314}
3315
3347__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
3348{
3349#if defined(ADC_VER_V5_V90)
3350 if (ADCx != ADC3)
3351 {
3352 /* Gets preselected ADC channel */
3353 return (uint32_t)(READ_BIT(ADCx->PCSEL_RES0, 1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL)));
3354 }
3355 else
3356 {
3357 return 0UL;
3358 }
3359#else
3360 /* Gets preselected ADC channel */
3361 return (uint32_t)(READ_BIT(ADCx->PCSEL, 1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL)));
3362#endif /* ADC_VER_V5_V90 */
3363}
3364
3438__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3439{
3440 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3441#if defined(ADC_VER_V5_V90)
3442 if (ADCx == ADC3)
3443 {
3444 MODIFY_REG(*preg,
3445 ADC3_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3446 ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3447 }
3448 else
3449#endif /* ADC_VER_V5_V90 */
3450 {
3451 MODIFY_REG(*preg,
3452 ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3453 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3454 }
3455}
3456
3520__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
3521{
3522 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3523
3524 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3525}
3526
3546__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
3547{
3548 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3549
3550 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3551}
3552
3553
3569__STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
3570{
3571 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
3572}
3573
3588__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety)
3589{
3590 return (uint32_t)((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));
3591}
3592
3611__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
3612{
3613#if defined(ADC_VER_V5_V90)
3614 if (ADCx == ADC3)
3615 {
3616 /* Function not available on this instance */
3617 }
3618 else
3619#endif /* ADC_VER_V5_V90 */
3620 {
3621 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3622 MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
3623 }
3624}
3625
3643__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
3644{
3645#if defined(ADC_VER_V5_V90)
3646 if (ADCx == ADC3)
3647 {
3648 /* Function not available on this instance */
3649 return 0UL;
3650 }
3651 else
3652#endif /* ADC_VER_V5_V90 */
3653 {
3654 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3655 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
3656 }
3657}
3658
3659#if defined(ADC_VER_V5_V90)
3682__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
3683{
3684 if (ADCx == ADC3)
3685 {
3686 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3687
3688 MODIFY_REG(*preg,
3689 ADC3_OFR1_SATEN,
3690 OffsetSaturation);
3691 }
3692}
3693
3711__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
3712{
3713 if (ADCx == ADC3)
3714 {
3715 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3716
3717 return (uint32_t) READ_BIT(*preg, ADC3_OFR1_SATEN);
3718 }else
3719 {
3720 return 0UL;
3721 }
3722}
3723
3746__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
3747{
3748 if (ADCx == ADC3)
3749 {
3750 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3751
3752 MODIFY_REG(*preg,
3753 ADC3_OFR1_OFFSETPOS,
3754 OffsetSign);
3755 }
3756}
3757
3775__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety)
3776{
3777 if (ADCx == ADC3)
3778 {
3779 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3780
3781 return (uint32_t) READ_BIT(*preg, ADC3_OFR1_OFFSETPOS);
3782 }
3783 else
3784 {
3785 return 0UL;
3786 }
3787}
3788
3815__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3816{
3817 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3818 if (ADCx == ADC3)
3819 {
3820 MODIFY_REG(*preg,
3821 ADC3_OFR1_OFFSET1_EN,
3822 OffsetState);
3823 }
3824 else
3825 {
3826 MODIFY_REG(*preg,
3827 ADC_OFR1_SSATE,
3828 OffsetState);
3829 }
3830}
3831
3849__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
3850{
3851 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3852 if (ADCx == ADC3)
3853 {
3854 return (uint32_t) READ_BIT(*preg, ADC3_OFR1_OFFSET1_EN);
3855 }
3856 else
3857 {
3858 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
3859 }
3860}
3861
3862#endif /* ADC_VER_V5_V90 */
3863
3917__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3918{
3919 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3920}
3921
3961__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
3962{
3963 __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3964
3965 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3966 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3967 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3968
3969 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3970 /* to match with triggers literals definition. */
3971 return ((TriggerSource
3972 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
3973 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
3974 );
3975}
3976
3988__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3989{
3990 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3991}
3992
4008__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4009{
4010 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
4011}
4012
4023__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
4024{
4025 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
4026}
4027
4028#if defined(ADC_VER_V5_V90)
4047__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
4048{
4049 if (ADCx != ADC3)
4050 {
4051 /* Function not available on this instance */
4052 }
4053 else
4054 {
4055 MODIFY_REG(ADCx->CFGR2, ADC3_CFGR2_BULB | ADC3_CFGR2_SMPTRIG, SamplingMode);
4056 }
4057}
4058#endif /* ADC_VER_V5_V90 */
4059
4114__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4115{
4116 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
4117}
4118
4168__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
4169{
4170 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
4171}
4172
4200__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4201{
4202 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
4203}
4204
4223__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
4224{
4225 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
4226}
4227
4315__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4316{
4317 /* Set bits with content of parameter "Channel" with bits position */
4318 /* in register and register position depending on parameter "Rank". */
4319 /* Parameters "Rank" and "Channel" are used with masks because containing */
4320 /* other bits reserved for other purpose. */
4321 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4322
4323 MODIFY_REG(*preg,
4324 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4325 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
4326}
4327
4417__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4418{
4419 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4420
4421 return (uint32_t)((READ_BIT(*preg,
4422 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4423 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4424 );
4425}
4426
4446__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
4447{
4448 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
4449}
4450
4463__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
4464{
4465 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
4466}
4479__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
4480{
4481 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);
4482}
4483
4484#if defined(ADC_VER_V5_V90)
4491__STATIC_INLINE void LL_ADC_EnableDMAReq (ADC_TypeDef *ADCx)
4492{
4493 SET_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN);
4494}
4495
4496__STATIC_INLINE void LL_ADC_DisableDMAReq(ADC_TypeDef *ADCx)
4497{
4498 CLEAR_BIT (ADCx->CFGR, ADC3_CFGR_DMAEN);
4499}
4500
4501__STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (ADC_TypeDef *ADCx)
4502{
4503 return ((READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN) == (ADC3_CFGR_DMAEN)) ? 1UL : 0UL);
4504}
4540__STATIC_INLINE void LL_ADC_REG_SetDMATransferMode(ADC_TypeDef *ADCx, uint32_t DMATransfer)
4541{
4542 if (ADCx == ADC3)
4543 {
4544 MODIFY_REG(ADCx->CFGR, ADC3_CFGR_DMAEN | ADC3_CFGR_DMACFG, DMATransfer);
4545 }
4546}
4547
4578__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx)
4579{
4580 if (ADCx == ADC3)
4581 {
4582 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN | ADC3_CFGR_DMACFG));
4583 }
4584 else
4585 {
4586 return 0UL;
4587 }
4588}
4589
4590#endif /* ADC_VER_V5_V90 */
4591
4607__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx)
4608{
4609 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT));
4610}
4611
4612
4633__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
4634{
4635 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
4636}
4637
4647__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
4648{
4649 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
4650}
4651
4705__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4706{
4707 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
4708}
4709
4749__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
4750{
4751 __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4752
4753 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4754 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4755 uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4756
4757 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4758 /* to match with triggers literals definition. */
4759 return ((TriggerSource
4760 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
4761 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
4762 );
4763}
4764
4776__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
4777{
4778 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
4779}
4780
4796__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4797{
4798 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4799}
4800
4811__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
4812{
4813 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4814}
4815
4837__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4838{
4839 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4840}
4841
4858__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
4859{
4860 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4861}
4862
4876__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4877{
4878 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4879}
4880
4891__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
4892{
4893 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4894}
4895
4954__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4955{
4956 /* Set bits with content of parameter "Channel" with bits position */
4957 /* in register depending on parameter "Rank". */
4958 /* Parameters "Rank" and "Channel" are used with masks because containing */
4959 /* other bits reserved for other purpose. */
4960 MODIFY_REG(ADCx->JSQR,
4961 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4962 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4963}
4964
5026__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
5027{
5028 return (uint32_t)((READ_BIT(ADCx->JSQR,
5029 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
5030 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
5031 );
5032}
5033
5064__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
5065{
5066 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
5067}
5068
5078__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
5079{
5080 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
5081}
5082
5124__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
5125{
5126 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
5127}
5128
5139__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
5140{
5141 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
5142}
5143
5340__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
5341 uint32_t TriggerSource,
5342 uint32_t ExternalTriggerEdge,
5343 uint32_t SequencerNbRanks,
5344 uint32_t Rank1_Channel,
5345 uint32_t Rank2_Channel,
5346 uint32_t Rank3_Channel,
5347 uint32_t Rank4_Channel)
5348{
5349 /* Set bits with content of parameter "Rankx_Channel" with bits position */
5350 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
5351 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
5352 /* because containing other bits reserved for other purpose. */
5353 /* If parameter "TriggerSource" is set to SW start, then parameter */
5354 /* "ExternalTriggerEdge" is discarded. */
5355 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
5356 MODIFY_REG(ADCx->JSQR,
5357 ADC_JSQR_JEXTSEL |
5358 ADC_JSQR_JEXTEN |
5359 ADC_JSQR_JSQ4 |
5360 ADC_JSQR_JSQ3 |
5361 ADC_JSQR_JSQ2 |
5362 ADC_JSQR_JSQ1 |
5363 ADC_JSQR_JL,
5364 (TriggerSource & ADC_JSQR_JEXTSEL) |
5365 (ExternalTriggerEdge * (is_trigger_not_sw)) |
5366 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5367 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5368 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5369 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5370 SequencerNbRanks
5371 );
5372}
5373
5471__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
5472{
5473 /* Set bits with content of parameter "SamplingTime" with bits position */
5474 /* in register and register position depending on parameter "Channel". */
5475 /* Parameter "Channel" is used with masks because containing */
5476 /* other bits reserved for other purpose. */
5477 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5478
5479 MODIFY_REG(*preg,
5480 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
5481 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
5482}
5483
5556__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
5557{
5558 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5559
5560 return (uint32_t)(READ_BIT(*preg,
5561 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
5562 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
5563 );
5564}
5565
5617__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
5618{
5619#if defined(ADC_VER_V5_V90)
5620 /* Bits of channels in single or differential mode are set only for */
5621 /* differential mode (for single mode, mask of bits allowed to be set is */
5622 /* shifted out of range of bits of channels in single or differential mode. */
5623 if (ADCx == ADC3)
5624 {
5625 MODIFY_REG(ADCx->LTR2_DIFSEL,
5626 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5627 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5628 }
5629 else
5630 {
5631 MODIFY_REG(ADCx->DIFSEL_RES12,
5632 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5633 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5634 }
5635#else /* ADC_VER_V5_V90 */
5636 /* Bits of channels in single or differential mode are set only for */
5637 /* differential mode (for single mode, mask of bits allowed to be set is */
5638 /* shifted out of range of bits of channels in single or differential mode. */
5639 MODIFY_REG(ADCx->DIFSEL,
5640 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5641 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5642#endif /* ADC_VER_V5_V90 */
5643}
5644
5688__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
5689{
5690#if defined(ADC_VER_V5_V90)
5691 return (uint32_t)(READ_BIT(ADCx->DIFSEL_RES12, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5692#else
5693 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5694#endif /* ADC_VER_V5_V90 */
5695}
5696
5837__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5838{
5839 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5840 /* in register and register position depending on parameter "AWDy". */
5841 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5842 /* containing other bits reserved for other purpose. */
5843 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5844 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5845
5846 MODIFY_REG(*preg,
5847 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5848 AWDChannelGroup & AWDy);
5849}
5850
5976__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
5977{
5978 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5979 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5980
5981 uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5982
5983 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
5984 /* (parameter value LL_ADC_AWD_DISABLE). */
5985 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5986 /* or a single channel. */
5987 if (AnalogWDMonitChannels != 0UL)
5988 {
5989 if (AWDy == LL_ADC_AWD1)
5990 {
5991 if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
5992 {
5993 /* AWD monitoring a group of channels */
5994 AnalogWDMonitChannels = ((AnalogWDMonitChannels
5995 | (ADC_AWD_CR23_CHANNEL_MASK)
5996 )
5997 & (~(ADC_CFGR_AWD1CH))
5998 );
5999 }
6000 else
6001 {
6002 /* AWD monitoring a single channel */
6003 AnalogWDMonitChannels = (AnalogWDMonitChannels
6004 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
6005 );
6006 }
6007 }
6008 else
6009 {
6010 if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
6011 {
6012 /* AWD monitoring a group of channels */
6013 AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
6014 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
6015 );
6016 }
6017 else
6018 {
6019 /* AWD monitoring a single channel */
6020 /* AWD monitoring a group of channels */
6021 AnalogWDMonitChannels = (AnalogWDMonitChannels
6022 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
6023 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
6024 );
6025 }
6026 }
6027 }
6028
6029 return AnalogWDMonitChannels;
6030}
6031
6085__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
6086{
6087#if defined(ADC_VER_V5_V90)
6088 if (ADCx == ADC3)
6089 {
6090 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6091 /* position in register and register position depending on parameters */
6092 /* "AWDThresholdsHighLow" and "AWDy". */
6093 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6094 /* containing other bits reserved for other purpose. */
6095 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6096
6097 MODIFY_REG(*preg,
6098 AWDThresholdsHighLow,
6099 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
6100 }
6101 else
6102 {
6103 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6104 /* position in register and register position depending on parameters */
6105 /* "AWDThresholdsHighLow" and "AWDy". */
6106 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6107 /* containing other bits reserved for other purpose. */
6108 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6109 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6110 + (AWDThresholdsHighLow));
6111
6112 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
6113 }
6114#else
6115 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6116 /* position in register and register position depending on parameters */
6117 /* "AWDThresholdsHighLow" and "AWDy". */
6118 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6119 /* containing other bits reserved for other purpose. */
6120 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6121 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6122 + (AWDThresholdsHighLow));
6123
6124 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
6125#endif /* ADC_VER_V5_V90 */
6126}
6127
6151__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
6152{
6153#if defined(ADC_VER_V5_V90)
6154 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6155 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6156 + (AWDThresholdsHighLow));
6157
6158 return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
6159#else
6160 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6161 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6162 + (AWDThresholdsHighLow));
6163
6164 return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
6165#endif /* ADC_VER_V5_V90 */
6166}
6167
6168#if defined(ADC_VER_V5_V90)
6169
6214__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
6215{
6216 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
6217 /* position in register and register position depending on parameter */
6218 /* "AWDy". */
6219 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
6220 /* containing other bits reserved for other purpose. */
6221 if (ADCx == ADC3)
6222 {
6223 uint32_t __IO *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6224
6225 MODIFY_REG(*preg,
6226 ADC3_TR1_HT1 | ADC3_TR1_LT1,
6227 (AWDThresholdHighValue << ADC3_TR1_HT1_Pos) | AWDThresholdLowValue);
6228 }
6229 else
6230 {
6231 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6232 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6233 + (LL_ADC_AWD_THRESHOLD_LOW));
6234 __IO uint32_t *preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6235 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6236 + (LL_ADC_AWD_THRESHOLD_HIGH));
6237
6238 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdLowValue);
6239 MODIFY_REG(*preg2, ADC_HTR_HT, AWDThresholdHighValue);
6240 }
6241}
6242
6243
6268__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
6269{
6270 if (ADCx == ADC3)
6271 {
6272 /* Prevent unused argument(s) compilation warning */
6273 (void)(AWDy);
6274 MODIFY_REG(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT, FilteringConfig);
6275 }
6276}
6277
6297__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy)
6298{
6299 if (ADCx == ADC3)
6300 {
6301 /* Prevent unused argument(s) compilation warning */
6302 (void)(AWDy);
6303 return (uint32_t)(READ_BIT(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT));
6304 }
6305 else
6306 {
6307 /* Function not available on this instance, return 0 */
6308 return 0UL;
6309 }
6310}
6311#endif /* ADC_VER_V5_V90 */
6346__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
6347{
6348 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
6349}
6350
6371__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
6372{
6373 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
6374}
6375
6398__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
6399{
6400 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
6401}
6402
6417__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
6418{
6419 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
6420}
6421
6460__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
6461{
6462#if defined(ADC_VER_V5_V90)
6463 if(ADCx==ADC3)
6464 {
6465 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC3_CFGR2_OVSR), (Shift | Ratio));
6466 }
6467 else
6468 {
6469 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
6470 }
6471#else
6472
6473 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
6474
6475#endif /* ADC_VER_V5_V90 */
6476}
6477
6494__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
6495{
6496#if defined(ADC_VER_V5_V90)
6497 if(ADCx==ADC3)
6498 {
6499 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC3_CFGR2_OVSR));
6500 }
6501 else
6502 {
6503 return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
6504 }
6505#else
6506
6507 return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
6508
6509#endif /* ADC_VER_V5_V90 */
6510}
6511
6531__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
6532{
6533 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
6534}
6535
6560__STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)
6561{
6562#if defined(ADC_VER_V5_V90)
6563 if (ADCx != ADC3)
6564 {
6565 MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
6566 }
6567#else /* ADC_VER_V5_V90 */
6568 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
6569 {
6570 MODIFY_REG(ADCx->CR, ADC_CR_BOOST_0, (BoostMode >> 2UL));
6571 }
6572 else /* Cut 2.x */
6573 {
6574 MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
6575 }
6576#endif /* ADC_VER_V5_V90 */
6577}
6578
6579
6590__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx)
6591{
6592 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
6593 {
6594 return (uint32_t)READ_BIT(ADCx->CR, ADC_CR_BOOST_0);
6595 }
6596 else /* Cut 2.x */
6597 {
6598 return ((READ_BIT(ADCx->CR, ADC_CR_BOOST) == (ADC_CR_BOOST)) ? 1UL : 0UL);
6599 }
6600}
6601
6628__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
6629{
6630 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
6631}
6632
6652__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
6653{
6654 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
6655}
6656
6700__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
6701{
6702 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);
6703}
6704
6743__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
6744{
6745 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
6746}
6747
6788__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
6789{
6790 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
6791}
6792
6821__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
6822{
6823 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
6824}
6825
6847__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
6848{
6849 /* Note: Write register with some additional bits forced to state reset */
6850 /* instead of modifying only the selected bit for this function, */
6851 /* to not interfere with bits with HW property "rs". */
6852 MODIFY_REG(ADCx->CR,
6853 ADC_CR_BITS_PROPERTY_RS,
6854 ADC_CR_DEEPPWD);
6855}
6856
6870__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
6871{
6872 /* Note: Write register with some additional bits forced to state reset */
6873 /* instead of modifying only the selected bit for this function, */
6874 /* to not interfere with bits with HW property "rs". */
6875 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
6876}
6877
6884__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
6885{
6886 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
6887}
6888
6903__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
6904{
6905 /* Note: Write register with some additional bits forced to state reset */
6906 /* instead of modifying only the selected bit for this function, */
6907 /* to not interfere with bits with HW property "rs". */
6908 MODIFY_REG(ADCx->CR,
6909 ADC_CR_BITS_PROPERTY_RS,
6910 ADC_CR_ADVREGEN);
6911}
6912
6922__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
6923{
6924 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
6925}
6926
6933__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
6934{
6935 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
6936}
6937
6954__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6955{
6956 /* Note: Write register with some additional bits forced to state reset */
6957 /* instead of modifying only the selected bit for this function, */
6958 /* to not interfere with bits with HW property "rs". */
6959 MODIFY_REG(ADCx->CR,
6960 ADC_CR_BITS_PROPERTY_RS,
6961 ADC_CR_ADEN);
6962}
6963
6974__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6975{
6976 /* Note: Write register with some additional bits forced to state reset */
6977 /* instead of modifying only the selected bit for this function, */
6978 /* to not interfere with bits with HW property "rs". */
6979 MODIFY_REG(ADCx->CR,
6980 ADC_CR_BITS_PROPERTY_RS,
6981 ADC_CR_ADDIS);
6982}
6983
6993__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
6994{
6995 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6996}
6997
7004__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
7005{
7006 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
7007}
7008
7042__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)
7043{
7044 /* Note: Write register with some additional bits forced to state reset */
7045 /* instead of modifying only the selected bit for this function, */
7046 /* to not interfere with bits with HW property "rs". */
7047 MODIFY_REG(ADCx->CR,
7048 ADC_CR_ADCALLIN | ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
7049 ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK) | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
7050}
7051
7058__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
7059{
7060 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
7061}
7062
7090__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
7091{
7092 /* Note: Write register with some additional bits forced to state reset */
7093 /* instead of modifying only the selected bit for this function, */
7094 /* to not interfere with bits with HW property "rs". */
7095 MODIFY_REG(ADCx->CR,
7096 ADC_CR_BITS_PROPERTY_RS,
7097 ADC_CR_ADSTART);
7098}
7099
7110__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
7111{
7112 /* Note: Write register with some additional bits forced to state reset */
7113 /* instead of modifying only the selected bit for this function, */
7114 /* to not interfere with bits with HW property "rs". */
7115 MODIFY_REG(ADCx->CR,
7116 ADC_CR_BITS_PROPERTY_RS,
7117 ADC_CR_ADSTP);
7118}
7119
7126__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
7127{
7128 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
7129}
7130
7137__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
7138{
7139 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
7140}
7141
7151__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
7152{
7153 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7154}
7155
7166__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx)
7167{
7168 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7169}
7170
7181__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx)
7182{
7183 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7184}
7185
7196__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
7197{
7198 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7199}
7200
7211__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
7212{
7213 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7214}
7215
7226__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
7227{
7228 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7229}
7251__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
7252{
7253 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
7254 ConversionData)
7255 >> (POSITION_VAL(ConversionData) & 0x1FUL)
7256 );
7257}
7258
7286__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
7287{
7288 /* Note: Write register with some additional bits forced to state reset */
7289 /* instead of modifying only the selected bit for this function, */
7290 /* to not interfere with bits with HW property "rs". */
7291 MODIFY_REG(ADCx->CR,
7292 ADC_CR_BITS_PROPERTY_RS,
7293 ADC_CR_JADSTART);
7294}
7295
7306__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
7307{
7308 /* Note: Write register with some additional bits forced to state reset */
7309 /* instead of modifying only the selected bit for this function, */
7310 /* to not interfere with bits with HW property "rs". */
7311 MODIFY_REG(ADCx->CR,
7312 ADC_CR_BITS_PROPERTY_RS,
7313 ADC_CR_JADSTP);
7314}
7315
7322__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
7323{
7324 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
7325}
7326
7333__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
7334{
7335 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
7336}
7337
7355__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
7356{
7357 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7358
7359 return (uint32_t)(READ_BIT(*preg,
7360 ADC_JDR1_JDATA)
7361 );
7362}
7363
7382__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)
7383{
7384 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7385
7386 return (uint16_t)(READ_BIT(*preg,
7387 ADC_JDR1_JDATA)
7388 );
7389}
7390
7409__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)
7410{
7411 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7412
7413 return (uint16_t)(READ_BIT(*preg,
7414 ADC_JDR1_JDATA)
7415 );
7416}
7417
7436__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
7437{
7438 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7439
7440 return (uint16_t)(READ_BIT(*preg,
7441 ADC_JDR1_JDATA)
7442 );
7443}
7444
7463__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
7464{
7465 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7466
7467 return (uint16_t)(READ_BIT(*preg,
7468 ADC_JDR1_JDATA)
7469 );
7470}
7471
7490__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
7491{
7492 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7493
7494 return (uint8_t)(READ_BIT(*preg,
7495 ADC_JDR1_JDATA)
7496 );
7497}
7498
7517__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
7518{
7519 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
7520}
7521
7528__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
7529{
7530 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
7531}
7532
7539__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
7540{
7541 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
7542}
7543
7550__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
7551{
7552 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
7553}
7554
7561__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
7562{
7563 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
7564}
7565
7572__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
7573{
7574 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
7575}
7576
7583__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
7584{
7585 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
7586}
7587
7594__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
7595{
7596 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
7597}
7598
7605__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(ADC_TypeDef *ADCx)
7606{
7607 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL);
7608}
7609
7616__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
7617{
7618 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
7619}
7620
7627__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
7628{
7629 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
7630}
7631
7638__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
7639{
7640 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
7641}
7642
7652__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
7653{
7654 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
7655}
7656
7663__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
7664{
7665 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
7666}
7667
7674__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
7675{
7676 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
7677}
7678
7685__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
7686{
7687 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
7688}
7689
7696__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
7697{
7698 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
7699}
7700
7707__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
7708{
7709 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
7710}
7711
7718__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
7719{
7720 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
7721}
7722
7729__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
7730{
7731 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
7732}
7733
7740__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
7741{
7742 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
7743}
7744
7751__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
7752{
7753 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
7754}
7755
7762__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
7763{
7764 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
7765}
7766
7774__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
7775{
7776 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
7777}
7778
7786__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
7787{
7788 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
7789}
7790
7798__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
7799{
7800 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7801}
7802
7810__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
7811{
7812 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7813}
7814
7822__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
7823{
7824 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
7825}
7826
7834__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
7835{
7836 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
7837}
7838
7846__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
7847{
7848 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
7849}
7850
7858__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
7859{
7860 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
7861}
7862
7870__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
7871{
7872 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
7873}
7874
7882__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
7883{
7884 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
7885}
7886
7894__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
7895{
7896 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
7897}
7898
7906__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
7907{
7908 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
7909}
7910
7918__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
7919{
7920 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
7921}
7922
7930__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
7931{
7932 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
7933}
7934
7942__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
7943{
7944 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
7945}
7946
7954__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
7955{
7956 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
7957}
7958
7966__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
7967{
7968 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
7969}
7970
7978__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
7979{
7980 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
7981}
7982
7990__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
7991{
7992 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
7993}
7994
8002__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
8003{
8004 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
8005}
8006
8014__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
8015{
8016 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
8017}
8018
8026__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
8027{
8028 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
8029}
8030
8046__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
8047{
8048 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
8049}
8050
8057__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
8058{
8059 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
8060}
8061
8068__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
8069{
8070 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
8071}
8072
8079__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
8080{
8081 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
8082}
8083
8090__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
8091{
8092 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8093}
8094
8101__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
8102{
8103 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8104}
8105
8112__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
8113{
8114 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8115}
8116
8123__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
8124{
8125 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
8126}
8127
8134__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
8135{
8136 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8137}
8138
8145__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
8146{
8147 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8148}
8149
8156__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
8157{
8158 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8159}
8160
8167__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
8168{
8169 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
8170}
8171
8178__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
8179{
8180 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
8181}
8182
8189__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
8190{
8191 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
8192}
8193
8200__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
8201{
8202 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
8203}
8204
8211__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
8212{
8213 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8214}
8215
8222__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
8223{
8224 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8225}
8226
8233__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
8234{
8235 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8236}
8237
8244__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
8245{
8246 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
8247}
8248
8255__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
8256{
8257 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8258}
8259
8266__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
8267{
8268 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8269}
8270
8277__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
8278{
8279 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8280}
8281
8289__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
8290{
8291 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
8292}
8293
8301__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
8302{
8303 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
8304}
8305
8313__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
8314{
8315 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
8316}
8317
8325__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
8326{
8327 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
8328}
8329
8337__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
8338{
8339 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
8340}
8341
8349__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
8350{
8351 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
8352}
8353
8361__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
8362{
8363 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
8364}
8365
8373__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
8374{
8375 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
8376}
8377
8385__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
8386{
8387 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
8388}
8389
8397__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
8398{
8399 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
8400}
8401
8409__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
8410{
8411 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
8412}
8413
8418#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
8424/* Initialization of some features of ADC common parameters and multimode */
8425ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
8426ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
8427void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
8428
8429/* De-initialization of ADC instance, ADC group regular and ADC group injected */
8430/* (availability of ADC group injected depends on STM32 families) */
8431ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
8432
8433/* Initialization of some features of ADC instance */
8434ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
8435void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
8436
8437/* Initialization of some features of ADC instance and ADC group regular */
8438ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
8439void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
8440
8441/* Initialization of some features of ADC instance and ADC group injected */
8442ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
8443void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
8444
8448#endif /* USE_FULL_LL_DRIVER */
8449
8458#endif /* ADC1 || ADC2 || ADC3 */
8459
8464#ifdef __cplusplus
8465}
8466#endif
8467
8468#endif /* STM32H7xx_LL_ADC_H */
8469
__IO
#define __IO
Definition: core_cm4.h:239
ADC_SMPR1_SMP0
#define ADC_SMPR1_SMP0
Definition: stm32h723xx.h:3032
ADC3_CFGR_DMAEN
#define ADC3_CFGR_DMAEN
Definition: stm32h723xx.h:2941
ADC_CCR_CKMODE
#define ADC_CCR_CKMODE
Definition: stm32h723xx.h:4078
ADC_CALFACT_CALFACT_S
#define ADC_CALFACT_CALFACT_S
Definition: stm32h723xx.h:3920
ADC_CCR_PRESC
#define ADC_CCR_PRESC
Definition: stm32h723xx.h:4084
ADC_CFGR_JAUTO
#define ADC_CFGR_JAUTO
Definition: stm32h723xx.h:2924
ADC_OFR1_OFFSET1_CH
#define ADC_OFR1_OFFSET1_CH
Definition: stm32h723xx.h:3491
ADC_CFGR_DISCEN
#define ADC_CFGR_DISCEN
Definition: stm32h723xx.h:2898
ADC_CALFACT2_LINCALFACT
#define ADC_CALFACT2_LINCALFACT
Definition: stm32h723xx.h:3950
ADC_CR_ADSTART
#define ADC_CR_ADSTART
Definition: stm32h723xx.h:2808
ADC_CR_ADEN
#define ADC_CR_ADEN
Definition: stm32h723xx.h:2802
ADC_CR_JADSTART
#define ADC_CR_JADSTART
Definition: stm32h723xx.h:2811
ADC_CR_ADCALLIN
#define ADC_CR_ADCALLIN
Definition: stm32h723xx.h:2825
ADC3_OFR1_OFFSETPOS
#define ADC3_OFR1_OFFSETPOS
Definition: stm32h723xx.h:3508
ADC_JSQR_JSQ4
#define ADC_JSQR_JSQ4
Definition: stm32h723xx.h:3451
ADC_CFGR2_TROVS
#define ADC_CFGR2_TROVS
Definition: stm32h723xx.h:2973
ADC_JSQR_JSQ2
#define ADC_JSQR_JSQ2
Definition: stm32h723xx.h:3433
ADC3_CFGR2_BULB
#define ADC3_CFGR2_BULB
Definition: stm32h723xx.h:3025
ADC3_CFGR2_OVSR
#define ADC3_CFGR2_OVSR
Definition: stm32h723xx.h:3015
ADC3_TR1_AWDFILT
#define ADC3_TR1_AWDFILT
Definition: stm32h723xx.h:3213
ADC_CFGR_DISCNUM
#define ADC_CFGR_DISCNUM
Definition: stm32h723xx.h:2902
ADC_DIFSEL_DIFSEL
#define ADC_DIFSEL_DIFSEL
Definition: stm32h723xx.h:3895
ADC_CFGR_DMNGT
#define ADC_CFGR_DMNGT
Definition: stm32h723xx.h:2860
ADC3_TR1_LT1
#define ADC3_TR1_LT1
Definition: stm32h723xx.h:3209
ADC_CR_ADSTP
#define ADC_CR_ADSTP
Definition: stm32h723xx.h:2814
ADC_CFGR_RES_0
#define ADC_CFGR_RES_0
Definition: stm32h723xx.h:2867
ADC_CR_ADVREGEN
#define ADC_CR_ADVREGEN
Definition: stm32h723xx.h:2846
ADC3_CFGR_DMACFG
#define ADC3_CFGR_DMACFG
Definition: stm32h723xx.h:2944
ADC_CR_ADCALDIF
#define ADC_CR_ADCALDIF
Definition: stm32h723xx.h:2852
ADC_CFGR2_OVSS
#define ADC_CFGR2_OVSS
Definition: stm32h723xx.h:2965
ADC_CR_DEEPPWD
#define ADC_CR_DEEPPWD
Definition: stm32h723xx.h:2849
ADC_CFGR2_ROVSE
#define ADC_CFGR2_ROVSE
Definition: stm32h723xx.h:2958
ADC_CFGR2_JOVSE
#define ADC_CFGR2_JOVSE
Definition: stm32h723xx.h:2961
ADC_OFR1_SSATE
#define ADC_OFR1_SSATE
Definition: stm32h723xx.h:3500
ADC_CFGR2_OVSR
#define ADC_CFGR2_OVSR
Definition: stm32h723xx.h:2993
ADC_CFGR_AUTDLY
#define ADC_CFGR_AUTDLY
Definition: stm32h723xx.h:2894
ADC_CFGR2_RSHIFT4
#define ADC_CFGR2_RSHIFT4
Definition: stm32h723xx.h:2989
ADC_OFR1_OFFSET1
#define ADC_OFR1_OFFSET1
Definition: stm32h723xx.h:3461
ADC_CFGR_JAWD1EN
#define ADC_CFGR_JAWD1EN
Definition: stm32h723xx.h:2921
ADC_CFGR_JQDIS
#define ADC_CFGR_JQDIS
Definition: stm32h723xx.h:2937
ADC_CFGR2_RSHIFT3
#define ADC_CFGR2_RSHIFT3
Definition: stm32h723xx.h:2986
ADC_CFGR2_RSHIFT1
#define ADC_CFGR2_RSHIFT1
Definition: stm32h723xx.h:2980
ADC_JSQR_JEXTSEL
#define ADC_JSQR_JEXTSEL
Definition: stm32h723xx.h:3409
ADC3_OFR1_OFFSET1_EN
#define ADC3_OFR1_OFFSET1_EN
Definition: stm32h723xx.h:3515
ADC_CFGR_CONT
#define ADC_CFGR_CONT
Definition: stm32h723xx.h:2891
ADC3_CFGR2_SMPTRIG
#define ADC3_CFGR2_SMPTRIG
Definition: stm32h723xx.h:3028
ADC_CR_ADCAL
#define ADC_CR_ADCAL
Definition: stm32h723xx.h:2855
ADC_CFGR_RES_1
#define ADC_CFGR_RES_1
Definition: stm32h723xx.h:2868
ADC_ISR_EOC
#define ADC_ISR_EOC
Definition: stm32h723xx.h:2735
ADC_CFGR_AWD1CH
#define ADC_CFGR_AWD1CH
Definition: stm32h723xx.h:2928
ADC3_TR1_HT1
#define ADC3_TR1_HT1
Definition: stm32h723xx.h:3220
ADC_CCR_DELAY
#define ADC_CCR_DELAY
Definition: stm32h723xx.h:4063
ADC_CCR_DAMDF
#define ADC_CCR_DAMDF
Definition: stm32h723xx.h:4072
ADC_JSQR_JL
#define ADC_JSQR_JL
Definition: stm32h723xx.h:3403
ADC_CFGR_AWD1EN
#define ADC_CFGR_AWD1EN
Definition: stm32h723xx.h:2918
ADC3_OFR1_SATEN
#define ADC3_OFR1_SATEN
Definition: stm32h723xx.h:3511
ADC_CCR_VBATEN
#define ADC_CCR_VBATEN
Definition: stm32h723xx.h:4098
ADC_CFGR_EXTSEL
#define ADC_CFGR_EXTSEL
Definition: stm32h723xx.h:2873
ADC_DR_RDATA
#define ADC_DR_RDATA
Definition: stm32h723xx.h:3398
ADC_CFGR2_ROVSM
#define ADC_CFGR2_ROVSM
Definition: stm32h723xx.h:2976
ADC_LTR_LT
#define ADC_LTR_LT
Definition: stm32h723xx.h:3199
ADC_CR_JADSTP
#define ADC_CR_JADSTP
Definition: stm32h723xx.h:2817
ADC_JDR1_JDATA
#define ADC_JDR1_JDATA
Definition: stm32h723xx.h:3697
ADC_JSQR_JEXTEN
#define ADC_JSQR_JEXTEN
Definition: stm32h723xx.h:3418
ADC_CFGR2_RSHIFT2
#define ADC_CFGR2_RSHIFT2
Definition: stm32h723xx.h:2983
ADC_HTR_HT
#define ADC_HTR_HT
Definition: stm32h723xx.h:3204
ADC_JSQR_JSQ1
#define ADC_JSQR_JSQ1
Definition: stm32h723xx.h:3424
ADC_CR_ADDIS
#define ADC_CR_ADDIS
Definition: stm32h723xx.h:2805
ADC_CFGR_AWD1SGL
#define ADC_CFGR_AWD1SGL
Definition: stm32h723xx.h:2915
ADC_CFGR_JQM
#define ADC_CFGR_JQM
Definition: stm32h723xx.h:2912
ADC_CCR_DUAL
#define ADC_CCR_DUAL
Definition: stm32h723xx.h:4054
ADC_JSQR_JSQ3
#define ADC_JSQR_JSQ3
Definition: stm32h723xx.h:3442
ADC_CR_BOOST
#define ADC_CR_BOOST
Definition: stm32h723xx.h:2820
ADC_SQR1_L
#define ADC_SQR1_L
Definition: stm32h723xx.h:3243
ADC_CR_BOOST_0
#define ADC_CR_BOOST_0
Definition: stm32h723xx.h:2821
ADC3_CFGR_RES
#define ADC3_CFGR_RES
Definition: stm32h723xx.h:2948
ADC_CFGR_JDISCEN
#define ADC_CFGR_JDISCEN
Definition: stm32h723xx.h:2909
ADC_CFGR_RES
#define ADC_CFGR_RES
Definition: stm32h723xx.h:2866
ADC_CCR_TSEN
#define ADC_CCR_TSEN
Definition: stm32h723xx.h:4095
ADC_CCR_VREFEN
#define ADC_CCR_VREFEN
Definition: stm32h723xx.h:4092
ADC_CFGR_OVRMOD
#define ADC_CFGR_OVRMOD
Definition: stm32h723xx.h:2888
ADC_CFGR_EXTEN
#define ADC_CFGR_EXTEN
Definition: stm32h723xx.h:2882
ADC_AWD2CR_AWD2CH_0
#define ADC_AWD2CR_AWD2CH_0
Definition: stm32h723xx.h:3846
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
ADC_Common_TypeDef
Definition: stm32h723xx.h:289
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
Definition: stm32h723xx.h:293
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32h723xx.h:290
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32h723xx.h:292
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32h723xx.h:242
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32h723xx.h:255
ADC_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition: stm32h723xx.h:247
ADC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32h723xx.h:246
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32h723xx.h:262
ADC_TypeDef::CR
__IO uint32_t CR
Definition: stm32h723xx.h:245
ADC_TypeDef::LTR1
__IO uint32_t LTR1
Definition: stm32h742xx.h:250
ADC_TypeDef::CALFACT
__IO uint32_t CALFACT
Definition: stm32h742xx.h:282
ADC_TypeDef::DIFSEL
__IO uint32_t DIFSEL
Definition: stm32h742xx.h:281
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32h723xx.h:248
ADC_TypeDef::IER
__IO uint32_t IER
Definition: stm32h723xx.h:244
ADC_TypeDef::CALFACT2
__IO uint32_t CALFACT2
Definition: stm32h742xx.h:283
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32h723xx.h:259
ADC_TypeDef::DIFSEL_RES12
__IO uint32_t DIFSEL_RES12
Definition: stm32h723xx.h:282
ADC_TypeDef::OFR1
__IO uint32_t OFR1
Definition: stm32h723xx.h:264
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32h723xx.h:269
ADC_TypeDef::LTR2_DIFSEL
__IO uint32_t LTR2_DIFSEL
Definition: stm32h723xx.h:278
ADC_TypeDef::PCSEL_RES0
__IO uint32_t PCSEL_RES0
Definition: stm32h723xx.h:250
ADC_TypeDef::CALFACT_RES13
__IO uint32_t CALFACT_RES13
Definition: stm32h723xx.h:283
ADC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32h723xx.h:243
ADC_TypeDef::CALFACT2_RES14
__IO uint32_t CALFACT2_RES14
Definition: stm32h723xx.h:284
ADC_TypeDef::PCSEL
__IO uint32_t PCSEL
Definition: stm32h742xx.h:249
ADC_TypeDef::LTR1_TR1
__IO uint32_t LTR1_TR1
Definition: stm32h723xx.h:251
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