20#ifndef STM32H7xx_HAL_DAC_H
21#define STM32H7xx_HAL_DAC_H
34#if defined(DAC1) || defined(DAC2)
52 HAL_DAC_STATE_RESET = 0x00U,
53 HAL_DAC_STATE_READY = 0x01U,
54 HAL_DAC_STATE_BUSY = 0x02U,
55 HAL_DAC_STATE_TIMEOUT = 0x03U,
56 HAL_DAC_STATE_ERROR = 0x04U
58} HAL_DAC_StateTypeDef;
63#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
64typedef struct __DAC_HandleTypeDef
71 __IO HAL_DAC_StateTypeDef State;
79 __IO uint32_t ErrorCode;
81#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
82 void (* ConvCpltCallbackCh1) (
struct __DAC_HandleTypeDef *hdac);
83 void (* ConvHalfCpltCallbackCh1) (
struct __DAC_HandleTypeDef *hdac);
84 void (* ErrorCallbackCh1) (
struct __DAC_HandleTypeDef *hdac);
85 void (* DMAUnderrunCallbackCh1) (
struct __DAC_HandleTypeDef *hdac);
87 void (* ConvCpltCallbackCh2) (
struct __DAC_HandleTypeDef *hdac);
88 void (* ConvHalfCpltCallbackCh2) (
struct __DAC_HandleTypeDef *hdac);
89 void (* ErrorCallbackCh2) (
struct __DAC_HandleTypeDef *hdac);
90 void (* DMAUnderrunCallbackCh2) (
struct __DAC_HandleTypeDef *hdac);
93 void (* MspInitCallback) (
struct __DAC_HandleTypeDef *hdac);
94 void (* MspDeInitCallback) (
struct __DAC_HandleTypeDef *hdac);
104 uint32_t DAC_SampleTime ;
108 uint32_t DAC_HoldTime ;
112 uint32_t DAC_RefreshTime ;
115} DAC_SampleAndHoldConfTypeDef;
122 uint32_t DAC_SampleAndHold;
125 uint32_t DAC_Trigger;
128 uint32_t DAC_OutputBuffer;
131 uint32_t DAC_ConnectOnChipPeripheral ;
134 uint32_t DAC_UserTrimming;
138 uint32_t DAC_TrimmingValue;
141 DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig;
142} DAC_ChannelConfTypeDef;
144#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
150 HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U,
151 HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U,
152 HAL_DAC_CH1_ERROR_ID = 0x02U,
153 HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U,
155 HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U,
156 HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U,
157 HAL_DAC_CH2_ERROR_ID = 0x06U,
158 HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U,
160 HAL_DAC_MSPINIT_CB_ID = 0x08U,
161 HAL_DAC_MSPDEINIT_CB_ID = 0x09U,
162 HAL_DAC_ALL_CB_ID = 0x0AU
163} HAL_DAC_CallbackIDTypeDef;
168typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
186#define HAL_DAC_ERROR_NONE 0x00U
187#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U
188#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U
189#define HAL_DAC_ERROR_DMA 0x04U
190#define HAL_DAC_ERROR_TIMEOUT 0x08U
191#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
192#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U
203#define DAC_TRIGGER_NONE 0x00000000U
204#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1)
205#define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1)
206#define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1)
207#define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
208#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1)
209#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
210#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
211#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
212#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1)
214#define DAC_TRIGGER_HR1_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
215#define DAC_TRIGGER_HR1_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
217#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
218#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)
219#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
221#define DAC_TRIGGER_T23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
224#define DAC_TRIGGER_T24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)
227#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)
238#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
239#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)
249#define DAC_CHANNEL_1 0x00000000U
251#define DAC_CHANNEL_2 0x00000010U
261#define DAC_ALIGN_12B_R 0x00000000U
262#define DAC_ALIGN_12B_L 0x00000004U
263#define DAC_ALIGN_8B_R 0x00000008U
273#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
275#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
286#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
288#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
299#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0)
300#define DAC_CHIPCONNECT_INTERNAL (1UL << 1)
301#define DAC_CHIPCONNECT_BOTH (1UL << 2)
311#define DAC_TRIMMING_FACTORY (0x00000000UL)
312#define DAC_TRIMMING_USER (0x00000001UL)
321#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
322#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)
342#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
343#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
344 (__HANDLE__)->State = HAL_DAC_STATE_RESET; \
345 (__HANDLE__)->MspInitCallback = NULL; \
346 (__HANDLE__)->MspDeInitCallback = NULL; \
349#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
357#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
358 ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
365#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
366 ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
372#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
379#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
386#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
396#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
406#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
416#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
417 & (__INTERRUPT__)) == (__INTERRUPT__))
427#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
437#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
449#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
450 ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
452#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
453 ((CHANNEL) == DAC_CHANNEL_2))
455#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
456 ((ALIGN) == DAC_ALIGN_12B_L) || \
457 ((ALIGN) == DAC_ALIGN_8B_R))
459#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
461#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)
482void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
483void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
495HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
498void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
499HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
501void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
502void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
503void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
504void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
506#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
508HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
509 pDAC_CallbackTypeDef pCallback);
510HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
521uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
522HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
531HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
532uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
#define __IO
Definition: core_cm4.h:239
Header file of DAC HAL Extended module.
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32h7xx_hal_def.h:58
Digital to Analog Converter.
Definition: stm32h723xx.h:469
DMA handle Structure definition.
Definition: stm32h7xx_hal_dma.h:138