66#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
67 !defined (STM32H745xx) && !defined (STM32H745xG) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H747xG)&& !defined (STM32H757xx) && \
68 !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) && \
69 !defined (STM32H735xx) && !defined (STM32H733xx) && !defined (STM32H730xx) && !defined (STM32H730xxQ) && !defined (STM32H725xx) && !defined (STM32H723xx)
97#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
98 #error "Dual core device, please select CORE_CM4 or CORE_CM7"
101#if !defined (USE_HAL_DRIVER)
113#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01)
114#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A)
115#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x03)
116#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00)
117#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
118 |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
119 |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
120 |(__STM32H7xx_CMSIS_DEVICE_VERSION_RC))
130#if defined(STM32H743xx)
132#elif defined(STM32H753xx)
134#elif defined(STM32H750xx)
136#elif defined(STM32H742xx)
138#elif defined(STM32H745xx)
140#elif defined(STM32H745xG)
142#elif defined(STM32H755xx)
144#elif defined(STM32H747xx)
146#elif defined(STM32H747xG)
148#elif defined(STM32H757xx)
150#elif defined(STM32H7B0xx)
152#elif defined(STM32H7B0xxQ)
153 #include "stm32h7b0xxq.h"
154#elif defined(STM32H7A3xx)
156#elif defined(STM32H7B3xx)
158#elif defined(STM32H7A3xxQ)
160#elif defined(STM32H7B3xxQ)
162#elif defined(STM32H735xx)
164#elif defined(STM32H733xx)
166#elif defined(STM32H730xx)
168#elif defined(STM32H730xxQ)
169 #include "stm32h730xxq.h"
170#elif defined(STM32H725xx)
172#elif defined(STM32H723xx)
175 #error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
189} FlagStatus, ITStatus;
196#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
212#define SET_BIT(REG, BIT) ((REG) |= (BIT))
214#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
216#define READ_BIT(REG, BIT) ((REG) & (BIT))
218#define CLEAR_REG(REG) ((REG) = (0x0))
220#define WRITE_REG(REG, VAL) ((REG) = (VAL))
222#define READ_REG(REG) ((REG))
224#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
226#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
230#define ATOMIC_SET_BIT(REG, BIT) \
234 val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
235 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
239#define ATOMIC_CLEAR_BIT(REG, BIT) \
243 val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
244 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
248#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
252 val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
253 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
257#define ATOMIC_SETH_BIT(REG, BIT) \
261 val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
262 } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
266#define ATOMIC_CLEARH_BIT(REG, BIT) \
270 val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
271 } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
275#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
279 val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
280 } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
287#if defined (USE_HAL_DRIVER)
CMSIS STM32H723xx Device Peripheral Access Layer Header File.
CMSIS STM32H725xx Device Peripheral Access Layer Header File.
CMSIS STM32H730xx Device Peripheral Access Layer Header File.
CMSIS STM32H733xx Device Peripheral Access Layer Header File.
CMSIS STM32H735xx Device Peripheral Access Layer Header File.
CMSIS STM32H742xx Device Peripheral Access Layer Header File.
CMSIS STM32H743xx Device Peripheral Access Layer Header File.
CMSIS STM32H745xG Device Peripheral Access Layer Header File.
CMSIS STM32H745xx Device Peripheral Access Layer Header File.
CMSIS STM32H747xG Device Peripheral Access Layer Header File.
CMSIS STM32H747xx Device Peripheral Access Layer Header File.
CMSIS STM32H750xx Device Peripheral Access Layer Header File.
CMSIS STM32H753xx Device Peripheral Access Layer Header File.
CMSIS STM32H755xx Device Peripheral Access Layer Header File.
CMSIS STM32H757xx Device Peripheral Access Layer Header File.
CMSIS STM32H7A3xx Device Peripheral Access Layer Header File.
CMSIS STM32H7A3xxQ Device Peripheral Access Layer Header File.
CMSIS STM32H7B0xx Device Peripheral Access Layer Header File.
CMSIS STM32H7B3xx Device Peripheral Access Layer Header File.
CMSIS STM32H7B3xxQ Device Peripheral Access Layer Header File.
This file contains all the functions prototypes for the HAL module driver.