RTEMS 6.1-rc2
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stm32h747xx.h
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1
33#ifndef STM32H747xx_H
34#define STM32H747xx_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
48typedef enum
49{
50/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
51 NonMaskableInt_IRQn = -14,
52 HardFault_IRQn = -13,
53 MemoryManagement_IRQn = -12,
54 BusFault_IRQn = -11,
55 UsageFault_IRQn = -10,
56 SVCall_IRQn = -5,
57 DebugMonitor_IRQn = -4,
58 PendSV_IRQn = -2,
59 SysTick_IRQn = -1,
60/****** STM32 specific Interrupt Numbers **********************************************************************/
61 WWDG_IRQn = 0,
62 PVD_AVD_IRQn = 1,
63 TAMP_STAMP_IRQn = 2,
64 RTC_WKUP_IRQn = 3,
65 FLASH_IRQn = 4,
66 RCC_IRQn = 5,
67 EXTI0_IRQn = 6,
68 EXTI1_IRQn = 7,
69 EXTI2_IRQn = 8,
70 EXTI3_IRQn = 9,
71 EXTI4_IRQn = 10,
72 DMA1_Stream0_IRQn = 11,
73 DMA1_Stream1_IRQn = 12,
74 DMA1_Stream2_IRQn = 13,
75 DMA1_Stream3_IRQn = 14,
76 DMA1_Stream4_IRQn = 15,
77 DMA1_Stream5_IRQn = 16,
78 DMA1_Stream6_IRQn = 17,
79 ADC_IRQn = 18,
80 FDCAN1_IT0_IRQn = 19,
81 FDCAN2_IT0_IRQn = 20,
82 FDCAN1_IT1_IRQn = 21,
83 FDCAN2_IT1_IRQn = 22,
84 EXTI9_5_IRQn = 23,
85 TIM1_BRK_IRQn = 24,
86 TIM1_UP_IRQn = 25,
87 TIM1_TRG_COM_IRQn = 26,
88 TIM1_CC_IRQn = 27,
89 TIM2_IRQn = 28,
90 TIM3_IRQn = 29,
91 TIM4_IRQn = 30,
92 I2C1_EV_IRQn = 31,
93 I2C1_ER_IRQn = 32,
94 I2C2_EV_IRQn = 33,
95 I2C2_ER_IRQn = 34,
96 SPI1_IRQn = 35,
97 SPI2_IRQn = 36,
98 USART1_IRQn = 37,
99 USART2_IRQn = 38,
100 USART3_IRQn = 39,
101 EXTI15_10_IRQn = 40,
102 RTC_Alarm_IRQn = 41,
103 TIM8_BRK_TIM12_IRQn = 43,
104 TIM8_UP_TIM13_IRQn = 44,
105 TIM8_TRG_COM_TIM14_IRQn = 45,
106 TIM8_CC_IRQn = 46,
107 DMA1_Stream7_IRQn = 47,
108 FMC_IRQn = 48,
109 SDMMC1_IRQn = 49,
110 TIM5_IRQn = 50,
111 SPI3_IRQn = 51,
112 UART4_IRQn = 52,
113 UART5_IRQn = 53,
114 TIM6_DAC_IRQn = 54,
115 TIM7_IRQn = 55,
116 DMA2_Stream0_IRQn = 56,
117 DMA2_Stream1_IRQn = 57,
118 DMA2_Stream2_IRQn = 58,
119 DMA2_Stream3_IRQn = 59,
120 DMA2_Stream4_IRQn = 60,
121 ETH_IRQn = 61,
122 ETH_WKUP_IRQn = 62,
123 FDCAN_CAL_IRQn = 63,
124 CM7_SEV_IRQn = 64,
125 CM4_SEV_IRQn = 65,
126 DMA2_Stream5_IRQn = 68,
127 DMA2_Stream6_IRQn = 69,
128 DMA2_Stream7_IRQn = 70,
129 USART6_IRQn = 71,
130 I2C3_EV_IRQn = 72,
131 I2C3_ER_IRQn = 73,
132 OTG_HS_EP1_OUT_IRQn = 74,
133 OTG_HS_EP1_IN_IRQn = 75,
134 OTG_HS_WKUP_IRQn = 76,
135 OTG_HS_IRQn = 77,
136 DCMI_IRQn = 78,
137 RNG_IRQn = 80,
138 FPU_IRQn = 81,
139 UART7_IRQn = 82,
140 UART8_IRQn = 83,
141 SPI4_IRQn = 84,
142 SPI5_IRQn = 85,
143 SPI6_IRQn = 86,
144 SAI1_IRQn = 87,
145 LTDC_IRQn = 88,
146 LTDC_ER_IRQn = 89,
147 DMA2D_IRQn = 90,
148 SAI2_IRQn = 91,
149 QUADSPI_IRQn = 92,
150 LPTIM1_IRQn = 93,
151 CEC_IRQn = 94,
152 I2C4_EV_IRQn = 95,
153 I2C4_ER_IRQn = 96,
154 SPDIF_RX_IRQn = 97,
155 OTG_FS_EP1_OUT_IRQn = 98,
156 OTG_FS_EP1_IN_IRQn = 99,
157 OTG_FS_WKUP_IRQn = 100,
158 OTG_FS_IRQn = 101,
159 DMAMUX1_OVR_IRQn = 102,
160 HRTIM1_Master_IRQn = 103,
161 HRTIM1_TIMA_IRQn = 104,
162 HRTIM1_TIMB_IRQn = 105,
163 HRTIM1_TIMC_IRQn = 106,
164 HRTIM1_TIMD_IRQn = 107,
165 HRTIM1_TIME_IRQn = 108,
166 HRTIM1_FLT_IRQn = 109,
167 DFSDM1_FLT0_IRQn = 110,
168 DFSDM1_FLT1_IRQn = 111,
169 DFSDM1_FLT2_IRQn = 112,
170 DFSDM1_FLT3_IRQn = 113,
171 SAI3_IRQn = 114,
172 SWPMI1_IRQn = 115,
173 TIM15_IRQn = 116,
174 TIM16_IRQn = 117,
175 TIM17_IRQn = 118,
176 MDIOS_WKUP_IRQn = 119,
177 MDIOS_IRQn = 120,
178 JPEG_IRQn = 121,
179 MDMA_IRQn = 122,
180 DSI_IRQn = 123,
181 SDMMC2_IRQn = 124,
182 HSEM1_IRQn = 125,
183 HSEM2_IRQn = 126,
184 ADC3_IRQn = 127,
185 DMAMUX2_OVR_IRQn = 128,
186 BDMA_Channel0_IRQn = 129,
187 BDMA_Channel1_IRQn = 130,
188 BDMA_Channel2_IRQn = 131,
189 BDMA_Channel3_IRQn = 132,
190 BDMA_Channel4_IRQn = 133,
191 BDMA_Channel5_IRQn = 134,
192 BDMA_Channel6_IRQn = 135,
193 BDMA_Channel7_IRQn = 136,
194 COMP_IRQn = 137 ,
195 LPTIM2_IRQn = 138,
196 LPTIM3_IRQn = 139,
197 LPTIM4_IRQn = 140,
198 LPTIM5_IRQn = 141,
199 LPUART1_IRQn = 142,
200 WWDG_RST_IRQn = 143,
201 CRS_IRQn = 144,
202 ECC_IRQn = 145,
203 SAI4_IRQn = 146,
204 HOLD_CORE_IRQn = 148,
205 WAKEUP_PIN_IRQn = 149,
206} IRQn_Type;
207
215#define DUAL_CORE
217#define SMPS
224#ifdef CORE_CM4
225#define __CM4_REV 0x0001U
226#define __MPU_PRESENT 1U
227#define __NVIC_PRIO_BITS 4U
228#define __Vendor_SysTickConfig 0U
229#define __FPU_PRESENT 1U
231#include "core_cm4.h"
232#else /* CORE_CM7 */
233#ifdef CORE_CM7
234#define __CM7_REV 0x0100U
235#define __MPU_PRESENT 1U
236#define __NVIC_PRIO_BITS 4U
237#define __Vendor_SysTickConfig 0U
238#define __FPU_PRESENT 1U
239#define __ICACHE_PRESENT 1U
240#define __DCACHE_PRESENT 1U
241#include "core_cm7.h"
242#else /* UNKNOWN_CORE */
243#error Please #define CORE_CM4 or CORE_CM7
244#endif /* CORE_CM7 */
245#endif /* CORE_CM4 */
246
255#include "system_stm32h7xx.h"
256#include <stdint.h>
257
266typedef struct
267{
268 __IO uint32_t ISR;
269 __IO uint32_t IER;
270 __IO uint32_t CR;
271 __IO uint32_t CFGR;
272 __IO uint32_t CFGR2;
273 __IO uint32_t SMPR1;
274 __IO uint32_t SMPR2;
275 __IO uint32_t PCSEL;
276 __IO uint32_t LTR1;
277 __IO uint32_t HTR1;
278 uint32_t RESERVED1;
279 uint32_t RESERVED2;
280 __IO uint32_t SQR1;
281 __IO uint32_t SQR2;
282 __IO uint32_t SQR3;
283 __IO uint32_t SQR4;
284 __IO uint32_t DR;
285 uint32_t RESERVED3;
286 uint32_t RESERVED4;
287 __IO uint32_t JSQR;
288 uint32_t RESERVED5[4];
289 __IO uint32_t OFR1;
290 __IO uint32_t OFR2;
291 __IO uint32_t OFR3;
292 __IO uint32_t OFR4;
293 uint32_t RESERVED6[4];
294 __IO uint32_t JDR1;
295 __IO uint32_t JDR2;
296 __IO uint32_t JDR3;
297 __IO uint32_t JDR4;
298 uint32_t RESERVED7[4];
299 __IO uint32_t AWD2CR;
300 __IO uint32_t AWD3CR;
301 uint32_t RESERVED8;
302 uint32_t RESERVED9;
303 __IO uint32_t LTR2;
304 __IO uint32_t HTR2;
305 __IO uint32_t LTR3;
306 __IO uint32_t HTR3;
307 __IO uint32_t DIFSEL;
308 __IO uint32_t CALFACT;
309 __IO uint32_t CALFACT2;
310} ADC_TypeDef;
311
312
313typedef struct
314{
315__IO uint32_t CSR;
316uint32_t RESERVED;
317__IO uint32_t CCR;
318__IO uint32_t CDR;
319__IO uint32_t CDR2;
321} ADC_Common_TypeDef;
322
327typedef struct
328{
329 __IO uint32_t CTR;
330}ART_TypeDef;
331
336typedef struct
337{
338 __IO uint32_t CSR;
339 __IO uint32_t CCR;
340} VREFBUF_TypeDef;
341
342
347typedef struct
348{
349 __IO uint32_t CREL;
350 __IO uint32_t ENDN;
351 __IO uint32_t RESERVED1;
352 __IO uint32_t DBTP;
353 __IO uint32_t TEST;
354 __IO uint32_t RWD;
355 __IO uint32_t CCCR;
356 __IO uint32_t NBTP;
357 __IO uint32_t TSCC;
358 __IO uint32_t TSCV;
359 __IO uint32_t TOCC;
360 __IO uint32_t TOCV;
361 __IO uint32_t RESERVED2[4];
362 __IO uint32_t ECR;
363 __IO uint32_t PSR;
364 __IO uint32_t TDCR;
365 __IO uint32_t RESERVED3;
366 __IO uint32_t IR;
367 __IO uint32_t IE;
368 __IO uint32_t ILS;
369 __IO uint32_t ILE;
370 __IO uint32_t RESERVED4[8];
371 __IO uint32_t GFC;
372 __IO uint32_t SIDFC;
373 __IO uint32_t XIDFC;
374 __IO uint32_t RESERVED5;
375 __IO uint32_t XIDAM;
376 __IO uint32_t HPMS;
377 __IO uint32_t NDAT1;
378 __IO uint32_t NDAT2;
379 __IO uint32_t RXF0C;
380 __IO uint32_t RXF0S;
381 __IO uint32_t RXF0A;
382 __IO uint32_t RXBC;
383 __IO uint32_t RXF1C;
384 __IO uint32_t RXF1S;
385 __IO uint32_t RXF1A;
386 __IO uint32_t RXESC;
387 __IO uint32_t TXBC;
388 __IO uint32_t TXFQS;
389 __IO uint32_t TXESC;
390 __IO uint32_t TXBRP;
391 __IO uint32_t TXBAR;
392 __IO uint32_t TXBCR;
393 __IO uint32_t TXBTO;
394 __IO uint32_t TXBCF;
395 __IO uint32_t TXBTIE;
396 __IO uint32_t TXBCIE;
397 __IO uint32_t RESERVED6[2];
398 __IO uint32_t TXEFC;
399 __IO uint32_t TXEFS;
400 __IO uint32_t TXEFA;
401 __IO uint32_t RESERVED7;
402} FDCAN_GlobalTypeDef;
403
408typedef struct
409{
410 __IO uint32_t TTTMC;
411 __IO uint32_t TTRMC;
412 __IO uint32_t TTOCF;
413 __IO uint32_t TTMLM;
414 __IO uint32_t TURCF;
415 __IO uint32_t TTOCN;
416 __IO uint32_t TTGTP;
417 __IO uint32_t TTTMK;
418 __IO uint32_t TTIR;
419 __IO uint32_t TTIE;
420 __IO uint32_t TTILS;
421 __IO uint32_t TTOST;
422 __IO uint32_t TURNA;
423 __IO uint32_t TTLGT;
424 __IO uint32_t TTCTC;
425 __IO uint32_t TTCPT;
426 __IO uint32_t TTCSM;
427 __IO uint32_t RESERVED1[111];
428 __IO uint32_t TTTS;
429} TTCAN_TypeDef;
430
435typedef struct
436{
437 __IO uint32_t CREL;
438 __IO uint32_t CCFG;
439 __IO uint32_t CSTAT;
440 __IO uint32_t CWD;
441 __IO uint32_t IR;
442 __IO uint32_t IE;
443} FDCAN_ClockCalibrationUnit_TypeDef;
444
445
450typedef struct
451{
452 __IO uint32_t CR;
453 __IO uint32_t CFGR;
454 __IO uint32_t TXDR;
455 __IO uint32_t RXDR;
456 __IO uint32_t ISR;
457 __IO uint32_t IER;
458}CEC_TypeDef;
459
464typedef struct
465{
466 __IO uint32_t DR;
467 __IO uint32_t IDR;
468 __IO uint32_t CR;
469 uint32_t RESERVED2;
470 __IO uint32_t INIT;
471 __IO uint32_t POL;
472} CRC_TypeDef;
473
474
478typedef struct
479{
480__IO uint32_t CR;
481__IO uint32_t CFGR;
482__IO uint32_t ISR;
483__IO uint32_t ICR;
484} CRS_TypeDef;
485
486
491typedef struct
492{
493 __IO uint32_t CR;
494 __IO uint32_t SWTRIGR;
495 __IO uint32_t DHR12R1;
496 __IO uint32_t DHR12L1;
497 __IO uint32_t DHR8R1;
498 __IO uint32_t DHR12R2;
499 __IO uint32_t DHR12L2;
500 __IO uint32_t DHR8R2;
501 __IO uint32_t DHR12RD;
502 __IO uint32_t DHR12LD;
503 __IO uint32_t DHR8RD;
504 __IO uint32_t DOR1;
505 __IO uint32_t DOR2;
506 __IO uint32_t SR;
507 __IO uint32_t CCR;
508 __IO uint32_t MCR;
509 __IO uint32_t SHSR1;
510 __IO uint32_t SHSR2;
511 __IO uint32_t SHHR;
512 __IO uint32_t SHRR;
513} DAC_TypeDef;
514
518typedef struct
519{
520 __IO uint32_t FLTCR1;
521 __IO uint32_t FLTCR2;
522 __IO uint32_t FLTISR;
523 __IO uint32_t FLTICR;
524 __IO uint32_t FLTJCHGR;
525 __IO uint32_t FLTFCR;
526 __IO uint32_t FLTJDATAR;
527 __IO uint32_t FLTRDATAR;
528 __IO uint32_t FLTAWHTR;
529 __IO uint32_t FLTAWLTR;
530 __IO uint32_t FLTAWSR;
531 __IO uint32_t FLTAWCFR;
532 __IO uint32_t FLTEXMAX;
533 __IO uint32_t FLTEXMIN;
534 __IO uint32_t FLTCNVTIMR;
535} DFSDM_Filter_TypeDef;
536
540typedef struct
541{
542 __IO uint32_t CHCFGR1;
543 __IO uint32_t CHCFGR2;
544 __IO uint32_t CHAWSCDR;
546 __IO uint32_t CHWDATAR;
547 __IO uint32_t CHDATINR;
548} DFSDM_Channel_TypeDef;
549
553typedef struct
554{
555 __IO uint32_t IDCODE;
556 __IO uint32_t CR;
557 __IO uint32_t RESERVED4[11];
558 __IO uint32_t APB3FZ1;
559 __IO uint32_t APB3FZ2;
560 __IO uint32_t APB1LFZ1;
561 __IO uint32_t APB1LFZ2;
562 __IO uint32_t APB1HFZ1;
563 __IO uint32_t APB1HFZ2;
564 __IO uint32_t APB2FZ1;
565 __IO uint32_t APB2FZ2;
566 __IO uint32_t APB4FZ1;
567 __IO uint32_t APB4FZ2;
569}DBGMCU_TypeDef;
574typedef struct
575{
576 __IO uint32_t CR;
577 __IO uint32_t SR;
578 __IO uint32_t RISR;
579 __IO uint32_t IER;
580 __IO uint32_t MISR;
581 __IO uint32_t ICR;
582 __IO uint32_t ESCR;
583 __IO uint32_t ESUR;
584 __IO uint32_t CWSTRTR;
585 __IO uint32_t CWSIZER;
586 __IO uint32_t DR;
587} DCMI_TypeDef;
588
593typedef struct
594{
595 __IO uint32_t CR;
596 __IO uint32_t NDTR;
597 __IO uint32_t PAR;
598 __IO uint32_t M0AR;
599 __IO uint32_t M1AR;
600 __IO uint32_t FCR;
601} DMA_Stream_TypeDef;
602
603typedef struct
604{
605 __IO uint32_t LISR;
606 __IO uint32_t HISR;
607 __IO uint32_t LIFCR;
608 __IO uint32_t HIFCR;
609} DMA_TypeDef;
610
611typedef struct
612{
613 __IO uint32_t CCR;
614 __IO uint32_t CNDTR;
615 __IO uint32_t CPAR;
616 __IO uint32_t CM0AR;
617 __IO uint32_t CM1AR;
618} BDMA_Channel_TypeDef;
619
620typedef struct
621{
622 __IO uint32_t ISR;
623 __IO uint32_t IFCR;
624} BDMA_TypeDef;
625
626typedef struct
627{
628 __IO uint32_t CCR;
629}DMAMUX_Channel_TypeDef;
630
631typedef struct
632{
633 __IO uint32_t CSR;
634 __IO uint32_t CFR;
635}DMAMUX_ChannelStatus_TypeDef;
636
637typedef struct
638{
639 __IO uint32_t RGCR;
640}DMAMUX_RequestGen_TypeDef;
641
642typedef struct
643{
644 __IO uint32_t RGSR;
645 __IO uint32_t RGCFR;
646}DMAMUX_RequestGenStatus_TypeDef;
647
651typedef struct
652{
653 __IO uint32_t GISR0;
654}MDMA_TypeDef;
655
656typedef struct
657{
658 __IO uint32_t CISR;
659 __IO uint32_t CIFCR;
660 __IO uint32_t CESR;
661 __IO uint32_t CCR;
662 __IO uint32_t CTCR;
663 __IO uint32_t CBNDTR;
664 __IO uint32_t CSAR;
665 __IO uint32_t CDAR;
666 __IO uint32_t CBRUR;
667 __IO uint32_t CLAR;
668 __IO uint32_t CTBR;
669 uint32_t RESERVED0;
670 __IO uint32_t CMAR;
671 __IO uint32_t CMDR;
672}MDMA_Channel_TypeDef;
673
678typedef struct
679{
680 __IO uint32_t CR;
681 __IO uint32_t ISR;
682 __IO uint32_t IFCR;
683 __IO uint32_t FGMAR;
684 __IO uint32_t FGOR;
685 __IO uint32_t BGMAR;
686 __IO uint32_t BGOR;
687 __IO uint32_t FGPFCCR;
688 __IO uint32_t FGCOLR;
689 __IO uint32_t BGPFCCR;
690 __IO uint32_t BGCOLR;
691 __IO uint32_t FGCMAR;
692 __IO uint32_t BGCMAR;
693 __IO uint32_t OPFCCR;
694 __IO uint32_t OCOLR;
695 __IO uint32_t OMAR;
696 __IO uint32_t OOR;
697 __IO uint32_t NLR;
698 __IO uint32_t LWR;
699 __IO uint32_t AMTCR;
700 uint32_t RESERVED[236];
701 __IO uint32_t FGCLUT[256];
702 __IO uint32_t BGCLUT[256];
703} DMA2D_TypeDef;
704
709typedef struct
710{
711 __IO uint32_t VR;
712 __IO uint32_t CR;
713 __IO uint32_t CCR;
714 __IO uint32_t LVCIDR;
715 __IO uint32_t LCOLCR;
716 __IO uint32_t LPCR;
717 __IO uint32_t LPMCR;
718 uint32_t RESERVED0[4];
719 __IO uint32_t PCR;
720 __IO uint32_t GVCIDR;
721 __IO uint32_t MCR;
722 __IO uint32_t VMCR;
723 __IO uint32_t VPCR;
724 __IO uint32_t VCCR;
725 __IO uint32_t VNPCR;
726 __IO uint32_t VHSACR;
727 __IO uint32_t VHBPCR;
728 __IO uint32_t VLCR;
729 __IO uint32_t VVSACR;
730 __IO uint32_t VVBPCR;
731 __IO uint32_t VVFPCR;
732 __IO uint32_t VVACR;
733 __IO uint32_t LCCR;
734 __IO uint32_t CMCR;
735 __IO uint32_t GHCR;
736 __IO uint32_t GPDR;
737 __IO uint32_t GPSR;
738 __IO uint32_t TCCR[6];
739 __IO uint32_t TDCR;
740 __IO uint32_t CLCR;
741 __IO uint32_t CLTCR;
742 __IO uint32_t DLTCR;
743 __IO uint32_t PCTLR;
744 __IO uint32_t PCONFR;
745 __IO uint32_t PUCR;
746 __IO uint32_t PTTCR;
747 __IO uint32_t PSR;
748 uint32_t RESERVED1[2];
749 __IO uint32_t ISR[2];
750 __IO uint32_t IER[2];
751 uint32_t RESERVED2[3];
752 __IO uint32_t FIR[2];
753 uint32_t RESERVED3[8];
754 __IO uint32_t VSCR;
755 uint32_t RESERVED4[2];
756 __IO uint32_t LCVCIDR;
757 __IO uint32_t LCCCR;
758 uint32_t RESERVED5;
759 __IO uint32_t LPMCCR;
760 uint32_t RESERVED6[7];
761 __IO uint32_t VMCCR;
762 __IO uint32_t VPCCR;
763 __IO uint32_t VCCCR;
764 __IO uint32_t VNPCCR;
765 __IO uint32_t VHSACCR;
766 __IO uint32_t VHBPCCR;
767 __IO uint32_t VLCCR;
768 __IO uint32_t VVSACCR;
769 __IO uint32_t VVBPCCR;
770 __IO uint32_t VVFPCCR;
771 __IO uint32_t VVACCR;
772 uint32_t RESERVED7[11];
773 __IO uint32_t TDCCR;
774 uint32_t RESERVED8[155];
775 __IO uint32_t WCFGR;
776 __IO uint32_t WCR;
777 __IO uint32_t WIER;
778 __IO uint32_t WISR;
779 __IO uint32_t WIFCR;
780 uint32_t RESERVED9;
781 __IO uint32_t WPCR[5];
782 uint32_t RESERVED10;
783 __IO uint32_t WRPCR;
784} DSI_TypeDef;
785
789typedef struct
790{
791 __IO uint32_t MACCR;
792 __IO uint32_t MACECR;
793 __IO uint32_t MACPFR;
794 __IO uint32_t MACWTR;
795 __IO uint32_t MACHT0R;
796 __IO uint32_t MACHT1R;
797 uint32_t RESERVED1[14];
798 __IO uint32_t MACVTR;
799 uint32_t RESERVED2;
800 __IO uint32_t MACVHTR;
801 uint32_t RESERVED3;
802 __IO uint32_t MACVIR;
803 __IO uint32_t MACIVIR;
804 uint32_t RESERVED4[2];
805 __IO uint32_t MACTFCR;
806 uint32_t RESERVED5[7];
807 __IO uint32_t MACRFCR;
808 uint32_t RESERVED6[7];
809 __IO uint32_t MACISR;
810 __IO uint32_t MACIER;
811 __IO uint32_t MACRXTXSR;
812 uint32_t RESERVED7;
813 __IO uint32_t MACPCSR;
814 __IO uint32_t MACRWKPFR;
815 uint32_t RESERVED8[2];
816 __IO uint32_t MACLCSR;
817 __IO uint32_t MACLTCR;
818 __IO uint32_t MACLETR;
819 __IO uint32_t MAC1USTCR;
820 uint32_t RESERVED9[12];
821 __IO uint32_t MACVR;
822 __IO uint32_t MACDR;
823 uint32_t RESERVED10;
824 __IO uint32_t MACHWF0R;
825 __IO uint32_t MACHWF1R;
826 __IO uint32_t MACHWF2R;
827 uint32_t RESERVED11[54];
828 __IO uint32_t MACMDIOAR;
829 __IO uint32_t MACMDIODR;
830 uint32_t RESERVED12[2];
831 __IO uint32_t MACARPAR;
832 uint32_t RESERVED13[59];
833 __IO uint32_t MACA0HR;
834 __IO uint32_t MACA0LR;
835 __IO uint32_t MACA1HR;
836 __IO uint32_t MACA1LR;
837 __IO uint32_t MACA2HR;
838 __IO uint32_t MACA2LR;
839 __IO uint32_t MACA3HR;
840 __IO uint32_t MACA3LR;
841 uint32_t RESERVED14[248];
842 __IO uint32_t MMCCR;
843 __IO uint32_t MMCRIR;
844 __IO uint32_t MMCTIR;
845 __IO uint32_t MMCRIMR;
846 __IO uint32_t MMCTIMR;
847 uint32_t RESERVED15[14];
848 __IO uint32_t MMCTSCGPR;
849 __IO uint32_t MMCTMCGPR;
850 uint32_t RESERVED16[5];
851 __IO uint32_t MMCTPCGR;
852 uint32_t RESERVED17[10];
853 __IO uint32_t MMCRCRCEPR;
854 __IO uint32_t MMCRAEPR;
855 uint32_t RESERVED18[10];
856 __IO uint32_t MMCRUPGR;
857 uint32_t RESERVED19[9];
858 __IO uint32_t MMCTLPIMSTR;
859 __IO uint32_t MMCTLPITCR;
860 __IO uint32_t MMCRLPIMSTR;
861 __IO uint32_t MMCRLPITCR;
862 uint32_t RESERVED20[65];
863 __IO uint32_t MACL3L4C0R;
864 __IO uint32_t MACL4A0R;
865 uint32_t RESERVED21[2];
866 __IO uint32_t MACL3A0R0R;
867 __IO uint32_t MACL3A1R0R;
868 __IO uint32_t MACL3A2R0R;
869 __IO uint32_t MACL3A3R0R;
870 uint32_t RESERVED22[4];
871 __IO uint32_t MACL3L4C1R;
872 __IO uint32_t MACL4A1R;
873 uint32_t RESERVED23[2];
874 __IO uint32_t MACL3A0R1R;
875 __IO uint32_t MACL3A1R1R;
876 __IO uint32_t MACL3A2R1R;
877 __IO uint32_t MACL3A3R1R;
878 uint32_t RESERVED24[108];
879 __IO uint32_t MACTSCR;
880 __IO uint32_t MACSSIR;
881 __IO uint32_t MACSTSR;
882 __IO uint32_t MACSTNR;
883 __IO uint32_t MACSTSUR;
884 __IO uint32_t MACSTNUR;
885 __IO uint32_t MACTSAR;
886 uint32_t RESERVED25;
887 __IO uint32_t MACTSSR;
888 uint32_t RESERVED26[3];
889 __IO uint32_t MACTTSSNR;
890 __IO uint32_t MACTTSSSR;
891 uint32_t RESERVED27[2];
892 __IO uint32_t MACACR;
893 uint32_t RESERVED28;
894 __IO uint32_t MACATSNR;
895 __IO uint32_t MACATSSR;
896 __IO uint32_t MACTSIACR;
897 __IO uint32_t MACTSEACR;
898 __IO uint32_t MACTSICNR;
899 __IO uint32_t MACTSECNR;
900 uint32_t RESERVED29[4];
901 __IO uint32_t MACPPSCR;
902 uint32_t RESERVED30[3];
903 __IO uint32_t MACPPSTTSR;
904 __IO uint32_t MACPPSTTNR;
905 __IO uint32_t MACPPSIR;
906 __IO uint32_t MACPPSWR;
907 uint32_t RESERVED31[12];
908 __IO uint32_t MACPOCR;
909 __IO uint32_t MACSPI0R;
910 __IO uint32_t MACSPI1R;
911 __IO uint32_t MACSPI2R;
912 __IO uint32_t MACLMIR;
913 uint32_t RESERVED32[11];
914 __IO uint32_t MTLOMR;
915 uint32_t RESERVED33[7];
916 __IO uint32_t MTLISR;
917 uint32_t RESERVED34[55];
918 __IO uint32_t MTLTQOMR;
919 __IO uint32_t MTLTQUR;
920 __IO uint32_t MTLTQDR;
921 uint32_t RESERVED35[8];
922 __IO uint32_t MTLQICSR;
923 __IO uint32_t MTLRQOMR;
924 __IO uint32_t MTLRQMPOCR;
925 __IO uint32_t MTLRQDR;
926 uint32_t RESERVED36[177];
927 __IO uint32_t DMAMR;
928 __IO uint32_t DMASBMR;
929 __IO uint32_t DMAISR;
930 __IO uint32_t DMADSR;
931 uint32_t RESERVED37[60];
932 __IO uint32_t DMACCR;
933 __IO uint32_t DMACTCR;
934 __IO uint32_t DMACRCR;
935 uint32_t RESERVED38[2];
936 __IO uint32_t DMACTDLAR;
937 uint32_t RESERVED39;
938 __IO uint32_t DMACRDLAR;
939 __IO uint32_t DMACTDTPR;
940 uint32_t RESERVED40;
941 __IO uint32_t DMACRDTPR;
942 __IO uint32_t DMACTDRLR;
943 __IO uint32_t DMACRDRLR;
944 __IO uint32_t DMACIER;
945 __IO uint32_t DMACRIWTR;
946__IO uint32_t DMACSFCSR;
947 uint32_t RESERVED41;
948 __IO uint32_t DMACCATDR;
949 uint32_t RESERVED42;
950 __IO uint32_t DMACCARDR;
951 uint32_t RESERVED43;
952 __IO uint32_t DMACCATBR;
953 uint32_t RESERVED44;
954 __IO uint32_t DMACCARBR;
955 __IO uint32_t DMACSR;
956uint32_t RESERVED45[2];
957__IO uint32_t DMACMFCR;
958}ETH_TypeDef;
963typedef struct
964{
965__IO uint32_t RTSR1;
966__IO uint32_t FTSR1;
967__IO uint32_t SWIER1;
968__IO uint32_t D3PMR1;
969__IO uint32_t D3PCR1L;
970__IO uint32_t D3PCR1H;
971uint32_t RESERVED1[2];
972__IO uint32_t RTSR2;
973__IO uint32_t FTSR2;
974__IO uint32_t SWIER2;
975__IO uint32_t D3PMR2;
976__IO uint32_t D3PCR2L;
977__IO uint32_t D3PCR2H;
978uint32_t RESERVED2[2];
979__IO uint32_t RTSR3;
980__IO uint32_t FTSR3;
981__IO uint32_t SWIER3;
982__IO uint32_t D3PMR3;
983__IO uint32_t D3PCR3L;
984__IO uint32_t D3PCR3H;
985uint32_t RESERVED3[10];
986__IO uint32_t IMR1;
987__IO uint32_t EMR1;
988__IO uint32_t PR1;
989uint32_t RESERVED4;
990__IO uint32_t IMR2;
991__IO uint32_t EMR2;
992__IO uint32_t PR2;
993uint32_t RESERVED5;
994__IO uint32_t IMR3;
995__IO uint32_t EMR3;
996__IO uint32_t PR3;
997uint32_t RESERVED6[5];
998__IO uint32_t C2IMR1;
999__IO uint32_t C2EMR1;
1000__IO uint32_t C2PR1;
1001uint32_t RESERVED7;
1002__IO uint32_t C2IMR2;
1003__IO uint32_t C2EMR2;
1004__IO uint32_t C2PR2;
1005uint32_t RESERVED8;
1006__IO uint32_t C2IMR3;
1007__IO uint32_t C2EMR3;
1008__IO uint32_t C2PR3;
1010}EXTI_TypeDef;
1011
1021typedef struct
1022{
1023__IO uint32_t IMR1;
1024__IO uint32_t EMR1;
1025__IO uint32_t PR1;
1026uint32_t RESERVED1;
1027__IO uint32_t IMR2;
1028__IO uint32_t EMR2;
1029__IO uint32_t PR2;
1030uint32_t RESERVED2;
1031__IO uint32_t IMR3;
1032__IO uint32_t EMR3;
1033__IO uint32_t PR3;
1034}EXTI_Core_TypeDef;
1035
1036
1041typedef struct
1042{
1043 __IO uint32_t ACR;
1044 __IO uint32_t KEYR1;
1045 __IO uint32_t OPTKEYR;
1046 __IO uint32_t CR1;
1047 __IO uint32_t SR1;
1048 __IO uint32_t CCR1;
1049 __IO uint32_t OPTCR;
1050 __IO uint32_t OPTSR_CUR;
1051 __IO uint32_t OPTSR_PRG;
1052 __IO uint32_t OPTCCR;
1053 __IO uint32_t PRAR_CUR1;
1054 __IO uint32_t PRAR_PRG1;
1055 __IO uint32_t SCAR_CUR1;
1056 __IO uint32_t SCAR_PRG1;
1057 __IO uint32_t WPSN_CUR1;
1058 __IO uint32_t WPSN_PRG1;
1059 __IO uint32_t BOOT7_CUR;
1060 __IO uint32_t BOOT7_PRG;
1061 __IO uint32_t BOOT4_CUR;
1062 __IO uint32_t BOOT4_PRG;
1063 __IO uint32_t CRCCR1;
1064 __IO uint32_t CRCSADD1;
1065 __IO uint32_t CRCEADD1;
1066 __IO uint32_t CRCDATA;
1067 __IO uint32_t ECC_FA1;
1068 uint32_t RESERVED1[40];
1069 __IO uint32_t KEYR2;
1070 uint32_t RESERVED2;
1071 __IO uint32_t CR2;
1072 __IO uint32_t SR2;
1073 __IO uint32_t CCR2;
1074 uint32_t RESERVED3[4];
1075 __IO uint32_t PRAR_CUR2;
1076 __IO uint32_t PRAR_PRG2;
1077 __IO uint32_t SCAR_CUR2;
1078 __IO uint32_t SCAR_PRG2;
1079 __IO uint32_t WPSN_CUR2;
1080 __IO uint32_t WPSN_PRG2;
1081 uint32_t RESERVED4[4];
1082 __IO uint32_t CRCCR2;
1083 __IO uint32_t CRCSADD2;
1084 __IO uint32_t CRCEADD2;
1085 __IO uint32_t CRCDATA2;
1086 __IO uint32_t ECC_FA2;
1087} FLASH_TypeDef;
1088
1093typedef struct
1094{
1095 __IO uint32_t BTCR[8];
1096} FMC_Bank1_TypeDef;
1097
1102typedef struct
1103{
1104 __IO uint32_t BWTR[7];
1105} FMC_Bank1E_TypeDef;
1106
1111typedef struct
1112{
1113 __IO uint32_t PCR2;
1114 __IO uint32_t SR2;
1115 __IO uint32_t PMEM2;
1116 __IO uint32_t PATT2;
1117 uint32_t RESERVED0;
1118 __IO uint32_t ECCR2;
1119} FMC_Bank2_TypeDef;
1120
1125typedef struct
1126{
1127 __IO uint32_t PCR;
1128 __IO uint32_t SR;
1129 __IO uint32_t PMEM;
1130 __IO uint32_t PATT;
1131 uint32_t RESERVED;
1132 __IO uint32_t ECCR;
1133} FMC_Bank3_TypeDef;
1134
1140typedef struct
1141{
1142 __IO uint32_t SDCR[2];
1143 __IO uint32_t SDTR[2];
1144 __IO uint32_t SDCMR;
1145 __IO uint32_t SDRTR;
1146 __IO uint32_t SDSR;
1147} FMC_Bank5_6_TypeDef;
1148
1153typedef struct
1154{
1155 __IO uint32_t MODER;
1156 __IO uint32_t OTYPER;
1157 __IO uint32_t OSPEEDR;
1158 __IO uint32_t PUPDR;
1159 __IO uint32_t IDR;
1160 __IO uint32_t ODR;
1161 __IO uint32_t BSRR;
1162 __IO uint32_t LCKR;
1163 __IO uint32_t AFR[2];
1164} GPIO_TypeDef;
1165
1170typedef struct
1171{
1172 __IO uint32_t CSR;
1173 __IO uint32_t OTR;
1174 __IO uint32_t HSOTR;
1175} OPAMP_TypeDef;
1176
1181typedef struct
1182{
1183 uint32_t RESERVED1;
1184 __IO uint32_t PMCR;
1185 __IO uint32_t EXTICR[4];
1186 __IO uint32_t CFGR;
1187 uint32_t RESERVED2;
1188 __IO uint32_t CCCSR;
1189 __IO uint32_t CCVR;
1190 __IO uint32_t CCCR;
1191 __IO uint32_t PWRCR;
1192 uint32_t RESERVED3[61];
1193 __IO uint32_t PKGR;
1194 uint32_t RESERVED4[118];
1195 __IO uint32_t UR0;
1196 __IO uint32_t UR1;
1197 __IO uint32_t UR2;
1198 __IO uint32_t UR3;
1199 __IO uint32_t UR4;
1200 __IO uint32_t UR5;
1201 __IO uint32_t UR6;
1202 __IO uint32_t UR7;
1203 __IO uint32_t UR8;
1204 __IO uint32_t UR9;
1205 __IO uint32_t UR10;
1206 __IO uint32_t UR11;
1207 __IO uint32_t UR12;
1208 __IO uint32_t UR13;
1209 __IO uint32_t UR14;
1210 __IO uint32_t UR15;
1211 __IO uint32_t UR16;
1212 __IO uint32_t UR17;
1214} SYSCFG_TypeDef;
1215
1220typedef struct
1221{
1222 __IO uint32_t CR1;
1223 __IO uint32_t CR2;
1224 __IO uint32_t OAR1;
1225 __IO uint32_t OAR2;
1226 __IO uint32_t TIMINGR;
1227 __IO uint32_t TIMEOUTR;
1228 __IO uint32_t ISR;
1229 __IO uint32_t ICR;
1230 __IO uint32_t PECR;
1231 __IO uint32_t RXDR;
1232 __IO uint32_t TXDR;
1233} I2C_TypeDef;
1234
1239typedef struct
1240{
1241 __IO uint32_t KR;
1242 __IO uint32_t PR;
1243 __IO uint32_t RLR;
1244 __IO uint32_t SR;
1245 __IO uint32_t WINR;
1246} IWDG_TypeDef;
1247
1248
1252typedef struct
1253{
1254 __IO uint32_t CONFR0;
1255 __IO uint32_t CONFR1;
1256 __IO uint32_t CONFR2;
1257 __IO uint32_t CONFR3;
1258 __IO uint32_t CONFR4;
1259 __IO uint32_t CONFR5;
1260 __IO uint32_t CONFR6;
1261 __IO uint32_t CONFR7;
1262 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
1263 __IO uint32_t CR;
1264 __IO uint32_t SR;
1265 __IO uint32_t CFR;
1266 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
1267 __IO uint32_t DIR;
1268 __IO uint32_t DOR;
1269 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
1270 __IO uint32_t QMEM0[16];
1271 __IO uint32_t QMEM1[16];
1272 __IO uint32_t QMEM2[16];
1273 __IO uint32_t QMEM3[16];
1274 __IO uint32_t HUFFMIN[16];
1275 __IO uint32_t HUFFBASE[32];
1276 __IO uint32_t HUFFSYMB[84];
1277 __IO uint32_t DHTMEM[103];
1278 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1279 __IO uint32_t HUFFENC_AC0[88];
1280 __IO uint32_t HUFFENC_AC1[88];
1281 __IO uint32_t HUFFENC_DC0[8];
1282 __IO uint32_t HUFFENC_DC1[8];
1284} JPEG_TypeDef;
1285
1290typedef struct
1291{
1292 uint32_t RESERVED0[2];
1293 __IO uint32_t SSCR;
1294 __IO uint32_t BPCR;
1295 __IO uint32_t AWCR;
1296 __IO uint32_t TWCR;
1297 __IO uint32_t GCR;
1298 uint32_t RESERVED1[2];
1299 __IO uint32_t SRCR;
1300 uint32_t RESERVED2[1];
1301 __IO uint32_t BCCR;
1302 uint32_t RESERVED3[1];
1303 __IO uint32_t IER;
1304 __IO uint32_t ISR;
1305 __IO uint32_t ICR;
1306 __IO uint32_t LIPCR;
1307 __IO uint32_t CPSR;
1308 __IO uint32_t CDSR;
1309} LTDC_TypeDef;
1310
1315typedef struct
1316{
1317 __IO uint32_t CR;
1318 __IO uint32_t WHPCR;
1319 __IO uint32_t WVPCR;
1320 __IO uint32_t CKCR;
1321 __IO uint32_t PFCR;
1322 __IO uint32_t CACR;
1323 __IO uint32_t DCCR;
1324 __IO uint32_t BFCR;
1325 uint32_t RESERVED0[2];
1326 __IO uint32_t CFBAR;
1327 __IO uint32_t CFBLR;
1328 __IO uint32_t CFBLNR;
1329 uint32_t RESERVED1[3];
1330 __IO uint32_t CLUTWR;
1332} LTDC_Layer_TypeDef;
1333
1338typedef struct
1339{
1340 __IO uint32_t CR1;
1341 __IO uint32_t CSR1;
1342 __IO uint32_t CR2;
1343 __IO uint32_t CR3;
1344 __IO uint32_t CPUCR;
1345 __IO uint32_t CPU2CR;
1346 __IO uint32_t D3CR;
1347 uint32_t RESERVED1;
1348 __IO uint32_t WKUPCR;
1349 __IO uint32_t WKUPFR;
1350 __IO uint32_t WKUPEPR;
1351} PWR_TypeDef;
1352
1357typedef struct
1358{
1359 __IO uint32_t CR;
1360 __IO uint32_t HSICFGR;
1361 __IO uint32_t CRRCR;
1362 __IO uint32_t CSICFGR;
1363 __IO uint32_t CFGR;
1364 uint32_t RESERVED1;
1365 __IO uint32_t D1CFGR;
1366 __IO uint32_t D2CFGR;
1367 __IO uint32_t D3CFGR;
1368 uint32_t RESERVED2;
1369 __IO uint32_t PLLCKSELR;
1370 __IO uint32_t PLLCFGR;
1371 __IO uint32_t PLL1DIVR;
1372 __IO uint32_t PLL1FRACR;
1373 __IO uint32_t PLL2DIVR;
1374 __IO uint32_t PLL2FRACR;
1375 __IO uint32_t PLL3DIVR;
1376 __IO uint32_t PLL3FRACR;
1377 uint32_t RESERVED3;
1378 __IO uint32_t D1CCIPR;
1379 __IO uint32_t D2CCIP1R;
1380 __IO uint32_t D2CCIP2R;
1381 __IO uint32_t D3CCIPR;
1382 uint32_t RESERVED4;
1383 __IO uint32_t CIER;
1384 __IO uint32_t CIFR;
1385 __IO uint32_t CICR;
1386 uint32_t RESERVED5;
1387 __IO uint32_t BDCR;
1388 __IO uint32_t CSR;
1389 uint32_t RESERVED6;
1390 __IO uint32_t AHB3RSTR;
1391 __IO uint32_t AHB1RSTR;
1392 __IO uint32_t AHB2RSTR;
1393 __IO uint32_t AHB4RSTR;
1394 __IO uint32_t APB3RSTR;
1395 __IO uint32_t APB1LRSTR;
1396 __IO uint32_t APB1HRSTR;
1397 __IO uint32_t APB2RSTR;
1398 __IO uint32_t APB4RSTR;
1399 __IO uint32_t GCR;
1400 uint32_t RESERVED8;
1401 __IO uint32_t D3AMR;
1402 uint32_t RESERVED11[9];
1403 __IO uint32_t RSR;
1404 __IO uint32_t AHB3ENR;
1405 __IO uint32_t AHB1ENR;
1406 __IO uint32_t AHB2ENR;
1407 __IO uint32_t AHB4ENR;
1408 __IO uint32_t APB3ENR;
1409 __IO uint32_t APB1LENR;
1410 __IO uint32_t APB1HENR;
1411 __IO uint32_t APB2ENR;
1412 __IO uint32_t APB4ENR;
1413 uint32_t RESERVED12;
1414 __IO uint32_t AHB3LPENR;
1415 __IO uint32_t AHB1LPENR;
1416 __IO uint32_t AHB2LPENR;
1417 __IO uint32_t AHB4LPENR;
1418 __IO uint32_t APB3LPENR;
1419 __IO uint32_t APB1LLPENR;
1420 __IO uint32_t APB1HLPENR;
1421 __IO uint32_t APB2LPENR;
1422 __IO uint32_t APB4LPENR;
1423 uint32_t RESERVED13[4];
1425} RCC_TypeDef;
1426
1427typedef struct
1428{
1429 __IO uint32_t RSR;
1430 __IO uint32_t AHB3ENR;
1431 __IO uint32_t AHB1ENR;
1432 __IO uint32_t AHB2ENR;
1433 __IO uint32_t AHB4ENR;
1434 __IO uint32_t APB3ENR;
1435 __IO uint32_t APB1LENR;
1436 __IO uint32_t APB1HENR;
1437 __IO uint32_t APB2ENR;
1438 __IO uint32_t APB4ENR;
1439 uint32_t RESERVED9;
1440 __IO uint32_t AHB3LPENR;
1441 __IO uint32_t AHB1LPENR;
1442 __IO uint32_t AHB2LPENR;
1443 __IO uint32_t AHB4LPENR;
1444 __IO uint32_t APB3LPENR;
1445 __IO uint32_t APB1LLPENR;
1446 __IO uint32_t APB1HLPENR;
1447 __IO uint32_t APB2LPENR;
1448 __IO uint32_t APB4LPENR;
1449 uint32_t RESERVED10[4];
1451} RCC_Core_TypeDef;
1452
1456typedef struct
1457{
1458 __IO uint32_t TR;
1459 __IO uint32_t DR;
1460 __IO uint32_t CR;
1461 __IO uint32_t ISR;
1462 __IO uint32_t PRER;
1463 __IO uint32_t WUTR;
1464 uint32_t RESERVED;
1465 __IO uint32_t ALRMAR;
1466 __IO uint32_t ALRMBR;
1467 __IO uint32_t WPR;
1468 __IO uint32_t SSR;
1469 __IO uint32_t SHIFTR;
1470 __IO uint32_t TSTR;
1471 __IO uint32_t TSDR;
1472 __IO uint32_t TSSSR;
1473 __IO uint32_t CALR;
1474 __IO uint32_t TAMPCR;
1475 __IO uint32_t ALRMASSR;
1476 __IO uint32_t ALRMBSSR;
1477 __IO uint32_t OR;
1478 __IO uint32_t BKP0R;
1479 __IO uint32_t BKP1R;
1480 __IO uint32_t BKP2R;
1481 __IO uint32_t BKP3R;
1482 __IO uint32_t BKP4R;
1483 __IO uint32_t BKP5R;
1484 __IO uint32_t BKP6R;
1485 __IO uint32_t BKP7R;
1486 __IO uint32_t BKP8R;
1487 __IO uint32_t BKP9R;
1488 __IO uint32_t BKP10R;
1489 __IO uint32_t BKP11R;
1490 __IO uint32_t BKP12R;
1491 __IO uint32_t BKP13R;
1492 __IO uint32_t BKP14R;
1493 __IO uint32_t BKP15R;
1494 __IO uint32_t BKP16R;
1495 __IO uint32_t BKP17R;
1496 __IO uint32_t BKP18R;
1497 __IO uint32_t BKP19R;
1498 __IO uint32_t BKP20R;
1499 __IO uint32_t BKP21R;
1500 __IO uint32_t BKP22R;
1501 __IO uint32_t BKP23R;
1502 __IO uint32_t BKP24R;
1503 __IO uint32_t BKP25R;
1504 __IO uint32_t BKP26R;
1505 __IO uint32_t BKP27R;
1506 __IO uint32_t BKP28R;
1507 __IO uint32_t BKP29R;
1508 __IO uint32_t BKP30R;
1509 __IO uint32_t BKP31R;
1510} RTC_TypeDef;
1511
1516typedef struct
1517{
1518 __IO uint32_t GCR;
1519 uint32_t RESERVED0[16];
1520 __IO uint32_t PDMCR;
1521 __IO uint32_t PDMDLY;
1522} SAI_TypeDef;
1523
1524typedef struct
1525{
1526 __IO uint32_t CR1;
1527 __IO uint32_t CR2;
1528 __IO uint32_t FRCR;
1529 __IO uint32_t SLOTR;
1530 __IO uint32_t IMR;
1531 __IO uint32_t SR;
1532 __IO uint32_t CLRFR;
1533 __IO uint32_t DR;
1534} SAI_Block_TypeDef;
1535
1540typedef struct
1541{
1542 __IO uint32_t CR;
1543 __IO uint32_t IMR;
1544 __IO uint32_t SR;
1545 __IO uint32_t IFCR;
1546 __IO uint32_t DR;
1547 __IO uint32_t CSR;
1548 __IO uint32_t DIR;
1549 uint32_t RESERVED2;
1550} SPDIFRX_TypeDef;
1551
1552
1557typedef struct
1558{
1559 __IO uint32_t POWER;
1560 __IO uint32_t CLKCR;
1561 __IO uint32_t ARG;
1562 __IO uint32_t CMD;
1563 __I uint32_t RESPCMD;
1564 __I uint32_t RESP1;
1565 __I uint32_t RESP2;
1566 __I uint32_t RESP3;
1567 __I uint32_t RESP4;
1568 __IO uint32_t DTIMER;
1569 __IO uint32_t DLEN;
1570 __IO uint32_t DCTRL;
1571 __I uint32_t DCOUNT;
1572 __I uint32_t STA;
1573 __IO uint32_t ICR;
1574 __IO uint32_t MASK;
1575 __IO uint32_t ACKTIME;
1576 uint32_t RESERVED0[3];
1577 __IO uint32_t IDMACTRL;
1578 __IO uint32_t IDMABSIZE;
1579 __IO uint32_t IDMABASE0;
1580 __IO uint32_t IDMABASE1;
1581 uint32_t RESERVED1[8];
1582 __IO uint32_t FIFO;
1583 uint32_t RESERVED2[222];
1584 __IO uint32_t IPVR;
1585} SDMMC_TypeDef;
1586
1587
1592typedef struct
1593{
1594 __IO uint32_t CR;
1595 __IO uint32_t CFGR;
1596} DLYB_TypeDef;
1597
1602typedef struct
1603{
1604 __IO uint32_t R[32];
1605 __IO uint32_t RLR[32];
1606 __IO uint32_t C1IER;
1607 __IO uint32_t C1ICR;
1608 __IO uint32_t C1ISR;
1609 __IO uint32_t C1MISR;
1610 __IO uint32_t C2IER;
1611 __IO uint32_t C2ICR;
1612 __IO uint32_t C2ISR;
1613 __IO uint32_t C2MISR;
1614 uint32_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
1615 __IO uint32_t CR;
1616 __IO uint32_t KEYR;
1618} HSEM_TypeDef;
1619
1620typedef struct
1621{
1622 __IO uint32_t IER;
1623 __IO uint32_t ICR;
1624 __IO uint32_t ISR;
1625 __IO uint32_t MISR;
1626} HSEM_Common_TypeDef;
1627
1632typedef struct
1633{
1634 __IO uint32_t CR1;
1635 __IO uint32_t CR2;
1636 __IO uint32_t CFG1;
1637 __IO uint32_t CFG2;
1638 __IO uint32_t IER;
1639 __IO uint32_t SR;
1640 __IO uint32_t IFCR;
1641 uint32_t RESERVED0;
1642 __IO uint32_t TXDR;
1643 uint32_t RESERVED1[3];
1644 __IO uint32_t RXDR;
1645 uint32_t RESERVED2[3];
1646 __IO uint32_t CRCPOLY;
1647 __IO uint32_t TXCRC;
1648 __IO uint32_t RXCRC;
1649 __IO uint32_t UDRDR;
1650 __IO uint32_t I2SCFGR;
1652} SPI_TypeDef;
1657typedef struct
1658{
1659 __IO uint32_t CR;
1660 __IO uint32_t DCR;
1661 __IO uint32_t SR;
1662 __IO uint32_t FCR;
1663 __IO uint32_t DLR;
1664 __IO uint32_t CCR;
1665 __IO uint32_t AR;
1666 __IO uint32_t ABR;
1667 __IO uint32_t DR;
1668 __IO uint32_t PSMKR;
1669 __IO uint32_t PSMAR;
1670 __IO uint32_t PIR;
1671 __IO uint32_t LPTR;
1672} QUADSPI_TypeDef;
1673
1678typedef struct
1679{
1680 __IO uint32_t CR1;
1681 __IO uint32_t CR2;
1682 __IO uint32_t SMCR;
1683 __IO uint32_t DIER;
1684 __IO uint32_t SR;
1685 __IO uint32_t EGR;
1686 __IO uint32_t CCMR1;
1687 __IO uint32_t CCMR2;
1688 __IO uint32_t CCER;
1689 __IO uint32_t CNT;
1690 __IO uint32_t PSC;
1691 __IO uint32_t ARR;
1692 __IO uint32_t RCR;
1693 __IO uint32_t CCR1;
1694 __IO uint32_t CCR2;
1695 __IO uint32_t CCR3;
1696 __IO uint32_t CCR4;
1697 __IO uint32_t BDTR;
1698 __IO uint32_t DCR;
1699 __IO uint32_t DMAR;
1700 uint32_t RESERVED1;
1701 __IO uint32_t CCMR3;
1702 __IO uint32_t CCR5;
1703 __IO uint32_t CCR6;
1704 __IO uint32_t AF1;
1705 __IO uint32_t AF2;
1706 __IO uint32_t TISEL;
1707} TIM_TypeDef;
1708
1712typedef struct
1713{
1714 __IO uint32_t ISR;
1715 __IO uint32_t ICR;
1716 __IO uint32_t IER;
1717 __IO uint32_t CFGR;
1718 __IO uint32_t CR;
1719 __IO uint32_t CMP;
1720 __IO uint32_t ARR;
1721 __IO uint32_t CNT;
1722 uint32_t RESERVED1;
1723 __IO uint32_t CFGR2;
1724} LPTIM_TypeDef;
1725
1729typedef struct
1730{
1731 __IO uint32_t SR;
1732 __IO uint32_t ICFR;
1733 __IO uint32_t OR;
1734} COMPOPT_TypeDef;
1735
1736typedef struct
1737{
1738 __IO uint32_t CFGR;
1739} COMP_TypeDef;
1740
1741typedef struct
1742{
1743 __IO uint32_t CFGR;
1744} COMP_Common_TypeDef;
1749typedef struct
1750{
1751 __IO uint32_t CR1;
1752 __IO uint32_t CR2;
1753 __IO uint32_t CR3;
1754 __IO uint32_t BRR;
1755 __IO uint32_t GTPR;
1756 __IO uint32_t RTOR;
1757 __IO uint32_t RQR;
1758 __IO uint32_t ISR;
1759 __IO uint32_t ICR;
1760 __IO uint32_t RDR;
1761 __IO uint32_t TDR;
1762 __IO uint32_t PRESC;
1763} USART_TypeDef;
1764
1768typedef struct
1769{
1770 __IO uint32_t CR;
1771 __IO uint32_t BRR;
1772 uint32_t RESERVED1;
1773 __IO uint32_t ISR;
1774 __IO uint32_t ICR;
1775 __IO uint32_t IER;
1776 __IO uint32_t RFL;
1777 __IO uint32_t TDR;
1778 __IO uint32_t RDR;
1779 __IO uint32_t OR;
1780} SWPMI_TypeDef;
1781
1786typedef struct
1787{
1788 __IO uint32_t CR;
1789 __IO uint32_t CFR;
1790 __IO uint32_t SR;
1791} WWDG_TypeDef;
1792
1793
1797typedef struct
1798{
1799 __IO uint32_t CR;
1800 __IO uint32_t SR;
1801 __IO uint32_t FAR;
1802 __IO uint32_t FDRL;
1803 __IO uint32_t FDRH;
1804 __IO uint32_t FECR;
1805} RAMECC_MonitorTypeDef;
1806
1807typedef struct
1808{
1809 __IO uint32_t IER;
1810} RAMECC_TypeDef;
1820/* HRTIM master registers definition */
1821typedef struct
1822{
1823 __IO uint32_t MCR;
1824 __IO uint32_t MISR;
1825 __IO uint32_t MICR;
1826 __IO uint32_t MDIER;
1827 __IO uint32_t MCNTR;
1828 __IO uint32_t MPER;
1829 __IO uint32_t MREP;
1830 __IO uint32_t MCMP1R;
1831 uint32_t RESERVED0;
1832 __IO uint32_t MCMP2R;
1833 __IO uint32_t MCMP3R;
1834 __IO uint32_t MCMP4R;
1835 uint32_t RESERVED1[20];
1836}HRTIM_Master_TypeDef;
1837
1838/* HRTIM Timer A to E registers definition */
1839typedef struct
1840{
1841 __IO uint32_t TIMxCR;
1842 __IO uint32_t TIMxISR;
1843 __IO uint32_t TIMxICR;
1844 __IO uint32_t TIMxDIER;
1845 __IO uint32_t CNTxR;
1846 __IO uint32_t PERxR;
1847 __IO uint32_t REPxR;
1848 __IO uint32_t CMP1xR;
1849 __IO uint32_t CMP1CxR;
1850 __IO uint32_t CMP2xR;
1851 __IO uint32_t CMP3xR;
1852 __IO uint32_t CMP4xR;
1853 __IO uint32_t CPT1xR;
1854 __IO uint32_t CPT2xR;
1855 __IO uint32_t DTxR;
1856 __IO uint32_t SETx1R;
1857 __IO uint32_t RSTx1R;
1858 __IO uint32_t SETx2R;
1859 __IO uint32_t RSTx2R;
1860 __IO uint32_t EEFxR1;
1861 __IO uint32_t EEFxR2;
1862 __IO uint32_t RSTxR;
1863 __IO uint32_t CHPxR;
1864 __IO uint32_t CPT1xCR;
1865 __IO uint32_t CPT2xCR;
1866 __IO uint32_t OUTxR;
1867 __IO uint32_t FLTxR;
1868 uint32_t RESERVED0[5];
1869}HRTIM_Timerx_TypeDef;
1870
1871/* HRTIM common register definition */
1872typedef struct
1873{
1874 __IO uint32_t CR1;
1875 __IO uint32_t CR2;
1876 __IO uint32_t ISR;
1877 __IO uint32_t ICR;
1878 __IO uint32_t IER;
1879 __IO uint32_t OENR;
1880 __IO uint32_t ODISR;
1881 __IO uint32_t ODSR;
1882 __IO uint32_t BMCR;
1883 __IO uint32_t BMTRGR;
1884 __IO uint32_t BMCMPR;
1885 __IO uint32_t BMPER;
1886 __IO uint32_t EECR1;
1887 __IO uint32_t EECR2;
1888 __IO uint32_t EECR3;
1889 __IO uint32_t ADC1R;
1890 __IO uint32_t ADC2R;
1891 __IO uint32_t ADC3R;
1892 __IO uint32_t ADC4R;
1893 __IO uint32_t RESERVED0;
1894 __IO uint32_t FLTINR1;
1895 __IO uint32_t FLTINR2;
1896 __IO uint32_t BDMUPR;
1897 __IO uint32_t BDTAUPR;
1898 __IO uint32_t BDTBUPR;
1899 __IO uint32_t BDTCUPR;
1900 __IO uint32_t BDTDUPR;
1901 __IO uint32_t BDTEUPR;
1902 __IO uint32_t BDMADR;
1903}HRTIM_Common_TypeDef;
1904
1905/* HRTIM register definition */
1906typedef struct {
1907 HRTIM_Master_TypeDef sMasterRegs;
1908 HRTIM_Timerx_TypeDef sTimerxRegs[5];
1909 uint32_t RESERVED0[32];
1910 HRTIM_Common_TypeDef sCommonRegs;
1911}HRTIM_TypeDef;
1916typedef struct
1917{
1918 __IO uint32_t CR;
1919 __IO uint32_t SR;
1920 __IO uint32_t DR;
1921} RNG_TypeDef;
1922
1927typedef struct
1928{
1929 __IO uint32_t CR;
1930 __IO uint32_t WRFR;
1931 __IO uint32_t CWRFR;
1932 __IO uint32_t RDFR;
1933 __IO uint32_t CRDFR;
1934 __IO uint32_t SR;
1935 __IO uint32_t CLRFR;
1936 uint32_t RESERVED[57];
1937 __IO uint32_t DINR0;
1938 __IO uint32_t DINR1;
1939 __IO uint32_t DINR2;
1940 __IO uint32_t DINR3;
1941 __IO uint32_t DINR4;
1942 __IO uint32_t DINR5;
1943 __IO uint32_t DINR6;
1944 __IO uint32_t DINR7;
1945 __IO uint32_t DINR8;
1946 __IO uint32_t DINR9;
1947 __IO uint32_t DINR10;
1948 __IO uint32_t DINR11;
1949 __IO uint32_t DINR12;
1950 __IO uint32_t DINR13;
1951 __IO uint32_t DINR14;
1952 __IO uint32_t DINR15;
1953 __IO uint32_t DINR16;
1954 __IO uint32_t DINR17;
1955 __IO uint32_t DINR18;
1956 __IO uint32_t DINR19;
1957 __IO uint32_t DINR20;
1958 __IO uint32_t DINR21;
1959 __IO uint32_t DINR22;
1960 __IO uint32_t DINR23;
1961 __IO uint32_t DINR24;
1962 __IO uint32_t DINR25;
1963 __IO uint32_t DINR26;
1964 __IO uint32_t DINR27;
1965 __IO uint32_t DINR28;
1966 __IO uint32_t DINR29;
1967 __IO uint32_t DINR30;
1968 __IO uint32_t DINR31;
1969 __IO uint32_t DOUTR0;
1970 __IO uint32_t DOUTR1;
1971 __IO uint32_t DOUTR2;
1972 __IO uint32_t DOUTR3;
1973 __IO uint32_t DOUTR4;
1974 __IO uint32_t DOUTR5;
1975 __IO uint32_t DOUTR6;
1976 __IO uint32_t DOUTR7;
1977 __IO uint32_t DOUTR8;
1978 __IO uint32_t DOUTR9;
1979 __IO uint32_t DOUTR10;
1980 __IO uint32_t DOUTR11;
1981 __IO uint32_t DOUTR12;
1982 __IO uint32_t DOUTR13;
1983 __IO uint32_t DOUTR14;
1984 __IO uint32_t DOUTR15;
1985 __IO uint32_t DOUTR16;
1986 __IO uint32_t DOUTR17;
1987 __IO uint32_t DOUTR18;
1988 __IO uint32_t DOUTR19;
1989 __IO uint32_t DOUTR20;
1990 __IO uint32_t DOUTR21;
1991 __IO uint32_t DOUTR22;
1992 __IO uint32_t DOUTR23;
1993 __IO uint32_t DOUTR24;
1994 __IO uint32_t DOUTR25;
1995 __IO uint32_t DOUTR26;
1996 __IO uint32_t DOUTR27;
1997 __IO uint32_t DOUTR28;
1998 __IO uint32_t DOUTR29;
1999 __IO uint32_t DOUTR30;
2000 __IO uint32_t DOUTR31;
2001} MDIOS_TypeDef;
2002
2003
2007typedef struct
2008{
2009 __IO uint32_t GOTGCTL;
2010 __IO uint32_t GOTGINT;
2011 __IO uint32_t GAHBCFG;
2012 __IO uint32_t GUSBCFG;
2013 __IO uint32_t GRSTCTL;
2014 __IO uint32_t GINTSTS;
2015 __IO uint32_t GINTMSK;
2016 __IO uint32_t GRXSTSR;
2017 __IO uint32_t GRXSTSP;
2018 __IO uint32_t GRXFSIZ;
2019 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
2020 __IO uint32_t HNPTXSTS;
2021 uint32_t Reserved30[2];
2022 __IO uint32_t GCCFG;
2023 __IO uint32_t CID;
2024 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
2025 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
2026 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
2027 __IO uint32_t GHWCFG3;
2028 uint32_t Reserved6;
2029 __IO uint32_t GLPMCFG;
2030 __IO uint32_t GPWRDN;
2031 __IO uint32_t GDFIFOCFG;
2032 __IO uint32_t GADPCTL;
2033 uint32_t Reserved43[39];
2034 __IO uint32_t HPTXFSIZ;
2035 __IO uint32_t DIEPTXF[0x0F];
2036} USB_OTG_GlobalTypeDef;
2037
2038
2042typedef struct
2043{
2044 __IO uint32_t DCFG;
2045 __IO uint32_t DCTL;
2046 __IO uint32_t DSTS;
2047 uint32_t Reserved0C;
2048 __IO uint32_t DIEPMSK;
2049 __IO uint32_t DOEPMSK;
2050 __IO uint32_t DAINT;
2051 __IO uint32_t DAINTMSK;
2052 uint32_t Reserved20;
2053 uint32_t Reserved9;
2054 __IO uint32_t DVBUSDIS;
2055 __IO uint32_t DVBUSPULSE;
2056 __IO uint32_t DTHRCTL;
2057 __IO uint32_t DIEPEMPMSK;
2058 __IO uint32_t DEACHINT;
2059 __IO uint32_t DEACHMSK;
2060 uint32_t Reserved40;
2061 __IO uint32_t DINEP1MSK;
2062 uint32_t Reserved44[15];
2063 __IO uint32_t DOUTEP1MSK;
2064} USB_OTG_DeviceTypeDef;
2065
2066
2070typedef struct
2071{
2072 __IO uint32_t DIEPCTL;
2073 uint32_t Reserved04;
2074 __IO uint32_t DIEPINT;
2075 uint32_t Reserved0C;
2076 __IO uint32_t DIEPTSIZ;
2077 __IO uint32_t DIEPDMA;
2078 __IO uint32_t DTXFSTS;
2079 uint32_t Reserved18;
2080} USB_OTG_INEndpointTypeDef;
2081
2082
2086typedef struct
2087{
2088 __IO uint32_t DOEPCTL;
2089 uint32_t Reserved04;
2090 __IO uint32_t DOEPINT;
2091 uint32_t Reserved0C;
2092 __IO uint32_t DOEPTSIZ;
2093 __IO uint32_t DOEPDMA;
2094 uint32_t Reserved18[2];
2095} USB_OTG_OUTEndpointTypeDef;
2096
2097
2101typedef struct
2102{
2103 __IO uint32_t HCFG;
2104 __IO uint32_t HFIR;
2105 __IO uint32_t HFNUM;
2106 uint32_t Reserved40C;
2107 __IO uint32_t HPTXSTS;
2108 __IO uint32_t HAINT;
2109 __IO uint32_t HAINTMSK;
2110} USB_OTG_HostTypeDef;
2111
2115typedef struct
2116{
2117 __IO uint32_t HCCHAR;
2118 __IO uint32_t HCSPLT;
2119 __IO uint32_t HCINT;
2120 __IO uint32_t HCINTMSK;
2121 __IO uint32_t HCTSIZ;
2122 __IO uint32_t HCDMA;
2123 uint32_t Reserved[2];
2124} USB_OTG_HostChannelTypeDef;
2134typedef struct
2135{
2136 uint32_t RESERVED0[2036];
2137 __IO uint32_t AXI_PERIPH_ID_4;
2138 uint32_t AXI_PERIPH_ID_5;
2139 uint32_t AXI_PERIPH_ID_6;
2140 uint32_t AXI_PERIPH_ID_7;
2141 __IO uint32_t AXI_PERIPH_ID_0;
2142 __IO uint32_t AXI_PERIPH_ID_1;
2143 __IO uint32_t AXI_PERIPH_ID_2;
2144 __IO uint32_t AXI_PERIPH_ID_3;
2145 __IO uint32_t AXI_COMP_ID_0;
2146 __IO uint32_t AXI_COMP_ID_1;
2147 __IO uint32_t AXI_COMP_ID_2;
2148 __IO uint32_t AXI_COMP_ID_3;
2149 uint32_t RESERVED1[2];
2150 __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM;
2151 uint32_t RESERVED2[6];
2152 __IO uint32_t AXI_TARG1_FN_MOD2;
2153 uint32_t RESERVED3;
2154 __IO uint32_t AXI_TARG1_FN_MOD_LB;
2155 uint32_t RESERVED4[54];
2156 __IO uint32_t AXI_TARG1_FN_MOD;
2157 uint32_t RESERVED5[959];
2158 __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM;
2159 uint32_t RESERVED6[6];
2160 __IO uint32_t AXI_TARG2_FN_MOD2;
2161 uint32_t RESERVED7;
2162 __IO uint32_t AXI_TARG2_FN_MOD_LB;
2163 uint32_t RESERVED8[54];
2164 __IO uint32_t AXI_TARG2_FN_MOD;
2165 uint32_t RESERVED9[959];
2166 __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM;
2167 uint32_t RESERVED10[1023];
2168 __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM;
2169 uint32_t RESERVED11[1023];
2170 __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM;
2171 uint32_t RESERVED12[1023];
2172 __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM;
2173 uint32_t RESERVED13[1023];
2174 __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM;
2175 uint32_t RESERVED14[6];
2176 __IO uint32_t AXI_TARG7_FN_MOD2;
2177 uint32_t RESERVED15;
2178 __IO uint32_t AXI_TARG7_FN_MOD_LB;
2179 uint32_t RESERVED16[54];
2180 __IO uint32_t AXI_TARG7_FN_MOD;
2181 uint32_t RESERVED17[59334];
2182 __IO uint32_t AXI_INI1_FN_MOD2;
2183 __IO uint32_t AXI_INI1_FN_MOD_AHB;
2184 uint32_t RESERVED18[53];
2185 __IO uint32_t AXI_INI1_READ_QOS;
2186 __IO uint32_t AXI_INI1_WRITE_QOS;
2187 __IO uint32_t AXI_INI1_FN_MOD;
2188 uint32_t RESERVED19[1021];
2189 __IO uint32_t AXI_INI2_READ_QOS;
2190 __IO uint32_t AXI_INI2_WRITE_QOS;
2191 __IO uint32_t AXI_INI2_FN_MOD;
2192 uint32_t RESERVED20[966];
2193 __IO uint32_t AXI_INI3_FN_MOD2;
2194 __IO uint32_t AXI_INI3_FN_MOD_AHB;
2195 uint32_t RESERVED21[53];
2196 __IO uint32_t AXI_INI3_READ_QOS;
2197 __IO uint32_t AXI_INI3_WRITE_QOS;
2198 __IO uint32_t AXI_INI3_FN_MOD;
2199 uint32_t RESERVED22[1021];
2200 __IO uint32_t AXI_INI4_READ_QOS;
2201 __IO uint32_t AXI_INI4_WRITE_QOS;
2202 __IO uint32_t AXI_INI4_FN_MOD;
2203 uint32_t RESERVED23[1021];
2204 __IO uint32_t AXI_INI5_READ_QOS;
2205 __IO uint32_t AXI_INI5_WRITE_QOS;
2206 __IO uint32_t AXI_INI5_FN_MOD;
2207 uint32_t RESERVED24[1021];
2208 __IO uint32_t AXI_INI6_READ_QOS;
2209 __IO uint32_t AXI_INI6_WRITE_QOS;
2210 __IO uint32_t AXI_INI6_FN_MOD;
2211 uint32_t RESERVED25[1021];
2212 __IO uint32_t AXI_INI7_READ_QOS;
2213 __IO uint32_t AXI_INI7_WRITE_QOS;
2214 __IO uint32_t AXI_INI7_FN_MOD;
2216} GPV_TypeDef;
2217
2221#define D1_ITCMRAM_BASE (0x00000000UL)
2222#define D1_ITCMICP_BASE (0x00100000UL)
2223#define D1_DTCMRAM_BASE (0x20000000UL)
2224#define D1_AXIFLASH_BASE (0x08000000UL)
2225#define D1_AXIICP_BASE (0x1FF00000UL)
2226#define D1_AXISRAM_BASE (0x24000000UL)
2228#define D2_AXISRAM_BASE (0x10000000UL)
2229#define D2_AHBSRAM_BASE (0x30000000UL)
2231#define D3_BKPSRAM_BASE (0x38800000UL)
2232#define D3_SRAM_BASE (0x38000000UL)
2234#define PERIPH_BASE (0x40000000UL)
2235#define QSPI_BASE (0x90000000UL)
2237#define FLASH_BANK1_BASE (0x08000000UL)
2238#define FLASH_BANK2_BASE (0x08100000UL)
2239#define FLASH_END (0x081FFFFFUL)
2241/* Legacy define */
2242#define FLASH_BASE FLASH_BANK1_BASE
2243
2245#define UID_BASE (0x1FF1E800UL)
2246#define FLASHSIZE_BASE (0x1FF1E880UL)
2250#define D2_APB1PERIPH_BASE PERIPH_BASE
2251#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2252#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2253#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
2254
2255#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
2256#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
2257
2258#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
2259#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
2260
2262#define APB1PERIPH_BASE PERIPH_BASE
2263#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2264#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2265#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
2266
2267
2270#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
2271#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
2272#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL)
2273#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
2274#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
2275#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
2276#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
2277#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
2278#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
2279#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
2280
2283#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
2284#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
2285#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
2286#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
2287#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
2288#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
2289#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL)
2290#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
2291#define ETH_MAC_BASE (ETH_BASE)
2292
2294#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2295#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)
2296#define USB_OTG_GLOBAL_BASE (0x000UL)
2297#define USB_OTG_DEVICE_BASE (0x800UL)
2298#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2299#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2300#define USB_OTG_EP_REG_SIZE (0x20UL)
2301#define USB_OTG_HOST_BASE (0x400UL)
2302#define USB_OTG_HOST_PORT_BASE (0x440UL)
2303#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2304#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2305#define USB_OTG_PCGCCTL_BASE (0xE00UL)
2306#define USB_OTG_FIFO_BASE (0x1000UL)
2307#define USB_OTG_FIFO_SIZE (0x1000UL)
2308
2311#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
2312#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
2313#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
2314#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
2315#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
2316
2318#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
2319#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
2320#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
2321#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
2322#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
2323#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
2324#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
2325#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
2326#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)
2327#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
2328#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
2329#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
2330#define RCC_C1_BASE (RCC_BASE + 0x130UL)
2331#define RCC_C2_BASE (RCC_BASE + 0x190UL)
2332#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
2333#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
2334#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
2335#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
2336#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
2337#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
2338#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
2339#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
2340
2342#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
2343#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
2344#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
2345#define DSI_BASE (D1_APB1PERIPH_BASE)
2346#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
2347
2349#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
2350#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
2351#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
2352#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
2353#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
2354#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
2355#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
2356#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
2357#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
2358#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
2359
2360#define WWDG2_BASE (D2_APB1PERIPH_BASE + 0x2C00UL)
2361
2362#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
2363#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
2364#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
2365#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
2366#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
2367#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
2368#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
2369#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
2370#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
2371#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
2372#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
2373#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
2374#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
2375#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
2376#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
2377#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
2378#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2379#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2380#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
2381#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
2382#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
2383#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
2384#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
2385#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
2386
2389#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
2390#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
2391#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
2392#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
2393#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
2394#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
2395#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
2396#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
2397#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
2398#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
2399#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
2400#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2401#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2402#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)
2403#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2404#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2405#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)
2406#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)
2407#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)
2408#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)
2409#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2410#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2411#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2412#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2413#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2414#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2415#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2416#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2417#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2418#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2419#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2420#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2421#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)
2422#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)
2423#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)
2424#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)
2425#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)
2426#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)
2427#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)
2428
2429
2431#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
2432#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2433#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
2434#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
2435#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
2436#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
2437#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
2438#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
2439#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
2440#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
2441#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
2442#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
2443#define COMP1_BASE (COMP12_BASE + 0x0CUL)
2444#define COMP2_BASE (COMP12_BASE + 0x10UL)
2445#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
2446#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
2447#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
2448
2449#define IWDG2_BASE (D3_APB1PERIPH_BASE + 0x4C00UL)
2450
2451#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
2452#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
2453#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
2454
2455
2456
2457
2458#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
2459#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
2460#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
2461#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
2462#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
2463#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
2464#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
2465#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
2466
2467#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2468#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2469#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2470#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2471#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2472#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2473#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2474#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2475
2476#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2477#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2478#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2479#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2480#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2481#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2482#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2483#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2484
2485#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2486#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2487
2488#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2489#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2490#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2491#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2492#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2493#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2494#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2495#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2496
2497#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2498#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2499#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2500#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2501#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2502#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2503#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2504#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2505
2506#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2507#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2508#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2509#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2510#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2511#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2512#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2513#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2514#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2515#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2516#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2517#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2518#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2519#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2520#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2521#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2522
2523#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2524#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2525#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2526#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2527#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2528#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2529#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2530#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2531
2532#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2533#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2534
2536#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2537#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2538#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2539#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2540#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2541
2542/* Debug MCU registers base address */
2543#define DBGMCU_BASE (0x5C001000UL)
2544
2545#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2546#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2547#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2548#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2549#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2550#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2551#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2552#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2553#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2554#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2555#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2556#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2557#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2558#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2559#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2560#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2561
2562#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
2563#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
2564#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
2565#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
2566#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
2567
2568#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
2569#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
2570#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
2571#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
2572#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
2573
2574#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
2575#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
2576
2577
2578
2579#define GPV_BASE (PERIPH_BASE + 0x11000000UL)
2588#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2589#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2590#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2591#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2592#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2593#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2594#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2595#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2596#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2597#define RTC ((RTC_TypeDef *) RTC_BASE)
2598#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2599
2600#define WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)
2601#define IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)
2602
2603#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2604#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2605#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2606#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2607#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2608#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2609#define USART2 ((USART_TypeDef *) USART2_BASE)
2610#define USART3 ((USART_TypeDef *) USART3_BASE)
2611#define USART6 ((USART_TypeDef *) USART6_BASE)
2612#define UART7 ((USART_TypeDef *) UART7_BASE)
2613#define UART8 ((USART_TypeDef *) UART8_BASE)
2614#define CRS ((CRS_TypeDef *) CRS_BASE)
2615#define UART4 ((USART_TypeDef *) UART4_BASE)
2616#define UART5 ((USART_TypeDef *) UART5_BASE)
2617#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2618#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2619#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2620#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2621#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2622#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2623#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2624#define CEC ((CEC_TypeDef *) CEC_BASE)
2625#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2626#define PWR ((PWR_TypeDef *) PWR_BASE)
2627#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2628#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2629#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2630#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2631#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2632#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
2633#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
2634
2635#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2636#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2637#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2638#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2639#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2640#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2641#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2642#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2643
2644
2645#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2646#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2647#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
2648#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2649#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2650#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2651#define USART1 ((USART_TypeDef *) USART1_BASE)
2652#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2653#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2654#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2655#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2656#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
2657#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
2658#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
2659#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
2660#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
2661#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
2662#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
2663#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2664#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2665#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2666#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2667#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2668#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2669#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
2670#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
2671#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
2672#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
2673#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
2674#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
2675
2676#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2677#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2678#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2679#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2680#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2681#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2682#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2683#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2684#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2685#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2686#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2687#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2688#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2689#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2690#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2691#define RCC ((RCC_TypeDef *) RCC_BASE)
2692#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
2693#define RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)
2694
2695#define ART ((ART_TypeDef *) ART_BASE)
2696#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2697#define CRC ((CRC_TypeDef *) CRC_BASE)
2698
2699#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2700#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2701#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2702#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2703#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2704#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2705#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2706#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2707#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2708#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2709#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2710
2711#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2712#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2713#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
2714#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
2715#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2716
2717#define RNG ((RNG_TypeDef *) RNG_BASE)
2718#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2719#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2720
2721#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
2722#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
2723#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
2724#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
2725#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
2726#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
2727#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
2728#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
2729#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
2730
2731#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
2732#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
2733#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
2734#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
2735#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
2736#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
2737
2738#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
2739#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
2740#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
2741#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
2742#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
2743#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
2744
2745#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
2746#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
2747#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
2748
2749#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2750#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2751#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2752#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2753#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2754#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2755#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2756#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2757#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2758
2759
2760#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2761#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2762#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2763#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2764#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2765#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2766#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2767#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2768
2769#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2770#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2771
2772#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2773#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2774#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2775#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2776#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2777#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2778#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2779#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2780#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2781
2782#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2783#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2784#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2785#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2786#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2787#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2788#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2789#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2790#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2791
2792
2793#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2794#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2795#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2796#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2797#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2798#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2799#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2800#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2801#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2802#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2803#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2804#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2805#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2806#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2807#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2808#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2809#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2810
2811#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2812#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2813#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2814#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2815#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2816#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2817#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2818#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2819
2820#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2821#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2822
2823
2824#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2825#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2826#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2827#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2828#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2829
2830
2831#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
2832#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
2833#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2834#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2835
2836#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2837
2838#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
2839#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2840#if defined(CORE_CM4)
2841#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))
2842#else /* CORE_CM7 */
2843#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2844#endif /* CORE_CM4 */
2845
2846#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2847#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2848#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2849#define DSI ((DSI_TypeDef *)DSI_BASE)
2850
2851#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2852
2853#define ETH ((ETH_TypeDef *)ETH_BASE)
2854#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2855#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2856#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2857#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2858#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2859#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2860#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2861#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2862#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2863#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2864#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2865#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2866#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2867#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2868#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2869#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2870#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2871
2872
2873#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2874#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
2875
2876/* Legacy defines */
2877#define USB_OTG_HS USB1_OTG_HS
2878#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2879#define USB_OTG_FS USB2_OTG_FS
2880#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
2881
2882#define GPV ((GPV_TypeDef *) GPV_BASE)
2883
2895#define LSI_STARTUP_TIME 130U
2905/******************************************************************************/
2906/* Peripheral Registers_Bits_Definition */
2907/******************************************************************************/
2908
2909/******************************************************************************/
2910/* */
2911/* Analog to Digital Converter */
2912/* */
2913/******************************************************************************/
2914/******************************* ADC VERSION ********************************/
2915#define ADC_VER_V5_X
2916/******************** Bit definition for ADC_ISR register ********************/
2917#define ADC_ISR_ADRDY_Pos (0U)
2918#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
2919#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
2920#define ADC_ISR_EOSMP_Pos (1U)
2921#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
2922#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
2923#define ADC_ISR_EOC_Pos (2U)
2924#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
2925#define ADC_ISR_EOC ADC_ISR_EOC_Msk
2926#define ADC_ISR_EOS_Pos (3U)
2927#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
2928#define ADC_ISR_EOS ADC_ISR_EOS_Msk
2929#define ADC_ISR_OVR_Pos (4U)
2930#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
2931#define ADC_ISR_OVR ADC_ISR_OVR_Msk
2932#define ADC_ISR_JEOC_Pos (5U)
2933#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)
2934#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk
2935#define ADC_ISR_JEOS_Pos (6U)
2936#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)
2937#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk
2938#define ADC_ISR_AWD1_Pos (7U)
2939#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
2940#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
2941#define ADC_ISR_AWD2_Pos (8U)
2942#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)
2943#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk
2944#define ADC_ISR_AWD3_Pos (9U)
2945#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)
2946#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk
2947#define ADC_ISR_JQOVF_Pos (10U)
2948#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)
2949#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk
2950#define ADC_ISR_LDORDY_Pos (12U)
2951#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos)
2952#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk
2954/******************** Bit definition for ADC_IER register ********************/
2955#define ADC_IER_ADRDYIE_Pos (0U)
2956#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
2957#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
2958#define ADC_IER_EOSMPIE_Pos (1U)
2959#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
2960#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
2961#define ADC_IER_EOCIE_Pos (2U)
2962#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
2963#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
2964#define ADC_IER_EOSIE_Pos (3U)
2965#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
2966#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
2967#define ADC_IER_OVRIE_Pos (4U)
2968#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
2969#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
2970#define ADC_IER_JEOCIE_Pos (5U)
2971#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)
2972#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk
2973#define ADC_IER_JEOSIE_Pos (6U)
2974#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)
2975#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk
2976#define ADC_IER_AWD1IE_Pos (7U)
2977#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
2978#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
2979#define ADC_IER_AWD2IE_Pos (8U)
2980#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)
2981#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk
2982#define ADC_IER_AWD3IE_Pos (9U)
2983#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)
2984#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk
2985#define ADC_IER_JQOVFIE_Pos (10U)
2986#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)
2987#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk
2989/******************** Bit definition for ADC_CR register ********************/
2990#define ADC_CR_ADEN_Pos (0U)
2991#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
2992#define ADC_CR_ADEN ADC_CR_ADEN_Msk
2993#define ADC_CR_ADDIS_Pos (1U)
2994#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
2995#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
2996#define ADC_CR_ADSTART_Pos (2U)
2997#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
2998#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
2999#define ADC_CR_JADSTART_Pos (3U)
3000#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)
3001#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk
3002#define ADC_CR_ADSTP_Pos (4U)
3003#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
3004#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
3005#define ADC_CR_JADSTP_Pos (5U)
3006#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)
3007#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk
3008#define ADC_CR_BOOST_Pos (8U)
3009#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos)
3010#define ADC_CR_BOOST ADC_CR_BOOST_Msk
3011#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos)
3012#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos)
3013#define ADC_CR_ADCALLIN_Pos (16U)
3014#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos)
3015#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk
3016#define ADC_CR_LINCALRDYW1_Pos (22U)
3017#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos)
3018#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk
3019#define ADC_CR_LINCALRDYW2_Pos (23U)
3020#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos)
3021#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk
3022#define ADC_CR_LINCALRDYW3_Pos (24U)
3023#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos)
3024#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk
3025#define ADC_CR_LINCALRDYW4_Pos (25U)
3026#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos)
3027#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk
3028#define ADC_CR_LINCALRDYW5_Pos (26U)
3029#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos)
3030#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk
3031#define ADC_CR_LINCALRDYW6_Pos (27U)
3032#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos)
3033#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk
3034#define ADC_CR_ADVREGEN_Pos (28U)
3035#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)
3036#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
3037#define ADC_CR_DEEPPWD_Pos (29U)
3038#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)
3039#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk
3040#define ADC_CR_ADCALDIF_Pos (30U)
3041#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)
3042#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk
3043#define ADC_CR_ADCAL_Pos (31U)
3044#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
3045#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
3047/******************** Bit definition for ADC_CFGR register ********************/
3048#define ADC_CFGR_DMNGT_Pos (0U)
3049#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos)
3050#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk
3051#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos)
3052#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos)
3054#define ADC_CFGR_RES_Pos (2U)
3055#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos)
3056#define ADC_CFGR_RES ADC_CFGR_RES_Msk
3057#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)
3058#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)
3059#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos)
3061#define ADC_CFGR_EXTSEL_Pos (5U)
3062#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos)
3063#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk
3064#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos)
3065#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos)
3066#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos)
3067#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos)
3068#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos)
3070#define ADC_CFGR_EXTEN_Pos (10U)
3071#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)
3072#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk
3073#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)
3074#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)
3076#define ADC_CFGR_OVRMOD_Pos (12U)
3077#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)
3078#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk
3079#define ADC_CFGR_CONT_Pos (13U)
3080#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)
3081#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk
3082#define ADC_CFGR_AUTDLY_Pos (14U)
3083#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)
3084#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk
3086#define ADC_CFGR_DISCEN_Pos (16U)
3087#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)
3088#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk
3090#define ADC_CFGR_DISCNUM_Pos (17U)
3091#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)
3092#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk
3093#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)
3094#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)
3095#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)
3097#define ADC_CFGR_JDISCEN_Pos (20U)
3098#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)
3099#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk
3100#define ADC_CFGR_JQM_Pos (21U)
3101#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)
3102#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk
3103#define ADC_CFGR_AWD1SGL_Pos (22U)
3104#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)
3105#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk
3106#define ADC_CFGR_AWD1EN_Pos (23U)
3107#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)
3108#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk
3109#define ADC_CFGR_JAWD1EN_Pos (24U)
3110#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)
3111#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk
3112#define ADC_CFGR_JAUTO_Pos (25U)
3113#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)
3114#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk
3116#define ADC_CFGR_AWD1CH_Pos (26U)
3117#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)
3118#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk
3119#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)
3120#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)
3121#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)
3122#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)
3123#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)
3125#define ADC_CFGR_JQDIS_Pos (31U)
3126#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)
3127#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk
3129/******************** Bit definition for ADC_CFGR2 register ********************/
3130#define ADC_CFGR2_ROVSE_Pos (0U)
3131#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)
3132#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk
3133#define ADC_CFGR2_JOVSE_Pos (1U)
3134#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)
3135#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk
3137#define ADC_CFGR2_OVSS_Pos (5U)
3138#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)
3139#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk
3140#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)
3141#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)
3142#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)
3143#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)
3145#define ADC_CFGR2_TROVS_Pos (9U)
3146#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)
3147#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk
3148#define ADC_CFGR2_ROVSM_Pos (10U)
3149#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)
3150#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk
3152#define ADC_CFGR2_RSHIFT1_Pos (11U)
3153#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos)
3154#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk
3155#define ADC_CFGR2_RSHIFT2_Pos (12U)
3156#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos)
3157#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk
3158#define ADC_CFGR2_RSHIFT3_Pos (13U)
3159#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos)
3160#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk
3161#define ADC_CFGR2_RSHIFT4_Pos (14U)
3162#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos)
3163#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk
3165#define ADC_CFGR2_OVSR_Pos (16U)
3166#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos)
3167#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk
3168#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos)
3169#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos)
3170#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos)
3171#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos)
3172#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos)
3173#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos)
3174#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos)
3175#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos)
3176#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos)
3177#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos)
3179#define ADC_CFGR2_LSHIFT_Pos (28U)
3180#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos)
3181#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk
3182#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos)
3183#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos)
3184#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos)
3185#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos)
3187/******************** Bit definition for ADC_SMPR1 register ********************/
3188#define ADC_SMPR1_SMP0_Pos (0U)
3189#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)
3190#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk
3191#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)
3192#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)
3193#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)
3195#define ADC_SMPR1_SMP1_Pos (3U)
3196#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)
3197#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk
3198#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)
3199#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)
3200#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)
3202#define ADC_SMPR1_SMP2_Pos (6U)
3203#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)
3204#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk
3205#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)
3206#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)
3207#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)
3209#define ADC_SMPR1_SMP3_Pos (9U)
3210#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)
3211#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk
3212#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)
3213#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)
3214#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)
3216#define ADC_SMPR1_SMP4_Pos (12U)
3217#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)
3218#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk
3219#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)
3220#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)
3221#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)
3223#define ADC_SMPR1_SMP5_Pos (15U)
3224#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)
3225#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk
3226#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)
3227#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)
3228#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)
3230#define ADC_SMPR1_SMP6_Pos (18U)
3231#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)
3232#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk
3233#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)
3234#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)
3235#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)
3237#define ADC_SMPR1_SMP7_Pos (21U)
3238#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)
3239#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk
3240#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)
3241#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)
3242#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)
3244#define ADC_SMPR1_SMP8_Pos (24U)
3245#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)
3246#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk
3247#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)
3248#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)
3249#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)
3251#define ADC_SMPR1_SMP9_Pos (27U)
3252#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)
3253#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk
3254#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
3255#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)
3256#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)
3258/******************** Bit definition for ADC_SMPR2 register ********************/
3259#define ADC_SMPR2_SMP10_Pos (0U)
3260#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)
3261#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk
3262#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)
3263#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)
3264#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
3266#define ADC_SMPR2_SMP11_Pos (3U)
3267#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)
3268#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk
3269#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)
3270#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)
3271#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
3273#define ADC_SMPR2_SMP12_Pos (6U)
3274#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)
3275#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk
3276#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)
3277#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)
3278#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
3280#define ADC_SMPR2_SMP13_Pos (9U)
3281#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)
3282#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk
3283#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)
3284#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)
3285#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
3287#define ADC_SMPR2_SMP14_Pos (12U)
3288#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)
3289#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk
3290#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)
3291#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)
3292#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
3294#define ADC_SMPR2_SMP15_Pos (15U)
3295#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)
3296#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk
3297#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)
3298#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)
3299#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)
3301#define ADC_SMPR2_SMP16_Pos (18U)
3302#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)
3303#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk
3304#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)
3305#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)
3306#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
3308#define ADC_SMPR2_SMP17_Pos (21U)
3309#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)
3310#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk
3311#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)
3312#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)
3313#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
3315#define ADC_SMPR2_SMP18_Pos (24U)
3316#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)
3317#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk
3318#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)
3319#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)
3320#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
3322#define ADC_SMPR2_SMP19_Pos (27U)
3323#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos)
3324#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk
3325#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos)
3326#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos)
3327#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos)
3329/******************** Bit definition for ADC_PCSEL register ********************/
3330#define ADC_PCSEL_PCSEL_Pos (0U)
3331#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)
3332#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk
3333#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos)
3334#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos)
3335#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos)
3336#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos)
3337#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos)
3338#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos)
3339#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos)
3340#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos)
3341#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos)
3342#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos)
3343#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos)
3344#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos)
3345#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos)
3346#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos)
3347#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos)
3348#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos)
3349#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos)
3350#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos)
3351#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos)
3352#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos)
3354/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3355#define ADC_LTR_LT_Pos (0U)
3356#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos)
3357#define ADC_LTR_LT ADC_LTR_LT_Msk
3359/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3360#define ADC_HTR_HT_Pos (0U)
3361#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos)
3362#define ADC_HTR_HT ADC_HTR_HT_Msk
3365/******************** Bit definition for ADC_SQR1 register ********************/
3366#define ADC_SQR1_L_Pos (0U)
3367#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
3368#define ADC_SQR1_L ADC_SQR1_L_Msk
3369#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
3370#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
3371#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
3372#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
3374#define ADC_SQR1_SQ1_Pos (6U)
3375#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)
3376#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk
3377#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)
3378#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)
3379#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)
3380#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)
3381#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
3383#define ADC_SQR1_SQ2_Pos (12U)
3384#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)
3385#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk
3386#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)
3387#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)
3388#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)
3389#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)
3390#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)
3392#define ADC_SQR1_SQ3_Pos (18U)
3393#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)
3394#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk
3395#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)
3396#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)
3397#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)
3398#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)
3399#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)
3401#define ADC_SQR1_SQ4_Pos (24U)
3402#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)
3403#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk
3404#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)
3405#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)
3406#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)
3407#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)
3408#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)
3410/******************** Bit definition for ADC_SQR2 register ********************/
3411#define ADC_SQR2_SQ5_Pos (0U)
3412#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)
3413#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk
3414#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)
3415#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)
3416#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)
3417#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)
3418#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)
3420#define ADC_SQR2_SQ6_Pos (6U)
3421#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)
3422#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk
3423#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)
3424#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)
3425#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)
3426#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)
3427#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)
3429#define ADC_SQR2_SQ7_Pos (12U)
3430#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
3431#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
3432#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
3433#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
3434#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
3435#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
3436#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
3438#define ADC_SQR2_SQ8_Pos (18U)
3439#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
3440#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
3441#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
3442#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
3443#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
3444#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
3445#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
3447#define ADC_SQR2_SQ9_Pos (24U)
3448#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
3449#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
3450#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
3451#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
3452#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
3453#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
3454#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
3456/******************** Bit definition for ADC_SQR3 register ********************/
3457#define ADC_SQR3_SQ10_Pos (0U)
3458#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)
3459#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk
3460#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)
3461#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)
3462#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)
3463#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)
3464#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)
3466#define ADC_SQR3_SQ11_Pos (6U)
3467#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)
3468#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk
3469#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)
3470#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)
3471#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)
3472#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)
3473#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)
3475#define ADC_SQR3_SQ12_Pos (12U)
3476#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)
3477#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk
3478#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)
3479#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)
3480#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)
3481#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)
3482#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)
3484#define ADC_SQR3_SQ13_Pos (18U)
3485#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)
3486#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk
3487#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)
3488#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)
3489#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)
3490#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)
3491#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)
3493#define ADC_SQR3_SQ14_Pos (24U)
3494#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)
3495#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk
3496#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)
3497#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)
3498#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)
3499#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)
3500#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)
3502/******************** Bit definition for ADC_SQR4 register ********************/
3503#define ADC_SQR4_SQ15_Pos (0U)
3504#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)
3505#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk
3506#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)
3507#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)
3508#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)
3509#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)
3510#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)
3512#define ADC_SQR4_SQ16_Pos (6U)
3513#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)
3514#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk
3515#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)
3516#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)
3517#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)
3518#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)
3519#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)
3520/******************** Bit definition for ADC_DR register ********************/
3521#define ADC_DR_RDATA_Pos (0U)
3522#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)
3523#define ADC_DR_RDATA ADC_DR_RDATA_Msk
3525/******************** Bit definition for ADC_JSQR register ********************/
3526#define ADC_JSQR_JL_Pos (0U)
3527#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
3528#define ADC_JSQR_JL ADC_JSQR_JL_Msk
3529#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
3530#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
3532#define ADC_JSQR_JEXTSEL_Pos (2U)
3533#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos)
3534#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk
3535#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos)
3536#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos)
3537#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos)
3538#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos)
3539#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos)
3541#define ADC_JSQR_JEXTEN_Pos (7U)
3542#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)
3543#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk
3544#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)
3545#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)
3547#define ADC_JSQR_JSQ1_Pos (9U)
3548#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
3549#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
3550#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
3551#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
3552#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
3553#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
3554#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
3556#define ADC_JSQR_JSQ2_Pos (15U)
3557#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
3558#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
3559#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
3560#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
3561#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
3562#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
3563#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
3565#define ADC_JSQR_JSQ3_Pos (21U)
3566#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
3567#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
3568#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
3569#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
3570#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
3571#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
3572#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
3574#define ADC_JSQR_JSQ4_Pos (27U)
3575#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
3576#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
3577#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
3578#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
3579#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
3580#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
3581#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
3583/******************** Bit definition for ADC_OFR1 register ********************/
3584#define ADC_OFR1_OFFSET1_Pos (0U)
3585#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos)
3586#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk
3587#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos)
3588#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos)
3589#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos)
3590#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos)
3591#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos)
3592#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos)
3593#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos)
3594#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos)
3595#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos)
3596#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos)
3597#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos)
3598#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos)
3599#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos)
3600#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos)
3601#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos)
3602#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos)
3603#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos)
3604#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos)
3605#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos)
3606#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos)
3607#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos)
3608#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos)
3609#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos)
3610#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos)
3611#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos)
3612#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos)
3614#define ADC_OFR1_OFFSET1_CH_Pos (26U)
3615#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
3616#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk
3617#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
3618#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
3619#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
3620#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
3621#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
3623#define ADC_OFR1_SSATE_Pos (31U)
3624#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos)
3625#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk
3628/******************** Bit definition for ADC_OFR2 register ********************/
3629#define ADC_OFR2_OFFSET2_Pos (0U)
3630#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos)
3631#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk
3632#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos)
3633#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos)
3634#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos)
3635#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos)
3636#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos)
3637#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos)
3638#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos)
3639#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos)
3640#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos)
3641#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos)
3642#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos)
3643#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos)
3644#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos)
3645#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos)
3646#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos)
3647#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos)
3648#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos)
3649#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos)
3650#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos)
3651#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos)
3652#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos)
3653#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos)
3654#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos)
3655#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos)
3656#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos)
3657#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos)
3659#define ADC_OFR2_OFFSET2_CH_Pos (26U)
3660#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
3661#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk
3662#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
3663#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
3664#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
3665#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
3666#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
3668#define ADC_OFR2_SSATE_Pos (31U)
3669#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos)
3670#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk
3673/******************** Bit definition for ADC_OFR3 register ********************/
3674#define ADC_OFR3_OFFSET3_Pos (0U)
3675#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos)
3676#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk
3677#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos)
3678#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos)
3679#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos)
3680#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos)
3681#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos)
3682#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos)
3683#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos)
3684#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos)
3685#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos)
3686#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos)
3687#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos)
3688#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos)
3689#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos)
3690#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos)
3691#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos)
3692#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos)
3693#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos)
3694#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos)
3695#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos)
3696#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos)
3697#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos)
3698#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos)
3699#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos)
3700#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos)
3701#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos)
3702#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos)
3704#define ADC_OFR3_OFFSET3_CH_Pos (26U)
3705#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
3706#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk
3707#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
3708#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
3709#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
3710#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
3711#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
3713#define ADC_OFR3_SSATE_Pos (31U)
3714#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos)
3715#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk
3718/******************** Bit definition for ADC_OFR4 register ********************/
3719#define ADC_OFR4_OFFSET4_Pos (0U)
3720#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos)
3721#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk
3722#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos)
3723#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos)
3724#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos)
3725#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos)
3726#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos)
3727#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos)
3728#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos)
3729#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos)
3730#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos)
3731#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos)
3732#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos)
3733#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos)
3734#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos)
3735#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos)
3736#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos)
3737#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos)
3738#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos)
3739#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos)
3740#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos)
3741#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos)
3742#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos)
3743#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos)
3744#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos)
3745#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos)
3746#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos)
3747#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos)
3749#define ADC_OFR4_OFFSET4_CH_Pos (26U)
3750#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
3751#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk
3752#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
3753#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
3754#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
3755#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
3756#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
3758#define ADC_OFR4_SSATE_Pos (31U)
3759#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos)
3760#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk
3763/******************** Bit definition for ADC_JDR1 register ********************/
3764#define ADC_JDR1_JDATA_Pos (0U)
3765#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)
3766#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
3767#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos)
3768#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos)
3769#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos)
3770#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos)
3771#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos)
3772#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos)
3773#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos)
3774#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos)
3775#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos)
3776#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos)
3777#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos)
3778#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos)
3779#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos)
3780#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos)
3781#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos)
3782#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos)
3783#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos)
3784#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos)
3785#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos)
3786#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos)
3787#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos)
3788#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos)
3789#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos)
3790#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos)
3791#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos)
3792#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos)
3793#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos)
3794#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos)
3795#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos)
3796#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos)
3797#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos)
3798#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos)
3800/******************** Bit definition for ADC_JDR2 register ********************/
3801#define ADC_JDR2_JDATA_Pos (0U)
3802#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)
3803#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
3804#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos)
3805#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos)
3806#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos)
3807#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos)
3808#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos)
3809#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos)
3810#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos)
3811#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos)
3812#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos)
3813#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos)
3814#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos)
3815#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos)
3816#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos)
3817#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos)
3818#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos)
3819#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos)
3820#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos)
3821#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos)
3822#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos)
3823#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos)
3824#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos)
3825#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos)
3826#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos)
3827#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos)
3828#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos)
3829#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos)
3830#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos)
3831#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos)
3832#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos)
3833#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos)
3834#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos)
3835#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos)
3837/******************** Bit definition for ADC_JDR3 register ********************/
3838#define ADC_JDR3_JDATA_Pos (0U)
3839#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)
3840#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
3841#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos)
3842#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos)
3843#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos)
3844#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos)
3845#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos)
3846#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos)
3847#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos)
3848#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos)
3849#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos)
3850#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos)
3851#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos)
3852#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos)
3853#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos)
3854#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos)
3855#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos)
3856#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos)
3857#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos)
3858#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos)
3859#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos)
3860#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos)
3861#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos)
3862#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos)
3863#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos)
3864#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos)
3865#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos)
3866#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos)
3867#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos)
3868#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos)
3869#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos)
3870#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos)
3871#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos)
3872#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos)
3874/******************** Bit definition for ADC_JDR4 register ********************/
3875#define ADC_JDR4_JDATA_Pos (0U)
3876#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)
3877#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
3878#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos)
3879#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos)
3880#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos)
3881#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos)
3882#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos)
3883#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos)
3884#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos)
3885#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos)
3886#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos)
3887#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos)
3888#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos)
3889#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos)
3890#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos)
3891#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos)
3892#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos)
3893#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos)
3894#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos)
3895#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos)
3896#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos)
3897#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos)
3898#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos)
3899#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos)
3900#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos)
3901#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos)
3902#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos)
3903#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos)
3904#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos)
3905#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos)
3906#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos)
3907#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos)
3908#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos)
3909#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos)
3911/******************** Bit definition for ADC_AWD2CR register ********************/
3912#define ADC_AWD2CR_AWD2CH_Pos (0U)
3913#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)
3914#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk
3915#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
3916#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
3917#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
3918#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
3919#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
3920#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
3921#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
3922#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
3923#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
3924#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
3925#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
3926#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
3927#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
3928#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
3929#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
3930#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
3931#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
3932#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
3933#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)
3934#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)
3936/******************** Bit definition for ADC_AWD3CR register ********************/
3937#define ADC_AWD3CR_AWD3CH_Pos (0U)
3938#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)
3939#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk
3940#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
3941#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
3942#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
3943#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
3944#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
3945#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
3946#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
3947#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
3948#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
3949#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
3950#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
3951#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
3952#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
3953#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
3954#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
3955#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
3956#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
3957#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
3958#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)
3959#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)
3961/******************** Bit definition for ADC_DIFSEL register ********************/
3962#define ADC_DIFSEL_DIFSEL_Pos (0U)
3963#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)
3964#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk
3965#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
3966#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
3967#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
3968#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
3969#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
3970#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
3971#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
3972#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
3973#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
3974#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
3975#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
3976#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
3977#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
3978#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
3979#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
3980#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
3981#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
3982#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
3983#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)
3984#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)
3986/******************** Bit definition for ADC_CALFACT register ********************/
3987#define ADC_CALFACT_CALFACT_S_Pos (0U)
3988#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos)
3989#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk
3990#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos)
3991#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos)
3992#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos)
3993#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos)
3994#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos)
3995#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos)
3996#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos)
3997#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos)
3998#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos)
3999#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos)
4000#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos)
4001#define ADC_CALFACT_CALFACT_D_Pos (16U)
4002#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos)
4003#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk
4004#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos)
4005#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos)
4006#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos)
4007#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos)
4008#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos)
4009#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos)
4010#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos)
4011#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos)
4012#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos)
4013#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos)
4014#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos)
4016/******************** Bit definition for ADC_CALFACT2 register ********************/
4017#define ADC_CALFACT2_LINCALFACT_Pos (0U)
4018#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos)
4019#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk
4020#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos)
4021#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos)
4022#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos)
4023#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos)
4024#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos)
4025#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos)
4026#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos)
4027#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos)
4028#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos)
4029#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos)
4030#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos)
4031#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos)
4032#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos)
4033#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos)
4034#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos)
4035#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos)
4036#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos)
4037#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos)
4038#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos)
4039#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos)
4040#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos)
4041#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos)
4042#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos)
4043#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos)
4044#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4045#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4046#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4047#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4048#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4049#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4051/************************* ADC Common registers *****************************/
4052/******************** Bit definition for ADC_CSR register ********************/
4053#define ADC_CSR_ADRDY_MST_Pos (0U)
4054#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)
4055#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk
4056#define ADC_CSR_EOSMP_MST_Pos (1U)
4057#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)
4058#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk
4059#define ADC_CSR_EOC_MST_Pos (2U)
4060#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)
4061#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk
4062#define ADC_CSR_EOS_MST_Pos (3U)
4063#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)
4064#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk
4065#define ADC_CSR_OVR_MST_Pos (4U)
4066#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)
4067#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk
4068#define ADC_CSR_JEOC_MST_Pos (5U)
4069#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)
4070#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk
4071#define ADC_CSR_JEOS_MST_Pos (6U)
4072#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)
4073#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk
4074#define ADC_CSR_AWD1_MST_Pos (7U)
4075#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)
4076#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk
4077#define ADC_CSR_AWD2_MST_Pos (8U)
4078#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)
4079#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk
4080#define ADC_CSR_AWD3_MST_Pos (9U)
4081#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)
4082#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk
4083#define ADC_CSR_JQOVF_MST_Pos (10U)
4084#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)
4085#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk
4086#define ADC_CSR_ADRDY_SLV_Pos (16U)
4087#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)
4088#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk
4089#define ADC_CSR_EOSMP_SLV_Pos (17U)
4090#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)
4091#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk
4092#define ADC_CSR_EOC_SLV_Pos (18U)
4093#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)
4094#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk
4095#define ADC_CSR_EOS_SLV_Pos (19U)
4096#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)
4097#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk
4098#define ADC_CSR_OVR_SLV_Pos (20U)
4099#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)
4100#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk
4101#define ADC_CSR_JEOC_SLV_Pos (21U)
4102#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)
4103#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk
4104#define ADC_CSR_JEOS_SLV_Pos (22U)
4105#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)
4106#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk
4107#define ADC_CSR_AWD1_SLV_Pos (23U)
4108#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)
4109#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk
4110#define ADC_CSR_AWD2_SLV_Pos (24U)
4111#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)
4112#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk
4113#define ADC_CSR_AWD3_SLV_Pos (25U)
4114#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)
4115#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk
4116#define ADC_CSR_JQOVF_SLV_Pos (26U)
4117#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)
4118#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk
4120/******************** Bit definition for ADC_CCR register ********************/
4121#define ADC_CCR_DUAL_Pos (0U)
4122#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)
4123#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk
4124#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)
4125#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)
4126#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)
4127#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)
4128#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)
4130#define ADC_CCR_DELAY_Pos (8U)
4131#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
4132#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
4133#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
4134#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
4135#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
4136#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
4139#define ADC_CCR_DAMDF_Pos (14U)
4140#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos)
4141#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk
4142#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos)
4143#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos)
4145#define ADC_CCR_CKMODE_Pos (16U)
4146#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)
4147#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk
4148#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)
4149#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
4151#define ADC_CCR_PRESC_Pos (18U)
4152#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)
4153#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk
4154#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)
4155#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)
4156#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)
4157#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)
4159#define ADC_CCR_VREFEN_Pos (22U)
4160#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
4161#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
4162#define ADC_CCR_TSEN_Pos (23U)
4163#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
4164#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk
4165#define ADC_CCR_VBATEN_Pos (24U)
4166#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)
4167#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk
4169/******************** Bit definition for ADC_CDR register *******************/
4170#define ADC_CDR_RDATA_MST_Pos (0U)
4171#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)
4172#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk
4174#define ADC_CDR_RDATA_SLV_Pos (16U)
4175#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)
4176#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk
4178/******************** Bit definition for ADC_CDR2 register ******************/
4179#define ADC_CDR2_RDATA_ALT_Pos (0U)
4180#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos)
4181#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk
4183/******************************************************************************/
4184/* */
4185/* ART accelerator */
4186/* */
4187/******************************************************************************/
4188/******************* Bit definition for ART_CTR register ********************/
4189#define ART_CTR_EN_Pos (0U)
4190#define ART_CTR_EN_Msk (0x1UL << ART_CTR_EN_Pos)
4191#define ART_CTR_EN ART_CTR_EN_Msk
4193#define ART_CTR_PCACHEADDR_Pos (8U)
4194#define ART_CTR_PCACHEADDR_Msk (0xFFFUL << ART_CTR_PCACHEADDR_Pos)
4195#define ART_CTR_PCACHEADDR ART_CTR_PCACHEADDR_Msk
4197/******************************************************************************/
4198/* */
4199/* VREFBUF */
4200/* */
4201/******************************************************************************/
4202/******************* Bit definition for VREFBUF_CSR register ****************/
4203#define VREFBUF_CSR_ENVR_Pos (0U)
4204#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)
4205#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk
4206#define VREFBUF_CSR_HIZ_Pos (1U)
4207#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)
4208#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk
4209#define VREFBUF_CSR_VRR_Pos (3U)
4210#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)
4211#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk
4212#define VREFBUF_CSR_VRS_Pos (4U)
4213#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos)
4214#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk
4216#define VREFBUF_CSR_VRS_OUT1 (0U)
4217#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
4218#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)
4219#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk
4220#define VREFBUF_CSR_VRS_OUT3_Pos (5U)
4221#define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)
4222#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk
4223#define VREFBUF_CSR_VRS_OUT4_Pos (4U)
4224#define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)
4225#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk
4227/******************* Bit definition for VREFBUF_CCR register ****************/
4228#define VREFBUF_CCR_TRIM_Pos (0U)
4229#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)
4230#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk
4232/******************************************************************************/
4233/* */
4234/* Flexible Datarate Controller Area Network */
4235/* */
4236/******************************************************************************/
4238/***************** Bit definition for FDCAN_CREL register *******************/
4239#define FDCAN_CREL_DAY_Pos (0U)
4240#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos)
4241#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk
4242#define FDCAN_CREL_MON_Pos (8U)
4243#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos)
4244#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk
4245#define FDCAN_CREL_YEAR_Pos (16U)
4246#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos)
4247#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk
4248#define FDCAN_CREL_SUBSTEP_Pos (20U)
4249#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos)
4250#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk
4251#define FDCAN_CREL_STEP_Pos (24U)
4252#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos)
4253#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk
4254#define FDCAN_CREL_REL_Pos (28U)
4255#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos)
4256#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk
4258/***************** Bit definition for FDCAN_ENDN register *******************/
4259#define FDCAN_ENDN_ETV_Pos (0U)
4260#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)
4261#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk
4263/***************** Bit definition for FDCAN_DBTP register *******************/
4264#define FDCAN_DBTP_DSJW_Pos (0U)
4265#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos)
4266#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk
4267#define FDCAN_DBTP_DTSEG2_Pos (4U)
4268#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos)
4269#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk
4270#define FDCAN_DBTP_DTSEG1_Pos (8U)
4271#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)
4272#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk
4273#define FDCAN_DBTP_DBRP_Pos (16U)
4274#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos)
4275#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk
4276#define FDCAN_DBTP_TDC_Pos (23U)
4277#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos)
4278#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk
4280/***************** Bit definition for FDCAN_TEST register *******************/
4281#define FDCAN_TEST_LBCK_Pos (4U)
4282#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos)
4283#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk
4284#define FDCAN_TEST_TX_Pos (5U)
4285#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos)
4286#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk
4287#define FDCAN_TEST_RX_Pos (7U)
4288#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos)
4289#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk
4291/***************** Bit definition for FDCAN_RWD register ********************/
4292#define FDCAN_RWD_WDC_Pos (0U)
4293#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos)
4294#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk
4295#define FDCAN_RWD_WDV_Pos (8U)
4296#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos)
4297#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk
4299/***************** Bit definition for FDCAN_CCCR register ********************/
4300#define FDCAN_CCCR_INIT_Pos (0U)
4301#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos)
4302#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk
4303#define FDCAN_CCCR_CCE_Pos (1U)
4304#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos)
4305#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk
4306#define FDCAN_CCCR_ASM_Pos (2U)
4307#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos)
4308#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk
4309#define FDCAN_CCCR_CSA_Pos (3U)
4310#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos)
4311#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk
4312#define FDCAN_CCCR_CSR_Pos (4U)
4313#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos)
4314#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk
4315#define FDCAN_CCCR_MON_Pos (5U)
4316#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos)
4317#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk
4318#define FDCAN_CCCR_DAR_Pos (6U)
4319#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos)
4320#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk
4321#define FDCAN_CCCR_TEST_Pos (7U)
4322#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos)
4323#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk
4324#define FDCAN_CCCR_FDOE_Pos (8U)
4325#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos)
4326#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk
4327#define FDCAN_CCCR_BRSE_Pos (9U)
4328#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos)
4329#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk
4330#define FDCAN_CCCR_PXHD_Pos (12U)
4331#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos)
4332#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk
4333#define FDCAN_CCCR_EFBI_Pos (13U)
4334#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos)
4335#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk
4336#define FDCAN_CCCR_TXP_Pos (14U)
4337#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos)
4338#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk
4339#define FDCAN_CCCR_NISO_Pos (15U)
4340#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos)
4341#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk
4343/***************** Bit definition for FDCAN_NBTP register ********************/
4344#define FDCAN_NBTP_NTSEG2_Pos (0U)
4345#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)
4346#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk
4347#define FDCAN_NBTP_NTSEG1_Pos (8U)
4348#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)
4349#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk
4350#define FDCAN_NBTP_NBRP_Pos (16U)
4351#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos)
4352#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk
4353#define FDCAN_NBTP_NSJW_Pos (25U)
4354#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos)
4355#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk
4357/***************** Bit definition for FDCAN_TSCC register ********************/
4358#define FDCAN_TSCC_TSS_Pos (0U)
4359#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos)
4360#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk
4361#define FDCAN_TSCC_TCP_Pos (16U)
4362#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos)
4363#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk
4365/***************** Bit definition for FDCAN_TSCV register ********************/
4366#define FDCAN_TSCV_TSC_Pos (0U)
4367#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos)
4368#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk
4370/***************** Bit definition for FDCAN_TOCC register ********************/
4371#define FDCAN_TOCC_ETOC_Pos (0U)
4372#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos)
4373#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk
4374#define FDCAN_TOCC_TOS_Pos (1U)
4375#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos)
4376#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk
4377#define FDCAN_TOCC_TOP_Pos (16U)
4378#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos)
4379#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk
4381/***************** Bit definition for FDCAN_TOCV register ********************/
4382#define FDCAN_TOCV_TOC_Pos (0U)
4383#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos)
4384#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk
4386/***************** Bit definition for FDCAN_ECR register *********************/
4387#define FDCAN_ECR_TEC_Pos (0U)
4388#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos)
4389#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk
4390#define FDCAN_ECR_REC_Pos (8U)
4391#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos)
4392#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk
4393#define FDCAN_ECR_RP_Pos (15U)
4394#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos)
4395#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk
4396#define FDCAN_ECR_CEL_Pos (16U)
4397#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos)
4398#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk
4400/***************** Bit definition for FDCAN_PSR register *********************/
4401#define FDCAN_PSR_LEC_Pos (0U)
4402#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos)
4403#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk
4404#define FDCAN_PSR_ACT_Pos (3U)
4405#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos)
4406#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk
4407#define FDCAN_PSR_EP_Pos (5U)
4408#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos)
4409#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk
4410#define FDCAN_PSR_EW_Pos (6U)
4411#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos)
4412#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk
4413#define FDCAN_PSR_BO_Pos (7U)
4414#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos)
4415#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk
4416#define FDCAN_PSR_DLEC_Pos (8U)
4417#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos)
4418#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk
4419#define FDCAN_PSR_RESI_Pos (11U)
4420#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos)
4421#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk
4422#define FDCAN_PSR_RBRS_Pos (12U)
4423#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos)
4424#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk
4425#define FDCAN_PSR_REDL_Pos (13U)
4426#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos)
4427#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk
4428#define FDCAN_PSR_PXE_Pos (14U)
4429#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos)
4430#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk
4431#define FDCAN_PSR_TDCV_Pos (16U)
4432#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos)
4433#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk
4435/***************** Bit definition for FDCAN_TDCR register ********************/
4436#define FDCAN_TDCR_TDCF_Pos (0U)
4437#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos)
4438#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk
4439#define FDCAN_TDCR_TDCO_Pos (8U)
4440#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos)
4441#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk
4443/***************** Bit definition for FDCAN_IR register **********************/
4444#define FDCAN_IR_RF0N_Pos (0U)
4445#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos)
4446#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk
4447#define FDCAN_IR_RF0W_Pos (1U)
4448#define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos)
4449#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk
4450#define FDCAN_IR_RF0F_Pos (2U)
4451#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos)
4452#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk
4453#define FDCAN_IR_RF0L_Pos (3U)
4454#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos)
4455#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk
4456#define FDCAN_IR_RF1N_Pos (4U)
4457#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos)
4458#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk
4459#define FDCAN_IR_RF1W_Pos (5U)
4460#define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos)
4461#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk
4462#define FDCAN_IR_RF1F_Pos (6U)
4463#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos)
4464#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk
4465#define FDCAN_IR_RF1L_Pos (7U)
4466#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos)
4467#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk
4468#define FDCAN_IR_HPM_Pos (8U)
4469#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos)
4470#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk
4471#define FDCAN_IR_TC_Pos (9U)
4472#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos)
4473#define FDCAN_IR_TC FDCAN_IR_TC_Msk
4474#define FDCAN_IR_TCF_Pos (10U)
4475#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos)
4476#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk
4477#define FDCAN_IR_TFE_Pos (11U)
4478#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos)
4479#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk
4480#define FDCAN_IR_TEFN_Pos (12U)
4481#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos)
4482#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk
4483#define FDCAN_IR_TEFW_Pos (13U)
4484#define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos)
4485#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk
4486#define FDCAN_IR_TEFF_Pos (14U)
4487#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos)
4488#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk
4489#define FDCAN_IR_TEFL_Pos (15U)
4490#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos)
4491#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk
4492#define FDCAN_IR_TSW_Pos (16U)
4493#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos)
4494#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk
4495#define FDCAN_IR_MRAF_Pos (17U)
4496#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos)
4497#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk
4498#define FDCAN_IR_TOO_Pos (18U)
4499#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos)
4500#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk
4501#define FDCAN_IR_DRX_Pos (19U)
4502#define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos)
4503#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk
4504#define FDCAN_IR_ELO_Pos (22U)
4505#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos)
4506#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk
4507#define FDCAN_IR_EP_Pos (23U)
4508#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos)
4509#define FDCAN_IR_EP FDCAN_IR_EP_Msk
4510#define FDCAN_IR_EW_Pos (24U)
4511#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos)
4512#define FDCAN_IR_EW FDCAN_IR_EW_Msk
4513#define FDCAN_IR_BO_Pos (25U)
4514#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos)
4515#define FDCAN_IR_BO FDCAN_IR_BO_Msk
4516#define FDCAN_IR_WDI_Pos (26U)
4517#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos)
4518#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk
4519#define FDCAN_IR_PEA_Pos (27U)
4520#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos)
4521#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk
4522#define FDCAN_IR_PED_Pos (28U)
4523#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos)
4524#define FDCAN_IR_PED FDCAN_IR_PED_Msk
4525#define FDCAN_IR_ARA_Pos (29U)
4526#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos)
4527#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk
4529/***************** Bit definition for FDCAN_IE register **********************/
4530#define FDCAN_IE_RF0NE_Pos (0U)
4531#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos)
4532#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk
4533#define FDCAN_IE_RF0WE_Pos (1U)
4534#define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos)
4535#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk
4536#define FDCAN_IE_RF0FE_Pos (2U)
4537#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos)
4538#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk
4539#define FDCAN_IE_RF0LE_Pos (3U)
4540#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos)
4541#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk
4542#define FDCAN_IE_RF1NE_Pos (4U)
4543#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos)
4544#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk
4545#define FDCAN_IE_RF1WE_Pos (5U)
4546#define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos)
4547#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk
4548#define FDCAN_IE_RF1FE_Pos (6U)
4549#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos)
4550#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk
4551#define FDCAN_IE_RF1LE_Pos (7U)
4552#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos)
4553#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk
4554#define FDCAN_IE_HPME_Pos (8U)
4555#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos)
4556#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk
4557#define FDCAN_IE_TCE_Pos (9U)
4558#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos)
4559#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk
4560#define FDCAN_IE_TCFE_Pos (10U)
4561#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos)
4562#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk
4563#define FDCAN_IE_TFEE_Pos (11U)
4564#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos)
4565#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk
4566#define FDCAN_IE_TEFNE_Pos (12U)
4567#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos)
4568#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk
4569#define FDCAN_IE_TEFWE_Pos (13U)
4570#define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos)
4571#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk
4572#define FDCAN_IE_TEFFE_Pos (14U)
4573#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos)
4574#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk
4575#define FDCAN_IE_TEFLE_Pos (15U)
4576#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos)
4577#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk
4578#define FDCAN_IE_TSWE_Pos (16U)
4579#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos)
4580#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk
4581#define FDCAN_IE_MRAFE_Pos (17U)
4582#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos)
4583#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk
4584#define FDCAN_IE_TOOE_Pos (18U)
4585#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos)
4586#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk
4587#define FDCAN_IE_DRXE_Pos (19U)
4588#define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos)
4589#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk
4590#define FDCAN_IE_BECE_Pos (20U)
4591#define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos)
4592#define FDCAN_IE_BECE FDCAN_IE_BECE_Msk
4593#define FDCAN_IE_BEUE_Pos (21U)
4594#define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos)
4595#define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk
4596#define FDCAN_IE_ELOE_Pos (22U)
4597#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos)
4598#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk
4599#define FDCAN_IE_EPE_Pos (23U)
4600#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos)
4601#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk
4602#define FDCAN_IE_EWE_Pos (24U)
4603#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos)
4604#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk
4605#define FDCAN_IE_BOE_Pos (25U)
4606#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos)
4607#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk
4608#define FDCAN_IE_WDIE_Pos (26U)
4609#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos)
4610#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk
4611#define FDCAN_IE_PEAE_Pos (27U)
4612#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos)
4613#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk
4614#define FDCAN_IE_PEDE_Pos (28U)
4615#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos)
4616#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk
4617#define FDCAN_IE_ARAE_Pos (29U)
4618#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos)
4619#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk
4621/***************** Bit definition for FDCAN_ILS register **********************/
4622#define FDCAN_ILS_RF0NL_Pos (0U)
4623#define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos)
4624#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk
4625#define FDCAN_ILS_RF0WL_Pos (1U)
4626#define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos)
4627#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk
4628#define FDCAN_ILS_RF0FL_Pos (2U)
4629#define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos)
4630#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk
4631#define FDCAN_ILS_RF0LL_Pos (3U)
4632#define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos)
4633#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk
4634#define FDCAN_ILS_RF1NL_Pos (4U)
4635#define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos)
4636#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk
4637#define FDCAN_ILS_RF1WL_Pos (5U)
4638#define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos)
4639#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk
4640#define FDCAN_ILS_RF1FL_Pos (6U)
4641#define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos)
4642#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk
4643#define FDCAN_ILS_RF1LL_Pos (7U)
4644#define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos)
4645#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk
4646#define FDCAN_ILS_HPML_Pos (8U)
4647#define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos)
4648#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk
4649#define FDCAN_ILS_TCL_Pos (9U)
4650#define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos)
4651#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk
4652#define FDCAN_ILS_TCFL_Pos (10U)
4653#define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos)
4654#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk
4655#define FDCAN_ILS_TFEL_Pos (11U)
4656#define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos)
4657#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk
4658#define FDCAN_ILS_TEFNL_Pos (12U)
4659#define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos)
4660#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk
4661#define FDCAN_ILS_TEFWL_Pos (13U)
4662#define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos)
4663#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk
4664#define FDCAN_ILS_TEFFL_Pos (14U)
4665#define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos)
4666#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk
4667#define FDCAN_ILS_TEFLL_Pos (15U)
4668#define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos)
4669#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk
4670#define FDCAN_ILS_TSWL_Pos (16U)
4671#define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos)
4672#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk
4673#define FDCAN_ILS_MRAFE_Pos (17U)
4674#define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos)
4675#define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk
4676#define FDCAN_ILS_TOOE_Pos (18U)
4677#define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos)
4678#define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk
4679#define FDCAN_ILS_DRXE_Pos (19U)
4680#define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos)
4681#define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk
4682#define FDCAN_ILS_BECE_Pos (20U)
4683#define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos)
4684#define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk
4685#define FDCAN_ILS_BEUE_Pos (21U)
4686#define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos)
4687#define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk
4688#define FDCAN_ILS_ELOE_Pos (22U)
4689#define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos)
4690#define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk
4691#define FDCAN_ILS_EPE_Pos (23U)
4692#define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos)
4693#define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk
4694#define FDCAN_ILS_EWE_Pos (24U)
4695#define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos)
4696#define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk
4697#define FDCAN_ILS_BOE_Pos (25U)
4698#define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos)
4699#define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk
4700#define FDCAN_ILS_WDIE_Pos (26U)
4701#define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos)
4702#define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk
4703#define FDCAN_ILS_PEAE_Pos (27U)
4704#define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos)
4705#define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk
4706#define FDCAN_ILS_PEDE_Pos (28U)
4707#define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos)
4708#define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk
4709#define FDCAN_ILS_ARAE_Pos (29U)
4710#define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos)
4711#define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk
4713/***************** Bit definition for FDCAN_ILE register **********************/
4714#define FDCAN_ILE_EINT0_Pos (0U)
4715#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos)
4716#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk
4717#define FDCAN_ILE_EINT1_Pos (1U)
4718#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos)
4719#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk
4721/***************** Bit definition for FDCAN_GFC register **********************/
4722#define FDCAN_GFC_RRFE_Pos (0U)
4723#define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos)
4724#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk
4725#define FDCAN_GFC_RRFS_Pos (1U)
4726#define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos)
4727#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk
4728#define FDCAN_GFC_ANFE_Pos (2U)
4729#define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos)
4730#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk
4731#define FDCAN_GFC_ANFS_Pos (4U)
4732#define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos)
4733#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk
4735/***************** Bit definition for FDCAN_SIDFC register ********************/
4736#define FDCAN_SIDFC_FLSSA_Pos (2U)
4737#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)
4738#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk
4739#define FDCAN_SIDFC_LSS_Pos (16U)
4740#define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos)
4741#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk
4743/***************** Bit definition for FDCAN_XIDFC register ********************/
4744#define FDCAN_XIDFC_FLESA_Pos (2U)
4745#define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)
4746#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk
4747#define FDCAN_XIDFC_LSE_Pos (16U)
4748#define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos)
4749#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk
4751/***************** Bit definition for FDCAN_XIDAM register ********************/
4752#define FDCAN_XIDAM_EIDM_Pos (0U)
4753#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)
4754#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk
4756/***************** Bit definition for FDCAN_HPMS register *********************/
4757#define FDCAN_HPMS_BIDX_Pos (0U)
4758#define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos)
4759#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk
4760#define FDCAN_HPMS_MSI_Pos (6U)
4761#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos)
4762#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk
4763#define FDCAN_HPMS_FIDX_Pos (8U)
4764#define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos)
4765#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk
4766#define FDCAN_HPMS_FLST_Pos (15U)
4767#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos)
4768#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk
4770/***************** Bit definition for FDCAN_NDAT1 register ********************/
4771#define FDCAN_NDAT1_ND0_Pos (0U)
4772#define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos)
4773#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk
4774#define FDCAN_NDAT1_ND1_Pos (1U)
4775#define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos)
4776#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk
4777#define FDCAN_NDAT1_ND2_Pos (2U)
4778#define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos)
4779#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk
4780#define FDCAN_NDAT1_ND3_Pos (3U)
4781#define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos)
4782#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk
4783#define FDCAN_NDAT1_ND4_Pos (4U)
4784#define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos)
4785#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk
4786#define FDCAN_NDAT1_ND5_Pos (5U)
4787#define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos)
4788#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk
4789#define FDCAN_NDAT1_ND6_Pos (6U)
4790#define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos)
4791#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk
4792#define FDCAN_NDAT1_ND7_Pos (7U)
4793#define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos)
4794#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk
4795#define FDCAN_NDAT1_ND8_Pos (8U)
4796#define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos)
4797#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk
4798#define FDCAN_NDAT1_ND9_Pos (9U)
4799#define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos)
4800#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk
4801#define FDCAN_NDAT1_ND10_Pos (10U)
4802#define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos)
4803#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk
4804#define FDCAN_NDAT1_ND11_Pos (11U)
4805#define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos)
4806#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk
4807#define FDCAN_NDAT1_ND12_Pos (12U)
4808#define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos)
4809#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk
4810#define FDCAN_NDAT1_ND13_Pos (13U)
4811#define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos)
4812#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk
4813#define FDCAN_NDAT1_ND14_Pos (14U)
4814#define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos)
4815#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk
4816#define FDCAN_NDAT1_ND15_Pos (15U)
4817#define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos)
4818#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk
4819#define FDCAN_NDAT1_ND16_Pos (16U)
4820#define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos)
4821#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk
4822#define FDCAN_NDAT1_ND17_Pos (17U)
4823#define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos)
4824#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk
4825#define FDCAN_NDAT1_ND18_Pos (18U)
4826#define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos)
4827#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk
4828#define FDCAN_NDAT1_ND19_Pos (19U)
4829#define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos)
4830#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk
4831#define FDCAN_NDAT1_ND20_Pos (20U)
4832#define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos)
4833#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk
4834#define FDCAN_NDAT1_ND21_Pos (21U)
4835#define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos)
4836#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk
4837#define FDCAN_NDAT1_ND22_Pos (22U)
4838#define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos)
4839#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk
4840#define FDCAN_NDAT1_ND23_Pos (23U)
4841#define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos)
4842#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk
4843#define FDCAN_NDAT1_ND24_Pos (24U)
4844#define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos)
4845#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk
4846#define FDCAN_NDAT1_ND25_Pos (25U)
4847#define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos)
4848#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk
4849#define FDCAN_NDAT1_ND26_Pos (26U)
4850#define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos)
4851#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk
4852#define FDCAN_NDAT1_ND27_Pos (27U)
4853#define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos)
4854#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk
4855#define FDCAN_NDAT1_ND28_Pos (28U)
4856#define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos)
4857#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk
4858#define FDCAN_NDAT1_ND29_Pos (29U)
4859#define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos)
4860#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk
4861#define FDCAN_NDAT1_ND30_Pos (30U)
4862#define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos)
4863#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk
4864#define FDCAN_NDAT1_ND31_Pos (31U)
4865#define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos)
4866#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk
4868/***************** Bit definition for FDCAN_NDAT2 register ********************/
4869#define FDCAN_NDAT2_ND32_Pos (0U)
4870#define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos)
4871#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk
4872#define FDCAN_NDAT2_ND33_Pos (1U)
4873#define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos)
4874#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk
4875#define FDCAN_NDAT2_ND34_Pos (2U)
4876#define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos)
4877#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk
4878#define FDCAN_NDAT2_ND35_Pos (3U)
4879#define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos)
4880#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk
4881#define FDCAN_NDAT2_ND36_Pos (4U)
4882#define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos)
4883#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk
4884#define FDCAN_NDAT2_ND37_Pos (5U)
4885#define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos)
4886#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk
4887#define FDCAN_NDAT2_ND38_Pos (6U)
4888#define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos)
4889#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk
4890#define FDCAN_NDAT2_ND39_Pos (7U)
4891#define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos)
4892#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk
4893#define FDCAN_NDAT2_ND40_Pos (8U)
4894#define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos)
4895#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk
4896#define FDCAN_NDAT2_ND41_Pos (9U)
4897#define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos)
4898#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk
4899#define FDCAN_NDAT2_ND42_Pos (10U)
4900#define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos)
4901#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk
4902#define FDCAN_NDAT2_ND43_Pos (11U)
4903#define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos)
4904#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk
4905#define FDCAN_NDAT2_ND44_Pos (12U)
4906#define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos)
4907#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk
4908#define FDCAN_NDAT2_ND45_Pos (13U)
4909#define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos)
4910#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk
4911#define FDCAN_NDAT2_ND46_Pos (14U)
4912#define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos)
4913#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk
4914#define FDCAN_NDAT2_ND47_Pos (15U)
4915#define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos)
4916#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk
4917#define FDCAN_NDAT2_ND48_Pos (16U)
4918#define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos)
4919#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk
4920#define FDCAN_NDAT2_ND49_Pos (17U)
4921#define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos)
4922#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk
4923#define FDCAN_NDAT2_ND50_Pos (18U)
4924#define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos)
4925#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk
4926#define FDCAN_NDAT2_ND51_Pos (19U)
4927#define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos)
4928#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk
4929#define FDCAN_NDAT2_ND52_Pos (20U)
4930#define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos)
4931#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk
4932#define FDCAN_NDAT2_ND53_Pos (21U)
4933#define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos)
4934#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk
4935#define FDCAN_NDAT2_ND54_Pos (22U)
4936#define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos)
4937#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk
4938#define FDCAN_NDAT2_ND55_Pos (23U)
4939#define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos)
4940#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk
4941#define FDCAN_NDAT2_ND56_Pos (24U)
4942#define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos)
4943#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk
4944#define FDCAN_NDAT2_ND57_Pos (25U)
4945#define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos)
4946#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk
4947#define FDCAN_NDAT2_ND58_Pos (26U)
4948#define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos)
4949#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk
4950#define FDCAN_NDAT2_ND59_Pos (27U)
4951#define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos)
4952#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk
4953#define FDCAN_NDAT2_ND60_Pos (28U)
4954#define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos)
4955#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk
4956#define FDCAN_NDAT2_ND61_Pos (29U)
4957#define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos)
4958#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk
4959#define FDCAN_NDAT2_ND62_Pos (30U)
4960#define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos)
4961#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk
4962#define FDCAN_NDAT2_ND63_Pos (31U)
4963#define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos)
4964#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk
4966/***************** Bit definition for FDCAN_RXF0C register ********************/
4967#define FDCAN_RXF0C_F0SA_Pos (2U)
4968#define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)
4969#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk
4970#define FDCAN_RXF0C_F0S_Pos (16U)
4971#define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos)
4972#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk
4973#define FDCAN_RXF0C_F0WM_Pos (24U)
4974#define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos)
4975#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk
4976#define FDCAN_RXF0C_F0OM_Pos (31U)
4977#define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos)
4978#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk
4980/***************** Bit definition for FDCAN_RXF0S register ********************/
4981#define FDCAN_RXF0S_F0FL_Pos (0U)
4982#define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos)
4983#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk
4984#define FDCAN_RXF0S_F0GI_Pos (8U)
4985#define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos)
4986#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk
4987#define FDCAN_RXF0S_F0PI_Pos (16U)
4988#define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos)
4989#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk
4990#define FDCAN_RXF0S_F0F_Pos (24U)
4991#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos)
4992#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk
4993#define FDCAN_RXF0S_RF0L_Pos (25U)
4994#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos)
4995#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk
4997/***************** Bit definition for FDCAN_RXF0A register ********************/
4998#define FDCAN_RXF0A_F0AI_Pos (0U)
4999#define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos)
5000#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk
5002/***************** Bit definition for FDCAN_RXBC register ********************/
5003#define FDCAN_RXBC_RBSA_Pos (2U)
5004#define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)
5005#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk
5007/***************** Bit definition for FDCAN_RXF1C register ********************/
5008#define FDCAN_RXF1C_F1SA_Pos (2U)
5009#define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)
5010#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk
5011#define FDCAN_RXF1C_F1S_Pos (16U)
5012#define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos)
5013#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk
5014#define FDCAN_RXF1C_F1WM_Pos (24U)
5015#define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos)
5016#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk
5017#define FDCAN_RXF1C_F1OM_Pos (31U)
5018#define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos)
5019#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk
5021/***************** Bit definition for FDCAN_RXF1S register ********************/
5022#define FDCAN_RXF1S_F1FL_Pos (0U)
5023#define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos)
5024#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk
5025#define FDCAN_RXF1S_F1GI_Pos (8U)
5026#define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos)
5027#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk
5028#define FDCAN_RXF1S_F1PI_Pos (16U)
5029#define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos)
5030#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk
5031#define FDCAN_RXF1S_F1F_Pos (24U)
5032#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos)
5033#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk
5034#define FDCAN_RXF1S_RF1L_Pos (25U)
5035#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos)
5036#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk
5038/***************** Bit definition for FDCAN_RXF1A register ********************/
5039#define FDCAN_RXF1A_F1AI_Pos (0U)
5040#define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos)
5041#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk
5043/***************** Bit definition for FDCAN_RXESC register ********************/
5044#define FDCAN_RXESC_F0DS_Pos (0U)
5045#define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos)
5046#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk
5047#define FDCAN_RXESC_F1DS_Pos (4U)
5048#define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos)
5049#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk
5050#define FDCAN_RXESC_RBDS_Pos (8U)
5051#define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos)
5052#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk
5054/***************** Bit definition for FDCAN_TXBC register *********************/
5055#define FDCAN_TXBC_TBSA_Pos (2U)
5056#define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)
5057#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk
5058#define FDCAN_TXBC_NDTB_Pos (16U)
5059#define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos)
5060#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk
5061#define FDCAN_TXBC_TFQS_Pos (24U)
5062#define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos)
5063#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk
5064#define FDCAN_TXBC_TFQM_Pos (30U)
5065#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos)
5066#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk
5068/***************** Bit definition for FDCAN_TXFQS register *********************/
5069#define FDCAN_TXFQS_TFFL_Pos (0U)
5070#define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos)
5071#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk
5072#define FDCAN_TXFQS_TFGI_Pos (8U)
5073#define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos)
5074#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk
5075#define FDCAN_TXFQS_TFQPI_Pos (16U)
5076#define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)
5077#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk
5078#define FDCAN_TXFQS_TFQF_Pos (21U)
5079#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos)
5080#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk
5082/***************** Bit definition for FDCAN_TXESC register *********************/
5083#define FDCAN_TXESC_TBDS_Pos (0U)
5084#define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos)
5085#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk
5087/***************** Bit definition for FDCAN_TXBRP register *********************/
5088#define FDCAN_TXBRP_TRP_Pos (0U)
5089#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)
5090#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk
5092/***************** Bit definition for FDCAN_TXBAR register *********************/
5093#define FDCAN_TXBAR_AR_Pos (0U)
5094#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)
5095#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk
5097/***************** Bit definition for FDCAN_TXBCR register *********************/
5098#define FDCAN_TXBCR_CR_Pos (0U)
5099#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)
5100#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk
5102/***************** Bit definition for FDCAN_TXBTO register *********************/
5103#define FDCAN_TXBTO_TO_Pos (0U)
5104#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)
5105#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk
5107/***************** Bit definition for FDCAN_TXBCF register *********************/
5108#define FDCAN_TXBCF_CF_Pos (0U)
5109#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)
5110#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk
5112/***************** Bit definition for FDCAN_TXBTIE register ********************/
5113#define FDCAN_TXBTIE_TIE_Pos (0U)
5114#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)
5115#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk
5117/***************** Bit definition for FDCAN_ TXBCIE register *******************/
5118#define FDCAN_TXBCIE_CFIE_Pos (0U)
5119#define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)
5120#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk
5122/***************** Bit definition for FDCAN_TXEFC register *********************/
5123#define FDCAN_TXEFC_EFSA_Pos (2U)
5124#define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)
5125#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk
5126#define FDCAN_TXEFC_EFS_Pos (16U)
5127#define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos)
5128#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk
5129#define FDCAN_TXEFC_EFWM_Pos (24U)
5130#define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos)
5131#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk
5133/***************** Bit definition for FDCAN_TXEFS register *********************/
5134#define FDCAN_TXEFS_EFFL_Pos (0U)
5135#define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos)
5136#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk
5137#define FDCAN_TXEFS_EFGI_Pos (8U)
5138#define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos)
5139#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk
5140#define FDCAN_TXEFS_EFPI_Pos (16U)
5141#define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos)
5142#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk
5143#define FDCAN_TXEFS_EFF_Pos (24U)
5144#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos)
5145#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk
5146#define FDCAN_TXEFS_TEFL_Pos (25U)
5147#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos)
5148#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk
5150/***************** Bit definition for FDCAN_TXEFA register *********************/
5151#define FDCAN_TXEFA_EFAI_Pos (0U)
5152#define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos)
5153#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk
5155/***************** Bit definition for FDCAN_TTTMC register *********************/
5156#define FDCAN_TTTMC_TMSA_Pos (2U)
5157#define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)
5158#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk
5159#define FDCAN_TTTMC_TME_Pos (16U)
5160#define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos)
5161#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk
5163/***************** Bit definition for FDCAN_TTRMC register *********************/
5164#define FDCAN_TTRMC_RID_Pos (0U)
5165#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)
5166#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk
5167#define FDCAN_TTRMC_XTD_Pos (30U)
5168#define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos)
5169#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk
5170#define FDCAN_TTRMC_RMPS_Pos (31U)
5171#define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos)
5172#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk
5174/***************** Bit definition for FDCAN_TTOCF register *********************/
5175#define FDCAN_TTOCF_OM_Pos (0U)
5176#define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos)
5177#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk
5178#define FDCAN_TTOCF_GEN_Pos (3U)
5179#define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos)
5180#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk
5181#define FDCAN_TTOCF_TM_Pos (4U)
5182#define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos)
5183#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk
5184#define FDCAN_TTOCF_LDSDL_Pos (5U)
5185#define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos)
5186#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk
5187#define FDCAN_TTOCF_IRTO_Pos (8U)
5188#define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos)
5189#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk
5190#define FDCAN_TTOCF_EECS_Pos (15U)
5191#define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos)
5192#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk
5193#define FDCAN_TTOCF_AWL_Pos (16U)
5194#define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos)
5195#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk
5196#define FDCAN_TTOCF_EGTF_Pos (24U)
5197#define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos)
5198#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk
5199#define FDCAN_TTOCF_ECC_Pos (25U)
5200#define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos)
5201#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk
5202#define FDCAN_TTOCF_EVTP_Pos (26U)
5203#define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos)
5204#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk
5206/***************** Bit definition for FDCAN_TTMLM register *********************/
5207#define FDCAN_TTMLM_CCM_Pos (0U)
5208#define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos)
5209#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk
5210#define FDCAN_TTMLM_CSS_Pos (6U)
5211#define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos)
5212#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk
5213#define FDCAN_TTMLM_TXEW_Pos (8U)
5214#define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos)
5215#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk
5216#define FDCAN_TTMLM_ENTT_Pos (16U)
5217#define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)
5218#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk
5220/***************** Bit definition for FDCAN_TURCF register *********************/
5221#define FDCAN_TURCF_NCL_Pos (0U)
5222#define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos)
5223#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk
5224#define FDCAN_TURCF_DC_Pos (16U)
5225#define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos)
5226#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk
5227#define FDCAN_TURCF_ELT_Pos (31U)
5228#define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos)
5229#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk
5231/***************** Bit definition for FDCAN_TTOCN register ********************/
5232#define FDCAN_TTOCN_SGT_Pos (0U)
5233#define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos)
5234#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk
5235#define FDCAN_TTOCN_ECS_Pos (1U)
5236#define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos)
5237#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk
5238#define FDCAN_TTOCN_SWP_Pos (2U)
5239#define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos)
5240#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk
5241#define FDCAN_TTOCN_SWS_Pos (3U)
5242#define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos)
5243#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk
5244#define FDCAN_TTOCN_RTIE_Pos (5U)
5245#define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos)
5246#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk
5247#define FDCAN_TTOCN_TMC_Pos (6U)
5248#define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos)
5249#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk
5250#define FDCAN_TTOCN_TTIE_Pos (8U)
5251#define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos)
5252#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk
5253#define FDCAN_TTOCN_GCS_Pos (9U)
5254#define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos)
5255#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk
5256#define FDCAN_TTOCN_FGP_Pos (10U)
5257#define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos)
5258#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk
5259#define FDCAN_TTOCN_TMG_Pos (11U)
5260#define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos)
5261#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk
5262#define FDCAN_TTOCN_NIG_Pos (12U)
5263#define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos)
5264#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk
5265#define FDCAN_TTOCN_ESCN_Pos (13U)
5266#define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos)
5267#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk
5268#define FDCAN_TTOCN_LCKC_Pos (15U)
5269#define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos)
5270#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk
5272/***************** Bit definition for FDCAN_TTGTP register ********************/
5273#define FDCAN_TTGTP_TP_Pos (0U)
5274#define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos)
5275#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk
5276#define FDCAN_TTGTP_CTP_Pos (16U)
5277#define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)
5278#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk
5280/***************** Bit definition for FDCAN_TTTMK register ********************/
5281#define FDCAN_TTTMK_TM_Pos (0U)
5282#define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos)
5283#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk
5284#define FDCAN_TTTMK_TICC_Pos (16U)
5285#define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos)
5286#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk
5287#define FDCAN_TTTMK_LCKM_Pos (31U)
5288#define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos)
5289#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk
5291/***************** Bit definition for FDCAN_TTIR register ********************/
5292#define FDCAN_TTIR_SBC_Pos (0U)
5293#define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos)
5294#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk
5295#define FDCAN_TTIR_SMC_Pos (1U)
5296#define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos)
5297#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk
5298#define FDCAN_TTIR_CSM_Pos (2U)
5299#define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos)
5300#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk
5301#define FDCAN_TTIR_SOG_Pos (3U)
5302#define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos)
5303#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk
5304#define FDCAN_TTIR_RTMI_Pos (4U)
5305#define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos)
5306#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk
5307#define FDCAN_TTIR_TTMI_Pos (5U)
5308#define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos)
5309#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk
5310#define FDCAN_TTIR_SWE_Pos (6U)
5311#define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos)
5312#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk
5313#define FDCAN_TTIR_GTW_Pos (7U)
5314#define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos)
5315#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk
5316#define FDCAN_TTIR_GTD_Pos (8U)
5317#define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos)
5318#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk
5319#define FDCAN_TTIR_GTE_Pos (9U)
5320#define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos)
5321#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk
5322#define FDCAN_TTIR_TXU_Pos (10U)
5323#define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos)
5324#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk
5325#define FDCAN_TTIR_TXO_Pos (11U)
5326#define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos)
5327#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk
5328#define FDCAN_TTIR_SE1_Pos (12U)
5329#define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos)
5330#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk
5331#define FDCAN_TTIR_SE2_Pos (13U)
5332#define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos)
5333#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk
5334#define FDCAN_TTIR_ELC_Pos (14U)
5335#define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos)
5336#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk
5337#define FDCAN_TTIR_IWT_Pos (15U)
5338#define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos)
5339#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk
5340#define FDCAN_TTIR_WT_Pos (16U)
5341#define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos)
5342#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk
5343#define FDCAN_TTIR_AW_Pos (17U)
5344#define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos)
5345#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk
5346#define FDCAN_TTIR_CER_Pos (18U)
5347#define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos)
5348#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk
5350/***************** Bit definition for FDCAN_TTIE register ********************/
5351#define FDCAN_TTIE_SBCE_Pos (0U)
5352#define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos)
5353#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk
5354#define FDCAN_TTIE_SMCE_Pos (1U)
5355#define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos)
5356#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk
5357#define FDCAN_TTIE_CSME_Pos (2U)
5358#define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos)
5359#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk
5360#define FDCAN_TTIE_SOGE_Pos (3U)
5361#define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos)
5362#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk
5363#define FDCAN_TTIE_RTMIE_Pos (4U)
5364#define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos)
5365#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk
5366#define FDCAN_TTIE_TTMIE_Pos (5U)
5367#define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos)
5368#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk
5369#define FDCAN_TTIE_SWEE_Pos (6U)
5370#define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos)
5371#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk
5372#define FDCAN_TTIE_GTWE_Pos (7U)
5373#define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos)
5374#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk
5375#define FDCAN_TTIE_GTDE_Pos (8U)
5376#define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos)
5377#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk
5378#define FDCAN_TTIE_GTEE_Pos (9U)
5379#define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos)
5380#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk
5381#define FDCAN_TTIE_TXUE_Pos (10U)
5382#define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos)
5383#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk
5384#define FDCAN_TTIE_TXOE_Pos (11U)
5385#define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos)
5386#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk
5387#define FDCAN_TTIE_SE1E_Pos (12U)
5388#define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos)
5389#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk
5390#define FDCAN_TTIE_SE2E_Pos (13U)
5391#define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos)
5392#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk
5393#define FDCAN_TTIE_ELCE_Pos (14U)
5394#define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos)
5395#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk
5396#define FDCAN_TTIE_IWTE_Pos (15U)
5397#define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos)
5398#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk
5399#define FDCAN_TTIE_WTE_Pos (16U)
5400#define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos)
5401#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk
5402#define FDCAN_TTIE_AWE_Pos (17U)
5403#define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos)
5404#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk
5405#define FDCAN_TTIE_CERE_Pos (18U)
5406#define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos)
5407#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk
5409/***************** Bit definition for FDCAN_TTILS register ********************/
5410#define FDCAN_TTILS_SBCS_Pos (0U)
5411#define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos)
5412#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk
5413#define FDCAN_TTILS_SMCS_Pos (1U)
5414#define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos)
5415#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk
5416#define FDCAN_TTILS_CSMS_Pos (2U)
5417#define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos)
5418#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk
5419#define FDCAN_TTILS_SOGS_Pos (3U)
5420#define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos)
5421#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk
5422#define FDCAN_TTILS_RTMIS_Pos (4U)
5423#define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos)
5424#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk
5425#define FDCAN_TTILS_TTMIS_Pos (5U)
5426#define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos)
5427#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk
5428#define FDCAN_TTILS_SWES_Pos (6U)
5429#define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos)
5430#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk
5431#define FDCAN_TTILS_GTWS_Pos (7U)
5432#define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos)
5433#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk
5434#define FDCAN_TTILS_GTDS_Pos (8U)
5435#define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos)
5436#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk
5437#define FDCAN_TTILS_GTES_Pos (9U)
5438#define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos)
5439#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk
5440#define FDCAN_TTILS_TXUS_Pos (10U)
5441#define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos)
5442#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk
5443#define FDCAN_TTILS_TXOS_Pos (11U)
5444#define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos)
5445#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk
5446#define FDCAN_TTILS_SE1S_Pos (12U)
5447#define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos)
5448#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk
5449#define FDCAN_TTILS_SE2S_Pos (13U)
5450#define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos)
5451#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk
5452#define FDCAN_TTILS_ELCS_Pos (14U)
5453#define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos)
5454#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk
5455#define FDCAN_TTILS_IWTS_Pos (15U)
5456#define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos)
5457#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk
5458#define FDCAN_TTILS_WTS_Pos (16U)
5459#define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos)
5460#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk
5461#define FDCAN_TTILS_AWS_Pos (17U)
5462#define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos)
5463#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk
5464#define FDCAN_TTILS_CERS_Pos (18U)
5465#define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos)
5466#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk
5468/***************** Bit definition for FDCAN_TTOST register ********************/
5469#define FDCAN_TTOST_EL_Pos (0U)
5470#define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos)
5471#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk
5472#define FDCAN_TTOST_MS_Pos (2U)
5473#define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos)
5474#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk
5475#define FDCAN_TTOST_SYS_Pos (4U)
5476#define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos)
5477#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk
5478#define FDCAN_TTOST_QGTP_Pos (6U)
5479#define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos)
5480#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk
5481#define FDCAN_TTOST_QCS_Pos (7U)
5482#define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos)
5483#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk
5484#define FDCAN_TTOST_RTO_Pos (8U)
5485#define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos)
5486#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk
5487#define FDCAN_TTOST_WGTD_Pos (22U)
5488#define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos)
5489#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk
5490#define FDCAN_TTOST_GFI_Pos (23U)
5491#define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos)
5492#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk
5493#define FDCAN_TTOST_TMP_Pos (24U)
5494#define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos)
5495#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk
5496#define FDCAN_TTOST_GSI_Pos (27U)
5497#define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos)
5498#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk
5499#define FDCAN_TTOST_WFE_Pos (28U)
5500#define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos)
5501#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk
5502#define FDCAN_TTOST_AWE_Pos (29U)
5503#define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos)
5504#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk
5505#define FDCAN_TTOST_WECS_Pos (30U)
5506#define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos)
5507#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk
5508#define FDCAN_TTOST_SPL_Pos (31U)
5509#define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos)
5510#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk
5512/***************** Bit definition for FDCAN_TURNA register ********************/
5513#define FDCAN_TURNA_NAV_Pos (0U)
5514#define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)
5515#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk
5517/***************** Bit definition for FDCAN_TTLGT register ********************/
5518#define FDCAN_TTLGT_LT_Pos (0U)
5519#define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos)
5520#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk
5521#define FDCAN_TTLGT_GT_Pos (16U)
5522#define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos)
5523#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk
5525/***************** Bit definition for FDCAN_TTCTC register ********************/
5526#define FDCAN_TTCTC_CT_Pos (0U)
5527#define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos)
5528#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk
5529#define FDCAN_TTCTC_CC_Pos (16U)
5530#define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos)
5531#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk
5533/***************** Bit definition for FDCAN_TTCPT register ********************/
5534#define FDCAN_TTCPT_CCV_Pos (0U)
5535#define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos)
5536#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk
5537#define FDCAN_TTCPT_SWV_Pos (16U)
5538#define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)
5539#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk
5541/***************** Bit definition for FDCAN_TTCSM register ********************/
5542#define FDCAN_TTCSM_CSM_Pos (0U)
5543#define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)
5544#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk
5546/***************** Bit definition for FDCAN_TTTS register *********************/
5547#define FDCAN_TTTS_SWTSEL_Pos (0U)
5548#define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos)
5549#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk
5550#define FDCAN_TTTS_EVTSEL_Pos (4U)
5551#define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos)
5552#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk
5554/********************************************************************************/
5555/* */
5556/* FDCANCCU (Clock Calibration unit) */
5557/* */
5558/********************************************************************************/
5559
5560/***************** Bit definition for FDCANCCU_CREL register ******************/
5561#define FDCANCCU_CREL_DAY_Pos (0U)
5562#define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos)
5563#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk
5564#define FDCANCCU_CREL_MON_Pos (8U)
5565#define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos)
5566#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk
5567#define FDCANCCU_CREL_YEAR_Pos (16U)
5568#define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos)
5569#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk
5570#define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5571#define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)
5572#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk
5573#define FDCANCCU_CREL_STEP_Pos (24U)
5574#define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos)
5575#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk
5576#define FDCANCCU_CREL_REL_Pos (28U)
5577#define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos)
5578#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk
5580/***************** Bit definition for FDCANCCU_CCFG register ******************/
5581#define FDCANCCU_CCFG_TQBT_Pos (0U)
5582#define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)
5583#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk
5584#define FDCANCCU_CCFG_BCC_Pos (6U)
5585#define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos)
5586#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk
5587#define FDCANCCU_CCFG_CFL_Pos (7U)
5588#define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos)
5589#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk
5590#define FDCANCCU_CCFG_OCPM_Pos (8U)
5591#define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)
5592#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk
5593#define FDCANCCU_CCFG_CDIV_Pos (16U)
5594#define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos)
5595#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk
5596#define FDCANCCU_CCFG_SWR_Pos (31U)
5597#define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos)
5598#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk
5600/***************** Bit definition for FDCANCCU_CSTAT register *****************/
5601#define FDCANCCU_CSTAT_OCPC_Pos (0U)
5602#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)
5603#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk
5604#define FDCANCCU_CSTAT_TQC_Pos (18U)
5605#define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)
5606#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk
5607#define FDCANCCU_CSTAT_CALS_Pos (30U)
5608#define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos)
5609#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk
5611/****************** Bit definition for FDCANCCU_CWD register ******************/
5612#define FDCANCCU_CWD_WDC_Pos (0U)
5613#define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)
5614#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk
5615#define FDCANCCU_CWD_WDV_Pos (16U)
5616#define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)
5617#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk
5619/****************** Bit definition for FDCANCCU_IR register *******************/
5620#define FDCANCCU_IR_CWE_Pos (0U)
5621#define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos)
5622#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk
5623#define FDCANCCU_IR_CSC_Pos (1U)
5624#define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos)
5625#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk
5627/****************** Bit definition for FDCANCCU_IE register *******************/
5628#define FDCANCCU_IE_CWEE_Pos (0U)
5629#define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos)
5630#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk
5631#define FDCANCCU_IE_CSCE_Pos (1U)
5632#define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos)
5633#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk
5635/******************************************************************************/
5636/* */
5637/* HDMI-CEC (CEC) */
5638/* */
5639/******************************************************************************/
5640
5641/******************* Bit definition for CEC_CR register *********************/
5642#define CEC_CR_CECEN_Pos (0U)
5643#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos)
5644#define CEC_CR_CECEN CEC_CR_CECEN_Msk
5645#define CEC_CR_TXSOM_Pos (1U)
5646#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos)
5647#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk
5648#define CEC_CR_TXEOM_Pos (2U)
5649#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos)
5650#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk
5652/******************* Bit definition for CEC_CFGR register *******************/
5653#define CEC_CFGR_SFT_Pos (0U)
5654#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos)
5655#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk
5656#define CEC_CFGR_RXTOL_Pos (3U)
5657#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos)
5658#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk
5659#define CEC_CFGR_BRESTP_Pos (4U)
5660#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos)
5661#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk
5662#define CEC_CFGR_BREGEN_Pos (5U)
5663#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos)
5664#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk
5665#define CEC_CFGR_LBPEGEN_Pos (6U)
5666#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos)
5667#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk
5668#define CEC_CFGR_SFTOPT_Pos (8U)
5669#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos)
5670#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk
5671#define CEC_CFGR_BRDNOGEN_Pos (7U)
5672#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos)
5673#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk
5674#define CEC_CFGR_OAR_Pos (16U)
5675#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos)
5676#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk
5677#define CEC_CFGR_LSTN_Pos (31U)
5678#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos)
5679#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk
5681/******************* Bit definition for CEC_TXDR register *******************/
5682#define CEC_TXDR_TXD_Pos (0U)
5683#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos)
5684#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk
5686/******************* Bit definition for CEC_RXDR register *******************/
5687#define CEC_RXDR_RXD_Pos (0U)
5688#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos)
5689#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk
5691/******************* Bit definition for CEC_ISR register ********************/
5692#define CEC_ISR_RXBR_Pos (0U)
5693#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos)
5694#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk
5695#define CEC_ISR_RXEND_Pos (1U)
5696#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos)
5697#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk
5698#define CEC_ISR_RXOVR_Pos (2U)
5699#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos)
5700#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk
5701#define CEC_ISR_BRE_Pos (3U)
5702#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos)
5703#define CEC_ISR_BRE CEC_ISR_BRE_Msk
5704#define CEC_ISR_SBPE_Pos (4U)
5705#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos)
5706#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk
5707#define CEC_ISR_LBPE_Pos (5U)
5708#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos)
5709#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk
5710#define CEC_ISR_RXACKE_Pos (6U)
5711#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos)
5712#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk
5713#define CEC_ISR_ARBLST_Pos (7U)
5714#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos)
5715#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk
5716#define CEC_ISR_TXBR_Pos (8U)
5717#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos)
5718#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk
5719#define CEC_ISR_TXEND_Pos (9U)
5720#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos)
5721#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk
5722#define CEC_ISR_TXUDR_Pos (10U)
5723#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos)
5724#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk
5725#define CEC_ISR_TXERR_Pos (11U)
5726#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos)
5727#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk
5728#define CEC_ISR_TXACKE_Pos (12U)
5729#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos)
5730#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk
5732/******************* Bit definition for CEC_IER register ********************/
5733#define CEC_IER_RXBRIE_Pos (0U)
5734#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos)
5735#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk
5736#define CEC_IER_RXENDIE_Pos (1U)
5737#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos)
5738#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk
5739#define CEC_IER_RXOVRIE_Pos (2U)
5740#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos)
5741#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk
5742#define CEC_IER_BREIE_Pos (3U)
5743#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos)
5744#define CEC_IER_BREIE CEC_IER_BREIE_Msk
5745#define CEC_IER_SBPEIE_Pos (4U)
5746#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos)
5747#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk
5748#define CEC_IER_LBPEIE_Pos (5U)
5749#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos)
5750#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk
5751#define CEC_IER_RXACKEIE_Pos (6U)
5752#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos)
5753#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk
5754#define CEC_IER_ARBLSTIE_Pos (7U)
5755#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos)
5756#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk
5757#define CEC_IER_TXBRIE_Pos (8U)
5758#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos)
5759#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk
5760#define CEC_IER_TXENDIE_Pos (9U)
5761#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos)
5762#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk
5763#define CEC_IER_TXUDRIE_Pos (10U)
5764#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos)
5765#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk
5766#define CEC_IER_TXERRIE_Pos (11U)
5767#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos)
5768#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk
5769#define CEC_IER_TXACKEIE_Pos (12U)
5770#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos)
5771#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk
5773/******************************************************************************/
5774/* */
5775/* CRC calculation unit */
5776/* */
5777/******************************************************************************/
5778/******************* Bit definition for CRC_DR register *********************/
5779#define CRC_DR_DR_Pos (0U)
5780#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5781#define CRC_DR_DR CRC_DR_DR_Msk
5783/******************* Bit definition for CRC_IDR register ********************/
5784#define CRC_IDR_IDR_Pos (0U)
5785#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)
5786#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5788/******************** Bit definition for CRC_CR register ********************/
5789#define CRC_CR_RESET_Pos (0U)
5790#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5791#define CRC_CR_RESET CRC_CR_RESET_Msk
5792#define CRC_CR_POLYSIZE_Pos (3U)
5793#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
5794#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
5795#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
5796#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
5797#define CRC_CR_REV_IN_Pos (5U)
5798#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
5799#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
5800#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
5801#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
5802#define CRC_CR_REV_OUT_Pos (7U)
5803#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
5804#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
5806/******************* Bit definition for CRC_INIT register *******************/
5807#define CRC_INIT_INIT_Pos (0U)
5808#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
5809#define CRC_INIT_INIT CRC_INIT_INIT_Msk
5811/******************* Bit definition for CRC_POL register ********************/
5812#define CRC_POL_POL_Pos (0U)
5813#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
5814#define CRC_POL_POL CRC_POL_POL_Msk
5816/******************************************************************************/
5817/* */
5818/* CRS Clock Recovery System */
5819/******************************************************************************/
5820
5821/******************* Bit definition for CRS_CR register *********************/
5822#define CRS_CR_SYNCOKIE_Pos (0U)
5823#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos)
5824#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk
5825#define CRS_CR_SYNCWARNIE_Pos (1U)
5826#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos)
5827#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk
5828#define CRS_CR_ERRIE_Pos (2U)
5829#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos)
5830#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk
5831#define CRS_CR_ESYNCIE_Pos (3U)
5832#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos)
5833#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk
5834#define CRS_CR_CEN_Pos (5U)
5835#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos)
5836#define CRS_CR_CEN CRS_CR_CEN_Msk
5837#define CRS_CR_AUTOTRIMEN_Pos (6U)
5838#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos)
5839#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk
5840#define CRS_CR_SWSYNC_Pos (7U)
5841#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos)
5842#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk
5843#define CRS_CR_TRIM_Pos (8U)
5844#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos)
5845#define CRS_CR_TRIM CRS_CR_TRIM_Msk
5847/******************* Bit definition for CRS_CFGR register *********************/
5848#define CRS_CFGR_RELOAD_Pos (0U)
5849#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos)
5850#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk
5851#define CRS_CFGR_FELIM_Pos (16U)
5852#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos)
5853#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk
5855#define CRS_CFGR_SYNCDIV_Pos (24U)
5856#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos)
5857#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk
5858#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos)
5859#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos)
5860#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos)
5862#define CRS_CFGR_SYNCSRC_Pos (28U)
5863#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos)
5864#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk
5865#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos)
5866#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos)
5868#define CRS_CFGR_SYNCPOL_Pos (31U)
5869#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos)
5870#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk
5872/******************* Bit definition for CRS_ISR register *********************/
5873#define CRS_ISR_SYNCOKF_Pos (0U)
5874#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos)
5875#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk
5876#define CRS_ISR_SYNCWARNF_Pos (1U)
5877#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos)
5878#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk
5879#define CRS_ISR_ERRF_Pos (2U)
5880#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos)
5881#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk
5882#define CRS_ISR_ESYNCF_Pos (3U)
5883#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos)
5884#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk
5885#define CRS_ISR_SYNCERR_Pos (8U)
5886#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos)
5887#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk
5888#define CRS_ISR_SYNCMISS_Pos (9U)
5889#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos)
5890#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk
5891#define CRS_ISR_TRIMOVF_Pos (10U)
5892#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos)
5893#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk
5894#define CRS_ISR_FEDIR_Pos (15U)
5895#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos)
5896#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk
5897#define CRS_ISR_FECAP_Pos (16U)
5898#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos)
5899#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk
5901/******************* Bit definition for CRS_ICR register *********************/
5902#define CRS_ICR_SYNCOKC_Pos (0U)
5903#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos)
5904#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk
5905#define CRS_ICR_SYNCWARNC_Pos (1U)
5906#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos)
5907#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk
5908#define CRS_ICR_ERRC_Pos (2U)
5909#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos)
5910#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk
5911#define CRS_ICR_ESYNCC_Pos (3U)
5912#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos)
5913#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk
5915/******************************************************************************/
5916/* */
5917/* Digital to Analog Converter */
5918/* */
5919/******************************************************************************/
5920/******************** Bit definition for DAC_CR register ********************/
5921#define DAC_CR_EN1_Pos (0U)
5922#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5923#define DAC_CR_EN1 DAC_CR_EN1_Msk
5924#define DAC_CR_TEN1_Pos (1U)
5925#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5926#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5928#define DAC_CR_TSEL1_Pos (2U)
5929#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos)
5930#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5931#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5932#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5933#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5934#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos)
5937#define DAC_CR_WAVE1_Pos (6U)
5938#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5939#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5940#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5941#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5943#define DAC_CR_MAMP1_Pos (8U)
5944#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5945#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5946#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5947#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5948#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5949#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5951#define DAC_CR_DMAEN1_Pos (12U)
5952#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5953#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5954#define DAC_CR_DMAUDRIE1_Pos (13U)
5955#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5956#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5957#define DAC_CR_CEN1_Pos (14U)
5958#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)
5959#define DAC_CR_CEN1 DAC_CR_CEN1_Msk
5961#define DAC_CR_EN2_Pos (16U)
5962#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5963#define DAC_CR_EN2 DAC_CR_EN2_Msk
5964#define DAC_CR_TEN2_Pos (17U)
5965#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5966#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5968#define DAC_CR_TSEL2_Pos (18U)
5969#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos)
5970#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5971#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5972#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5973#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5974#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos)
5977#define DAC_CR_WAVE2_Pos (22U)
5978#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5979#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5980#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5981#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5983#define DAC_CR_MAMP2_Pos (24U)
5984#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5985#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5986#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5987#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5988#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5989#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5991#define DAC_CR_DMAEN2_Pos (28U)
5992#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5993#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5994#define DAC_CR_DMAUDRIE2_Pos (29U)
5995#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5996#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5997#define DAC_CR_CEN2_Pos (30U)
5998#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)
5999#define DAC_CR_CEN2 DAC_CR_CEN2_Msk
6001/***************** Bit definition for DAC_SWTRIGR register ******************/
6002#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6003#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
6004#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
6005#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6006#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
6007#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
6009/***************** Bit definition for DAC_DHR12R1 register ******************/
6010#define DAC_DHR12R1_DACC1DHR_Pos (0U)
6011#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
6012#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
6014/***************** Bit definition for DAC_DHR12L1 register ******************/
6015#define DAC_DHR12L1_DACC1DHR_Pos (4U)
6016#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
6017#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
6019/****************** Bit definition for DAC_DHR8R1 register ******************/
6020#define DAC_DHR8R1_DACC1DHR_Pos (0U)
6021#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
6022#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
6024/***************** Bit definition for DAC_DHR12R2 register ******************/
6025#define DAC_DHR12R2_DACC2DHR_Pos (0U)
6026#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
6027#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
6029/***************** Bit definition for DAC_DHR12L2 register ******************/
6030#define DAC_DHR12L2_DACC2DHR_Pos (4U)
6031#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
6032#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
6034/****************** Bit definition for DAC_DHR8R2 register ******************/
6035#define DAC_DHR8R2_DACC2DHR_Pos (0U)
6036#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
6037#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
6039/***************** Bit definition for DAC_DHR12RD register ******************/
6040#define DAC_DHR12RD_DACC1DHR_Pos (0U)
6041#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
6042#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
6043#define DAC_DHR12RD_DACC2DHR_Pos (16U)
6044#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
6045#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
6047/***************** Bit definition for DAC_DHR12LD register ******************/
6048#define DAC_DHR12LD_DACC1DHR_Pos (4U)
6049#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
6050#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
6051#define DAC_DHR12LD_DACC2DHR_Pos (20U)
6052#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
6053#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
6055/****************** Bit definition for DAC_DHR8RD register ******************/
6056#define DAC_DHR8RD_DACC1DHR_Pos (0U)
6057#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
6058#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
6059#define DAC_DHR8RD_DACC2DHR_Pos (8U)
6060#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
6061#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
6063/******************* Bit definition for DAC_DOR1 register *******************/
6064#define DAC_DOR1_DACC1DOR_Pos (0U)
6065#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
6066#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
6068/******************* Bit definition for DAC_DOR2 register *******************/
6069#define DAC_DOR2_DACC2DOR_Pos (0U)
6070#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
6071#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
6073/******************** Bit definition for DAC_SR register ********************/
6074#define DAC_SR_DMAUDR1_Pos (13U)
6075#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
6076#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
6077#define DAC_SR_CAL_FLAG1_Pos (14U)
6078#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)
6079#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk
6080#define DAC_SR_BWST1_Pos (15U)
6081#define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos)
6082#define DAC_SR_BWST1 DAC_SR_BWST1_Msk
6084#define DAC_SR_DMAUDR2_Pos (29U)
6085#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
6086#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
6087#define DAC_SR_CAL_FLAG2_Pos (30U)
6088#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)
6089#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk
6090#define DAC_SR_BWST2_Pos (31U)
6091#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)
6092#define DAC_SR_BWST2 DAC_SR_BWST2_Msk
6094/******************* Bit definition for DAC_CCR register ********************/
6095#define DAC_CCR_OTRIM1_Pos (0U)
6096#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)
6097#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk
6098#define DAC_CCR_OTRIM2_Pos (16U)
6099#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)
6100#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk
6102/******************* Bit definition for DAC_MCR register *******************/
6103#define DAC_MCR_MODE1_Pos (0U)
6104#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)
6105#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk
6106#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)
6107#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)
6108#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)
6110#define DAC_MCR_MODE2_Pos (16U)
6111#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)
6112#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk
6113#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)
6114#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)
6115#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)
6117/****************** Bit definition for DAC_SHSR1 register ******************/
6118#define DAC_SHSR1_TSAMPLE1_Pos (0U)
6119#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)
6120#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk
6122/****************** Bit definition for DAC_SHSR2 register ******************/
6123#define DAC_SHSR2_TSAMPLE2_Pos (0U)
6124#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)
6125#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk
6127/****************** Bit definition for DAC_SHHR register ******************/
6128#define DAC_SHHR_THOLD1_Pos (0U)
6129#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)
6130#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk
6131#define DAC_SHHR_THOLD2_Pos (16U)
6132#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)
6133#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk
6135/****************** Bit definition for DAC_SHRR register ******************/
6136#define DAC_SHRR_TREFRESH1_Pos (0U)
6137#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)
6138#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk
6139#define DAC_SHRR_TREFRESH2_Pos (16U)
6140#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)
6141#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk
6143/******************************************************************************/
6144/* */
6145/* DCMI */
6146/* */
6147/******************************************************************************/
6148/******************** Bits definition for DCMI_CR register ******************/
6149#define DCMI_CR_CAPTURE_Pos (0U)
6150#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
6151#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6152#define DCMI_CR_CM_Pos (1U)
6153#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
6154#define DCMI_CR_CM DCMI_CR_CM_Msk
6155#define DCMI_CR_CROP_Pos (2U)
6156#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
6157#define DCMI_CR_CROP DCMI_CR_CROP_Msk
6158#define DCMI_CR_JPEG_Pos (3U)
6159#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
6160#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6161#define DCMI_CR_ESS_Pos (4U)
6162#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
6163#define DCMI_CR_ESS DCMI_CR_ESS_Msk
6164#define DCMI_CR_PCKPOL_Pos (5U)
6165#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
6166#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6167#define DCMI_CR_HSPOL_Pos (6U)
6168#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
6169#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6170#define DCMI_CR_VSPOL_Pos (7U)
6171#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
6172#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6173#define DCMI_CR_FCRC_0 (0x00000100U)
6174#define DCMI_CR_FCRC_1 (0x00000200U)
6175#define DCMI_CR_EDM_0 (0x00000400U)
6176#define DCMI_CR_EDM_1 (0x00000800U)
6177#define DCMI_CR_CRE_Pos (12U)
6178#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
6179#define DCMI_CR_CRE DCMI_CR_CRE_Msk
6180#define DCMI_CR_ENABLE_Pos (14U)
6181#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
6182#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6183#define DCMI_CR_BSM_Pos (16U)
6184#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos)
6185#define DCMI_CR_BSM DCMI_CR_BSM_Msk
6186#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos)
6187#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos)
6188#define DCMI_CR_OEBS_Pos (18U)
6189#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
6190#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6191#define DCMI_CR_LSM_Pos (19U)
6192#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
6193#define DCMI_CR_LSM DCMI_CR_LSM_Msk
6194#define DCMI_CR_OELS_Pos (20U)
6195#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
6196#define DCMI_CR_OELS DCMI_CR_OELS_Msk
6197
6198/******************** Bits definition for DCMI_SR register ******************/
6199#define DCMI_SR_HSYNC_Pos (0U)
6200#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
6201#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6202#define DCMI_SR_VSYNC_Pos (1U)
6203#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
6204#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6205#define DCMI_SR_FNE_Pos (2U)
6206#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
6207#define DCMI_SR_FNE DCMI_SR_FNE_Msk
6208
6209/******************** Bits definition for DCMI_RIS register ****************/
6210#define DCMI_RIS_FRAME_RIS_Pos (0U)
6211#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
6212#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6213#define DCMI_RIS_OVR_RIS_Pos (1U)
6214#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
6215#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6216#define DCMI_RIS_ERR_RIS_Pos (2U)
6217#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
6218#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6219#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6220#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
6221#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6222#define DCMI_RIS_LINE_RIS_Pos (4U)
6223#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
6224#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6225
6226/******************** Bits definition for DCMI_IER register *****************/
6227#define DCMI_IER_FRAME_IE_Pos (0U)
6228#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
6229#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6230#define DCMI_IER_OVR_IE_Pos (1U)
6231#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
6232#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6233#define DCMI_IER_ERR_IE_Pos (2U)
6234#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
6235#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6236#define DCMI_IER_VSYNC_IE_Pos (3U)
6237#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
6238#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6239#define DCMI_IER_LINE_IE_Pos (4U)
6240#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
6241#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6242
6243
6244/******************** Bits definition for DCMI_MIS register *****************/
6245#define DCMI_MIS_FRAME_MIS_Pos (0U)
6246#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
6247#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6248#define DCMI_MIS_OVR_MIS_Pos (1U)
6249#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
6250#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6251#define DCMI_MIS_ERR_MIS_Pos (2U)
6252#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
6253#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6254#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6255#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
6256#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6257#define DCMI_MIS_LINE_MIS_Pos (4U)
6258#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
6259#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6260
6261
6262/******************** Bits definition for DCMI_ICR register *****************/
6263#define DCMI_ICR_FRAME_ISC_Pos (0U)
6264#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
6265#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6266#define DCMI_ICR_OVR_ISC_Pos (1U)
6267#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
6268#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6269#define DCMI_ICR_ERR_ISC_Pos (2U)
6270#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
6271#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6272#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6273#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
6274#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6275#define DCMI_ICR_LINE_ISC_Pos (4U)
6276#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
6277#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6278
6279
6280/******************** Bits definition for DCMI_ESCR register ******************/
6281#define DCMI_ESCR_FSC_Pos (0U)
6282#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
6283#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6284#define DCMI_ESCR_LSC_Pos (8U)
6285#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
6286#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6287#define DCMI_ESCR_LEC_Pos (16U)
6288#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
6289#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6290#define DCMI_ESCR_FEC_Pos (24U)
6291#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
6292#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6293
6294/******************** Bits definition for DCMI_ESUR register ******************/
6295#define DCMI_ESUR_FSU_Pos (0U)
6296#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
6297#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6298#define DCMI_ESUR_LSU_Pos (8U)
6299#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
6300#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6301#define DCMI_ESUR_LEU_Pos (16U)
6302#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
6303#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6304#define DCMI_ESUR_FEU_Pos (24U)
6305#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
6306#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6307
6308/******************** Bits definition for DCMI_CWSTRT register ******************/
6309#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6310#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
6311#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6312#define DCMI_CWSTRT_VST_Pos (16U)
6313#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
6314#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6315
6316/******************** Bits definition for DCMI_CWSIZE register ******************/
6317#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6318#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
6319#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6320#define DCMI_CWSIZE_VLINE_Pos (16U)
6321#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
6322#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6323
6324/******************** Bits definition for DCMI_DR register ******************/
6325#define DCMI_DR_BYTE0_Pos (0U)
6326#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
6327#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6328#define DCMI_DR_BYTE1_Pos (8U)
6329#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
6330#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6331#define DCMI_DR_BYTE2_Pos (16U)
6332#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
6333#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6334#define DCMI_DR_BYTE3_Pos (24U)
6335#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
6336#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6337
6338/******************************************************************************/
6339/* */
6340/* Digital Filter for Sigma Delta Modulators */
6341/* */
6342/******************************************************************************/
6343
6344/**************** DFSDM channel configuration registers ********************/
6345
6346/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6347#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6348#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
6349#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
6350#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6351#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
6352#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
6353#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6354#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
6355#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
6356#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6357#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
6358#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
6359#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
6360#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
6361#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6362#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
6363#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
6364#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
6365#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
6366#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6367#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
6368#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
6369#define DFSDM_CHCFGR1_CHEN_Pos (7U)
6370#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
6371#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
6372#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6373#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
6374#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
6375#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6376#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
6377#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
6378#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6379#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6380#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
6381#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6382#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6383#define DFSDM_CHCFGR1_SITP_Pos (0U)
6384#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
6385#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
6386#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
6387#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
6389/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6390#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6391#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
6392#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
6393#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6394#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
6395#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
6397/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6398#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6399#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6400#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
6401#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6402#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6403#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6404#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
6405#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
6406#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6407#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
6408#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
6409#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6410#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
6411#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
6413/**************** Bit definition for DFSDM_CHWDATR register *******************/
6414#define DFSDM_CHWDATR_WDATA_Pos (0U)
6415#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
6416#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
6418/**************** Bit definition for DFSDM_CHDATINR register *****************/
6419#define DFSDM_CHDATINR_INDAT0_Pos (0U)
6420#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
6421#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
6422#define DFSDM_CHDATINR_INDAT1_Pos (16U)
6423#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
6424#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
6426/************************ DFSDM module registers ****************************/
6427
6428/******************** Bit definition for DFSDM_FLTCR1 register *******************/
6429#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6430#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
6431#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
6432#define DFSDM_FLTCR1_FAST_Pos (29U)
6433#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
6434#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
6435#define DFSDM_FLTCR1_RCH_Pos (24U)
6436#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
6437#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
6438#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6439#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
6440#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
6441#define DFSDM_FLTCR1_RSYNC_Pos (19U)
6442#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
6443#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
6444#define DFSDM_FLTCR1_RCONT_Pos (18U)
6445#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
6446#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
6447#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6448#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
6449#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
6450#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6451#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
6452#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
6453#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
6454#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
6455#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6456#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)
6457#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
6458#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6459#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6460#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6461#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6462#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6464#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6465#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
6466#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
6467#define DFSDM_FLTCR1_JSCAN_Pos (4U)
6468#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
6469#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
6470#define DFSDM_FLTCR1_JSYNC_Pos (3U)
6471#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
6472#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
6473#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6474#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
6475#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
6476#define DFSDM_FLTCR1_DFEN_Pos (0U)
6477#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
6478#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
6480/******************** Bit definition for DFSDM_FLTCR2 register *******************/
6481#define DFSDM_FLTCR2_AWDCH_Pos (16U)
6482#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
6483#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
6484#define DFSDM_FLTCR2_EXCH_Pos (8U)
6485#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
6486#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
6487#define DFSDM_FLTCR2_CKABIE_Pos (6U)
6488#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
6489#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
6490#define DFSDM_FLTCR2_SCDIE_Pos (5U)
6491#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
6492#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
6493#define DFSDM_FLTCR2_AWDIE_Pos (4U)
6494#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
6495#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
6496#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6497#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
6498#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
6499#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6500#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
6501#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
6502#define DFSDM_FLTCR2_REOCIE_Pos (1U)
6503#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
6504#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
6505#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6506#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
6507#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
6509/******************** Bit definition for DFSDM_FLTISR register *******************/
6510#define DFSDM_FLTISR_SCDF_Pos (24U)
6511#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
6512#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
6513#define DFSDM_FLTISR_CKABF_Pos (16U)
6514#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
6515#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
6516#define DFSDM_FLTISR_RCIP_Pos (14U)
6517#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
6518#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
6519#define DFSDM_FLTISR_JCIP_Pos (13U)
6520#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
6521#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
6522#define DFSDM_FLTISR_AWDF_Pos (4U)
6523#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
6524#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
6525#define DFSDM_FLTISR_ROVRF_Pos (3U)
6526#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
6527#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
6528#define DFSDM_FLTISR_JOVRF_Pos (2U)
6529#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
6530#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
6531#define DFSDM_FLTISR_REOCF_Pos (1U)
6532#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
6533#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
6534#define DFSDM_FLTISR_JEOCF_Pos (0U)
6535#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
6536#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
6538/******************** Bit definition for DFSDM_FLTICR register *******************/
6539#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6540#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
6541#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
6542#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6543#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
6544#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
6545#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6546#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
6547#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
6548#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6549#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
6550#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
6552/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6553#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6554#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
6555#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
6557/******************** Bit definition for DFSDM_FLTFCR register *******************/
6558#define DFSDM_FLTFCR_FORD_Pos (29U)
6559#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
6560#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
6561#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
6562#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
6563#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
6564#define DFSDM_FLTFCR_FOSR_Pos (16U)
6565#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
6566#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
6567#define DFSDM_FLTFCR_IOSR_Pos (0U)
6568#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
6569#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
6571/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6572#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6573#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
6574#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
6575#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6576#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
6577#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
6579/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6580#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6581#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
6582#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
6583#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6584#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
6585#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
6586#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6587#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
6588#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
6590/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6591#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6592#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
6593#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
6594#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6595#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
6596#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
6598/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6599#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6600#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
6601#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
6602#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6603#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
6604#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
6606/****************** Bit definition for DFSDM_FLTAWSR register ******************/
6607#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6608#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
6609#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
6610#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6611#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
6612#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
6614/****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6615#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6616#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
6617#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
6618#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6619#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
6620#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
6622/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6623#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6624#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
6625#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
6626#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6627#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
6628#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
6630/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6631#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6632#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
6633#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
6634#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6635#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
6636#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
6638/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6639#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6640#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
6641#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
6643/******************************************************************************/
6644/* */
6645/* BDMA Controller */
6646/* */
6647/******************************************************************************/
6648
6649/******************* Bit definition for BDMA_ISR register ********************/
6650#define BDMA_ISR_GIF0_Pos (0U)
6651#define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos)
6652#define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk
6653#define BDMA_ISR_TCIF0_Pos (1U)
6654#define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos)
6655#define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk
6656#define BDMA_ISR_HTIF0_Pos (2U)
6657#define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos)
6658#define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk
6659#define BDMA_ISR_TEIF0_Pos (3U)
6660#define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos)
6661#define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk
6662#define BDMA_ISR_GIF1_Pos (4U)
6663#define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos)
6664#define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk
6665#define BDMA_ISR_TCIF1_Pos (5U)
6666#define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos)
6667#define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk
6668#define BDMA_ISR_HTIF1_Pos (6U)
6669#define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos)
6670#define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk
6671#define BDMA_ISR_TEIF1_Pos (7U)
6672#define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos)
6673#define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk
6674#define BDMA_ISR_GIF2_Pos (8U)
6675#define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos)
6676#define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk
6677#define BDMA_ISR_TCIF2_Pos (9U)
6678#define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos)
6679#define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk
6680#define BDMA_ISR_HTIF2_Pos (10U)
6681#define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos)
6682#define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk
6683#define BDMA_ISR_TEIF2_Pos (11U)
6684#define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos)
6685#define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk
6686#define BDMA_ISR_GIF3_Pos (12U)
6687#define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos)
6688#define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk
6689#define BDMA_ISR_TCIF3_Pos (13U)
6690#define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos)
6691#define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk
6692#define BDMA_ISR_HTIF3_Pos (14U)
6693#define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos)
6694#define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk
6695#define BDMA_ISR_TEIF3_Pos (15U)
6696#define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos)
6697#define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk
6698#define BDMA_ISR_GIF4_Pos (16U)
6699#define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos)
6700#define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk
6701#define BDMA_ISR_TCIF4_Pos (17U)
6702#define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos)
6703#define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk
6704#define BDMA_ISR_HTIF4_Pos (18U)
6705#define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos)
6706#define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk
6707#define BDMA_ISR_TEIF4_Pos (19U)
6708#define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos)
6709#define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk
6710#define BDMA_ISR_GIF5_Pos (20U)
6711#define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos)
6712#define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk
6713#define BDMA_ISR_TCIF5_Pos (21U)
6714#define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos)
6715#define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk
6716#define BDMA_ISR_HTIF5_Pos (22U)
6717#define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos)
6718#define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk
6719#define BDMA_ISR_TEIF5_Pos (23U)
6720#define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos)
6721#define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk
6722#define BDMA_ISR_GIF6_Pos (24U)
6723#define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos)
6724#define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk
6725#define BDMA_ISR_TCIF6_Pos (25U)
6726#define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos)
6727#define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk
6728#define BDMA_ISR_HTIF6_Pos (26U)
6729#define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos)
6730#define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk
6731#define BDMA_ISR_TEIF6_Pos (27U)
6732#define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos)
6733#define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk
6734#define BDMA_ISR_GIF7_Pos (28U)
6735#define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos)
6736#define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk
6737#define BDMA_ISR_TCIF7_Pos (29U)
6738#define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos)
6739#define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk
6740#define BDMA_ISR_HTIF7_Pos (30U)
6741#define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos)
6742#define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk
6743#define BDMA_ISR_TEIF7_Pos (31U)
6744#define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos)
6745#define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk
6747/******************* Bit definition for BDMA_IFCR register *******************/
6748#define BDMA_IFCR_CGIF0_Pos (0U)
6749#define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos)
6750#define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk
6751#define BDMA_IFCR_CTCIF0_Pos (1U)
6752#define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos)
6753#define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk
6754#define BDMA_IFCR_CHTIF0_Pos (2U)
6755#define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos)
6756#define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk
6757#define BDMA_IFCR_CTEIF0_Pos (3U)
6758#define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos)
6759#define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk
6760#define BDMA_IFCR_CGIF1_Pos (4U)
6761#define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos)
6762#define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk
6763#define BDMA_IFCR_CTCIF1_Pos (5U)
6764#define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos)
6765#define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk
6766#define BDMA_IFCR_CHTIF1_Pos (6U)
6767#define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos)
6768#define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk
6769#define BDMA_IFCR_CTEIF1_Pos (7U)
6770#define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos)
6771#define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk
6772#define BDMA_IFCR_CGIF2_Pos (8U)
6773#define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos)
6774#define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk
6775#define BDMA_IFCR_CTCIF2_Pos (9U)
6776#define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos)
6777#define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk
6778#define BDMA_IFCR_CHTIF2_Pos (10U)
6779#define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos)
6780#define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk
6781#define BDMA_IFCR_CTEIF2_Pos (11U)
6782#define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos)
6783#define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk
6784#define BDMA_IFCR_CGIF3_Pos (12U)
6785#define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos)
6786#define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk
6787#define BDMA_IFCR_CTCIF3_Pos (13U)
6788#define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos)
6789#define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk
6790#define BDMA_IFCR_CHTIF3_Pos (14U)
6791#define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos)
6792#define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk
6793#define BDMA_IFCR_CTEIF3_Pos (15U)
6794#define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos)
6795#define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk
6796#define BDMA_IFCR_CGIF4_Pos (16U)
6797#define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos)
6798#define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk
6799#define BDMA_IFCR_CTCIF4_Pos (17U)
6800#define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos)
6801#define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk
6802#define BDMA_IFCR_CHTIF4_Pos (18U)
6803#define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos)
6804#define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk
6805#define BDMA_IFCR_CTEIF4_Pos (19U)
6806#define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos)
6807#define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk
6808#define BDMA_IFCR_CGIF5_Pos (20U)
6809#define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos)
6810#define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk
6811#define BDMA_IFCR_CTCIF5_Pos (21U)
6812#define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos)
6813#define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk
6814#define BDMA_IFCR_CHTIF5_Pos (22U)
6815#define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos)
6816#define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk
6817#define BDMA_IFCR_CTEIF5_Pos (23U)
6818#define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos)
6819#define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk
6820#define BDMA_IFCR_CGIF6_Pos (24U)
6821#define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos)
6822#define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk
6823#define BDMA_IFCR_CTCIF6_Pos (25U)
6824#define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos)
6825#define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk
6826#define BDMA_IFCR_CHTIF6_Pos (26U)
6827#define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos)
6828#define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk
6829#define BDMA_IFCR_CTEIF6_Pos (27U)
6830#define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos)
6831#define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk
6832#define BDMA_IFCR_CGIF7_Pos (28U)
6833#define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos)
6834#define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk
6835#define BDMA_IFCR_CTCIF7_Pos (29U)
6836#define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos)
6837#define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk
6838#define BDMA_IFCR_CHTIF7_Pos (30U)
6839#define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos)
6840#define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk
6841#define BDMA_IFCR_CTEIF7_Pos (31U)
6842#define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos)
6843#define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk
6845/******************* Bit definition for BDMA_CCR register ********************/
6846#define BDMA_CCR_EN_Pos (0U)
6847#define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos)
6848#define BDMA_CCR_EN BDMA_CCR_EN_Msk
6849#define BDMA_CCR_TCIE_Pos (1U)
6850#define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos)
6851#define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk
6852#define BDMA_CCR_HTIE_Pos (2U)
6853#define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos)
6854#define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk
6855#define BDMA_CCR_TEIE_Pos (3U)
6856#define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos)
6857#define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk
6858#define BDMA_CCR_DIR_Pos (4U)
6859#define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos)
6860#define BDMA_CCR_DIR BDMA_CCR_DIR_Msk
6861#define BDMA_CCR_CIRC_Pos (5U)
6862#define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos)
6863#define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk
6864#define BDMA_CCR_PINC_Pos (6U)
6865#define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos)
6866#define BDMA_CCR_PINC BDMA_CCR_PINC_Msk
6867#define BDMA_CCR_MINC_Pos (7U)
6868#define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos)
6869#define BDMA_CCR_MINC BDMA_CCR_MINC_Msk
6871#define BDMA_CCR_PSIZE_Pos (8U)
6872#define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos)
6873#define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk
6874#define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos)
6875#define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos)
6877#define BDMA_CCR_MSIZE_Pos (10U)
6878#define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos)
6879#define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk
6880#define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos)
6881#define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos)
6883#define BDMA_CCR_PL_Pos (12U)
6884#define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos)
6885#define BDMA_CCR_PL BDMA_CCR_PL_Msk
6886#define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos)
6887#define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos)
6889#define BDMA_CCR_MEM2MEM_Pos (14U)
6890#define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos)
6891#define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk
6892#define BDMA_CCR_DBM_Pos (15U)
6893#define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos)
6894#define BDMA_CCR_DBM BDMA_CCR_DBM_Msk
6895#define BDMA_CCR_CT_Pos (16U)
6896#define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos)
6897#define BDMA_CCR_CT BDMA_CCR_CT_Msk
6899/****************** Bit definition for BDMA_CNDTR register *******************/
6900#define BDMA_CNDTR_NDT_Pos (0U)
6901#define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos)
6902#define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk
6904/****************** Bit definition for BDMA_CPAR register ********************/
6905#define BDMA_CPAR_PA_Pos (0U)
6906#define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)
6907#define BDMA_CPAR_PA BDMA_CPAR_PA_Msk
6909/****************** Bit definition for BDMA_CM0AR register ********************/
6910#define BDMA_CM0AR_MA_Pos (0U)
6911#define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)
6912#define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk
6914/****************** Bit definition for BDMA_CM1AR register ********************/
6915#define BDMA_CM1AR_MA_Pos (0U)
6916#define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)
6917#define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk
6919/******************************************************************************/
6920/* */
6921/* Ethernet MAC Registers bits definitions */
6922/* */
6923/******************************************************************************/
6924/* Bit definition for Ethernet MAC Configuration Register register */
6925#define ETH_MACCR_ARP_Pos (31U)
6926#define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos)
6927#define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
6928#define ETH_MACCR_SARC_Pos (28U)
6929#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos)
6930#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
6931#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
6932#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
6933#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos)
6934#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
6935#define ETH_MACCR_SARC_INSADDR1_Pos (29U)
6936#define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos)
6937#define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
6938#define ETH_MACCR_SARC_REPADDR0_Pos (28U)
6939#define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos)
6940#define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
6941#define ETH_MACCR_SARC_REPADDR1_Pos (28U)
6942#define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos)
6943#define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
6944#define ETH_MACCR_IPC_Pos (27U)
6945#define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos)
6946#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
6947#define ETH_MACCR_IPG_Pos (24U)
6948#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos)
6949#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
6950#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
6951#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
6952#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
6953#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
6954#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
6955#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
6956#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
6957#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
6958#define ETH_MACCR_GPSLCE_Pos (23U)
6959#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos)
6960#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
6961#define ETH_MACCR_S2KP_Pos (22U)
6962#define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos)
6963#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
6964#define ETH_MACCR_CST_Pos (21U)
6965#define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos)
6966#define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
6967#define ETH_MACCR_ACS_Pos (20U)
6968#define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos)
6969#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
6970#define ETH_MACCR_WD_Pos (19U)
6971#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
6972#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
6973#define ETH_MACCR_JD_Pos (17U)
6974#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
6975#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
6976#define ETH_MACCR_JE_Pos (16U)
6977#define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos)
6978#define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
6979#define ETH_MACCR_FES_Pos (14U)
6980#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
6981#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
6982#define ETH_MACCR_DM_Pos (13U)
6983#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
6984#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
6985#define ETH_MACCR_LM_Pos (12U)
6986#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
6987#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
6988#define ETH_MACCR_ECRSFD_Pos (11U)
6989#define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos)
6990#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
6991#define ETH_MACCR_DO_Pos (10U)
6992#define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos)
6993#define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
6994#define ETH_MACCR_DCRS_Pos (9U)
6995#define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos)
6996#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
6997#define ETH_MACCR_DR_Pos (8U)
6998#define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos)
6999#define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
7000#define ETH_MACCR_BL_Pos (5U)
7001#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
7002#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
7003#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos)
7004#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos)
7005#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos)
7006#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos)
7007#define ETH_MACCR_DC_Pos (4U)
7008#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
7009#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
7010#define ETH_MACCR_PRELEN_Pos (2U)
7011#define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos)
7012#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
7013#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos)
7014#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos)
7015#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos)
7016#define ETH_MACCR_TE_Pos (1U)
7017#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
7018#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
7019#define ETH_MACCR_RE_Pos (0U)
7020#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
7021#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
7022
7023/* Bit definition for Ethernet MAC Extended Configuration Register register */
7024#define ETH_MACECR_EIPG_Pos (25U)
7025#define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos)
7026#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
7027#define ETH_MACECR_EIPGEN_Pos (24U)
7028#define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos)
7029#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
7030#define ETH_MACECR_USP_Pos (18U)
7031#define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos)
7032#define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
7033#define ETH_MACECR_SPEN_Pos (17U)
7034#define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos)
7035#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
7036#define ETH_MACECR_DCRCC_Pos (16U)
7037#define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos)
7038#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
7039#define ETH_MACECR_GPSL_Pos (0U)
7040#define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos)
7041#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
7042
7043/* Bit definition for Ethernet MAC Packet Filter Register */
7044#define ETH_MACPFR_RA_Pos (31U)
7045#define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos)
7046#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
7047#define ETH_MACPFR_DNTU_Pos (21U)
7048#define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos)
7049#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
7050#define ETH_MACPFR_IPFE_Pos (20U)
7051#define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos)
7052#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
7053#define ETH_MACPFR_VTFE_Pos (16U)
7054#define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos)
7055#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
7056#define ETH_MACPFR_HPF_Pos (10U)
7057#define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos)
7058#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
7059#define ETH_MACPFR_SAF_Pos (9U)
7060#define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos)
7061#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
7062#define ETH_MACPFR_SAIF_Pos (8U)
7063#define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos)
7064#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
7065#define ETH_MACPFR_PCF_Pos (6U)
7066#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos)
7067#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
7068#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
7069#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
7070#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos)
7071#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
7072#define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
7073#define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos)
7074#define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
7075#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
7076#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos)
7077#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
7078#define ETH_MACPFR_DBF_Pos (5U)
7079#define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos)
7080#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
7081#define ETH_MACPFR_PM_Pos (4U)
7082#define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos)
7083#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
7084#define ETH_MACPFR_DAIF_Pos (3U)
7085#define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos)
7086#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
7087#define ETH_MACPFR_HMC_Pos (2U)
7088#define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos)
7089#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
7090#define ETH_MACPFR_HUC_Pos (1U)
7091#define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos)
7092#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
7093#define ETH_MACPFR_PR_Pos (0U)
7094#define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos)
7095#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
7096
7097/* Bit definition for Ethernet MAC Watchdog Timeout Register */
7098#define ETH_MACWTR_PWE_Pos (8U)
7099#define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos)
7100#define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
7101#define ETH_MACWTR_WTO_Pos (0U)
7102#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos)
7103#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
7104#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
7105#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
7106#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
7107#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
7108#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
7109#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
7110#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
7111#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
7112#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
7113#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
7114#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
7115#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
7116#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
7117#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
7118#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
7119
7120/* Bit definition for Ethernet MAC Hash Table High Register */
7121#define ETH_MACHTHR_HTH_Pos (0U)
7122#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
7123#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
7124
7125/* Bit definition for Ethernet MAC Hash Table Low Register */
7126#define ETH_MACHTLR_HTL_Pos (0U)
7127#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
7128#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
7129
7130/* Bit definition for Ethernet MAC VLAN Tag Register */
7131#define ETH_MACVTR_EIVLRXS_Pos (31U)
7132#define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos)
7133#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
7134#define ETH_MACVTR_EIVLS_Pos (28U)
7135#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos)
7136#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
7137#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
7138#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
7139#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos)
7140#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
7141#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)
7142#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos)
7143#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
7144#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)
7145#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos)
7146#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
7147#define ETH_MACVTR_ERIVLT_Pos (27U)
7148#define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos)
7149#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
7150#define ETH_MACVTR_EDVLP_Pos (26U)
7151#define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos)
7152#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
7153#define ETH_MACVTR_VTHM_Pos (25U)
7154#define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos)
7155#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
7156#define ETH_MACVTR_EVLRXS_Pos (24U)
7157#define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos)
7158#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
7159#define ETH_MACVTR_EVLS_Pos (21U)
7160#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos)
7161#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
7162#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
7163#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
7164#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos)
7165#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
7166#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)
7167#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos)
7168#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
7169#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)
7170#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos)
7171#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
7172#define ETH_MACVTR_DOVLTC_Pos (20U)
7173#define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos)
7174#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
7175#define ETH_MACVTR_ERSVLM_Pos (19U)
7176#define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos)
7177#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
7178#define ETH_MACVTR_ESVL_Pos (18U)
7179#define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos)
7180#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
7181#define ETH_MACVTR_VTIM_Pos (17U)
7182#define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos)
7183#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
7184#define ETH_MACVTR_ETV_Pos (16U)
7185#define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos)
7186#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
7187#define ETH_MACVTR_VL_Pos (0U)
7188#define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos)
7189#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
7190#define ETH_MACVTR_VL_UP_Pos (13U)
7191#define ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos)
7192#define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */
7193#define ETH_MACVTR_VL_CFIDEI_Pos (12U)
7194#define ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos)
7195#define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7196#define ETH_MACVTR_VL_VID_Pos (0U)
7197#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos)
7198#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
7199
7200/* Bit definition for Ethernet MAC VLAN Hash Table Register */
7201#define ETH_MACVHTR_VLHT_Pos (0U)
7202#define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos)
7203#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
7204
7205/* Bit definition for Ethernet MAC VLAN Incl Register */
7206#define ETH_MACVIR_VLTI_Pos (20U)
7207#define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos)
7208#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
7209#define ETH_MACVIR_CSVL_Pos (19U)
7210#define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos)
7211#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
7212#define ETH_MACVIR_VLP_Pos (18U)
7213#define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos)
7214#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
7215#define ETH_MACVIR_VLC_Pos (16U)
7216#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos)
7217#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
7218#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
7219#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
7220#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos)
7221#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
7222#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
7223#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos)
7224#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
7225#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
7226#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos)
7227#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
7228#define ETH_MACVIR_VLT_Pos (0U)
7229#define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos)
7230#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
7231#define ETH_MACVIR_VLT_UP_Pos (13U)
7232#define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos)
7233#define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
7234#define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
7235#define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos)
7236#define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7237#define ETH_MACVIR_VLT_VID_Pos (0U)
7238#define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos)
7239#define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
7240
7241/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
7242#define ETH_MACIVIR_VLTI_Pos (20U)
7243#define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos)
7244#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
7245#define ETH_MACIVIR_CSVL_Pos (19U)
7246#define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos)
7247#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
7248#define ETH_MACIVIR_VLP_Pos (18U)
7249#define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos)
7250#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
7251#define ETH_MACIVIR_VLC_Pos (16U)
7252#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos)
7253#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
7254#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
7255#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
7256#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos)
7257#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
7258#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
7259#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos)
7260#define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
7261#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
7262#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos)
7263#define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
7264#define ETH_MACIVIR_VLT_Pos (0U)
7265#define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos)
7266#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
7267#define ETH_MACIVIR_VLT_UP_Pos (13U)
7268#define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos)
7269#define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
7270#define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
7271#define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos)
7272#define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7273#define ETH_MACIVIR_VLT_VID_Pos (0U)
7274#define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos)
7275#define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
7276
7277/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
7278#define ETH_MACTFCR_PT_Pos (16U)
7279#define ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos)
7280#define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */
7281#define ETH_MACTFCR_DZPQ_Pos (7U)
7282#define ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos)
7283#define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
7284#define ETH_MACTFCR_PLT_Pos (4U)
7285#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos)
7286#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
7287#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
7288#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
7289#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos)
7290#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
7291#define ETH_MACTFCR_PLT_MINUS36_Pos (5U)
7292#define ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos)
7293#define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
7294#define ETH_MACTFCR_PLT_MINUS144_Pos (4U)
7295#define ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos)
7296#define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
7297#define ETH_MACTFCR_PLT_MINUS256_Pos (6U)
7298#define ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos)
7299#define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
7300#define ETH_MACTFCR_PLT_MINUS512_Pos (4U)
7301#define ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos)
7302#define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
7303#define ETH_MACTFCR_TFE_Pos (1U)
7304#define ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos)
7305#define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
7306#define ETH_MACTFCR_FCB_Pos (0U)
7307#define ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos)
7308#define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
7309
7310/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
7311#define ETH_MACRFCR_UP_Pos (1U)
7312#define ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos)
7313#define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
7314#define ETH_MACRFCR_RFE_Pos (0U)
7315#define ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos)
7316#define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
7317
7318/* Bit definition for Ethernet MAC Interrupt Status Register */
7319#define ETH_MACISR_RXSTSIS_Pos (14U)
7320#define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos)
7321#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
7322#define ETH_MACISR_TXSTSIS_Pos (13U)
7323#define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos)
7324#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
7325#define ETH_MACISR_TSIS_Pos (12U)
7326#define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos)
7327#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
7328#define ETH_MACISR_MMCTXIS_Pos (10U)
7329#define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos)
7330#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
7331#define ETH_MACISR_MMCRXIS_Pos (9U)
7332#define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos)
7333#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
7334#define ETH_MACISR_MMCIS_Pos (8U)
7335#define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos)
7336#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
7337#define ETH_MACISR_LPIIS_Pos (5U)
7338#define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos)
7339#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
7340#define ETH_MACISR_PMTIS_Pos (4U)
7341#define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos)
7342#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
7343#define ETH_MACISR_PHYIS_Pos (3U)
7344#define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos)
7345#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
7346
7347/* Bit definition for Ethernet MAC Interrupt Enable Register */
7348#define ETH_MACIER_RXSTSIE_Pos (14U)
7349#define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos)
7350#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
7351#define ETH_MACIER_TXSTSIE_Pos (13U)
7352#define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos)
7353#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
7354#define ETH_MACIER_TSIE_Pos (12U)
7355#define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos)
7356#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
7357#define ETH_MACIER_LPIIE_Pos (5U)
7358#define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos)
7359#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
7360#define ETH_MACIER_PMTIE_Pos (4U)
7361#define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos)
7362#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
7363#define ETH_MACIER_PHYIE_Pos (3U)
7364#define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos)
7365#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
7366
7367/* Bit definition for Ethernet MAC Rx Tx Status Register */
7368#define ETH_MACRXTXSR_RWT_Pos (8U)
7369#define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos)
7370#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
7371#define ETH_MACRXTXSR_EXCOL_Pos (5U)
7372#define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos)
7373#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
7374#define ETH_MACRXTXSR_LCOL_Pos (4U)
7375#define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos)
7376#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
7377#define ETH_MACRXTXSR_EXDEF_Pos (3U)
7378#define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos)
7379#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
7380#define ETH_MACRXTXSR_LCARR_Pos (2U)
7381#define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos)
7382#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
7383#define ETH_MACRXTXSR_NCARR_Pos (1U)
7384#define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos)
7385#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
7386#define ETH_MACRXTXSR_TJT_Pos (0U)
7387#define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos)
7388#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
7389
7390/* Bit definition for Ethernet MAC PMT Control Status Register */
7391#define ETH_MACPCSR_RWKFILTRST_Pos (31U)
7392#define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos)
7393#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
7394#define ETH_MACPCSR_RWKPTR_Pos (24U)
7395#define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos)
7396#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
7397#define ETH_MACPCSR_RWKPFE_Pos (10U)
7398#define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos)
7399#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
7400#define ETH_MACPCSR_GLBLUCAST_Pos (9U)
7401#define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos)
7402#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
7403#define ETH_MACPCSR_RWKPRCVD_Pos (6U)
7404#define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos)
7405#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
7406#define ETH_MACPCSR_MGKPRCVD_Pos (5U)
7407#define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos)
7408#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
7409#define ETH_MACPCSR_RWKPKTEN_Pos (2U)
7410#define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos)
7411#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
7412#define ETH_MACPCSR_MGKPKTEN_Pos (1U)
7413#define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos)
7414#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
7415#define ETH_MACPCSR_PWRDWN_Pos (0U)
7416#define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos)
7417#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
7418
7419/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
7420#define ETH_MACRWUPFR_D_Pos (0U)
7421#define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos)
7422#define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
7423
7424/* Bit definition for Ethernet MAC LPI Control Status Register */
7425#define ETH_MACLCSR_LPITCSE_Pos (21U)
7426#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos)
7427#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
7428#define ETH_MACLCSR_LPITE_Pos (20U)
7429#define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos)
7430#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
7431#define ETH_MACLCSR_LPITXA_Pos (19U)
7432#define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos)
7433#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
7434#define ETH_MACLCSR_PLS_Pos (17U)
7435#define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos)
7436#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
7437#define ETH_MACLCSR_LPIEN_Pos (16U)
7438#define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos)
7439#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
7440#define ETH_MACLCSR_RLPIST_Pos (9U)
7441#define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos)
7442#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
7443#define ETH_MACLCSR_TLPIST_Pos (8U)
7444#define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos)
7445#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
7446#define ETH_MACLCSR_RLPIEX_Pos (3U)
7447#define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos)
7448#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
7449#define ETH_MACLCSR_RLPIEN_Pos (2U)
7450#define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos)
7451#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
7452#define ETH_MACLCSR_TLPIEX_Pos (1U)
7453#define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos)
7454#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
7455#define ETH_MACLCSR_TLPIEN_Pos (0U)
7456#define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos)
7457#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
7458
7459/* Bit definition for Ethernet MAC LPI Timers Control Register */
7460#define ETH_MACLTCR_LST_Pos (16U)
7461#define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos)
7462#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
7463#define ETH_MACLTCR_TWT_Pos (0U)
7464#define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos)
7465#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
7466
7467/* Bit definition for Ethernet MAC LPI Entry Timer Register */
7468#define ETH_MACLETR_LPIET_Pos (0U)
7469#define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos)
7470#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
7471
7472/* Bit definition for Ethernet MAC 1US Tic Counter Register */
7473#define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
7474#define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos)
7475#define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
7476
7477/* Bit definition for Ethernet MAC Version Register */
7478#define ETH_MACVR_USERVER_Pos (8U)
7479#define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos)
7480#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
7481#define ETH_MACVR_SNPSVER_Pos (0U)
7482#define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos)
7483#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
7484
7485/* Bit definition for Ethernet MAC Debug Register */
7486#define ETH_MACDR_TFCSTS_Pos (17U)
7487#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos)
7488#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
7489#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
7490#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
7491#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos)
7492#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
7493#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
7494#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos)
7495#define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
7496#define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
7497#define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos)
7498#define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
7499#define ETH_MACDR_TPESTS_Pos (16U)
7500#define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos)
7501#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
7502#define ETH_MACDR_RFCFCSTS_Pos (1U)
7503#define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos)
7504#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
7505#define ETH_MACDR_RPESTS_Pos (0U)
7506#define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos)
7507#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
7508
7509/* Bit definition for Ethernet MAC HW Feature0 Register */
7510#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
7511#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos)
7512#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
7513#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
7514#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
7515#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos)
7516#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
7517#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)
7518#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos)
7519#define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
7520#define ETH_MACHWF0R_SAVLANINS_Pos (27U)
7521#define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos)
7522#define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
7523#define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
7524#define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos)
7525#define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
7526#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
7527#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos)
7528#define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
7529#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
7530#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos)
7531#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
7532#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
7533#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos)
7534#define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
7535#define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
7536#define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos)
7537#define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
7538#define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
7539#define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos)
7540#define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
7541#define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
7542#define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos)
7543#define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
7544#define ETH_MACHWF0R_RXCOESEL_Pos (16U)
7545#define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos)
7546#define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
7547#define ETH_MACHWF0R_TXCOESEL_Pos (14U)
7548#define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos)
7549#define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
7550#define ETH_MACHWF0R_EEESEL_Pos (13U)
7551#define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos)
7552#define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
7553#define ETH_MACHWF0R_TSSEL_Pos (12U)
7554#define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos)
7555#define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
7556#define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
7557#define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos)
7558#define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
7559#define ETH_MACHWF0R_MMCSEL_Pos (8U)
7560#define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos)
7561#define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
7562#define ETH_MACHWF0R_MGKSEL_Pos (7U)
7563#define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos)
7564#define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
7565#define ETH_MACHWF0R_RWKSEL_Pos (6U)
7566#define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos)
7567#define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
7568#define ETH_MACHWF0R_SMASEL_Pos (5U)
7569#define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos)
7570#define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
7571#define ETH_MACHWF0R_VLHASH_Pos (4U)
7572#define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos)
7573#define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
7574#define ETH_MACHWF0R_PCSSEL_Pos (3U)
7575#define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos)
7576#define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
7577#define ETH_MACHWF0R_HDSEL_Pos (2U)
7578#define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos)
7579#define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
7580#define ETH_MACHWF0R_GMIISEL_Pos (1U)
7581#define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos)
7582#define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
7583#define ETH_MACHWF0R_MIISEL_Pos (0U)
7584#define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos)
7585#define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
7586
7587/* Bit definition for Ethernet MAC HW Feature1 Register */
7588#define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
7589#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos)
7590#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
7591#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
7592#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos)
7593#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
7594#define ETH_MACHWF1R_AVSEL_Pos (20U)
7595#define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos)
7596#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
7597#define ETH_MACHWF1R_DBGMEMA_Pos (19U)
7598#define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos)
7599#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
7600#define ETH_MACHWF1R_TSOEN_Pos (18U)
7601#define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos)
7602#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
7603#define ETH_MACHWF1R_SPHEN_Pos (17U)
7604#define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos)
7605#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
7606#define ETH_MACHWF1R_DCBEN_Pos (16U)
7607#define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos)
7608#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
7609#define ETH_MACHWF1R_ADDR64_Pos (14U)
7610#define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos)
7611#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
7612#define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos)
7613#define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos)
7614#define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos)
7615#define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
7616#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos)
7617#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
7618#define ETH_MACHWF1R_PTOEN_Pos (12U)
7619#define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos)
7620#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
7621#define ETH_MACHWF1R_OSTEN_Pos (11U)
7622#define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos)
7623#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
7624#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
7625#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos)
7626#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
7627#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
7628#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos)
7629#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
7630
7631/* Bit definition for Ethernet MAC HW Feature2 Register */
7632#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
7633#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos)
7634#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
7635#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
7636#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos)
7637#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
7638#define ETH_MACHWF2R_TXCHCNT_Pos (18U)
7639#define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos)
7640#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
7641#define ETH_MACHWF2R_RXCHCNT_Pos (13U)
7642#define ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos)
7643#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
7644#define ETH_MACHWF2R_TXQCNT_Pos (6U)
7645#define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos)
7646#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
7647#define ETH_MACHWF2R_RXQCNT_Pos (0U)
7648#define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos)
7649#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
7650
7651/* Bit definition for Ethernet MAC MDIO Address Register */
7652#define ETH_MACMDIOAR_PSE_Pos (27U)
7653#define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos)
7654#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
7655#define ETH_MACMDIOAR_BTB_Pos (26U)
7656#define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos)
7657#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
7658#define ETH_MACMDIOAR_PA_Pos (21U)
7659#define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos)
7660#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
7661#define ETH_MACMDIOAR_RDA_Pos (16U)
7662#define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos)
7663#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
7664#define ETH_MACMDIOAR_NTC_Pos (12U)
7665#define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos)
7666#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
7667#define ETH_MACMDIOAR_CR_Pos (8U)
7668#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos)
7669#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
7670#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
7671#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
7672#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos)
7673#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
7674#define ETH_MACMDIOAR_CR_DIV16_Pos (9U)
7675#define ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos)
7676#define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
7677#define ETH_MACMDIOAR_CR_DIV26_Pos (8U)
7678#define ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos)
7679#define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
7680#define ETH_MACMDIOAR_CR_DIV102_Pos (10U)
7681#define ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos)
7682#define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
7683#define ETH_MACMDIOAR_CR_DIV124_Pos (8U)
7684#define ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos)
7685#define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
7686#define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)
7687#define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos)
7688#define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
7689#define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)
7690#define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos)
7691#define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
7692#define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)
7693#define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos)
7694#define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
7695#define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)
7696#define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos)
7697#define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
7698#define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)
7699#define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos)
7700#define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
7701#define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)
7702#define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos)
7703#define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
7704#define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)
7705#define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos)
7706#define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
7707#define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)
7708#define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos)
7709#define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
7710#define ETH_MACMDIOAR_SKAP_Pos (4U)
7711#define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos)
7712#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
7713#define ETH_MACMDIOAR_MOC_Pos (2U)
7714#define ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos)
7715#define ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */
7716#define ETH_MACMDIOAR_MOC_WR_Pos (2U)
7717#define ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos)
7718#define ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */
7719#define ETH_MACMDIOAR_MOC_PRDIA_Pos (3U)
7720#define ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos)
7721#define ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
7722#define ETH_MACMDIOAR_MOC_RD_Pos (2U)
7723#define ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos)
7724#define ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */
7725#define ETH_MACMDIOAR_C45E_Pos (1U)
7726#define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos)
7727#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
7728#define ETH_MACMDIOAR_MB_Pos (0U)
7729#define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos)
7730#define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */
7731
7732/* Bit definition for Ethernet MAC MDIO Data Register */
7733#define ETH_MACMDIODR_RA_Pos (16U)
7734#define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos)
7735#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */
7736#define ETH_MACMDIODR_MD_Pos (0U)
7737#define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos)
7738#define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */
7739
7740/* Bit definition for Ethernet ARP Address Register */
7741#define ETH_MACARPAR_ARPPA_Pos (0U)
7742#define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos)
7743#define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */
7744
7745/* Bit definition for Ethernet MAC Address 0 High Register */
7746#define ETH_MACA0HR_AE_Pos (31U)
7747#define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos)
7748#define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/
7749#define ETH_MACA0HR_ADDRHI_Pos (0U)
7750#define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos)
7751#define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/
7752
7753/* Bit definition for Ethernet MAC Address 0 Low Register */
7754#define ETH_MACA0LR_ADDRLO_Pos (0U)
7755#define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos)
7756#define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/
7757
7758/* Bit definition for Ethernet MAC Address 1 High Register */
7759#define ETH_MACA1HR_AE_Pos (31U)
7760#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
7761#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address Enable*/
7762#define ETH_MACA1HR_SA_Pos (30U)
7763#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
7764#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source Address */
7765#define ETH_MACA1HR_MBC_Pos (24U)
7766#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
7767#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
7768#define ETH_MACA1HR_ADDRHI_Pos (0U)
7769#define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos)
7770#define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/
7771
7772/* Bit definition for Ethernet MAC Address 1 Low Register */
7773#define ETH_MACA1LR_ADDRLO_Pos (0U)
7774#define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos)
7775#define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/
7776
7777/* Bit definition for Ethernet MAC Address 2 High Register */
7778#define ETH_MACA2HR_AE_Pos (31U)
7779#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
7780#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address Enable*/
7781#define ETH_MACA2HR_SA_Pos (30U)
7782#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
7783#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source Address */
7784#define ETH_MACA2HR_MBC_Pos (24U)
7785#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
7786#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
7787#define ETH_MACA2HR_ADDRHI_Pos (0U)
7788#define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos)
7789#define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/
7790
7791/* Bit definition for Ethernet MAC Address 2 Low Register */
7792#define ETH_MACA2LR_ADDRLO_Pos (0U)
7793#define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos)
7794#define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/
7795
7796/* Bit definition for Ethernet MAC Address 3 High Register */
7797#define ETH_MACA3HR_AE_Pos (31U)
7798#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
7799#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address Enable*/
7800#define ETH_MACA3HR_SA_Pos (30U)
7801#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
7802#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source Address */
7803#define ETH_MACA3HR_MBC_Pos (24U)
7804#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
7805#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
7806#define ETH_MACA3HR_ADDRHI_Pos (0U)
7807#define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos)
7808#define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/
7809
7810/* Bit definition for Ethernet MAC Address 3 Low Register */
7811#define ETH_MACA3LR_ADDRLO_Pos (0U)
7812#define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos)
7813#define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/
7814
7815/* Bit definition for Ethernet MAC Address High Register */
7816#define ETH_MACAHR_AE_Pos (31U)
7817#define ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos)
7818#define ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */
7819#define ETH_MACAHR_SA_Pos (30U)
7820#define ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos)
7821#define ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */
7822#define ETH_MACAHR_MBC_Pos (24U)
7823#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos)
7824#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7825#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
7826#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
7827#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
7828#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
7829#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
7830#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
7831#define ETH_MACAHR_MACAH_Pos (0U)
7832#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos)
7833#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
7834
7835/* Bit definition for Ethernet MAC Address Low Register */
7836#define ETH_MACALR_MACAL_Pos (0U)
7837#define ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos)
7838#define ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */
7839
7840/* Bit definition for Ethernet MMC Control Register */
7841#define ETH_MMCCR_UCDBC_Pos (8U)
7842#define ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos)
7843#define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */
7844#define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
7845#define ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos)
7846#define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */
7847#define ETH_MMCCR_CNTPRST_Pos (4U)
7848#define ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos)
7849#define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */
7850#define ETH_MMCCR_CNTFREEZ_Pos (3U)
7851#define ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos)
7852#define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */
7853#define ETH_MMCCR_RSTONRD_Pos (2U)
7854#define ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos)
7855#define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */
7856#define ETH_MMCCR_CNTSTOPRO_Pos (1U)
7857#define ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos)
7858#define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */
7859#define ETH_MMCCR_CNTRST_Pos (0U)
7860#define ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos)
7861#define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */
7862
7863/* Bit definition for Ethernet MMC Rx Interrupt Register */
7864#define ETH_MMCRIR_RXLPITRCIS_Pos (27U)
7865#define ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos)
7866#define ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */
7867#define ETH_MMCRIR_RXLPIUSCIS_Pos (26U)
7868#define ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos)
7869#define ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */
7870#define ETH_MMCRIR_RXUCGPIS_Pos (17U)
7871#define ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos)
7872#define ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */
7873#define ETH_MMCRIR_RXALGNERPIS_Pos (6U)
7874#define ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos)
7875#define ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */
7876#define ETH_MMCRIR_RXCRCERPIS_Pos (5U)
7877#define ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos)
7878#define ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */
7879
7880/* Bit definition for Ethernet MMC Tx Interrupt Register */
7881#define ETH_MMCTIR_TXLPITRCIS_Pos (27U)
7882#define ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos)
7883#define ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */
7884#define ETH_MMCTIR_TXLPIUSCIS_Pos (26U)
7885#define ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos)
7886#define ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */
7887#define ETH_MMCTIR_TXGPKTIS_Pos (21U)
7888#define ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos)
7889#define ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */
7890#define ETH_MMCTIR_TXMCOLGPIS_Pos (15U)
7891#define ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos)
7892#define ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
7893#define ETH_MMCTIR_TXSCOLGPIS_Pos (14U)
7894#define ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos)
7895#define ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
7896
7897/* Bit definition for Ethernet MMC Rx interrupt Mask register */
7898#define ETH_MMCRIMR_RXLPITRCIM_Pos (27U)
7899#define ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos)
7900#define ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */
7901#define ETH_MMCRIMR_RXLPIUSCIM_Pos (26U)
7902#define ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos)
7903#define ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */
7904#define ETH_MMCRIMR_RXUCGPIM_Pos (17U)
7905#define ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos)
7906#define ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
7907#define ETH_MMCRIMR_RXALGNERPIM_Pos (6U)
7908#define ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos)
7909#define ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
7910#define ETH_MMCRIMR_RXCRCERPIM_Pos (5U)
7911#define ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos)
7912#define ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */
7913
7914/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
7915#define ETH_MMCTIMR_TXLPITRCIM_Pos (27U)
7916#define ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos)
7917#define ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/
7918#define ETH_MMCTIMR_TXLPIUSCIM_Pos (26U)
7919#define ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos)
7920#define ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/
7921#define ETH_MMCTIMR_TXGPKTIM_Pos (21U)
7922#define ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos)
7923#define ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/
7924#define ETH_MMCTIMR_TXMCOLGPIM_Pos (15U)
7925#define ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos)
7926#define ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
7927#define ETH_MMCTIMR_TXSCOLGPIM_Pos (14U)
7928#define ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos)
7929#define ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
7930
7931/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
7932#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U)
7933#define ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos)
7934#define ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
7935
7936/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
7937#define ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U)
7938#define ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos)
7939#define ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
7940
7941/* Bit definition for Ethernet MMC Tx Packet Count Good Register */
7942#define ETH_MMCTPCGR_TXPKTG_Pos (0U)
7943#define ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos)
7944#define ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
7945
7946/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
7947#define ETH_MMCRCRCEPR_RXCRCERR_Pos (0U)
7948#define ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos)
7949#define ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
7950
7951/* Bit definition for Ethernet MMC Rx alignment error packets register */
7952#define ETH_MMCRAEPR_RXALGNERR_Pos (0U)
7953#define ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos)
7954#define ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
7955
7956/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
7957#define ETH_MMCRUPGR_RXUCASTG_Pos (0U)
7958#define ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos)
7959#define ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
7960
7961/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
7962#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U)
7963#define ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos)
7964#define ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
7965
7966/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
7967#define ETH_MMCTLPITCR_TXLPITRC_Pos (0U)
7968#define ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos)
7969#define ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
7970
7971/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
7972#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U)
7973#define ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos)
7974#define ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
7975
7976/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
7977#define ETH_MMCRLPITCR_RXLPITRC_Pos (0U)
7978#define ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos)
7979#define ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
7980
7981/* Bit definition for Ethernet MAC L3 L4 Control Register */
7982#define ETH_MACL3L4CR_L4DPIM_Pos (21U)
7983#define ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos)
7984#define ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
7985#define ETH_MACL3L4CR_L4DPM_Pos (20U)
7986#define ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos)
7987#define ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */
7988#define ETH_MACL3L4CR_L4SPIM_Pos (19U)
7989#define ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos)
7990#define ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
7991#define ETH_MACL3L4CR_L4SPM_Pos (18U)
7992#define ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos)
7993#define ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */
7994#define ETH_MACL3L4CR_L4PEN_Pos (16U)
7995#define ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos)
7996#define ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */
7997#define ETH_MACL3L4CR_L3HDBM_Pos (11U)
7998#define ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos)
7999#define ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
8000#define ETH_MACL3L4CR_L3HSBM_Pos (6U)
8001#define ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos)
8002#define ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
8003#define ETH_MACL3L4CR_L3DAIM_Pos (5U)
8004#define ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos)
8005#define ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
8006#define ETH_MACL3L4CR_L3DAM_Pos (4U)
8007#define ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos)
8008#define ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */
8009#define ETH_MACL3L4CR_L3SAIM_Pos (3U)
8010#define ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos)
8011#define ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
8012#define ETH_MACL3L4CR_L3SAM_Pos (2U)
8013#define ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos)
8014#define ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/
8015#define ETH_MACL3L4CR_L3PEN_Pos (0U)
8016#define ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos)
8017#define ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */
8018
8019/* Bit definition for Ethernet MAC L4 Address Register */
8020#define ETH_MACL4AR_L4DP_Pos (16U)
8021#define ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos)
8022#define ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */
8023#define ETH_MACL4AR_L4SP_Pos (0U)
8024#define ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos)
8025#define ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */
8026
8027/* Bit definition for Ethernet MAC L3 Address0 Register */
8028#define ETH_MACL3A0R_L3A0_Pos (0U)
8029#define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos)
8030#define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
8031
8032/* Bit definition for Ethernet MAC L4 Address1 Register */
8033#define ETH_MACL3A1R_L3A1_Pos (0U)
8034#define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos)
8035#define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
8036
8037/* Bit definition for Ethernet MAC L4 Address2 Register */
8038#define ETH_MACL3A2R_L3A2_Pos (0U)
8039#define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos)
8040#define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
8041
8042/* Bit definition for Ethernet MAC L4 Address3 Register */
8043#define ETH_MACL3A3R_L3A3_Pos (0U)
8044#define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos)
8045#define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
8046
8047/* Bit definition for Ethernet MAC Timestamp Control Register */
8048#define ETH_MACTSCR_TXTSSTSM_Pos (24U)
8049#define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos)
8050#define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */
8051#define ETH_MACTSCR_CSC_Pos (19U)
8052#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos)
8053#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
8054#define ETH_MACTSCR_TSENMACADDR_Pos (18U)
8055#define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos)
8056#define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */
8057#define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
8058#define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos)
8059#define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */
8060#define ETH_MACTSCR_TSMSTRENA_Pos (15U)
8061#define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos)
8062#define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */
8063#define ETH_MACTSCR_TSEVNTENA_Pos (14U)
8064#define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos)
8065#define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */
8066#define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
8067#define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos)
8068#define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
8069#define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
8070#define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos)
8071#define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
8072#define ETH_MACTSCR_TSIPENA_Pos (11U)
8073#define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos)
8074#define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */
8075#define ETH_MACTSCR_TSVER2ENA_Pos (10U)
8076#define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos)
8077#define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */
8078#define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
8079#define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos)
8080#define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */
8081#define ETH_MACTSCR_TSENALL_Pos (8U)
8082#define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos)
8083#define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */
8084#define ETH_MACTSCR_TSADDREG_Pos (5U)
8085#define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos)
8086#define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */
8087#define ETH_MACTSCR_TSUPDT_Pos (3U)
8088#define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos)
8089#define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */
8090#define ETH_MACTSCR_TSINIT_Pos (2U)
8091#define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos)
8092#define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */
8093#define ETH_MACTSCR_TSCFUPDT_Pos (1U)
8094#define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos)
8095#define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/
8096#define ETH_MACTSCR_TSENA_Pos (0U)
8097#define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos)
8098#define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */
8099
8100/* Bit definition for Ethernet MAC Sub-second Increment Register */
8101#define ETH_MACMACSSIR_SSINC_Pos (16U)
8102#define ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos)
8103#define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */
8104#define ETH_MACMACSSIR_SNSINC_Pos (8U)
8105#define ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos)
8106#define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */
8107
8108/* Bit definition for Ethernet MAC System Time Seconds Register */
8109#define ETH_MACSTSR_TSS_Pos (0U)
8110#define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos)
8111#define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */
8112
8113/* Bit definition for Ethernet MAC System Time Nanoseconds Register */
8114#define ETH_MACSTNR_TSSS_Pos (0U)
8115#define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos)
8116#define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */
8117
8118/* Bit definition for Ethernet MAC System Time Seconds Update Register */
8119#define ETH_MACSTSUR_TSS_Pos (0U)
8120#define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos)
8121#define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */
8122
8123/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
8124#define ETH_MACSTNUR_ADDSUB_Pos (31U)
8125#define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos)
8126#define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */
8127#define ETH_MACSTNUR_TSSS_Pos (0U)
8128#define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos)
8129#define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */
8130
8131/* Bit definition for Ethernet MAC Timestamp Addend Register */
8132#define ETH_MACTSAR_TSAR_Pos (0U)
8133#define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos)
8134#define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */
8135
8136/* Bit definition for Ethernet MAC Timestamp Status Register */
8137#define ETH_MACTSSR_ATSNS_Pos (25U)
8138#define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos)
8139#define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */
8140#define ETH_MACTSSR_ATSSTM_Pos (24U)
8141#define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos)
8142#define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */
8143#define ETH_MACTSSR_ATSSTN_Pos (16U)
8144#define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos)
8145#define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */
8146#define ETH_MACTSSR_TXTSSIS_Pos (15U)
8147#define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos)
8148#define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */
8149#define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
8150#define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos)
8151#define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */
8152#define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
8153#define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos)
8154#define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/
8155#define ETH_MACTSSR_TSTARGT0_Pos (1U)
8156#define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos)
8157#define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */
8158#define ETH_MACTSSR_TSSOVF_Pos (0U)
8159#define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos)
8160#define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */
8161
8162/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
8163#define ETH_MACTTSSNR_TXTSSMIS_Pos (31U)
8164#define ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos)
8165#define ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */
8166#define ETH_MACTTSSNR_TXTSSLO_Pos (0U)
8167#define ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos)
8168#define ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */
8169
8170/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
8171#define ETH_MACTTSSSR_TXTSSHI_Pos (0U)
8172#define ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos)
8173#define ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */
8174
8175/* Bit definition for Ethernet MAC Auxiliary Control Register*/
8176#define ETH_MACACR_ATSEN3_Pos (7U)
8177#define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos)
8178#define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */
8179#define ETH_MACACR_ATSEN2_Pos (6U)
8180#define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos)
8181#define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */
8182#define ETH_MACACR_ATSEN1_Pos (5U)
8183#define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos)
8184#define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */
8185#define ETH_MACACR_ATSEN0_Pos (4U)
8186#define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos)
8187#define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */
8188#define ETH_MACACR_ATSFC_Pos (0U)
8189#define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos)
8190#define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */
8191
8192/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
8193#define ETH_MACATSNR_AUXTSLO_Pos (0U)
8194#define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos)
8195#define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */
8196
8197/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
8198#define ETH_MACATSSR_AUXTSHI_Pos (0U)
8199#define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos)
8200#define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */
8201
8202/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
8203#define ETH_MACTSIACR_OSTIAC_Pos (0U)
8204#define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos)
8205#define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */
8206
8207/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
8208#define ETH_MACTSEACR_OSTEAC_Pos (0U)
8209#define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos)
8210#define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */
8211
8212/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
8213#define ETH_MACTSICNR_TSIC_Pos (0U)
8214#define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos)
8215#define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */
8216
8217/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
8218#define ETH_MACTSECNR_TSEC_Pos (0U)
8219#define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos)
8220#define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */
8221
8222/* Bit definition for Ethernet MAC PPS Control Register */
8223#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
8224#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos)
8225#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */
8226#define ETH_MACPPSCR_PPSEN0_Pos (4U)
8227#define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos)
8228#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */
8229#define ETH_MACPPSCR_PPSCTRL_Pos (0U)
8230#define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos)
8231#define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */
8232
8233/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
8234#define ETH_MACPPSTTSR_TSTRH0_Pos (0U)
8235#define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos)
8236#define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */
8237
8238/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
8239#define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)
8240#define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos)
8241#define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */
8242#define ETH_MACPPSTTNR_TTSL0_Pos (0U)
8243#define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos)
8244#define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */
8245
8246/* Bit definition for Ethernet MAC PPS Interval Register */
8247#define ETH_MACPPSIR_PPSINT0_Pos (0U)
8248#define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos)
8249#define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */
8250
8251/* Bit definition for Ethernet MAC PPS Width Register */
8252#define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)
8253#define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos)
8254#define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */
8255
8256/* Bit definition for Ethernet MAC PTP Offload Control Register */
8257#define ETH_MACPOCR_DN_Pos (8U)
8258#define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos)
8259#define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */
8260#define ETH_MACPOCR_DRRDIS_Pos (6U)
8261#define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos)
8262#define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */
8263#define ETH_MACPOCR_APDREQTRIG_Pos (5U)
8264#define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos)
8265#define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */
8266#define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
8267#define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos)
8268#define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */
8269#define ETH_MACPOCR_APDREQEN_Pos (2U)
8270#define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos)
8271#define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */
8272#define ETH_MACPOCR_ASYNCEN_Pos (1U)
8273#define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos)
8274#define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */
8275#define ETH_MACPOCR_PTOEN_Pos (0U)
8276#define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos)
8277#define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */
8278
8279/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
8280#define ETH_MACSPI0R_SPI0_Pos (0U)
8281#define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos)
8282#define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */
8283
8284/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
8285#define ETH_MACSPI1R_SPI1_Pos (0U)
8286#define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos)
8287#define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */
8288
8289/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
8290#define ETH_MACSPI2R_SPI2_Pos (0U)
8291#define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos)
8292#define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */
8293
8294/* Bit definition for Ethernet MAC Log Message Interval Register */
8295#define ETH_MACLMIR_LMPDRI_Pos (24U)
8296#define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos)
8297#define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */
8298#define ETH_MACLMIR_DRSYNCR_Pos (8U)
8299#define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos)
8300#define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */
8301#define ETH_MACLMIR_LSI_Pos (0U)
8302#define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos)
8303#define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */
8304
8305/* Bit definition for Ethernet MTL Operation Mode Register */
8306#define ETH_MTLOMR_CNTCLR_Pos (9U)
8307#define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos)
8308#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
8309#define ETH_MTLOMR_CNTPRST_Pos (8U)
8310#define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos)
8311#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
8312#define ETH_MTLOMR_DTXSTS_Pos (1U)
8313#define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos)
8314#define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */
8315
8316/* Bit definition for Ethernet MTL Interrupt Status Register */
8317#define ETH_MTLISR_MACIS_Pos (16U)
8318#define ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos)
8319#define ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */
8320#define ETH_MTLISR_QIS_Pos (0U)
8321#define ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos)
8322#define ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */
8323
8324/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
8325#define ETH_MTLTQOMR_TTC_Pos (4U)
8326#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos)
8327#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
8328#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
8329#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
8330#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
8331#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
8332#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
8333#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
8334#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
8335#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
8336#define ETH_MTLTQOMR_TSF_Pos (1U)
8337#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos)
8338#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
8339#define ETH_MTLTQOMR_FTQ_Pos (0U)
8340#define ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos)
8341#define ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */
8342
8343/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
8344#define ETH_MTLTQUR_UFCNTOVF_Pos (11U)
8345#define ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos)
8346#define ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
8347#define ETH_MTLTQUR_UFPKTCNT_Pos (0U)
8348#define ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos)
8349#define ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
8350
8351/* Bit definition for Ethernet MTL Tx Queue Debug Register */
8352#define ETH_MTLTQDR_STXSTSF_Pos (20U)
8353#define ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos)
8354#define ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
8355#define ETH_MTLTQDR_PTXQ_Pos (16U)
8356#define ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos)
8357#define ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
8358#define ETH_MTLTQDR_TXSTSFSTS_Pos (5U)
8359#define ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos)
8360#define ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
8361#define ETH_MTLTQDR_TXQSTS_Pos (4U)
8362#define ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos)
8363#define ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
8364#define ETH_MTLTQDR_TWCSTS_Pos (3U)
8365#define ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos)
8366#define ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
8367#define ETH_MTLTQDR_TRCSTS_Pos (1U)
8368#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos)
8369#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
8370#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
8371#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
8372#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
8373#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
8374#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
8375#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos)
8376#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
8377
8378/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
8379#define ETH_MTLQICSR_RXOIE_Pos (24U)
8380#define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos)
8381#define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
8382#define ETH_MTLQICSR_RXOVFIS_Pos (16U)
8383#define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos)
8384#define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
8385#define ETH_MTLQICSR_TXUIE_Pos (8U)
8386#define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos)
8387#define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
8388#define ETH_MTLQICSR_TXUNFIS_Pos (0U)
8389#define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos)
8390#define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
8391
8392/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
8393#define ETH_MTLRQOMR_RQS_Pos (20U)
8394#define ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos)
8395#define ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
8396#define ETH_MTLRQOMR_RFD_Pos (14U)
8397#define ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos)
8398#define ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
8399#define ETH_MTLRQOMR_RFA_Pos (8U)
8400#define ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos)
8401#define ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
8402#define ETH_MTLRQOMR_EHFC_Pos (7U)
8403#define ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos)
8404#define ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
8405#define ETH_MTLRQOMR_DISTCPEF_Pos (6U)
8406#define ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos)
8407#define ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
8408#define ETH_MTLRQOMR_RSF_Pos (5U)
8409#define ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos)
8410#define ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */
8411#define ETH_MTLRQOMR_FEP_Pos (4U)
8412#define ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos)
8413#define ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */
8414#define ETH_MTLRQOMR_FUP_Pos (3U)
8415#define ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos)
8416#define ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */
8417#define ETH_MTLRQOMR_RTC_Pos (0U)
8418#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos)
8419#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
8420#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
8421#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
8422#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
8423#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
8424
8425/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
8426#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
8427#define ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos)
8428#define ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
8429#define ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U)
8430#define ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos)
8431#define ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
8432#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U)
8433#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos)
8434#define ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
8435#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U)
8436#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos)
8437#define ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
8438
8439/* Bit definition for Ethernet MTL Rx Queue Debug Register */
8440#define ETH_MTLRQDR_PRXQ_Pos (16U)
8441#define ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos)
8442#define ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */
8443#define ETH_MTLRQDR_RXQSTS_Pos (4U)
8444#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos)
8445#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
8446#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
8447#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
8448#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos)
8449#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
8450#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)
8451#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos)
8452#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
8453#define ETH_MTLRQDR_RXQSTS_FULL_Pos (4U)
8454#define ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos)
8455#define ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
8456#define ETH_MTLRQDR_RRCSTS_Pos (1U)
8457#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos)
8458#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
8459#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
8460#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
8461#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos)
8462#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
8463#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U)
8464#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos)
8465#define ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
8466#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U)
8467#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos)
8468#define ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
8469#define ETH_MTLRQDR_RWCSTS_Pos (0U)
8470#define ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos)
8471#define ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
8472
8473/* Bit definition for Ethernet MTL Rx Queue Control Register */
8474#define ETH_MTLRQCR_RQPA_Pos (3U)
8475#define ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos)
8476#define ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */
8477#define ETH_MTLRQCR_RQW_Pos (0U)
8478#define ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos)
8479#define ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */
8480
8481/* Bit definition for Ethernet DMA Mode Register */
8482#define ETH_DMAMR_INTM_Pos (16U)
8483#define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos)
8484#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
8485#define ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos)
8486#define ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos)
8487#define ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos)
8488#define ETH_DMAMR_PR_Pos (12U)
8489#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos)
8490#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
8491#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
8492#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
8493#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
8494#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
8495#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
8496#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
8497#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
8498#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
8499#define ETH_DMAMR_TXPR_Pos (11U)
8500#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos)
8501#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
8502#define ETH_DMAMR_DA_Pos (1U)
8503#define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos)
8504#define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */
8505#define ETH_DMAMR_SWR_Pos (0U)
8506#define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos)
8507#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */
8508
8509/* Bit definition for Ethernet DMA SysBus Mode Register */
8510#define ETH_DMASBMR_RB_Pos (15U)
8511#define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos)
8512#define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */
8513#define ETH_DMASBMR_MB_Pos (14U)
8514#define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos)
8515#define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */
8516#define ETH_DMASBMR_AAL_Pos (12U)
8517#define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos)
8518#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
8519#define ETH_DMASBMR_FB_Pos (0U)
8520#define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos)
8521#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
8522
8523/* Bit definition for Ethernet DMA Interrupt Status Register */
8524#define ETH_DMAISR_MACIS_Pos (17U)
8525#define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos)
8526#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
8527#define ETH_DMAISR_MTLIS_Pos (16U)
8528#define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos)
8529#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
8530#define ETH_DMAISR_DMACIS_Pos (0U)
8531#define ETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos)
8532#define ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */
8533
8534/* Bit definition for Ethernet DMA Debug Status Register */
8535#define ETH_DMADSR_TPS_Pos (12U)
8536#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos)
8537#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
8538#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
8539#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
8540#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos)
8541#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
8542#define ETH_DMADSR_TPS_WAITING_Pos (13U)
8543#define ETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos)
8544#define ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
8545#define ETH_DMADSR_TPS_READING_Pos (12U)
8546#define ETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos)
8547#define ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
8548#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U)
8549#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos)
8550#define ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8551#define ETH_DMADSR_TPS_SUSPENDED_Pos (13U)
8552#define ETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos)
8553#define ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
8554#define ETH_DMADSR_TPS_CLOSING_Pos (12U)
8555#define ETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos)
8556#define ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
8557#define ETH_DMADSR_RPS_Pos (8U)
8558#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos)
8559#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
8560#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
8561#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
8562#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos)
8563#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
8564#define ETH_DMADSR_RPS_WAITING_Pos (12U)
8565#define ETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos)
8566#define ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
8567#define ETH_DMADSR_RPS_SUSPENDED_Pos (14U)
8568#define ETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos)
8569#define ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
8570#define ETH_DMADSR_RPS_CLOSING_Pos (12U)
8571#define ETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos)
8572#define ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
8573#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U)
8574#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos)
8575#define ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8576#define ETH_DMADSR_RPS_TRANSFERRING_Pos (12U)
8577#define ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos)
8578#define ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
8579
8580/* Bit definition for Ethernet DMA Channel Control Register */
8581#define ETH_DMACCR_DSL_Pos (18U)
8582#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos)
8583#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
8584#define ETH_DMACCR_DSL_0BIT (0U)
8585#define ETH_DMACCR_DSL_32BIT (0x00040000U)
8586#define ETH_DMACCR_DSL_64BIT (0x00080000U)
8587#define ETH_DMACCR_DSL_128BIT (0x00100000U)
8588#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
8589#define ETH_DMACCR_MSS_Pos (0U)
8590#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos)
8591#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
8592
8593/* Bit definition for Ethernet DMA Channel Tx Control Register */
8594#define ETH_DMACTCR_TPBL_Pos (16U)
8595#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos)
8596#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
8597#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
8598#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
8599#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
8600#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
8601#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
8602#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
8603#define ETH_DMACTCR_TSE_Pos (12U)
8604#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos)
8605#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
8606#define ETH_DMACTCR_OSP_Pos (4U)
8607#define ETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos)
8608#define ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */
8609#define ETH_DMACTCR_ST_Pos (0U)
8610#define ETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos)
8611#define ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */
8612
8613/* Bit definition for Ethernet DMA Channel Rx Control Register */
8614#define ETH_DMACRCR_RPF_Pos (31U)
8615#define ETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos)
8616#define ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */
8617#define ETH_DMACRCR_RPBL_Pos (16U)
8618#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos)
8619#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
8620#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
8621#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
8622#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
8623#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
8624#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
8625#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
8626#define ETH_DMACRCR_RBSZ_Pos (1U)
8627#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos)
8628#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
8629#define ETH_DMACRCR_SR_Pos (0U)
8630#define ETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos)
8631#define ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */
8632
8633/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
8634#define ETH_DMACTDLAR_TDESLA_Pos (2U)
8635#define ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos)
8636#define ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
8637
8638/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
8639#define ETH_DMACRDLAR_RDESLA_Pos (2U)
8640#define ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos)
8641#define ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
8642
8643/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
8644#define ETH_DMACTDTPR_TDT_Pos (2U)
8645#define ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos)
8646#define ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
8647
8648/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
8649#define ETH_DMACRDTPR_RDT_Pos (2U)
8650#define ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos)
8651#define ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */
8652
8653/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
8654#define ETH_DMACTDRLR_TDRL_Pos (0U)
8655#define ETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos)
8656#define ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
8657
8658/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
8659#define ETH_DMACRDRLR_RDRL_Pos (0U)
8660#define ETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos)
8661#define ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */
8662
8663/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
8664#define ETH_DMACIER_NIE_Pos (15U)
8665#define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos)
8666#define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */
8667#define ETH_DMACIER_AIE_Pos (14U)
8668#define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos)
8669#define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
8670#define ETH_DMACIER_CDEE_Pos (13U)
8671#define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos)
8672#define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */
8673#define ETH_DMACIER_FBEE_Pos (12U)
8674#define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos)
8675#define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */
8676#define ETH_DMACIER_ERIE_Pos (11U)
8677#define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos)
8678#define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */
8679#define ETH_DMACIER_ETIE_Pos (10U)
8680#define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos)
8681#define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */
8682#define ETH_DMACIER_RWTE_Pos (9U)
8683#define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos)
8684#define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
8685#define ETH_DMACIER_RSE_Pos (8U)
8686#define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos)
8687#define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */
8688#define ETH_DMACIER_RBUE_Pos (7U)
8689#define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos)
8690#define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
8691#define ETH_DMACIER_RIE_Pos (6U)
8692#define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos)
8693#define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */
8694#define ETH_DMACIER_TBUE_Pos (2U)
8695#define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos)
8696#define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
8697#define ETH_DMACIER_TXSE_Pos (1U)
8698#define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos)
8699#define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */
8700#define ETH_DMACIER_TIE_Pos (0U)
8701#define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos)
8702#define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */
8703
8704/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
8705#define ETH_DMACRIWTR_RWT_Pos (0U)
8706#define ETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos)
8707#define ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
8708
8709/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
8710#define ETH_DMACCATDR_CURTDESAPTR_Pos (0U)
8711#define ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos)
8712#define ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
8713
8714/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
8715#define ETH_DMACCARDR_CURRDESAPTR_Pos (0U)
8716#define ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos)
8717#define ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
8718
8719/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
8720#define ETH_DMACCATBR_CURTBUFAPTR_Pos (0U)
8721#define ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos)
8722#define ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
8723
8724/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
8725#define ETH_DMACCARBR_CURRBUFAPTR_Pos (0U)
8726#define ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos)
8727#define ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
8728
8729/* Bit definition for Ethernet DMA Channel Status Register */
8730#define ETH_DMACSR_REB_Pos (19U)
8731#define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos)
8732#define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */
8733#define ETH_DMACSR_TEB_Pos (16U)
8734#define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos)
8735#define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */
8736#define ETH_DMACSR_NIS_Pos (15U)
8737#define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos)
8738#define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */
8739#define ETH_DMACSR_AIS_Pos (14U)
8740#define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos)
8741#define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */
8742#define ETH_DMACSR_CDE_Pos (13U)
8743#define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos)
8744#define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */
8745#define ETH_DMACSR_FBE_Pos (12U)
8746#define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos)
8747#define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */
8748#define ETH_DMACSR_ERI_Pos (11U)
8749#define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos)
8750#define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */
8751#define ETH_DMACSR_ETI_Pos (10U)
8752#define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos)
8753#define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */
8754#define ETH_DMACSR_RWT_Pos (9U)
8755#define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos)
8756#define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */
8757#define ETH_DMACSR_RPS_Pos (8U)
8758#define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos)
8759#define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */
8760#define ETH_DMACSR_RBU_Pos (7U)
8761#define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos)
8762#define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */
8763#define ETH_DMACSR_RI_Pos (6U)
8764#define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos)
8765#define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */
8766#define ETH_DMACSR_TBU_Pos (2U)
8767#define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos)
8768#define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */
8769#define ETH_DMACSR_TPS_Pos (1U)
8770#define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos)
8771#define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */
8772#define ETH_DMACSR_TI_Pos (0U)
8773#define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos)
8774#define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */
8775
8776/* Bit definition for Ethernet DMA Channel missed frame count register */
8777#define ETH_DMACMFCR_MFCO_Pos (15U)
8778#define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos)
8779#define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
8780#define ETH_DMACMFCR_MFC_Pos (0U)
8781#define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos)
8782#define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
8783
8784/******************************************************************************/
8785/* */
8786/* DMA Controller */
8787/* */
8788/******************************************************************************/
8789/******************** Bits definition for DMA_SxCR register *****************/
8790#define DMA_SxCR_MBURST_Pos (23U)
8791#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
8792#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
8793#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
8794#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
8795#define DMA_SxCR_PBURST_Pos (21U)
8796#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
8797#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
8798#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
8799#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
8800#define DMA_SxCR_TRBUFF_Pos (20U)
8801#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos)
8802#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk
8803#define DMA_SxCR_CT_Pos (19U)
8804#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
8805#define DMA_SxCR_CT DMA_SxCR_CT_Msk
8806#define DMA_SxCR_DBM_Pos (18U)
8807#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
8808#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
8809#define DMA_SxCR_PL_Pos (16U)
8810#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
8811#define DMA_SxCR_PL DMA_SxCR_PL_Msk
8812#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
8813#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
8814#define DMA_SxCR_PINCOS_Pos (15U)
8815#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
8816#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
8817#define DMA_SxCR_MSIZE_Pos (13U)
8818#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
8819#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
8820#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
8821#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
8822#define DMA_SxCR_PSIZE_Pos (11U)
8823#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
8824#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
8825#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
8826#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
8827#define DMA_SxCR_MINC_Pos (10U)
8828#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
8829#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
8830#define DMA_SxCR_PINC_Pos (9U)
8831#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
8832#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
8833#define DMA_SxCR_CIRC_Pos (8U)
8834#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
8835#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
8836#define DMA_SxCR_DIR_Pos (6U)
8837#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
8838#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
8839#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
8840#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
8841#define DMA_SxCR_PFCTRL_Pos (5U)
8842#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
8843#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
8844#define DMA_SxCR_TCIE_Pos (4U)
8845#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
8846#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
8847#define DMA_SxCR_HTIE_Pos (3U)
8848#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
8849#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
8850#define DMA_SxCR_TEIE_Pos (2U)
8851#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
8852#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
8853#define DMA_SxCR_DMEIE_Pos (1U)
8854#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
8855#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
8856#define DMA_SxCR_EN_Pos (0U)
8857#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
8858#define DMA_SxCR_EN DMA_SxCR_EN_Msk
8860/******************** Bits definition for DMA_SxCNDTR register **************/
8861#define DMA_SxNDT_Pos (0U)
8862#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
8863#define DMA_SxNDT DMA_SxNDT_Msk
8864#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
8865#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
8866#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
8867#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
8868#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
8869#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
8870#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
8871#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
8872#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
8873#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
8874#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
8875#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
8876#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
8877#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
8878#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
8879#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
8881/******************** Bits definition for DMA_SxFCR register ****************/
8882#define DMA_SxFCR_FEIE_Pos (7U)
8883#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
8884#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
8885#define DMA_SxFCR_FS_Pos (3U)
8886#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
8887#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
8888#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
8889#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
8890#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
8891#define DMA_SxFCR_DMDIS_Pos (2U)
8892#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
8893#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
8894#define DMA_SxFCR_FTH_Pos (0U)
8895#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
8896#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
8897#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
8898#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
8900/******************** Bits definition for DMA_LISR register *****************/
8901#define DMA_LISR_TCIF3_Pos (27U)
8902#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
8903#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
8904#define DMA_LISR_HTIF3_Pos (26U)
8905#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
8906#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
8907#define DMA_LISR_TEIF3_Pos (25U)
8908#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
8909#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
8910#define DMA_LISR_DMEIF3_Pos (24U)
8911#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
8912#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
8913#define DMA_LISR_FEIF3_Pos (22U)
8914#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
8915#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
8916#define DMA_LISR_TCIF2_Pos (21U)
8917#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
8918#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
8919#define DMA_LISR_HTIF2_Pos (20U)
8920#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
8921#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
8922#define DMA_LISR_TEIF2_Pos (19U)
8923#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
8924#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
8925#define DMA_LISR_DMEIF2_Pos (18U)
8926#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
8927#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
8928#define DMA_LISR_FEIF2_Pos (16U)
8929#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
8930#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
8931#define DMA_LISR_TCIF1_Pos (11U)
8932#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
8933#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
8934#define DMA_LISR_HTIF1_Pos (10U)
8935#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
8936#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
8937#define DMA_LISR_TEIF1_Pos (9U)
8938#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
8939#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
8940#define DMA_LISR_DMEIF1_Pos (8U)
8941#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
8942#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
8943#define DMA_LISR_FEIF1_Pos (6U)
8944#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
8945#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
8946#define DMA_LISR_TCIF0_Pos (5U)
8947#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
8948#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
8949#define DMA_LISR_HTIF0_Pos (4U)
8950#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
8951#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
8952#define DMA_LISR_TEIF0_Pos (3U)
8953#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
8954#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
8955#define DMA_LISR_DMEIF0_Pos (2U)
8956#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
8957#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
8958#define DMA_LISR_FEIF0_Pos (0U)
8959#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
8960#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
8962/******************** Bits definition for DMA_HISR register *****************/
8963#define DMA_HISR_TCIF7_Pos (27U)
8964#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
8965#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
8966#define DMA_HISR_HTIF7_Pos (26U)
8967#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
8968#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
8969#define DMA_HISR_TEIF7_Pos (25U)
8970#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
8971#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
8972#define DMA_HISR_DMEIF7_Pos (24U)
8973#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
8974#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
8975#define DMA_HISR_FEIF7_Pos (22U)
8976#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
8977#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
8978#define DMA_HISR_TCIF6_Pos (21U)
8979#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
8980#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
8981#define DMA_HISR_HTIF6_Pos (20U)
8982#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
8983#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
8984#define DMA_HISR_TEIF6_Pos (19U)
8985#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
8986#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
8987#define DMA_HISR_DMEIF6_Pos (18U)
8988#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
8989#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
8990#define DMA_HISR_FEIF6_Pos (16U)
8991#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
8992#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
8993#define DMA_HISR_TCIF5_Pos (11U)
8994#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
8995#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
8996#define DMA_HISR_HTIF5_Pos (10U)
8997#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
8998#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
8999#define DMA_HISR_TEIF5_Pos (9U)
9000#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
9001#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
9002#define DMA_HISR_DMEIF5_Pos (8U)
9003#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
9004#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
9005#define DMA_HISR_FEIF5_Pos (6U)
9006#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
9007#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
9008#define DMA_HISR_TCIF4_Pos (5U)
9009#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
9010#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
9011#define DMA_HISR_HTIF4_Pos (4U)
9012#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
9013#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
9014#define DMA_HISR_TEIF4_Pos (3U)
9015#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
9016#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
9017#define DMA_HISR_DMEIF4_Pos (2U)
9018#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
9019#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
9020#define DMA_HISR_FEIF4_Pos (0U)
9021#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
9022#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
9024/******************** Bits definition for DMA_LIFCR register ****************/
9025#define DMA_LIFCR_CTCIF3_Pos (27U)
9026#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
9027#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
9028#define DMA_LIFCR_CHTIF3_Pos (26U)
9029#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
9030#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
9031#define DMA_LIFCR_CTEIF3_Pos (25U)
9032#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
9033#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
9034#define DMA_LIFCR_CDMEIF3_Pos (24U)
9035#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
9036#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
9037#define DMA_LIFCR_CFEIF3_Pos (22U)
9038#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
9039#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
9040#define DMA_LIFCR_CTCIF2_Pos (21U)
9041#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
9042#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
9043#define DMA_LIFCR_CHTIF2_Pos (20U)
9044#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
9045#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
9046#define DMA_LIFCR_CTEIF2_Pos (19U)
9047#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
9048#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
9049#define DMA_LIFCR_CDMEIF2_Pos (18U)
9050#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
9051#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
9052#define DMA_LIFCR_CFEIF2_Pos (16U)
9053#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
9054#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
9055#define DMA_LIFCR_CTCIF1_Pos (11U)
9056#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
9057#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
9058#define DMA_LIFCR_CHTIF1_Pos (10U)
9059#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
9060#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
9061#define DMA_LIFCR_CTEIF1_Pos (9U)
9062#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
9063#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
9064#define DMA_LIFCR_CDMEIF1_Pos (8U)
9065#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
9066#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
9067#define DMA_LIFCR_CFEIF1_Pos (6U)
9068#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
9069#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
9070#define DMA_LIFCR_CTCIF0_Pos (5U)
9071#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
9072#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
9073#define DMA_LIFCR_CHTIF0_Pos (4U)
9074#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
9075#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
9076#define DMA_LIFCR_CTEIF0_Pos (3U)
9077#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
9078#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
9079#define DMA_LIFCR_CDMEIF0_Pos (2U)
9080#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
9081#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
9082#define DMA_LIFCR_CFEIF0_Pos (0U)
9083#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
9084#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
9086/******************** Bits definition for DMA_HIFCR register ****************/
9087#define DMA_HIFCR_CTCIF7_Pos (27U)
9088#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
9089#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
9090#define DMA_HIFCR_CHTIF7_Pos (26U)
9091#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
9092#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
9093#define DMA_HIFCR_CTEIF7_Pos (25U)
9094#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
9095#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
9096#define DMA_HIFCR_CDMEIF7_Pos (24U)
9097#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
9098#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
9099#define DMA_HIFCR_CFEIF7_Pos (22U)
9100#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
9101#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
9102#define DMA_HIFCR_CTCIF6_Pos (21U)
9103#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
9104#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
9105#define DMA_HIFCR_CHTIF6_Pos (20U)
9106#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
9107#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
9108#define DMA_HIFCR_CTEIF6_Pos (19U)
9109#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
9110#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
9111#define DMA_HIFCR_CDMEIF6_Pos (18U)
9112#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
9113#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
9114#define DMA_HIFCR_CFEIF6_Pos (16U)
9115#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
9116#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
9117#define DMA_HIFCR_CTCIF5_Pos (11U)
9118#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
9119#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
9120#define DMA_HIFCR_CHTIF5_Pos (10U)
9121#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
9122#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
9123#define DMA_HIFCR_CTEIF5_Pos (9U)
9124#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
9125#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
9126#define DMA_HIFCR_CDMEIF5_Pos (8U)
9127#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
9128#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
9129#define DMA_HIFCR_CFEIF5_Pos (6U)
9130#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
9131#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
9132#define DMA_HIFCR_CTCIF4_Pos (5U)
9133#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
9134#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
9135#define DMA_HIFCR_CHTIF4_Pos (4U)
9136#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
9137#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
9138#define DMA_HIFCR_CTEIF4_Pos (3U)
9139#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
9140#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
9141#define DMA_HIFCR_CDMEIF4_Pos (2U)
9142#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
9143#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
9144#define DMA_HIFCR_CFEIF4_Pos (0U)
9145#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
9146#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
9148/****************** Bit definition for DMA_SxPAR register ********************/
9149#define DMA_SxPAR_PA_Pos (0U)
9150#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
9151#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
9153/****************** Bit definition for DMA_SxM0AR register ********************/
9154#define DMA_SxM0AR_M0A_Pos (0U)
9155#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
9156#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
9158/****************** Bit definition for DMA_SxM1AR register ********************/
9159#define DMA_SxM1AR_M1A_Pos (0U)
9160#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
9161#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
9163/******************************************************************************/
9164/* */
9165/* DMAMUX Controller */
9166/* */
9167/******************************************************************************/
9168/******************** Bits definition for DMAMUX_CxCR register **************/
9169#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
9170#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9171#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
9172#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9173#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9174#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9175#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9176#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9177#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9178#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9179#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9180#define DMAMUX_CxCR_SOIE_Pos (8U)
9181#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)
9182#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
9183#define DMAMUX_CxCR_EGE_Pos (9U)
9184#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)
9185#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
9186#define DMAMUX_CxCR_SE_Pos (16U)
9187#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)
9188#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
9189#define DMAMUX_CxCR_SPOL_Pos (17U)
9190#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)
9191#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
9192#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)
9193#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)
9194#define DMAMUX_CxCR_NBREQ_Pos (19U)
9195#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)
9196#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
9197#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)
9198#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)
9199#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)
9200#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)
9201#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)
9202#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
9203#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)
9204#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
9205#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)
9206#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)
9207#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)
9208#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)
9209#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)
9211/******************** Bits definition for DMAMUX_CSR register **************/
9212#define DMAMUX_CSR_SOF0_Pos (0U)
9213#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)
9214#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
9215#define DMAMUX_CSR_SOF1_Pos (1U)
9216#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)
9217#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
9218#define DMAMUX_CSR_SOF2_Pos (2U)
9219#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)
9220#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
9221#define DMAMUX_CSR_SOF3_Pos (3U)
9222#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)
9223#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
9224#define DMAMUX_CSR_SOF4_Pos (4U)
9225#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)
9226#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
9227#define DMAMUX_CSR_SOF5_Pos (5U)
9228#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)
9229#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
9230#define DMAMUX_CSR_SOF6_Pos (6U)
9231#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)
9232#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
9233#define DMAMUX_CSR_SOF7_Pos (7U)
9234#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)
9235#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
9236#define DMAMUX_CSR_SOF8_Pos (8U)
9237#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)
9238#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
9239#define DMAMUX_CSR_SOF9_Pos (9U)
9240#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)
9241#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
9242#define DMAMUX_CSR_SOF10_Pos (10U)
9243#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)
9244#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
9245#define DMAMUX_CSR_SOF11_Pos (11U)
9246#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)
9247#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
9248#define DMAMUX_CSR_SOF12_Pos (12U)
9249#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)
9250#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
9251#define DMAMUX_CSR_SOF13_Pos (13U)
9252#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)
9253#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
9254#define DMAMUX_CSR_SOF14_Pos (14U)
9255#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)
9256#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
9257#define DMAMUX_CSR_SOF15_Pos (15U)
9258#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)
9259#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
9261/******************** Bits definition for DMAMUX_CFR register **************/
9262#define DMAMUX_CFR_CSOF0_Pos (0U)
9263#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)
9264#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
9265#define DMAMUX_CFR_CSOF1_Pos (1U)
9266#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)
9267#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
9268#define DMAMUX_CFR_CSOF2_Pos (2U)
9269#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)
9270#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
9271#define DMAMUX_CFR_CSOF3_Pos (3U)
9272#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)
9273#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
9274#define DMAMUX_CFR_CSOF4_Pos (4U)
9275#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)
9276#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
9277#define DMAMUX_CFR_CSOF5_Pos (5U)
9278#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)
9279#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
9280#define DMAMUX_CFR_CSOF6_Pos (6U)
9281#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)
9282#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
9283#define DMAMUX_CFR_CSOF7_Pos (7U)
9284#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)
9285#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
9286#define DMAMUX_CFR_CSOF8_Pos (8U)
9287#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)
9288#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
9289#define DMAMUX_CFR_CSOF9_Pos (9U)
9290#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)
9291#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
9292#define DMAMUX_CFR_CSOF10_Pos (10U)
9293#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)
9294#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
9295#define DMAMUX_CFR_CSOF11_Pos (11U)
9296#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)
9297#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
9298#define DMAMUX_CFR_CSOF12_Pos (12U)
9299#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)
9300#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
9301#define DMAMUX_CFR_CSOF13_Pos (13U)
9302#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)
9303#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
9304#define DMAMUX_CFR_CSOF14_Pos (14U)
9305#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)
9306#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
9307#define DMAMUX_CFR_CSOF15_Pos (15U)
9308#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)
9309#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
9311/******************** Bits definition for DMAMUX_RGxCR register ************/
9312#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
9313#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)
9314#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
9315#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)
9316#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)
9317#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)
9318#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)
9319#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)
9320#define DMAMUX_RGxCR_OIE_Pos (8U)
9321#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)
9322#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
9323#define DMAMUX_RGxCR_GE_Pos (16U)
9324#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)
9325#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
9326#define DMAMUX_RGxCR_GPOL_Pos (17U)
9327#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)
9328#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
9329#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)
9330#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)
9331#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
9332#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)
9333#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
9334#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)
9335#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)
9336#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)
9337#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)
9338#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)
9340/******************** Bits definition for DMAMUX_RGSR register **************/
9341#define DMAMUX_RGSR_OF0_Pos (0U)
9342#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)
9343#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
9344#define DMAMUX_RGSR_OF1_Pos (1U)
9345#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)
9346#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
9347#define DMAMUX_RGSR_OF2_Pos (2U)
9348#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)
9349#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
9350#define DMAMUX_RGSR_OF3_Pos (3U)
9351#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)
9352#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
9353#define DMAMUX_RGSR_OF4_Pos (4U)
9354#define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos)
9355#define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk
9356#define DMAMUX_RGSR_OF5_Pos (5U)
9357#define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos)
9358#define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk
9359#define DMAMUX_RGSR_OF6_Pos (6U)
9360#define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos)
9361#define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk
9362#define DMAMUX_RGSR_OF7_Pos (7U)
9363#define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos)
9364#define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk
9366/******************** Bits definition for DMAMUX_RGCFR register **************/
9367#define DMAMUX_RGCFR_COF0_Pos (0U)
9368#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)
9369#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
9370#define DMAMUX_RGCFR_COF1_Pos (1U)
9371#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)
9372#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
9373#define DMAMUX_RGCFR_COF2_Pos (2U)
9374#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)
9375#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
9376#define DMAMUX_RGCFR_COF3_Pos (3U)
9377#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)
9378#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
9379#define DMAMUX_RGCFR_COF4_Pos (4U)
9380#define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos)
9381#define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk
9382#define DMAMUX_RGCFR_COF5_Pos (5U)
9383#define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos)
9384#define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk
9385#define DMAMUX_RGCFR_COF6_Pos (6U)
9386#define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos)
9387#define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk
9388#define DMAMUX_RGCFR_COF7_Pos (7U)
9389#define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos)
9390#define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk
9392/******************************************************************************/
9393/* */
9394/* AHB Master DMA2D Controller (DMA2D) */
9395/* */
9396/******************************************************************************/
9397
9398/******************** Bit definition for DMA2D_CR register ******************/
9399
9400#define DMA2D_CR_START_Pos (0U)
9401#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
9402#define DMA2D_CR_START DMA2D_CR_START_Msk
9403#define DMA2D_CR_SUSP_Pos (1U)
9404#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
9405#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
9406#define DMA2D_CR_ABORT_Pos (2U)
9407#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
9408#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
9409#define DMA2D_CR_LOM_Pos (6U)
9410#define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos)
9411#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk
9412#define DMA2D_CR_TEIE_Pos (8U)
9413#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
9414#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
9415#define DMA2D_CR_TCIE_Pos (9U)
9416#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
9417#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
9418#define DMA2D_CR_TWIE_Pos (10U)
9419#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
9420#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
9421#define DMA2D_CR_CAEIE_Pos (11U)
9422#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
9423#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
9424#define DMA2D_CR_CTCIE_Pos (12U)
9425#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
9426#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
9427#define DMA2D_CR_CEIE_Pos (13U)
9428#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
9429#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
9430#define DMA2D_CR_MODE_Pos (16U)
9431#define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos)
9432#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
9433#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
9434#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
9435#define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos)
9437/******************** Bit definition for DMA2D_ISR register *****************/
9438
9439#define DMA2D_ISR_TEIF_Pos (0U)
9440#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
9441#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
9442#define DMA2D_ISR_TCIF_Pos (1U)
9443#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
9444#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
9445#define DMA2D_ISR_TWIF_Pos (2U)
9446#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
9447#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
9448#define DMA2D_ISR_CAEIF_Pos (3U)
9449#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
9450#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
9451#define DMA2D_ISR_CTCIF_Pos (4U)
9452#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
9453#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
9454#define DMA2D_ISR_CEIF_Pos (5U)
9455#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
9456#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
9458/******************** Bit definition for DMA2D_IFCR register ****************/
9459
9460#define DMA2D_IFCR_CTEIF_Pos (0U)
9461#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
9462#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
9463#define DMA2D_IFCR_CTCIF_Pos (1U)
9464#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
9465#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
9466#define DMA2D_IFCR_CTWIF_Pos (2U)
9467#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
9468#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
9469#define DMA2D_IFCR_CAECIF_Pos (3U)
9470#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
9471#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
9472#define DMA2D_IFCR_CCTCIF_Pos (4U)
9473#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
9474#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
9475#define DMA2D_IFCR_CCEIF_Pos (5U)
9476#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
9477#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
9479/******************** Bit definition for DMA2D_FGMAR register ***************/
9480
9481#define DMA2D_FGMAR_MA_Pos (0U)
9482#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
9483#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
9485/******************** Bit definition for DMA2D_FGOR register ****************/
9486
9487#define DMA2D_FGOR_LO_Pos (0U)
9488#define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos)
9489#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
9491/******************** Bit definition for DMA2D_BGMAR register ***************/
9492
9493#define DMA2D_BGMAR_MA_Pos (0U)
9494#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
9495#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
9497/******************** Bit definition for DMA2D_BGOR register ****************/
9498
9499#define DMA2D_BGOR_LO_Pos (0U)
9500#define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos)
9501#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
9503/******************** Bit definition for DMA2D_FGPFCCR register *************/
9504
9505#define DMA2D_FGPFCCR_CM_Pos (0U)
9506#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
9507#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
9508#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
9509#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
9510#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
9511#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
9512#define DMA2D_FGPFCCR_CCM_Pos (4U)
9513#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
9514#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
9515#define DMA2D_FGPFCCR_START_Pos (5U)
9516#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
9517#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
9518#define DMA2D_FGPFCCR_CS_Pos (8U)
9519#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
9520#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
9521#define DMA2D_FGPFCCR_AM_Pos (16U)
9522#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
9523#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
9524#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
9525#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
9526#define DMA2D_FGPFCCR_CSS_Pos (18U)
9527#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos)
9528#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
9529#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos)
9530#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos)
9531#define DMA2D_FGPFCCR_AI_Pos (20U)
9532#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos)
9533#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk
9534#define DMA2D_FGPFCCR_RBS_Pos (21U)
9535#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos)
9536#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk
9537#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
9538#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
9539#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
9541/******************** Bit definition for DMA2D_FGCOLR register **************/
9542
9543#define DMA2D_FGCOLR_BLUE_Pos (0U)
9544#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
9545#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
9546#define DMA2D_FGCOLR_GREEN_Pos (8U)
9547#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
9548#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
9549#define DMA2D_FGCOLR_RED_Pos (16U)
9550#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
9551#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
9553/******************** Bit definition for DMA2D_BGPFCCR register *************/
9554
9555#define DMA2D_BGPFCCR_CM_Pos (0U)
9556#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
9557#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
9558#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
9559#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
9560#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
9561#define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos)
9562#define DMA2D_BGPFCCR_CCM_Pos (4U)
9563#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
9564#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
9565#define DMA2D_BGPFCCR_START_Pos (5U)
9566#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
9567#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
9568#define DMA2D_BGPFCCR_CS_Pos (8U)
9569#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
9570#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
9571#define DMA2D_BGPFCCR_AM_Pos (16U)
9572#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
9573#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
9574#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
9575#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
9576#define DMA2D_BGPFCCR_AI_Pos (20U)
9577#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos)
9578#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk
9579#define DMA2D_BGPFCCR_RBS_Pos (21U)
9580#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos)
9581#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk
9582#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
9583#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
9584#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
9586/******************** Bit definition for DMA2D_BGCOLR register **************/
9587
9588#define DMA2D_BGCOLR_BLUE_Pos (0U)
9589#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
9590#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
9591#define DMA2D_BGCOLR_GREEN_Pos (8U)
9592#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
9593#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
9594#define DMA2D_BGCOLR_RED_Pos (16U)
9595#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
9596#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
9598/******************** Bit definition for DMA2D_FGCMAR register **************/
9599
9600#define DMA2D_FGCMAR_MA_Pos (0U)
9601#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
9602#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
9604/******************** Bit definition for DMA2D_BGCMAR register **************/
9605
9606#define DMA2D_BGCMAR_MA_Pos (0U)
9607#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
9608#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
9610/******************** Bit definition for DMA2D_OPFCCR register **************/
9611
9612#define DMA2D_OPFCCR_CM_Pos (0U)
9613#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
9614#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
9615#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
9616#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
9617#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
9618#define DMA2D_OPFCCR_SB_Pos (8U)
9619#define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos)
9620#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk
9621#define DMA2D_OPFCCR_AI_Pos (20U)
9622#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos)
9623#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk
9624#define DMA2D_OPFCCR_RBS_Pos (21U)
9625#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos)
9626#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk
9628/******************** Bit definition for DMA2D_OCOLR register ***************/
9629
9632#define DMA2D_OCOLR_BLUE_1_Pos (0U)
9633#define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
9634#define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk
9635#define DMA2D_OCOLR_GREEN_1_Pos (8U)
9636#define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
9637#define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk
9638#define DMA2D_OCOLR_RED_1_Pos (16U)
9639#define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
9640#define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk
9641#define DMA2D_OCOLR_ALPHA_1_Pos (24U)
9642#define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
9643#define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk
9646#define DMA2D_OCOLR_BLUE_2_Pos (0U)
9647#define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
9648#define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk
9649#define DMA2D_OCOLR_GREEN_2_Pos (5U)
9650#define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
9651#define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk
9652#define DMA2D_OCOLR_RED_2_Pos (11U)
9653#define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
9654#define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk
9657#define DMA2D_OCOLR_BLUE_3_Pos (0U)
9658#define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
9659#define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk
9660#define DMA2D_OCOLR_GREEN_3_Pos (5U)
9661#define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
9662#define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk
9663#define DMA2D_OCOLR_RED_3_Pos (10U)
9664#define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
9665#define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk
9666#define DMA2D_OCOLR_ALPHA_3_Pos (15U)
9667#define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
9668#define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk
9671#define DMA2D_OCOLR_BLUE_4_Pos (0U)
9672#define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
9673#define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk
9674#define DMA2D_OCOLR_GREEN_4_Pos (4U)
9675#define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
9676#define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk
9677#define DMA2D_OCOLR_RED_4_Pos (8U)
9678#define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
9679#define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk
9680#define DMA2D_OCOLR_ALPHA_4_Pos (12U)
9681#define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
9682#define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk
9684/******************** Bit definition for DMA2D_OMAR register ****************/
9685
9686#define DMA2D_OMAR_MA_Pos (0U)
9687#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
9688#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
9690/******************** Bit definition for DMA2D_OOR register *****************/
9691
9692#define DMA2D_OOR_LO_Pos (0U)
9693#define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos)
9694#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
9696/******************** Bit definition for DMA2D_NLR register *****************/
9697
9698#define DMA2D_NLR_NL_Pos (0U)
9699#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
9700#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
9701#define DMA2D_NLR_PL_Pos (16U)
9702#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
9703#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
9705/******************** Bit definition for DMA2D_LWR register *****************/
9706
9707#define DMA2D_LWR_LW_Pos (0U)
9708#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
9709#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
9711/******************** Bit definition for DMA2D_AMTCR register ***************/
9712
9713#define DMA2D_AMTCR_EN_Pos (0U)
9714#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
9715#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
9716#define DMA2D_AMTCR_DT_Pos (8U)
9717#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
9718#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
9721/******************** Bit definition for DMA2D_FGCLUT register **************/
9722
9723/******************** Bit definition for DMA2D_BGCLUT register **************/
9724
9725/******************************************************************************/
9726/* */
9727/* Display Serial Interface (DSI) */
9728/* */
9729/******************************************************************************/
9730/******************* Bit definition for DSI_VR register *****************/
9731#define DSI_VR_Pos (1U)
9732#define DSI_VR_Msk (0x18999815UL << DSI_VR_Pos)
9733#define DSI_VR DSI_VR_Msk
9735/******************* Bit definition for DSI_CR register *****************/
9736#define DSI_CR_EN_Pos (0U)
9737#define DSI_CR_EN_Msk (0x1UL << DSI_CR_EN_Pos)
9738#define DSI_CR_EN DSI_CR_EN_Msk
9740/******************* Bit definition for DSI_CCR register ****************/
9741#define DSI_CCR_TXECKDIV_Pos (0U)
9742#define DSI_CCR_TXECKDIV_Msk (0xFFUL << DSI_CCR_TXECKDIV_Pos)
9743#define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk
9744#define DSI_CCR_TXECKDIV0_Pos (0U)
9745#define DSI_CCR_TXECKDIV0_Msk (0x1UL << DSI_CCR_TXECKDIV0_Pos)
9746#define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
9747#define DSI_CCR_TXECKDIV1_Pos (1U)
9748#define DSI_CCR_TXECKDIV1_Msk (0x1UL << DSI_CCR_TXECKDIV1_Pos)
9749#define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
9750#define DSI_CCR_TXECKDIV2_Pos (2U)
9751#define DSI_CCR_TXECKDIV2_Msk (0x1UL << DSI_CCR_TXECKDIV2_Pos)
9752#define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
9753#define DSI_CCR_TXECKDIV3_Pos (3U)
9754#define DSI_CCR_TXECKDIV3_Msk (0x1UL << DSI_CCR_TXECKDIV3_Pos)
9755#define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
9756#define DSI_CCR_TXECKDIV4_Pos (4U)
9757#define DSI_CCR_TXECKDIV4_Msk (0x1UL << DSI_CCR_TXECKDIV4_Pos)
9758#define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
9759#define DSI_CCR_TXECKDIV5_Pos (5U)
9760#define DSI_CCR_TXECKDIV5_Msk (0x1UL << DSI_CCR_TXECKDIV5_Pos)
9761#define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
9762#define DSI_CCR_TXECKDIV6_Pos (6U)
9763#define DSI_CCR_TXECKDIV6_Msk (0x1UL << DSI_CCR_TXECKDIV6_Pos)
9764#define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
9765#define DSI_CCR_TXECKDIV7_Pos (7U)
9766#define DSI_CCR_TXECKDIV7_Msk (0x1UL << DSI_CCR_TXECKDIV7_Pos)
9767#define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
9768
9769#define DSI_CCR_TOCKDIV_Pos (8U)
9770#define DSI_CCR_TOCKDIV_Msk (0xFFUL << DSI_CCR_TOCKDIV_Pos)
9771#define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk
9772#define DSI_CCR_TOCKDIV0_Pos (8U)
9773#define DSI_CCR_TOCKDIV0_Msk (0x1UL << DSI_CCR_TOCKDIV0_Pos)
9774#define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
9775#define DSI_CCR_TOCKDIV1_Pos (9U)
9776#define DSI_CCR_TOCKDIV1_Msk (0x1UL << DSI_CCR_TOCKDIV1_Pos)
9777#define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
9778#define DSI_CCR_TOCKDIV2_Pos (10U)
9779#define DSI_CCR_TOCKDIV2_Msk (0x1UL << DSI_CCR_TOCKDIV2_Pos)
9780#define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
9781#define DSI_CCR_TOCKDIV3_Pos (11U)
9782#define DSI_CCR_TOCKDIV3_Msk (0x1UL << DSI_CCR_TOCKDIV3_Pos)
9783#define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
9784#define DSI_CCR_TOCKDIV4_Pos (12U)
9785#define DSI_CCR_TOCKDIV4_Msk (0x1UL << DSI_CCR_TOCKDIV4_Pos)
9786#define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
9787#define DSI_CCR_TOCKDIV5_Pos (13U)
9788#define DSI_CCR_TOCKDIV5_Msk (0x1UL << DSI_CCR_TOCKDIV5_Pos)
9789#define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
9790#define DSI_CCR_TOCKDIV6_Pos (14U)
9791#define DSI_CCR_TOCKDIV6_Msk (0x1UL << DSI_CCR_TOCKDIV6_Pos)
9792#define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
9793#define DSI_CCR_TOCKDIV7_Pos (15U)
9794#define DSI_CCR_TOCKDIV7_Msk (0x1UL << DSI_CCR_TOCKDIV7_Pos)
9795#define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
9796
9797/******************* Bit definition for DSI_LVCIDR register *************/
9798#define DSI_LVCIDR_VCID_Pos (0U)
9799#define DSI_LVCIDR_VCID_Msk (0x3UL << DSI_LVCIDR_VCID_Pos)
9800#define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk
9801#define DSI_LVCIDR_VCID0_Pos (0U)
9802#define DSI_LVCIDR_VCID0_Msk (0x1UL << DSI_LVCIDR_VCID0_Pos)
9803#define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
9804#define DSI_LVCIDR_VCID1_Pos (1U)
9805#define DSI_LVCIDR_VCID1_Msk (0x1UL << DSI_LVCIDR_VCID1_Pos)
9806#define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
9807
9808/******************* Bit definition for DSI_LCOLCR register *************/
9809#define DSI_LCOLCR_COLC_Pos (0U)
9810#define DSI_LCOLCR_COLC_Msk (0xFUL << DSI_LCOLCR_COLC_Pos)
9811#define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk
9812#define DSI_LCOLCR_COLC0_Pos (0U)
9813#define DSI_LCOLCR_COLC0_Msk (0x1UL << DSI_LCOLCR_COLC0_Pos)
9814#define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
9815#define DSI_LCOLCR_COLC1_Pos (5U)
9816#define DSI_LCOLCR_COLC1_Msk (0x1UL << DSI_LCOLCR_COLC1_Pos)
9817#define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
9818#define DSI_LCOLCR_COLC2_Pos (6U)
9819#define DSI_LCOLCR_COLC2_Msk (0x1UL << DSI_LCOLCR_COLC2_Pos)
9820#define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
9821#define DSI_LCOLCR_COLC3_Pos (7U)
9822#define DSI_LCOLCR_COLC3_Msk (0x1UL << DSI_LCOLCR_COLC3_Pos)
9823#define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
9824
9825#define DSI_LCOLCR_LPE_Pos (8U)
9826#define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos)
9827#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk
9829/******************* Bit definition for DSI_LPCR register ***************/
9830#define DSI_LPCR_DEP_Pos (0U)
9831#define DSI_LPCR_DEP_Msk (0x1UL << DSI_LPCR_DEP_Pos)
9832#define DSI_LPCR_DEP DSI_LPCR_DEP_Msk
9833#define DSI_LPCR_VSP_Pos (1U)
9834#define DSI_LPCR_VSP_Msk (0x1UL << DSI_LPCR_VSP_Pos)
9835#define DSI_LPCR_VSP DSI_LPCR_VSP_Msk
9836#define DSI_LPCR_HSP_Pos (2U)
9837#define DSI_LPCR_HSP_Msk (0x1UL << DSI_LPCR_HSP_Pos)
9838#define DSI_LPCR_HSP DSI_LPCR_HSP_Msk
9840/******************* Bit definition for DSI_LPMCR register **************/
9841#define DSI_LPMCR_VLPSIZE_Pos (0U)
9842#define DSI_LPMCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCR_VLPSIZE_Pos)
9843#define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk
9844#define DSI_LPMCR_VLPSIZE0_Pos (0U)
9845#define DSI_LPMCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCR_VLPSIZE0_Pos)
9846#define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
9847#define DSI_LPMCR_VLPSIZE1_Pos (1U)
9848#define DSI_LPMCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCR_VLPSIZE1_Pos)
9849#define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
9850#define DSI_LPMCR_VLPSIZE2_Pos (2U)
9851#define DSI_LPMCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCR_VLPSIZE2_Pos)
9852#define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
9853#define DSI_LPMCR_VLPSIZE3_Pos (3U)
9854#define DSI_LPMCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCR_VLPSIZE3_Pos)
9855#define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
9856#define DSI_LPMCR_VLPSIZE4_Pos (4U)
9857#define DSI_LPMCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCR_VLPSIZE4_Pos)
9858#define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
9859#define DSI_LPMCR_VLPSIZE5_Pos (5U)
9860#define DSI_LPMCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCR_VLPSIZE5_Pos)
9861#define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
9862#define DSI_LPMCR_VLPSIZE6_Pos (6U)
9863#define DSI_LPMCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCR_VLPSIZE6_Pos)
9864#define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
9865#define DSI_LPMCR_VLPSIZE7_Pos (7U)
9866#define DSI_LPMCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCR_VLPSIZE7_Pos)
9867#define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
9868
9869#define DSI_LPMCR_LPSIZE_Pos (16U)
9870#define DSI_LPMCR_LPSIZE_Msk (0xFFUL << DSI_LPMCR_LPSIZE_Pos)
9871#define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk
9872#define DSI_LPMCR_LPSIZE0_Pos (16U)
9873#define DSI_LPMCR_LPSIZE0_Msk (0x1UL << DSI_LPMCR_LPSIZE0_Pos)
9874#define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
9875#define DSI_LPMCR_LPSIZE1_Pos (17U)
9876#define DSI_LPMCR_LPSIZE1_Msk (0x1UL << DSI_LPMCR_LPSIZE1_Pos)
9877#define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
9878#define DSI_LPMCR_LPSIZE2_Pos (18U)
9879#define DSI_LPMCR_LPSIZE2_Msk (0x1UL << DSI_LPMCR_LPSIZE2_Pos)
9880#define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
9881#define DSI_LPMCR_LPSIZE3_Pos (19U)
9882#define DSI_LPMCR_LPSIZE3_Msk (0x1UL << DSI_LPMCR_LPSIZE3_Pos)
9883#define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
9884#define DSI_LPMCR_LPSIZE4_Pos (20U)
9885#define DSI_LPMCR_LPSIZE4_Msk (0x1UL << DSI_LPMCR_LPSIZE4_Pos)
9886#define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
9887#define DSI_LPMCR_LPSIZE5_Pos (21U)
9888#define DSI_LPMCR_LPSIZE5_Msk (0x1UL << DSI_LPMCR_LPSIZE5_Pos)
9889#define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
9890#define DSI_LPMCR_LPSIZE6_Pos (22U)
9891#define DSI_LPMCR_LPSIZE6_Msk (0x1UL << DSI_LPMCR_LPSIZE6_Pos)
9892#define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
9893#define DSI_LPMCR_LPSIZE7_Pos (23U)
9894#define DSI_LPMCR_LPSIZE7_Msk (0x1UL << DSI_LPMCR_LPSIZE7_Pos)
9895#define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
9896
9897/******************* Bit definition for DSI_PCR register ****************/
9898#define DSI_PCR_ETTXE_Pos (0U)
9899#define DSI_PCR_ETTXE_Msk (0x1UL << DSI_PCR_ETTXE_Pos)
9900#define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk
9901#define DSI_PCR_ETRXE_Pos (1U)
9902#define DSI_PCR_ETRXE_Msk (0x1UL << DSI_PCR_ETRXE_Pos)
9903#define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk
9904#define DSI_PCR_BTAE_Pos (2U)
9905#define DSI_PCR_BTAE_Msk (0x1UL << DSI_PCR_BTAE_Pos)
9906#define DSI_PCR_BTAE DSI_PCR_BTAE_Msk
9907#define DSI_PCR_ECCRXE_Pos (3U)
9908#define DSI_PCR_ECCRXE_Msk (0x1UL << DSI_PCR_ECCRXE_Pos)
9909#define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk
9910#define DSI_PCR_CRCRXE_Pos (4U)
9911#define DSI_PCR_CRCRXE_Msk (0x1UL << DSI_PCR_CRCRXE_Pos)
9912#define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk
9914/******************* Bit definition for DSI_GVCIDR register *************/
9915#define DSI_GVCIDR_VCID_Pos (0U)
9916#define DSI_GVCIDR_VCID_Msk (0x3UL << DSI_GVCIDR_VCID_Pos)
9917#define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk
9918#define DSI_GVCIDR_VCID0_Pos (0U)
9919#define DSI_GVCIDR_VCID0_Msk (0x1UL << DSI_GVCIDR_VCID0_Pos)
9920#define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
9921#define DSI_GVCIDR_VCID1_Pos (1U)
9922#define DSI_GVCIDR_VCID1_Msk (0x1UL << DSI_GVCIDR_VCID1_Pos)
9923#define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
9924
9925/******************* Bit definition for DSI_MCR register ****************/
9926#define DSI_MCR_CMDM_Pos (0U)
9927#define DSI_MCR_CMDM_Msk (0x1UL << DSI_MCR_CMDM_Pos)
9928#define DSI_MCR_CMDM DSI_MCR_CMDM_Msk
9930/******************* Bit definition for DSI_VMCR register ***************/
9931#define DSI_VMCR_VMT_Pos (0U)
9932#define DSI_VMCR_VMT_Msk (0x3UL << DSI_VMCR_VMT_Pos)
9933#define DSI_VMCR_VMT DSI_VMCR_VMT_Msk
9934#define DSI_VMCR_VMT0_Pos (0U)
9935#define DSI_VMCR_VMT0_Msk (0x1UL << DSI_VMCR_VMT0_Pos)
9936#define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
9937#define DSI_VMCR_VMT1_Pos (1U)
9938#define DSI_VMCR_VMT1_Msk (0x1UL << DSI_VMCR_VMT1_Pos)
9939#define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
9940
9941#define DSI_VMCR_LPVSAE_Pos (8U)
9942#define DSI_VMCR_LPVSAE_Msk (0x1UL << DSI_VMCR_LPVSAE_Pos)
9943#define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk
9944#define DSI_VMCR_LPVBPE_Pos (9U)
9945#define DSI_VMCR_LPVBPE_Msk (0x1UL << DSI_VMCR_LPVBPE_Pos)
9946#define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk
9947#define DSI_VMCR_LPVFPE_Pos (10U)
9948#define DSI_VMCR_LPVFPE_Msk (0x1UL << DSI_VMCR_LPVFPE_Pos)
9949#define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk
9950#define DSI_VMCR_LPVAE_Pos (11U)
9951#define DSI_VMCR_LPVAE_Msk (0x1UL << DSI_VMCR_LPVAE_Pos)
9952#define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk
9953#define DSI_VMCR_LPHBPE_Pos (12U)
9954#define DSI_VMCR_LPHBPE_Msk (0x1UL << DSI_VMCR_LPHBPE_Pos)
9955#define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk
9956#define DSI_VMCR_LPHFPE_Pos (13U)
9957#define DSI_VMCR_LPHFPE_Msk (0x1UL << DSI_VMCR_LPHFPE_Pos)
9958#define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk
9959#define DSI_VMCR_FBTAAE_Pos (14U)
9960#define DSI_VMCR_FBTAAE_Msk (0x1UL << DSI_VMCR_FBTAAE_Pos)
9961#define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk
9962#define DSI_VMCR_LPCE_Pos (15U)
9963#define DSI_VMCR_LPCE_Msk (0x1UL << DSI_VMCR_LPCE_Pos)
9964#define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk
9965#define DSI_VMCR_PGE_Pos (16U)
9966#define DSI_VMCR_PGE_Msk (0x1UL << DSI_VMCR_PGE_Pos)
9967#define DSI_VMCR_PGE DSI_VMCR_PGE_Msk
9968#define DSI_VMCR_PGM_Pos (20U)
9969#define DSI_VMCR_PGM_Msk (0x1UL << DSI_VMCR_PGM_Pos)
9970#define DSI_VMCR_PGM DSI_VMCR_PGM_Msk
9971#define DSI_VMCR_PGO_Pos (24U)
9972#define DSI_VMCR_PGO_Msk (0x1UL << DSI_VMCR_PGO_Pos)
9973#define DSI_VMCR_PGO DSI_VMCR_PGO_Msk
9975/******************* Bit definition for DSI_VPCR register ***************/
9976#define DSI_VPCR_VPSIZE_Pos (0U)
9977#define DSI_VPCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCR_VPSIZE_Pos)
9978#define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk
9979#define DSI_VPCR_VPSIZE0_Pos (0U)
9980#define DSI_VPCR_VPSIZE0_Msk (0x1UL << DSI_VPCR_VPSIZE0_Pos)
9981#define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
9982#define DSI_VPCR_VPSIZE1_Pos (1U)
9983#define DSI_VPCR_VPSIZE1_Msk (0x1UL << DSI_VPCR_VPSIZE1_Pos)
9984#define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
9985#define DSI_VPCR_VPSIZE2_Pos (2U)
9986#define DSI_VPCR_VPSIZE2_Msk (0x1UL << DSI_VPCR_VPSIZE2_Pos)
9987#define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
9988#define DSI_VPCR_VPSIZE3_Pos (3U)
9989#define DSI_VPCR_VPSIZE3_Msk (0x1UL << DSI_VPCR_VPSIZE3_Pos)
9990#define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
9991#define DSI_VPCR_VPSIZE4_Pos (4U)
9992#define DSI_VPCR_VPSIZE4_Msk (0x1UL << DSI_VPCR_VPSIZE4_Pos)
9993#define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
9994#define DSI_VPCR_VPSIZE5_Pos (5U)
9995#define DSI_VPCR_VPSIZE5_Msk (0x1UL << DSI_VPCR_VPSIZE5_Pos)
9996#define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
9997#define DSI_VPCR_VPSIZE6_Pos (6U)
9998#define DSI_VPCR_VPSIZE6_Msk (0x1UL << DSI_VPCR_VPSIZE6_Pos)
9999#define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
10000#define DSI_VPCR_VPSIZE7_Pos (7U)
10001#define DSI_VPCR_VPSIZE7_Msk (0x1UL << DSI_VPCR_VPSIZE7_Pos)
10002#define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
10003#define DSI_VPCR_VPSIZE8_Pos (8U)
10004#define DSI_VPCR_VPSIZE8_Msk (0x1UL << DSI_VPCR_VPSIZE8_Pos)
10005#define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
10006#define DSI_VPCR_VPSIZE9_Pos (9U)
10007#define DSI_VPCR_VPSIZE9_Msk (0x1UL << DSI_VPCR_VPSIZE9_Pos)
10008#define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
10009#define DSI_VPCR_VPSIZE10_Pos (10U)
10010#define DSI_VPCR_VPSIZE10_Msk (0x1UL << DSI_VPCR_VPSIZE10_Pos)
10011#define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
10012#define DSI_VPCR_VPSIZE11_Pos (11U)
10013#define DSI_VPCR_VPSIZE11_Msk (0x1UL << DSI_VPCR_VPSIZE11_Pos)
10014#define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
10015#define DSI_VPCR_VPSIZE12_Pos (12U)
10016#define DSI_VPCR_VPSIZE12_Msk (0x1UL << DSI_VPCR_VPSIZE12_Pos)
10017#define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
10018#define DSI_VPCR_VPSIZE13_Pos (13U)
10019#define DSI_VPCR_VPSIZE13_Msk (0x1UL << DSI_VPCR_VPSIZE13_Pos)
10020#define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
10021
10022/******************* Bit definition for DSI_VCCR register ***************/
10023#define DSI_VCCR_NUMC_Pos (0U)
10024#define DSI_VCCR_NUMC_Msk (0x1FFFUL << DSI_VCCR_NUMC_Pos)
10025#define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk
10026#define DSI_VCCR_NUMC0_Pos (0U)
10027#define DSI_VCCR_NUMC0_Msk (0x1UL << DSI_VCCR_NUMC0_Pos)
10028#define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
10029#define DSI_VCCR_NUMC1_Pos (1U)
10030#define DSI_VCCR_NUMC1_Msk (0x1UL << DSI_VCCR_NUMC1_Pos)
10031#define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
10032#define DSI_VCCR_NUMC2_Pos (2U)
10033#define DSI_VCCR_NUMC2_Msk (0x1UL << DSI_VCCR_NUMC2_Pos)
10034#define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
10035#define DSI_VCCR_NUMC3_Pos (3U)
10036#define DSI_VCCR_NUMC3_Msk (0x1UL << DSI_VCCR_NUMC3_Pos)
10037#define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
10038#define DSI_VCCR_NUMC4_Pos (4U)
10039#define DSI_VCCR_NUMC4_Msk (0x1UL << DSI_VCCR_NUMC4_Pos)
10040#define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
10041#define DSI_VCCR_NUMC5_Pos (5U)
10042#define DSI_VCCR_NUMC5_Msk (0x1UL << DSI_VCCR_NUMC5_Pos)
10043#define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
10044#define DSI_VCCR_NUMC6_Pos (6U)
10045#define DSI_VCCR_NUMC6_Msk (0x1UL << DSI_VCCR_NUMC6_Pos)
10046#define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
10047#define DSI_VCCR_NUMC7_Pos (7U)
10048#define DSI_VCCR_NUMC7_Msk (0x1UL << DSI_VCCR_NUMC7_Pos)
10049#define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
10050#define DSI_VCCR_NUMC8_Pos (8U)
10051#define DSI_VCCR_NUMC8_Msk (0x1UL << DSI_VCCR_NUMC8_Pos)
10052#define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
10053#define DSI_VCCR_NUMC9_Pos (9U)
10054#define DSI_VCCR_NUMC9_Msk (0x1UL << DSI_VCCR_NUMC9_Pos)
10055#define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
10056#define DSI_VCCR_NUMC10_Pos (10U)
10057#define DSI_VCCR_NUMC10_Msk (0x1UL << DSI_VCCR_NUMC10_Pos)
10058#define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
10059#define DSI_VCCR_NUMC11_Pos (11U)
10060#define DSI_VCCR_NUMC11_Msk (0x1UL << DSI_VCCR_NUMC11_Pos)
10061#define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
10062#define DSI_VCCR_NUMC12_Pos (12U)
10063#define DSI_VCCR_NUMC12_Msk (0x1UL << DSI_VCCR_NUMC12_Pos)
10064#define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
10065
10066/******************* Bit definition for DSI_VNPCR register **************/
10067#define DSI_VNPCR_NPSIZE_Pos (0U)
10068#define DSI_VNPCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos)
10069#define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk
10070#define DSI_VNPCR_NPSIZE0_Pos (0U)
10071#define DSI_VNPCR_NPSIZE0_Msk (0x1UL << DSI_VNPCR_NPSIZE0_Pos)
10072#define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
10073#define DSI_VNPCR_NPSIZE1_Pos (1U)
10074#define DSI_VNPCR_NPSIZE1_Msk (0x1UL << DSI_VNPCR_NPSIZE1_Pos)
10075#define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
10076#define DSI_VNPCR_NPSIZE2_Pos (2U)
10077#define DSI_VNPCR_NPSIZE2_Msk (0x1UL << DSI_VNPCR_NPSIZE2_Pos)
10078#define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
10079#define DSI_VNPCR_NPSIZE3_Pos (3U)
10080#define DSI_VNPCR_NPSIZE3_Msk (0x1UL << DSI_VNPCR_NPSIZE3_Pos)
10081#define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
10082#define DSI_VNPCR_NPSIZE4_Pos (4U)
10083#define DSI_VNPCR_NPSIZE4_Msk (0x1UL << DSI_VNPCR_NPSIZE4_Pos)
10084#define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
10085#define DSI_VNPCR_NPSIZE5_Pos (5U)
10086#define DSI_VNPCR_NPSIZE5_Msk (0x1UL << DSI_VNPCR_NPSIZE5_Pos)
10087#define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
10088#define DSI_VNPCR_NPSIZE6_Pos (6U)
10089#define DSI_VNPCR_NPSIZE6_Msk (0x1UL << DSI_VNPCR_NPSIZE6_Pos)
10090#define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
10091#define DSI_VNPCR_NPSIZE7_Pos (7U)
10092#define DSI_VNPCR_NPSIZE7_Msk (0x1UL << DSI_VNPCR_NPSIZE7_Pos)
10093#define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
10094#define DSI_VNPCR_NPSIZE8_Pos (8U)
10095#define DSI_VNPCR_NPSIZE8_Msk (0x1UL << DSI_VNPCR_NPSIZE8_Pos)
10096#define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
10097#define DSI_VNPCR_NPSIZE9_Pos (9U)
10098#define DSI_VNPCR_NPSIZE9_Msk (0x1UL << DSI_VNPCR_NPSIZE9_Pos)
10099#define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
10100#define DSI_VNPCR_NPSIZE10_Pos (10U)
10101#define DSI_VNPCR_NPSIZE10_Msk (0x1UL << DSI_VNPCR_NPSIZE10_Pos)
10102#define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
10103#define DSI_VNPCR_NPSIZE11_Pos (11U)
10104#define DSI_VNPCR_NPSIZE11_Msk (0x1UL << DSI_VNPCR_NPSIZE11_Pos)
10105#define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
10106#define DSI_VNPCR_NPSIZE12_Pos (12U)
10107#define DSI_VNPCR_NPSIZE12_Msk (0x1UL << DSI_VNPCR_NPSIZE12_Pos)
10108#define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
10109
10110/******************* Bit definition for DSI_VHSACR register *************/
10111#define DSI_VHSACR_HSA_Pos (0U)
10112#define DSI_VHSACR_HSA_Msk (0xFFFUL << DSI_VHSACR_HSA_Pos)
10113#define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk
10114#define DSI_VHSACR_HSA0_Pos (0U)
10115#define DSI_VHSACR_HSA0_Msk (0x1UL << DSI_VHSACR_HSA0_Pos)
10116#define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
10117#define DSI_VHSACR_HSA1_Pos (1U)
10118#define DSI_VHSACR_HSA1_Msk (0x1UL << DSI_VHSACR_HSA1_Pos)
10119#define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
10120#define DSI_VHSACR_HSA2_Pos (2U)
10121#define DSI_VHSACR_HSA2_Msk (0x1UL << DSI_VHSACR_HSA2_Pos)
10122#define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
10123#define DSI_VHSACR_HSA3_Pos (3U)
10124#define DSI_VHSACR_HSA3_Msk (0x1UL << DSI_VHSACR_HSA3_Pos)
10125#define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
10126#define DSI_VHSACR_HSA4_Pos (4U)
10127#define DSI_VHSACR_HSA4_Msk (0x1UL << DSI_VHSACR_HSA4_Pos)
10128#define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
10129#define DSI_VHSACR_HSA5_Pos (5U)
10130#define DSI_VHSACR_HSA5_Msk (0x1UL << DSI_VHSACR_HSA5_Pos)
10131#define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
10132#define DSI_VHSACR_HSA6_Pos (6U)
10133#define DSI_VHSACR_HSA6_Msk (0x1UL << DSI_VHSACR_HSA6_Pos)
10134#define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
10135#define DSI_VHSACR_HSA7_Pos (7U)
10136#define DSI_VHSACR_HSA7_Msk (0x1UL << DSI_VHSACR_HSA7_Pos)
10137#define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
10138#define DSI_VHSACR_HSA8_Pos (8U)
10139#define DSI_VHSACR_HSA8_Msk (0x1UL << DSI_VHSACR_HSA8_Pos)
10140#define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
10141#define DSI_VHSACR_HSA9_Pos (9U)
10142#define DSI_VHSACR_HSA9_Msk (0x1UL << DSI_VHSACR_HSA9_Pos)
10143#define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
10144#define DSI_VHSACR_HSA10_Pos (10U)
10145#define DSI_VHSACR_HSA10_Msk (0x1UL << DSI_VHSACR_HSA10_Pos)
10146#define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
10147#define DSI_VHSACR_HSA11_Pos (11U)
10148#define DSI_VHSACR_HSA11_Msk (0x1UL << DSI_VHSACR_HSA11_Pos)
10149#define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
10150
10151/******************* Bit definition for DSI_VHBPCR register *************/
10152#define DSI_VHBPCR_HBP_Pos (0U)
10153#define DSI_VHBPCR_HBP_Msk (0xFFFUL << DSI_VHBPCR_HBP_Pos)
10154#define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk
10155#define DSI_VHBPCR_HBP0_Pos (0U)
10156#define DSI_VHBPCR_HBP0_Msk (0x1UL << DSI_VHBPCR_HBP0_Pos)
10157#define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
10158#define DSI_VHBPCR_HBP1_Pos (1U)
10159#define DSI_VHBPCR_HBP1_Msk (0x1UL << DSI_VHBPCR_HBP1_Pos)
10160#define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
10161#define DSI_VHBPCR_HBP2_Pos (2U)
10162#define DSI_VHBPCR_HBP2_Msk (0x1UL << DSI_VHBPCR_HBP2_Pos)
10163#define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
10164#define DSI_VHBPCR_HBP3_Pos (3U)
10165#define DSI_VHBPCR_HBP3_Msk (0x1UL << DSI_VHBPCR_HBP3_Pos)
10166#define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
10167#define DSI_VHBPCR_HBP4_Pos (4U)
10168#define DSI_VHBPCR_HBP4_Msk (0x1UL << DSI_VHBPCR_HBP4_Pos)
10169#define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
10170#define DSI_VHBPCR_HBP5_Pos (5U)
10171#define DSI_VHBPCR_HBP5_Msk (0x1UL << DSI_VHBPCR_HBP5_Pos)
10172#define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
10173#define DSI_VHBPCR_HBP6_Pos (6U)
10174#define DSI_VHBPCR_HBP6_Msk (0x1UL << DSI_VHBPCR_HBP6_Pos)
10175#define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
10176#define DSI_VHBPCR_HBP7_Pos (7U)
10177#define DSI_VHBPCR_HBP7_Msk (0x1UL << DSI_VHBPCR_HBP7_Pos)
10178#define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
10179#define DSI_VHBPCR_HBP8_Pos (8U)
10180#define DSI_VHBPCR_HBP8_Msk (0x1UL << DSI_VHBPCR_HBP8_Pos)
10181#define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
10182#define DSI_VHBPCR_HBP9_Pos (9U)
10183#define DSI_VHBPCR_HBP9_Msk (0x1UL << DSI_VHBPCR_HBP9_Pos)
10184#define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
10185#define DSI_VHBPCR_HBP10_Pos (10U)
10186#define DSI_VHBPCR_HBP10_Msk (0x1UL << DSI_VHBPCR_HBP10_Pos)
10187#define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
10188#define DSI_VHBPCR_HBP11_Pos (11U)
10189#define DSI_VHBPCR_HBP11_Msk (0x1UL << DSI_VHBPCR_HBP11_Pos)
10190#define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
10191
10192/******************* Bit definition for DSI_VLCR register ***************/
10193#define DSI_VLCR_HLINE_Pos (0U)
10194#define DSI_VLCR_HLINE_Msk (0x7FFFUL << DSI_VLCR_HLINE_Pos)
10195#define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk
10196#define DSI_VLCR_HLINE0_Pos (0U)
10197#define DSI_VLCR_HLINE0_Msk (0x1UL << DSI_VLCR_HLINE0_Pos)
10198#define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
10199#define DSI_VLCR_HLINE1_Pos (1U)
10200#define DSI_VLCR_HLINE1_Msk (0x1UL << DSI_VLCR_HLINE1_Pos)
10201#define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
10202#define DSI_VLCR_HLINE2_Pos (2U)
10203#define DSI_VLCR_HLINE2_Msk (0x1UL << DSI_VLCR_HLINE2_Pos)
10204#define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
10205#define DSI_VLCR_HLINE3_Pos (3U)
10206#define DSI_VLCR_HLINE3_Msk (0x1UL << DSI_VLCR_HLINE3_Pos)
10207#define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
10208#define DSI_VLCR_HLINE4_Pos (4U)
10209#define DSI_VLCR_HLINE4_Msk (0x1UL << DSI_VLCR_HLINE4_Pos)
10210#define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
10211#define DSI_VLCR_HLINE5_Pos (5U)
10212#define DSI_VLCR_HLINE5_Msk (0x1UL << DSI_VLCR_HLINE5_Pos)
10213#define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
10214#define DSI_VLCR_HLINE6_Pos (6U)
10215#define DSI_VLCR_HLINE6_Msk (0x1UL << DSI_VLCR_HLINE6_Pos)
10216#define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
10217#define DSI_VLCR_HLINE7_Pos (7U)
10218#define DSI_VLCR_HLINE7_Msk (0x1UL << DSI_VLCR_HLINE7_Pos)
10219#define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
10220#define DSI_VLCR_HLINE8_Pos (8U)
10221#define DSI_VLCR_HLINE8_Msk (0x1UL << DSI_VLCR_HLINE8_Pos)
10222#define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
10223#define DSI_VLCR_HLINE9_Pos (9U)
10224#define DSI_VLCR_HLINE9_Msk (0x1UL << DSI_VLCR_HLINE9_Pos)
10225#define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
10226#define DSI_VLCR_HLINE10_Pos (10U)
10227#define DSI_VLCR_HLINE10_Msk (0x1UL << DSI_VLCR_HLINE10_Pos)
10228#define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
10229#define DSI_VLCR_HLINE11_Pos (11U)
10230#define DSI_VLCR_HLINE11_Msk (0x1UL << DSI_VLCR_HLINE11_Pos)
10231#define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
10232#define DSI_VLCR_HLINE12_Pos (12U)
10233#define DSI_VLCR_HLINE12_Msk (0x1UL << DSI_VLCR_HLINE12_Pos)
10234#define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
10235#define DSI_VLCR_HLINE13_Pos (13U)
10236#define DSI_VLCR_HLINE13_Msk (0x1UL << DSI_VLCR_HLINE13_Pos)
10237#define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
10238#define DSI_VLCR_HLINE14_Pos (14U)
10239#define DSI_VLCR_HLINE14_Msk (0x1UL << DSI_VLCR_HLINE14_Pos)
10240#define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
10241
10242/******************* Bit definition for DSI_VVSACR register *************/
10243#define DSI_VVSACR_VSA_Pos (0U)
10244#define DSI_VVSACR_VSA_Msk (0x3FFUL << DSI_VVSACR_VSA_Pos)
10245#define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk
10246#define DSI_VVSACR_VSA0_Pos (0U)
10247#define DSI_VVSACR_VSA0_Msk (0x1UL << DSI_VVSACR_VSA0_Pos)
10248#define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
10249#define DSI_VVSACR_VSA1_Pos (1U)
10250#define DSI_VVSACR_VSA1_Msk (0x1UL << DSI_VVSACR_VSA1_Pos)
10251#define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
10252#define DSI_VVSACR_VSA2_Pos (2U)
10253#define DSI_VVSACR_VSA2_Msk (0x1UL << DSI_VVSACR_VSA2_Pos)
10254#define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
10255#define DSI_VVSACR_VSA3_Pos (3U)
10256#define DSI_VVSACR_VSA3_Msk (0x1UL << DSI_VVSACR_VSA3_Pos)
10257#define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
10258#define DSI_VVSACR_VSA4_Pos (4U)
10259#define DSI_VVSACR_VSA4_Msk (0x1UL << DSI_VVSACR_VSA4_Pos)
10260#define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
10261#define DSI_VVSACR_VSA5_Pos (5U)
10262#define DSI_VVSACR_VSA5_Msk (0x1UL << DSI_VVSACR_VSA5_Pos)
10263#define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
10264#define DSI_VVSACR_VSA6_Pos (6U)
10265#define DSI_VVSACR_VSA6_Msk (0x1UL << DSI_VVSACR_VSA6_Pos)
10266#define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
10267#define DSI_VVSACR_VSA7_Pos (7U)
10268#define DSI_VVSACR_VSA7_Msk (0x1UL << DSI_VVSACR_VSA7_Pos)
10269#define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
10270#define DSI_VVSACR_VSA8_Pos (8U)
10271#define DSI_VVSACR_VSA8_Msk (0x1UL << DSI_VVSACR_VSA8_Pos)
10272#define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
10273#define DSI_VVSACR_VSA9_Pos (9U)
10274#define DSI_VVSACR_VSA9_Msk (0x1UL << DSI_VVSACR_VSA9_Pos)
10275#define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
10276
10277/******************* Bit definition for DSI_VVBPCR register *************/
10278#define DSI_VVBPCR_VBP_Pos (0U)
10279#define DSI_VVBPCR_VBP_Msk (0x3FFUL << DSI_VVBPCR_VBP_Pos)
10280#define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk
10281#define DSI_VVBPCR_VBP0_Pos (0U)
10282#define DSI_VVBPCR_VBP0_Msk (0x1UL << DSI_VVBPCR_VBP0_Pos)
10283#define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
10284#define DSI_VVBPCR_VBP1_Pos (1U)
10285#define DSI_VVBPCR_VBP1_Msk (0x1UL << DSI_VVBPCR_VBP1_Pos)
10286#define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
10287#define DSI_VVBPCR_VBP2_Pos (2U)
10288#define DSI_VVBPCR_VBP2_Msk (0x1UL << DSI_VVBPCR_VBP2_Pos)
10289#define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
10290#define DSI_VVBPCR_VBP3_Pos (3U)
10291#define DSI_VVBPCR_VBP3_Msk (0x1UL << DSI_VVBPCR_VBP3_Pos)
10292#define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
10293#define DSI_VVBPCR_VBP4_Pos (4U)
10294#define DSI_VVBPCR_VBP4_Msk (0x1UL << DSI_VVBPCR_VBP4_Pos)
10295#define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
10296#define DSI_VVBPCR_VBP5_Pos (5U)
10297#define DSI_VVBPCR_VBP5_Msk (0x1UL << DSI_VVBPCR_VBP5_Pos)
10298#define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
10299#define DSI_VVBPCR_VBP6_Pos (6U)
10300#define DSI_VVBPCR_VBP6_Msk (0x1UL << DSI_VVBPCR_VBP6_Pos)
10301#define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
10302#define DSI_VVBPCR_VBP7_Pos (7U)
10303#define DSI_VVBPCR_VBP7_Msk (0x1UL << DSI_VVBPCR_VBP7_Pos)
10304#define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
10305#define DSI_VVBPCR_VBP8_Pos (8U)
10306#define DSI_VVBPCR_VBP8_Msk (0x1UL << DSI_VVBPCR_VBP8_Pos)
10307#define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
10308#define DSI_VVBPCR_VBP9_Pos (9U)
10309#define DSI_VVBPCR_VBP9_Msk (0x1UL << DSI_VVBPCR_VBP9_Pos)
10310#define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
10311
10312/******************* Bit definition for DSI_VVFPCR register *************/
10313#define DSI_VVFPCR_VFP_Pos (0U)
10314#define DSI_VVFPCR_VFP_Msk (0x3FFUL << DSI_VVFPCR_VFP_Pos)
10315#define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk
10316#define DSI_VVFPCR_VFP0_Pos (0U)
10317#define DSI_VVFPCR_VFP0_Msk (0x1UL << DSI_VVFPCR_VFP0_Pos)
10318#define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
10319#define DSI_VVFPCR_VFP1_Pos (1U)
10320#define DSI_VVFPCR_VFP1_Msk (0x1UL << DSI_VVFPCR_VFP1_Pos)
10321#define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
10322#define DSI_VVFPCR_VFP2_Pos (2U)
10323#define DSI_VVFPCR_VFP2_Msk (0x1UL << DSI_VVFPCR_VFP2_Pos)
10324#define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
10325#define DSI_VVFPCR_VFP3_Pos (3U)
10326#define DSI_VVFPCR_VFP3_Msk (0x1UL << DSI_VVFPCR_VFP3_Pos)
10327#define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
10328#define DSI_VVFPCR_VFP4_Pos (4U)
10329#define DSI_VVFPCR_VFP4_Msk (0x1UL << DSI_VVFPCR_VFP4_Pos)
10330#define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
10331#define DSI_VVFPCR_VFP5_Pos (5U)
10332#define DSI_VVFPCR_VFP5_Msk (0x1UL << DSI_VVFPCR_VFP5_Pos)
10333#define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
10334#define DSI_VVFPCR_VFP6_Pos (6U)
10335#define DSI_VVFPCR_VFP6_Msk (0x1UL << DSI_VVFPCR_VFP6_Pos)
10336#define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
10337#define DSI_VVFPCR_VFP7_Pos (7U)
10338#define DSI_VVFPCR_VFP7_Msk (0x1UL << DSI_VVFPCR_VFP7_Pos)
10339#define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
10340#define DSI_VVFPCR_VFP8_Pos (8U)
10341#define DSI_VVFPCR_VFP8_Msk (0x1UL << DSI_VVFPCR_VFP8_Pos)
10342#define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
10343#define DSI_VVFPCR_VFP9_Pos (9U)
10344#define DSI_VVFPCR_VFP9_Msk (0x1UL << DSI_VVFPCR_VFP9_Pos)
10345#define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
10346
10347/******************* Bit definition for DSI_VVACR register **************/
10348#define DSI_VVACR_VA_Pos (0U)
10349#define DSI_VVACR_VA_Msk (0x3FFFUL << DSI_VVACR_VA_Pos)
10350#define DSI_VVACR_VA DSI_VVACR_VA_Msk
10351#define DSI_VVACR_VA0_Pos (0U)
10352#define DSI_VVACR_VA0_Msk (0x1UL << DSI_VVACR_VA0_Pos)
10353#define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
10354#define DSI_VVACR_VA1_Pos (1U)
10355#define DSI_VVACR_VA1_Msk (0x1UL << DSI_VVACR_VA1_Pos)
10356#define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
10357#define DSI_VVACR_VA2_Pos (2U)
10358#define DSI_VVACR_VA2_Msk (0x1UL << DSI_VVACR_VA2_Pos)
10359#define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
10360#define DSI_VVACR_VA3_Pos (3U)
10361#define DSI_VVACR_VA3_Msk (0x1UL << DSI_VVACR_VA3_Pos)
10362#define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
10363#define DSI_VVACR_VA4_Pos (4U)
10364#define DSI_VVACR_VA4_Msk (0x1UL << DSI_VVACR_VA4_Pos)
10365#define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
10366#define DSI_VVACR_VA5_Pos (5U)
10367#define DSI_VVACR_VA5_Msk (0x1UL << DSI_VVACR_VA5_Pos)
10368#define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
10369#define DSI_VVACR_VA6_Pos (6U)
10370#define DSI_VVACR_VA6_Msk (0x1UL << DSI_VVACR_VA6_Pos)
10371#define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
10372#define DSI_VVACR_VA7_Pos (7U)
10373#define DSI_VVACR_VA7_Msk (0x1UL << DSI_VVACR_VA7_Pos)
10374#define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
10375#define DSI_VVACR_VA8_Pos (8U)
10376#define DSI_VVACR_VA8_Msk (0x1UL << DSI_VVACR_VA8_Pos)
10377#define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
10378#define DSI_VVACR_VA9_Pos (9U)
10379#define DSI_VVACR_VA9_Msk (0x1UL << DSI_VVACR_VA9_Pos)
10380#define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
10381#define DSI_VVACR_VA10_Pos (10U)
10382#define DSI_VVACR_VA10_Msk (0x1UL << DSI_VVACR_VA10_Pos)
10383#define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
10384#define DSI_VVACR_VA11_Pos (11U)
10385#define DSI_VVACR_VA11_Msk (0x1UL << DSI_VVACR_VA11_Pos)
10386#define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
10387#define DSI_VVACR_VA12_Pos (12U)
10388#define DSI_VVACR_VA12_Msk (0x1UL << DSI_VVACR_VA12_Pos)
10389#define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
10390#define DSI_VVACR_VA13_Pos (13U)
10391#define DSI_VVACR_VA13_Msk (0x1UL << DSI_VVACR_VA13_Pos)
10392#define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
10393
10394/******************* Bit definition for DSI_LCCR register ***************/
10395#define DSI_LCCR_CMDSIZE_Pos (0U)
10396#define DSI_LCCR_CMDSIZE_Msk (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos)
10397#define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk
10398#define DSI_LCCR_CMDSIZE0_Pos (0U)
10399#define DSI_LCCR_CMDSIZE0_Msk (0x1UL << DSI_LCCR_CMDSIZE0_Pos)
10400#define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
10401#define DSI_LCCR_CMDSIZE1_Pos (1U)
10402#define DSI_LCCR_CMDSIZE1_Msk (0x1UL << DSI_LCCR_CMDSIZE1_Pos)
10403#define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
10404#define DSI_LCCR_CMDSIZE2_Pos (2U)
10405#define DSI_LCCR_CMDSIZE2_Msk (0x1UL << DSI_LCCR_CMDSIZE2_Pos)
10406#define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
10407#define DSI_LCCR_CMDSIZE3_Pos (3U)
10408#define DSI_LCCR_CMDSIZE3_Msk (0x1UL << DSI_LCCR_CMDSIZE3_Pos)
10409#define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
10410#define DSI_LCCR_CMDSIZE4_Pos (4U)
10411#define DSI_LCCR_CMDSIZE4_Msk (0x1UL << DSI_LCCR_CMDSIZE4_Pos)
10412#define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
10413#define DSI_LCCR_CMDSIZE5_Pos (5U)
10414#define DSI_LCCR_CMDSIZE5_Msk (0x1UL << DSI_LCCR_CMDSIZE5_Pos)
10415#define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
10416#define DSI_LCCR_CMDSIZE6_Pos (6U)
10417#define DSI_LCCR_CMDSIZE6_Msk (0x1UL << DSI_LCCR_CMDSIZE6_Pos)
10418#define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
10419#define DSI_LCCR_CMDSIZE7_Pos (7U)
10420#define DSI_LCCR_CMDSIZE7_Msk (0x1UL << DSI_LCCR_CMDSIZE7_Pos)
10421#define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
10422#define DSI_LCCR_CMDSIZE8_Pos (8U)
10423#define DSI_LCCR_CMDSIZE8_Msk (0x1UL << DSI_LCCR_CMDSIZE8_Pos)
10424#define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
10425#define DSI_LCCR_CMDSIZE9_Pos (9U)
10426#define DSI_LCCR_CMDSIZE9_Msk (0x1UL << DSI_LCCR_CMDSIZE9_Pos)
10427#define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
10428#define DSI_LCCR_CMDSIZE10_Pos (10U)
10429#define DSI_LCCR_CMDSIZE10_Msk (0x1UL << DSI_LCCR_CMDSIZE10_Pos)
10430#define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
10431#define DSI_LCCR_CMDSIZE11_Pos (11U)
10432#define DSI_LCCR_CMDSIZE11_Msk (0x1UL << DSI_LCCR_CMDSIZE11_Pos)
10433#define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
10434#define DSI_LCCR_CMDSIZE12_Pos (12U)
10435#define DSI_LCCR_CMDSIZE12_Msk (0x1UL << DSI_LCCR_CMDSIZE12_Pos)
10436#define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
10437#define DSI_LCCR_CMDSIZE13_Pos (13U)
10438#define DSI_LCCR_CMDSIZE13_Msk (0x1UL << DSI_LCCR_CMDSIZE13_Pos)
10439#define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
10440#define DSI_LCCR_CMDSIZE14_Pos (14U)
10441#define DSI_LCCR_CMDSIZE14_Msk (0x1UL << DSI_LCCR_CMDSIZE14_Pos)
10442#define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
10443#define DSI_LCCR_CMDSIZE15_Pos (15U)
10444#define DSI_LCCR_CMDSIZE15_Msk (0x1UL << DSI_LCCR_CMDSIZE15_Pos)
10445#define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
10446
10447/******************* Bit definition for DSI_CMCR register ***************/
10448#define DSI_CMCR_TEARE_Pos (0U)
10449#define DSI_CMCR_TEARE_Msk (0x1UL << DSI_CMCR_TEARE_Pos)
10450#define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk
10451#define DSI_CMCR_ARE_Pos (1U)
10452#define DSI_CMCR_ARE_Msk (0x1UL << DSI_CMCR_ARE_Pos)
10453#define DSI_CMCR_ARE DSI_CMCR_ARE_Msk
10454#define DSI_CMCR_GSW0TX_Pos (8U)
10455#define DSI_CMCR_GSW0TX_Msk (0x1UL << DSI_CMCR_GSW0TX_Pos)
10456#define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk
10457#define DSI_CMCR_GSW1TX_Pos (9U)
10458#define DSI_CMCR_GSW1TX_Msk (0x1UL << DSI_CMCR_GSW1TX_Pos)
10459#define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk
10460#define DSI_CMCR_GSW2TX_Pos (10U)
10461#define DSI_CMCR_GSW2TX_Msk (0x1UL << DSI_CMCR_GSW2TX_Pos)
10462#define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk
10463#define DSI_CMCR_GSR0TX_Pos (11U)
10464#define DSI_CMCR_GSR0TX_Msk (0x1UL << DSI_CMCR_GSR0TX_Pos)
10465#define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk
10466#define DSI_CMCR_GSR1TX_Pos (12U)
10467#define DSI_CMCR_GSR1TX_Msk (0x1UL << DSI_CMCR_GSR1TX_Pos)
10468#define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk
10469#define DSI_CMCR_GSR2TX_Pos (13U)
10470#define DSI_CMCR_GSR2TX_Msk (0x1UL << DSI_CMCR_GSR2TX_Pos)
10471#define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk
10472#define DSI_CMCR_GLWTX_Pos (14U)
10473#define DSI_CMCR_GLWTX_Msk (0x1UL << DSI_CMCR_GLWTX_Pos)
10474#define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk
10475#define DSI_CMCR_DSW0TX_Pos (16U)
10476#define DSI_CMCR_DSW0TX_Msk (0x1UL << DSI_CMCR_DSW0TX_Pos)
10477#define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk
10478#define DSI_CMCR_DSW1TX_Pos (17U)
10479#define DSI_CMCR_DSW1TX_Msk (0x1UL << DSI_CMCR_DSW1TX_Pos)
10480#define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk
10481#define DSI_CMCR_DSR0TX_Pos (18U)
10482#define DSI_CMCR_DSR0TX_Msk (0x1UL << DSI_CMCR_DSR0TX_Pos)
10483#define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk
10484#define DSI_CMCR_DLWTX_Pos (19U)
10485#define DSI_CMCR_DLWTX_Msk (0x1UL << DSI_CMCR_DLWTX_Pos)
10486#define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk
10487#define DSI_CMCR_MRDPS_Pos (24U)
10488#define DSI_CMCR_MRDPS_Msk (0x1UL << DSI_CMCR_MRDPS_Pos)
10489#define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk
10491/******************* Bit definition for DSI_GHCR register ***************/
10492#define DSI_GHCR_DT_Pos (0U)
10493#define DSI_GHCR_DT_Msk (0x3FUL << DSI_GHCR_DT_Pos)
10494#define DSI_GHCR_DT DSI_GHCR_DT_Msk
10495#define DSI_GHCR_DT0_Pos (0U)
10496#define DSI_GHCR_DT0_Msk (0x1UL << DSI_GHCR_DT0_Pos)
10497#define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
10498#define DSI_GHCR_DT1_Pos (1U)
10499#define DSI_GHCR_DT1_Msk (0x1UL << DSI_GHCR_DT1_Pos)
10500#define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
10501#define DSI_GHCR_DT2_Pos (2U)
10502#define DSI_GHCR_DT2_Msk (0x1UL << DSI_GHCR_DT2_Pos)
10503#define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
10504#define DSI_GHCR_DT3_Pos (3U)
10505#define DSI_GHCR_DT3_Msk (0x1UL << DSI_GHCR_DT3_Pos)
10506#define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
10507#define DSI_GHCR_DT4_Pos (4U)
10508#define DSI_GHCR_DT4_Msk (0x1UL << DSI_GHCR_DT4_Pos)
10509#define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
10510#define DSI_GHCR_DT5_Pos (5U)
10511#define DSI_GHCR_DT5_Msk (0x1UL << DSI_GHCR_DT5_Pos)
10512#define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
10513
10514#define DSI_GHCR_VCID_Pos (6U)
10515#define DSI_GHCR_VCID_Msk (0x3UL << DSI_GHCR_VCID_Pos)
10516#define DSI_GHCR_VCID DSI_GHCR_VCID_Msk
10517#define DSI_GHCR_VCID0_Pos (6U)
10518#define DSI_GHCR_VCID0_Msk (0x1UL << DSI_GHCR_VCID0_Pos)
10519#define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
10520#define DSI_GHCR_VCID1_Pos (7U)
10521#define DSI_GHCR_VCID1_Msk (0x1UL << DSI_GHCR_VCID1_Pos)
10522#define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
10523
10524#define DSI_GHCR_WCLSB_Pos (8U)
10525#define DSI_GHCR_WCLSB_Msk (0xFFUL << DSI_GHCR_WCLSB_Pos)
10526#define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk
10527#define DSI_GHCR_WCLSB0_Pos (8U)
10528#define DSI_GHCR_WCLSB0_Msk (0x1UL << DSI_GHCR_WCLSB0_Pos)
10529#define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
10530#define DSI_GHCR_WCLSB1_Pos (9U)
10531#define DSI_GHCR_WCLSB1_Msk (0x1UL << DSI_GHCR_WCLSB1_Pos)
10532#define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
10533#define DSI_GHCR_WCLSB2_Pos (10U)
10534#define DSI_GHCR_WCLSB2_Msk (0x1UL << DSI_GHCR_WCLSB2_Pos)
10535#define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
10536#define DSI_GHCR_WCLSB3_Pos (11U)
10537#define DSI_GHCR_WCLSB3_Msk (0x1UL << DSI_GHCR_WCLSB3_Pos)
10538#define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
10539#define DSI_GHCR_WCLSB4_Pos (12U)
10540#define DSI_GHCR_WCLSB4_Msk (0x1UL << DSI_GHCR_WCLSB4_Pos)
10541#define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
10542#define DSI_GHCR_WCLSB5_Pos (13U)
10543#define DSI_GHCR_WCLSB5_Msk (0x1UL << DSI_GHCR_WCLSB5_Pos)
10544#define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
10545#define DSI_GHCR_WCLSB6_Pos (14U)
10546#define DSI_GHCR_WCLSB6_Msk (0x1UL << DSI_GHCR_WCLSB6_Pos)
10547#define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
10548#define DSI_GHCR_WCLSB7_Pos (15U)
10549#define DSI_GHCR_WCLSB7_Msk (0x1UL << DSI_GHCR_WCLSB7_Pos)
10550#define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
10551
10552#define DSI_GHCR_WCMSB_Pos (16U)
10553#define DSI_GHCR_WCMSB_Msk (0xFFUL << DSI_GHCR_WCMSB_Pos)
10554#define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk
10555#define DSI_GHCR_WCMSB0_Pos (16U)
10556#define DSI_GHCR_WCMSB0_Msk (0x1UL << DSI_GHCR_WCMSB0_Pos)
10557#define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
10558#define DSI_GHCR_WCMSB1_Pos (17U)
10559#define DSI_GHCR_WCMSB1_Msk (0x1UL << DSI_GHCR_WCMSB1_Pos)
10560#define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
10561#define DSI_GHCR_WCMSB2_Pos (18U)
10562#define DSI_GHCR_WCMSB2_Msk (0x1UL << DSI_GHCR_WCMSB2_Pos)
10563#define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
10564#define DSI_GHCR_WCMSB3_Pos (19U)
10565#define DSI_GHCR_WCMSB3_Msk (0x1UL << DSI_GHCR_WCMSB3_Pos)
10566#define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
10567#define DSI_GHCR_WCMSB4_Pos (20U)
10568#define DSI_GHCR_WCMSB4_Msk (0x1UL << DSI_GHCR_WCMSB4_Pos)
10569#define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
10570#define DSI_GHCR_WCMSB5_Pos (21U)
10571#define DSI_GHCR_WCMSB5_Msk (0x1UL << DSI_GHCR_WCMSB5_Pos)
10572#define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
10573#define DSI_GHCR_WCMSB6_Pos (22U)
10574#define DSI_GHCR_WCMSB6_Msk (0x1UL << DSI_GHCR_WCMSB6_Pos)
10575#define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
10576#define DSI_GHCR_WCMSB7_Pos (23U)
10577#define DSI_GHCR_WCMSB7_Msk (0x1UL << DSI_GHCR_WCMSB7_Pos)
10578#define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
10579
10580/******************* Bit definition for DSI_GPDR register ***************/
10581#define DSI_GPDR_DATA1_Pos (0U)
10582#define DSI_GPDR_DATA1_Msk (0xFFUL << DSI_GPDR_DATA1_Pos)
10583#define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk
10584#define DSI_GPDR_DATA1_0 (0x01UL << DSI_GPDR_DATA1_Pos)
10585#define DSI_GPDR_DATA1_1 (0x02UL << DSI_GPDR_DATA1_Pos)
10586#define DSI_GPDR_DATA1_2 (0x04UL << DSI_GPDR_DATA1_Pos)
10587#define DSI_GPDR_DATA1_3 (0x08UL << DSI_GPDR_DATA1_Pos)
10588#define DSI_GPDR_DATA1_4 (0x10UL << DSI_GPDR_DATA1_Pos)
10589#define DSI_GPDR_DATA1_5 (0x20UL << DSI_GPDR_DATA1_Pos)
10590#define DSI_GPDR_DATA1_6 (0x40UL << DSI_GPDR_DATA1_Pos)
10591#define DSI_GPDR_DATA1_7 (0x80UL << DSI_GPDR_DATA1_Pos)
10593#define DSI_GPDR_DATA2_Pos (8U)
10594#define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos)
10595#define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk
10596#define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos)
10597#define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos)
10598#define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos)
10599#define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos)
10600#define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos)
10601#define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos)
10602#define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos)
10603#define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos)
10605#define DSI_GPDR_DATA3_Pos (16U)
10606#define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos)
10607#define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk
10608#define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos)
10609#define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos)
10610#define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos)
10611#define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos)
10612#define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos)
10613#define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos)
10614#define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos)
10615#define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos)
10617#define DSI_GPDR_DATA4_Pos (24U)
10618#define DSI_GPDR_DATA4_Msk (0xFFUL << DSI_GPDR_DATA4_Pos)
10619#define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk
10620#define DSI_GPDR_DATA4_0 (0x01UL << DSI_GPDR_DATA4_Pos)
10621#define DSI_GPDR_DATA4_1 (0x02UL << DSI_GPDR_DATA4_Pos)
10622#define DSI_GPDR_DATA4_2 (0x04UL << DSI_GPDR_DATA4_Pos)
10623#define DSI_GPDR_DATA4_3 (0x08UL << DSI_GPDR_DATA4_Pos)
10624#define DSI_GPDR_DATA4_4 (0x10UL << DSI_GPDR_DATA4_Pos)
10625#define DSI_GPDR_DATA4_5 (0x20UL << DSI_GPDR_DATA4_Pos)
10626#define DSI_GPDR_DATA4_6 (0x40UL << DSI_GPDR_DATA4_Pos)
10627#define DSI_GPDR_DATA4_7 (0x80UL << DSI_GPDR_DATA4_Pos)
10629/******************* Bit definition for DSI_GPSR register ***************/
10630#define DSI_GPSR_CMDFE_Pos (0U)
10631#define DSI_GPSR_CMDFE_Msk (0x1UL << DSI_GPSR_CMDFE_Pos)
10632#define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk
10633#define DSI_GPSR_CMDFF_Pos (1U)
10634#define DSI_GPSR_CMDFF_Msk (0x1UL << DSI_GPSR_CMDFF_Pos)
10635#define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk
10636#define DSI_GPSR_PWRFE_Pos (2U)
10637#define DSI_GPSR_PWRFE_Msk (0x1UL << DSI_GPSR_PWRFE_Pos)
10638#define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk
10639#define DSI_GPSR_PWRFF_Pos (3U)
10640#define DSI_GPSR_PWRFF_Msk (0x1UL << DSI_GPSR_PWRFF_Pos)
10641#define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk
10642#define DSI_GPSR_PRDFE_Pos (4U)
10643#define DSI_GPSR_PRDFE_Msk (0x1UL << DSI_GPSR_PRDFE_Pos)
10644#define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk
10645#define DSI_GPSR_PRDFF_Pos (5U)
10646#define DSI_GPSR_PRDFF_Msk (0x1UL << DSI_GPSR_PRDFF_Pos)
10647#define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk
10648#define DSI_GPSR_RCB_Pos (6U)
10649#define DSI_GPSR_RCB_Msk (0x1UL << DSI_GPSR_RCB_Pos)
10650#define DSI_GPSR_RCB DSI_GPSR_RCB_Msk
10652/******************* Bit definition for DSI_TCCR0 register **************/
10653#define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
10654#define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos)
10655#define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk
10656#define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
10657#define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos)
10658#define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
10659#define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
10660#define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos)
10661#define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
10662#define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
10663#define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos)
10664#define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
10665#define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
10666#define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos)
10667#define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
10668#define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
10669#define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos)
10670#define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
10671#define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
10672#define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos)
10673#define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
10674#define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
10675#define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos)
10676#define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
10677#define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
10678#define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos)
10679#define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
10680#define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
10681#define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos)
10682#define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
10683#define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
10684#define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos)
10685#define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
10686#define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
10687#define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos)
10688#define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
10689#define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
10690#define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos)
10691#define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
10692#define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
10693#define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos)
10694#define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
10695#define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
10696#define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos)
10697#define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
10698#define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
10699#define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos)
10700#define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
10701#define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
10702#define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos)
10703#define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
10704
10705#define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
10706#define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos)
10707#define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk
10708#define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
10709#define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos)
10710#define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
10711#define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
10712#define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos)
10713#define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
10714#define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
10715#define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos)
10716#define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
10717#define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
10718#define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos)
10719#define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
10720#define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
10721#define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos)
10722#define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
10723#define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
10724#define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos)
10725#define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
10726#define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
10727#define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos)
10728#define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
10729#define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
10730#define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos)
10731#define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
10732#define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
10733#define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos)
10734#define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
10735#define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
10736#define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos)
10737#define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
10738#define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
10739#define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos)
10740#define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
10741#define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
10742#define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos)
10743#define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
10744#define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
10745#define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos)
10746#define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
10747#define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
10748#define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos)
10749#define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
10750#define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
10751#define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos)
10752#define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
10753#define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
10754#define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos)
10755#define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
10756
10757/******************* Bit definition for DSI_TCCR1 register **************/
10758#define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
10759#define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos)
10760#define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk
10761#define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
10762#define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos)
10763#define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
10764#define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
10765#define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos)
10766#define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
10767#define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
10768#define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos)
10769#define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
10770#define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
10771#define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos)
10772#define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
10773#define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
10774#define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos)
10775#define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
10776#define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
10777#define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos)
10778#define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
10779#define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
10780#define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos)
10781#define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
10782#define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
10783#define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos)
10784#define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
10785#define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
10786#define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos)
10787#define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
10788#define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
10789#define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos)
10790#define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
10791#define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
10792#define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos)
10793#define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
10794#define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
10795#define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos)
10796#define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
10797#define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
10798#define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos)
10799#define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
10800#define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
10801#define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos)
10802#define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
10803#define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
10804#define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos)
10805#define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
10806#define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
10807#define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos)
10808#define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
10809
10810/******************* Bit definition for DSI_TCCR2 register **************/
10811#define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
10812#define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos)
10813#define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk
10814#define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
10815#define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos)
10816#define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
10817#define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
10818#define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos)
10819#define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
10820#define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
10821#define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos)
10822#define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
10823#define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
10824#define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos)
10825#define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
10826#define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
10827#define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos)
10828#define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
10829#define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
10830#define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos)
10831#define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
10832#define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
10833#define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos)
10834#define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
10835#define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
10836#define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos)
10837#define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
10838#define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
10839#define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos)
10840#define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
10841#define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
10842#define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos)
10843#define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
10844#define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
10845#define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos)
10846#define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
10847#define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
10848#define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos)
10849#define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
10850#define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
10851#define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos)
10852#define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
10853#define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
10854#define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos)
10855#define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
10856#define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
10857#define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos)
10858#define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
10859#define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
10860#define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos)
10861#define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
10862
10863/******************* Bit definition for DSI_TCCR3 register **************/
10864#define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
10865#define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos)
10866#define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk
10867#define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
10868#define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos)
10869#define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
10870#define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
10871#define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos)
10872#define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
10873#define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
10874#define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos)
10875#define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
10876#define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
10877#define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos)
10878#define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
10879#define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
10880#define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos)
10881#define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
10882#define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
10883#define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos)
10884#define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
10885#define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
10886#define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos)
10887#define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
10888#define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
10889#define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos)
10890#define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
10891#define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
10892#define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos)
10893#define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
10894#define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
10895#define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos)
10896#define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
10897#define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
10898#define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos)
10899#define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
10900#define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
10901#define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos)
10902#define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
10903#define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
10904#define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos)
10905#define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
10906#define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
10907#define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos)
10908#define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
10909#define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
10910#define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos)
10911#define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
10912#define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
10913#define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos)
10914#define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
10915
10916#define DSI_TCCR3_PM_Pos (24U)
10917#define DSI_TCCR3_PM_Msk (0x1UL << DSI_TCCR3_PM_Pos)
10918#define DSI_TCCR3_PM DSI_TCCR3_PM_Msk
10920/******************* Bit definition for DSI_TCCR4 register **************/
10921#define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
10922#define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos)
10923#define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk
10924#define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
10925#define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos)
10926#define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
10927#define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
10928#define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos)
10929#define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
10930#define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
10931#define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos)
10932#define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
10933#define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
10934#define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos)
10935#define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
10936#define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
10937#define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos)
10938#define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
10939#define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
10940#define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos)
10941#define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
10942#define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
10943#define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos)
10944#define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
10945#define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
10946#define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos)
10947#define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
10948#define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
10949#define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos)
10950#define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
10951#define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
10952#define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos)
10953#define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
10954#define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
10955#define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos)
10956#define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
10957#define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
10958#define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos)
10959#define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
10960#define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
10961#define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos)
10962#define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
10963#define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
10964#define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos)
10965#define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
10966#define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
10967#define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos)
10968#define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
10969#define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
10970#define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos)
10971#define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
10972
10973/******************* Bit definition for DSI_TCCR5 register **************/
10974#define DSI_TCCR5_BTA_TOCNT_Pos (0U)
10975#define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos)
10976#define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk
10977#define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
10978#define DSI_TCCR5_BTA_TOCNT0_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos)
10979#define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
10980#define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
10981#define DSI_TCCR5_BTA_TOCNT1_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos)
10982#define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
10983#define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
10984#define DSI_TCCR5_BTA_TOCNT2_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos)
10985#define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
10986#define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
10987#define DSI_TCCR5_BTA_TOCNT3_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos)
10988#define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
10989#define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
10990#define DSI_TCCR5_BTA_TOCNT4_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos)
10991#define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
10992#define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
10993#define DSI_TCCR5_BTA_TOCNT5_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos)
10994#define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
10995#define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
10996#define DSI_TCCR5_BTA_TOCNT6_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos)
10997#define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
10998#define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
10999#define DSI_TCCR5_BTA_TOCNT7_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos)
11000#define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
11001#define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
11002#define DSI_TCCR5_BTA_TOCNT8_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos)
11003#define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
11004#define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
11005#define DSI_TCCR5_BTA_TOCNT9_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos)
11006#define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
11007#define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
11008#define DSI_TCCR5_BTA_TOCNT10_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos)
11009#define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
11010#define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
11011#define DSI_TCCR5_BTA_TOCNT11_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos)
11012#define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
11013#define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
11014#define DSI_TCCR5_BTA_TOCNT12_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos)
11015#define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
11016#define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
11017#define DSI_TCCR5_BTA_TOCNT13_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos)
11018#define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
11019#define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
11020#define DSI_TCCR5_BTA_TOCNT14_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos)
11021#define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
11022#define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
11023#define DSI_TCCR5_BTA_TOCNT15_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos)
11024#define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
11025
11026/******************* Bit definition for DSI_TDCR register ***************/
11027#define DSI_TDCR_3DM (0x00000003U)
11028#define DSI_TDCR_3DM0 (0x00000001U)
11029#define DSI_TDCR_3DM1 (0x00000002U)
11030
11031#define DSI_TDCR_3DF (0x0000000CU)
11032#define DSI_TDCR_3DF0 (0x00000004U)
11033#define DSI_TDCR_3DF1 (0x00000008U)
11034
11035#define DSI_TDCR_SVS_Pos (4U)
11036#define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos)
11037#define DSI_TDCR_SVS DSI_TDCR_SVS_Msk
11038#define DSI_TDCR_RF_Pos (5U)
11039#define DSI_TDCR_RF_Msk (0x1UL << DSI_TDCR_RF_Pos)
11040#define DSI_TDCR_RF DSI_TDCR_RF_Msk
11041#define DSI_TDCR_S3DC_Pos (16U)
11042#define DSI_TDCR_S3DC_Msk (0x1UL << DSI_TDCR_S3DC_Pos)
11043#define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk
11045/******************* Bit definition for DSI_CLCR register ***************/
11046#define DSI_CLCR_DPCC_Pos (0U)
11047#define DSI_CLCR_DPCC_Msk (0x1UL << DSI_CLCR_DPCC_Pos)
11048#define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk
11049#define DSI_CLCR_ACR_Pos (1U)
11050#define DSI_CLCR_ACR_Msk (0x1UL << DSI_CLCR_ACR_Pos)
11051#define DSI_CLCR_ACR DSI_CLCR_ACR_Msk
11053/******************* Bit definition for DSI_CLTCR register **************/
11054#define DSI_CLTCR_LP2HS_TIME_Pos (0U)
11055#define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos)
11056#define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk
11057#define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
11058#define DSI_CLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos)
11059#define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
11060#define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
11061#define DSI_CLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos)
11062#define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
11063#define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
11064#define DSI_CLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos)
11065#define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
11066#define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
11067#define DSI_CLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos)
11068#define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
11069#define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
11070#define DSI_CLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos)
11071#define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
11072#define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
11073#define DSI_CLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos)
11074#define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
11075#define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
11076#define DSI_CLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos)
11077#define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
11078#define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
11079#define DSI_CLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos)
11080#define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
11081#define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
11082#define DSI_CLTCR_LP2HS_TIME8_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos)
11083#define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
11084#define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
11085#define DSI_CLTCR_LP2HS_TIME9_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos)
11086#define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
11087
11088#define DSI_CLTCR_HS2LP_TIME_Pos (16U)
11089#define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos)
11090#define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk
11091#define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
11092#define DSI_CLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos)
11093#define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
11094#define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
11095#define DSI_CLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos)
11096#define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
11097#define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
11098#define DSI_CLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos)
11099#define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
11100#define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
11101#define DSI_CLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos)
11102#define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
11103#define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
11104#define DSI_CLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos)
11105#define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
11106#define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
11107#define DSI_CLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos)
11108#define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
11109#define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
11110#define DSI_CLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos)
11111#define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
11112#define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
11113#define DSI_CLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos)
11114#define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
11115#define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
11116#define DSI_CLTCR_HS2LP_TIME8_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos)
11117#define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
11118#define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
11119#define DSI_CLTCR_HS2LP_TIME9_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos)
11120#define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
11121
11122/******************* Bit definition for DSI_DLTCR register **************/
11123#define DSI_DLTCR_MRD_TIME_Pos (0U)
11124#define DSI_DLTCR_MRD_TIME_Msk (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos)
11125#define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk
11126#define DSI_DLTCR_MRD_TIME0_Pos (0U)
11127#define DSI_DLTCR_MRD_TIME0_Msk (0x1UL << DSI_DLTCR_MRD_TIME0_Pos)
11128#define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
11129#define DSI_DLTCR_MRD_TIME1_Pos (1U)
11130#define DSI_DLTCR_MRD_TIME1_Msk (0x1UL << DSI_DLTCR_MRD_TIME1_Pos)
11131#define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
11132#define DSI_DLTCR_MRD_TIME2_Pos (2U)
11133#define DSI_DLTCR_MRD_TIME2_Msk (0x1UL << DSI_DLTCR_MRD_TIME2_Pos)
11134#define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
11135#define DSI_DLTCR_MRD_TIME3_Pos (3U)
11136#define DSI_DLTCR_MRD_TIME3_Msk (0x1UL << DSI_DLTCR_MRD_TIME3_Pos)
11137#define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
11138#define DSI_DLTCR_MRD_TIME4_Pos (4U)
11139#define DSI_DLTCR_MRD_TIME4_Msk (0x1UL << DSI_DLTCR_MRD_TIME4_Pos)
11140#define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
11141#define DSI_DLTCR_MRD_TIME5_Pos (5U)
11142#define DSI_DLTCR_MRD_TIME5_Msk (0x1UL << DSI_DLTCR_MRD_TIME5_Pos)
11143#define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
11144#define DSI_DLTCR_MRD_TIME6_Pos (6U)
11145#define DSI_DLTCR_MRD_TIME6_Msk (0x1UL << DSI_DLTCR_MRD_TIME6_Pos)
11146#define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
11147#define DSI_DLTCR_MRD_TIME7_Pos (7U)
11148#define DSI_DLTCR_MRD_TIME7_Msk (0x1UL << DSI_DLTCR_MRD_TIME7_Pos)
11149#define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
11150#define DSI_DLTCR_MRD_TIME8_Pos (8U)
11151#define DSI_DLTCR_MRD_TIME8_Msk (0x1UL << DSI_DLTCR_MRD_TIME8_Pos)
11152#define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
11153#define DSI_DLTCR_MRD_TIME9_Pos (9U)
11154#define DSI_DLTCR_MRD_TIME9_Msk (0x1UL << DSI_DLTCR_MRD_TIME9_Pos)
11155#define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
11156#define DSI_DLTCR_MRD_TIME10_Pos (10U)
11157#define DSI_DLTCR_MRD_TIME10_Msk (0x1UL << DSI_DLTCR_MRD_TIME10_Pos)
11158#define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
11159#define DSI_DLTCR_MRD_TIME11_Pos (11U)
11160#define DSI_DLTCR_MRD_TIME11_Msk (0x1UL << DSI_DLTCR_MRD_TIME11_Pos)
11161#define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
11162#define DSI_DLTCR_MRD_TIME12_Pos (12U)
11163#define DSI_DLTCR_MRD_TIME12_Msk (0x1UL << DSI_DLTCR_MRD_TIME12_Pos)
11164#define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
11165#define DSI_DLTCR_MRD_TIME13_Pos (13U)
11166#define DSI_DLTCR_MRD_TIME13_Msk (0x1UL << DSI_DLTCR_MRD_TIME13_Pos)
11167#define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
11168#define DSI_DLTCR_MRD_TIME14_Pos (14U)
11169#define DSI_DLTCR_MRD_TIME14_Msk (0x1UL << DSI_DLTCR_MRD_TIME14_Pos)
11170#define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
11171
11172#define DSI_DLTCR_LP2HS_TIME_Pos (16U)
11173#define DSI_DLTCR_LP2HS_TIME_Msk (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos)
11174#define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk
11175#define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
11176#define DSI_DLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos)
11177#define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
11178#define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
11179#define DSI_DLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos)
11180#define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
11181#define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
11182#define DSI_DLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos)
11183#define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
11184#define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
11185#define DSI_DLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos)
11186#define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
11187#define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
11188#define DSI_DLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos)
11189#define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
11190#define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
11191#define DSI_DLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos)
11192#define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
11193#define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
11194#define DSI_DLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos)
11195#define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
11196#define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
11197#define DSI_DLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos)
11198#define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
11199
11200#define DSI_DLTCR_HS2LP_TIME_Pos (24U)
11201#define DSI_DLTCR_HS2LP_TIME_Msk (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos)
11202#define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk
11203#define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
11204#define DSI_DLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos)
11205#define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
11206#define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
11207#define DSI_DLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos)
11208#define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
11209#define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
11210#define DSI_DLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos)
11211#define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
11212#define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
11213#define DSI_DLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos)
11214#define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
11215#define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
11216#define DSI_DLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos)
11217#define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
11218#define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
11219#define DSI_DLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos)
11220#define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
11221#define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
11222#define DSI_DLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos)
11223#define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
11224#define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
11225#define DSI_DLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos)
11226#define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
11227
11228/******************* Bit definition for DSI_PCTLR register **************/
11229#define DSI_PCTLR_DEN_Pos (1U)
11230#define DSI_PCTLR_DEN_Msk (0x1UL << DSI_PCTLR_DEN_Pos)
11231#define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk
11232#define DSI_PCTLR_CKE_Pos (2U)
11233#define DSI_PCTLR_CKE_Msk (0x1UL << DSI_PCTLR_CKE_Pos)
11234#define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk
11236/******************* Bit definition for DSI_PCONFR register *************/
11237#define DSI_PCONFR_NL_Pos (0U)
11238#define DSI_PCONFR_NL_Msk (0x3UL << DSI_PCONFR_NL_Pos)
11239#define DSI_PCONFR_NL DSI_PCONFR_NL_Msk
11240#define DSI_PCONFR_NL0_Pos (0U)
11241#define DSI_PCONFR_NL0_Msk (0x1UL << DSI_PCONFR_NL0_Pos)
11242#define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
11243#define DSI_PCONFR_NL1_Pos (1U)
11244#define DSI_PCONFR_NL1_Msk (0x1UL << DSI_PCONFR_NL1_Pos)
11245#define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
11246
11247#define DSI_PCONFR_SW_TIME_Pos (8U)
11248#define DSI_PCONFR_SW_TIME_Msk (0xFFUL << DSI_PCONFR_SW_TIME_Pos)
11249#define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk
11250#define DSI_PCONFR_SW_TIME0_Pos (8U)
11251#define DSI_PCONFR_SW_TIME0_Msk (0x1UL << DSI_PCONFR_SW_TIME0_Pos)
11252#define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
11253#define DSI_PCONFR_SW_TIME1_Pos (9U)
11254#define DSI_PCONFR_SW_TIME1_Msk (0x1UL << DSI_PCONFR_SW_TIME1_Pos)
11255#define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
11256#define DSI_PCONFR_SW_TIME2_Pos (10U)
11257#define DSI_PCONFR_SW_TIME2_Msk (0x1UL << DSI_PCONFR_SW_TIME2_Pos)
11258#define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
11259#define DSI_PCONFR_SW_TIME3_Pos (11U)
11260#define DSI_PCONFR_SW_TIME3_Msk (0x1UL << DSI_PCONFR_SW_TIME3_Pos)
11261#define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
11262#define DSI_PCONFR_SW_TIME4_Pos (12U)
11263#define DSI_PCONFR_SW_TIME4_Msk (0x1UL << DSI_PCONFR_SW_TIME4_Pos)
11264#define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
11265#define DSI_PCONFR_SW_TIME5_Pos (13U)
11266#define DSI_PCONFR_SW_TIME5_Msk (0x1UL << DSI_PCONFR_SW_TIME5_Pos)
11267#define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
11268#define DSI_PCONFR_SW_TIME6_Pos (14U)
11269#define DSI_PCONFR_SW_TIME6_Msk (0x1UL << DSI_PCONFR_SW_TIME6_Pos)
11270#define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
11271#define DSI_PCONFR_SW_TIME7_Pos (15U)
11272#define DSI_PCONFR_SW_TIME7_Msk (0x1UL << DSI_PCONFR_SW_TIME7_Pos)
11273#define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
11274
11275/******************* Bit definition for DSI_PUCR register ***************/
11276#define DSI_PUCR_URCL_Pos (0U)
11277#define DSI_PUCR_URCL_Msk (0x1UL << DSI_PUCR_URCL_Pos)
11278#define DSI_PUCR_URCL DSI_PUCR_URCL_Msk
11279#define DSI_PUCR_UECL_Pos (1U)
11280#define DSI_PUCR_UECL_Msk (0x1UL << DSI_PUCR_UECL_Pos)
11281#define DSI_PUCR_UECL DSI_PUCR_UECL_Msk
11282#define DSI_PUCR_URDL_Pos (2U)
11283#define DSI_PUCR_URDL_Msk (0x1UL << DSI_PUCR_URDL_Pos)
11284#define DSI_PUCR_URDL DSI_PUCR_URDL_Msk
11285#define DSI_PUCR_UEDL_Pos (3U)
11286#define DSI_PUCR_UEDL_Msk (0x1UL << DSI_PUCR_UEDL_Pos)
11287#define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk
11289/******************* Bit definition for DSI_PTTCR register **************/
11290#define DSI_PTTCR_TX_TRIG_Pos (0U)
11291#define DSI_PTTCR_TX_TRIG_Msk (0xFUL << DSI_PTTCR_TX_TRIG_Pos)
11292#define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk
11293#define DSI_PTTCR_TX_TRIG0_Pos (0U)
11294#define DSI_PTTCR_TX_TRIG0_Msk (0x1UL << DSI_PTTCR_TX_TRIG0_Pos)
11295#define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
11296#define DSI_PTTCR_TX_TRIG1_Pos (1U)
11297#define DSI_PTTCR_TX_TRIG1_Msk (0x1UL << DSI_PTTCR_TX_TRIG1_Pos)
11298#define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
11299#define DSI_PTTCR_TX_TRIG2_Pos (2U)
11300#define DSI_PTTCR_TX_TRIG2_Msk (0x1UL << DSI_PTTCR_TX_TRIG2_Pos)
11301#define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
11302#define DSI_PTTCR_TX_TRIG3_Pos (3U)
11303#define DSI_PTTCR_TX_TRIG3_Msk (0x1UL << DSI_PTTCR_TX_TRIG3_Pos)
11304#define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
11305
11306/******************* Bit definition for DSI_PSR register ****************/
11307#define DSI_PSR_PD_Pos (1U)
11308#define DSI_PSR_PD_Msk (0x1UL << DSI_PSR_PD_Pos)
11309#define DSI_PSR_PD DSI_PSR_PD_Msk
11310#define DSI_PSR_PSSC_Pos (2U)
11311#define DSI_PSR_PSSC_Msk (0x1UL << DSI_PSR_PSSC_Pos)
11312#define DSI_PSR_PSSC DSI_PSR_PSSC_Msk
11313#define DSI_PSR_UANC_Pos (3U)
11314#define DSI_PSR_UANC_Msk (0x1UL << DSI_PSR_UANC_Pos)
11315#define DSI_PSR_UANC DSI_PSR_UANC_Msk
11316#define DSI_PSR_PSS0_Pos (4U)
11317#define DSI_PSR_PSS0_Msk (0x1UL << DSI_PSR_PSS0_Pos)
11318#define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk
11319#define DSI_PSR_UAN0_Pos (5U)
11320#define DSI_PSR_UAN0_Msk (0x1UL << DSI_PSR_UAN0_Pos)
11321#define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk
11322#define DSI_PSR_RUE0_Pos (6U)
11323#define DSI_PSR_RUE0_Msk (0x1UL << DSI_PSR_RUE0_Pos)
11324#define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk
11325#define DSI_PSR_PSS1_Pos (7U)
11326#define DSI_PSR_PSS1_Msk (0x1UL << DSI_PSR_PSS1_Pos)
11327#define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk
11328#define DSI_PSR_UAN1_Pos (8U)
11329#define DSI_PSR_UAN1_Msk (0x1UL << DSI_PSR_UAN1_Pos)
11330#define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk
11332/******************* Bit definition for DSI_ISR0 register ***************/
11333#define DSI_ISR0_AE0_Pos (0U)
11334#define DSI_ISR0_AE0_Msk (0x1UL << DSI_ISR0_AE0_Pos)
11335#define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk
11336#define DSI_ISR0_AE1_Pos (1U)
11337#define DSI_ISR0_AE1_Msk (0x1UL << DSI_ISR0_AE1_Pos)
11338#define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk
11339#define DSI_ISR0_AE2_Pos (2U)
11340#define DSI_ISR0_AE2_Msk (0x1UL << DSI_ISR0_AE2_Pos)
11341#define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk
11342#define DSI_ISR0_AE3_Pos (3U)
11343#define DSI_ISR0_AE3_Msk (0x1UL << DSI_ISR0_AE3_Pos)
11344#define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk
11345#define DSI_ISR0_AE4_Pos (4U)
11346#define DSI_ISR0_AE4_Msk (0x1UL << DSI_ISR0_AE4_Pos)
11347#define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk
11348#define DSI_ISR0_AE5_Pos (5U)
11349#define DSI_ISR0_AE5_Msk (0x1UL << DSI_ISR0_AE5_Pos)
11350#define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk
11351#define DSI_ISR0_AE6_Pos (6U)
11352#define DSI_ISR0_AE6_Msk (0x1UL << DSI_ISR0_AE6_Pos)
11353#define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk
11354#define DSI_ISR0_AE7_Pos (7U)
11355#define DSI_ISR0_AE7_Msk (0x1UL << DSI_ISR0_AE7_Pos)
11356#define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk
11357#define DSI_ISR0_AE8_Pos (8U)
11358#define DSI_ISR0_AE8_Msk (0x1UL << DSI_ISR0_AE8_Pos)
11359#define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk
11360#define DSI_ISR0_AE9_Pos (9U)
11361#define DSI_ISR0_AE9_Msk (0x1UL << DSI_ISR0_AE9_Pos)
11362#define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk
11363#define DSI_ISR0_AE10_Pos (10U)
11364#define DSI_ISR0_AE10_Msk (0x1UL << DSI_ISR0_AE10_Pos)
11365#define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk
11366#define DSI_ISR0_AE11_Pos (11U)
11367#define DSI_ISR0_AE11_Msk (0x1UL << DSI_ISR0_AE11_Pos)
11368#define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk
11369#define DSI_ISR0_AE12_Pos (12U)
11370#define DSI_ISR0_AE12_Msk (0x1UL << DSI_ISR0_AE12_Pos)
11371#define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk
11372#define DSI_ISR0_AE13_Pos (13U)
11373#define DSI_ISR0_AE13_Msk (0x1UL << DSI_ISR0_AE13_Pos)
11374#define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk
11375#define DSI_ISR0_AE14_Pos (14U)
11376#define DSI_ISR0_AE14_Msk (0x1UL << DSI_ISR0_AE14_Pos)
11377#define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk
11378#define DSI_ISR0_AE15_Pos (15U)
11379#define DSI_ISR0_AE15_Msk (0x1UL << DSI_ISR0_AE15_Pos)
11380#define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk
11381#define DSI_ISR0_PE0_Pos (16U)
11382#define DSI_ISR0_PE0_Msk (0x1UL << DSI_ISR0_PE0_Pos)
11383#define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk
11384#define DSI_ISR0_PE1_Pos (17U)
11385#define DSI_ISR0_PE1_Msk (0x1UL << DSI_ISR0_PE1_Pos)
11386#define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk
11387#define DSI_ISR0_PE2_Pos (18U)
11388#define DSI_ISR0_PE2_Msk (0x1UL << DSI_ISR0_PE2_Pos)
11389#define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk
11390#define DSI_ISR0_PE3_Pos (19U)
11391#define DSI_ISR0_PE3_Msk (0x1UL << DSI_ISR0_PE3_Pos)
11392#define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk
11393#define DSI_ISR0_PE4_Pos (20U)
11394#define DSI_ISR0_PE4_Msk (0x1UL << DSI_ISR0_PE4_Pos)
11395#define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk
11397/******************* Bit definition for DSI_ISR1 register ***************/
11398#define DSI_ISR1_TOHSTX_Pos (0U)
11399#define DSI_ISR1_TOHSTX_Msk (0x1UL << DSI_ISR1_TOHSTX_Pos)
11400#define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk
11401#define DSI_ISR1_TOLPRX_Pos (1U)
11402#define DSI_ISR1_TOLPRX_Msk (0x1UL << DSI_ISR1_TOLPRX_Pos)
11403#define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk
11404#define DSI_ISR1_ECCSE_Pos (2U)
11405#define DSI_ISR1_ECCSE_Msk (0x1UL << DSI_ISR1_ECCSE_Pos)
11406#define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk
11407#define DSI_ISR1_ECCME_Pos (3U)
11408#define DSI_ISR1_ECCME_Msk (0x1UL << DSI_ISR1_ECCME_Pos)
11409#define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk
11410#define DSI_ISR1_CRCE_Pos (4U)
11411#define DSI_ISR1_CRCE_Msk (0x1UL << DSI_ISR1_CRCE_Pos)
11412#define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk
11413#define DSI_ISR1_PSE_Pos (5U)
11414#define DSI_ISR1_PSE_Msk (0x1UL << DSI_ISR1_PSE_Pos)
11415#define DSI_ISR1_PSE DSI_ISR1_PSE_Msk
11416#define DSI_ISR1_EOTPE_Pos (6U)
11417#define DSI_ISR1_EOTPE_Msk (0x1UL << DSI_ISR1_EOTPE_Pos)
11418#define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk
11419#define DSI_ISR1_LPWRE_Pos (7U)
11420#define DSI_ISR1_LPWRE_Msk (0x1UL << DSI_ISR1_LPWRE_Pos)
11421#define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk
11422#define DSI_ISR1_GCWRE_Pos (8U)
11423#define DSI_ISR1_GCWRE_Msk (0x1UL << DSI_ISR1_GCWRE_Pos)
11424#define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk
11425#define DSI_ISR1_GPWRE_Pos (9U)
11426#define DSI_ISR1_GPWRE_Msk (0x1UL << DSI_ISR1_GPWRE_Pos)
11427#define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk
11428#define DSI_ISR1_GPTXE_Pos (10U)
11429#define DSI_ISR1_GPTXE_Msk (0x1UL << DSI_ISR1_GPTXE_Pos)
11430#define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk
11431#define DSI_ISR1_GPRDE_Pos (11U)
11432#define DSI_ISR1_GPRDE_Msk (0x1UL << DSI_ISR1_GPRDE_Pos)
11433#define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk
11434#define DSI_ISR1_GPRXE_Pos (12U)
11435#define DSI_ISR1_GPRXE_Msk (0x1UL << DSI_ISR1_GPRXE_Pos)
11436#define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk
11438/******************* Bit definition for DSI_IER0 register ***************/
11439#define DSI_IER0_AE0IE_Pos (0U)
11440#define DSI_IER0_AE0IE_Msk (0x1UL << DSI_IER0_AE0IE_Pos)
11441#define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk
11442#define DSI_IER0_AE1IE_Pos (1U)
11443#define DSI_IER0_AE1IE_Msk (0x1UL << DSI_IER0_AE1IE_Pos)
11444#define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk
11445#define DSI_IER0_AE2IE_Pos (2U)
11446#define DSI_IER0_AE2IE_Msk (0x1UL << DSI_IER0_AE2IE_Pos)
11447#define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk
11448#define DSI_IER0_AE3IE_Pos (3U)
11449#define DSI_IER0_AE3IE_Msk (0x1UL << DSI_IER0_AE3IE_Pos)
11450#define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk
11451#define DSI_IER0_AE4IE_Pos (4U)
11452#define DSI_IER0_AE4IE_Msk (0x1UL << DSI_IER0_AE4IE_Pos)
11453#define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk
11454#define DSI_IER0_AE5IE_Pos (5U)
11455#define DSI_IER0_AE5IE_Msk (0x1UL << DSI_IER0_AE5IE_Pos)
11456#define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk
11457#define DSI_IER0_AE6IE_Pos (6U)
11458#define DSI_IER0_AE6IE_Msk (0x1UL << DSI_IER0_AE6IE_Pos)
11459#define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk
11460#define DSI_IER0_AE7IE_Pos (7U)
11461#define DSI_IER0_AE7IE_Msk (0x1UL << DSI_IER0_AE7IE_Pos)
11462#define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk
11463#define DSI_IER0_AE8IE_Pos (8U)
11464#define DSI_IER0_AE8IE_Msk (0x1UL << DSI_IER0_AE8IE_Pos)
11465#define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk
11466#define DSI_IER0_AE9IE_Pos (9U)
11467#define DSI_IER0_AE9IE_Msk (0x1UL << DSI_IER0_AE9IE_Pos)
11468#define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk
11469#define DSI_IER0_AE10IE_Pos (10U)
11470#define DSI_IER0_AE10IE_Msk (0x1UL << DSI_IER0_AE10IE_Pos)
11471#define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk
11472#define DSI_IER0_AE11IE_Pos (11U)
11473#define DSI_IER0_AE11IE_Msk (0x1UL << DSI_IER0_AE11IE_Pos)
11474#define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk
11475#define DSI_IER0_AE12IE_Pos (12U)
11476#define DSI_IER0_AE12IE_Msk (0x1UL << DSI_IER0_AE12IE_Pos)
11477#define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk
11478#define DSI_IER0_AE13IE_Pos (13U)
11479#define DSI_IER0_AE13IE_Msk (0x1UL << DSI_IER0_AE13IE_Pos)
11480#define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk
11481#define DSI_IER0_AE14IE_Pos (14U)
11482#define DSI_IER0_AE14IE_Msk (0x1UL << DSI_IER0_AE14IE_Pos)
11483#define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk
11484#define DSI_IER0_AE15IE_Pos (15U)
11485#define DSI_IER0_AE15IE_Msk (0x1UL << DSI_IER0_AE15IE_Pos)
11486#define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk
11487#define DSI_IER0_PE0IE_Pos (16U)
11488#define DSI_IER0_PE0IE_Msk (0x1UL << DSI_IER0_PE0IE_Pos)
11489#define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk
11490#define DSI_IER0_PE1IE_Pos (17U)
11491#define DSI_IER0_PE1IE_Msk (0x1UL << DSI_IER0_PE1IE_Pos)
11492#define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk
11493#define DSI_IER0_PE2IE_Pos (18U)
11494#define DSI_IER0_PE2IE_Msk (0x1UL << DSI_IER0_PE2IE_Pos)
11495#define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk
11496#define DSI_IER0_PE3IE_Pos (19U)
11497#define DSI_IER0_PE3IE_Msk (0x1UL << DSI_IER0_PE3IE_Pos)
11498#define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk
11499#define DSI_IER0_PE4IE_Pos (20U)
11500#define DSI_IER0_PE4IE_Msk (0x1UL << DSI_IER0_PE4IE_Pos)
11501#define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk
11503/******************* Bit definition for DSI_IER1 register ***************/
11504#define DSI_IER1_TOHSTXIE_Pos (0U)
11505#define DSI_IER1_TOHSTXIE_Msk (0x1UL << DSI_IER1_TOHSTXIE_Pos)
11506#define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk
11507#define DSI_IER1_TOLPRXIE_Pos (1U)
11508#define DSI_IER1_TOLPRXIE_Msk (0x1UL << DSI_IER1_TOLPRXIE_Pos)
11509#define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk
11510#define DSI_IER1_ECCSEIE_Pos (2U)
11511#define DSI_IER1_ECCSEIE_Msk (0x1UL << DSI_IER1_ECCSEIE_Pos)
11512#define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk
11513#define DSI_IER1_ECCMEIE_Pos (3U)
11514#define DSI_IER1_ECCMEIE_Msk (0x1UL << DSI_IER1_ECCMEIE_Pos)
11515#define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk
11516#define DSI_IER1_CRCEIE_Pos (4U)
11517#define DSI_IER1_CRCEIE_Msk (0x1UL << DSI_IER1_CRCEIE_Pos)
11518#define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk
11519#define DSI_IER1_PSEIE_Pos (5U)
11520#define DSI_IER1_PSEIE_Msk (0x1UL << DSI_IER1_PSEIE_Pos)
11521#define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk
11522#define DSI_IER1_EOTPEIE_Pos (6U)
11523#define DSI_IER1_EOTPEIE_Msk (0x1UL << DSI_IER1_EOTPEIE_Pos)
11524#define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk
11525#define DSI_IER1_LPWREIE_Pos (7U)
11526#define DSI_IER1_LPWREIE_Msk (0x1UL << DSI_IER1_LPWREIE_Pos)
11527#define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk
11528#define DSI_IER1_GCWREIE_Pos (8U)
11529#define DSI_IER1_GCWREIE_Msk (0x1UL << DSI_IER1_GCWREIE_Pos)
11530#define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk
11531#define DSI_IER1_GPWREIE_Pos (9U)
11532#define DSI_IER1_GPWREIE_Msk (0x1UL << DSI_IER1_GPWREIE_Pos)
11533#define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk
11534#define DSI_IER1_GPTXEIE_Pos (10U)
11535#define DSI_IER1_GPTXEIE_Msk (0x1UL << DSI_IER1_GPTXEIE_Pos)
11536#define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk
11537#define DSI_IER1_GPRDEIE_Pos (11U)
11538#define DSI_IER1_GPRDEIE_Msk (0x1UL << DSI_IER1_GPRDEIE_Pos)
11539#define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk
11540#define DSI_IER1_GPRXEIE_Pos (12U)
11541#define DSI_IER1_GPRXEIE_Msk (0x1UL << DSI_IER1_GPRXEIE_Pos)
11542#define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk
11544/******************* Bit definition for DSI_FIR0 register ***************/
11545#define DSI_FIR0_FAE0_Pos (0U)
11546#define DSI_FIR0_FAE0_Msk (0x1UL << DSI_FIR0_FAE0_Pos)
11547#define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk
11548#define DSI_FIR0_FAE1_Pos (1U)
11549#define DSI_FIR0_FAE1_Msk (0x1UL << DSI_FIR0_FAE1_Pos)
11550#define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk
11551#define DSI_FIR0_FAE2_Pos (2U)
11552#define DSI_FIR0_FAE2_Msk (0x1UL << DSI_FIR0_FAE2_Pos)
11553#define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk
11554#define DSI_FIR0_FAE3_Pos (3U)
11555#define DSI_FIR0_FAE3_Msk (0x1UL << DSI_FIR0_FAE3_Pos)
11556#define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk
11557#define DSI_FIR0_FAE4_Pos (4U)
11558#define DSI_FIR0_FAE4_Msk (0x1UL << DSI_FIR0_FAE4_Pos)
11559#define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk
11560#define DSI_FIR0_FAE5_Pos (5U)
11561#define DSI_FIR0_FAE5_Msk (0x1UL << DSI_FIR0_FAE5_Pos)
11562#define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk
11563#define DSI_FIR0_FAE6_Pos (6U)
11564#define DSI_FIR0_FAE6_Msk (0x1UL << DSI_FIR0_FAE6_Pos)
11565#define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk
11566#define DSI_FIR0_FAE7_Pos (7U)
11567#define DSI_FIR0_FAE7_Msk (0x1UL << DSI_FIR0_FAE7_Pos)
11568#define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk
11569#define DSI_FIR0_FAE8_Pos (8U)
11570#define DSI_FIR0_FAE8_Msk (0x1UL << DSI_FIR0_FAE8_Pos)
11571#define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk
11572#define DSI_FIR0_FAE9_Pos (9U)
11573#define DSI_FIR0_FAE9_Msk (0x1UL << DSI_FIR0_FAE9_Pos)
11574#define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk
11575#define DSI_FIR0_FAE10_Pos (10U)
11576#define DSI_FIR0_FAE10_Msk (0x1UL << DSI_FIR0_FAE10_Pos)
11577#define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk
11578#define DSI_FIR0_FAE11_Pos (11U)
11579#define DSI_FIR0_FAE11_Msk (0x1UL << DSI_FIR0_FAE11_Pos)
11580#define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk
11581#define DSI_FIR0_FAE12_Pos (12U)
11582#define DSI_FIR0_FAE12_Msk (0x1UL << DSI_FIR0_FAE12_Pos)
11583#define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk
11584#define DSI_FIR0_FAE13_Pos (13U)
11585#define DSI_FIR0_FAE13_Msk (0x1UL << DSI_FIR0_FAE13_Pos)
11586#define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk
11587#define DSI_FIR0_FAE14_Pos (14U)
11588#define DSI_FIR0_FAE14_Msk (0x1UL << DSI_FIR0_FAE14_Pos)
11589#define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk
11590#define DSI_FIR0_FAE15_Pos (15U)
11591#define DSI_FIR0_FAE15_Msk (0x1UL << DSI_FIR0_FAE15_Pos)
11592#define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk
11593#define DSI_FIR0_FPE0_Pos (16U)
11594#define DSI_FIR0_FPE0_Msk (0x1UL << DSI_FIR0_FPE0_Pos)
11595#define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk
11596#define DSI_FIR0_FPE1_Pos (17U)
11597#define DSI_FIR0_FPE1_Msk (0x1UL << DSI_FIR0_FPE1_Pos)
11598#define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk
11599#define DSI_FIR0_FPE2_Pos (18U)
11600#define DSI_FIR0_FPE2_Msk (0x1UL << DSI_FIR0_FPE2_Pos)
11601#define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk
11602#define DSI_FIR0_FPE3_Pos (19U)
11603#define DSI_FIR0_FPE3_Msk (0x1UL << DSI_FIR0_FPE3_Pos)
11604#define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk
11605#define DSI_FIR0_FPE4_Pos (20U)
11606#define DSI_FIR0_FPE4_Msk (0x1UL << DSI_FIR0_FPE4_Pos)
11607#define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk
11609/******************* Bit definition for DSI_FIR1 register ***************/
11610#define DSI_FIR1_FTOHSTX_Pos (0U)
11611#define DSI_FIR1_FTOHSTX_Msk (0x1UL << DSI_FIR1_FTOHSTX_Pos)
11612#define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk
11613#define DSI_FIR1_FTOLPRX_Pos (1U)
11614#define DSI_FIR1_FTOLPRX_Msk (0x1UL << DSI_FIR1_FTOLPRX_Pos)
11615#define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk
11616#define DSI_FIR1_FECCSE_Pos (2U)
11617#define DSI_FIR1_FECCSE_Msk (0x1UL << DSI_FIR1_FECCSE_Pos)
11618#define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk
11619#define DSI_FIR1_FECCME_Pos (3U)
11620#define DSI_FIR1_FECCME_Msk (0x1UL << DSI_FIR1_FECCME_Pos)
11621#define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk
11622#define DSI_FIR1_FCRCE_Pos (4U)
11623#define DSI_FIR1_FCRCE_Msk (0x1UL << DSI_FIR1_FCRCE_Pos)
11624#define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk
11625#define DSI_FIR1_FPSE_Pos (5U)
11626#define DSI_FIR1_FPSE_Msk (0x1UL << DSI_FIR1_FPSE_Pos)
11627#define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk
11628#define DSI_FIR1_FEOTPE_Pos (6U)
11629#define DSI_FIR1_FEOTPE_Msk (0x1UL << DSI_FIR1_FEOTPE_Pos)
11630#define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk
11631#define DSI_FIR1_FLPWRE_Pos (7U)
11632#define DSI_FIR1_FLPWRE_Msk (0x1UL << DSI_FIR1_FLPWRE_Pos)
11633#define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk
11634#define DSI_FIR1_FGCWRE_Pos (8U)
11635#define DSI_FIR1_FGCWRE_Msk (0x1UL << DSI_FIR1_FGCWRE_Pos)
11636#define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk
11637#define DSI_FIR1_FGPWRE_Pos (9U)
11638#define DSI_FIR1_FGPWRE_Msk (0x1UL << DSI_FIR1_FGPWRE_Pos)
11639#define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk
11640#define DSI_FIR1_FGPTXE_Pos (10U)
11641#define DSI_FIR1_FGPTXE_Msk (0x1UL << DSI_FIR1_FGPTXE_Pos)
11642#define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk
11643#define DSI_FIR1_FGPRDE_Pos (11U)
11644#define DSI_FIR1_FGPRDE_Msk (0x1UL << DSI_FIR1_FGPRDE_Pos)
11645#define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk
11646#define DSI_FIR1_FGPRXE_Pos (12U)
11647#define DSI_FIR1_FGPRXE_Msk (0x1UL << DSI_FIR1_FGPRXE_Pos)
11648#define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk
11650/******************* Bit definition for DSI_VSCR register ***************/
11651#define DSI_VSCR_EN_Pos (0U)
11652#define DSI_VSCR_EN_Msk (0x1UL << DSI_VSCR_EN_Pos)
11653#define DSI_VSCR_EN DSI_VSCR_EN_Msk
11654#define DSI_VSCR_UR_Pos (8U)
11655#define DSI_VSCR_UR_Msk (0x1UL << DSI_VSCR_UR_Pos)
11656#define DSI_VSCR_UR DSI_VSCR_UR_Msk
11658/******************* Bit definition for DSI_LCVCIDR register ************/
11659#define DSI_LCVCIDR_VCID_Pos (0U)
11660#define DSI_LCVCIDR_VCID_Msk (0x3UL << DSI_LCVCIDR_VCID_Pos)
11661#define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk
11662#define DSI_LCVCIDR_VCID0_Pos (0U)
11663#define DSI_LCVCIDR_VCID0_Msk (0x1UL << DSI_LCVCIDR_VCID0_Pos)
11664#define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
11665#define DSI_LCVCIDR_VCID1_Pos (1U)
11666#define DSI_LCVCIDR_VCID1_Msk (0x1UL << DSI_LCVCIDR_VCID1_Pos)
11667#define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
11668
11669/******************* Bit definition for DSI_LCCCR register **************/
11670#define DSI_LCCCR_COLC_Pos (0U)
11671#define DSI_LCCCR_COLC_Msk (0xFUL << DSI_LCCCR_COLC_Pos)
11672#define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk
11673#define DSI_LCCCR_COLC0_Pos (0U)
11674#define DSI_LCCCR_COLC0_Msk (0x1UL << DSI_LCCCR_COLC0_Pos)
11675#define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
11676#define DSI_LCCCR_COLC1_Pos (1U)
11677#define DSI_LCCCR_COLC1_Msk (0x1UL << DSI_LCCCR_COLC1_Pos)
11678#define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
11679#define DSI_LCCCR_COLC2_Pos (2U)
11680#define DSI_LCCCR_COLC2_Msk (0x1UL << DSI_LCCCR_COLC2_Pos)
11681#define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
11682#define DSI_LCCCR_COLC3_Pos (3U)
11683#define DSI_LCCCR_COLC3_Msk (0x1UL << DSI_LCCCR_COLC3_Pos)
11684#define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
11685
11686#define DSI_LCCCR_LPE_Pos (8U)
11687#define DSI_LCCCR_LPE_Msk (0x1UL << DSI_LCCCR_LPE_Pos)
11688#define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk
11690/******************* Bit definition for DSI_LPMCCR register *************/
11691#define DSI_LPMCCR_VLPSIZE_Pos (0U)
11692#define DSI_LPMCCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos)
11693#define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk
11694#define DSI_LPMCCR_VLPSIZE0_Pos (0U)
11695#define DSI_LPMCCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos)
11696#define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
11697#define DSI_LPMCCR_VLPSIZE1_Pos (1U)
11698#define DSI_LPMCCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos)
11699#define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
11700#define DSI_LPMCCR_VLPSIZE2_Pos (2U)
11701#define DSI_LPMCCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos)
11702#define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
11703#define DSI_LPMCCR_VLPSIZE3_Pos (3U)
11704#define DSI_LPMCCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos)
11705#define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
11706#define DSI_LPMCCR_VLPSIZE4_Pos (4U)
11707#define DSI_LPMCCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos)
11708#define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
11709#define DSI_LPMCCR_VLPSIZE5_Pos (5U)
11710#define DSI_LPMCCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos)
11711#define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
11712#define DSI_LPMCCR_VLPSIZE6_Pos (6U)
11713#define DSI_LPMCCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos)
11714#define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
11715#define DSI_LPMCCR_VLPSIZE7_Pos (7U)
11716#define DSI_LPMCCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos)
11717#define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
11718
11719#define DSI_LPMCCR_LPSIZE_Pos (16U)
11720#define DSI_LPMCCR_LPSIZE_Msk (0xFFUL << DSI_LPMCCR_LPSIZE_Pos)
11721#define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk
11722#define DSI_LPMCCR_LPSIZE0_Pos (16U)
11723#define DSI_LPMCCR_LPSIZE0_Msk (0x1UL << DSI_LPMCCR_LPSIZE0_Pos)
11724#define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
11725#define DSI_LPMCCR_LPSIZE1_Pos (17U)
11726#define DSI_LPMCCR_LPSIZE1_Msk (0x1UL << DSI_LPMCCR_LPSIZE1_Pos)
11727#define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
11728#define DSI_LPMCCR_LPSIZE2_Pos (18U)
11729#define DSI_LPMCCR_LPSIZE2_Msk (0x1UL << DSI_LPMCCR_LPSIZE2_Pos)
11730#define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
11731#define DSI_LPMCCR_LPSIZE3_Pos (19U)
11732#define DSI_LPMCCR_LPSIZE3_Msk (0x1UL << DSI_LPMCCR_LPSIZE3_Pos)
11733#define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
11734#define DSI_LPMCCR_LPSIZE4_Pos (20U)
11735#define DSI_LPMCCR_LPSIZE4_Msk (0x1UL << DSI_LPMCCR_LPSIZE4_Pos)
11736#define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
11737#define DSI_LPMCCR_LPSIZE5_Pos (21U)
11738#define DSI_LPMCCR_LPSIZE5_Msk (0x1UL << DSI_LPMCCR_LPSIZE5_Pos)
11739#define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
11740#define DSI_LPMCCR_LPSIZE6_Pos (22U)
11741#define DSI_LPMCCR_LPSIZE6_Msk (0x1UL << DSI_LPMCCR_LPSIZE6_Pos)
11742#define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
11743#define DSI_LPMCCR_LPSIZE7_Pos (23U)
11744#define DSI_LPMCCR_LPSIZE7_Msk (0x1UL << DSI_LPMCCR_LPSIZE7_Pos)
11745#define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
11746
11747/******************* Bit definition for DSI_VMCCR register **************/
11748#define DSI_VMCCR_VMT_Pos (0U)
11749#define DSI_VMCCR_VMT_Msk (0x3UL << DSI_VMCCR_VMT_Pos)
11750#define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk
11751#define DSI_VMCCR_VMT0_Pos (0U)
11752#define DSI_VMCCR_VMT0_Msk (0x1UL << DSI_VMCCR_VMT0_Pos)
11753#define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
11754#define DSI_VMCCR_VMT1_Pos (1U)
11755#define DSI_VMCCR_VMT1_Msk (0x1UL << DSI_VMCCR_VMT1_Pos)
11756#define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
11757
11758#define DSI_VMCCR_LPVSAE_Pos (8U)
11759#define DSI_VMCCR_LPVSAE_Msk (0x1UL << DSI_VMCCR_LPVSAE_Pos)
11760#define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk
11761#define DSI_VMCCR_LPVBPE_Pos (9U)
11762#define DSI_VMCCR_LPVBPE_Msk (0x1UL << DSI_VMCCR_LPVBPE_Pos)
11763#define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk
11764#define DSI_VMCCR_LPVFPE_Pos (10U)
11765#define DSI_VMCCR_LPVFPE_Msk (0x1UL << DSI_VMCCR_LPVFPE_Pos)
11766#define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk
11767#define DSI_VMCCR_LPVAE_Pos (11U)
11768#define DSI_VMCCR_LPVAE_Msk (0x1UL << DSI_VMCCR_LPVAE_Pos)
11769#define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk
11770#define DSI_VMCCR_LPHBPE_Pos (12U)
11771#define DSI_VMCCR_LPHBPE_Msk (0x1UL << DSI_VMCCR_LPHBPE_Pos)
11772#define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk
11773#define DSI_VMCCR_LPHFE_Pos (13U)
11774#define DSI_VMCCR_LPHFE_Msk (0x1UL << DSI_VMCCR_LPHFE_Pos)
11775#define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk
11776#define DSI_VMCCR_FBTAAE_Pos (14U)
11777#define DSI_VMCCR_FBTAAE_Msk (0x1UL << DSI_VMCCR_FBTAAE_Pos)
11778#define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk
11779#define DSI_VMCCR_LPCE_Pos (15U)
11780#define DSI_VMCCR_LPCE_Msk (0x1UL << DSI_VMCCR_LPCE_Pos)
11781#define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk
11783/******************* Bit definition for DSI_VPCCR register **************/
11784#define DSI_VPCCR_VPSIZE_Pos (0U)
11785#define DSI_VPCCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos)
11786#define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk
11787#define DSI_VPCCR_VPSIZE0_Pos (0U)
11788#define DSI_VPCCR_VPSIZE0_Msk (0x1UL << DSI_VPCCR_VPSIZE0_Pos)
11789#define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
11790#define DSI_VPCCR_VPSIZE1_Pos (1U)
11791#define DSI_VPCCR_VPSIZE1_Msk (0x1UL << DSI_VPCCR_VPSIZE1_Pos)
11792#define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
11793#define DSI_VPCCR_VPSIZE2_Pos (2U)
11794#define DSI_VPCCR_VPSIZE2_Msk (0x1UL << DSI_VPCCR_VPSIZE2_Pos)
11795#define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
11796#define DSI_VPCCR_VPSIZE3_Pos (3U)
11797#define DSI_VPCCR_VPSIZE3_Msk (0x1UL << DSI_VPCCR_VPSIZE3_Pos)
11798#define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
11799#define DSI_VPCCR_VPSIZE4_Pos (4U)
11800#define DSI_VPCCR_VPSIZE4_Msk (0x1UL << DSI_VPCCR_VPSIZE4_Pos)
11801#define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
11802#define DSI_VPCCR_VPSIZE5_Pos (5U)
11803#define DSI_VPCCR_VPSIZE5_Msk (0x1UL << DSI_VPCCR_VPSIZE5_Pos)
11804#define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
11805#define DSI_VPCCR_VPSIZE6_Pos (6U)
11806#define DSI_VPCCR_VPSIZE6_Msk (0x1UL << DSI_VPCCR_VPSIZE6_Pos)
11807#define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
11808#define DSI_VPCCR_VPSIZE7_Pos (7U)
11809#define DSI_VPCCR_VPSIZE7_Msk (0x1UL << DSI_VPCCR_VPSIZE7_Pos)
11810#define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
11811#define DSI_VPCCR_VPSIZE8_Pos (8U)
11812#define DSI_VPCCR_VPSIZE8_Msk (0x1UL << DSI_VPCCR_VPSIZE8_Pos)
11813#define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
11814#define DSI_VPCCR_VPSIZE9_Pos (9U)
11815#define DSI_VPCCR_VPSIZE9_Msk (0x1UL << DSI_VPCCR_VPSIZE9_Pos)
11816#define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
11817#define DSI_VPCCR_VPSIZE10_Pos (10U)
11818#define DSI_VPCCR_VPSIZE10_Msk (0x1UL << DSI_VPCCR_VPSIZE10_Pos)
11819#define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
11820#define DSI_VPCCR_VPSIZE11_Pos (11U)
11821#define DSI_VPCCR_VPSIZE11_Msk (0x1UL << DSI_VPCCR_VPSIZE11_Pos)
11822#define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
11823#define DSI_VPCCR_VPSIZE12_Pos (12U)
11824#define DSI_VPCCR_VPSIZE12_Msk (0x1UL << DSI_VPCCR_VPSIZE12_Pos)
11825#define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
11826#define DSI_VPCCR_VPSIZE13_Pos (13U)
11827#define DSI_VPCCR_VPSIZE13_Msk (0x1UL << DSI_VPCCR_VPSIZE13_Pos)
11828#define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
11829
11830/******************* Bit definition for DSI_VCCCR register **************/
11831#define DSI_VCCCR_NUMC_Pos (0U)
11832#define DSI_VCCCR_NUMC_Msk (0x1FFFUL << DSI_VCCCR_NUMC_Pos)
11833#define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk
11834#define DSI_VCCCR_NUMC0_Pos (0U)
11835#define DSI_VCCCR_NUMC0_Msk (0x1UL << DSI_VCCCR_NUMC0_Pos)
11836#define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
11837#define DSI_VCCCR_NUMC1_Pos (1U)
11838#define DSI_VCCCR_NUMC1_Msk (0x1UL << DSI_VCCCR_NUMC1_Pos)
11839#define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
11840#define DSI_VCCCR_NUMC2_Pos (2U)
11841#define DSI_VCCCR_NUMC2_Msk (0x1UL << DSI_VCCCR_NUMC2_Pos)
11842#define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
11843#define DSI_VCCCR_NUMC3_Pos (3U)
11844#define DSI_VCCCR_NUMC3_Msk (0x1UL << DSI_VCCCR_NUMC3_Pos)
11845#define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
11846#define DSI_VCCCR_NUMC4_Pos (4U)
11847#define DSI_VCCCR_NUMC4_Msk (0x1UL << DSI_VCCCR_NUMC4_Pos)
11848#define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
11849#define DSI_VCCCR_NUMC5_Pos (5U)
11850#define DSI_VCCCR_NUMC5_Msk (0x1UL << DSI_VCCCR_NUMC5_Pos)
11851#define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
11852#define DSI_VCCCR_NUMC6_Pos (6U)
11853#define DSI_VCCCR_NUMC6_Msk (0x1UL << DSI_VCCCR_NUMC6_Pos)
11854#define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
11855#define DSI_VCCCR_NUMC7_Pos (7U)
11856#define DSI_VCCCR_NUMC7_Msk (0x1UL << DSI_VCCCR_NUMC7_Pos)
11857#define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
11858#define DSI_VCCCR_NUMC8_Pos (8U)
11859#define DSI_VCCCR_NUMC8_Msk (0x1UL << DSI_VCCCR_NUMC8_Pos)
11860#define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
11861#define DSI_VCCCR_NUMC9_Pos (9U)
11862#define DSI_VCCCR_NUMC9_Msk (0x1UL << DSI_VCCCR_NUMC9_Pos)
11863#define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
11864#define DSI_VCCCR_NUMC10_Pos (10U)
11865#define DSI_VCCCR_NUMC10_Msk (0x1UL << DSI_VCCCR_NUMC10_Pos)
11866#define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
11867#define DSI_VCCCR_NUMC11_Pos (11U)
11868#define DSI_VCCCR_NUMC11_Msk (0x1UL << DSI_VCCCR_NUMC11_Pos)
11869#define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
11870#define DSI_VCCCR_NUMC12_Pos (12U)
11871#define DSI_VCCCR_NUMC12_Msk (0x1UL << DSI_VCCCR_NUMC12_Pos)
11872#define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
11873
11874/******************* Bit definition for DSI_VNPCCR register *************/
11875#define DSI_VNPCCR_NPSIZE_Pos (0U)
11876#define DSI_VNPCCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos)
11877#define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk
11878#define DSI_VNPCCR_NPSIZE0_Pos (0U)
11879#define DSI_VNPCCR_NPSIZE0_Msk (0x1UL << DSI_VNPCCR_NPSIZE0_Pos)
11880#define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
11881#define DSI_VNPCCR_NPSIZE1_Pos (1U)
11882#define DSI_VNPCCR_NPSIZE1_Msk (0x1UL << DSI_VNPCCR_NPSIZE1_Pos)
11883#define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
11884#define DSI_VNPCCR_NPSIZE2_Pos (2U)
11885#define DSI_VNPCCR_NPSIZE2_Msk (0x1UL << DSI_VNPCCR_NPSIZE2_Pos)
11886#define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
11887#define DSI_VNPCCR_NPSIZE3_Pos (3U)
11888#define DSI_VNPCCR_NPSIZE3_Msk (0x1UL << DSI_VNPCCR_NPSIZE3_Pos)
11889#define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
11890#define DSI_VNPCCR_NPSIZE4_Pos (4U)
11891#define DSI_VNPCCR_NPSIZE4_Msk (0x1UL << DSI_VNPCCR_NPSIZE4_Pos)
11892#define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
11893#define DSI_VNPCCR_NPSIZE5_Pos (5U)
11894#define DSI_VNPCCR_NPSIZE5_Msk (0x1UL << DSI_VNPCCR_NPSIZE5_Pos)
11895#define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
11896#define DSI_VNPCCR_NPSIZE6_Pos (6U)
11897#define DSI_VNPCCR_NPSIZE6_Msk (0x1UL << DSI_VNPCCR_NPSIZE6_Pos)
11898#define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
11899#define DSI_VNPCCR_NPSIZE7_Pos (7U)
11900#define DSI_VNPCCR_NPSIZE7_Msk (0x1UL << DSI_VNPCCR_NPSIZE7_Pos)
11901#define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
11902#define DSI_VNPCCR_NPSIZE8_Pos (8U)
11903#define DSI_VNPCCR_NPSIZE8_Msk (0x1UL << DSI_VNPCCR_NPSIZE8_Pos)
11904#define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
11905#define DSI_VNPCCR_NPSIZE9_Pos (9U)
11906#define DSI_VNPCCR_NPSIZE9_Msk (0x1UL << DSI_VNPCCR_NPSIZE9_Pos)
11907#define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
11908#define DSI_VNPCCR_NPSIZE10_Pos (10U)
11909#define DSI_VNPCCR_NPSIZE10_Msk (0x1UL << DSI_VNPCCR_NPSIZE10_Pos)
11910#define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
11911#define DSI_VNPCCR_NPSIZE11_Pos (11U)
11912#define DSI_VNPCCR_NPSIZE11_Msk (0x1UL << DSI_VNPCCR_NPSIZE11_Pos)
11913#define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
11914#define DSI_VNPCCR_NPSIZE12_Pos (12U)
11915#define DSI_VNPCCR_NPSIZE12_Msk (0x1UL << DSI_VNPCCR_NPSIZE12_Pos)
11916#define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
11917
11918/******************* Bit definition for DSI_VHSACCR register ************/
11919#define DSI_VHSACCR_HSA_Pos (0U)
11920#define DSI_VHSACCR_HSA_Msk (0xFFFUL << DSI_VHSACCR_HSA_Pos)
11921#define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk
11922#define DSI_VHSACCR_HSA0_Pos (0U)
11923#define DSI_VHSACCR_HSA0_Msk (0x1UL << DSI_VHSACCR_HSA0_Pos)
11924#define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
11925#define DSI_VHSACCR_HSA1_Pos (1U)
11926#define DSI_VHSACCR_HSA1_Msk (0x1UL << DSI_VHSACCR_HSA1_Pos)
11927#define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
11928#define DSI_VHSACCR_HSA2_Pos (2U)
11929#define DSI_VHSACCR_HSA2_Msk (0x1UL << DSI_VHSACCR_HSA2_Pos)
11930#define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
11931#define DSI_VHSACCR_HSA3_Pos (3U)
11932#define DSI_VHSACCR_HSA3_Msk (0x1UL << DSI_VHSACCR_HSA3_Pos)
11933#define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
11934#define DSI_VHSACCR_HSA4_Pos (4U)
11935#define DSI_VHSACCR_HSA4_Msk (0x1UL << DSI_VHSACCR_HSA4_Pos)
11936#define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
11937#define DSI_VHSACCR_HSA5_Pos (5U)
11938#define DSI_VHSACCR_HSA5_Msk (0x1UL << DSI_VHSACCR_HSA5_Pos)
11939#define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
11940#define DSI_VHSACCR_HSA6_Pos (6U)
11941#define DSI_VHSACCR_HSA6_Msk (0x1UL << DSI_VHSACCR_HSA6_Pos)
11942#define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
11943#define DSI_VHSACCR_HSA7_Pos (7U)
11944#define DSI_VHSACCR_HSA7_Msk (0x1UL << DSI_VHSACCR_HSA7_Pos)
11945#define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
11946#define DSI_VHSACCR_HSA8_Pos (8U)
11947#define DSI_VHSACCR_HSA8_Msk (0x1UL << DSI_VHSACCR_HSA8_Pos)
11948#define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
11949#define DSI_VHSACCR_HSA9_Pos (9U)
11950#define DSI_VHSACCR_HSA9_Msk (0x1UL << DSI_VHSACCR_HSA9_Pos)
11951#define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
11952#define DSI_VHSACCR_HSA10_Pos (10U)
11953#define DSI_VHSACCR_HSA10_Msk (0x1UL << DSI_VHSACCR_HSA10_Pos)
11954#define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
11955#define DSI_VHSACCR_HSA11_Pos (11U)
11956#define DSI_VHSACCR_HSA11_Msk (0x1UL << DSI_VHSACCR_HSA11_Pos)
11957#define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
11958
11959/******************* Bit definition for DSI_VHBPCCR register ************/
11960#define DSI_VHBPCCR_HBP_Pos (0U)
11961#define DSI_VHBPCCR_HBP_Msk (0xFFFUL << DSI_VHBPCCR_HBP_Pos)
11962#define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk
11963#define DSI_VHBPCCR_HBP0_Pos (0U)
11964#define DSI_VHBPCCR_HBP0_Msk (0x1UL << DSI_VHBPCCR_HBP0_Pos)
11965#define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
11966#define DSI_VHBPCCR_HBP1_Pos (1U)
11967#define DSI_VHBPCCR_HBP1_Msk (0x1UL << DSI_VHBPCCR_HBP1_Pos)
11968#define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
11969#define DSI_VHBPCCR_HBP2_Pos (2U)
11970#define DSI_VHBPCCR_HBP2_Msk (0x1UL << DSI_VHBPCCR_HBP2_Pos)
11971#define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
11972#define DSI_VHBPCCR_HBP3_Pos (3U)
11973#define DSI_VHBPCCR_HBP3_Msk (0x1UL << DSI_VHBPCCR_HBP3_Pos)
11974#define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
11975#define DSI_VHBPCCR_HBP4_Pos (4U)
11976#define DSI_VHBPCCR_HBP4_Msk (0x1UL << DSI_VHBPCCR_HBP4_Pos)
11977#define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
11978#define DSI_VHBPCCR_HBP5_Pos (5U)
11979#define DSI_VHBPCCR_HBP5_Msk (0x1UL << DSI_VHBPCCR_HBP5_Pos)
11980#define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
11981#define DSI_VHBPCCR_HBP6_Pos (6U)
11982#define DSI_VHBPCCR_HBP6_Msk (0x1UL << DSI_VHBPCCR_HBP6_Pos)
11983#define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
11984#define DSI_VHBPCCR_HBP7_Pos (7U)
11985#define DSI_VHBPCCR_HBP7_Msk (0x1UL << DSI_VHBPCCR_HBP7_Pos)
11986#define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
11987#define DSI_VHBPCCR_HBP8_Pos (8U)
11988#define DSI_VHBPCCR_HBP8_Msk (0x1UL << DSI_VHBPCCR_HBP8_Pos)
11989#define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
11990#define DSI_VHBPCCR_HBP9_Pos (9U)
11991#define DSI_VHBPCCR_HBP9_Msk (0x1UL << DSI_VHBPCCR_HBP9_Pos)
11992#define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
11993#define DSI_VHBPCCR_HBP10_Pos (10U)
11994#define DSI_VHBPCCR_HBP10_Msk (0x1UL << DSI_VHBPCCR_HBP10_Pos)
11995#define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
11996#define DSI_VHBPCCR_HBP11_Pos (11U)
11997#define DSI_VHBPCCR_HBP11_Msk (0x1UL << DSI_VHBPCCR_HBP11_Pos)
11998#define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
11999
12000/******************* Bit definition for DSI_VLCCR register **************/
12001#define DSI_VLCCR_HLINE_Pos (0U)
12002#define DSI_VLCCR_HLINE_Msk (0x7FFFUL << DSI_VLCCR_HLINE_Pos)
12003#define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk
12004#define DSI_VLCCR_HLINE0_Pos (0U)
12005#define DSI_VLCCR_HLINE0_Msk (0x1UL << DSI_VLCCR_HLINE0_Pos)
12006#define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
12007#define DSI_VLCCR_HLINE1_Pos (1U)
12008#define DSI_VLCCR_HLINE1_Msk (0x1UL << DSI_VLCCR_HLINE1_Pos)
12009#define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
12010#define DSI_VLCCR_HLINE2_Pos (2U)
12011#define DSI_VLCCR_HLINE2_Msk (0x1UL << DSI_VLCCR_HLINE2_Pos)
12012#define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
12013#define DSI_VLCCR_HLINE3_Pos (3U)
12014#define DSI_VLCCR_HLINE3_Msk (0x1UL << DSI_VLCCR_HLINE3_Pos)
12015#define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
12016#define DSI_VLCCR_HLINE4_Pos (4U)
12017#define DSI_VLCCR_HLINE4_Msk (0x1UL << DSI_VLCCR_HLINE4_Pos)
12018#define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
12019#define DSI_VLCCR_HLINE5_Pos (5U)
12020#define DSI_VLCCR_HLINE5_Msk (0x1UL << DSI_VLCCR_HLINE5_Pos)
12021#define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
12022#define DSI_VLCCR_HLINE6_Pos (6U)
12023#define DSI_VLCCR_HLINE6_Msk (0x1UL << DSI_VLCCR_HLINE6_Pos)
12024#define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
12025#define DSI_VLCCR_HLINE7_Pos (7U)
12026#define DSI_VLCCR_HLINE7_Msk (0x1UL << DSI_VLCCR_HLINE7_Pos)
12027#define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
12028#define DSI_VLCCR_HLINE8_Pos (8U)
12029#define DSI_VLCCR_HLINE8_Msk (0x1UL << DSI_VLCCR_HLINE8_Pos)
12030#define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
12031#define DSI_VLCCR_HLINE9_Pos (9U)
12032#define DSI_VLCCR_HLINE9_Msk (0x1UL << DSI_VLCCR_HLINE9_Pos)
12033#define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
12034#define DSI_VLCCR_HLINE10_Pos (10U)
12035#define DSI_VLCCR_HLINE10_Msk (0x1UL << DSI_VLCCR_HLINE10_Pos)
12036#define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
12037#define DSI_VLCCR_HLINE11_Pos (11U)
12038#define DSI_VLCCR_HLINE11_Msk (0x1UL << DSI_VLCCR_HLINE11_Pos)
12039#define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
12040#define DSI_VLCCR_HLINE12_Pos (12U)
12041#define DSI_VLCCR_HLINE12_Msk (0x1UL << DSI_VLCCR_HLINE12_Pos)
12042#define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
12043#define DSI_VLCCR_HLINE13_Pos (13U)
12044#define DSI_VLCCR_HLINE13_Msk (0x1UL << DSI_VLCCR_HLINE13_Pos)
12045#define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
12046#define DSI_VLCCR_HLINE14_Pos (14U)
12047#define DSI_VLCCR_HLINE14_Msk (0x1UL << DSI_VLCCR_HLINE14_Pos)
12048#define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
12049
12050/******************* Bit definition for DSI_VVSACCR register ***************/
12051#define DSI_VVSACCR_VSA_Pos (0U)
12052#define DSI_VVSACCR_VSA_Msk (0x3FFUL << DSI_VVSACCR_VSA_Pos)
12053#define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk
12054#define DSI_VVSACCR_VSA0_Pos (0U)
12055#define DSI_VVSACCR_VSA0_Msk (0x1UL << DSI_VVSACCR_VSA0_Pos)
12056#define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
12057#define DSI_VVSACCR_VSA1_Pos (1U)
12058#define DSI_VVSACCR_VSA1_Msk (0x1UL << DSI_VVSACCR_VSA1_Pos)
12059#define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
12060#define DSI_VVSACCR_VSA2_Pos (2U)
12061#define DSI_VVSACCR_VSA2_Msk (0x1UL << DSI_VVSACCR_VSA2_Pos)
12062#define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
12063#define DSI_VVSACCR_VSA3_Pos (3U)
12064#define DSI_VVSACCR_VSA3_Msk (0x1UL << DSI_VVSACCR_VSA3_Pos)
12065#define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
12066#define DSI_VVSACCR_VSA4_Pos (4U)
12067#define DSI_VVSACCR_VSA4_Msk (0x1UL << DSI_VVSACCR_VSA4_Pos)
12068#define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
12069#define DSI_VVSACCR_VSA5_Pos (5U)
12070#define DSI_VVSACCR_VSA5_Msk (0x1UL << DSI_VVSACCR_VSA5_Pos)
12071#define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
12072#define DSI_VVSACCR_VSA6_Pos (6U)
12073#define DSI_VVSACCR_VSA6_Msk (0x1UL << DSI_VVSACCR_VSA6_Pos)
12074#define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
12075#define DSI_VVSACCR_VSA7_Pos (7U)
12076#define DSI_VVSACCR_VSA7_Msk (0x1UL << DSI_VVSACCR_VSA7_Pos)
12077#define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
12078#define DSI_VVSACCR_VSA8_Pos (8U)
12079#define DSI_VVSACCR_VSA8_Msk (0x1UL << DSI_VVSACCR_VSA8_Pos)
12080#define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
12081#define DSI_VVSACCR_VSA9_Pos (9U)
12082#define DSI_VVSACCR_VSA9_Msk (0x1UL << DSI_VVSACCR_VSA9_Pos)
12083#define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
12084
12085/******************* Bit definition for DSI_VVBPCCR register ************/
12086#define DSI_VVBPCCR_VBP_Pos (0U)
12087#define DSI_VVBPCCR_VBP_Msk (0x3FFUL << DSI_VVBPCCR_VBP_Pos)
12088#define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk
12089#define DSI_VVBPCCR_VBP0_Pos (0U)
12090#define DSI_VVBPCCR_VBP0_Msk (0x1UL << DSI_VVBPCCR_VBP0_Pos)
12091#define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
12092#define DSI_VVBPCCR_VBP1_Pos (1U)
12093#define DSI_VVBPCCR_VBP1_Msk (0x1UL << DSI_VVBPCCR_VBP1_Pos)
12094#define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
12095#define DSI_VVBPCCR_VBP2_Pos (2U)
12096#define DSI_VVBPCCR_VBP2_Msk (0x1UL << DSI_VVBPCCR_VBP2_Pos)
12097#define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
12098#define DSI_VVBPCCR_VBP3_Pos (3U)
12099#define DSI_VVBPCCR_VBP3_Msk (0x1UL << DSI_VVBPCCR_VBP3_Pos)
12100#define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
12101#define DSI_VVBPCCR_VBP4_Pos (4U)
12102#define DSI_VVBPCCR_VBP4_Msk (0x1UL << DSI_VVBPCCR_VBP4_Pos)
12103#define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
12104#define DSI_VVBPCCR_VBP5_Pos (5U)
12105#define DSI_VVBPCCR_VBP5_Msk (0x1UL << DSI_VVBPCCR_VBP5_Pos)
12106#define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
12107#define DSI_VVBPCCR_VBP6_Pos (6U)
12108#define DSI_VVBPCCR_VBP6_Msk (0x1UL << DSI_VVBPCCR_VBP6_Pos)
12109#define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
12110#define DSI_VVBPCCR_VBP7_Pos (7U)
12111#define DSI_VVBPCCR_VBP7_Msk (0x1UL << DSI_VVBPCCR_VBP7_Pos)
12112#define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
12113#define DSI_VVBPCCR_VBP8_Pos (8U)
12114#define DSI_VVBPCCR_VBP8_Msk (0x1UL << DSI_VVBPCCR_VBP8_Pos)
12115#define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
12116#define DSI_VVBPCCR_VBP9_Pos (9U)
12117#define DSI_VVBPCCR_VBP9_Msk (0x1UL << DSI_VVBPCCR_VBP9_Pos)
12118#define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
12119
12120/******************* Bit definition for DSI_VVFPCCR register ************/
12121#define DSI_VVFPCCR_VFP_Pos (0U)
12122#define DSI_VVFPCCR_VFP_Msk (0x3FFUL << DSI_VVFPCCR_VFP_Pos)
12123#define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk
12124#define DSI_VVFPCCR_VFP0_Pos (0U)
12125#define DSI_VVFPCCR_VFP0_Msk (0x1UL << DSI_VVFPCCR_VFP0_Pos)
12126#define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
12127#define DSI_VVFPCCR_VFP1_Pos (1U)
12128#define DSI_VVFPCCR_VFP1_Msk (0x1UL << DSI_VVFPCCR_VFP1_Pos)
12129#define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
12130#define DSI_VVFPCCR_VFP2_Pos (2U)
12131#define DSI_VVFPCCR_VFP2_Msk (0x1UL << DSI_VVFPCCR_VFP2_Pos)
12132#define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
12133#define DSI_VVFPCCR_VFP3_Pos (3U)
12134#define DSI_VVFPCCR_VFP3_Msk (0x1UL << DSI_VVFPCCR_VFP3_Pos)
12135#define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
12136#define DSI_VVFPCCR_VFP4_Pos (4U)
12137#define DSI_VVFPCCR_VFP4_Msk (0x1UL << DSI_VVFPCCR_VFP4_Pos)
12138#define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
12139#define DSI_VVFPCCR_VFP5_Pos (5U)
12140#define DSI_VVFPCCR_VFP5_Msk (0x1UL << DSI_VVFPCCR_VFP5_Pos)
12141#define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
12142#define DSI_VVFPCCR_VFP6_Pos (6U)
12143#define DSI_VVFPCCR_VFP6_Msk (0x1UL << DSI_VVFPCCR_VFP6_Pos)
12144#define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
12145#define DSI_VVFPCCR_VFP7_Pos (7U)
12146#define DSI_VVFPCCR_VFP7_Msk (0x1UL << DSI_VVFPCCR_VFP7_Pos)
12147#define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
12148#define DSI_VVFPCCR_VFP8_Pos (8U)
12149#define DSI_VVFPCCR_VFP8_Msk (0x1UL << DSI_VVFPCCR_VFP8_Pos)
12150#define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
12151#define DSI_VVFPCCR_VFP9_Pos (9U)
12152#define DSI_VVFPCCR_VFP9_Msk (0x1UL << DSI_VVFPCCR_VFP9_Pos)
12153#define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
12154
12155/******************* Bit definition for DSI_VVACCR register *************/
12156#define DSI_VVACCR_VA_Pos (0U)
12157#define DSI_VVACCR_VA_Msk (0x3FFFUL << DSI_VVACCR_VA_Pos)
12158#define DSI_VVACCR_VA DSI_VVACCR_VA_Msk
12159#define DSI_VVACCR_VA0_Pos (0U)
12160#define DSI_VVACCR_VA0_Msk (0x1UL << DSI_VVACCR_VA0_Pos)
12161#define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
12162#define DSI_VVACCR_VA1_Pos (1U)
12163#define DSI_VVACCR_VA1_Msk (0x1UL << DSI_VVACCR_VA1_Pos)
12164#define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
12165#define DSI_VVACCR_VA2_Pos (2U)
12166#define DSI_VVACCR_VA2_Msk (0x1UL << DSI_VVACCR_VA2_Pos)
12167#define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
12168#define DSI_VVACCR_VA3_Pos (3U)
12169#define DSI_VVACCR_VA3_Msk (0x1UL << DSI_VVACCR_VA3_Pos)
12170#define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
12171#define DSI_VVACCR_VA4_Pos (4U)
12172#define DSI_VVACCR_VA4_Msk (0x1UL << DSI_VVACCR_VA4_Pos)
12173#define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
12174#define DSI_VVACCR_VA5_Pos (5U)
12175#define DSI_VVACCR_VA5_Msk (0x1UL << DSI_VVACCR_VA5_Pos)
12176#define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
12177#define DSI_VVACCR_VA6_Pos (6U)
12178#define DSI_VVACCR_VA6_Msk (0x1UL << DSI_VVACCR_VA6_Pos)
12179#define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
12180#define DSI_VVACCR_VA7_Pos (7U)
12181#define DSI_VVACCR_VA7_Msk (0x1UL << DSI_VVACCR_VA7_Pos)
12182#define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
12183#define DSI_VVACCR_VA8_Pos (8U)
12184#define DSI_VVACCR_VA8_Msk (0x1UL << DSI_VVACCR_VA8_Pos)
12185#define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
12186#define DSI_VVACCR_VA9_Pos (9U)
12187#define DSI_VVACCR_VA9_Msk (0x1UL << DSI_VVACCR_VA9_Pos)
12188#define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
12189#define DSI_VVACCR_VA10_Pos (10U)
12190#define DSI_VVACCR_VA10_Msk (0x1UL << DSI_VVACCR_VA10_Pos)
12191#define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
12192#define DSI_VVACCR_VA11_Pos (11U)
12193#define DSI_VVACCR_VA11_Msk (0x1UL << DSI_VVACCR_VA11_Pos)
12194#define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
12195#define DSI_VVACCR_VA12_Pos (12U)
12196#define DSI_VVACCR_VA12_Msk (0x1UL << DSI_VVACCR_VA12_Pos)
12197#define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
12198#define DSI_VVACCR_VA13_Pos (13U)
12199#define DSI_VVACCR_VA13_Msk (0x1UL << DSI_VVACCR_VA13_Pos)
12200#define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
12201
12202/******************* Bit definition for DSI_TDCCR register **************/
12203#define DSI_TDCCR_3DM (0x00000003U)
12204#define DSI_TDCCR_3DM0 (0x00000001U)
12205#define DSI_TDCCR_3DM1 (0x00000002U)
12206
12207#define DSI_TDCCR_3DF (0x0000000CU)
12208#define DSI_TDCCR_3DF0 (0x00000004U)
12209#define DSI_TDCCR_3DF1 (0x00000008U)
12210
12211#define DSI_TDCCR_SVS_Pos (4U)
12212#define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos)
12213#define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk
12214#define DSI_TDCCR_RF_Pos (5U)
12215#define DSI_TDCCR_RF_Msk (0x1UL << DSI_TDCCR_RF_Pos)
12216#define DSI_TDCCR_RF DSI_TDCCR_RF_Msk
12217#define DSI_TDCCR_S3DC_Pos (16U)
12218#define DSI_TDCCR_S3DC_Msk (0x1UL << DSI_TDCCR_S3DC_Pos)
12219#define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk
12221/******************* Bit definition for DSI_WCFGR register ***************/
12222#define DSI_WCFGR_DSIM_Pos (0U)
12223#define DSI_WCFGR_DSIM_Msk (0x1UL << DSI_WCFGR_DSIM_Pos)
12224#define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk
12225#define DSI_WCFGR_COLMUX_Pos (1U)
12226#define DSI_WCFGR_COLMUX_Msk (0x7UL << DSI_WCFGR_COLMUX_Pos)
12227#define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk
12228#define DSI_WCFGR_COLMUX0_Pos (1U)
12229#define DSI_WCFGR_COLMUX0_Msk (0x1UL << DSI_WCFGR_COLMUX0_Pos)
12230#define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
12231#define DSI_WCFGR_COLMUX1_Pos (2U)
12232#define DSI_WCFGR_COLMUX1_Msk (0x1UL << DSI_WCFGR_COLMUX1_Pos)
12233#define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
12234#define DSI_WCFGR_COLMUX2_Pos (3U)
12235#define DSI_WCFGR_COLMUX2_Msk (0x1UL << DSI_WCFGR_COLMUX2_Pos)
12236#define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
12237
12238#define DSI_WCFGR_TESRC_Pos (4U)
12239#define DSI_WCFGR_TESRC_Msk (0x1UL << DSI_WCFGR_TESRC_Pos)
12240#define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk
12241#define DSI_WCFGR_TEPOL_Pos (5U)
12242#define DSI_WCFGR_TEPOL_Msk (0x1UL << DSI_WCFGR_TEPOL_Pos)
12243#define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk
12244#define DSI_WCFGR_AR_Pos (6U)
12245#define DSI_WCFGR_AR_Msk (0x1UL << DSI_WCFGR_AR_Pos)
12246#define DSI_WCFGR_AR DSI_WCFGR_AR_Msk
12247#define DSI_WCFGR_VSPOL_Pos (7U)
12248#define DSI_WCFGR_VSPOL_Msk (0x1UL << DSI_WCFGR_VSPOL_Pos)
12249#define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk
12251/******************* Bit definition for DSI_WCR register *****************/
12252#define DSI_WCR_COLM_Pos (0U)
12253#define DSI_WCR_COLM_Msk (0x1UL << DSI_WCR_COLM_Pos)
12254#define DSI_WCR_COLM DSI_WCR_COLM_Msk
12255#define DSI_WCR_SHTDN_Pos (1U)
12256#define DSI_WCR_SHTDN_Msk (0x1UL << DSI_WCR_SHTDN_Pos)
12257#define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk
12258#define DSI_WCR_LTDCEN_Pos (2U)
12259#define DSI_WCR_LTDCEN_Msk (0x1UL << DSI_WCR_LTDCEN_Pos)
12260#define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk
12261#define DSI_WCR_DSIEN_Pos (3U)
12262#define DSI_WCR_DSIEN_Msk (0x1UL << DSI_WCR_DSIEN_Pos)
12263#define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk
12265/******************* Bit definition for DSI_WIER register ****************/
12266#define DSI_WIER_TEIE_Pos (0U)
12267#define DSI_WIER_TEIE_Msk (0x1UL << DSI_WIER_TEIE_Pos)
12268#define DSI_WIER_TEIE DSI_WIER_TEIE_Msk
12269#define DSI_WIER_ERIE_Pos (1U)
12270#define DSI_WIER_ERIE_Msk (0x1UL << DSI_WIER_ERIE_Pos)
12271#define DSI_WIER_ERIE DSI_WIER_ERIE_Msk
12272#define DSI_WIER_PLLLIE_Pos (9U)
12273#define DSI_WIER_PLLLIE_Msk (0x1UL << DSI_WIER_PLLLIE_Pos)
12274#define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk
12275#define DSI_WIER_PLLUIE_Pos (10U)
12276#define DSI_WIER_PLLUIE_Msk (0x1UL << DSI_WIER_PLLUIE_Pos)
12277#define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk
12278#define DSI_WIER_RRIE_Pos (13U)
12279#define DSI_WIER_RRIE_Msk (0x1UL << DSI_WIER_RRIE_Pos)
12280#define DSI_WIER_RRIE DSI_WIER_RRIE_Msk
12282/******************* Bit definition for DSI_WISR register ****************/
12283#define DSI_WISR_TEIF_Pos (0U)
12284#define DSI_WISR_TEIF_Msk (0x1UL << DSI_WISR_TEIF_Pos)
12285#define DSI_WISR_TEIF DSI_WISR_TEIF_Msk
12286#define DSI_WISR_ERIF_Pos (1U)
12287#define DSI_WISR_ERIF_Msk (0x1UL << DSI_WISR_ERIF_Pos)
12288#define DSI_WISR_ERIF DSI_WISR_ERIF_Msk
12289#define DSI_WISR_BUSY_Pos (2U)
12290#define DSI_WISR_BUSY_Msk (0x1UL << DSI_WISR_BUSY_Pos)
12291#define DSI_WISR_BUSY DSI_WISR_BUSY_Msk
12292#define DSI_WISR_PLLLS_Pos (8U)
12293#define DSI_WISR_PLLLS_Msk (0x1UL << DSI_WISR_PLLLS_Pos)
12294#define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk
12295#define DSI_WISR_PLLLIF_Pos (9U)
12296#define DSI_WISR_PLLLIF_Msk (0x1UL << DSI_WISR_PLLLIF_Pos)
12297#define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk
12298#define DSI_WISR_PLLUIF_Pos (10U)
12299#define DSI_WISR_PLLUIF_Msk (0x1UL << DSI_WISR_PLLUIF_Pos)
12300#define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk
12301#define DSI_WISR_RRS_Pos (12U)
12302#define DSI_WISR_RRS_Msk (0x1UL << DSI_WISR_RRS_Pos)
12303#define DSI_WISR_RRS DSI_WISR_RRS_Msk
12304#define DSI_WISR_RRIF_Pos (13U)
12305#define DSI_WISR_RRIF_Msk (0x1UL << DSI_WISR_RRIF_Pos)
12306#define DSI_WISR_RRIF DSI_WISR_RRIF_Msk
12308/******************* Bit definition for DSI_WIFCR register ***************/
12309#define DSI_WIFCR_CTEIF_Pos (0U)
12310#define DSI_WIFCR_CTEIF_Msk (0x1UL << DSI_WIFCR_CTEIF_Pos)
12311#define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk
12312#define DSI_WIFCR_CERIF_Pos (1U)
12313#define DSI_WIFCR_CERIF_Msk (0x1UL << DSI_WIFCR_CERIF_Pos)
12314#define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk
12315#define DSI_WIFCR_CPLLLIF_Pos (9U)
12316#define DSI_WIFCR_CPLLLIF_Msk (0x1UL << DSI_WIFCR_CPLLLIF_Pos)
12317#define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk
12318#define DSI_WIFCR_CPLLUIF_Pos (10U)
12319#define DSI_WIFCR_CPLLUIF_Msk (0x1UL << DSI_WIFCR_CPLLUIF_Pos)
12320#define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk
12321#define DSI_WIFCR_CRRIF_Pos (13U)
12322#define DSI_WIFCR_CRRIF_Msk (0x1UL << DSI_WIFCR_CRRIF_Pos)
12323#define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk
12325/******************* Bit definition for DSI_WPCR0 register ***************/
12326#define DSI_WPCR0_UIX4_Pos (0U)
12327#define DSI_WPCR0_UIX4_Msk (0x3FUL << DSI_WPCR0_UIX4_Pos)
12328#define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk
12329#define DSI_WPCR0_UIX4_0 (0x01UL << DSI_WPCR0_UIX4_Pos)
12330#define DSI_WPCR0_UIX4_1 (0x02UL << DSI_WPCR0_UIX4_Pos)
12331#define DSI_WPCR0_UIX4_2 (0x04UL << DSI_WPCR0_UIX4_Pos)
12332#define DSI_WPCR0_UIX4_3 (0x08UL << DSI_WPCR0_UIX4_Pos)
12333#define DSI_WPCR0_UIX4_4 (0x10UL << DSI_WPCR0_UIX4_Pos)
12334#define DSI_WPCR0_UIX4_5 (0x20UL << DSI_WPCR0_UIX4_Pos)
12336#define DSI_WPCR0_SWCL_Pos (6U)
12337#define DSI_WPCR0_SWCL_Msk (0x1UL << DSI_WPCR0_SWCL_Pos)
12338#define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk
12339#define DSI_WPCR0_SWDL0_Pos (7U)
12340#define DSI_WPCR0_SWDL0_Msk (0x1UL << DSI_WPCR0_SWDL0_Pos)
12341#define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk
12342#define DSI_WPCR0_SWDL1_Pos (8U)
12343#define DSI_WPCR0_SWDL1_Msk (0x1UL << DSI_WPCR0_SWDL1_Pos)
12344#define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk
12345#define DSI_WPCR0_HSICL_Pos (9U)
12346#define DSI_WPCR0_HSICL_Msk (0x1UL << DSI_WPCR0_HSICL_Pos)
12347#define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk
12348#define DSI_WPCR0_HSIDL0_Pos (10U)
12349#define DSI_WPCR0_HSIDL0_Msk (0x1UL << DSI_WPCR0_HSIDL0_Pos)
12350#define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk
12351#define DSI_WPCR0_HSIDL1_Pos (11U)
12352#define DSI_WPCR0_HSIDL1_Msk (0x1UL << DSI_WPCR0_HSIDL1_Pos)
12353#define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk
12354#define DSI_WPCR0_FTXSMCL_Pos (12U)
12355#define DSI_WPCR0_FTXSMCL_Msk (0x1UL << DSI_WPCR0_FTXSMCL_Pos)
12356#define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk
12357#define DSI_WPCR0_FTXSMDL_Pos (13U)
12358#define DSI_WPCR0_FTXSMDL_Msk (0x1UL << DSI_WPCR0_FTXSMDL_Pos)
12359#define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk
12360#define DSI_WPCR0_CDOFFDL_Pos (14U)
12361#define DSI_WPCR0_CDOFFDL_Msk (0x1UL << DSI_WPCR0_CDOFFDL_Pos)
12362#define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk
12363#define DSI_WPCR0_TDDL_Pos (16U)
12364#define DSI_WPCR0_TDDL_Msk (0x1UL << DSI_WPCR0_TDDL_Pos)
12365#define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk
12366#define DSI_WPCR0_PDEN_Pos (18U)
12367#define DSI_WPCR0_PDEN_Msk (0x1UL << DSI_WPCR0_PDEN_Pos)
12368#define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk
12369#define DSI_WPCR0_TCLKPREPEN_Pos (19U)
12370#define DSI_WPCR0_TCLKPREPEN_Msk (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos)
12371#define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk
12372#define DSI_WPCR0_TCLKZEROEN_Pos (20U)
12373#define DSI_WPCR0_TCLKZEROEN_Msk (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos)
12374#define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk
12375#define DSI_WPCR0_THSPREPEN_Pos (21U)
12376#define DSI_WPCR0_THSPREPEN_Msk (0x1UL << DSI_WPCR0_THSPREPEN_Pos)
12377#define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk
12378#define DSI_WPCR0_THSTRAILEN_Pos (22U)
12379#define DSI_WPCR0_THSTRAILEN_Msk (0x1UL << DSI_WPCR0_THSTRAILEN_Pos)
12380#define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk
12381#define DSI_WPCR0_THSZEROEN_Pos (23U)
12382#define DSI_WPCR0_THSZEROEN_Msk (0x1UL << DSI_WPCR0_THSZEROEN_Pos)
12383#define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk
12384#define DSI_WPCR0_TLPXDEN_Pos (24U)
12385#define DSI_WPCR0_TLPXDEN_Msk (0x1UL << DSI_WPCR0_TLPXDEN_Pos)
12386#define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk
12387#define DSI_WPCR0_THSEXITEN_Pos (25U)
12388#define DSI_WPCR0_THSEXITEN_Msk (0x1UL << DSI_WPCR0_THSEXITEN_Pos)
12389#define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk
12390#define DSI_WPCR0_TLPXCEN_Pos (26U)
12391#define DSI_WPCR0_TLPXCEN_Msk (0x1UL << DSI_WPCR0_TLPXCEN_Pos)
12392#define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk
12393#define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
12394#define DSI_WPCR0_TCLKPOSTEN_Msk (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos)
12395#define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk
12397/******************* Bit definition for DSI_WPCR1 register ***************/
12398#define DSI_WPCR1_HSTXDCL_Pos (0U)
12399#define DSI_WPCR1_HSTXDCL_Msk (0x3UL << DSI_WPCR1_HSTXDCL_Pos)
12400#define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk
12401#define DSI_WPCR1_HSTXDCL0_Pos (0U)
12402#define DSI_WPCR1_HSTXDCL0_Msk (0x1UL << DSI_WPCR1_HSTXDCL0_Pos)
12403#define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
12404#define DSI_WPCR1_HSTXDCL1_Pos (1U)
12405#define DSI_WPCR1_HSTXDCL1_Msk (0x1UL << DSI_WPCR1_HSTXDCL1_Pos)
12406#define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
12407
12408#define DSI_WPCR1_HSTXDDL_Pos (2U)
12409#define DSI_WPCR1_HSTXDDL_Msk (0x3UL << DSI_WPCR1_HSTXDDL_Pos)
12410#define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk
12411#define DSI_WPCR1_HSTXDDL0_Pos (2U)
12412#define DSI_WPCR1_HSTXDDL0_Msk (0x1UL << DSI_WPCR1_HSTXDDL0_Pos)
12413#define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
12414#define DSI_WPCR1_HSTXDDL1_Pos (3U)
12415#define DSI_WPCR1_HSTXDDL1_Msk (0x1UL << DSI_WPCR1_HSTXDDL1_Pos)
12416#define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
12417
12418#define DSI_WPCR1_LPSRCCL_Pos (6U)
12419#define DSI_WPCR1_LPSRCCL_Msk (0x3UL << DSI_WPCR1_LPSRCCL_Pos)
12420#define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk
12421#define DSI_WPCR1_LPSRCCL0_Pos (6U)
12422#define DSI_WPCR1_LPSRCCL0_Msk (0x1UL << DSI_WPCR1_LPSRCCL0_Pos)
12423#define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
12424#define DSI_WPCR1_LPSRCCL1_Pos (7U)
12425#define DSI_WPCR1_LPSRCCL1_Msk (0x1UL << DSI_WPCR1_LPSRCCL1_Pos)
12426#define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
12427
12428#define DSI_WPCR1_LPSRCDL_Pos (8U)
12429#define DSI_WPCR1_LPSRCDL_Msk (0x3UL << DSI_WPCR1_LPSRCDL_Pos)
12430#define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk
12431#define DSI_WPCR1_LPSRCDL0_Pos (8U)
12432#define DSI_WPCR1_LPSRCDL0_Msk (0x1UL << DSI_WPCR1_LPSRCDL0_Pos)
12433#define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
12434#define DSI_WPCR1_LPSRCDL1_Pos (9U)
12435#define DSI_WPCR1_LPSRCDL1_Msk (0x1UL << DSI_WPCR1_LPSRCDL1_Pos)
12436#define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
12437
12438#define DSI_WPCR1_SDDC_Pos (12U)
12439#define DSI_WPCR1_SDDC_Msk (0x1UL << DSI_WPCR1_SDDC_Pos)
12440#define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk
12442#define DSI_WPCR1_LPRXVCDL_Pos (14U)
12443#define DSI_WPCR1_LPRXVCDL_Msk (0x3UL << DSI_WPCR1_LPRXVCDL_Pos)
12444#define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk
12445#define DSI_WPCR1_LPRXVCDL0_Pos (14U)
12446#define DSI_WPCR1_LPRXVCDL0_Msk (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos)
12447#define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
12448#define DSI_WPCR1_LPRXVCDL1_Pos (15U)
12449#define DSI_WPCR1_LPRXVCDL1_Msk (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos)
12450#define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
12451
12452#define DSI_WPCR1_HSTXSRCCL_Pos (16U)
12453#define DSI_WPCR1_HSTXSRCCL_Msk (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos)
12454#define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk
12455#define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
12456#define DSI_WPCR1_HSTXSRCCL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos)
12457#define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
12458#define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
12459#define DSI_WPCR1_HSTXSRCCL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos)
12460#define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
12461
12462#define DSI_WPCR1_HSTXSRCDL_Pos (18U)
12463#define DSI_WPCR1_HSTXSRCDL_Msk (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos)
12464#define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk
12465#define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
12466#define DSI_WPCR1_HSTXSRCDL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos)
12467#define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
12468#define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
12469#define DSI_WPCR1_HSTXSRCDL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos)
12470#define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
12471
12472#define DSI_WPCR1_FLPRXLPM_Pos (22U)
12473#define DSI_WPCR1_FLPRXLPM_Msk (0x1UL << DSI_WPCR1_FLPRXLPM_Pos)
12474#define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk
12476#define DSI_WPCR1_LPRXFT_Pos (25U)
12477#define DSI_WPCR1_LPRXFT_Msk (0x3UL << DSI_WPCR1_LPRXFT_Pos)
12478#define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk
12479#define DSI_WPCR1_LPRXFT0_Pos (25U)
12480#define DSI_WPCR1_LPRXFT0_Msk (0x1UL << DSI_WPCR1_LPRXFT0_Pos)
12481#define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
12482#define DSI_WPCR1_LPRXFT1_Pos (26U)
12483#define DSI_WPCR1_LPRXFT1_Msk (0x1UL << DSI_WPCR1_LPRXFT1_Pos)
12484#define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
12485
12486/******************* Bit definition for DSI_WPCR2 register ***************/
12487#define DSI_WPCR2_TCLKPREP_Pos (0U)
12488#define DSI_WPCR2_TCLKPREP_Msk (0xFFUL << DSI_WPCR2_TCLKPREP_Pos)
12489#define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk
12490#define DSI_WPCR2_TCLKPREP0_Pos (0U)
12491#define DSI_WPCR2_TCLKPREP0_Msk (0x1UL << DSI_WPCR2_TCLKPREP0_Pos)
12492#define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
12493#define DSI_WPCR2_TCLKPREP1_Pos (1U)
12494#define DSI_WPCR2_TCLKPREP1_Msk (0x1UL << DSI_WPCR2_TCLKPREP1_Pos)
12495#define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
12496#define DSI_WPCR2_TCLKPREP2_Pos (2U)
12497#define DSI_WPCR2_TCLKPREP2_Msk (0x1UL << DSI_WPCR2_TCLKPREP2_Pos)
12498#define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
12499#define DSI_WPCR2_TCLKPREP3_Pos (3U)
12500#define DSI_WPCR2_TCLKPREP3_Msk (0x1UL << DSI_WPCR2_TCLKPREP3_Pos)
12501#define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
12502#define DSI_WPCR2_TCLKPREP4_Pos (4U)
12503#define DSI_WPCR2_TCLKPREP4_Msk (0x1UL << DSI_WPCR2_TCLKPREP4_Pos)
12504#define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
12505#define DSI_WPCR2_TCLKPREP5_Pos (5U)
12506#define DSI_WPCR2_TCLKPREP5_Msk (0x1UL << DSI_WPCR2_TCLKPREP5_Pos)
12507#define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
12508#define DSI_WPCR2_TCLKPREP6_Pos (6U)
12509#define DSI_WPCR2_TCLKPREP6_Msk (0x1UL << DSI_WPCR2_TCLKPREP6_Pos)
12510#define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
12511#define DSI_WPCR2_TCLKPREP7_Pos (7U)
12512#define DSI_WPCR2_TCLKPREP7_Msk (0x1UL << DSI_WPCR2_TCLKPREP7_Pos)
12513#define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
12514
12515#define DSI_WPCR2_TCLKZERO_Pos (8U)
12516#define DSI_WPCR2_TCLKZERO_Msk (0xFFUL << DSI_WPCR2_TCLKZERO_Pos)
12517#define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk
12518#define DSI_WPCR2_TCLKZERO0_Pos (8U)
12519#define DSI_WPCR2_TCLKZERO0_Msk (0x1UL << DSI_WPCR2_TCLKZERO0_Pos)
12520#define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
12521#define DSI_WPCR2_TCLKZERO1_Pos (9U)
12522#define DSI_WPCR2_TCLKZERO1_Msk (0x1UL << DSI_WPCR2_TCLKZERO1_Pos)
12523#define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
12524#define DSI_WPCR2_TCLKZERO2_Pos (10U)
12525#define DSI_WPCR2_TCLKZERO2_Msk (0x1UL << DSI_WPCR2_TCLKZERO2_Pos)
12526#define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
12527#define DSI_WPCR2_TCLKZERO3_Pos (11U)
12528#define DSI_WPCR2_TCLKZERO3_Msk (0x1UL << DSI_WPCR2_TCLKZERO3_Pos)
12529#define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
12530#define DSI_WPCR2_TCLKZERO4_Pos (12U)
12531#define DSI_WPCR2_TCLKZERO4_Msk (0x1UL << DSI_WPCR2_TCLKZERO4_Pos)
12532#define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
12533#define DSI_WPCR2_TCLKZERO5_Pos (13U)
12534#define DSI_WPCR2_TCLKZERO5_Msk (0x1UL << DSI_WPCR2_TCLKZERO5_Pos)
12535#define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
12536#define DSI_WPCR2_TCLKZERO6_Pos (14U)
12537#define DSI_WPCR2_TCLKZERO6_Msk (0x1UL << DSI_WPCR2_TCLKZERO6_Pos)
12538#define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
12539#define DSI_WPCR2_TCLKZERO7_Pos (15U)
12540#define DSI_WPCR2_TCLKZERO7_Msk (0x1UL << DSI_WPCR2_TCLKZERO7_Pos)
12541#define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
12542
12543#define DSI_WPCR2_THSPREP_Pos (16U)
12544#define DSI_WPCR2_THSPREP_Msk (0xFFUL << DSI_WPCR2_THSPREP_Pos)
12545#define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk
12546#define DSI_WPCR2_THSPREP0_Pos (16U)
12547#define DSI_WPCR2_THSPREP0_Msk (0x1UL << DSI_WPCR2_THSPREP0_Pos)
12548#define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
12549#define DSI_WPCR2_THSPREP1_Pos (17U)
12550#define DSI_WPCR2_THSPREP1_Msk (0x1UL << DSI_WPCR2_THSPREP1_Pos)
12551#define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
12552#define DSI_WPCR2_THSPREP2_Pos (18U)
12553#define DSI_WPCR2_THSPREP2_Msk (0x1UL << DSI_WPCR2_THSPREP2_Pos)
12554#define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
12555#define DSI_WPCR2_THSPREP3_Pos (19U)
12556#define DSI_WPCR2_THSPREP3_Msk (0x1UL << DSI_WPCR2_THSPREP3_Pos)
12557#define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
12558#define DSI_WPCR2_THSPREP4_Pos (20U)
12559#define DSI_WPCR2_THSPREP4_Msk (0x1UL << DSI_WPCR2_THSPREP4_Pos)
12560#define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
12561#define DSI_WPCR2_THSPREP5_Pos (21U)
12562#define DSI_WPCR2_THSPREP5_Msk (0x1UL << DSI_WPCR2_THSPREP5_Pos)
12563#define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
12564#define DSI_WPCR2_THSPREP6_Pos (22U)
12565#define DSI_WPCR2_THSPREP6_Msk (0x1UL << DSI_WPCR2_THSPREP6_Pos)
12566#define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
12567#define DSI_WPCR2_THSPREP7_Pos (23U)
12568#define DSI_WPCR2_THSPREP7_Msk (0x1UL << DSI_WPCR2_THSPREP7_Pos)
12569#define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
12570
12571#define DSI_WPCR2_THSTRAIL_Pos (24U)
12572#define DSI_WPCR2_THSTRAIL_Msk (0xFFUL << DSI_WPCR2_THSTRAIL_Pos)
12573#define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk
12574#define DSI_WPCR2_THSTRAIL0_Pos (24U)
12575#define DSI_WPCR2_THSTRAIL0_Msk (0x1UL << DSI_WPCR2_THSTRAIL0_Pos)
12576#define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
12577#define DSI_WPCR2_THSTRAIL1_Pos (25U)
12578#define DSI_WPCR2_THSTRAIL1_Msk (0x1UL << DSI_WPCR2_THSTRAIL1_Pos)
12579#define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
12580#define DSI_WPCR2_THSTRAIL2_Pos (26U)
12581#define DSI_WPCR2_THSTRAIL2_Msk (0x1UL << DSI_WPCR2_THSTRAIL2_Pos)
12582#define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
12583#define DSI_WPCR2_THSTRAIL3_Pos (27U)
12584#define DSI_WPCR2_THSTRAIL3_Msk (0x1UL << DSI_WPCR2_THSTRAIL3_Pos)
12585#define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
12586#define DSI_WPCR2_THSTRAIL4_Pos (28U)
12587#define DSI_WPCR2_THSTRAIL4_Msk (0x1UL << DSI_WPCR2_THSTRAIL4_Pos)
12588#define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
12589#define DSI_WPCR2_THSTRAIL5_Pos (29U)
12590#define DSI_WPCR2_THSTRAIL5_Msk (0x1UL << DSI_WPCR2_THSTRAIL5_Pos)
12591#define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
12592#define DSI_WPCR2_THSTRAIL6_Pos (30U)
12593#define DSI_WPCR2_THSTRAIL6_Msk (0x1UL << DSI_WPCR2_THSTRAIL6_Pos)
12594#define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
12595#define DSI_WPCR2_THSTRAIL7_Pos (31U)
12596#define DSI_WPCR2_THSTRAIL7_Msk (0x1UL << DSI_WPCR2_THSTRAIL7_Pos)
12597#define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
12598
12599/******************* Bit definition for DSI_WPCR3 register ***************/
12600#define DSI_WPCR3_THSZERO_Pos (0U)
12601#define DSI_WPCR3_THSZERO_Msk (0xFFUL << DSI_WPCR3_THSZERO_Pos)
12602#define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk
12603#define DSI_WPCR3_THSZERO0_Pos (0U)
12604#define DSI_WPCR3_THSZERO0_Msk (0x1UL << DSI_WPCR3_THSZERO0_Pos)
12605#define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
12606#define DSI_WPCR3_THSZERO1_Pos (1U)
12607#define DSI_WPCR3_THSZERO1_Msk (0x1UL << DSI_WPCR3_THSZERO1_Pos)
12608#define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
12609#define DSI_WPCR3_THSZERO2_Pos (2U)
12610#define DSI_WPCR3_THSZERO2_Msk (0x1UL << DSI_WPCR3_THSZERO2_Pos)
12611#define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
12612#define DSI_WPCR3_THSZERO3_Pos (3U)
12613#define DSI_WPCR3_THSZERO3_Msk (0x1UL << DSI_WPCR3_THSZERO3_Pos)
12614#define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
12615#define DSI_WPCR3_THSZERO4_Pos (4U)
12616#define DSI_WPCR3_THSZERO4_Msk (0x1UL << DSI_WPCR3_THSZERO4_Pos)
12617#define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
12618#define DSI_WPCR3_THSZERO5_Pos (5U)
12619#define DSI_WPCR3_THSZERO5_Msk (0x1UL << DSI_WPCR3_THSZERO5_Pos)
12620#define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
12621#define DSI_WPCR3_THSZERO6_Pos (6U)
12622#define DSI_WPCR3_THSZERO6_Msk (0x1UL << DSI_WPCR3_THSZERO6_Pos)
12623#define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
12624#define DSI_WPCR3_THSZERO7_Pos (7U)
12625#define DSI_WPCR3_THSZERO7_Msk (0x1UL << DSI_WPCR3_THSZERO7_Pos)
12626#define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
12627
12628#define DSI_WPCR3_TLPXD_Pos (8U)
12629#define DSI_WPCR3_TLPXD_Msk (0xFFUL << DSI_WPCR3_TLPXD_Pos)
12630#define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk
12631#define DSI_WPCR3_TLPXD0_Pos (8U)
12632#define DSI_WPCR3_TLPXD0_Msk (0x1UL << DSI_WPCR3_TLPXD0_Pos)
12633#define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
12634#define DSI_WPCR3_TLPXD1_Pos (9U)
12635#define DSI_WPCR3_TLPXD1_Msk (0x1UL << DSI_WPCR3_TLPXD1_Pos)
12636#define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
12637#define DSI_WPCR3_TLPXD2_Pos (10U)
12638#define DSI_WPCR3_TLPXD2_Msk (0x1UL << DSI_WPCR3_TLPXD2_Pos)
12639#define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
12640#define DSI_WPCR3_TLPXD3_Pos (11U)
12641#define DSI_WPCR3_TLPXD3_Msk (0x1UL << DSI_WPCR3_TLPXD3_Pos)
12642#define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
12643#define DSI_WPCR3_TLPXD4_Pos (12U)
12644#define DSI_WPCR3_TLPXD4_Msk (0x1UL << DSI_WPCR3_TLPXD4_Pos)
12645#define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
12646#define DSI_WPCR3_TLPXD5_Pos (13U)
12647#define DSI_WPCR3_TLPXD5_Msk (0x1UL << DSI_WPCR3_TLPXD5_Pos)
12648#define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
12649#define DSI_WPCR3_TLPXD6_Pos (14U)
12650#define DSI_WPCR3_TLPXD6_Msk (0x1UL << DSI_WPCR3_TLPXD6_Pos)
12651#define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
12652#define DSI_WPCR3_TLPXD7_Pos (15U)
12653#define DSI_WPCR3_TLPXD7_Msk (0x1UL << DSI_WPCR3_TLPXD7_Pos)
12654#define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
12655
12656#define DSI_WPCR3_THSEXIT_Pos (16U)
12657#define DSI_WPCR3_THSEXIT_Msk (0xFFUL << DSI_WPCR3_THSEXIT_Pos)
12658#define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk
12659#define DSI_WPCR3_THSEXIT0_Pos (16U)
12660#define DSI_WPCR3_THSEXIT0_Msk (0x1UL << DSI_WPCR3_THSEXIT0_Pos)
12661#define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
12662#define DSI_WPCR3_THSEXIT1_Pos (17U)
12663#define DSI_WPCR3_THSEXIT1_Msk (0x1UL << DSI_WPCR3_THSEXIT1_Pos)
12664#define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
12665#define DSI_WPCR3_THSEXIT2_Pos (18U)
12666#define DSI_WPCR3_THSEXIT2_Msk (0x1UL << DSI_WPCR3_THSEXIT2_Pos)
12667#define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
12668#define DSI_WPCR3_THSEXIT3_Pos (19U)
12669#define DSI_WPCR3_THSEXIT3_Msk (0x1UL << DSI_WPCR3_THSEXIT3_Pos)
12670#define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
12671#define DSI_WPCR3_THSEXIT4_Pos (20U)
12672#define DSI_WPCR3_THSEXIT4_Msk (0x1UL << DSI_WPCR3_THSEXIT4_Pos)
12673#define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
12674#define DSI_WPCR3_THSEXIT5_Pos (21U)
12675#define DSI_WPCR3_THSEXIT5_Msk (0x1UL << DSI_WPCR3_THSEXIT5_Pos)
12676#define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
12677#define DSI_WPCR3_THSEXIT6_Pos (22U)
12678#define DSI_WPCR3_THSEXIT6_Msk (0x1UL << DSI_WPCR3_THSEXIT6_Pos)
12679#define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
12680#define DSI_WPCR3_THSEXIT7_Pos (23U)
12681#define DSI_WPCR3_THSEXIT7_Msk (0x1UL << DSI_WPCR3_THSEXIT7_Pos)
12682#define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
12683
12684#define DSI_WPCR3_TLPXC_Pos (24U)
12685#define DSI_WPCR3_TLPXC_Msk (0xFFUL << DSI_WPCR3_TLPXC_Pos)
12686#define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk
12687#define DSI_WPCR3_TLPXC0_Pos (24U)
12688#define DSI_WPCR3_TLPXC0_Msk (0x1UL << DSI_WPCR3_TLPXC0_Pos)
12689#define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
12690#define DSI_WPCR3_TLPXC1_Pos (25U)
12691#define DSI_WPCR3_TLPXC1_Msk (0x1UL << DSI_WPCR3_TLPXC1_Pos)
12692#define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
12693#define DSI_WPCR3_TLPXC2_Pos (26U)
12694#define DSI_WPCR3_TLPXC2_Msk (0x1UL << DSI_WPCR3_TLPXC2_Pos)
12695#define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
12696#define DSI_WPCR3_TLPXC3_Pos (27U)
12697#define DSI_WPCR3_TLPXC3_Msk (0x1UL << DSI_WPCR3_TLPXC3_Pos)
12698#define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
12699#define DSI_WPCR3_TLPXC4_Pos (28U)
12700#define DSI_WPCR3_TLPXC4_Msk (0x1UL << DSI_WPCR3_TLPXC4_Pos)
12701#define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
12702#define DSI_WPCR3_TLPXC5_Pos (29U)
12703#define DSI_WPCR3_TLPXC5_Msk (0x1UL << DSI_WPCR3_TLPXC5_Pos)
12704#define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
12705#define DSI_WPCR3_TLPXC6_Pos (30U)
12706#define DSI_WPCR3_TLPXC6_Msk (0x1UL << DSI_WPCR3_TLPXC6_Pos)
12707#define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
12708#define DSI_WPCR3_TLPXC7_Pos (31U)
12709#define DSI_WPCR3_TLPXC7_Msk (0x1UL << DSI_WPCR3_TLPXC7_Pos)
12710#define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
12711
12712/******************* Bit definition for DSI_WPCR4 register ***************/
12713#define DSI_WPCR4_TCLKPOST_Pos (0U)
12714#define DSI_WPCR4_TCLKPOST_Msk (0xFFUL << DSI_WPCR4_TCLKPOST_Pos)
12715#define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk
12716#define DSI_WPCR4_TCLKPOST0_Pos (0U)
12717#define DSI_WPCR4_TCLKPOST0_Msk (0x1UL << DSI_WPCR4_TCLKPOST0_Pos)
12718#define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
12719#define DSI_WPCR4_TCLKPOST1_Pos (1U)
12720#define DSI_WPCR4_TCLKPOST1_Msk (0x1UL << DSI_WPCR4_TCLKPOST1_Pos)
12721#define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
12722#define DSI_WPCR4_TCLKPOST2_Pos (2U)
12723#define DSI_WPCR4_TCLKPOST2_Msk (0x1UL << DSI_WPCR4_TCLKPOST2_Pos)
12724#define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
12725#define DSI_WPCR4_TCLKPOST3_Pos (3U)
12726#define DSI_WPCR4_TCLKPOST3_Msk (0x1UL << DSI_WPCR4_TCLKPOST3_Pos)
12727#define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
12728#define DSI_WPCR4_TCLKPOST4_Pos (4U)
12729#define DSI_WPCR4_TCLKPOST4_Msk (0x1UL << DSI_WPCR4_TCLKPOST4_Pos)
12730#define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
12731#define DSI_WPCR4_TCLKPOST5_Pos (5U)
12732#define DSI_WPCR4_TCLKPOST5_Msk (0x1UL << DSI_WPCR4_TCLKPOST5_Pos)
12733#define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
12734#define DSI_WPCR4_TCLKPOST6_Pos (6U)
12735#define DSI_WPCR4_TCLKPOST6_Msk (0x1UL << DSI_WPCR4_TCLKPOST6_Pos)
12736#define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
12737#define DSI_WPCR4_TCLKPOST7_Pos (7U)
12738#define DSI_WPCR4_TCLKPOST7_Msk (0x1UL << DSI_WPCR4_TCLKPOST7_Pos)
12739#define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
12740
12741/******************* Bit definition for DSI_WRPCR register ***************/
12742#define DSI_WRPCR_PLLEN_Pos (0U)
12743#define DSI_WRPCR_PLLEN_Msk (0x1UL << DSI_WRPCR_PLLEN_Pos)
12744#define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk
12745#define DSI_WRPCR_PLL_NDIV_Pos (2U)
12746#define DSI_WRPCR_PLL_NDIV_Msk (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos)
12747#define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk
12748#define DSI_WRPCR_PLL_NDIV0_Pos (2U)
12749#define DSI_WRPCR_PLL_NDIV0_Msk (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos)
12750#define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
12751#define DSI_WRPCR_PLL_NDIV1_Pos (3U)
12752#define DSI_WRPCR_PLL_NDIV1_Msk (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos)
12753#define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
12754#define DSI_WRPCR_PLL_NDIV2_Pos (4U)
12755#define DSI_WRPCR_PLL_NDIV2_Msk (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos)
12756#define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
12757#define DSI_WRPCR_PLL_NDIV3_Pos (5U)
12758#define DSI_WRPCR_PLL_NDIV3_Msk (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos)
12759#define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
12760#define DSI_WRPCR_PLL_NDIV4_Pos (6U)
12761#define DSI_WRPCR_PLL_NDIV4_Msk (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos)
12762#define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
12763#define DSI_WRPCR_PLL_NDIV5_Pos (7U)
12764#define DSI_WRPCR_PLL_NDIV5_Msk (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos)
12765#define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
12766#define DSI_WRPCR_PLL_NDIV6_Pos (8U)
12767#define DSI_WRPCR_PLL_NDIV6_Msk (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos)
12768#define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
12769
12770#define DSI_WRPCR_PLL_IDF_Pos (11U)
12771#define DSI_WRPCR_PLL_IDF_Msk (0xFUL << DSI_WRPCR_PLL_IDF_Pos)
12772#define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk
12773#define DSI_WRPCR_PLL_IDF0_Pos (11U)
12774#define DSI_WRPCR_PLL_IDF0_Msk (0x1UL << DSI_WRPCR_PLL_IDF0_Pos)
12775#define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
12776#define DSI_WRPCR_PLL_IDF1_Pos (12U)
12777#define DSI_WRPCR_PLL_IDF1_Msk (0x1UL << DSI_WRPCR_PLL_IDF1_Pos)
12778#define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
12779#define DSI_WRPCR_PLL_IDF2_Pos (13U)
12780#define DSI_WRPCR_PLL_IDF2_Msk (0x1UL << DSI_WRPCR_PLL_IDF2_Pos)
12781#define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
12782#define DSI_WRPCR_PLL_IDF3_Pos (14U)
12783#define DSI_WRPCR_PLL_IDF3_Msk (0x1UL << DSI_WRPCR_PLL_IDF3_Pos)
12784#define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
12785
12786#define DSI_WRPCR_PLL_ODF_Pos (16U)
12787#define DSI_WRPCR_PLL_ODF_Msk (0x3UL << DSI_WRPCR_PLL_ODF_Pos)
12788#define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk
12789#define DSI_WRPCR_PLL_ODF0_Pos (16U)
12790#define DSI_WRPCR_PLL_ODF0_Msk (0x1UL << DSI_WRPCR_PLL_ODF0_Pos)
12791#define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
12792#define DSI_WRPCR_PLL_ODF1_Pos (17U)
12793#define DSI_WRPCR_PLL_ODF1_Msk (0x1UL << DSI_WRPCR_PLL_ODF1_Pos)
12794#define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
12795
12796#define DSI_WRPCR_REGEN_Pos (24U)
12797#define DSI_WRPCR_REGEN_Msk (0x1UL << DSI_WRPCR_REGEN_Pos)
12798#define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk
12800/******************************************************************************/
12801/* */
12802/* External Interrupt/Event Controller */
12803/* */
12804/******************************************************************************/
12805/****************** Bit definition for EXTI_RTSR1 register *******************/
12806#define EXTI_RTSR1_TR_Pos (0U)
12807#define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)
12808#define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk
12809#define EXTI_RTSR1_TR0_Pos (0U)
12810#define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos)
12811#define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk
12812#define EXTI_RTSR1_TR1_Pos (1U)
12813#define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos)
12814#define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk
12815#define EXTI_RTSR1_TR2_Pos (2U)
12816#define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos)
12817#define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk
12818#define EXTI_RTSR1_TR3_Pos (3U)
12819#define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos)
12820#define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk
12821#define EXTI_RTSR1_TR4_Pos (4U)
12822#define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos)
12823#define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk
12824#define EXTI_RTSR1_TR5_Pos (5U)
12825#define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos)
12826#define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk
12827#define EXTI_RTSR1_TR6_Pos (6U)
12828#define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos)
12829#define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk
12830#define EXTI_RTSR1_TR7_Pos (7U)
12831#define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos)
12832#define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk
12833#define EXTI_RTSR1_TR8_Pos (8U)
12834#define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos)
12835#define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk
12836#define EXTI_RTSR1_TR9_Pos (9U)
12837#define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos)
12838#define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk
12839#define EXTI_RTSR1_TR10_Pos (10U)
12840#define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos)
12841#define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk
12842#define EXTI_RTSR1_TR11_Pos (11U)
12843#define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos)
12844#define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk
12845#define EXTI_RTSR1_TR12_Pos (12U)
12846#define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos)
12847#define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk
12848#define EXTI_RTSR1_TR13_Pos (13U)
12849#define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos)
12850#define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk
12851#define EXTI_RTSR1_TR14_Pos (14U)
12852#define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos)
12853#define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk
12854#define EXTI_RTSR1_TR15_Pos (15U)
12855#define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos)
12856#define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk
12857#define EXTI_RTSR1_TR16_Pos (16U)
12858#define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos)
12859#define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk
12860#define EXTI_RTSR1_TR17_Pos (17U)
12861#define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos)
12862#define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk
12863#define EXTI_RTSR1_TR18_Pos (18U)
12864#define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos)
12865#define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk
12866#define EXTI_RTSR1_TR19_Pos (19U)
12867#define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos)
12868#define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk
12869#define EXTI_RTSR1_TR20_Pos (20U)
12870#define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos)
12871#define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk
12872#define EXTI_RTSR1_TR21_Pos (21U)
12873#define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos)
12874#define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk
12876/****************** Bit definition for EXTI_FTSR1 register *******************/
12877#define EXTI_FTSR1_TR_Pos (0U)
12878#define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)
12879#define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk
12880#define EXTI_FTSR1_TR0_Pos (0U)
12881#define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos)
12882#define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk
12883#define EXTI_FTSR1_TR1_Pos (1U)
12884#define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos)
12885#define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk
12886#define EXTI_FTSR1_TR2_Pos (2U)
12887#define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos)
12888#define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk
12889#define EXTI_FTSR1_TR3_Pos (3U)
12890#define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos)
12891#define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk
12892#define EXTI_FTSR1_TR4_Pos (4U)
12893#define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos)
12894#define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk
12895#define EXTI_FTSR1_TR5_Pos (5U)
12896#define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos)
12897#define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk
12898#define EXTI_FTSR1_TR6_Pos (6U)
12899#define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos)
12900#define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk
12901#define EXTI_FTSR1_TR7_Pos (7U)
12902#define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos)
12903#define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk
12904#define EXTI_FTSR1_TR8_Pos (8U)
12905#define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos)
12906#define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk
12907#define EXTI_FTSR1_TR9_Pos (9U)
12908#define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos)
12909#define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk
12910#define EXTI_FTSR1_TR10_Pos (10U)
12911#define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos)
12912#define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk
12913#define EXTI_FTSR1_TR11_Pos (11U)
12914#define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos)
12915#define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk
12916#define EXTI_FTSR1_TR12_Pos (12U)
12917#define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos)
12918#define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk
12919#define EXTI_FTSR1_TR13_Pos (13U)
12920#define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos)
12921#define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk
12922#define EXTI_FTSR1_TR14_Pos (14U)
12923#define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos)
12924#define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk
12925#define EXTI_FTSR1_TR15_Pos (15U)
12926#define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos)
12927#define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk
12928#define EXTI_FTSR1_TR16_Pos (16U)
12929#define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos)
12930#define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk
12931#define EXTI_FTSR1_TR17_Pos (17U)
12932#define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos)
12933#define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk
12934#define EXTI_FTSR1_TR18_Pos (18U)
12935#define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos)
12936#define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk
12937#define EXTI_FTSR1_TR19_Pos (19U)
12938#define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos)
12939#define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk
12940#define EXTI_FTSR1_TR20_Pos (20U)
12941#define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos)
12942#define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk
12943#define EXTI_FTSR1_TR21_Pos (21U)
12944#define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos)
12945#define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk
12947/****************** Bit definition for EXTI_SWIER1 register ******************/
12948#define EXTI_SWIER1_SWIER0_Pos (0U)
12949#define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos)
12950#define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk
12951#define EXTI_SWIER1_SWIER1_Pos (1U)
12952#define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos)
12953#define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk
12954#define EXTI_SWIER1_SWIER2_Pos (2U)
12955#define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos)
12956#define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk
12957#define EXTI_SWIER1_SWIER3_Pos (3U)
12958#define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos)
12959#define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk
12960#define EXTI_SWIER1_SWIER4_Pos (4U)
12961#define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos)
12962#define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk
12963#define EXTI_SWIER1_SWIER5_Pos (5U)
12964#define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos)
12965#define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk
12966#define EXTI_SWIER1_SWIER6_Pos (6U)
12967#define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos)
12968#define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk
12969#define EXTI_SWIER1_SWIER7_Pos (7U)
12970#define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos)
12971#define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk
12972#define EXTI_SWIER1_SWIER8_Pos (8U)
12973#define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos)
12974#define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk
12975#define EXTI_SWIER1_SWIER9_Pos (9U)
12976#define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos)
12977#define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk
12978#define EXTI_SWIER1_SWIER10_Pos (10U)
12979#define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos)
12980#define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk
12981#define EXTI_SWIER1_SWIER11_Pos (11U)
12982#define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos)
12983#define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk
12984#define EXTI_SWIER1_SWIER12_Pos (12U)
12985#define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos)
12986#define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk
12987#define EXTI_SWIER1_SWIER13_Pos (13U)
12988#define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos)
12989#define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk
12990#define EXTI_SWIER1_SWIER14_Pos (14U)
12991#define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos)
12992#define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk
12993#define EXTI_SWIER1_SWIER15_Pos (15U)
12994#define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos)
12995#define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk
12996#define EXTI_SWIER1_SWIER16_Pos (16U)
12997#define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos)
12998#define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk
12999#define EXTI_SWIER1_SWIER17_Pos (17U)
13000#define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos)
13001#define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk
13002#define EXTI_SWIER1_SWIER18_Pos (18U)
13003#define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos)
13004#define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk
13005#define EXTI_SWIER1_SWIER19_Pos (19U)
13006#define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos)
13007#define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk
13008#define EXTI_SWIER1_SWIER20_Pos (20U)
13009#define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos)
13010#define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk
13011#define EXTI_SWIER1_SWIER21_Pos (21U)
13012#define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos)
13013#define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk
13015/****************** Bit definition for EXTI_D3PMR1 register ******************/
13016#define EXTI_D3PMR1_MR0_Pos (0U)
13017#define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos)
13018#define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk
13019#define EXTI_D3PMR1_MR1_Pos (1U)
13020#define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos)
13021#define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk
13022#define EXTI_D3PMR1_MR2_Pos (2U)
13023#define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos)
13024#define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk
13025#define EXTI_D3PMR1_MR3_Pos (3U)
13026#define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos)
13027#define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk
13028#define EXTI_D3PMR1_MR4_Pos (4U)
13029#define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos)
13030#define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk
13031#define EXTI_D3PMR1_MR5_Pos (5U)
13032#define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos)
13033#define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk
13034#define EXTI_D3PMR1_MR6_Pos (6U)
13035#define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos)
13036#define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk
13037#define EXTI_D3PMR1_MR7_Pos (7U)
13038#define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos)
13039#define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk
13040#define EXTI_D3PMR1_MR8_Pos (8U)
13041#define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos)
13042#define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk
13043#define EXTI_D3PMR1_MR9_Pos (9U)
13044#define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos)
13045#define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk
13046#define EXTI_D3PMR1_MR10_Pos (10U)
13047#define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos)
13048#define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk
13049#define EXTI_D3PMR1_MR11_Pos (11U)
13050#define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos)
13051#define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk
13052#define EXTI_D3PMR1_MR12_Pos (12U)
13053#define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos)
13054#define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk
13055#define EXTI_D3PMR1_MR13_Pos (13U)
13056#define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos)
13057#define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk
13058#define EXTI_D3PMR1_MR14_Pos (14U)
13059#define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos)
13060#define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk
13061#define EXTI_D3PMR1_MR15_Pos (15U)
13062#define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos)
13063#define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk
13064#define EXTI_D3PMR1_MR19_Pos (19U)
13065#define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos)
13066#define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk
13067#define EXTI_D3PMR1_MR20_Pos (20U)
13068#define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos)
13069#define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk
13070#define EXTI_D3PMR1_MR21_Pos (21U)
13071#define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos)
13072#define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk
13073#define EXTI_D3PMR1_MR25_Pos (24U)
13074#define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos)
13075#define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk
13077/******************* Bit definition for EXTI_D3PCR1L register ****************/
13078#define EXTI_D3PCR1L_PCS0_Pos (0U)
13079#define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos)
13080#define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk
13081#define EXTI_D3PCR1L_PCS1_Pos (2U)
13082#define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos)
13083#define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk
13084#define EXTI_D3PCR1L_PCS2_Pos (4U)
13085#define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos)
13086#define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk
13087#define EXTI_D3PCR1L_PCS3_Pos (6U)
13088#define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos)
13089#define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk
13090#define EXTI_D3PCR1L_PCS4_Pos (8U)
13091#define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos)
13092#define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk
13093#define EXTI_D3PCR1L_PCS5_Pos (10U)
13094#define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos)
13095#define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk
13096#define EXTI_D3PCR1L_PCS6_Pos (12U)
13097#define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos)
13098#define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk
13099#define EXTI_D3PCR1L_PCS7_Pos (14U)
13100#define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos)
13101#define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk
13102#define EXTI_D3PCR1L_PCS8_Pos (16U)
13103#define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos)
13104#define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk
13105#define EXTI_D3PCR1L_PCS9_Pos (18U)
13106#define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos)
13107#define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk
13108#define EXTI_D3PCR1L_PCS10_Pos (20U)
13109#define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos)
13110#define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk
13111#define EXTI_D3PCR1L_PCS11_Pos (22U)
13112#define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos)
13113#define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk
13114#define EXTI_D3PCR1L_PCS12_Pos (24U)
13115#define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos)
13116#define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk
13117#define EXTI_D3PCR1L_PCS13_Pos (26U)
13118#define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos)
13119#define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk
13120#define EXTI_D3PCR1L_PCS14_Pos (28U)
13121#define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos)
13122#define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk
13123#define EXTI_D3PCR1L_PCS15_Pos (30U)
13124#define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos)
13125#define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk
13127/******************* Bit definition for EXTI_D3PCR1H register ****************/
13128#define EXTI_D3PCR1H_PCS19_Pos (6U)
13129#define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos)
13130#define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk
13131#define EXTI_D3PCR1H_PCS20_Pos (8U)
13132#define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos)
13133#define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk
13134#define EXTI_D3PCR1H_PCS21_Pos (10U)
13135#define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos)
13136#define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk
13137#define EXTI_D3PCR1H_PCS25_Pos (18U)
13138#define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos)
13139#define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk
13141/****************** Bit definition for EXTI_RTSR2 register *******************/
13142#define EXTI_RTSR2_TR_Pos (17U)
13143#define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos)
13144#define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk
13145#define EXTI_RTSR2_TR49_Pos (17U)
13146#define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos)
13147#define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk
13148#define EXTI_RTSR2_TR51_Pos (19U)
13149#define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos)
13150#define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk
13152/****************** Bit definition for EXTI_FTSR2 register *******************/
13153#define EXTI_FTSR2_TR_Pos (17U)
13154#define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos)
13155#define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk
13156#define EXTI_FTSR2_TR49_Pos (17U)
13157#define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos)
13158#define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk
13159#define EXTI_FTSR2_TR51_Pos (19U)
13160#define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos)
13161#define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk
13163/****************** Bit definition for EXTI_SWIER2 register ******************/
13164#define EXTI_SWIER2_SWIER49_Pos (17U)
13165#define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos)
13166#define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk
13167#define EXTI_SWIER2_SWIER51_Pos (19U)
13168#define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos)
13169#define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk
13171/****************** Bit definition for EXTI_D3PMR2 register ******************/
13172#define EXTI_D3PMR2_MR34_Pos (2U)
13173#define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos)
13174#define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk
13175#define EXTI_D3PMR2_MR35_Pos (3U)
13176#define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos)
13177#define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk
13178#define EXTI_D3PMR2_MR41_Pos (9U)
13179#define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos)
13180#define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk
13181#define EXTI_D3PMR2_MR48_Pos (16U)
13182#define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos)
13183#define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk
13184#define EXTI_D3PMR2_MR49_Pos (17U)
13185#define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos)
13186#define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk
13187#define EXTI_D3PMR2_MR50_Pos (18U)
13188#define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos)
13189#define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk
13190#define EXTI_D3PMR2_MR51_Pos (19U)
13191#define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos)
13192#define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk
13193#define EXTI_D3PMR2_MR52_Pos (20U)
13194#define EXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos)
13195#define EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk
13196#define EXTI_D3PMR2_MR53_Pos (21U)
13197#define EXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos)
13198#define EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk
13199/******************* Bit definition for EXTI_D3PCR2L register ****************/
13200#define EXTI_D3PCR2L_PCS34_Pos (4U)
13201#define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos)
13202#define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk
13203#define EXTI_D3PCR2L_PCS35_Pos (6U)
13204#define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos)
13205#define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk
13206#define EXTI_D3PCR2L_PCS41_Pos (18U)
13207#define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos)
13208#define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk
13211/******************* Bit definition for EXTI_D3PCR2H register ****************/
13212#define EXTI_D3PCR2H_PCS48_Pos (0U)
13213#define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos)
13214#define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk
13215#define EXTI_D3PCR2H_PCS49_Pos (2U)
13216#define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos)
13217#define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk
13218#define EXTI_D3PCR2H_PCS50_Pos (4U)
13219#define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos)
13220#define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk
13221#define EXTI_D3PCR2H_PCS51_Pos (6U)
13222#define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos)
13223#define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk
13224#define EXTI_D3PCR2H_PCS52_Pos (8U)
13225#define EXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos)
13226#define EXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk
13227#define EXTI_D3PCR2H_PCS53_Pos (10U)
13228#define EXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos)
13229#define EXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk
13230/****************** Bit definition for EXTI_RTSR3 register *******************/
13231#define EXTI_RTSR3_TR_Pos (18U)
13232#define EXTI_RTSR3_TR_Msk (0x1DUL << EXTI_RTSR3_TR_Pos)
13233#define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk
13234#define EXTI_RTSR3_TR82_Pos (18U)
13235#define EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos)
13236#define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk
13237#define EXTI_RTSR3_TR84_Pos (20U)
13238#define EXTI_RTSR3_TR84_Msk (0x1UL << EXTI_RTSR3_TR84_Pos)
13239#define EXTI_RTSR3_TR84 EXTI_RTSR3_TR84_Msk
13240#define EXTI_RTSR3_TR85_Pos (21U)
13241#define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos)
13242#define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk
13243#define EXTI_RTSR3_TR86_Pos (22U)
13244#define EXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos)
13245#define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk
13247/****************** Bit definition for EXTI_FTSR3 register *******************/
13248#define EXTI_FTSR3_TR_Pos (18U)
13249#define EXTI_FTSR3_TR_Msk (0x1DUL << EXTI_FTSR3_TR_Pos)
13250#define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk
13251#define EXTI_FTSR3_TR82_Pos (18U)
13252#define EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos)
13253#define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk
13254#define EXTI_FTSR3_TR84_Pos (20U)
13255#define EXTI_FTSR3_TR84_Msk (0x1UL << EXTI_FTSR3_TR84_Pos)
13256#define EXTI_FTSR3_TR84 EXTI_FTSR3_TR84_Msk
13257#define EXTI_FTSR3_TR85_Pos (21U)
13258#define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos)
13259#define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk
13260#define EXTI_FTSR3_TR86_Pos (22U)
13261#define EXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos)
13262#define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk
13264/****************** Bit definition for EXTI_SWIER3 register ******************/
13265#define EXTI_SWIER3_SWI_Pos (18U)
13266#define EXTI_SWIER3_SWI_Msk (0x1DUL << EXTI_SWIER3_SWI_Pos)
13267#define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk
13268#define EXTI_SWIER3_SWIER82_Pos (18U)
13269#define EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos)
13270#define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk
13271#define EXTI_SWIER3_SWIER84_Pos (20U)
13272#define EXTI_SWIER3_SWIER84_Msk (0x1UL << EXTI_SWIER3_SWIER84_Pos)
13273#define EXTI_SWIER3_SWIER84 EXTI_SWIER3_SWIER84_Msk
13274#define EXTI_SWIER3_SWIER85_Pos (21U)
13275#define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos)
13276#define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk
13277#define EXTI_SWIER3_SWIER86_Pos (22U)
13278#define EXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos)
13279#define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk
13281/******************* Bit definition for EXTI_IMR1 register *******************/
13282#define EXTI_IMR1_IM_Pos (0U)
13283#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)
13284#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk
13285#define EXTI_IMR1_IM0_Pos (0U)
13286#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)
13287#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk
13288#define EXTI_IMR1_IM1_Pos (1U)
13289#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)
13290#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk
13291#define EXTI_IMR1_IM2_Pos (2U)
13292#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)
13293#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk
13294#define EXTI_IMR1_IM3_Pos (3U)
13295#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)
13296#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk
13297#define EXTI_IMR1_IM4_Pos (4U)
13298#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)
13299#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk
13300#define EXTI_IMR1_IM5_Pos (5U)
13301#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)
13302#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk
13303#define EXTI_IMR1_IM6_Pos (6U)
13304#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)
13305#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk
13306#define EXTI_IMR1_IM7_Pos (7U)
13307#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)
13308#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk
13309#define EXTI_IMR1_IM8_Pos (8U)
13310#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)
13311#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk
13312#define EXTI_IMR1_IM9_Pos (9U)
13313#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)
13314#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk
13315#define EXTI_IMR1_IM10_Pos (10U)
13316#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)
13317#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk
13318#define EXTI_IMR1_IM11_Pos (11U)
13319#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)
13320#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk
13321#define EXTI_IMR1_IM12_Pos (12U)
13322#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)
13323#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk
13324#define EXTI_IMR1_IM13_Pos (13U)
13325#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)
13326#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk
13327#define EXTI_IMR1_IM14_Pos (14U)
13328#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)
13329#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk
13330#define EXTI_IMR1_IM15_Pos (15U)
13331#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)
13332#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk
13333#define EXTI_IMR1_IM16_Pos (16U)
13334#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)
13335#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk
13336#define EXTI_IMR1_IM17_Pos (17U)
13337#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)
13338#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk
13339#define EXTI_IMR1_IM18_Pos (18U)
13340#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)
13341#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk
13342#define EXTI_IMR1_IM19_Pos (19U)
13343#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)
13344#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk
13345#define EXTI_IMR1_IM20_Pos (20U)
13346#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)
13347#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk
13348#define EXTI_IMR1_IM21_Pos (21U)
13349#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)
13350#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk
13351#define EXTI_IMR1_IM22_Pos (22U)
13352#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)
13353#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk
13354#define EXTI_IMR1_IM23_Pos (23U)
13355#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)
13356#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk
13357#define EXTI_IMR1_IM24_Pos (24U)
13358#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)
13359#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk
13360#define EXTI_IMR1_IM25_Pos (25U)
13361#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)
13362#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk
13363#define EXTI_IMR1_IM26_Pos (26U)
13364#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)
13365#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk
13366#define EXTI_IMR1_IM27_Pos (27U)
13367#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)
13368#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk
13369#define EXTI_IMR1_IM28_Pos (28U)
13370#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)
13371#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk
13372#define EXTI_IMR1_IM29_Pos (29U)
13373#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)
13374#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk
13375#define EXTI_IMR1_IM30_Pos (30U)
13376#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)
13377#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk
13378#define EXTI_IMR1_IM31_Pos (31U)
13379#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)
13380#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk
13382/******************* Bit definition for EXTI_EMR1 register *******************/
13383#define EXTI_EMR1_EM_Pos (0U)
13384#define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)
13385#define EXTI_EMR1_EM EXTI_EMR1_EM_Msk
13386#define EXTI_EMR1_EM0_Pos (0U)
13387#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)
13388#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk
13389#define EXTI_EMR1_EM1_Pos (1U)
13390#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)
13391#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk
13392#define EXTI_EMR1_EM2_Pos (2U)
13393#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)
13394#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk
13395#define EXTI_EMR1_EM3_Pos (3U)
13396#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)
13397#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk
13398#define EXTI_EMR1_EM4_Pos (4U)
13399#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)
13400#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk
13401#define EXTI_EMR1_EM5_Pos (5U)
13402#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)
13403#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk
13404#define EXTI_EMR1_EM6_Pos (6U)
13405#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)
13406#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk
13407#define EXTI_EMR1_EM7_Pos (7U)
13408#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)
13409#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk
13410#define EXTI_EMR1_EM8_Pos (8U)
13411#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)
13412#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk
13413#define EXTI_EMR1_EM9_Pos (9U)
13414#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)
13415#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk
13416#define EXTI_EMR1_EM10_Pos (10U)
13417#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)
13418#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk
13419#define EXTI_EMR1_EM11_Pos (11U)
13420#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)
13421#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk
13422#define EXTI_EMR1_EM12_Pos (12U)
13423#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)
13424#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk
13425#define EXTI_EMR1_EM13_Pos (13U)
13426#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)
13427#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk
13428#define EXTI_EMR1_EM14_Pos (14U)
13429#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)
13430#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk
13431#define EXTI_EMR1_EM15_Pos (15U)
13432#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)
13433#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk
13434#define EXTI_EMR1_EM16_Pos (16U)
13435#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)
13436#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk
13437#define EXTI_EMR1_EM17_Pos (17U)
13438#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)
13439#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk
13440#define EXTI_EMR1_EM18_Pos (18U)
13441#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)
13442#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk
13443#define EXTI_EMR1_EM20_Pos (20U)
13444#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)
13445#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk
13446#define EXTI_EMR1_EM21_Pos (21U)
13447#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)
13448#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk
13449#define EXTI_EMR1_EM22_Pos (22U)
13450#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)
13451#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk
13452#define EXTI_EMR1_EM23_Pos (23U)
13453#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)
13454#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk
13455#define EXTI_EMR1_EM24_Pos (24U)
13456#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)
13457#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk
13458#define EXTI_EMR1_EM25_Pos (25U)
13459#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)
13460#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk
13461#define EXTI_EMR1_EM26_Pos (26U)
13462#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)
13463#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk
13464#define EXTI_EMR1_EM27_Pos (27U)
13465#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)
13466#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk
13467#define EXTI_EMR1_EM28_Pos (28U)
13468#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)
13469#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk
13470#define EXTI_EMR1_EM29_Pos (29U)
13471#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos)
13472#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk
13473#define EXTI_EMR1_EM30_Pos (30U)
13474#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos)
13475#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk
13476#define EXTI_EMR1_EM31_Pos (31U)
13477#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)
13478#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk
13480/******************* Bit definition for EXTI_PR1 register ********************/
13481#define EXTI_PR1_PR_Pos (0U)
13482#define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos)
13483#define EXTI_PR1_PR EXTI_PR1_PR_Msk
13484#define EXTI_PR1_PR0_Pos (0U)
13485#define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos)
13486#define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk
13487#define EXTI_PR1_PR1_Pos (1U)
13488#define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos)
13489#define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk
13490#define EXTI_PR1_PR2_Pos (2U)
13491#define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos)
13492#define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk
13493#define EXTI_PR1_PR3_Pos (3U)
13494#define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos)
13495#define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk
13496#define EXTI_PR1_PR4_Pos (4U)
13497#define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos)
13498#define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk
13499#define EXTI_PR1_PR5_Pos (5U)
13500#define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos)
13501#define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk
13502#define EXTI_PR1_PR6_Pos (6U)
13503#define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos)
13504#define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk
13505#define EXTI_PR1_PR7_Pos (7U)
13506#define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos)
13507#define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk
13508#define EXTI_PR1_PR8_Pos (8U)
13509#define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos)
13510#define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk
13511#define EXTI_PR1_PR9_Pos (9U)
13512#define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos)
13513#define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk
13514#define EXTI_PR1_PR10_Pos (10U)
13515#define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos)
13516#define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk
13517#define EXTI_PR1_PR11_Pos (11U)
13518#define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos)
13519#define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk
13520#define EXTI_PR1_PR12_Pos (12U)
13521#define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos)
13522#define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk
13523#define EXTI_PR1_PR13_Pos (13U)
13524#define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos)
13525#define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk
13526#define EXTI_PR1_PR14_Pos (14U)
13527#define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos)
13528#define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk
13529#define EXTI_PR1_PR15_Pos (15U)
13530#define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos)
13531#define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk
13532#define EXTI_PR1_PR16_Pos (16U)
13533#define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos)
13534#define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk
13535#define EXTI_PR1_PR17_Pos (17U)
13536#define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos)
13537#define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk
13538#define EXTI_PR1_PR18_Pos (18U)
13539#define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos)
13540#define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk
13541#define EXTI_PR1_PR19_Pos (19U)
13542#define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos)
13543#define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk
13544#define EXTI_PR1_PR20_Pos (20U)
13545#define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos)
13546#define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk
13547#define EXTI_PR1_PR21_Pos (21U)
13548#define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos)
13549#define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk
13551/******************* Bit definition for EXTI_IMR2 register *******************/
13552#define EXTI_IMR2_IM_Pos (0U)
13553#define EXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)
13554#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
13555#define EXTI_IMR2_IM32_Pos (0U)
13556#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos)
13557#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk
13558#define EXTI_IMR2_IM33_Pos (1U)
13559#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos)
13560#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk
13561#define EXTI_IMR2_IM34_Pos (2U)
13562#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)
13563#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk
13564#define EXTI_IMR2_IM35_Pos (3U)
13565#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos)
13566#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk
13567#define EXTI_IMR2_IM36_Pos (4U)
13568#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)
13569#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk
13570#define EXTI_IMR2_IM37_Pos (5U)
13571#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)
13572#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk
13573#define EXTI_IMR2_IM38_Pos (6U)
13574#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)
13575#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk
13576#define EXTI_IMR2_IM39_Pos (7U)
13577#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos)
13578#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk
13579#define EXTI_IMR2_IM40_Pos (8U)
13580#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos)
13581#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk
13582#define EXTI_IMR2_IM41_Pos (9U)
13583#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos)
13584#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk
13585#define EXTI_IMR2_IM42_Pos (10U)
13586#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos)
13587#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk
13588#define EXTI_IMR2_IM43_Pos (11U)
13589#define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos)
13590#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk
13591#define EXTI_IMR2_IM44_Pos (12U)
13592#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos)
13593#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk
13594#define EXTI_IMR2_IM46_Pos (14U)
13595#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos)
13596#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk
13597#define EXTI_IMR2_IM47_Pos (15U)
13598#define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos)
13599#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk
13600#define EXTI_IMR2_IM48_Pos (16U)
13601#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos)
13602#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk
13603#define EXTI_IMR2_IM49_Pos (17U)
13604#define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos)
13605#define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk
13606#define EXTI_IMR2_IM50_Pos (18U)
13607#define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos)
13608#define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk
13609#define EXTI_IMR2_IM51_Pos (19U)
13610#define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos)
13611#define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk
13612#define EXTI_IMR2_IM52_Pos (20U)
13613#define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos)
13614#define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk
13615#define EXTI_IMR2_IM53_Pos (21U)
13616#define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos)
13617#define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk
13618#define EXTI_IMR2_IM54_Pos (22U)
13619#define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos)
13620#define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk
13621#define EXTI_IMR2_IM55_Pos (23U)
13622#define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos)
13623#define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk
13624#define EXTI_IMR2_IM56_Pos (24U)
13625#define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos)
13626#define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk
13627#define EXTI_IMR2_IM57_Pos (25U)
13628#define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos)
13629#define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk
13630#define EXTI_IMR2_IM58_Pos (26U)
13631#define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos)
13632#define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk
13633#define EXTI_IMR2_IM59_Pos (27U)
13634#define EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos)
13635#define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk
13636#define EXTI_IMR2_IM60_Pos (28U)
13637#define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos)
13638#define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk
13639#define EXTI_IMR2_IM61_Pos (29U)
13640#define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos)
13641#define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk
13642#define EXTI_IMR2_IM62_Pos (30U)
13643#define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos)
13644#define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk
13645#define EXTI_IMR2_IM63_Pos (31U)
13646#define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos)
13647#define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk
13649/******************* Bit definition for EXTI_EMR2 register *******************/
13650#define EXTI_EMR2_EM_Pos (0U)
13651#define EXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)
13652#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
13653#define EXTI_EMR2_EM32_Pos (0U)
13654#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos)
13655#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk
13656#define EXTI_EMR2_EM33_Pos (1U)
13657#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos)
13658#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk
13659#define EXTI_EMR2_EM34_Pos (2U)
13660#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)
13661#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk
13662#define EXTI_EMR2_EM35_Pos (3U)
13663#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos)
13664#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk
13665#define EXTI_EMR2_EM36_Pos (4U)
13666#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos)
13667#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk
13668#define EXTI_EMR2_EM37_Pos (5U)
13669#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)
13670#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk
13671#define EXTI_EMR2_EM38_Pos (6U)
13672#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)
13673#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk
13674#define EXTI_EMR2_EM39_Pos (7U)
13675#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos)
13676#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk
13677#define EXTI_EMR2_EM40_Pos (8U)
13678#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos)
13679#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk
13680#define EXTI_EMR2_EM41_Pos (9U)
13681#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos)
13682#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk
13683#define EXTI_EMR2_EM42_Pos (10U)
13684#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos)
13685#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk
13686#define EXTI_EMR2_EM43_Pos (11U)
13687#define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos)
13688#define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk
13689#define EXTI_EMR2_EM44_Pos (12U)
13690#define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos)
13691#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk
13692#define EXTI_EMR2_EM46_Pos (14U)
13693#define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos)
13694#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk
13695#define EXTI_EMR2_EM47_Pos (15U)
13696#define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos)
13697#define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk
13698#define EXTI_EMR2_EM48_Pos (16U)
13699#define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos)
13700#define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk
13701#define EXTI_EMR2_EM49_Pos (17U)
13702#define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos)
13703#define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk
13704#define EXTI_EMR2_EM50_Pos (18U)
13705#define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos)
13706#define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk
13707#define EXTI_EMR2_EM51_Pos (19U)
13708#define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos)
13709#define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk
13710#define EXTI_EMR2_EM52_Pos (20U)
13711#define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos)
13712#define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk
13713#define EXTI_EMR2_EM53_Pos (21U)
13714#define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos)
13715#define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk
13716#define EXTI_EMR2_EM54_Pos (22U)
13717#define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos)
13718#define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk
13719#define EXTI_EMR2_EM55_Pos (23U)
13720#define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos)
13721#define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk
13722#define EXTI_EMR2_EM56_Pos (24U)
13723#define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos)
13724#define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk
13725#define EXTI_EMR2_EM57_Pos (25U)
13726#define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos)
13727#define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk
13728#define EXTI_EMR2_EM58_Pos (26U)
13729#define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos)
13730#define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk
13731#define EXTI_EMR2_EM59_Pos (27U)
13732#define EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos)
13733#define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk
13734#define EXTI_EMR2_EM60_Pos (28U)
13735#define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos)
13736#define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk
13737#define EXTI_EMR2_EM61_Pos (29U)
13738#define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos)
13739#define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk
13740#define EXTI_EMR2_EM62_Pos (30U)
13741#define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos)
13742#define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk
13743#define EXTI_EMR2_EM63_Pos (31U)
13744#define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos)
13745#define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk
13747/******************* Bit definition for EXTI_PR2 register ********************/
13748#define EXTI_PR2_PR_Pos (17U)
13749#define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos)
13750#define EXTI_PR2_PR EXTI_PR2_PR_Msk
13751#define EXTI_PR2_PR49_Pos (17U)
13752#define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos)
13753#define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk
13754#define EXTI_PR2_PR51_Pos (19U)
13755#define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos)
13756#define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk
13758/******************* Bit definition for EXTI_IMR3 register *******************/
13759#define EXTI_IMR3_IM_Pos (0U)
13760#define EXTI_IMR3_IM_Msk (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)
13761#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk
13762#define EXTI_IMR3_IM64_Pos (0U)
13763#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos)
13764#define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk
13765#define EXTI_IMR3_IM65_Pos (1U)
13766#define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos)
13767#define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk
13768#define EXTI_IMR3_IM66_Pos (2U)
13769#define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos)
13770#define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk
13771#define EXTI_IMR3_IM67_Pos (3U)
13772#define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos)
13773#define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk
13774#define EXTI_IMR3_IM68_Pos (4U)
13775#define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos)
13776#define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk
13777#define EXTI_IMR3_IM69_Pos (5U)
13778#define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos)
13779#define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk
13780#define EXTI_IMR3_IM70_Pos (6U)
13781#define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos)
13782#define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk
13783#define EXTI_IMR3_IM71_Pos (7U)
13784#define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos)
13785#define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk
13786#define EXTI_IMR3_IM72_Pos (8U)
13787#define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos)
13788#define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk
13789#define EXTI_IMR3_IM73_Pos (9U)
13790#define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos)
13791#define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk
13792#define EXTI_IMR3_IM74_Pos (10U)
13793#define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos)
13794#define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk
13795#define EXTI_IMR3_IM75_Pos (11U)
13796#define EXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos)
13797#define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk
13798#define EXTI_IMR3_IM76_Pos (12U)
13799#define EXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos)
13800#define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk
13801#define EXTI_IMR3_IM77_Pos (13U)
13802#define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos)
13803#define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk
13804#define EXTI_IMR3_IM78_Pos (14U)
13805#define EXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos)
13806#define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk
13807#define EXTI_IMR3_IM79_Pos (15U)
13808#define EXTI_IMR3_IM79_Msk (0x1UL << EXTI_IMR3_IM79_Pos)
13809#define EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk
13810#define EXTI_IMR3_IM80_Pos (16U)
13811#define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos)
13812#define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk
13813#define EXTI_IMR3_IM82_Pos (18U)
13814#define EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos)
13815#define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk
13816#define EXTI_IMR3_IM84_Pos (20U)
13817#define EXTI_IMR3_IM84_Msk (0x1UL << EXTI_IMR3_IM84_Pos)
13818#define EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk
13819#define EXTI_IMR3_IM85_Pos (21U)
13820#define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos)
13821#define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk
13822#define EXTI_IMR3_IM86_Pos (22U)
13823#define EXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos)
13824#define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk
13825#define EXTI_IMR3_IM87_Pos (23U)
13826#define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos)
13827#define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk
13830/******************* Bit definition for EXTI_EMR3 register *******************/
13831#define EXTI_EMR3_EM_Pos (0U)
13832#define EXTI_EMR3_EM_Msk (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)
13833#define EXTI_EMR3_EM EXTI_EMR3_EM_Msk
13834#define EXTI_EMR3_EM64_Pos (0U)
13835#define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos)
13836#define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk
13837#define EXTI_EMR3_EM65_Pos (1U)
13838#define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos)
13839#define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk
13840#define EXTI_EMR3_EM66_Pos (2U)
13841#define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos)
13842#define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk
13843#define EXTI_EMR3_EM67_Pos (3U)
13844#define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos)
13845#define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk
13846#define EXTI_EMR3_EM68_Pos (4U)
13847#define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos)
13848#define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk
13849#define EXTI_EMR3_EM69_Pos (5U)
13850#define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos)
13851#define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk
13852#define EXTI_EMR3_EM70_Pos (6U)
13853#define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos)
13854#define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk
13855#define EXTI_EMR3_EM71_Pos (7U)
13856#define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos)
13857#define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk
13858#define EXTI_EMR3_EM72_Pos (8U)
13859#define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos)
13860#define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk
13861#define EXTI_EMR3_EM73_Pos (9U)
13862#define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos)
13863#define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk
13864#define EXTI_EMR3_EM74_Pos (10U)
13865#define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos)
13866#define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk
13867#define EXTI_EMR3_EM75_Pos (11U)
13868#define EXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos)
13869#define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk
13870#define EXTI_EMR3_EM76_Pos (12U)
13871#define EXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos)
13872#define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk
13873#define EXTI_EMR3_EM77_Pos (13U)
13874#define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos)
13875#define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk
13876#define EXTI_EMR3_EM78_Pos (14U)
13877#define EXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos)
13878#define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk
13879#define EXTI_EMR3_EM79_Pos (15U)
13880#define EXTI_EMR3_EM79_Msk (0x1UL << EXTI_EMR3_EM79_Pos)
13881#define EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk
13882#define EXTI_EMR3_EM80_Pos (16U)
13883#define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos)
13884#define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk
13885#define EXTI_EMR3_EM81_Pos (17U)
13886#define EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos)
13887#define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk
13888#define EXTI_EMR3_EM82_Pos (18U)
13889#define EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos)
13890#define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk
13891#define EXTI_EMR3_EM84_Pos (20U)
13892#define EXTI_EMR3_EM84_Msk (0x1UL << EXTI_EMR3_EM84_Pos)
13893#define EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk
13894#define EXTI_EMR3_EM85_Pos (21U)
13895#define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos)
13896#define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk
13897#define EXTI_EMR3_EM86_Pos (22U)
13898#define EXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos)
13899#define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk
13900#define EXTI_EMR3_EM87_Pos (23U)
13901#define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos)
13902#define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk
13904/******************* Bit definition for EXTI_PR3 register ********************/
13905#define EXTI_PR3_PR_Pos (18U)
13906#define EXTI_PR3_PR_Msk (0x1DUL << EXTI_PR3_PR_Pos)
13907#define EXTI_PR3_PR EXTI_PR3_PR_Msk
13908#define EXTI_PR3_PR82_Pos (18U)
13909#define EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos)
13910#define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk
13911#define EXTI_PR3_PR84_Pos (20U)
13912#define EXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos)
13913#define EXTI_PR3_PR84 EXTI_PR3_PR84_Msk
13914#define EXTI_PR3_PR85_Pos (21U)
13915#define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos)
13916#define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk
13917#define EXTI_PR3_PR86_Pos (22U)
13918#define EXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos)
13919#define EXTI_PR3_PR86 EXTI_PR3_PR86_Msk
13920/******************************************************************************/
13921/* */
13922/* FLASH */
13923/* */
13924/******************************************************************************/
13925/*
13926* @brief FLASH Global Defines
13927*/
13928#if defined(CORE_CM4)
13929#define FLASH_SIZE 0x200000UL /* 2 MB */
13930#else
13931#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
13932#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
13933 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
13934 (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
13935#endif /* CORE_CM4 */
13936#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
13937#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
13938#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
13939#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
13940#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
13941#define DUAL_BANK /* Dual-bank Flash */
13942
13943/******************* Bits definition for FLASH_ACR register **********************/
13944#define FLASH_ACR_LATENCY_Pos (0U)
13945#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
13946#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
13947#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
13948#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
13949#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
13950#define FLASH_ACR_LATENCY_3WS (0x00000003UL)
13951#define FLASH_ACR_LATENCY_4WS (0x00000004UL)
13952#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
13953#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
13954#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
13955
13956#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
13957#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)
13958#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk
13959#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)
13960#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)
13962/* Legacy FLASH Latency defines */
13963#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
13964#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
13965#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
13966#define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
13967#define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
13968#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
13969#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
13970#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
13971/******************* Bits definition for FLASH_CR register ***********************/
13972#define FLASH_CR_LOCK_Pos (0U)
13973#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
13974#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
13975#define FLASH_CR_PG_Pos (1U)
13976#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
13977#define FLASH_CR_PG FLASH_CR_PG_Msk
13978#define FLASH_CR_SER_Pos (2U)
13979#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
13980#define FLASH_CR_SER FLASH_CR_SER_Msk
13981#define FLASH_CR_BER_Pos (3U)
13982#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos)
13983#define FLASH_CR_BER FLASH_CR_BER_Msk
13984#define FLASH_CR_PSIZE_Pos (4U)
13985#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
13986#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
13987#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
13988#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
13989#define FLASH_CR_FW_Pos (6U)
13990#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos)
13991#define FLASH_CR_FW FLASH_CR_FW_Msk
13992#define FLASH_CR_START_Pos (7U)
13993#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos)
13994#define FLASH_CR_START FLASH_CR_START_Msk
13995#define FLASH_CR_SNB_Pos (8U)
13996#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos)
13997#define FLASH_CR_SNB FLASH_CR_SNB_Msk
13998#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos)
13999#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos)
14000#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos)
14001#define FLASH_CR_CRC_EN_Pos (15U)
14002#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos)
14003#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk
14004#define FLASH_CR_EOPIE_Pos (16U)
14005#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
14006#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
14007#define FLASH_CR_WRPERRIE_Pos (17U)
14008#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos)
14009#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk
14010#define FLASH_CR_PGSERRIE_Pos (18U)
14011#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos)
14012#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk
14013#define FLASH_CR_STRBERRIE_Pos (19U)
14014#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos)
14015#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk
14016#define FLASH_CR_INCERRIE_Pos (21U)
14017#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos)
14018#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk
14019#define FLASH_CR_OPERRIE_Pos (22U)
14020#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos)
14021#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk
14022#define FLASH_CR_RDPERRIE_Pos (23U)
14023#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos)
14024#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk
14025#define FLASH_CR_RDSERRIE_Pos (24U)
14026#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos)
14027#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk
14028#define FLASH_CR_SNECCERRIE_Pos (25U)
14029#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos)
14030#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk
14031#define FLASH_CR_DBECCERRIE_Pos (26U)
14032#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos)
14033#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk
14034#define FLASH_CR_CRCENDIE_Pos (27U)
14035#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos)
14036#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk
14037#define FLASH_CR_CRCRDERRIE_Pos (28U)
14038#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos)
14039#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk
14041/******************* Bits definition for FLASH_SR register ***********************/
14042#define FLASH_SR_BSY_Pos (0U)
14043#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
14044#define FLASH_SR_BSY FLASH_SR_BSY_Msk
14045#define FLASH_SR_WBNE_Pos (1U)
14046#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos)
14047#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk
14048#define FLASH_SR_QW_Pos (2U)
14049#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos)
14050#define FLASH_SR_QW FLASH_SR_QW_Msk
14051#define FLASH_SR_CRC_BUSY_Pos (3U)
14052#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos)
14053#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk
14054#define FLASH_SR_EOP_Pos (16U)
14055#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
14056#define FLASH_SR_EOP FLASH_SR_EOP_Msk
14057#define FLASH_SR_WRPERR_Pos (17U)
14058#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
14059#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
14060#define FLASH_SR_PGSERR_Pos (18U)
14061#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
14062#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
14063#define FLASH_SR_STRBERR_Pos (19U)
14064#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos)
14065#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk
14066#define FLASH_SR_INCERR_Pos (21U)
14067#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos)
14068#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk
14069#define FLASH_SR_OPERR_Pos (22U)
14070#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
14071#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
14072#define FLASH_SR_RDPERR_Pos (23U)
14073#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos)
14074#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk
14075#define FLASH_SR_RDSERR_Pos (24U)
14076#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos)
14077#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk
14078#define FLASH_SR_SNECCERR_Pos (25U)
14079#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos)
14080#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk
14081#define FLASH_SR_DBECCERR_Pos (26U)
14082#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos)
14083#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk
14084#define FLASH_SR_CRCEND_Pos (27U)
14085#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos)
14086#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk
14087#define FLASH_SR_CRCRDERR_Pos (28U)
14088#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos)
14089#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk
14091/******************* Bits definition for FLASH_CCR register *******************/
14092#define FLASH_CCR_CLR_EOP_Pos (16U)
14093#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos)
14094#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk
14095#define FLASH_CCR_CLR_WRPERR_Pos (17U)
14096#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos)
14097#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk
14098#define FLASH_CCR_CLR_PGSERR_Pos (18U)
14099#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos)
14100#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk
14101#define FLASH_CCR_CLR_STRBERR_Pos (19U)
14102#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos)
14103#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk
14104#define FLASH_CCR_CLR_INCERR_Pos (21U)
14105#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos)
14106#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk
14107#define FLASH_CCR_CLR_OPERR_Pos (22U)
14108#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos)
14109#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk
14110#define FLASH_CCR_CLR_RDPERR_Pos (23U)
14111#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos)
14112#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk
14113#define FLASH_CCR_CLR_RDSERR_Pos (24U)
14114#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos)
14115#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk
14116#define FLASH_CCR_CLR_SNECCERR_Pos (25U)
14117#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos)
14118#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk
14119#define FLASH_CCR_CLR_DBECCERR_Pos (26U)
14120#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos)
14121#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk
14122#define FLASH_CCR_CLR_CRCEND_Pos (27U)
14123#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos)
14124#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk
14125#define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
14126#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos)
14127#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk
14129/******************* Bits definition for FLASH_OPTCR register *******************/
14130#define FLASH_OPTCR_OPTLOCK_Pos (0U)
14131#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
14132#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
14133#define FLASH_OPTCR_OPTSTART_Pos (1U)
14134#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos)
14135#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk
14136#define FLASH_OPTCR_MER_Pos (4U)
14137#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos)
14138#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk
14139#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
14140#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos)
14141#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk
14142#define FLASH_OPTCR_SWAP_BANK_Pos (31U)
14143#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos)
14144#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk
14146/******************* Bits definition for FLASH_OPTSR register ***************/
14147#define FLASH_OPTSR_OPT_BUSY_Pos (0U)
14148#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos)
14149#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk
14150#define FLASH_OPTSR_BOR_LEV_Pos (2U)
14151#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos)
14152#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk
14153#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos)
14154#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos)
14155#define FLASH_OPTSR_IWDG1_SW_Pos (4U)
14156#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos)
14157#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk
14158#define FLASH_OPTSR_IWDG2_SW_Pos (5U)
14159#define FLASH_OPTSR_IWDG2_SW_Msk (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos)
14160#define FLASH_OPTSR_IWDG2_SW FLASH_OPTSR_IWDG2_SW_Msk
14161#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
14162#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos)
14163#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk
14164#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
14165#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos)
14166#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk
14167#define FLASH_OPTSR_RDP_Pos (8U)
14168#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos)
14169#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk
14170#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
14171#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos)
14172#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk
14173#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
14174#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos)
14175#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk
14176#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
14177#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
14178#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk
14179#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
14180#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
14181#define FLASH_OPTSR_SECURITY_Pos (21U)
14182#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos)
14183#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk
14184#define FLASH_OPTSR_BCM4_Pos (22U)
14185#define FLASH_OPTSR_BCM4_Msk (0x1UL << FLASH_OPTSR_BCM4_Pos)
14186#define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk
14187#define FLASH_OPTSR_BCM7_Pos (23U)
14188#define FLASH_OPTSR_BCM7_Msk (0x1UL << FLASH_OPTSR_BCM7_Pos)
14189#define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk
14190#define FLASH_OPTSR_NRST_STOP_D2_Pos (24U)
14191#define FLASH_OPTSR_NRST_STOP_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos)
14192#define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk
14193#define FLASH_OPTSR_NRST_STBY_D2_Pos (25U)
14194#define FLASH_OPTSR_NRST_STBY_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos)
14195#define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk
14196#define FLASH_OPTSR_IO_HSLV_Pos (29U)
14197#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos)
14198#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk
14199#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
14200#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos)
14201#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk
14202#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
14203#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos)
14204#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk
14206/******************* Bits definition for FLASH_OPTCCR register *******************/
14207#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
14208#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos)
14209#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk
14211/******************* Bits definition for FLASH_PRAR register *********************/
14212#define FLASH_PRAR_PROT_AREA_START_Pos (0U)
14213#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos)
14214#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk
14215#define FLASH_PRAR_PROT_AREA_END_Pos (16U)
14216#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos)
14217#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk
14218#define FLASH_PRAR_DMEP_Pos (31U)
14219#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos)
14220#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk
14222/******************* Bits definition for FLASH_SCAR register *********************/
14223#define FLASH_SCAR_SEC_AREA_START_Pos (0U)
14224#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos)
14225#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk
14226#define FLASH_SCAR_SEC_AREA_END_Pos (16U)
14227#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos)
14228#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk
14229#define FLASH_SCAR_DMES_Pos (31U)
14230#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos)
14231#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk
14233/******************* Bits definition for FLASH_WPSN register *********************/
14234#define FLASH_WPSN_WRPSN_Pos (0U)
14235#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos)
14236#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk
14238/******************* Bits definition for FLASH_BOOT7_CUR register ****************/
14239#define FLASH_BOOT7_BCM7_ADD0_Pos (0U)
14240#define FLASH_BOOT7_BCM7_ADD0_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos)
14241#define FLASH_BOOT7_BCM7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk
14242#define FLASH_BOOT7_BCM7_ADD1_Pos (16U)
14243#define FLASH_BOOT7_BCM7_ADD1_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos)
14244#define FLASH_BOOT7_BCM7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk
14246/******************* Bits definition for FLASH_BOOT4 register ********************/
14247#define FLASH_BOOT4_BCM4_ADD0_Pos (0U)
14248#define FLASH_BOOT4_BCM4_ADD0_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos)
14249#define FLASH_BOOT4_BCM4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk
14250#define FLASH_BOOT4_BCM4_ADD1_Pos (16U)
14251#define FLASH_BOOT4_BCM4_ADD1_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos)
14252#define FLASH_BOOT4_BCM4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk
14254/******************* Bits definition for FLASH_CRCCR register ********************/
14255#define FLASH_CRCCR_CRC_SECT_Pos (0U)
14256#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos)
14257#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk
14258#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
14259#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos)
14260#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk
14261#define FLASH_CRCCR_ADD_SECT_Pos (9U)
14262#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos)
14263#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk
14264#define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
14265#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos)
14266#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk
14267#define FLASH_CRCCR_START_CRC_Pos (16U)
14268#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos)
14269#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk
14270#define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
14271#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos)
14272#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk
14273#define FLASH_CRCCR_CRC_BURST_Pos (20U)
14274#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos)
14275#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk
14276#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos)
14277#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos)
14278#define FLASH_CRCCR_ALL_BANK_Pos (22U)
14279#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos)
14280#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk
14282/******************* Bits definition for FLASH_CRCSADD register ****************/
14283#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
14284#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos)
14285#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk
14287/******************* Bits definition for FLASH_CRCEADD register ****************/
14288#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
14289#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos)
14290#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk
14292/******************* Bits definition for FLASH_CRCDATA register ***************/
14293#define FLASH_CRCDATA_CRC_DATA_Pos (0U)
14294#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos)
14295#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk
14297/******************* Bits definition for FLASH_ECC_FA register *******************/
14298#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
14299#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos)
14300#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk
14302/******************************************************************************/
14303/* */
14304/* Flexible Memory Controller */
14305/* */
14306/******************************************************************************/
14307/****************** Bit definition for FMC_BCR1 register *******************/
14308#define FMC_BCR1_CCLKEN_Pos (20U)
14309#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
14310#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
14311#define FMC_BCR1_WFDIS_Pos (21U)
14312#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
14313#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
14315#define FMC_BCR1_BMAP_Pos (24U)
14316#define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos)
14317#define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk
14318#define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos)
14319#define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos)
14321#define FMC_BCR1_FMCEN_Pos (31U)
14322#define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos)
14323#define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk
14324/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
14325#define FMC_BCRx_MBKEN_Pos (0U)
14326#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)
14327#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk
14328#define FMC_BCRx_MUXEN_Pos (1U)
14329#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)
14330#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk
14332#define FMC_BCRx_MTYP_Pos (2U)
14333#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)
14334#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk
14335#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)
14336#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)
14338#define FMC_BCRx_MWID_Pos (4U)
14339#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)
14340#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk
14341#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)
14342#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)
14344#define FMC_BCRx_FACCEN_Pos (6U)
14345#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)
14346#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk
14347#define FMC_BCRx_BURSTEN_Pos (8U)
14348#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)
14349#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk
14350#define FMC_BCRx_WAITPOL_Pos (9U)
14351#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)
14352#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk
14353#define FMC_BCRx_WAITCFG_Pos (11U)
14354#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)
14355#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk
14356#define FMC_BCRx_WREN_Pos (12U)
14357#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)
14358#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk
14359#define FMC_BCRx_WAITEN_Pos (13U)
14360#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)
14361#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk
14362#define FMC_BCRx_EXTMOD_Pos (14U)
14363#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)
14364#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk
14365#define FMC_BCRx_ASYNCWAIT_Pos (15U)
14366#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)
14367#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk
14369#define FMC_BCRx_CPSIZE_Pos (16U)
14370#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos)
14371#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk
14372#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos)
14373#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos)
14374#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos)
14376#define FMC_BCRx_CBURSTRW_Pos (19U)
14377#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)
14378#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk
14380/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
14381#define FMC_BTRx_ADDSET_Pos (0U)
14382#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)
14383#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk
14384#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)
14385#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)
14386#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)
14387#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos)
14389#define FMC_BTRx_ADDHLD_Pos (4U)
14390#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)
14391#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk
14392#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)
14393#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)
14394#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)
14395#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)
14397#define FMC_BTRx_DATAST_Pos (8U)
14398#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)
14399#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk
14400#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos)
14401#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos)
14402#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos)
14403#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos)
14404#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos)
14405#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos)
14406#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos)
14407#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos)
14409#define FMC_BTRx_BUSTURN_Pos (16U)
14410#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)
14411#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk
14412#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)
14413#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)
14414#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)
14415#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)
14417#define FMC_BTRx_CLKDIV_Pos (20U)
14418#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)
14419#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk
14420#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)
14421#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)
14422#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)
14423#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)
14425#define FMC_BTRx_DATLAT_Pos (24U)
14426#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)
14427#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk
14428#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)
14429#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)
14430#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)
14431#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)
14433#define FMC_BTRx_ACCMOD_Pos (28U)
14434#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)
14435#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk
14436#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)
14437#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)
14439/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
14440#define FMC_BWTRx_ADDSET_Pos (0U)
14441#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)
14442#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk
14443#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)
14444#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)
14445#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)
14446#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)
14448#define FMC_BWTRx_ADDHLD_Pos (4U)
14449#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)
14450#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk
14451#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)
14452#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)
14453#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)
14454#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)
14456#define FMC_BWTRx_DATAST_Pos (8U)
14457#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)
14458#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk
14459#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)
14460#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)
14461#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)
14462#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)
14463#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)
14464#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)
14465#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)
14466#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)
14468#define FMC_BWTRx_BUSTURN_Pos (16U)
14469#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos)
14470#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk
14471#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos)
14472#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos)
14473#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos)
14474#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos)
14476#define FMC_BWTRx_ACCMOD_Pos (28U)
14477#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)
14478#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk
14479#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)
14480#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)
14482/****************** Bit definition for FMC_PCR register *******************/
14483#define FMC_PCR_PWAITEN_Pos (1U)
14484#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
14485#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
14486#define FMC_PCR_PBKEN_Pos (2U)
14487#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
14488#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
14490#define FMC_PCR_PWID_Pos (4U)
14491#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
14492#define FMC_PCR_PWID FMC_PCR_PWID_Msk
14493#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
14494#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
14496#define FMC_PCR_ECCEN_Pos (6U)
14497#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
14498#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
14500#define FMC_PCR_TCLR_Pos (9U)
14501#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
14502#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
14503#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
14504#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
14505#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
14506#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
14508#define FMC_PCR_TAR_Pos (13U)
14509#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
14510#define FMC_PCR_TAR FMC_PCR_TAR_Msk
14511#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
14512#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
14513#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
14514#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
14516#define FMC_PCR_ECCPS_Pos (17U)
14517#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
14518#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
14519#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
14520#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
14521#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
14523/******************* Bit definition for FMC_SR register *******************/
14524#define FMC_SR_IRS_Pos (0U)
14525#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
14526#define FMC_SR_IRS FMC_SR_IRS_Msk
14527#define FMC_SR_ILS_Pos (1U)
14528#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
14529#define FMC_SR_ILS FMC_SR_ILS_Msk
14530#define FMC_SR_IFS_Pos (2U)
14531#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
14532#define FMC_SR_IFS FMC_SR_IFS_Msk
14533#define FMC_SR_IREN_Pos (3U)
14534#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
14535#define FMC_SR_IREN FMC_SR_IREN_Msk
14536#define FMC_SR_ILEN_Pos (4U)
14537#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
14538#define FMC_SR_ILEN FMC_SR_ILEN_Msk
14539#define FMC_SR_IFEN_Pos (5U)
14540#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
14541#define FMC_SR_IFEN FMC_SR_IFEN_Msk
14542#define FMC_SR_FEMPT_Pos (6U)
14543#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
14544#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
14546/****************** Bit definition for FMC_PMEM register ******************/
14547#define FMC_PMEM_MEMSET_Pos (0U)
14548#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos)
14549#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk
14550#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos)
14551#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos)
14552#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos)
14553#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos)
14554#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos)
14555#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos)
14556#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos)
14557#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos)
14559#define FMC_PMEM_MEMWAIT_Pos (8U)
14560#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos)
14561#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk
14562#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos)
14563#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos)
14564#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos)
14565#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos)
14566#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos)
14567#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos)
14568#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos)
14569#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos)
14571#define FMC_PMEM_MEMHOLD_Pos (16U)
14572#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos)
14573#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk
14574#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos)
14575#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos)
14576#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos)
14577#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos)
14578#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos)
14579#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos)
14580#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos)
14581#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos)
14583#define FMC_PMEM_MEMHIZ_Pos (24U)
14584#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos)
14585#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk
14586#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos)
14587#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos)
14588#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos)
14589#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos)
14590#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos)
14591#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos)
14592#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos)
14593#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos)
14595/****************** Bit definition for FMC_PATT register ******************/
14596#define FMC_PATT_ATTSET_Pos (0U)
14597#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos)
14598#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk
14599#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos)
14600#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos)
14601#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos)
14602#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos)
14603#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos)
14604#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos)
14605#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos)
14606#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos)
14608#define FMC_PATT_ATTWAIT_Pos (8U)
14609#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos)
14610#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk
14611#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos)
14612#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos)
14613#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos)
14614#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos)
14615#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos)
14616#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos)
14617#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos)
14618#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos)
14620#define FMC_PATT_ATTHOLD_Pos (16U)
14621#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos)
14622#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk
14623#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos)
14624#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos)
14625#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos)
14626#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos)
14627#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos)
14628#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos)
14629#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos)
14630#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos)
14632#define FMC_PATT_ATTHIZ_Pos (24U)
14633#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos)
14634#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk
14635#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos)
14636#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos)
14637#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos)
14638#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos)
14639#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos)
14640#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos)
14641#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos)
14642#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos)
14644/****************** Bit definition for FMC_ECCR3 register ******************/
14645#define FMC_ECCR3_ECC3_Pos (0U)
14646#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)
14647#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk
14649/****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
14650#define FMC_SDCRx_NC_Pos (0U)
14651#define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos)
14652#define FMC_SDCRx_NC FMC_SDCRx_NC_Msk
14653#define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos)
14654#define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos)
14656#define FMC_SDCRx_NR_Pos (2U)
14657#define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos)
14658#define FMC_SDCRx_NR FMC_SDCRx_NR_Msk
14659#define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos)
14660#define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos)
14662#define FMC_SDCRx_MWID_Pos (4U)
14663#define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos)
14664#define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk
14665#define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos)
14666#define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos)
14668#define FMC_SDCRx_NB_Pos (6U)
14669#define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos)
14670#define FMC_SDCRx_NB FMC_SDCRx_NB_Msk
14672#define FMC_SDCRx_CAS_Pos (7U)
14673#define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos)
14674#define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk
14675#define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos)
14676#define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos)
14678#define FMC_SDCRx_WP_Pos (9U)
14679#define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos)
14680#define FMC_SDCRx_WP FMC_SDCRx_WP_Msk
14682#define FMC_SDCRx_SDCLK_Pos (10U)
14683#define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos)
14684#define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk
14685#define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos)
14686#define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos)
14688#define FMC_SDCRx_RBURST_Pos (12U)
14689#define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos)
14690#define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk
14692#define FMC_SDCRx_RPIPE_Pos (13U)
14693#define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos)
14694#define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk
14695#define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos)
14696#define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos)
14698/****************** Bit definition for FMC_SDTRx(1,2) register ******************/
14699#define FMC_SDTRx_TMRD_Pos (0U)
14700#define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos)
14701#define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk
14702#define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos)
14703#define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos)
14704#define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos)
14705#define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos)
14707#define FMC_SDTRx_TXSR_Pos (4U)
14708#define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos)
14709#define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk
14710#define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos)
14711#define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos)
14712#define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos)
14713#define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos)
14715#define FMC_SDTRx_TRAS_Pos (8U)
14716#define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos)
14717#define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk
14718#define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos)
14719#define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos)
14720#define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos)
14721#define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos)
14723#define FMC_SDTRx_TRC_Pos (12U)
14724#define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos)
14725#define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk
14726#define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos)
14727#define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos)
14728#define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos)
14730#define FMC_SDTRx_TWR_Pos (16U)
14731#define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos)
14732#define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk
14733#define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos)
14734#define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos)
14735#define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos)
14737#define FMC_SDTRx_TRP_Pos (20U)
14738#define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos)
14739#define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk
14740#define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos)
14741#define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos)
14742#define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos)
14744#define FMC_SDTRx_TRCD_Pos (24U)
14745#define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos)
14746#define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk
14747#define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos)
14748#define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos)
14749#define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos)
14751/****************** Bit definition for FMC_SDCMR register ******************/
14752#define FMC_SDCMR_MODE_Pos (0U)
14753#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
14754#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
14755#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
14756#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
14757#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos)
14759#define FMC_SDCMR_CTB2_Pos (3U)
14760#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
14761#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
14763#define FMC_SDCMR_CTB1_Pos (4U)
14764#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
14765#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
14767#define FMC_SDCMR_NRFS_Pos (5U)
14768#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
14769#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
14770#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
14771#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
14772#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
14773#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
14775#define FMC_SDCMR_MRD_Pos (9U)
14776#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
14777#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
14779/****************** Bit definition for FMC_SDRTR register ******************/
14780#define FMC_SDRTR_CRE_Pos (0U)
14781#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
14782#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
14784#define FMC_SDRTR_COUNT_Pos (1U)
14785#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
14786#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
14788#define FMC_SDRTR_REIE_Pos (14U)
14789#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
14790#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
14792/****************** Bit definition for FMC_SDSR register ******************/
14793#define FMC_SDSR_RE_Pos (0U)
14794#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
14795#define FMC_SDSR_RE FMC_SDSR_RE_Msk
14797#define FMC_SDSR_MODES1_Pos (1U)
14798#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
14799#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
14800#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
14801#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
14803#define FMC_SDSR_MODES2_Pos (3U)
14804#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
14805#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
14806#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
14807#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
14809/******************************************************************************/
14810/* */
14811/* General Purpose I/O */
14812/* */
14813/******************************************************************************/
14814/****************** Bits definition for GPIO_MODER register *****************/
14815#define GPIO_MODER_MODE0_Pos (0U)
14816#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
14817#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
14818#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
14819#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
14821#define GPIO_MODER_MODE1_Pos (2U)
14822#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)
14823#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
14824#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)
14825#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)
14827#define GPIO_MODER_MODE2_Pos (4U)
14828#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)
14829#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
14830#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)
14831#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)
14833#define GPIO_MODER_MODE3_Pos (6U)
14834#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)
14835#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
14836#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)
14837#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)
14839#define GPIO_MODER_MODE4_Pos (8U)
14840#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)
14841#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
14842#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)
14843#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)
14845#define GPIO_MODER_MODE5_Pos (10U)
14846#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)
14847#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
14848#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)
14849#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)
14851#define GPIO_MODER_MODE6_Pos (12U)
14852#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)
14853#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
14854#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)
14855#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)
14857#define GPIO_MODER_MODE7_Pos (14U)
14858#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)
14859#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
14860#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)
14861#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)
14863#define GPIO_MODER_MODE8_Pos (16U)
14864#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)
14865#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
14866#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)
14867#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)
14869#define GPIO_MODER_MODE9_Pos (18U)
14870#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)
14871#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
14872#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)
14873#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)
14875#define GPIO_MODER_MODE10_Pos (20U)
14876#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)
14877#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
14878#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)
14879#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)
14881#define GPIO_MODER_MODE11_Pos (22U)
14882#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)
14883#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
14884#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)
14885#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)
14887#define GPIO_MODER_MODE12_Pos (24U)
14888#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)
14889#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
14890#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)
14891#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)
14893#define GPIO_MODER_MODE13_Pos (26U)
14894#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)
14895#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
14896#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)
14897#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)
14899#define GPIO_MODER_MODE14_Pos (28U)
14900#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)
14901#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
14902#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)
14903#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)
14905#define GPIO_MODER_MODE15_Pos (30U)
14906#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)
14907#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
14908#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)
14909#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)
14911/****************** Bits definition for GPIO_OTYPER register ****************/
14912#define GPIO_OTYPER_OT0_Pos (0U)
14913#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
14914#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
14915#define GPIO_OTYPER_OT1_Pos (1U)
14916#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
14917#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
14918#define GPIO_OTYPER_OT2_Pos (2U)
14919#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
14920#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
14921#define GPIO_OTYPER_OT3_Pos (3U)
14922#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
14923#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
14924#define GPIO_OTYPER_OT4_Pos (4U)
14925#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
14926#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
14927#define GPIO_OTYPER_OT5_Pos (5U)
14928#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
14929#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
14930#define GPIO_OTYPER_OT6_Pos (6U)
14931#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
14932#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
14933#define GPIO_OTYPER_OT7_Pos (7U)
14934#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
14935#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
14936#define GPIO_OTYPER_OT8_Pos (8U)
14937#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
14938#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
14939#define GPIO_OTYPER_OT9_Pos (9U)
14940#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
14941#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
14942#define GPIO_OTYPER_OT10_Pos (10U)
14943#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
14944#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
14945#define GPIO_OTYPER_OT11_Pos (11U)
14946#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
14947#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
14948#define GPIO_OTYPER_OT12_Pos (12U)
14949#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
14950#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
14951#define GPIO_OTYPER_OT13_Pos (13U)
14952#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
14953#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
14954#define GPIO_OTYPER_OT14_Pos (14U)
14955#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
14956#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
14957#define GPIO_OTYPER_OT15_Pos (15U)
14958#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
14959#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
14960
14961/****************** Bits definition for GPIO_OSPEEDR register ***************/
14962#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
14963#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
14964#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
14965#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
14966#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
14968#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
14969#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
14970#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
14971#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
14972#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
14974#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
14975#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
14976#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
14977#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
14978#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
14980#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
14981#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
14982#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
14983#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
14984#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
14986#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
14987#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
14988#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
14989#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
14990#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
14992#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
14993#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
14994#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
14995#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
14996#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
14998#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
14999#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
15000#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
15001#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
15002#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
15004#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
15005#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
15006#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
15007#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
15008#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
15010#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
15011#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
15012#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
15013#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
15014#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
15016#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
15017#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
15018#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
15019#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
15020#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
15022#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
15023#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
15024#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
15025#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
15026#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
15028#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
15029#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
15030#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
15031#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
15032#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
15034#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
15035#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
15036#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
15037#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
15038#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
15040#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
15041#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
15042#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
15043#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
15044#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
15046#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
15047#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
15048#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
15049#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
15050#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
15052#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
15053#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
15054#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
15055#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
15056#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
15058/****************** Bits definition for GPIO_PUPDR register *****************/
15059#define GPIO_PUPDR_PUPD0_Pos (0U)
15060#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
15061#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
15062#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
15063#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
15065#define GPIO_PUPDR_PUPD1_Pos (2U)
15066#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
15067#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
15068#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
15069#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
15071#define GPIO_PUPDR_PUPD2_Pos (4U)
15072#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
15073#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
15074#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
15075#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
15077#define GPIO_PUPDR_PUPD3_Pos (6U)
15078#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
15079#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
15080#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
15081#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
15083#define GPIO_PUPDR_PUPD4_Pos (8U)
15084#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
15085#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
15086#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
15087#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
15089#define GPIO_PUPDR_PUPD5_Pos (10U)
15090#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
15091#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
15092#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
15093#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
15095#define GPIO_PUPDR_PUPD6_Pos (12U)
15096#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
15097#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
15098#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
15099#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
15101#define GPIO_PUPDR_PUPD7_Pos (14U)
15102#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
15103#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
15104#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
15105#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
15107#define GPIO_PUPDR_PUPD8_Pos (16U)
15108#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
15109#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
15110#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
15111#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
15113#define GPIO_PUPDR_PUPD9_Pos (18U)
15114#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
15115#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
15116#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
15117#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
15119#define GPIO_PUPDR_PUPD10_Pos (20U)
15120#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
15121#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
15122#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
15123#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
15125#define GPIO_PUPDR_PUPD11_Pos (22U)
15126#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
15127#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
15128#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
15129#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
15131#define GPIO_PUPDR_PUPD12_Pos (24U)
15132#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
15133#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
15134#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
15135#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
15137#define GPIO_PUPDR_PUPD13_Pos (26U)
15138#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
15139#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
15140#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
15141#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
15143#define GPIO_PUPDR_PUPD14_Pos (28U)
15144#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
15145#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
15146#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
15147#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
15149#define GPIO_PUPDR_PUPD15_Pos (30U)
15150#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
15151#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
15152#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
15153#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
15155/****************** Bits definition for GPIO_IDR register *******************/
15156#define GPIO_IDR_ID0_Pos (0U)
15157#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
15158#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
15159#define GPIO_IDR_ID1_Pos (1U)
15160#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
15161#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
15162#define GPIO_IDR_ID2_Pos (2U)
15163#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
15164#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
15165#define GPIO_IDR_ID3_Pos (3U)
15166#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
15167#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
15168#define GPIO_IDR_ID4_Pos (4U)
15169#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
15170#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
15171#define GPIO_IDR_ID5_Pos (5U)
15172#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
15173#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
15174#define GPIO_IDR_ID6_Pos (6U)
15175#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
15176#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
15177#define GPIO_IDR_ID7_Pos (7U)
15178#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
15179#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
15180#define GPIO_IDR_ID8_Pos (8U)
15181#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
15182#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
15183#define GPIO_IDR_ID9_Pos (9U)
15184#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
15185#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
15186#define GPIO_IDR_ID10_Pos (10U)
15187#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
15188#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
15189#define GPIO_IDR_ID11_Pos (11U)
15190#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
15191#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
15192#define GPIO_IDR_ID12_Pos (12U)
15193#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
15194#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
15195#define GPIO_IDR_ID13_Pos (13U)
15196#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
15197#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
15198#define GPIO_IDR_ID14_Pos (14U)
15199#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
15200#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
15201#define GPIO_IDR_ID15_Pos (15U)
15202#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
15203#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
15204
15205/****************** Bits definition for GPIO_ODR register *******************/
15206#define GPIO_ODR_OD0_Pos (0U)
15207#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
15208#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
15209#define GPIO_ODR_OD1_Pos (1U)
15210#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
15211#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
15212#define GPIO_ODR_OD2_Pos (2U)
15213#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
15214#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
15215#define GPIO_ODR_OD3_Pos (3U)
15216#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
15217#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
15218#define GPIO_ODR_OD4_Pos (4U)
15219#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
15220#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
15221#define GPIO_ODR_OD5_Pos (5U)
15222#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
15223#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
15224#define GPIO_ODR_OD6_Pos (6U)
15225#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
15226#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
15227#define GPIO_ODR_OD7_Pos (7U)
15228#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
15229#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
15230#define GPIO_ODR_OD8_Pos (8U)
15231#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
15232#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
15233#define GPIO_ODR_OD9_Pos (9U)
15234#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
15235#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
15236#define GPIO_ODR_OD10_Pos (10U)
15237#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
15238#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
15239#define GPIO_ODR_OD11_Pos (11U)
15240#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
15241#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
15242#define GPIO_ODR_OD12_Pos (12U)
15243#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
15244#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
15245#define GPIO_ODR_OD13_Pos (13U)
15246#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
15247#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
15248#define GPIO_ODR_OD14_Pos (14U)
15249#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
15250#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
15251#define GPIO_ODR_OD15_Pos (15U)
15252#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
15253#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
15254
15255/****************** Bits definition for GPIO_BSRR register ******************/
15256#define GPIO_BSRR_BS0_Pos (0U)
15257#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
15258#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
15259#define GPIO_BSRR_BS1_Pos (1U)
15260#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
15261#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
15262#define GPIO_BSRR_BS2_Pos (2U)
15263#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
15264#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
15265#define GPIO_BSRR_BS3_Pos (3U)
15266#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
15267#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
15268#define GPIO_BSRR_BS4_Pos (4U)
15269#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
15270#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
15271#define GPIO_BSRR_BS5_Pos (5U)
15272#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
15273#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
15274#define GPIO_BSRR_BS6_Pos (6U)
15275#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
15276#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
15277#define GPIO_BSRR_BS7_Pos (7U)
15278#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
15279#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
15280#define GPIO_BSRR_BS8_Pos (8U)
15281#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
15282#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
15283#define GPIO_BSRR_BS9_Pos (9U)
15284#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
15285#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
15286#define GPIO_BSRR_BS10_Pos (10U)
15287#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
15288#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
15289#define GPIO_BSRR_BS11_Pos (11U)
15290#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
15291#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
15292#define GPIO_BSRR_BS12_Pos (12U)
15293#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
15294#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
15295#define GPIO_BSRR_BS13_Pos (13U)
15296#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
15297#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
15298#define GPIO_BSRR_BS14_Pos (14U)
15299#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
15300#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
15301#define GPIO_BSRR_BS15_Pos (15U)
15302#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
15303#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
15304#define GPIO_BSRR_BR0_Pos (16U)
15305#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
15306#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
15307#define GPIO_BSRR_BR1_Pos (17U)
15308#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
15309#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
15310#define GPIO_BSRR_BR2_Pos (18U)
15311#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
15312#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
15313#define GPIO_BSRR_BR3_Pos (19U)
15314#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
15315#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
15316#define GPIO_BSRR_BR4_Pos (20U)
15317#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
15318#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
15319#define GPIO_BSRR_BR5_Pos (21U)
15320#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
15321#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
15322#define GPIO_BSRR_BR6_Pos (22U)
15323#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
15324#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
15325#define GPIO_BSRR_BR7_Pos (23U)
15326#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
15327#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
15328#define GPIO_BSRR_BR8_Pos (24U)
15329#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
15330#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
15331#define GPIO_BSRR_BR9_Pos (25U)
15332#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
15333#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
15334#define GPIO_BSRR_BR10_Pos (26U)
15335#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
15336#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
15337#define GPIO_BSRR_BR11_Pos (27U)
15338#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
15339#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
15340#define GPIO_BSRR_BR12_Pos (28U)
15341#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
15342#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
15343#define GPIO_BSRR_BR13_Pos (29U)
15344#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
15345#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
15346#define GPIO_BSRR_BR14_Pos (30U)
15347#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
15348#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
15349#define GPIO_BSRR_BR15_Pos (31U)
15350#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
15351#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
15352
15353/****************** Bit definition for GPIO_LCKR register *********************/
15354#define GPIO_LCKR_LCK0_Pos (0U)
15355#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
15356#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
15357#define GPIO_LCKR_LCK1_Pos (1U)
15358#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
15359#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
15360#define GPIO_LCKR_LCK2_Pos (2U)
15361#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
15362#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
15363#define GPIO_LCKR_LCK3_Pos (3U)
15364#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
15365#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
15366#define GPIO_LCKR_LCK4_Pos (4U)
15367#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
15368#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
15369#define GPIO_LCKR_LCK5_Pos (5U)
15370#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
15371#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
15372#define GPIO_LCKR_LCK6_Pos (6U)
15373#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
15374#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
15375#define GPIO_LCKR_LCK7_Pos (7U)
15376#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
15377#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
15378#define GPIO_LCKR_LCK8_Pos (8U)
15379#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
15380#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
15381#define GPIO_LCKR_LCK9_Pos (9U)
15382#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
15383#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
15384#define GPIO_LCKR_LCK10_Pos (10U)
15385#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
15386#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
15387#define GPIO_LCKR_LCK11_Pos (11U)
15388#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
15389#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
15390#define GPIO_LCKR_LCK12_Pos (12U)
15391#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
15392#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
15393#define GPIO_LCKR_LCK13_Pos (13U)
15394#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
15395#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
15396#define GPIO_LCKR_LCK14_Pos (14U)
15397#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
15398#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
15399#define GPIO_LCKR_LCK15_Pos (15U)
15400#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
15401#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
15402#define GPIO_LCKR_LCKK_Pos (16U)
15403#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
15404#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
15405
15406/****************** Bit definition for GPIO_AFRL register ********************/
15407#define GPIO_AFRL_AFSEL0_Pos (0U)
15408#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
15409#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
15410#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
15411#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
15412#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
15413#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
15414#define GPIO_AFRL_AFSEL1_Pos (4U)
15415#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
15416#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
15417#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
15418#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
15419#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
15420#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
15421#define GPIO_AFRL_AFSEL2_Pos (8U)
15422#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
15423#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
15424#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
15425#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
15426#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
15427#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
15428#define GPIO_AFRL_AFSEL3_Pos (12U)
15429#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
15430#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
15431#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
15432#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
15433#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
15434#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
15435#define GPIO_AFRL_AFSEL4_Pos (16U)
15436#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
15437#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
15438#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
15439#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
15440#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
15441#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
15442#define GPIO_AFRL_AFSEL5_Pos (20U)
15443#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
15444#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
15445#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
15446#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
15447#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
15448#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
15449#define GPIO_AFRL_AFSEL6_Pos (24U)
15450#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
15451#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
15452#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
15453#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
15454#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
15455#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
15456#define GPIO_AFRL_AFSEL7_Pos (28U)
15457#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
15458#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
15459#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
15460#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
15461#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
15462#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
15464/* Legacy defines */
15465#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
15466#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
15467#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
15468#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
15469#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
15470#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
15471#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
15472#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
15473
15474/****************** Bit definition for GPIO_AFRH register ********************/
15475#define GPIO_AFRH_AFSEL8_Pos (0U)
15476#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
15477#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
15478#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
15479#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
15480#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
15481#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
15482#define GPIO_AFRH_AFSEL9_Pos (4U)
15483#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
15484#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
15485#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
15486#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
15487#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
15488#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
15489#define GPIO_AFRH_AFSEL10_Pos (8U)
15490#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
15491#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
15492#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
15493#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
15494#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
15495#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
15496#define GPIO_AFRH_AFSEL11_Pos (12U)
15497#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
15498#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
15499#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
15500#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
15501#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
15502#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
15503#define GPIO_AFRH_AFSEL12_Pos (16U)
15504#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
15505#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
15506#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
15507#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
15508#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
15509#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
15510#define GPIO_AFRH_AFSEL13_Pos (20U)
15511#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
15512#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
15513#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
15514#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
15515#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
15516#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
15517#define GPIO_AFRH_AFSEL14_Pos (24U)
15518#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
15519#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
15520#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
15521#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
15522#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
15523#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
15524#define GPIO_AFRH_AFSEL15_Pos (28U)
15525#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
15526#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
15527#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
15528#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
15529#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
15530#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
15532/* Legacy defines */
15533#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
15534#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
15535#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
15536#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
15537#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
15538#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
15539#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
15540#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
15541
15542/******************************************************************************/
15543/* */
15544/* HSEM HW Semaphore */
15545/* */
15546/******************************************************************************/
15547/******************** Bit definition for HSEM_R register ********************/
15548#define HSEM_R_PROCID_Pos (0U)
15549#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos)
15550#define HSEM_R_PROCID HSEM_R_PROCID_Msk
15551#define HSEM_R_COREID_Pos (8U)
15552#define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos)
15553#define HSEM_R_COREID HSEM_R_COREID_Msk
15554#define HSEM_R_LOCK_Pos (31U)
15555#define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos)
15556#define HSEM_R_LOCK HSEM_R_LOCK_Msk
15558/******************** Bit definition for HSEM_RLR register ******************/
15559#define HSEM_RLR_PROCID_Pos (0U)
15560#define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos)
15561#define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk
15562#define HSEM_RLR_COREID_Pos (8U)
15563#define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos)
15564#define HSEM_RLR_COREID HSEM_RLR_COREID_Msk
15565#define HSEM_RLR_LOCK_Pos (31U)
15566#define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos)
15567#define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk
15569/******************** Bit definition for HSEM_C1IER register *****************/
15570#define HSEM_C1IER_ISE0_Pos (0U)
15571#define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos)
15572#define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk
15573#define HSEM_C1IER_ISE1_Pos (1U)
15574#define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos)
15575#define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk
15576#define HSEM_C1IER_ISE2_Pos (2U)
15577#define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos)
15578#define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk
15579#define HSEM_C1IER_ISE3_Pos (3U)
15580#define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos)
15581#define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk
15582#define HSEM_C1IER_ISE4_Pos (4U)
15583#define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos)
15584#define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk
15585#define HSEM_C1IER_ISE5_Pos (5U)
15586#define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos)
15587#define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk
15588#define HSEM_C1IER_ISE6_Pos (6U)
15589#define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos)
15590#define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk
15591#define HSEM_C1IER_ISE7_Pos (7U)
15592#define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos)
15593#define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk
15594#define HSEM_C1IER_ISE8_Pos (8U)
15595#define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos)
15596#define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk
15597#define HSEM_C1IER_ISE9_Pos (9U)
15598#define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos)
15599#define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk
15600#define HSEM_C1IER_ISE10_Pos (10U)
15601#define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos)
15602#define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk
15603#define HSEM_C1IER_ISE11_Pos (11U)
15604#define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos)
15605#define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk
15606#define HSEM_C1IER_ISE12_Pos (12U)
15607#define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos)
15608#define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk
15609#define HSEM_C1IER_ISE13_Pos (13U)
15610#define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos)
15611#define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk
15612#define HSEM_C1IER_ISE14_Pos (14U)
15613#define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos)
15614#define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk
15615#define HSEM_C1IER_ISE15_Pos (15U)
15616#define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos)
15617#define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk
15618#define HSEM_C1IER_ISE16_Pos (16U)
15619#define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos)
15620#define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk
15621#define HSEM_C1IER_ISE17_Pos (17U)
15622#define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos)
15623#define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk
15624#define HSEM_C1IER_ISE18_Pos (18U)
15625#define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos)
15626#define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk
15627#define HSEM_C1IER_ISE19_Pos (19U)
15628#define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos)
15629#define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk
15630#define HSEM_C1IER_ISE20_Pos (20U)
15631#define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos)
15632#define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk
15633#define HSEM_C1IER_ISE21_Pos (21U)
15634#define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos)
15635#define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk
15636#define HSEM_C1IER_ISE22_Pos (22U)
15637#define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos)
15638#define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk
15639#define HSEM_C1IER_ISE23_Pos (23U)
15640#define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos)
15641#define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk
15642#define HSEM_C1IER_ISE24_Pos (24U)
15643#define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos)
15644#define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk
15645#define HSEM_C1IER_ISE25_Pos (25U)
15646#define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos)
15647#define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk
15648#define HSEM_C1IER_ISE26_Pos (26U)
15649#define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos)
15650#define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk
15651#define HSEM_C1IER_ISE27_Pos (27U)
15652#define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos)
15653#define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk
15654#define HSEM_C1IER_ISE28_Pos (28U)
15655#define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos)
15656#define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk
15657#define HSEM_C1IER_ISE29_Pos (29U)
15658#define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos)
15659#define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk
15660#define HSEM_C1IER_ISE30_Pos (30U)
15661#define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos)
15662#define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk
15663#define HSEM_C1IER_ISE31_Pos (31U)
15664#define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos)
15665#define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk
15667/******************** Bit definition for HSEM_C1ICR register *****************/
15668#define HSEM_C1ICR_ISC0_Pos (0U)
15669#define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos)
15670#define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk
15671#define HSEM_C1ICR_ISC1_Pos (1U)
15672#define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos)
15673#define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk
15674#define HSEM_C1ICR_ISC2_Pos (2U)
15675#define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos)
15676#define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk
15677#define HSEM_C1ICR_ISC3_Pos (3U)
15678#define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos)
15679#define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk
15680#define HSEM_C1ICR_ISC4_Pos (4U)
15681#define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos)
15682#define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk
15683#define HSEM_C1ICR_ISC5_Pos (5U)
15684#define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos)
15685#define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk
15686#define HSEM_C1ICR_ISC6_Pos (6U)
15687#define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos)
15688#define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk
15689#define HSEM_C1ICR_ISC7_Pos (7U)
15690#define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos)
15691#define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk
15692#define HSEM_C1ICR_ISC8_Pos (8U)
15693#define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos)
15694#define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk
15695#define HSEM_C1ICR_ISC9_Pos (9U)
15696#define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos)
15697#define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk
15698#define HSEM_C1ICR_ISC10_Pos (10U)
15699#define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos)
15700#define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk
15701#define HSEM_C1ICR_ISC11_Pos (11U)
15702#define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos)
15703#define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk
15704#define HSEM_C1ICR_ISC12_Pos (12U)
15705#define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos)
15706#define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk
15707#define HSEM_C1ICR_ISC13_Pos (13U)
15708#define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos)
15709#define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk
15710#define HSEM_C1ICR_ISC14_Pos (14U)
15711#define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos)
15712#define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk
15713#define HSEM_C1ICR_ISC15_Pos (15U)
15714#define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos)
15715#define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk
15716#define HSEM_C1ICR_ISC16_Pos (16U)
15717#define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos)
15718#define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk
15719#define HSEM_C1ICR_ISC17_Pos (17U)
15720#define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos)
15721#define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk
15722#define HSEM_C1ICR_ISC18_Pos (18U)
15723#define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos)
15724#define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk
15725#define HSEM_C1ICR_ISC19_Pos (19U)
15726#define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos)
15727#define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk
15728#define HSEM_C1ICR_ISC20_Pos (20U)
15729#define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos)
15730#define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk
15731#define HSEM_C1ICR_ISC21_Pos (21U)
15732#define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos)
15733#define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk
15734#define HSEM_C1ICR_ISC22_Pos (22U)
15735#define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos)
15736#define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk
15737#define HSEM_C1ICR_ISC23_Pos (23U)
15738#define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos)
15739#define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk
15740#define HSEM_C1ICR_ISC24_Pos (24U)
15741#define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos)
15742#define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk
15743#define HSEM_C1ICR_ISC25_Pos (25U)
15744#define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos)
15745#define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk
15746#define HSEM_C1ICR_ISC26_Pos (26U)
15747#define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos)
15748#define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk
15749#define HSEM_C1ICR_ISC27_Pos (27U)
15750#define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos)
15751#define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk
15752#define HSEM_C1ICR_ISC28_Pos (28U)
15753#define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos)
15754#define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk
15755#define HSEM_C1ICR_ISC29_Pos (29U)
15756#define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos)
15757#define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk
15758#define HSEM_C1ICR_ISC30_Pos (30U)
15759#define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos)
15760#define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk
15761#define HSEM_C1ICR_ISC31_Pos (31U)
15762#define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos)
15763#define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk
15765/******************** Bit definition for HSEM_C1ISR register *****************/
15766#define HSEM_C1ISR_ISF0_Pos (0U)
15767#define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos)
15768#define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk
15769#define HSEM_C1ISR_ISF1_Pos (1U)
15770#define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos)
15771#define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk
15772#define HSEM_C1ISR_ISF2_Pos (2U)
15773#define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos)
15774#define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk
15775#define HSEM_C1ISR_ISF3_Pos (3U)
15776#define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos)
15777#define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk
15778#define HSEM_C1ISR_ISF4_Pos (4U)
15779#define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos)
15780#define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk
15781#define HSEM_C1ISR_ISF5_Pos (5U)
15782#define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos)
15783#define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk
15784#define HSEM_C1ISR_ISF6_Pos (6U)
15785#define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos)
15786#define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk
15787#define HSEM_C1ISR_ISF7_Pos (7U)
15788#define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos)
15789#define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk
15790#define HSEM_C1ISR_ISF8_Pos (8U)
15791#define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos)
15792#define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk
15793#define HSEM_C1ISR_ISF9_Pos (9U)
15794#define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos)
15795#define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk
15796#define HSEM_C1ISR_ISF10_Pos (10U)
15797#define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos)
15798#define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk
15799#define HSEM_C1ISR_ISF11_Pos (11U)
15800#define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos)
15801#define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk
15802#define HSEM_C1ISR_ISF12_Pos (12U)
15803#define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos)
15804#define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk
15805#define HSEM_C1ISR_ISF13_Pos (13U)
15806#define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos)
15807#define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk
15808#define HSEM_C1ISR_ISF14_Pos (14U)
15809#define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos)
15810#define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk
15811#define HSEM_C1ISR_ISF15_Pos (15U)
15812#define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos)
15813#define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk
15814#define HSEM_C1ISR_ISF16_Pos (16U)
15815#define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos)
15816#define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk
15817#define HSEM_C1ISR_ISF17_Pos (17U)
15818#define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos)
15819#define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk
15820#define HSEM_C1ISR_ISF18_Pos (18U)
15821#define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos)
15822#define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk
15823#define HSEM_C1ISR_ISF19_Pos (19U)
15824#define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos)
15825#define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk
15826#define HSEM_C1ISR_ISF20_Pos (20U)
15827#define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos)
15828#define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk
15829#define HSEM_C1ISR_ISF21_Pos (21U)
15830#define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos)
15831#define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk
15832#define HSEM_C1ISR_ISF22_Pos (22U)
15833#define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos)
15834#define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk
15835#define HSEM_C1ISR_ISF23_Pos (23U)
15836#define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos)
15837#define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk
15838#define HSEM_C1ISR_ISF24_Pos (24U)
15839#define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos)
15840#define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk
15841#define HSEM_C1ISR_ISF25_Pos (25U)
15842#define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos)
15843#define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk
15844#define HSEM_C1ISR_ISF26_Pos (26U)
15845#define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos)
15846#define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk
15847#define HSEM_C1ISR_ISF27_Pos (27U)
15848#define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos)
15849#define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk
15850#define HSEM_C1ISR_ISF28_Pos (28U)
15851#define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos)
15852#define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk
15853#define HSEM_C1ISR_ISF29_Pos (29U)
15854#define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos)
15855#define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk
15856#define HSEM_C1ISR_ISF30_Pos (30U)
15857#define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos)
15858#define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk
15859#define HSEM_C1ISR_ISF31_Pos (31U)
15860#define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos)
15861#define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk
15863/******************** Bit definition for HSEM_C1MISR register *****************/
15864#define HSEM_C1MISR_MISF0_Pos (0U)
15865#define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos)
15866#define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk
15867#define HSEM_C1MISR_MISF1_Pos (1U)
15868#define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos)
15869#define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk
15870#define HSEM_C1MISR_MISF2_Pos (2U)
15871#define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos)
15872#define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk
15873#define HSEM_C1MISR_MISF3_Pos (3U)
15874#define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos)
15875#define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk
15876#define HSEM_C1MISR_MISF4_Pos (4U)
15877#define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos)
15878#define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk
15879#define HSEM_C1MISR_MISF5_Pos (5U)
15880#define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos)
15881#define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk
15882#define HSEM_C1MISR_MISF6_Pos (6U)
15883#define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos)
15884#define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk
15885#define HSEM_C1MISR_MISF7_Pos (7U)
15886#define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos)
15887#define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk
15888#define HSEM_C1MISR_MISF8_Pos (8U)
15889#define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos)
15890#define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk
15891#define HSEM_C1MISR_MISF9_Pos (9U)
15892#define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos)
15893#define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk
15894#define HSEM_C1MISR_MISF10_Pos (10U)
15895#define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos)
15896#define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk
15897#define HSEM_C1MISR_MISF11_Pos (11U)
15898#define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos)
15899#define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk
15900#define HSEM_C1MISR_MISF12_Pos (12U)
15901#define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos)
15902#define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk
15903#define HSEM_C1MISR_MISF13_Pos (13U)
15904#define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos)
15905#define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk
15906#define HSEM_C1MISR_MISF14_Pos (14U)
15907#define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos)
15908#define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk
15909#define HSEM_C1MISR_MISF15_Pos (15U)
15910#define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos)
15911#define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk
15912#define HSEM_C1MISR_MISF16_Pos (16U)
15913#define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos)
15914#define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk
15915#define HSEM_C1MISR_MISF17_Pos (17U)
15916#define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos)
15917#define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk
15918#define HSEM_C1MISR_MISF18_Pos (18U)
15919#define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos)
15920#define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk
15921#define HSEM_C1MISR_MISF19_Pos (19U)
15922#define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos)
15923#define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk
15924#define HSEM_C1MISR_MISF20_Pos (20U)
15925#define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos)
15926#define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk
15927#define HSEM_C1MISR_MISF21_Pos (21U)
15928#define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos)
15929#define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk
15930#define HSEM_C1MISR_MISF22_Pos (22U)
15931#define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos)
15932#define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk
15933#define HSEM_C1MISR_MISF23_Pos (23U)
15934#define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos)
15935#define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk
15936#define HSEM_C1MISR_MISF24_Pos (24U)
15937#define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos)
15938#define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk
15939#define HSEM_C1MISR_MISF25_Pos (25U)
15940#define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos)
15941#define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk
15942#define HSEM_C1MISR_MISF26_Pos (26U)
15943#define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos)
15944#define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk
15945#define HSEM_C1MISR_MISF27_Pos (27U)
15946#define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos)
15947#define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk
15948#define HSEM_C1MISR_MISF28_Pos (28U)
15949#define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos)
15950#define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk
15951#define HSEM_C1MISR_MISF29_Pos (29U)
15952#define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos)
15953#define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk
15954#define HSEM_C1MISR_MISF30_Pos (30U)
15955#define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos)
15956#define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk
15957#define HSEM_C1MISR_MISF31_Pos (31U)
15958#define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos)
15959#define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk
15961/******************** Bit definition for HSEM_C2IER register *****************/
15962#define HSEM_C2IER_ISE0_Pos (0U)
15963#define HSEM_C2IER_ISE0_Msk (0x1UL << HSEM_C2IER_ISE0_Pos)
15964#define HSEM_C2IER_ISE0 HSEM_C2IER_ISE0_Msk
15965#define HSEM_C2IER_ISE1_Pos (1U)
15966#define HSEM_C2IER_ISE1_Msk (0x1UL << HSEM_C2IER_ISE1_Pos)
15967#define HSEM_C2IER_ISE1 HSEM_C2IER_ISE1_Msk
15968#define HSEM_C2IER_ISE2_Pos (2U)
15969#define HSEM_C2IER_ISE2_Msk (0x1UL << HSEM_C2IER_ISE2_Pos)
15970#define HSEM_C2IER_ISE2 HSEM_C2IER_ISE2_Msk
15971#define HSEM_C2IER_ISE3_Pos (3U)
15972#define HSEM_C2IER_ISE3_Msk (0x1UL << HSEM_C2IER_ISE3_Pos)
15973#define HSEM_C2IER_ISE3 HSEM_C2IER_ISE3_Msk
15974#define HSEM_C2IER_ISE4_Pos (4U)
15975#define HSEM_C2IER_ISE4_Msk (0x1UL << HSEM_C2IER_ISE4_Pos)
15976#define HSEM_C2IER_ISE4 HSEM_C2IER_ISE4_Msk
15977#define HSEM_C2IER_ISE5_Pos (5U)
15978#define HSEM_C2IER_ISE5_Msk (0x1UL << HSEM_C2IER_ISE5_Pos)
15979#define HSEM_C2IER_ISE5 HSEM_C2IER_ISE5_Msk
15980#define HSEM_C2IER_ISE6_Pos (6U)
15981#define HSEM_C2IER_ISE6_Msk (0x1UL << HSEM_C2IER_ISE6_Pos)
15982#define HSEM_C2IER_ISE6 HSEM_C2IER_ISE6_Msk
15983#define HSEM_C2IER_ISE7_Pos (7U)
15984#define HSEM_C2IER_ISE7_Msk (0x1UL << HSEM_C2IER_ISE7_Pos)
15985#define HSEM_C2IER_ISE7 HSEM_C2IER_ISE7_Msk
15986#define HSEM_C2IER_ISE8_Pos (8U)
15987#define HSEM_C2IER_ISE8_Msk (0x1UL << HSEM_C2IER_ISE8_Pos)
15988#define HSEM_C2IER_ISE8 HSEM_C2IER_ISE8_Msk
15989#define HSEM_C2IER_ISE9_Pos (9U)
15990#define HSEM_C2IER_ISE9_Msk (0x1UL << HSEM_C2IER_ISE9_Pos)
15991#define HSEM_C2IER_ISE9 HSEM_C2IER_ISE9_Msk
15992#define HSEM_C2IER_ISE10_Pos (10U)
15993#define HSEM_C2IER_ISE10_Msk (0x1UL << HSEM_C2IER_ISE10_Pos)
15994#define HSEM_C2IER_ISE10 HSEM_C2IER_ISE10_Msk
15995#define HSEM_C2IER_ISE11_Pos (11U)
15996#define HSEM_C2IER_ISE11_Msk (0x1UL << HSEM_C2IER_ISE11_Pos)
15997#define HSEM_C2IER_ISE11 HSEM_C2IER_ISE11_Msk
15998#define HSEM_C2IER_ISE12_Pos (12U)
15999#define HSEM_C2IER_ISE12_Msk (0x1UL << HSEM_C2IER_ISE12_Pos)
16000#define HSEM_C2IER_ISE12 HSEM_C2IER_ISE12_Msk
16001#define HSEM_C2IER_ISE13_Pos (13U)
16002#define HSEM_C2IER_ISE13_Msk (0x1UL << HSEM_C2IER_ISE13_Pos)
16003#define HSEM_C2IER_ISE13 HSEM_C2IER_ISE13_Msk
16004#define HSEM_C2IER_ISE14_Pos (14U)
16005#define HSEM_C2IER_ISE14_Msk (0x1UL << HSEM_C2IER_ISE14_Pos)
16006#define HSEM_C2IER_ISE14 HSEM_C2IER_ISE14_Msk
16007#define HSEM_C2IER_ISE15_Pos (15U)
16008#define HSEM_C2IER_ISE15_Msk (0x1UL << HSEM_C2IER_ISE15_Pos)
16009#define HSEM_C2IER_ISE15 HSEM_C2IER_ISE15_Msk
16010#define HSEM_C2IER_ISE16_Pos (16U)
16011#define HSEM_C2IER_ISE16_Msk (0x1UL << HSEM_C2IER_ISE16_Pos)
16012#define HSEM_C2IER_ISE16 HSEM_C2IER_ISE16_Msk
16013#define HSEM_C2IER_ISE17_Pos (17U)
16014#define HSEM_C2IER_ISE17_Msk (0x1UL << HSEM_C2IER_ISE17_Pos)
16015#define HSEM_C2IER_ISE17 HSEM_C2IER_ISE17_Msk
16016#define HSEM_C2IER_ISE18_Pos (18U)
16017#define HSEM_C2IER_ISE18_Msk (0x1UL << HSEM_C2IER_ISE18_Pos)
16018#define HSEM_C2IER_ISE18 HSEM_C2IER_ISE18_Msk
16019#define HSEM_C2IER_ISE19_Pos (19U)
16020#define HSEM_C2IER_ISE19_Msk (0x1UL << HSEM_C2IER_ISE19_Pos)
16021#define HSEM_C2IER_ISE19 HSEM_C2IER_ISE19_Msk
16022#define HSEM_C2IER_ISE20_Pos (20U)
16023#define HSEM_C2IER_ISE20_Msk (0x1UL << HSEM_C2IER_ISE20_Pos)
16024#define HSEM_C2IER_ISE20 HSEM_C2IER_ISE20_Msk
16025#define HSEM_C2IER_ISE21_Pos (21U)
16026#define HSEM_C2IER_ISE21_Msk (0x1UL << HSEM_C2IER_ISE21_Pos)
16027#define HSEM_C2IER_ISE21 HSEM_C2IER_ISE21_Msk
16028#define HSEM_C2IER_ISE22_Pos (22U)
16029#define HSEM_C2IER_ISE22_Msk (0x1UL << HSEM_C2IER_ISE22_Pos)
16030#define HSEM_C2IER_ISE22 HSEM_C2IER_ISE22_Msk
16031#define HSEM_C2IER_ISE23_Pos (23U)
16032#define HSEM_C2IER_ISE23_Msk (0x1UL << HSEM_C2IER_ISE23_Pos)
16033#define HSEM_C2IER_ISE23 HSEM_C2IER_ISE23_Msk
16034#define HSEM_C2IER_ISE24_Pos (24U)
16035#define HSEM_C2IER_ISE24_Msk (0x1UL << HSEM_C2IER_ISE24_Pos)
16036#define HSEM_C2IER_ISE24 HSEM_C2IER_ISE24_Msk
16037#define HSEM_C2IER_ISE25_Pos (25U)
16038#define HSEM_C2IER_ISE25_Msk (0x1UL << HSEM_C2IER_ISE25_Pos)
16039#define HSEM_C2IER_ISE25 HSEM_C2IER_ISE25_Msk
16040#define HSEM_C2IER_ISE26_Pos (26U)
16041#define HSEM_C2IER_ISE26_Msk (0x1UL << HSEM_C2IER_ISE26_Pos)
16042#define HSEM_C2IER_ISE26 HSEM_C2IER_ISE26_Msk
16043#define HSEM_C2IER_ISE27_Pos (27U)
16044#define HSEM_C2IER_ISE27_Msk (0x1UL << HSEM_C2IER_ISE27_Pos)
16045#define HSEM_C2IER_ISE27 HSEM_C2IER_ISE27_Msk
16046#define HSEM_C2IER_ISE28_Pos (28U)
16047#define HSEM_C2IER_ISE28_Msk (0x1UL << HSEM_C2IER_ISE28_Pos)
16048#define HSEM_C2IER_ISE28 HSEM_C2IER_ISE28_Msk
16049#define HSEM_C2IER_ISE29_Pos (29U)
16050#define HSEM_C2IER_ISE29_Msk (0x1UL << HSEM_C2IER_ISE29_Pos)
16051#define HSEM_C2IER_ISE29 HSEM_C2IER_ISE29_Msk
16052#define HSEM_C2IER_ISE30_Pos (30U)
16053#define HSEM_C2IER_ISE30_Msk (0x1UL << HSEM_C2IER_ISE30_Pos)
16054#define HSEM_C2IER_ISE30 HSEM_C2IER_ISE30_Msk
16055#define HSEM_C2IER_ISE31_Pos (31U)
16056#define HSEM_C2IER_ISE31_Msk (0x1UL << HSEM_C2IER_ISE31_Pos)
16057#define HSEM_C2IER_ISE31 HSEM_C2IER_ISE31_Msk
16059/******************** Bit definition for HSEM_C2ICR register *****************/
16060#define HSEM_C2ICR_ISC0_Pos (0U)
16061#define HSEM_C2ICR_ISC0_Msk (0x1UL << HSEM_C2ICR_ISC0_Pos)
16062#define HSEM_C2ICR_ISC0 HSEM_C2ICR_ISC0_Msk
16063#define HSEM_C2ICR_ISC1_Pos (1U)
16064#define HSEM_C2ICR_ISC1_Msk (0x1UL << HSEM_C2ICR_ISC1_Pos)
16065#define HSEM_C2ICR_ISC1 HSEM_C2ICR_ISC1_Msk
16066#define HSEM_C2ICR_ISC2_Pos (2U)
16067#define HSEM_C2ICR_ISC2_Msk (0x1UL << HSEM_C2ICR_ISC2_Pos)
16068#define HSEM_C2ICR_ISC2 HSEM_C2ICR_ISC2_Msk
16069#define HSEM_C2ICR_ISC3_Pos (3U)
16070#define HSEM_C2ICR_ISC3_Msk (0x1UL << HSEM_C2ICR_ISC3_Pos)
16071#define HSEM_C2ICR_ISC3 HSEM_C2ICR_ISC3_Msk
16072#define HSEM_C2ICR_ISC4_Pos (4U)
16073#define HSEM_C2ICR_ISC4_Msk (0x1UL << HSEM_C2ICR_ISC4_Pos)
16074#define HSEM_C2ICR_ISC4 HSEM_C2ICR_ISC4_Msk
16075#define HSEM_C2ICR_ISC5_Pos (5U)
16076#define HSEM_C2ICR_ISC5_Msk (0x1UL << HSEM_C2ICR_ISC5_Pos)
16077#define HSEM_C2ICR_ISC5 HSEM_C2ICR_ISC5_Msk
16078#define HSEM_C2ICR_ISC6_Pos (6U)
16079#define HSEM_C2ICR_ISC6_Msk (0x1UL << HSEM_C2ICR_ISC6_Pos)
16080#define HSEM_C2ICR_ISC6 HSEM_C2ICR_ISC6_Msk
16081#define HSEM_C2ICR_ISC7_Pos (7U)
16082#define HSEM_C2ICR_ISC7_Msk (0x1UL << HSEM_C2ICR_ISC7_Pos)
16083#define HSEM_C2ICR_ISC7 HSEM_C2ICR_ISC7_Msk
16084#define HSEM_C2ICR_ISC8_Pos (8U)
16085#define HSEM_C2ICR_ISC8_Msk (0x1UL << HSEM_C2ICR_ISC8_Pos)
16086#define HSEM_C2ICR_ISC8 HSEM_C2ICR_ISC8_Msk
16087#define HSEM_C2ICR_ISC9_Pos (9U)
16088#define HSEM_C2ICR_ISC9_Msk (0x1UL << HSEM_C2ICR_ISC9_Pos)
16089#define HSEM_C2ICR_ISC9 HSEM_C2ICR_ISC9_Msk
16090#define HSEM_C2ICR_ISC10_Pos (10U)
16091#define HSEM_C2ICR_ISC10_Msk (0x1UL << HSEM_C2ICR_ISC10_Pos)
16092#define HSEM_C2ICR_ISC10 HSEM_C2ICR_ISC10_Msk
16093#define HSEM_C2ICR_ISC11_Pos (11U)
16094#define HSEM_C2ICR_ISC11_Msk (0x1UL << HSEM_C2ICR_ISC11_Pos)
16095#define HSEM_C2ICR_ISC11 HSEM_C2ICR_ISC11_Msk
16096#define HSEM_C2ICR_ISC12_Pos (12U)
16097#define HSEM_C2ICR_ISC12_Msk (0x1UL << HSEM_C2ICR_ISC12_Pos)
16098#define HSEM_C2ICR_ISC12 HSEM_C2ICR_ISC12_Msk
16099#define HSEM_C2ICR_ISC13_Pos (13U)
16100#define HSEM_C2ICR_ISC13_Msk (0x1UL << HSEM_C2ICR_ISC13_Pos)
16101#define HSEM_C2ICR_ISC13 HSEM_C2ICR_ISC13_Msk
16102#define HSEM_C2ICR_ISC14_Pos (14U)
16103#define HSEM_C2ICR_ISC14_Msk (0x1UL << HSEM_C2ICR_ISC14_Pos)
16104#define HSEM_C2ICR_ISC14 HSEM_C2ICR_ISC14_Msk
16105#define HSEM_C2ICR_ISC15_Pos (15U)
16106#define HSEM_C2ICR_ISC15_Msk (0x1UL << HSEM_C2ICR_ISC15_Pos)
16107#define HSEM_C2ICR_ISC15 HSEM_C2ICR_ISC15_Msk
16108#define HSEM_C2ICR_ISC16_Pos (16U)
16109#define HSEM_C2ICR_ISC16_Msk (0x1UL << HSEM_C2ICR_ISC16_Pos)
16110#define HSEM_C2ICR_ISC16 HSEM_C2ICR_ISC16_Msk
16111#define HSEM_C2ICR_ISC17_Pos (17U)
16112#define HSEM_C2ICR_ISC17_Msk (0x1UL << HSEM_C2ICR_ISC17_Pos)
16113#define HSEM_C2ICR_ISC17 HSEM_C2ICR_ISC17_Msk
16114#define HSEM_C2ICR_ISC18_Pos (18U)
16115#define HSEM_C2ICR_ISC18_Msk (0x1UL << HSEM_C2ICR_ISC18_Pos)
16116#define HSEM_C2ICR_ISC18 HSEM_C2ICR_ISC18_Msk
16117#define HSEM_C2ICR_ISC19_Pos (19U)
16118#define HSEM_C2ICR_ISC19_Msk (0x1UL << HSEM_C2ICR_ISC19_Pos)
16119#define HSEM_C2ICR_ISC19 HSEM_C2ICR_ISC19_Msk
16120#define HSEM_C2ICR_ISC20_Pos (20U)
16121#define HSEM_C2ICR_ISC20_Msk (0x1UL << HSEM_C2ICR_ISC20_Pos)
16122#define HSEM_C2ICR_ISC20 HSEM_C2ICR_ISC20_Msk
16123#define HSEM_C2ICR_ISC21_Pos (21U)
16124#define HSEM_C2ICR_ISC21_Msk (0x1UL << HSEM_C2ICR_ISC21_Pos)
16125#define HSEM_C2ICR_ISC21 HSEM_C2ICR_ISC21_Msk
16126#define HSEM_C2ICR_ISC22_Pos (22U)
16127#define HSEM_C2ICR_ISC22_Msk (0x1UL << HSEM_C2ICR_ISC22_Pos)
16128#define HSEM_C2ICR_ISC22 HSEM_C2ICR_ISC22_Msk
16129#define HSEM_C2ICR_ISC23_Pos (23U)
16130#define HSEM_C2ICR_ISC23_Msk (0x1UL << HSEM_C2ICR_ISC23_Pos)
16131#define HSEM_C2ICR_ISC23 HSEM_C2ICR_ISC23_Msk
16132#define HSEM_C2ICR_ISC24_Pos (24U)
16133#define HSEM_C2ICR_ISC24_Msk (0x1UL << HSEM_C2ICR_ISC24_Pos)
16134#define HSEM_C2ICR_ISC24 HSEM_C2ICR_ISC24_Msk
16135#define HSEM_C2ICR_ISC25_Pos (25U)
16136#define HSEM_C2ICR_ISC25_Msk (0x1UL << HSEM_C2ICR_ISC25_Pos)
16137#define HSEM_C2ICR_ISC25 HSEM_C2ICR_ISC25_Msk
16138#define HSEM_C2ICR_ISC26_Pos (26U)
16139#define HSEM_C2ICR_ISC26_Msk (0x1UL << HSEM_C2ICR_ISC26_Pos)
16140#define HSEM_C2ICR_ISC26 HSEM_C2ICR_ISC26_Msk
16141#define HSEM_C2ICR_ISC27_Pos (27U)
16142#define HSEM_C2ICR_ISC27_Msk (0x1UL << HSEM_C2ICR_ISC27_Pos)
16143#define HSEM_C2ICR_ISC27 HSEM_C2ICR_ISC27_Msk
16144#define HSEM_C2ICR_ISC28_Pos (28U)
16145#define HSEM_C2ICR_ISC28_Msk (0x1UL << HSEM_C2ICR_ISC28_Pos)
16146#define HSEM_C2ICR_ISC28 HSEM_C2ICR_ISC28_Msk
16147#define HSEM_C2ICR_ISC29_Pos (29U)
16148#define HSEM_C2ICR_ISC29_Msk (0x1UL << HSEM_C2ICR_ISC29_Pos)
16149#define HSEM_C2ICR_ISC29 HSEM_C2ICR_ISC29_Msk
16150#define HSEM_C2ICR_ISC30_Pos (30U)
16151#define HSEM_C2ICR_ISC30_Msk (0x1UL << HSEM_C2ICR_ISC30_Pos)
16152#define HSEM_C2ICR_ISC30 HSEM_C2ICR_ISC30_Msk
16153#define HSEM_C2ICR_ISC31_Pos (31U)
16154#define HSEM_C2ICR_ISC31_Msk (0x1UL << HSEM_C2ICR_ISC31_Pos)
16155#define HSEM_C2ICR_ISC31 HSEM_C2ICR_ISC31_Msk
16157/******************** Bit definition for HSEM_C2ISR register *****************/
16158#define HSEM_C2ISR_ISF0_Pos (0U)
16159#define HSEM_C2ISR_ISF0_Msk (0x1UL << HSEM_C2ISR_ISF0_Pos)
16160#define HSEM_C2ISR_ISF0 HSEM_C2ISR_ISF0_Msk
16161#define HSEM_C2ISR_ISF1_Pos (1U)
16162#define HSEM_C2ISR_ISF1_Msk (0x1UL << HSEM_C2ISR_ISF1_Pos)
16163#define HSEM_C2ISR_ISF1 HSEM_C2ISR_ISF1_Msk
16164#define HSEM_C2ISR_ISF2_Pos (2U)
16165#define HSEM_C2ISR_ISF2_Msk (0x1UL << HSEM_C2ISR_ISF2_Pos)
16166#define HSEM_C2ISR_ISF2 HSEM_C2ISR_ISF2_Msk
16167#define HSEM_C2ISR_ISF3_Pos (3U)
16168#define HSEM_C2ISR_ISF3_Msk (0x1UL << HSEM_C2ISR_ISF3_Pos)
16169#define HSEM_C2ISR_ISF3 HSEM_C2ISR_ISF3_Msk
16170#define HSEM_C2ISR_ISF4_Pos (4U)
16171#define HSEM_C2ISR_ISF4_Msk (0x1UL << HSEM_C2ISR_ISF4_Pos)
16172#define HSEM_C2ISR_ISF4 HSEM_C2ISR_ISF4_Msk
16173#define HSEM_C2ISR_ISF5_Pos (5U)
16174#define HSEM_C2ISR_ISF5_Msk (0x1UL << HSEM_C2ISR_ISF5_Pos)
16175#define HSEM_C2ISR_ISF5 HSEM_C2ISR_ISF5_Msk
16176#define HSEM_C2ISR_ISF6_Pos (6U)
16177#define HSEM_C2ISR_ISF6_Msk (0x1UL << HSEM_C2ISR_ISF6_Pos)
16178#define HSEM_C2ISR_ISF6 HSEM_C2ISR_ISF6_Msk
16179#define HSEM_C2ISR_ISF7_Pos (7U)
16180#define HSEM_C2ISR_ISF7_Msk (0x1UL << HSEM_C2ISR_ISF7_Pos)
16181#define HSEM_C2ISR_ISF7 HSEM_C2ISR_ISF7_Msk
16182#define HSEM_C2ISR_ISF8_Pos (8U)
16183#define HSEM_C2ISR_ISF8_Msk (0x1UL << HSEM_C2ISR_ISF8_Pos)
16184#define HSEM_C2ISR_ISF8 HSEM_C2ISR_ISF8_Msk
16185#define HSEM_C2ISR_ISF9_Pos (9U)
16186#define HSEM_C2ISR_ISF9_Msk (0x1UL << HSEM_C2ISR_ISF9_Pos)
16187#define HSEM_C2ISR_ISF9 HSEM_C2ISR_ISF9_Msk
16188#define HSEM_C2ISR_ISF10_Pos (10U)
16189#define HSEM_C2ISR_ISF10_Msk (0x1UL << HSEM_C2ISR_ISF10_Pos)
16190#define HSEM_C2ISR_ISF10 HSEM_C2ISR_ISF10_Msk
16191#define HSEM_C2ISR_ISF11_Pos (11U)
16192#define HSEM_C2ISR_ISF11_Msk (0x1UL << HSEM_C2ISR_ISF11_Pos)
16193#define HSEM_C2ISR_ISF11 HSEM_C2ISR_ISF11_Msk
16194#define HSEM_C2ISR_ISF12_Pos (12U)
16195#define HSEM_C2ISR_ISF12_Msk (0x1UL << HSEM_C2ISR_ISF12_Pos)
16196#define HSEM_C2ISR_ISF12 HSEM_C2ISR_ISF12_Msk
16197#define HSEM_C2ISR_ISF13_Pos (13U)
16198#define HSEM_C2ISR_ISF13_Msk (0x1UL << HSEM_C2ISR_ISF13_Pos)
16199#define HSEM_C2ISR_ISF13 HSEM_C2ISR_ISF13_Msk
16200#define HSEM_C2ISR_ISF14_Pos (14U)
16201#define HSEM_C2ISR_ISF14_Msk (0x1UL << HSEM_C2ISR_ISF14_Pos)
16202#define HSEM_C2ISR_ISF14 HSEM_C2ISR_ISF14_Msk
16203#define HSEM_C2ISR_ISF15_Pos (15U)
16204#define HSEM_C2ISR_ISF15_Msk (0x1UL << HSEM_C2ISR_ISF15_Pos)
16205#define HSEM_C2ISR_ISF15 HSEM_C2ISR_ISF15_Msk
16206#define HSEM_C2ISR_ISF16_Pos (16U)
16207#define HSEM_C2ISR_ISF16_Msk (0x1UL << HSEM_C2ISR_ISF16_Pos)
16208#define HSEM_C2ISR_ISF16 HSEM_C2ISR_ISF16_Msk
16209#define HSEM_C2ISR_ISF17_Pos (17U)
16210#define HSEM_C2ISR_ISF17_Msk (0x1UL << HSEM_C2ISR_ISF17_Pos)
16211#define HSEM_C2ISR_ISF17 HSEM_C2ISR_ISF17_Msk
16212#define HSEM_C2ISR_ISF18_Pos (18U)
16213#define HSEM_C2ISR_ISF18_Msk (0x1UL << HSEM_C2ISR_ISF18_Pos)
16214#define HSEM_C2ISR_ISF18 HSEM_C2ISR_ISF18_Msk
16215#define HSEM_C2ISR_ISF19_Pos (19U)
16216#define HSEM_C2ISR_ISF19_Msk (0x1UL << HSEM_C2ISR_ISF19_Pos)
16217#define HSEM_C2ISR_ISF19 HSEM_C2ISR_ISF19_Msk
16218#define HSEM_C2ISR_ISF20_Pos (20U)
16219#define HSEM_C2ISR_ISF20_Msk (0x1UL << HSEM_C2ISR_ISF20_Pos)
16220#define HSEM_C2ISR_ISF20 HSEM_C2ISR_ISF20_Msk
16221#define HSEM_C2ISR_ISF21_Pos (21U)
16222#define HSEM_C2ISR_ISF21_Msk (0x1UL << HSEM_C2ISR_ISF21_Pos)
16223#define HSEM_C2ISR_ISF21 HSEM_C2ISR_ISF21_Msk
16224#define HSEM_C2ISR_ISF22_Pos (22U)
16225#define HSEM_C2ISR_ISF22_Msk (0x1UL << HSEM_C2ISR_ISF22_Pos)
16226#define HSEM_C2ISR_ISF22 HSEM_C2ISR_ISF22_Msk
16227#define HSEM_C2ISR_ISF23_Pos (23U)
16228#define HSEM_C2ISR_ISF23_Msk (0x1UL << HSEM_C2ISR_ISF23_Pos)
16229#define HSEM_C2ISR_ISF23 HSEM_C2ISR_ISF23_Msk
16230#define HSEM_C2ISR_ISF24_Pos (24U)
16231#define HSEM_C2ISR_ISF24_Msk (0x1UL << HSEM_C2ISR_ISF24_Pos)
16232#define HSEM_C2ISR_ISF24 HSEM_C2ISR_ISF24_Msk
16233#define HSEM_C2ISR_ISF25_Pos (25U)
16234#define HSEM_C2ISR_ISF25_Msk (0x1UL << HSEM_C2ISR_ISF25_Pos)
16235#define HSEM_C2ISR_ISF25 HSEM_C2ISR_ISF25_Msk
16236#define HSEM_C2ISR_ISF26_Pos (26U)
16237#define HSEM_C2ISR_ISF26_Msk (0x1UL << HSEM_C2ISR_ISF26_Pos)
16238#define HSEM_C2ISR_ISF26 HSEM_C2ISR_ISF26_Msk
16239#define HSEM_C2ISR_ISF27_Pos (27U)
16240#define HSEM_C2ISR_ISF27_Msk (0x1UL << HSEM_C2ISR_ISF27_Pos)
16241#define HSEM_C2ISR_ISF27 HSEM_C2ISR_ISF27_Msk
16242#define HSEM_C2ISR_ISF28_Pos (28U)
16243#define HSEM_C2ISR_ISF28_Msk (0x1UL << HSEM_C2ISR_ISF28_Pos)
16244#define HSEM_C2ISR_ISF28 HSEM_C2ISR_ISF28_Msk
16245#define HSEM_C2ISR_ISF29_Pos (29U)
16246#define HSEM_C2ISR_ISF29_Msk (0x1UL << HSEM_C2ISR_ISF29_Pos)
16247#define HSEM_C2ISR_ISF29 HSEM_C2ISR_ISF29_Msk
16248#define HSEM_C2ISR_ISF30_Pos (30U)
16249#define HSEM_C2ISR_ISF30_Msk (0x1UL << HSEM_C2ISR_ISF30_Pos)
16250#define HSEM_C2ISR_ISF30 HSEM_C2ISR_ISF30_Msk
16251#define HSEM_C2ISR_ISF31_Pos (31U)
16252#define HSEM_C2ISR_ISF31_Msk (0x1UL << HSEM_C2ISR_ISF31_Pos)
16253#define HSEM_C2ISR_ISF31 HSEM_C2ISR_ISF31_Msk
16255/******************** Bit definition for HSEM_C2MISR register *****************/
16256#define HSEM_C2MISR_MISF0_Pos (0U)
16257#define HSEM_C2MISR_MISF0_Msk (0x1UL << HSEM_C2MISR_MISF0_Pos)
16258#define HSEM_C2MISR_MISF0 HSEM_C2MISR_MISF0_Msk
16259#define HSEM_C2MISR_MISF1_Pos (1U)
16260#define HSEM_C2MISR_MISF1_Msk (0x1UL << HSEM_C2MISR_MISF1_Pos)
16261#define HSEM_C2MISR_MISF1 HSEM_C2MISR_MISF1_Msk
16262#define HSEM_C2MISR_MISF2_Pos (2U)
16263#define HSEM_C2MISR_MISF2_Msk (0x1UL << HSEM_C2MISR_MISF2_Pos)
16264#define HSEM_C2MISR_MISF2 HSEM_C2MISR_MISF2_Msk
16265#define HSEM_C2MISR_MISF3_Pos (3U)
16266#define HSEM_C2MISR_MISF3_Msk (0x1UL << HSEM_C2MISR_MISF3_Pos)
16267#define HSEM_C2MISR_MISF3 HSEM_C2MISR_MISF3_Msk
16268#define HSEM_C2MISR_MISF4_Pos (4U)
16269#define HSEM_C2MISR_MISF4_Msk (0x1UL << HSEM_C2MISR_MISF4_Pos)
16270#define HSEM_C2MISR_MISF4 HSEM_C2MISR_MISF4_Msk
16271#define HSEM_C2MISR_MISF5_Pos (5U)
16272#define HSEM_C2MISR_MISF5_Msk (0x1UL << HSEM_C2MISR_MISF5_Pos)
16273#define HSEM_C2MISR_MISF5 HSEM_C2MISR_MISF5_Msk
16274#define HSEM_C2MISR_MISF6_Pos (6U)
16275#define HSEM_C2MISR_MISF6_Msk (0x1UL << HSEM_C2MISR_MISF6_Pos)
16276#define HSEM_C2MISR_MISF6 HSEM_C2MISR_MISF6_Msk
16277#define HSEM_C2MISR_MISF7_Pos (7U)
16278#define HSEM_C2MISR_MISF7_Msk (0x1UL << HSEM_C2MISR_MISF7_Pos)
16279#define HSEM_C2MISR_MISF7 HSEM_C2MISR_MISF7_Msk
16280#define HSEM_C2MISR_MISF8_Pos (8U)
16281#define HSEM_C2MISR_MISF8_Msk (0x1UL << HSEM_C2MISR_MISF8_Pos)
16282#define HSEM_C2MISR_MISF8 HSEM_C2MISR_MISF8_Msk
16283#define HSEM_C2MISR_MISF9_Pos (9U)
16284#define HSEM_C2MISR_MISF9_Msk (0x1UL << HSEM_C2MISR_MISF9_Pos)
16285#define HSEM_C2MISR_MISF9 HSEM_C2MISR_MISF9_Msk
16286#define HSEM_C2MISR_MISF10_Pos (10U)
16287#define HSEM_C2MISR_MISF10_Msk (0x1UL << HSEM_C2MISR_MISF10_Pos)
16288#define HSEM_C2MISR_MISF10 HSEM_C2MISR_MISF10_Msk
16289#define HSEM_C2MISR_MISF11_Pos (11U)
16290#define HSEM_C2MISR_MISF11_Msk (0x1UL << HSEM_C2MISR_MISF11_Pos)
16291#define HSEM_C2MISR_MISF11 HSEM_C2MISR_MISF11_Msk
16292#define HSEM_C2MISR_MISF12_Pos (12U)
16293#define HSEM_C2MISR_MISF12_Msk (0x1UL << HSEM_C2MISR_MISF12_Pos)
16294#define HSEM_C2MISR_MISF12 HSEM_C2MISR_MISF12_Msk
16295#define HSEM_C2MISR_MISF13_Pos (13U)
16296#define HSEM_C2MISR_MISF13_Msk (0x1UL << HSEM_C2MISR_MISF13_Pos)
16297#define HSEM_C2MISR_MISF13 HSEM_C2MISR_MISF13_Msk
16298#define HSEM_C2MISR_MISF14_Pos (14U)
16299#define HSEM_C2MISR_MISF14_Msk (0x1UL << HSEM_C2MISR_MISF14_Pos)
16300#define HSEM_C2MISR_MISF14 HSEM_C2MISR_MISF14_Msk
16301#define HSEM_C2MISR_MISF15_Pos (15U)
16302#define HSEM_C2MISR_MISF15_Msk (0x1UL << HSEM_C2MISR_MISF15_Pos)
16303#define HSEM_C2MISR_MISF15 HSEM_C2MISR_MISF15_Msk
16304#define HSEM_C2MISR_MISF16_Pos (16U)
16305#define HSEM_C2MISR_MISF16_Msk (0x1UL << HSEM_C2MISR_MISF16_Pos)
16306#define HSEM_C2MISR_MISF16 HSEM_C2MISR_MISF16_Msk
16307#define HSEM_C2MISR_MISF17_Pos (17U)
16308#define HSEM_C2MISR_MISF17_Msk (0x1UL << HSEM_C2MISR_MISF17_Pos)
16309#define HSEM_C2MISR_MISF17 HSEM_C2MISR_MISF17_Msk
16310#define HSEM_C2MISR_MISF18_Pos (18U)
16311#define HSEM_C2MISR_MISF18_Msk (0x1UL << HSEM_C2MISR_MISF18_Pos)
16312#define HSEM_C2MISR_MISF18 HSEM_C2MISR_MISF18_Msk
16313#define HSEM_C2MISR_MISF19_Pos (19U)
16314#define HSEM_C2MISR_MISF19_Msk (0x1UL << HSEM_C2MISR_MISF19_Pos)
16315#define HSEM_C2MISR_MISF19 HSEM_C2MISR_MISF19_Msk
16316#define HSEM_C2MISR_MISF20_Pos (20U)
16317#define HSEM_C2MISR_MISF20_Msk (0x1UL << HSEM_C2MISR_MISF20_Pos)
16318#define HSEM_C2MISR_MISF20 HSEM_C2MISR_MISF20_Msk
16319#define HSEM_C2MISR_MISF21_Pos (21U)
16320#define HSEM_C2MISR_MISF21_Msk (0x1UL << HSEM_C2MISR_MISF21_Pos)
16321#define HSEM_C2MISR_MISF21 HSEM_C2MISR_MISF21_Msk
16322#define HSEM_C2MISR_MISF22_Pos (22U)
16323#define HSEM_C2MISR_MISF22_Msk (0x1UL << HSEM_C2MISR_MISF22_Pos)
16324#define HSEM_C2MISR_MISF22 HSEM_C2MISR_MISF22_Msk
16325#define HSEM_C2MISR_MISF23_Pos (23U)
16326#define HSEM_C2MISR_MISF23_Msk (0x1UL << HSEM_C2MISR_MISF23_Pos)
16327#define HSEM_C2MISR_MISF23 HSEM_C2MISR_MISF23_Msk
16328#define HSEM_C2MISR_MISF24_Pos (24U)
16329#define HSEM_C2MISR_MISF24_Msk (0x1UL << HSEM_C2MISR_MISF24_Pos)
16330#define HSEM_C2MISR_MISF24 HSEM_C2MISR_MISF24_Msk
16331#define HSEM_C2MISR_MISF25_Pos (25U)
16332#define HSEM_C2MISR_MISF25_Msk (0x1UL << HSEM_C2MISR_MISF25_Pos)
16333#define HSEM_C2MISR_MISF25 HSEM_C2MISR_MISF25_Msk
16334#define HSEM_C2MISR_MISF26_Pos (26U)
16335#define HSEM_C2MISR_MISF26_Msk (0x1UL << HSEM_C2MISR_MISF26_Pos)
16336#define HSEM_C2MISR_MISF26 HSEM_C2MISR_MISF26_Msk
16337#define HSEM_C2MISR_MISF27_Pos (27U)
16338#define HSEM_C2MISR_MISF27_Msk (0x1UL << HSEM_C2MISR_MISF27_Pos)
16339#define HSEM_C2MISR_MISF27 HSEM_C2MISR_MISF27_Msk
16340#define HSEM_C2MISR_MISF28_Pos (28U)
16341#define HSEM_C2MISR_MISF28_Msk (0x1UL << HSEM_C2MISR_MISF28_Pos)
16342#define HSEM_C2MISR_MISF28 HSEM_C2MISR_MISF28_Msk
16343#define HSEM_C2MISR_MISF29_Pos (29U)
16344#define HSEM_C2MISR_MISF29_Msk (0x1UL << HSEM_C2MISR_MISF29_Pos)
16345#define HSEM_C2MISR_MISF29 HSEM_C2MISR_MISF29_Msk
16346#define HSEM_C2MISR_MISF30_Pos (30U)
16347#define HSEM_C2MISR_MISF30_Msk (0x1UL << HSEM_C2MISR_MISF30_Pos)
16348#define HSEM_C2MISR_MISF30 HSEM_C2MISR_MISF30_Msk
16349#define HSEM_C2MISR_MISF31_Pos (31U)
16350#define HSEM_C2MISR_MISF31_Msk (0x1UL << HSEM_C2MISR_MISF31_Pos)
16351#define HSEM_C2MISR_MISF31 HSEM_C2MISR_MISF31_Msk
16352/******************** Bit definition for HSEM_CR register *****************/
16353#define HSEM_CR_COREID_Pos (8U)
16354#define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos)
16355#define HSEM_CR_COREID HSEM_CR_COREID_Msk
16356#define HSEM_CR_KEY_Pos (16U)
16357#define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos)
16358#define HSEM_CR_KEY HSEM_CR_KEY_Msk
16360/******************** Bit definition for HSEM_KEYR register *****************/
16361#define HSEM_KEYR_KEY_Pos (16U)
16362#define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos)
16363#define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk
16365/******************************************************************************/
16366/* */
16367/* Inter-integrated Circuit Interface (I2C) */
16368/* */
16369/******************************************************************************/
16370/******************* Bit definition for I2C_CR1 register *******************/
16371#define I2C_CR1_PE_Pos (0U)
16372#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
16373#define I2C_CR1_PE I2C_CR1_PE_Msk
16374#define I2C_CR1_TXIE_Pos (1U)
16375#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
16376#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
16377#define I2C_CR1_RXIE_Pos (2U)
16378#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
16379#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
16380#define I2C_CR1_ADDRIE_Pos (3U)
16381#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
16382#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
16383#define I2C_CR1_NACKIE_Pos (4U)
16384#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
16385#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
16386#define I2C_CR1_STOPIE_Pos (5U)
16387#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
16388#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
16389#define I2C_CR1_TCIE_Pos (6U)
16390#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
16391#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
16392#define I2C_CR1_ERRIE_Pos (7U)
16393#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
16394#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
16395#define I2C_CR1_DNF_Pos (8U)
16396#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
16397#define I2C_CR1_DNF I2C_CR1_DNF_Msk
16398#define I2C_CR1_ANFOFF_Pos (12U)
16399#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
16400#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
16401#define I2C_CR1_TXDMAEN_Pos (14U)
16402#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
16403#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
16404#define I2C_CR1_RXDMAEN_Pos (15U)
16405#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
16406#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
16407#define I2C_CR1_SBC_Pos (16U)
16408#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
16409#define I2C_CR1_SBC I2C_CR1_SBC_Msk
16410#define I2C_CR1_NOSTRETCH_Pos (17U)
16411#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
16412#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
16413#define I2C_CR1_WUPEN_Pos (18U)
16414#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
16415#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
16416#define I2C_CR1_GCEN_Pos (19U)
16417#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
16418#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
16419#define I2C_CR1_SMBHEN_Pos (20U)
16420#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
16421#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
16422#define I2C_CR1_SMBDEN_Pos (21U)
16423#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
16424#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
16425#define I2C_CR1_ALERTEN_Pos (22U)
16426#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
16427#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
16428#define I2C_CR1_PECEN_Pos (23U)
16429#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
16430#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
16432/****************** Bit definition for I2C_CR2 register ********************/
16433#define I2C_CR2_SADD_Pos (0U)
16434#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
16435#define I2C_CR2_SADD I2C_CR2_SADD_Msk
16436#define I2C_CR2_RD_WRN_Pos (10U)
16437#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
16438#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
16439#define I2C_CR2_ADD10_Pos (11U)
16440#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
16441#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
16442#define I2C_CR2_HEAD10R_Pos (12U)
16443#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
16444#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
16445#define I2C_CR2_START_Pos (13U)
16446#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
16447#define I2C_CR2_START I2C_CR2_START_Msk
16448#define I2C_CR2_STOP_Pos (14U)
16449#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
16450#define I2C_CR2_STOP I2C_CR2_STOP_Msk
16451#define I2C_CR2_NACK_Pos (15U)
16452#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
16453#define I2C_CR2_NACK I2C_CR2_NACK_Msk
16454#define I2C_CR2_NBYTES_Pos (16U)
16455#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
16456#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
16457#define I2C_CR2_RELOAD_Pos (24U)
16458#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
16459#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
16460#define I2C_CR2_AUTOEND_Pos (25U)
16461#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
16462#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
16463#define I2C_CR2_PECBYTE_Pos (26U)
16464#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
16465#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
16467/******************* Bit definition for I2C_OAR1 register ******************/
16468#define I2C_OAR1_OA1_Pos (0U)
16469#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
16470#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
16471#define I2C_OAR1_OA1MODE_Pos (10U)
16472#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
16473#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
16474#define I2C_OAR1_OA1EN_Pos (15U)
16475#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
16476#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
16478/******************* Bit definition for I2C_OAR2 register ******************/
16479#define I2C_OAR2_OA2_Pos (1U)
16480#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
16481#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
16482#define I2C_OAR2_OA2MSK_Pos (8U)
16483#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
16484#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
16485#define I2C_OAR2_OA2NOMASK 0x00000000UL
16486#define I2C_OAR2_OA2MASK01_Pos (8U)
16487#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
16488#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
16489#define I2C_OAR2_OA2MASK02_Pos (9U)
16490#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
16491#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
16492#define I2C_OAR2_OA2MASK03_Pos (8U)
16493#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
16494#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
16495#define I2C_OAR2_OA2MASK04_Pos (10U)
16496#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
16497#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
16498#define I2C_OAR2_OA2MASK05_Pos (8U)
16499#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
16500#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
16501#define I2C_OAR2_OA2MASK06_Pos (9U)
16502#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
16503#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
16504#define I2C_OAR2_OA2MASK07_Pos (8U)
16505#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
16506#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
16507#define I2C_OAR2_OA2EN_Pos (15U)
16508#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
16509#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
16511/******************* Bit definition for I2C_TIMINGR register *******************/
16512#define I2C_TIMINGR_SCLL_Pos (0U)
16513#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
16514#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
16515#define I2C_TIMINGR_SCLH_Pos (8U)
16516#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
16517#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
16518#define I2C_TIMINGR_SDADEL_Pos (16U)
16519#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
16520#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
16521#define I2C_TIMINGR_SCLDEL_Pos (20U)
16522#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
16523#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
16524#define I2C_TIMINGR_PRESC_Pos (28U)
16525#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
16526#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
16528/******************* Bit definition for I2C_TIMEOUTR register *******************/
16529#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
16530#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
16531#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
16532#define I2C_TIMEOUTR_TIDLE_Pos (12U)
16533#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
16534#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
16535#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
16536#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
16537#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
16538#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
16539#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
16540#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
16541#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
16542#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
16543#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
16545/****************** Bit definition for I2C_ISR register *********************/
16546#define I2C_ISR_TXE_Pos (0U)
16547#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
16548#define I2C_ISR_TXE I2C_ISR_TXE_Msk
16549#define I2C_ISR_TXIS_Pos (1U)
16550#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
16551#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
16552#define I2C_ISR_RXNE_Pos (2U)
16553#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
16554#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
16555#define I2C_ISR_ADDR_Pos (3U)
16556#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
16557#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
16558#define I2C_ISR_NACKF_Pos (4U)
16559#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
16560#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
16561#define I2C_ISR_STOPF_Pos (5U)
16562#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
16563#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
16564#define I2C_ISR_TC_Pos (6U)
16565#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
16566#define I2C_ISR_TC I2C_ISR_TC_Msk
16567#define I2C_ISR_TCR_Pos (7U)
16568#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
16569#define I2C_ISR_TCR I2C_ISR_TCR_Msk
16570#define I2C_ISR_BERR_Pos (8U)
16571#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
16572#define I2C_ISR_BERR I2C_ISR_BERR_Msk
16573#define I2C_ISR_ARLO_Pos (9U)
16574#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
16575#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
16576#define I2C_ISR_OVR_Pos (10U)
16577#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
16578#define I2C_ISR_OVR I2C_ISR_OVR_Msk
16579#define I2C_ISR_PECERR_Pos (11U)
16580#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
16581#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
16582#define I2C_ISR_TIMEOUT_Pos (12U)
16583#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
16584#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
16585#define I2C_ISR_ALERT_Pos (13U)
16586#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
16587#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
16588#define I2C_ISR_BUSY_Pos (15U)
16589#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
16590#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
16591#define I2C_ISR_DIR_Pos (16U)
16592#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
16593#define I2C_ISR_DIR I2C_ISR_DIR_Msk
16594#define I2C_ISR_ADDCODE_Pos (17U)
16595#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
16596#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
16598/****************** Bit definition for I2C_ICR register *********************/
16599#define I2C_ICR_ADDRCF_Pos (3U)
16600#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
16601#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
16602#define I2C_ICR_NACKCF_Pos (4U)
16603#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
16604#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
16605#define I2C_ICR_STOPCF_Pos (5U)
16606#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
16607#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
16608#define I2C_ICR_BERRCF_Pos (8U)
16609#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
16610#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
16611#define I2C_ICR_ARLOCF_Pos (9U)
16612#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
16613#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
16614#define I2C_ICR_OVRCF_Pos (10U)
16615#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
16616#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
16617#define I2C_ICR_PECCF_Pos (11U)
16618#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
16619#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
16620#define I2C_ICR_TIMOUTCF_Pos (12U)
16621#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
16622#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
16623#define I2C_ICR_ALERTCF_Pos (13U)
16624#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
16625#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
16627/****************** Bit definition for I2C_PECR register *********************/
16628#define I2C_PECR_PEC_Pos (0U)
16629#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
16630#define I2C_PECR_PEC I2C_PECR_PEC_Msk
16632/****************** Bit definition for I2C_RXDR register *********************/
16633#define I2C_RXDR_RXDATA_Pos (0U)
16634#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
16635#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
16637/****************** Bit definition for I2C_TXDR register *********************/
16638#define I2C_TXDR_TXDATA_Pos (0U)
16639#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
16640#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
16642/******************************************************************************/
16643/* */
16644/* Independent WATCHDOG */
16645/* */
16646/******************************************************************************/
16647/******************* Bit definition for IWDG_KR register ********************/
16648#define IWDG_KR_KEY_Pos (0U)
16649#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
16650#define IWDG_KR_KEY IWDG_KR_KEY_Msk
16652/******************* Bit definition for IWDG_PR register ********************/
16653#define IWDG_PR_PR_Pos (0U)
16654#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
16655#define IWDG_PR_PR IWDG_PR_PR_Msk
16656#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
16657#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
16658#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
16660/******************* Bit definition for IWDG_RLR register *******************/
16661#define IWDG_RLR_RL_Pos (0U)
16662#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
16663#define IWDG_RLR_RL IWDG_RLR_RL_Msk
16665/******************* Bit definition for IWDG_SR register ********************/
16666#define IWDG_SR_PVU_Pos (0U)
16667#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
16668#define IWDG_SR_PVU IWDG_SR_PVU_Msk
16669#define IWDG_SR_RVU_Pos (1U)
16670#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
16671#define IWDG_SR_RVU IWDG_SR_RVU_Msk
16672#define IWDG_SR_WVU_Pos (2U)
16673#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
16674#define IWDG_SR_WVU IWDG_SR_WVU_Msk
16676/******************* Bit definition for IWDG_KR register ********************/
16677#define IWDG_WINR_WIN_Pos (0U)
16678#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
16679#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
16681/******************************************************************************/
16682/* */
16683/* JPEG Encoder/Decoder */
16684/* */
16685/******************************************************************************/
16686/******************** Bit definition for CONFR0 register ********************/
16687#define JPEG_CONFR0_START_Pos (0U)
16688#define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos)
16689#define JPEG_CONFR0_START JPEG_CONFR0_START_Msk
16691/******************** Bit definition for CONFR1 register ********************/
16692#define JPEG_CONFR1_NF_Pos (0U)
16693#define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos)
16694#define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk
16695#define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos)
16696#define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos)
16697#define JPEG_CONFR1_DE_Pos (3U)
16698#define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos)
16699#define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk
16700#define JPEG_CONFR1_COLORSPACE_Pos (4U)
16701#define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)
16702#define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk
16703#define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)
16704#define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)
16705#define JPEG_CONFR1_NS_Pos (6U)
16706#define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos)
16707#define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk
16708#define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos)
16709#define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos)
16710#define JPEG_CONFR1_HDR_Pos (8U)
16711#define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos)
16712#define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk
16713#define JPEG_CONFR1_YSIZE_Pos (16U)
16714#define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)
16715#define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk
16717/******************** Bit definition for CONFR2 register ********************/
16718#define JPEG_CONFR2_NMCU_Pos (0U)
16719#define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)
16720#define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk
16722/******************** Bit definition for CONFR3 register ********************/
16723#define JPEG_CONFR3_XSIZE_Pos (16U)
16724#define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)
16725#define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk
16727/******************** Bit definition for CONFR4 register ********************/
16728#define JPEG_CONFR4_HD_Pos (0U)
16729#define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos)
16730#define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk
16731#define JPEG_CONFR4_HA_Pos (1U)
16732#define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos)
16733#define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk
16734#define JPEG_CONFR4_QT_Pos (2U)
16735#define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos)
16736#define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk
16737#define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos)
16738#define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos)
16739#define JPEG_CONFR4_NB_Pos (4U)
16740#define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos)
16741#define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk
16742#define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos)
16743#define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos)
16744#define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos)
16745#define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos)
16746#define JPEG_CONFR4_VSF_Pos (8U)
16747#define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos)
16748#define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk
16749#define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos)
16750#define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos)
16751#define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos)
16752#define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos)
16753#define JPEG_CONFR4_HSF_Pos (12U)
16754#define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos)
16755#define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk
16756#define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos)
16757#define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos)
16758#define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos)
16759#define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos)
16761/******************** Bit definition for CONFR5 register ********************/
16762#define JPEG_CONFR5_HD_Pos (0U)
16763#define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos)
16764#define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk
16765#define JPEG_CONFR5_HA_Pos (1U)
16766#define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos)
16767#define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk
16768#define JPEG_CONFR5_QT_Pos (2U)
16769#define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos)
16770#define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk
16771#define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos)
16772#define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos)
16773#define JPEG_CONFR5_NB_Pos (4U)
16774#define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos)
16775#define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk
16776#define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos)
16777#define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos)
16778#define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos)
16779#define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos)
16780#define JPEG_CONFR5_VSF_Pos (8U)
16781#define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos)
16782#define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk
16783#define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos)
16784#define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos)
16785#define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos)
16786#define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos)
16787#define JPEG_CONFR5_HSF_Pos (12U)
16788#define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos)
16789#define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk
16790#define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos)
16791#define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos)
16792#define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos)
16793#define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos)
16795/******************** Bit definition for CONFR6 register ********************/
16796#define JPEG_CONFR6_HD_Pos (0U)
16797#define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos)
16798#define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk
16799#define JPEG_CONFR6_HA_Pos (1U)
16800#define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos)
16801#define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk
16802#define JPEG_CONFR6_QT_Pos (2U)
16803#define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos)
16804#define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk
16805#define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos)
16806#define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos)
16807#define JPEG_CONFR6_NB_Pos (4U)
16808#define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos)
16809#define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk
16810#define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos)
16811#define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos)
16812#define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos)
16813#define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos)
16814#define JPEG_CONFR6_VSF_Pos (8U)
16815#define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos)
16816#define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk
16817#define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos)
16818#define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos)
16819#define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos)
16820#define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos)
16821#define JPEG_CONFR6_HSF_Pos (12U)
16822#define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos)
16823#define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk
16824#define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos)
16825#define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos)
16826#define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos)
16827#define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos)
16829/******************** Bit definition for CONFR7 register ********************/
16830#define JPEG_CONFR7_HD_Pos (0U)
16831#define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos)
16832#define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk
16833#define JPEG_CONFR7_HA_Pos (1U)
16834#define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos)
16835#define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk
16836#define JPEG_CONFR7_QT_Pos (2U)
16837#define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos)
16838#define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk
16839#define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos)
16840#define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos)
16841#define JPEG_CONFR7_NB_Pos (4U)
16842#define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos)
16843#define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk
16844#define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos)
16845#define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos)
16846#define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos)
16847#define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos)
16848#define JPEG_CONFR7_VSF_Pos (8U)
16849#define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos)
16850#define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk
16851#define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos)
16852#define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos)
16853#define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos)
16854#define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos)
16855#define JPEG_CONFR7_HSF_Pos (12U)
16856#define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos)
16857#define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk
16858#define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos)
16859#define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos)
16860#define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos)
16861#define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos)
16863/******************** Bit definition for CR register ********************/
16864#define JPEG_CR_JCEN_Pos (0U)
16865#define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos)
16866#define JPEG_CR_JCEN JPEG_CR_JCEN_Msk
16867#define JPEG_CR_IFTIE_Pos (1U)
16868#define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos)
16869#define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk
16870#define JPEG_CR_IFNFIE_Pos (2U)
16871#define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos)
16872#define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk
16873#define JPEG_CR_OFTIE_Pos (3U)
16874#define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos)
16875#define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk
16876#define JPEG_CR_OFNEIE_Pos (4U)
16877#define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos)
16878#define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk
16879#define JPEG_CR_EOCIE_Pos (5U)
16880#define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos)
16881#define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk
16882#define JPEG_CR_HPDIE_Pos (6U)
16883#define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos)
16884#define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk
16885#define JPEG_CR_IFF_Pos (13U)
16886#define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos)
16887#define JPEG_CR_IFF JPEG_CR_IFF_Msk
16888#define JPEG_CR_OFF_Pos (14U)
16889#define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos)
16890#define JPEG_CR_OFF JPEG_CR_OFF_Msk
16892/******************** Bit definition for SR register ********************/
16893#define JPEG_SR_IFTF_Pos (1U)
16894#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos)
16895#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk
16896#define JPEG_SR_IFNFF_Pos (2U)
16897#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos)
16898#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk
16899#define JPEG_SR_OFTF_Pos (3U)
16900#define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos)
16901#define JPEG_SR_OFTF JPEG_SR_OFTF_Msk
16902#define JPEG_SR_OFNEF_Pos (4U)
16903#define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos)
16904#define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk
16905#define JPEG_SR_EOCF_Pos (5U)
16906#define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos)
16907#define JPEG_SR_EOCF JPEG_SR_EOCF_Msk
16908#define JPEG_SR_HPDF_Pos (6U)
16909#define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos)
16910#define JPEG_SR_HPDF JPEG_SR_HPDF_Msk
16911#define JPEG_SR_COF_Pos (7U)
16912#define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos)
16913#define JPEG_SR_COF JPEG_SR_COF_Msk
16915/******************** Bit definition for CFR register ********************/
16916#define JPEG_CFR_CEOCF_Pos (4U)
16917#define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos)
16918#define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk
16919#define JPEG_CFR_CHPDF_Pos (5U)
16920#define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos)
16921#define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk
16923/******************** Bit definition for DIR register ********************/
16924#define JPEG_DIR_DATAIN_Pos (0U)
16925#define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)
16926#define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk
16928/******************** Bit definition for DOR register ********************/
16929#define JPEG_DOR_DATAOUT_Pos (0U)
16930#define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos)
16931#define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk
16933/******************************************************************************/
16934/* */
16935/* LCD-TFT Display Controller (LTDC) */
16936/* */
16937/******************************************************************************/
16938
16939/******************** Bit definition for LTDC_SSCR register *****************/
16940
16941#define LTDC_SSCR_VSH_Pos (0U)
16942#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos)
16943#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk
16944#define LTDC_SSCR_HSW_Pos (16U)
16945#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos)
16946#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk
16948/******************** Bit definition for LTDC_BPCR register *****************/
16949
16950#define LTDC_BPCR_AVBP_Pos (0U)
16951#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos)
16952#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk
16953#define LTDC_BPCR_AHBP_Pos (16U)
16954#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos)
16955#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk
16957/******************** Bit definition for LTDC_AWCR register *****************/
16958
16959#define LTDC_AWCR_AAH_Pos (0U)
16960#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos)
16961#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk
16962#define LTDC_AWCR_AAW_Pos (16U)
16963#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos)
16964#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk
16966/******************** Bit definition for LTDC_TWCR register *****************/
16967
16968#define LTDC_TWCR_TOTALH_Pos (0U)
16969#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos)
16970#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk
16971#define LTDC_TWCR_TOTALW_Pos (16U)
16972#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos)
16973#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk
16975/******************** Bit definition for LTDC_GCR register ******************/
16976
16977#define LTDC_GCR_LTDCEN_Pos (0U)
16978#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos)
16979#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk
16980#define LTDC_GCR_DBW_Pos (4U)
16981#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos)
16982#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk
16983#define LTDC_GCR_DGW_Pos (8U)
16984#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos)
16985#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk
16986#define LTDC_GCR_DRW_Pos (12U)
16987#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos)
16988#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk
16989#define LTDC_GCR_DEN_Pos (16U)
16990#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos)
16991#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk
16992#define LTDC_GCR_PCPOL_Pos (28U)
16993#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos)
16994#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk
16995#define LTDC_GCR_DEPOL_Pos (29U)
16996#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos)
16997#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk
16998#define LTDC_GCR_VSPOL_Pos (30U)
16999#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos)
17000#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk
17001#define LTDC_GCR_HSPOL_Pos (31U)
17002#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos)
17003#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk
17006/******************** Bit definition for LTDC_SRCR register *****************/
17007
17008#define LTDC_SRCR_IMR_Pos (0U)
17009#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos)
17010#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk
17011#define LTDC_SRCR_VBR_Pos (1U)
17012#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos)
17013#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk
17015/******************** Bit definition for LTDC_BCCR register *****************/
17016
17017#define LTDC_BCCR_BCBLUE_Pos (0U)
17018#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos)
17019#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk
17020#define LTDC_BCCR_BCGREEN_Pos (8U)
17021#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos)
17022#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk
17023#define LTDC_BCCR_BCRED_Pos (16U)
17024#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos)
17025#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk
17027/******************** Bit definition for LTDC_IER register ******************/
17028
17029#define LTDC_IER_LIE_Pos (0U)
17030#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos)
17031#define LTDC_IER_LIE LTDC_IER_LIE_Msk
17032#define LTDC_IER_FUIE_Pos (1U)
17033#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos)
17034#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk
17035#define LTDC_IER_TERRIE_Pos (2U)
17036#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos)
17037#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk
17038#define LTDC_IER_RRIE_Pos (3U)
17039#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos)
17040#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk
17042/******************** Bit definition for LTDC_ISR register ******************/
17043
17044#define LTDC_ISR_LIF_Pos (0U)
17045#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos)
17046#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk
17047#define LTDC_ISR_FUIF_Pos (1U)
17048#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos)
17049#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk
17050#define LTDC_ISR_TERRIF_Pos (2U)
17051#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos)
17052#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk
17053#define LTDC_ISR_RRIF_Pos (3U)
17054#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos)
17055#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk
17057/******************** Bit definition for LTDC_ICR register ******************/
17058
17059#define LTDC_ICR_CLIF_Pos (0U)
17060#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos)
17061#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk
17062#define LTDC_ICR_CFUIF_Pos (1U)
17063#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos)
17064#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk
17065#define LTDC_ICR_CTERRIF_Pos (2U)
17066#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos)
17067#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk
17068#define LTDC_ICR_CRRIF_Pos (3U)
17069#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos)
17070#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk
17072/******************** Bit definition for LTDC_LIPCR register ****************/
17073
17074#define LTDC_LIPCR_LIPOS_Pos (0U)
17075#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)
17076#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk
17078/******************** Bit definition for LTDC_CPSR register *****************/
17079
17080#define LTDC_CPSR_CYPOS_Pos (0U)
17081#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)
17082#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk
17083#define LTDC_CPSR_CXPOS_Pos (16U)
17084#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)
17085#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk
17087/******************** Bit definition for LTDC_CDSR register *****************/
17088
17089#define LTDC_CDSR_VDES_Pos (0U)
17090#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos)
17091#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk
17092#define LTDC_CDSR_HDES_Pos (1U)
17093#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos)
17094#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk
17095#define LTDC_CDSR_VSYNCS_Pos (2U)
17096#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos)
17097#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk
17098#define LTDC_CDSR_HSYNCS_Pos (3U)
17099#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos)
17100#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk
17102/******************** Bit definition for LTDC_LxCR register *****************/
17103
17104#define LTDC_LxCR_LEN_Pos (0U)
17105#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos)
17106#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk
17107#define LTDC_LxCR_COLKEN_Pos (1U)
17108#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos)
17109#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk
17110#define LTDC_LxCR_CLUTEN_Pos (4U)
17111#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos)
17112#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk
17114/******************** Bit definition for LTDC_LxWHPCR register **************/
17115
17116#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
17117#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)
17118#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk
17119#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
17120#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)
17121#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk
17123/******************** Bit definition for LTDC_LxWVPCR register **************/
17124
17125#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
17126#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)
17127#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk
17128#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
17129#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)
17130#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk
17132/******************** Bit definition for LTDC_LxCKCR register ***************/
17133
17134#define LTDC_LxCKCR_CKBLUE_Pos (0U)
17135#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)
17136#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk
17137#define LTDC_LxCKCR_CKGREEN_Pos (8U)
17138#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)
17139#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk
17140#define LTDC_LxCKCR_CKRED_Pos (16U)
17141#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos)
17142#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk
17144/******************** Bit definition for LTDC_LxPFCR register ***************/
17145
17146#define LTDC_LxPFCR_PF_Pos (0U)
17147#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos)
17148#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk
17150/******************** Bit definition for LTDC_LxCACR register ***************/
17151
17152#define LTDC_LxCACR_CONSTA_Pos (0U)
17153#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos)
17154#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk
17156/******************** Bit definition for LTDC_LxDCCR register ***************/
17157
17158#define LTDC_LxDCCR_DCBLUE_Pos (0U)
17159#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)
17160#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk
17161#define LTDC_LxDCCR_DCGREEN_Pos (8U)
17162#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)
17163#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk
17164#define LTDC_LxDCCR_DCRED_Pos (16U)
17165#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos)
17166#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk
17167#define LTDC_LxDCCR_DCALPHA_Pos (24U)
17168#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)
17169#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk
17171/******************** Bit definition for LTDC_LxBFCR register ***************/
17172
17173#define LTDC_LxBFCR_BF2_Pos (0U)
17174#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos)
17175#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk
17176#define LTDC_LxBFCR_BF1_Pos (8U)
17177#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos)
17178#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk
17180/******************** Bit definition for LTDC_LxCFBAR register **************/
17181
17182#define LTDC_LxCFBAR_CFBADD_Pos (0U)
17183#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)
17184#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk
17186/******************** Bit definition for LTDC_LxCFBLR register **************/
17187
17188#define LTDC_LxCFBLR_CFBLL_Pos (0U)
17189#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)
17190#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk
17191#define LTDC_LxCFBLR_CFBP_Pos (16U)
17192#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)
17193#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk
17195/******************** Bit definition for LTDC_LxCFBLNR register *************/
17196
17197#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
17198#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
17199#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk
17201/******************** Bit definition for LTDC_LxCLUTWR register *************/
17202
17203#define LTDC_LxCLUTWR_BLUE_Pos (0U)
17204#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)
17205#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk
17206#define LTDC_LxCLUTWR_GREEN_Pos (8U)
17207#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)
17208#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk
17209#define LTDC_LxCLUTWR_RED_Pos (16U)
17210#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos)
17211#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk
17212#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
17213#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)
17214#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk
17216/******************************************************************************/
17217/* */
17218/* MDMA */
17219/* */
17220/******************************************************************************/
17221/******************** Bit definition for MDMA_GISR0 register ****************/
17222#define MDMA_GISR0_GIF0_Pos (0U)
17223#define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos)
17224#define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk
17225#define MDMA_GISR0_GIF1_Pos (1U)
17226#define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos)
17227#define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk
17228#define MDMA_GISR0_GIF2_Pos (2U)
17229#define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos)
17230#define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk
17231#define MDMA_GISR0_GIF3_Pos (3U)
17232#define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos)
17233#define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk
17234#define MDMA_GISR0_GIF4_Pos (4U)
17235#define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos)
17236#define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk
17237#define MDMA_GISR0_GIF5_Pos (5U)
17238#define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos)
17239#define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk
17240#define MDMA_GISR0_GIF6_Pos (6U)
17241#define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos)
17242#define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk
17243#define MDMA_GISR0_GIF7_Pos (7U)
17244#define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos)
17245#define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk
17246#define MDMA_GISR0_GIF8_Pos (8U)
17247#define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos)
17248#define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk
17249#define MDMA_GISR0_GIF9_Pos (9U)
17250#define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos)
17251#define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk
17252#define MDMA_GISR0_GIF10_Pos (10U)
17253#define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos)
17254#define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk
17255#define MDMA_GISR0_GIF11_Pos (11U)
17256#define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos)
17257#define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk
17258#define MDMA_GISR0_GIF12_Pos (12U)
17259#define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos)
17260#define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk
17261#define MDMA_GISR0_GIF13_Pos (13U)
17262#define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos)
17263#define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk
17264#define MDMA_GISR0_GIF14_Pos (14U)
17265#define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos)
17266#define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk
17267#define MDMA_GISR0_GIF15_Pos (15U)
17268#define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos)
17269#define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk
17271/******************** Bit definition for MDMA_CxISR register ****************/
17272#define MDMA_CISR_TEIF_Pos (0U)
17273#define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos)
17274#define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk
17275#define MDMA_CISR_CTCIF_Pos (1U)
17276#define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos)
17277#define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk
17278#define MDMA_CISR_BRTIF_Pos (2U)
17279#define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos)
17280#define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk
17281#define MDMA_CISR_BTIF_Pos (3U)
17282#define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos)
17283#define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk
17284#define MDMA_CISR_TCIF_Pos (4U)
17285#define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos)
17286#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk
17287#define MDMA_CISR_CRQA_Pos (16U)
17288#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos)
17289#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk
17291/******************** Bit definition for MDMA_CxIFCR register ****************/
17292#define MDMA_CIFCR_CTEIF_Pos (0U)
17293#define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos)
17294#define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk
17295#define MDMA_CIFCR_CCTCIF_Pos (1U)
17296#define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos)
17297#define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk
17298#define MDMA_CIFCR_CBRTIF_Pos (2U)
17299#define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos)
17300#define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk
17301#define MDMA_CIFCR_CBTIF_Pos (3U)
17302#define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos)
17303#define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk
17304#define MDMA_CIFCR_CLTCIF_Pos (4U)
17305#define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos)
17306#define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk
17308/******************** Bit definition for MDMA_CxESR register ****************/
17309#define MDMA_CESR_TEA_Pos (0U)
17310#define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos)
17311#define MDMA_CESR_TEA MDMA_CESR_TEA_Msk
17312#define MDMA_CESR_TED_Pos (7U)
17313#define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos)
17314#define MDMA_CESR_TED MDMA_CESR_TED_Msk
17315#define MDMA_CESR_TELD_Pos (8U)
17316#define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos)
17317#define MDMA_CESR_TELD MDMA_CESR_TELD_Msk
17318#define MDMA_CESR_TEMD_Pos (9U)
17319#define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos)
17320#define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk
17321#define MDMA_CESR_ASE_Pos (10U)
17322#define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos)
17323#define MDMA_CESR_ASE MDMA_CESR_ASE_Msk
17324#define MDMA_CESR_BSE_Pos (11U)
17325#define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos)
17326#define MDMA_CESR_BSE MDMA_CESR_BSE_Msk
17328/******************** Bit definition for MDMA_CxCR register ****************/
17329#define MDMA_CCR_EN_Pos (0U)
17330#define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos)
17331#define MDMA_CCR_EN MDMA_CCR_EN_Msk
17332#define MDMA_CCR_TEIE_Pos (1U)
17333#define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos)
17334#define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk
17335#define MDMA_CCR_CTCIE_Pos (2U)
17336#define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos)
17337#define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk
17338#define MDMA_CCR_BRTIE_Pos (3U)
17339#define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos)
17340#define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk
17341#define MDMA_CCR_BTIE_Pos (4U)
17342#define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos)
17343#define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk
17344#define MDMA_CCR_TCIE_Pos (5U)
17345#define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos)
17346#define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk
17347#define MDMA_CCR_PL_Pos (6U)
17348#define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos)
17349#define MDMA_CCR_PL MDMA_CCR_PL_Msk
17350#define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos)
17351#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos)
17352#define MDMA_CCR_BEX_Pos (12U)
17353#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos)
17354#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk
17355#define MDMA_CCR_HEX_Pos (13U)
17356#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos)
17357#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk
17358#define MDMA_CCR_WEX_Pos (14U)
17359#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos)
17360#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk
17361#define MDMA_CCR_SWRQ_Pos (16U)
17362#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos)
17363#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk
17365/******************** Bit definition for MDMA_CxTCR register ****************/
17366#define MDMA_CTCR_SINC_Pos (0U)
17367#define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos)
17368#define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk
17369#define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos)
17370#define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos)
17371#define MDMA_CTCR_DINC_Pos (2U)
17372#define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos)
17373#define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk
17374#define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos)
17375#define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos)
17376#define MDMA_CTCR_SSIZE_Pos (4U)
17377#define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos)
17378#define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk
17379#define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos)
17380#define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos)
17381#define MDMA_CTCR_DSIZE_Pos (6U)
17382#define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos)
17383#define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk
17384#define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos)
17385#define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos)
17386#define MDMA_CTCR_SINCOS_Pos (8U)
17387#define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos)
17388#define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk
17389#define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos)
17390#define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos)
17391#define MDMA_CTCR_DINCOS_Pos (10U)
17392#define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos)
17393#define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk
17394#define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos)
17395#define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos)
17396#define MDMA_CTCR_SBURST_Pos (12U)
17397#define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos)
17398#define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk
17399#define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos)
17400#define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos)
17401#define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos)
17402#define MDMA_CTCR_DBURST_Pos (15U)
17403#define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos)
17404#define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk
17405#define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos)
17406#define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos)
17407#define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos)
17408#define MDMA_CTCR_TLEN_Pos (18U)
17409#define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos)
17410#define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk
17411#define MDMA_CTCR_PKE_Pos (25U)
17412#define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos)
17413#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk
17414#define MDMA_CTCR_PAM_Pos (26U)
17415#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos)
17416#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk
17417#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos)
17418#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos)
17419#define MDMA_CTCR_TRGM_Pos (28U)
17420#define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos)
17421#define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk
17422#define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos)
17423#define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos)
17424#define MDMA_CTCR_SWRM_Pos (30U)
17425#define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos)
17426#define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk
17427#define MDMA_CTCR_BWM_Pos (31U)
17428#define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos)
17429#define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk
17431/******************** Bit definition for MDMA_CxBNDTR register ****************/
17432#define MDMA_CBNDTR_BNDT_Pos (0U)
17433#define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)
17434#define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk
17435#define MDMA_CBNDTR_BRSUM_Pos (18U)
17436#define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos)
17437#define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk
17438#define MDMA_CBNDTR_BRDUM_Pos (19U)
17439#define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos)
17440#define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk
17441#define MDMA_CBNDTR_BRC_Pos (20U)
17442#define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos)
17443#define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk
17445/******************** Bit definition for MDMA_CxSAR register ****************/
17446#define MDMA_CSAR_SAR_Pos (0U)
17447#define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)
17448#define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk
17450/******************** Bit definition for MDMA_CxDAR register ****************/
17451#define MDMA_CDAR_DAR_Pos (0U)
17452#define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)
17453#define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk
17455/******************** Bit definition for MDMA_CxBRUR ************************/
17456#define MDMA_CBRUR_SUV_Pos (0U)
17457#define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos)
17458#define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk
17459#define MDMA_CBRUR_DUV_Pos (16U)
17460#define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos)
17461#define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk
17463/******************** Bit definition for MDMA_CxLAR *************************/
17464#define MDMA_CLAR_LAR_Pos (0U)
17465#define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)
17466#define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk
17468/******************** Bit definition for MDMA_CxTBR) ************************/
17469#define MDMA_CTBR_TSEL_Pos (0U)
17470#define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos)
17471#define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk
17472#define MDMA_CTBR_SBUS_Pos (16U)
17473#define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos)
17474#define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk
17475#define MDMA_CTBR_DBUS_Pos (17U)
17476#define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos)
17477#define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk
17479/******************** Bit definition for MDMA_CxMAR) ************************/
17480#define MDMA_CMAR_MAR_Pos (0U)
17481#define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)
17482#define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk
17484/******************** Bit definition for MDMA_CxMDR) ************************/
17485#define MDMA_CMDR_MDR_Pos (0U)
17486#define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)
17487#define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk
17489/******************************************************************************/
17490/* */
17491/* Operational Amplifier (OPAMP) */
17492/* */
17493/******************************************************************************/
17494/********************* Bit definition for OPAMPx_CSR register ***************/
17495#define OPAMP_CSR_OPAMPxEN_Pos (0U)
17496#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
17497#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk
17498#define OPAMP_CSR_FORCEVP_Pos (1U)
17499#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)
17500#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk
17502#define OPAMP_CSR_VPSEL_Pos (2U)
17503#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)
17504#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk
17505#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)
17506#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)
17508#define OPAMP_CSR_VMSEL_Pos (5U)
17509#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)
17510#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk
17511#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)
17512#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)
17514#define OPAMP_CSR_OPAHSM_Pos (8U)
17515#define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos)
17516#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk
17517#define OPAMP_CSR_CALON_Pos (11U)
17518#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)
17519#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk
17521#define OPAMP_CSR_CALSEL_Pos (12U)
17522#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)
17523#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk
17524#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)
17525#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)
17527#define OPAMP_CSR_PGGAIN_Pos (14U)
17528#define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos)
17529#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk
17530#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)
17531#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)
17532#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)
17533#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)
17535#define OPAMP_CSR_USERTRIM_Pos (18U)
17536#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)
17537#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk
17538#define OPAMP_CSR_TSTREF_Pos (29U)
17539#define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos)
17540#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk
17541#define OPAMP_CSR_CALOUT_Pos (30U)
17542#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos)
17543#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk
17545/********************* Bit definition for OPAMP1_CSR register ***************/
17546#define OPAMP1_CSR_OPAEN_Pos (0U)
17547#define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos)
17548#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk
17549#define OPAMP1_CSR_FORCEVP_Pos (1U)
17550#define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos)
17551#define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk
17553#define OPAMP1_CSR_VPSEL_Pos (2U)
17554#define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos)
17555#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk
17556#define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos)
17557#define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos)
17559#define OPAMP1_CSR_VMSEL_Pos (5U)
17560#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)
17561#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk
17562#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)
17563#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)
17565#define OPAMP1_CSR_OPAHSM_Pos (8U)
17566#define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos)
17567#define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk
17568#define OPAMP1_CSR_CALON_Pos (11U)
17569#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)
17570#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk
17572#define OPAMP1_CSR_CALSEL_Pos (12U)
17573#define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos)
17574#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk
17575#define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos)
17576#define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos)
17578#define OPAMP1_CSR_PGGAIN_Pos (14U)
17579#define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos)
17580#define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk
17581#define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos)
17582#define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos)
17583#define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos)
17584#define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos)
17586#define OPAMP1_CSR_USERTRIM_Pos (18U)
17587#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)
17588#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk
17589#define OPAMP1_CSR_TSTREF_Pos (29U)
17590#define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos)
17591#define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk
17592#define OPAMP1_CSR_CALOUT_Pos (30U)
17593#define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos)
17594#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk
17596/********************* Bit definition for OPAMP2_CSR register ***************/
17597#define OPAMP2_CSR_OPAEN_Pos (0U)
17598#define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos)
17599#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk
17600#define OPAMP2_CSR_FORCEVP_Pos (1U)
17601#define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos)
17602#define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk
17604#define OPAMP2_CSR_VPSEL_Pos (2U)
17605#define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos)
17606#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk
17607#define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos)
17608#define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos)
17610#define OPAMP2_CSR_VMSEL_Pos (5U)
17611#define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)
17612#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk
17613#define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)
17614#define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)
17616#define OPAMP2_CSR_OPAHSM_Pos (8U)
17617#define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos)
17618#define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk
17619#define OPAMP2_CSR_CALON_Pos (11U)
17620#define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)
17621#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk
17623#define OPAMP2_CSR_CALSEL_Pos (12U)
17624#define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos)
17625#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk
17626#define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos)
17627#define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos)
17629#define OPAMP2_CSR_PGGAIN_Pos (14U)
17630#define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos)
17631#define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk
17632#define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos)
17633#define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos)
17634#define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos)
17635#define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos)
17637#define OPAMP2_CSR_USERTRIM_Pos (18U)
17638#define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)
17639#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk
17640#define OPAMP2_CSR_TSTREF_Pos (29U)
17641#define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos)
17642#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk
17643#define OPAMP2_CSR_CALOUT_Pos (30U)
17644#define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos)
17645#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk
17647/******************* Bit definition for OPAMP_OTR register ******************/
17648#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
17649#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)
17650#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk
17651#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
17652#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)
17653#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk
17655/******************* Bit definition for OPAMP1_OTR register ******************/
17656#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
17657#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos)
17658#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk
17659#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
17660#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos)
17661#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk
17663/******************* Bit definition for OPAMP2_OTR register ******************/
17664#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
17665#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos)
17666#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk
17667#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
17668#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos)
17669#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk
17671/******************* Bit definition for OPAMP_HSOTR register ****************/
17672#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
17673#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos)
17674#define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk
17675#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
17676#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos)
17677#define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk
17679/******************* Bit definition for OPAMP1_HSOTR register ****************/
17680#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
17681#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos)
17682#define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk
17683#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
17684#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos)
17685#define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk
17687/******************* Bit definition for OPAMP2_HSOTR register ****************/
17688#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
17689#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos)
17690#define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk
17691#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
17692#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos)
17693#define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk
17695/******************************************************************************/
17696/* */
17697/* Power Control */
17698/* */
17699/******************************************************************************/
17700/************************* NUMBER OF POWER DOMAINS **************************/
17701#define POWER_DOMAINS_NUMBER 3U
17703/******************** Bit definition for PWR_CR1 register *******************/
17704#define PWR_CR1_ALS_Pos (17U)
17705#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos)
17706#define PWR_CR1_ALS PWR_CR1_ALS_Msk
17707#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos)
17708#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos)
17709#define PWR_CR1_AVDEN_Pos (16U)
17710#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos)
17711#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk
17712#define PWR_CR1_SVOS_Pos (14U)
17713#define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos)
17714#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk
17715#define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos)
17716#define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos)
17717#define PWR_CR1_FLPS_Pos (9U)
17718#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos)
17719#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk
17720#define PWR_CR1_DBP_Pos (8U)
17721#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
17722#define PWR_CR1_DBP PWR_CR1_DBP_Msk
17723#define PWR_CR1_PLS_Pos (5U)
17724#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos)
17725#define PWR_CR1_PLS PWR_CR1_PLS_Msk
17726#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos)
17727#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos)
17728#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos)
17729#define PWR_CR1_PVDEN_Pos (4U)
17730#define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos)
17731#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk
17732#define PWR_CR1_LPDS_Pos (0U)
17733#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos)
17734#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk
17737#define PWR_CR1_PLS_LEV0 (0UL)
17738#define PWR_CR1_PLS_LEV1_Pos (5U)
17739#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos)
17740#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk
17741#define PWR_CR1_PLS_LEV2_Pos (6U)
17742#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos)
17743#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk
17744#define PWR_CR1_PLS_LEV3_Pos (5U)
17745#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos)
17746#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk
17747#define PWR_CR1_PLS_LEV4_Pos (7U)
17748#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos)
17749#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk
17750#define PWR_CR1_PLS_LEV5_Pos (5U)
17751#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos)
17752#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk
17753#define PWR_CR1_PLS_LEV6_Pos (6U)
17754#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos)
17755#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk
17756#define PWR_CR1_PLS_LEV7_Pos (5U)
17757#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos)
17758#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk
17761#define PWR_CR1_ALS_LEV0 (0UL)
17762#define PWR_CR1_ALS_LEV1_Pos (17U)
17763#define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos)
17764#define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk
17765#define PWR_CR1_ALS_LEV2_Pos (18U)
17766#define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos)
17767#define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk
17768#define PWR_CR1_ALS_LEV3_Pos (17U)
17769#define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos)
17770#define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk
17772/******************** Bit definition for PWR_CSR1 register ******************/
17773#define PWR_CSR1_AVDO_Pos (16U)
17774#define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos)
17775#define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk
17776#define PWR_CSR1_ACTVOS_Pos (14U)
17777#define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos)
17778#define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk
17779#define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos)
17780#define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos)
17781#define PWR_CSR1_ACTVOSRDY_Pos (13U)
17782#define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)
17783#define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk
17784#define PWR_CSR1_PVDO_Pos (4U)
17785#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos)
17786#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk
17788/******************** Bit definition for PWR_CR2 register *******************/
17789#define PWR_CR2_TEMPH_Pos (23U)
17790#define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos)
17791#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk
17792#define PWR_CR2_TEMPL_Pos (22U)
17793#define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos)
17794#define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk
17795#define PWR_CR2_VBATH_Pos (21U)
17796#define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos)
17797#define PWR_CR2_VBATH PWR_CR2_VBATH_Msk
17798#define PWR_CR2_VBATL_Pos (20U)
17799#define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos)
17800#define PWR_CR2_VBATL PWR_CR2_VBATL_Msk
17801#define PWR_CR2_BRRDY_Pos (16U)
17802#define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos)
17803#define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk
17804#define PWR_CR2_MONEN_Pos (4U)
17805#define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos)
17806#define PWR_CR2_MONEN PWR_CR2_MONEN_Msk
17807#define PWR_CR2_BREN_Pos (0U)
17808#define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos)
17809#define PWR_CR2_BREN PWR_CR2_BREN_Msk
17811/******************** Bit definition for PWR_CR3 register *******************/
17812#define PWR_CR3_USB33RDY_Pos (26U)
17813#define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos)
17814#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk
17815#define PWR_CR3_USBREGEN_Pos (25U)
17816#define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos)
17817#define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk
17818#define PWR_CR3_USB33DEN_Pos (24U)
17819#define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos)
17820#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk
17821#define PWR_CR3_SMPSEXTRDY_Pos (16U)
17822#define PWR_CR3_SMPSEXTRDY_Msk (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)
17823#define PWR_CR3_SMPSEXTRDY PWR_CR3_SMPSEXTRDY_Msk
17824#define PWR_CR3_VBRS_Pos (9U)
17825#define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos)
17826#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk
17827#define PWR_CR3_VBE_Pos (8U)
17828#define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos)
17829#define PWR_CR3_VBE PWR_CR3_VBE_Msk
17830#define PWR_CR3_SMPSLEVEL_Pos (4U)
17831#define PWR_CR3_SMPSLEVEL_Msk (0x3UL << PWR_CR3_SMPSLEVEL_Pos)
17832#define PWR_CR3_SMPSLEVEL PWR_CR3_SMPSLEVEL_Msk
17833#define PWR_CR3_SMPSLEVEL_0 (0x1UL << PWR_CR3_SMPSLEVEL_Pos)
17834#define PWR_CR3_SMPSLEVEL_1 (0x2UL << PWR_CR3_SMPSLEVEL_Pos)
17835#define PWR_CR3_SMPSEXTHP_Pos (3U)
17836#define PWR_CR3_SMPSEXTHP_Msk (0x1UL << PWR_CR3_SMPSEXTHP_Pos)
17837#define PWR_CR3_SMPSEXTHP PWR_CR3_SMPSEXTHP_Msk
17838#define PWR_CR3_SMPSEN_Pos (2U)
17839#define PWR_CR3_SMPSEN_Msk (0x1UL << PWR_CR3_SMPSEN_Pos)
17840#define PWR_CR3_SMPSEN PWR_CR3_SMPSEN_Msk
17841#define PWR_CR3_LDOEN_Pos (1U)
17842#define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos)
17843#define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk
17844#define PWR_CR3_BYPASS_Pos (0U)
17845#define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos)
17846#define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk
17848/******************** Bit definition for PWR_CPUCR register *****************/
17849#define PWR_CPUCR_RUN_D3_Pos (11U)
17850#define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos)
17851#define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk
17852#define PWR_CPUCR_HOLD2_Pos (10U)
17853#define PWR_CPUCR_HOLD2_Msk (0x1UL << PWR_CPUCR_HOLD2_Pos)
17854#define PWR_CPUCR_HOLD2 PWR_CPUCR_HOLD2_Msk
17855#define PWR_CPUCR_CSSF_Pos (9U)
17856#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos)
17857#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk
17858#define PWR_CPUCR_SBF_D2_Pos (8U)
17859#define PWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos)
17860#define PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk
17861#define PWR_CPUCR_SBF_D1_Pos (7U)
17862#define PWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos)
17863#define PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk
17864#define PWR_CPUCR_SBF_Pos (6U)
17865#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos)
17866#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk
17867#define PWR_CPUCR_STOPF_Pos (5U)
17868#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos)
17869#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk
17870#define PWR_CPUCR_HOLD2F_Pos (4U)
17871#define PWR_CPUCR_HOLD2F_Msk (0x1UL << PWR_CPUCR_HOLD2F_Pos)
17872#define PWR_CPUCR_HOLD2F PWR_CPUCR_HOLD2F_Msk
17873#define PWR_CPUCR_PDDS_D3_Pos (2U)
17874#define PWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos)
17875#define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk
17876#define PWR_CPUCR_PDDS_D2_Pos (1U)
17877#define PWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos)
17878#define PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk
17879#define PWR_CPUCR_PDDS_D1_Pos (0U)
17880#define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos)
17881#define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk
17883/******************** Bit definition for PWR_CPU2CR register ****************/
17884#define PWR_CPU2CR_RUN_D3_Pos (11U)
17885#define PWR_CPU2CR_RUN_D3_Msk (0x1UL << PWR_CPU2CR_RUN_D3_Pos)
17886#define PWR_CPU2CR_RUN_D3 PWR_CPU2CR_RUN_D3_Msk
17887#define PWR_CPU2CR_HOLD1_Pos (10U)
17888#define PWR_CPU2CR_HOLD1_Msk (0x1UL << PWR_CPU2CR_HOLD1_Pos)
17889#define PWR_CPU2CR_HOLD1 PWR_CPU2CR_HOLD1_Msk
17890#define PWR_CPU2CR_CSSF_Pos (9U)
17891#define PWR_CPU2CR_CSSF_Msk (0x1UL << PWR_CPU2CR_CSSF_Pos)
17892#define PWR_CPU2CR_CSSF PWR_CPU2CR_CSSF_Msk
17893#define PWR_CPU2CR_SBF_D2_Pos (8U)
17894#define PWR_CPU2CR_SBF_D2_Msk (0x1UL << PWR_CPU2CR_SBF_D2_Pos)
17895#define PWR_CPU2CR_SBF_D2 PWR_CPU2CR_SBF_D2_Msk
17896#define PWR_CPU2CR_SBF_D1_Pos (7U)
17897#define PWR_CPU2CR_SBF_D1_Msk (0x1UL << PWR_CPU2CR_SBF_D1_Pos)
17898#define PWR_CPU2CR_SBF_D1 PWR_CPU2CR_SBF_D1_Msk
17899#define PWR_CPU2CR_SBF_Pos (6U)
17900#define PWR_CPU2CR_SBF_Msk (0x1UL << PWR_CPU2CR_SBF_Pos)
17901#define PWR_CPU2CR_SBF PWR_CPU2CR_SBF_Msk
17902#define PWR_CPU2CR_STOPF_Pos (5U)
17903#define PWR_CPU2CR_STOPF_Msk (0x1UL << PWR_CPU2CR_STOPF_Pos)
17904#define PWR_CPU2CR_STOPF PWR_CPU2CR_STOPF_Msk
17905#define PWR_CPU2CR_HOLD1F_Pos (4U)
17906#define PWR_CPU2CR_HOLD1F_Msk (0x1UL << PWR_CPU2CR_HOLD1F_Pos)
17907#define PWR_CPU2CR_HOLD1F PWR_CPU2CR_HOLD1F_Msk
17908#define PWR_CPU2CR_PDDS_D3_Pos (2U)
17909#define PWR_CPU2CR_PDDS_D3_Msk (0x1UL << PWR_CPU2CR_PDDS_D3_Pos)
17910#define PWR_CPU2CR_PDDS_D3 PWR_CPU2CR_PDDS_D3_Msk
17911#define PWR_CPU2CR_PDDS_D2_Pos (1U)
17912#define PWR_CPU2CR_PDDS_D2_Msk (0x1UL << PWR_CPU2CR_PDDS_D2_Pos)
17913#define PWR_CPU2CR_PDDS_D2 PWR_CPU2CR_PDDS_D2_Msk
17914#define PWR_CPU2CR_PDDS_D1_Pos (0U)
17915#define PWR_CPU2CR_PDDS_D1_Msk (0x1UL << PWR_CPU2CR_PDDS_D1_Pos)
17916#define PWR_CPU2CR_PDDS_D1 PWR_CPU2CR_PDDS_D1_Msk
17919/******************** Bit definition for PWR_D3CR register ******************/
17920#define PWR_D3CR_VOS_Pos (14U)
17921#define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos)
17922#define PWR_D3CR_VOS PWR_D3CR_VOS_Msk
17923#define PWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos)
17924#define PWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos)
17925#define PWR_D3CR_VOSRDY_Pos (13U)
17926#define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos)
17927#define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk
17929/****************** Bit definition for PWR_WKUPCR register ******************/
17930#define PWR_WKUPCR_WKUPC6_Pos (5U)
17931#define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos)
17932#define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk
17933#define PWR_WKUPCR_WKUPC5_Pos (4U)
17934#define PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos)
17935#define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk
17936#define PWR_WKUPCR_WKUPC4_Pos (3U)
17937#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos)
17938#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk
17939#define PWR_WKUPCR_WKUPC3_Pos (2U)
17940#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos)
17941#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk
17942#define PWR_WKUPCR_WKUPC2_Pos (1U)
17943#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos)
17944#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk
17945#define PWR_WKUPCR_WKUPC1_Pos (0U)
17946#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos)
17947#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk
17949/******************** Bit definition for PWR_WKUPFR register ****************/
17950#define PWR_WKUPFR_WKUPF6_Pos (5U)
17951#define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos)
17952#define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk
17953#define PWR_WKUPFR_WKUPF5_Pos (4U)
17954#define PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos)
17955#define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk
17956#define PWR_WKUPFR_WKUPF4_Pos (3U)
17957#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos)
17958#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk
17959#define PWR_WKUPFR_WKUPF3_Pos (2U)
17960#define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos)
17961#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk
17962#define PWR_WKUPFR_WKUPF2_Pos (1U)
17963#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos)
17964#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk
17965#define PWR_WKUPFR_WKUPF1_Pos (0U)
17966#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos)
17967#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk
17969/****************** Bit definition for PWR_WKUPEPR register *****************/
17970#define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
17971#define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
17972#define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk
17973#define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
17974#define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
17975#define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)
17976#define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)
17977#define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk
17978#define PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)
17979#define PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)
17980#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
17981#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
17982#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk
17983#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
17984#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
17985#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
17986#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)
17987#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk
17988#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)
17989#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)
17990#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
17991#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
17992#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk
17993#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
17994#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
17995#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
17996#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
17997#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk
17998#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
17999#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
18000#define PWR_WKUPEPR_WKUPP6_Pos (13U)
18001#define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)
18002#define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk
18003#define PWR_WKUPEPR_WKUPP5_Pos (12U)
18004#define PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)
18005#define PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk
18006#define PWR_WKUPEPR_WKUPP4_Pos (11U)
18007#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)
18008#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk
18009#define PWR_WKUPEPR_WKUPP3_Pos (10U)
18010#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)
18011#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk
18012#define PWR_WKUPEPR_WKUPP2_Pos (9U)
18013#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)
18014#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk
18015#define PWR_WKUPEPR_WKUPP1_Pos (8U)
18016#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)
18017#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk
18018#define PWR_WKUPEPR_WKUPEN6_Pos (5U)
18019#define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)
18020#define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk
18021#define PWR_WKUPEPR_WKUPEN5_Pos (4U)
18022#define PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)
18023#define PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk
18024#define PWR_WKUPEPR_WKUPEN4_Pos (3U)
18025#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)
18026#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk
18027#define PWR_WKUPEPR_WKUPEN3_Pos (2U)
18028#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)
18029#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk
18030#define PWR_WKUPEPR_WKUPEN2_Pos (1U)
18031#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)
18032#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk
18033#define PWR_WKUPEPR_WKUPEN1_Pos (0U)
18034#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)
18035#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk
18036#define PWR_WKUPEPR_WKUPEN_Pos (0U)
18037#define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)
18038#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk
18040/******************************************************************************/
18041/* */
18042/* Reset and Clock Control */
18043/* */
18044/******************************************************************************/
18045/******************************* RCC VERSION ********************************/
18046#define RCC_VER_X
18047
18048/******************** Bit definition for RCC_CR register ********************/
18049#define RCC_CR_HSION_Pos (0U)
18050#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
18051#define RCC_CR_HSION RCC_CR_HSION_Msk
18052#define RCC_CR_HSIKERON_Pos (1U)
18053#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)
18054#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk
18055#define RCC_CR_HSIRDY_Pos (2U)
18056#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
18057#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
18058#define RCC_CR_HSIDIV_Pos (3U)
18059#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos)
18060#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk
18061#define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos)
18062#define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos)
18063#define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos)
18064#define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos)
18066#define RCC_CR_HSIDIVF_Pos (5U)
18067#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos)
18068#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk
18069#define RCC_CR_CSION_Pos (7U)
18070#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos)
18071#define RCC_CR_CSION RCC_CR_CSION_Msk
18072#define RCC_CR_CSIRDY_Pos (8U)
18073#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos)
18074#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk
18075#define RCC_CR_CSIKERON_Pos (9U)
18076#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos)
18077#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk
18078#define RCC_CR_HSI48ON_Pos (12U)
18079#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos)
18080#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk
18081#define RCC_CR_HSI48RDY_Pos (13U)
18082#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos)
18083#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk
18085#define RCC_CR_D1CKRDY_Pos (14U)
18086#define RCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos)
18087#define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk
18088#define RCC_CR_D2CKRDY_Pos (15U)
18089#define RCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos)
18090#define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk
18092#define RCC_CR_HSEON_Pos (16U)
18093#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
18094#define RCC_CR_HSEON RCC_CR_HSEON_Msk
18095#define RCC_CR_HSERDY_Pos (17U)
18096#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
18097#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
18098#define RCC_CR_HSEBYP_Pos (18U)
18099#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
18100#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
18101#define RCC_CR_CSSHSEON_Pos (19U)
18102#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos)
18103#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk
18106#define RCC_CR_PLL1ON_Pos (24U)
18107#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos)
18108#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk
18109#define RCC_CR_PLL1RDY_Pos (25U)
18110#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos)
18111#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk
18112#define RCC_CR_PLL2ON_Pos (26U)
18113#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos)
18114#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk
18115#define RCC_CR_PLL2RDY_Pos (27U)
18116#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos)
18117#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk
18118#define RCC_CR_PLL3ON_Pos (28U)
18119#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos)
18120#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk
18121#define RCC_CR_PLL3RDY_Pos (29U)
18122#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos)
18123#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk
18125/*Legacy */
18126#define RCC_CR_PLLON_Pos (24U)
18127#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
18128#define RCC_CR_PLLON RCC_CR_PLLON_Msk
18129#define RCC_CR_PLLRDY_Pos (25U)
18130#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
18131#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
18133/******************** Bit definition for RCC_HSICFGR register ***************/
18135#define RCC_HSICFGR_HSICAL_Pos (0U)
18136#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos)
18137#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk
18138#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos)
18139#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos)
18140#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos)
18141#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos)
18142#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos)
18143#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos)
18144#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos)
18145#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos)
18146#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos)
18147#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos)
18148#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos)
18149#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos)
18152#define RCC_HSICFGR_HSITRIM_Pos (24U)
18153#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)
18154#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk
18155#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos)
18156#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos)
18157#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos)
18158#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos)
18159#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos)
18160#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos)
18161#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos)
18164/******************** Bit definition for RCC_CRRCR register *****************/
18165
18167#define RCC_CRRCR_HSI48CAL_Pos (0U)
18168#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos)
18169#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk
18170#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)
18171#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)
18172#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)
18173#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)
18174#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)
18175#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)
18176#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)
18177#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)
18178#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)
18179#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos)
18182/******************** Bit definition for RCC_CSICFGR register *****************/
18184#define RCC_CSICFGR_CSICAL_Pos (0U)
18185#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos)
18186#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk
18187#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos)
18188#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos)
18189#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos)
18190#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos)
18191#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos)
18192#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos)
18193#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos)
18194#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos)
18197#define RCC_CSICFGR_CSITRIM_Pos (24U)
18198#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos)
18199#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk
18200#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos)
18201#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos)
18202#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos)
18203#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos)
18204#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos)
18205#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos)
18207/******************** Bit definition for RCC_CFGR register ******************/
18209#define RCC_CFGR_SW_Pos (0U)
18210#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos)
18211#define RCC_CFGR_SW RCC_CFGR_SW_Msk
18212#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
18213#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
18214#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos)
18216#define RCC_CFGR_SW_HSI (0x00000000UL)
18217#define RCC_CFGR_SW_CSI (0x00000001UL)
18218#define RCC_CFGR_SW_HSE (0x00000002UL)
18219#define RCC_CFGR_SW_PLL1 (0x00000003UL)
18222#define RCC_CFGR_SWS_Pos (3U)
18223#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos)
18224#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
18225#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
18226#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
18227#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos)
18229#define RCC_CFGR_SWS_HSI (0x00000000UL)
18230#define RCC_CFGR_SWS_CSI (0x00000008UL)
18231#define RCC_CFGR_SWS_HSE (0x00000010UL)
18232#define RCC_CFGR_SWS_PLL1 (0x00000018UL)
18234#define RCC_CFGR_STOPWUCK_Pos (6U)
18235#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)
18236#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk
18238#define RCC_CFGR_STOPKERWUCK_Pos (7U)
18239#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)
18240#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk
18243#define RCC_CFGR_RTCPRE_Pos (8U)
18244#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
18245#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
18246#define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos)
18247#define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos)
18248#define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos)
18249#define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos)
18250#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
18251#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos)
18254#define RCC_CFGR_HRTIMSEL_Pos (14U)
18255#define RCC_CFGR_HRTIMSEL_Msk (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
18256#define RCC_CFGR_HRTIMSEL RCC_CFGR_HRTIMSEL_Msk
18259#define RCC_CFGR_TIMPRE_Pos (15U)
18260#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
18261#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk
18264#define RCC_CFGR_MCO1_Pos (22U)
18265#define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
18266#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
18267#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
18268#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
18269#define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos)
18271#define RCC_CFGR_MCO1PRE_Pos (18U)
18272#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
18273#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
18274#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
18275#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
18276#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
18277#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos)
18279#define RCC_CFGR_MCO2PRE_Pos (25U)
18280#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
18281#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
18282#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
18283#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
18284#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
18285#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos)
18287#define RCC_CFGR_MCO2_Pos (29U)
18288#define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
18289#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
18290#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
18291#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
18292#define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos)
18294/******************** Bit definition for RCC_D1CFGR register ******************/
18296#define RCC_D1CFGR_HPRE_Pos (0U)
18297#define RCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos)
18298#define RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk
18299#define RCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos)
18300#define RCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos)
18301#define RCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos)
18302#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos)
18305#define RCC_D1CFGR_HPRE_DIV1 (0U)
18306#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
18307#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos)
18308#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk
18309#define RCC_D1CFGR_HPRE_DIV4_Pos (0U)
18310#define RCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos)
18311#define RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk
18312#define RCC_D1CFGR_HPRE_DIV8_Pos (1U)
18313#define RCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos)
18314#define RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk
18315#define RCC_D1CFGR_HPRE_DIV16_Pos (0U)
18316#define RCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos)
18317#define RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk
18318#define RCC_D1CFGR_HPRE_DIV64_Pos (2U)
18319#define RCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos)
18320#define RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk
18321#define RCC_D1CFGR_HPRE_DIV128_Pos (0U)
18322#define RCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos)
18323#define RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk
18324#define RCC_D1CFGR_HPRE_DIV256_Pos (1U)
18325#define RCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos)
18326#define RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk
18327#define RCC_D1CFGR_HPRE_DIV512_Pos (0U)
18328#define RCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos)
18329#define RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk
18332#define RCC_D1CFGR_D1PPRE_Pos (4U)
18333#define RCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos)
18334#define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk
18335#define RCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos)
18336#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos)
18337#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos)
18339#define RCC_D1CFGR_D1PPRE_DIV1 (0U)
18340#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
18341#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos)
18342#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk
18343#define RCC_D1CFGR_D1PPRE_DIV4_Pos (4U)
18344#define RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos)
18345#define RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk
18346#define RCC_D1CFGR_D1PPRE_DIV8_Pos (5U)
18347#define RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos)
18348#define RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk
18349#define RCC_D1CFGR_D1PPRE_DIV16_Pos (4U)
18350#define RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos)
18351#define RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk
18353#define RCC_D1CFGR_D1CPRE_Pos (8U)
18354#define RCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos)
18355#define RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk
18356#define RCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos)
18357#define RCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos)
18358#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos)
18359#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos)
18361#define RCC_D1CFGR_D1CPRE_DIV1 (0U)
18362#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
18363#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos)
18364#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk
18365#define RCC_D1CFGR_D1CPRE_DIV4_Pos (8U)
18366#define RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos)
18367#define RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk
18368#define RCC_D1CFGR_D1CPRE_DIV8_Pos (9U)
18369#define RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos)
18370#define RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk
18371#define RCC_D1CFGR_D1CPRE_DIV16_Pos (8U)
18372#define RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos)
18373#define RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk
18374#define RCC_D1CFGR_D1CPRE_DIV64_Pos (10U)
18375#define RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos)
18376#define RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk
18377#define RCC_D1CFGR_D1CPRE_DIV128_Pos (8U)
18378#define RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos)
18379#define RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk
18380#define RCC_D1CFGR_D1CPRE_DIV256_Pos (9U)
18381#define RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos)
18382#define RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk
18383#define RCC_D1CFGR_D1CPRE_DIV512_Pos (8U)
18384#define RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos)
18385#define RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk
18387/******************** Bit definition for RCC_D2CFGR register ******************/
18389#define RCC_D2CFGR_D2PPRE1_Pos (4U)
18390#define RCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos)
18391#define RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk
18392#define RCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos)
18393#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos)
18394#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos)
18396#define RCC_D2CFGR_D2PPRE1_DIV1 (0U)
18397#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
18398#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos)
18399#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk
18400#define RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U)
18401#define RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos)
18402#define RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk
18403#define RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U)
18404#define RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos)
18405#define RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk
18406#define RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U)
18407#define RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos)
18408#define RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk
18411#define RCC_D2CFGR_D2PPRE2_Pos (8U)
18412#define RCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos)
18413#define RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk
18414#define RCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos)
18415#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos)
18416#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos)
18418#define RCC_D2CFGR_D2PPRE2_DIV1 (0U)
18419#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
18420#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos)
18421#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk
18422#define RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U)
18423#define RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos)
18424#define RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk
18425#define RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U)
18426#define RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos)
18427#define RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk
18428#define RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U)
18429#define RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos)
18430#define RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk
18432/******************** Bit definition for RCC_D3CFGR register ******************/
18434#define RCC_D3CFGR_D3PPRE_Pos (4U)
18435#define RCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos)
18436#define RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk
18437#define RCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos)
18438#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos)
18439#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos)
18441#define RCC_D3CFGR_D3PPRE_DIV1 (0U)
18442#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
18443#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos)
18444#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk
18445#define RCC_D3CFGR_D3PPRE_DIV4_Pos (4U)
18446#define RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos)
18447#define RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk
18448#define RCC_D3CFGR_D3PPRE_DIV8_Pos (5U)
18449#define RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos)
18450#define RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk
18451#define RCC_D3CFGR_D3PPRE_DIV16_Pos (4U)
18452#define RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos)
18453#define RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk
18455/******************** Bit definition for RCC_PLLCKSELR register *************/
18456
18457#define RCC_PLLCKSELR_PLLSRC_Pos (0U)
18458#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos)
18459#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
18460
18461#define RCC_PLLCKSELR_PLLSRC_HSI (0U)
18462#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
18463#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos)
18464#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk
18465#define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
18466#define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos)
18467#define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk
18468#define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
18469#define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos)
18470#define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk
18472#define RCC_PLLCKSELR_DIVM1_Pos (4U)
18473#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos)
18474#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
18475#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos)
18476#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos)
18477#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos)
18478#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos)
18479#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos)
18480#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos)
18482#define RCC_PLLCKSELR_DIVM2_Pos (12U)
18483#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos)
18484#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
18485#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos)
18486#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos)
18487#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos)
18488#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos)
18489#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos)
18490#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos)
18492#define RCC_PLLCKSELR_DIVM3_Pos (20U)
18493#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos)
18494#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
18495#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos)
18496#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos)
18497#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos)
18498#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos)
18499#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos)
18500#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos)
18502/******************** Bit definition for RCC_PLLCFGR register ***************/
18503
18504#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
18505#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos)
18506#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
18507#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
18508#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos)
18509#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
18510#define RCC_PLLCFGR_PLL1RGE_Pos (2U)
18511#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
18512#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
18513#define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos)
18514#define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos)
18515#define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos)
18516#define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
18518#define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
18519#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos)
18520#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
18521#define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
18522#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos)
18523#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
18524#define RCC_PLLCFGR_PLL2RGE_Pos (6U)
18525#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
18526#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
18527#define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos)
18528#define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos)
18529#define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos)
18530#define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
18532#define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
18533#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos)
18534#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
18535#define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
18536#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos)
18537#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
18538#define RCC_PLLCFGR_PLL3RGE_Pos (10U)
18539#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
18540#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
18541#define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos)
18542#define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos)
18543#define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos)
18544#define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
18546#define RCC_PLLCFGR_DIVP1EN_Pos (16U)
18547#define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos)
18548#define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
18549#define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
18550#define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos)
18551#define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
18552#define RCC_PLLCFGR_DIVR1EN_Pos (18U)
18553#define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos)
18554#define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
18555
18556#define RCC_PLLCFGR_DIVP2EN_Pos (19U)
18557#define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos)
18558#define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
18559#define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
18560#define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos)
18561#define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
18562#define RCC_PLLCFGR_DIVR2EN_Pos (21U)
18563#define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos)
18564#define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
18565
18566#define RCC_PLLCFGR_DIVP3EN_Pos (22U)
18567#define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos)
18568#define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
18569#define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
18570#define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos)
18571#define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
18572#define RCC_PLLCFGR_DIVR3EN_Pos (24U)
18573#define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos)
18574#define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
18575
18576
18577/******************** Bit definition for RCC_PLL1DIVR register ***************/
18578#define RCC_PLL1DIVR_N1_Pos (0U)
18579#define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos)
18580#define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
18581#define RCC_PLL1DIVR_P1_Pos (9U)
18582#define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos)
18583#define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
18584#define RCC_PLL1DIVR_Q1_Pos (16U)
18585#define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos)
18586#define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
18587#define RCC_PLL1DIVR_R1_Pos (24U)
18588#define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos)
18589#define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
18590
18591/******************** Bit definition for RCC_PLL1FRACR register ***************/
18592#define RCC_PLL1FRACR_FRACN1_Pos (3U)
18593#define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos)
18594#define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
18595
18596/******************** Bit definition for RCC_PLL2DIVR register ***************/
18597#define RCC_PLL2DIVR_N2_Pos (0U)
18598#define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos)
18599#define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
18600#define RCC_PLL2DIVR_P2_Pos (9U)
18601#define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos)
18602#define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
18603#define RCC_PLL2DIVR_Q2_Pos (16U)
18604#define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos)
18605#define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
18606#define RCC_PLL2DIVR_R2_Pos (24U)
18607#define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos)
18608#define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
18609
18610/******************** Bit definition for RCC_PLL2FRACR register ***************/
18611#define RCC_PLL2FRACR_FRACN2_Pos (3U)
18612#define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos)
18613#define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
18614
18615/******************** Bit definition for RCC_PLL3DIVR register ***************/
18616#define RCC_PLL3DIVR_N3_Pos (0U)
18617#define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos)
18618#define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
18619#define RCC_PLL3DIVR_P3_Pos (9U)
18620#define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos)
18621#define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
18622#define RCC_PLL3DIVR_Q3_Pos (16U)
18623#define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos)
18624#define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
18625#define RCC_PLL3DIVR_R3_Pos (24U)
18626#define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos)
18627#define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
18628
18629/******************** Bit definition for RCC_PLL3FRACR register ***************/
18630#define RCC_PLL3FRACR_FRACN3_Pos (3U)
18631#define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos)
18632#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
18633
18634/******************** Bit definition for RCC_D1CCIPR register ***************/
18635#define RCC_D1CCIPR_FMCSEL_Pos (0U)
18636#define RCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos)
18637#define RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk
18638#define RCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos)
18639#define RCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos)
18640#define RCC_D1CCIPR_QSPISEL_Pos (4U)
18641#define RCC_D1CCIPR_QSPISEL_Msk (0x3UL << RCC_D1CCIPR_QSPISEL_Pos)
18642#define RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_Msk
18643#define RCC_D1CCIPR_QSPISEL_0 (0x1UL << RCC_D1CCIPR_QSPISEL_Pos)
18644#define RCC_D1CCIPR_QSPISEL_1 (0x2UL << RCC_D1CCIPR_QSPISEL_Pos)
18645#define RCC_D1CCIPR_DSISEL_Pos (8U)
18646#define RCC_D1CCIPR_DSISEL_Msk (0x1UL << RCC_D1CCIPR_DSISEL_Pos)
18647#define RCC_D1CCIPR_DSISEL RCC_D1CCIPR_DSISEL_Msk
18648#define RCC_D1CCIPR_SDMMCSEL_Pos (16U)
18649#define RCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos)
18650#define RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk
18651#define RCC_D1CCIPR_CKPERSEL_Pos (28U)
18652#define RCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos)
18653#define RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk
18654#define RCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos)
18655#define RCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos)
18657/******************** Bit definition for RCC_D2CCIP1R register ***************/
18658#define RCC_D2CCIP1R_SAI1SEL_Pos (0U)
18659#define RCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos)
18660#define RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk
18661#define RCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos)
18662#define RCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos)
18663#define RCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos)
18665#define RCC_D2CCIP1R_SAI23SEL_Pos (6U)
18666#define RCC_D2CCIP1R_SAI23SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos)
18667#define RCC_D2CCIP1R_SAI23SEL RCC_D2CCIP1R_SAI23SEL_Msk
18668#define RCC_D2CCIP1R_SAI23SEL_0 (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos)
18669#define RCC_D2CCIP1R_SAI23SEL_1 (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos)
18670#define RCC_D2CCIP1R_SAI23SEL_2 (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos)
18672#define RCC_D2CCIP1R_SPI123SEL_Pos (12U)
18673#define RCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos)
18674#define RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk
18675#define RCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos)
18676#define RCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos)
18677#define RCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos)
18679#define RCC_D2CCIP1R_SPI45SEL_Pos (16U)
18680#define RCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos)
18681#define RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk
18682#define RCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos)
18683#define RCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos)
18684#define RCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos)
18686#define RCC_D2CCIP1R_SPDIFSEL_Pos (20U)
18687#define RCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
18688#define RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk
18689#define RCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
18690#define RCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
18692#define RCC_D2CCIP1R_DFSDM1SEL_Pos (24U)
18693#define RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos)
18694#define RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk
18695
18696#define RCC_D2CCIP1R_FDCANSEL_Pos (28U)
18697#define RCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos)
18698#define RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk
18699#define RCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos)
18700#define RCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos)
18702#define RCC_D2CCIP1R_SWPSEL_Pos (31U)
18703#define RCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos)
18704#define RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk
18705
18706/******************** Bit definition for RCC_D2CCIP2R register ***************/
18707#define RCC_D2CCIP2R_USART16SEL_Pos (3U)
18708#define RCC_D2CCIP2R_USART16SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos)
18709#define RCC_D2CCIP2R_USART16SEL RCC_D2CCIP2R_USART16SEL_Msk
18710#define RCC_D2CCIP2R_USART16SEL_0 (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos)
18711#define RCC_D2CCIP2R_USART16SEL_1 (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos)
18712#define RCC_D2CCIP2R_USART16SEL_2 (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos)
18714#define RCC_D2CCIP2R_USART28SEL_Pos (0U)
18715#define RCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos)
18716#define RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk
18717#define RCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos)
18718#define RCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos)
18719#define RCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos)
18721#define RCC_D2CCIP2R_RNGSEL_Pos (8U)
18722#define RCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos)
18723#define RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk
18724#define RCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos)
18725#define RCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos)
18727#define RCC_D2CCIP2R_I2C123SEL_Pos (12U)
18728#define RCC_D2CCIP2R_I2C123SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos)
18729#define RCC_D2CCIP2R_I2C123SEL RCC_D2CCIP2R_I2C123SEL_Msk
18730#define RCC_D2CCIP2R_I2C123SEL_0 (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos)
18731#define RCC_D2CCIP2R_I2C123SEL_1 (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos)
18733#define RCC_D2CCIP2R_USBSEL_Pos (20U)
18734#define RCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos)
18735#define RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk
18736#define RCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos)
18737#define RCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos)
18739#define RCC_D2CCIP2R_CECSEL_Pos (22U)
18740#define RCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos)
18741#define RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk
18742#define RCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos)
18743#define RCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos)
18745#define RCC_D2CCIP2R_LPTIM1SEL_Pos (28U)
18746#define RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
18747#define RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk
18748#define RCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
18749#define RCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
18750#define RCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
18752/******************** Bit definition for RCC_D3CCIPR register ***************/
18753#define RCC_D3CCIPR_LPUART1SEL_Pos (0U)
18754#define RCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos)
18755#define RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk
18756#define RCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos)
18757#define RCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos)
18758#define RCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos)
18760#define RCC_D3CCIPR_I2C4SEL_Pos (8U)
18761#define RCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos)
18762#define RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk
18763#define RCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos)
18764#define RCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos)
18766#define RCC_D3CCIPR_LPTIM2SEL_Pos (10U)
18767#define RCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
18768#define RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk
18769#define RCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
18770#define RCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
18771#define RCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
18773#define RCC_D3CCIPR_LPTIM345SEL_Pos (13U)
18774#define RCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
18775#define RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk
18776#define RCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
18777#define RCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
18778#define RCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
18780#define RCC_D3CCIPR_SAI4ASEL_Pos (21U)
18781#define RCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos)
18782#define RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk
18783#define RCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos)
18784#define RCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos)
18785#define RCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos)
18787#define RCC_D3CCIPR_SAI4BSEL_Pos (24U)
18788#define RCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos)
18789#define RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk
18790#define RCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos)
18791#define RCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos)
18792#define RCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos)
18794#define RCC_D3CCIPR_ADCSEL_Pos (16U)
18795#define RCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos)
18796#define RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk
18797#define RCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos)
18798#define RCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos)
18800#define RCC_D3CCIPR_SPI6SEL_Pos (28U)
18801#define RCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos)
18802#define RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk
18803#define RCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos)
18804#define RCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos)
18805#define RCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos)
18806/******************** Bit definition for RCC_CIER register ******************/
18807#define RCC_CIER_LSIRDYIE_Pos (0U)
18808#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)
18809#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
18810#define RCC_CIER_LSERDYIE_Pos (1U)
18811#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)
18812#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
18813#define RCC_CIER_HSIRDYIE_Pos (2U)
18814#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)
18815#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
18816#define RCC_CIER_HSERDYIE_Pos (3U)
18817#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)
18818#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
18819#define RCC_CIER_CSIRDYIE_Pos (4U)
18820#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos)
18821#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
18822#define RCC_CIER_HSI48RDYIE_Pos (5U)
18823#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)
18824#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
18825#define RCC_CIER_PLL1RDYIE_Pos (6U)
18826#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos)
18827#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
18828#define RCC_CIER_PLL2RDYIE_Pos (7U)
18829#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos)
18830#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
18831#define RCC_CIER_PLL3RDYIE_Pos (8U)
18832#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos)
18833#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
18834#define RCC_CIER_LSECSSIE_Pos (9U)
18835#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)
18836#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
18837
18838/******************** Bit definition for RCC_CIFR register ******************/
18839#define RCC_CIFR_LSIRDYF_Pos (0U)
18840#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)
18841#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
18842#define RCC_CIFR_LSERDYF_Pos (1U)
18843#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)
18844#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
18845#define RCC_CIFR_HSIRDYF_Pos (2U)
18846#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)
18847#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
18848#define RCC_CIFR_HSERDYF_Pos (3U)
18849#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)
18850#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
18851#define RCC_CIFR_CSIRDYF_Pos (4U)
18852#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos)
18853#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
18854#define RCC_CIFR_HSI48RDYF_Pos (5U)
18855#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos)
18856#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
18857#define RCC_CIFR_PLLRDYF_Pos (6U)
18858#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)
18859#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
18860#define RCC_CIFR_PLL2RDYF_Pos (7U)
18861#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos)
18862#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
18863#define RCC_CIFR_PLL3RDYF_Pos (8U)
18864#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos)
18865#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
18866#define RCC_CIFR_LSECSSF_Pos (9U)
18867#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)
18868#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
18869#define RCC_CIFR_HSECSSF_Pos (10U)
18870#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos)
18871#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
18872
18873/******************** Bit definition for RCC_CICR register ******************/
18874#define RCC_CICR_LSIRDYC_Pos (0U)
18875#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)
18876#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
18877#define RCC_CICR_LSERDYC_Pos (1U)
18878#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)
18879#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
18880#define RCC_CICR_HSIRDYC_Pos (2U)
18881#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)
18882#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
18883#define RCC_CICR_HSERDYC_Pos (3U)
18884#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)
18885#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
18886#define RCC_CICR_CSIRDYC_Pos (4U)
18887#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos)
18888#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
18889#define RCC_CICR_HSI48RDYC_Pos (5U)
18890#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos)
18891#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
18892#define RCC_CICR_PLLRDYC_Pos (6U)
18893#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)
18894#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
18895#define RCC_CICR_PLL2RDYC_Pos (7U)
18896#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos)
18897#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
18898#define RCC_CICR_PLL3RDYC_Pos (8U)
18899#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos)
18900#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
18901#define RCC_CICR_LSECSSC_Pos (9U)
18902#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)
18903#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
18904#define RCC_CICR_HSECSSC_Pos (10U)
18905#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos)
18906#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
18907
18908/******************** Bit definition for RCC_BDCR register ******************/
18909#define RCC_BDCR_LSEON_Pos (0U)
18910#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
18911#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
18912#define RCC_BDCR_LSERDY_Pos (1U)
18913#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
18914#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
18915#define RCC_BDCR_LSEBYP_Pos (2U)
18916#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
18917#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
18918
18919#define RCC_BDCR_LSEDRV_Pos (3U)
18920#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
18921#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
18922#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
18923#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
18925#define RCC_BDCR_LSECSSON_Pos (5U)
18926#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)
18927#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
18928#define RCC_BDCR_LSECSSD_Pos (6U)
18929#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)
18930#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
18931
18932#define RCC_BDCR_RTCSEL_Pos (8U)
18933#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
18934#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
18935#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
18936#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
18938#define RCC_BDCR_RTCEN_Pos (15U)
18939#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
18940#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
18941#define RCC_BDCR_BDRST_Pos (16U)
18942#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
18943#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
18944/******************** Bit definition for RCC_CSR register *******************/
18945#define RCC_CSR_LSION_Pos (0U)
18946#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
18947#define RCC_CSR_LSION RCC_CSR_LSION_Msk
18948#define RCC_CSR_LSIRDY_Pos (1U)
18949#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
18950#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
18951
18952
18953/******************** Bit definition for RCC_AHB3ENR register **************/
18954#define RCC_AHB3ENR_MDMAEN_Pos (0U)
18955#define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)
18956#define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
18957#define RCC_AHB3ENR_DMA2DEN_Pos (4U)
18958#define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)
18959#define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
18960#define RCC_AHB3ENR_JPGDECEN_Pos (5U)
18961#define RCC_AHB3ENR_JPGDECEN_Msk (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)
18962#define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
18963#define RCC_AHB3ENR_FMCEN_Pos (12U)
18964#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
18965#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
18966#define RCC_AHB3ENR_QSPIEN_Pos (14U)
18967#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
18968#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
18969#define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
18970#define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)
18971#define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
18972#define RCC_AHB3ENR_FLASHEN_Pos (8U)
18973#define RCC_AHB3ENR_FLASHEN_Msk (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)
18974#define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk
18975#define RCC_AHB3ENR_DTCM1EN_Pos (28U)
18976#define RCC_AHB3ENR_DTCM1EN_Msk (0x1UL << RCC_AHB3ENR_DTCM1EN_Pos)
18977#define RCC_AHB3ENR_DTCM1EN RCC_AHB3ENR_DTCM1EN_Msk
18978#define RCC_AHB3ENR_DTCM2EN_Pos (29U)
18979#define RCC_AHB3ENR_DTCM2EN_Msk (0x1UL << RCC_AHB3ENR_DTCM2EN_Pos)
18980#define RCC_AHB3ENR_DTCM2EN RCC_AHB3ENR_DTCM2EN_Msk
18981#define RCC_AHB3ENR_ITCMEN_Pos (30U)
18982#define RCC_AHB3ENR_ITCMEN_Msk (0x1UL << RCC_AHB3ENR_ITCMEN_Pos)
18983#define RCC_AHB3ENR_ITCMEN RCC_AHB3ENR_ITCMEN_Msk
18984#define RCC_AHB3ENR_AXISRAMEN_Pos (31U)
18985#define RCC_AHB3ENR_AXISRAMEN_Msk (0x1UL << RCC_AHB3ENR_AXISRAMEN_Pos)
18986#define RCC_AHB3ENR_AXISRAMEN RCC_AHB3ENR_AXISRAMEN_Msk
18987
18988/* Legacy define */
18989#define RCC_AHB3ENR_D1SRAM1EN_Pos RCC_AHB3ENR_AXISRAMEN_Pos
18990#define RCC_AHB3ENR_D1SRAM1EN_Msk RCC_AHB3ENR_AXISRAMEN_Msk
18991#define RCC_AHB3ENR_D1SRAM1EN RCC_AHB3ENR_AXISRAMEN
18992
18993/******************** Bit definition for RCC_AHB1ENR register ***************/
18994#define RCC_AHB1ENR_DMA1EN_Pos (0U)
18995#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
18996#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
18997#define RCC_AHB1ENR_DMA2EN_Pos (1U)
18998#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
18999#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
19000#define RCC_AHB1ENR_ADC12EN_Pos (5U)
19001#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)
19002#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
19003#define RCC_AHB1ENR_ARTEN_Pos (14U)
19004#define RCC_AHB1ENR_ARTEN_Msk (0x1UL << RCC_AHB1ENR_ARTEN_Pos)
19005#define RCC_AHB1ENR_ARTEN RCC_AHB1ENR_ARTEN_Msk
19006#define RCC_AHB1ENR_ETH1MACEN_Pos (15U)
19007#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)
19008#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk
19009#define RCC_AHB1ENR_ETH1TXEN_Pos (16U)
19010#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)
19011#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk
19012#define RCC_AHB1ENR_ETH1RXEN_Pos (17U)
19013#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)
19014#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk
19015#define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
19016#define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)
19017#define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
19018#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
19019#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos)
19020#define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
19021#define RCC_AHB1ENR_USB2OTGFSEN_Pos (27U)
19022#define RCC_AHB1ENR_USB2OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)
19023#define RCC_AHB1ENR_USB2OTGFSEN RCC_AHB1ENR_USB2OTGFSEN_Msk
19024#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos (28U)
19025#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos)
19026#define RCC_AHB1ENR_USB2OTGFSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
19027
19028/* Legacy define */
19029#define RCC_AHB1ENR_USB2OTGHSEN_Pos RCC_AHB1ENR_USB2OTGFSEN_Pos
19030#define RCC_AHB1ENR_USB2OTGHSEN_Msk RCC_AHB1ENR_USB2OTGFSEN_Msk
19031#define RCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGFSEN
19032#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
19033#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
19034#define RCC_AHB1ENR_USB2OTGHSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN
19035
19036
19037/******************** Bit definition for RCC_AHB2ENR register ***************/
19038#define RCC_AHB2ENR_DCMIEN_Pos (0U)
19039#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
19040#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
19041#define RCC_AHB2ENR_RNGEN_Pos (6U)
19042#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
19043#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
19044#define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
19045#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)
19046#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
19047#define RCC_AHB2ENR_SRAM1EN_Pos (29U)
19048#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)
19049#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk
19050#define RCC_AHB2ENR_SRAM2EN_Pos (30U)
19051#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)
19052#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk
19053#define RCC_AHB2ENR_SRAM3EN_Pos (31U)
19054#define RCC_AHB2ENR_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)
19055#define RCC_AHB2ENR_SRAM3EN RCC_AHB2ENR_SRAM3EN_Msk
19056
19057/* Legacy define */
19058#define RCC_AHB2ENR_D2SRAM1EN_Pos RCC_AHB2ENR_SRAM1EN_Pos
19059#define RCC_AHB2ENR_D2SRAM1EN_Msk RCC_AHB2ENR_SRAM1EN_Msk
19060#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_SRAM1EN
19061#define RCC_AHB2ENR_D2SRAM2EN_Pos RCC_AHB2ENR_SRAM2EN_Pos
19062#define RCC_AHB2ENR_D2SRAM2EN_Msk RCC_AHB2ENR_SRAM2EN_Msk
19063#define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_SRAM2EN
19064#define RCC_AHB2ENR_D2SRAM3EN_Pos RCC_AHB2ENR_SRAM3EN_Pos
19065#define RCC_AHB2ENR_D2SRAM3EN_Msk RCC_AHB2ENR_SRAM3EN_Msk
19066#define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_SRAM3EN
19067
19068/******************** Bit definition for RCC_AHB4ENR register ******************/
19069#define RCC_AHB4ENR_GPIOAEN_Pos (0U)
19070#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)
19071#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
19072#define RCC_AHB4ENR_GPIOBEN_Pos (1U)
19073#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)
19074#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
19075#define RCC_AHB4ENR_GPIOCEN_Pos (2U)
19076#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)
19077#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
19078#define RCC_AHB4ENR_GPIODEN_Pos (3U)
19079#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)
19080#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
19081#define RCC_AHB4ENR_GPIOEEN_Pos (4U)
19082#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)
19083#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
19084#define RCC_AHB4ENR_GPIOFEN_Pos (5U)
19085#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)
19086#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
19087#define RCC_AHB4ENR_GPIOGEN_Pos (6U)
19088#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)
19089#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
19090#define RCC_AHB4ENR_GPIOHEN_Pos (7U)
19091#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)
19092#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
19093#define RCC_AHB4ENR_GPIOIEN_Pos (8U)
19094#define RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)
19095#define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk
19096#define RCC_AHB4ENR_GPIOJEN_Pos (9U)
19097#define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)
19098#define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
19099#define RCC_AHB4ENR_GPIOKEN_Pos (10U)
19100#define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)
19101#define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
19102#define RCC_AHB4ENR_CRCEN_Pos (19U)
19103#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos)
19104#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk
19105#define RCC_AHB4ENR_BDMAEN_Pos (21U)
19106#define RCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)
19107#define RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk
19108#define RCC_AHB4ENR_ADC3EN_Pos (24U)
19109#define RCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)
19110#define RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk
19111#define RCC_AHB4ENR_HSEMEN_Pos (25U)
19112#define RCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)
19113#define RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk
19114#define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
19115#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)
19116#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
19117
19118/******************** Bit definition for RCC_APB3ENR register ******************/
19119#define RCC_APB3ENR_LTDCEN_Pos (3U)
19120#define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos)
19121#define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
19122#define RCC_APB3ENR_DSIEN_Pos (4U)
19123#define RCC_APB3ENR_DSIEN_Msk (0x1UL << RCC_APB3ENR_DSIEN_Pos)
19124#define RCC_APB3ENR_DSIEN RCC_APB3ENR_DSIEN_Msk
19125#define RCC_APB3ENR_WWDG1EN_Pos (6U)
19126#define RCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos)
19127#define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk
19128
19129/******************** Bit definition for RCC_APB1LENR register ******************/
19130
19131#define RCC_APB1LENR_TIM2EN_Pos (0U)
19132#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos)
19133#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
19134#define RCC_APB1LENR_TIM3EN_Pos (1U)
19135#define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos)
19136#define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
19137#define RCC_APB1LENR_TIM4EN_Pos (2U)
19138#define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos)
19139#define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
19140#define RCC_APB1LENR_TIM5EN_Pos (3U)
19141#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos)
19142#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
19143#define RCC_APB1LENR_TIM6EN_Pos (4U)
19144#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos)
19145#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
19146#define RCC_APB1LENR_TIM7EN_Pos (5U)
19147#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos)
19148#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
19149#define RCC_APB1LENR_TIM12EN_Pos (6U)
19150#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos)
19151#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
19152#define RCC_APB1LENR_TIM13EN_Pos (7U)
19153#define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos)
19154#define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
19155#define RCC_APB1LENR_TIM14EN_Pos (8U)
19156#define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos)
19157#define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
19158#define RCC_APB1LENR_LPTIM1EN_Pos (9U)
19159#define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos)
19160#define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
19161
19162#define RCC_APB1LENR_WWDG2EN_Pos (11U)
19163#define RCC_APB1LENR_WWDG2EN_Msk (0x1UL << RCC_APB1LENR_WWDG2EN_Pos)
19164#define RCC_APB1LENR_WWDG2EN RCC_APB1LENR_WWDG2EN_Msk
19165
19166#define RCC_APB1LENR_SPI2EN_Pos (14U)
19167#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos)
19168#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
19169#define RCC_APB1LENR_SPI3EN_Pos (15U)
19170#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos)
19171#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
19172#define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
19173#define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos)
19174#define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
19175#define RCC_APB1LENR_USART2EN_Pos (17U)
19176#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos)
19177#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
19178#define RCC_APB1LENR_USART3EN_Pos (18U)
19179#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos)
19180#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
19181#define RCC_APB1LENR_UART4EN_Pos (19U)
19182#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos)
19183#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
19184#define RCC_APB1LENR_UART5EN_Pos (20U)
19185#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos)
19186#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
19187#define RCC_APB1LENR_I2C1EN_Pos (21U)
19188#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos)
19189#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
19190#define RCC_APB1LENR_I2C2EN_Pos (22U)
19191#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos)
19192#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
19193#define RCC_APB1LENR_I2C3EN_Pos (23U)
19194#define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos)
19195#define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
19196#define RCC_APB1LENR_CECEN_Pos (27U)
19197#define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos)
19198#define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
19199#define RCC_APB1LENR_DAC12EN_Pos (29U)
19200#define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos)
19201#define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
19202#define RCC_APB1LENR_UART7EN_Pos (30U)
19203#define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos)
19204#define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
19205#define RCC_APB1LENR_UART8EN_Pos (31U)
19206#define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos)
19207#define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
19208
19209/* Legacy define */
19210#define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
19211#define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
19212#define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
19213/******************** Bit definition for RCC_APB1HENR register ******************/
19214#define RCC_APB1HENR_CRSEN_Pos (1U)
19215#define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos)
19216#define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
19217#define RCC_APB1HENR_SWPMIEN_Pos (2U)
19218#define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos)
19219#define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
19220#define RCC_APB1HENR_OPAMPEN_Pos (4U)
19221#define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos)
19222#define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
19223#define RCC_APB1HENR_MDIOSEN_Pos (5U)
19224#define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos)
19225#define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
19226#define RCC_APB1HENR_FDCANEN_Pos (8U)
19227#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos)
19228#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
19229
19230/******************** Bit definition for RCC_APB2ENR register ******************/
19231#define RCC_APB2ENR_TIM1EN_Pos (0U)
19232#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
19233#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
19234#define RCC_APB2ENR_TIM8EN_Pos (1U)
19235#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
19236#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
19237#define RCC_APB2ENR_USART1EN_Pos (4U)
19238#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
19239#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
19240#define RCC_APB2ENR_USART6EN_Pos (5U)
19241#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
19242#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
19243#define RCC_APB2ENR_SPI1EN_Pos (12U)
19244#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
19245#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
19246#define RCC_APB2ENR_SPI4EN_Pos (13U)
19247#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
19248#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
19249#define RCC_APB2ENR_TIM15EN_Pos (16U)
19250#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
19251#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
19252#define RCC_APB2ENR_TIM16EN_Pos (17U)
19253#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
19254#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
19255#define RCC_APB2ENR_TIM17EN_Pos (18U)
19256#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
19257#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
19258#define RCC_APB2ENR_SPI5EN_Pos (20U)
19259#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
19260#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
19261#define RCC_APB2ENR_SAI1EN_Pos (22U)
19262#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
19263#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
19264#define RCC_APB2ENR_SAI2EN_Pos (23U)
19265#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos)
19266#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
19267#define RCC_APB2ENR_SAI3EN_Pos (24U)
19268#define RCC_APB2ENR_SAI3EN_Msk (0x1UL << RCC_APB2ENR_SAI3EN_Pos)
19269#define RCC_APB2ENR_SAI3EN RCC_APB2ENR_SAI3EN_Msk
19270#define RCC_APB2ENR_DFSDM1EN_Pos (28U)
19271#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
19272#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
19273#define RCC_APB2ENR_HRTIMEN_Pos (29U)
19274#define RCC_APB2ENR_HRTIMEN_Msk (0x1UL << RCC_APB2ENR_HRTIMEN_Pos)
19275#define RCC_APB2ENR_HRTIMEN RCC_APB2ENR_HRTIMEN_Msk
19276
19277/******************** Bit definition for RCC_APB4ENR register ******************/
19278#define RCC_APB4ENR_SYSCFGEN_Pos (1U)
19279#define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos)
19280#define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
19281#define RCC_APB4ENR_LPUART1EN_Pos (3U)
19282#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos)
19283#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
19284#define RCC_APB4ENR_SPI6EN_Pos (5U)
19285#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos)
19286#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
19287#define RCC_APB4ENR_I2C4EN_Pos (7U)
19288#define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos)
19289#define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
19290#define RCC_APB4ENR_LPTIM2EN_Pos (9U)
19291#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos)
19292#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
19293#define RCC_APB4ENR_LPTIM3EN_Pos (10U)
19294#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos)
19295#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
19296#define RCC_APB4ENR_LPTIM4EN_Pos (11U)
19297#define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos)
19298#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk
19299#define RCC_APB4ENR_LPTIM5EN_Pos (12U)
19300#define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos)
19301#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk
19302#define RCC_APB4ENR_COMP12EN_Pos (14U)
19303#define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos)
19304#define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
19305#define RCC_APB4ENR_VREFEN_Pos (15U)
19306#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos)
19307#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
19308#define RCC_APB4ENR_RTCAPBEN_Pos (16U)
19309#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos)
19310#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
19311#define RCC_APB4ENR_SAI4EN_Pos (21U)
19312#define RCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos)
19313#define RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk
19314
19315
19316/******************** Bit definition for RCC_AHB3RSTR register ***************/
19317#define RCC_AHB3RSTR_MDMARST_Pos (0U)
19318#define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)
19319#define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
19320#define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
19321#define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)
19322#define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
19323#define RCC_AHB3RSTR_JPGDECRST_Pos (5U)
19324#define RCC_AHB3RSTR_JPGDECRST_Msk (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)
19325#define RCC_AHB3RSTR_JPGDECRST RCC_AHB3RSTR_JPGDECRST_Msk
19326#define RCC_AHB3RSTR_FMCRST_Pos (12U)
19327#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
19328#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
19329#define RCC_AHB3RSTR_QSPIRST_Pos (14U)
19330#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
19331#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
19332#define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
19333#define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)
19334#define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
19335
19336
19337/******************** Bit definition for RCC_AHB1RSTR register ***************/
19338#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
19339#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
19340#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
19341#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
19342#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
19343#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
19344#define RCC_AHB1RSTR_ADC12RST_Pos (5U)
19345#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)
19346#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
19347#define RCC_AHB1RSTR_ARTRST_Pos (14U)
19348#define RCC_AHB1RSTR_ARTRST_Msk (0x1UL << RCC_AHB1RSTR_ARTRST_Pos)
19349#define RCC_AHB1RSTR_ARTRST RCC_AHB1RSTR_ARTRST_Msk
19350#define RCC_AHB1RSTR_ETH1MACRST_Pos (15U)
19351#define RCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)
19352#define RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk
19353#define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
19354#define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos)
19355#define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
19356#define RCC_AHB1RSTR_USB2OTGFSRST_Pos (27U)
19357#define RCC_AHB1RSTR_USB2OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos)
19358#define RCC_AHB1RSTR_USB2OTGFSRST RCC_AHB1RSTR_USB2OTGFSRST_Msk
19359
19360/* Legacy define */
19361#define RCC_AHB1RSTR_USB2OTGHSRST_Pos RCC_AHB1RSTR_USB2OTGFSRST_Pos
19362#define RCC_AHB1RSTR_USB2OTGHSRST_Msk RCC_AHB1RSTR_USB2OTGFSRST_Msk
19363#define RCC_AHB1RSTR_USB2OTGHSRST RCC_AHB1RSTR_USB2OTGFSRST
19364
19365/******************** Bit definition for RCC_AHB2RSTR register ***************/
19366#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
19367#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
19368#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
19369#define RCC_AHB2RSTR_RNGRST_Pos (6U)
19370#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
19371#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
19372#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
19373#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)
19374#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
19375
19376/******************** Bit definition for RCC_AHB4RSTR register ******************/
19377#define RCC_AHB4RSTR_GPIOARST_Pos (0U)
19378#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)
19379#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
19380#define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
19381#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)
19382#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
19383#define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
19384#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)
19385#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
19386#define RCC_AHB4RSTR_GPIODRST_Pos (3U)
19387#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)
19388#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
19389#define RCC_AHB4RSTR_GPIOERST_Pos (4U)
19390#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)
19391#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
19392#define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
19393#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)
19394#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
19395#define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
19396#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)
19397#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
19398#define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
19399#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)
19400#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
19401#define RCC_AHB4RSTR_GPIOIRST_Pos (8U)
19402#define RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)
19403#define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk
19404#define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
19405#define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)
19406#define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
19407#define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
19408#define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)
19409#define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
19410#define RCC_AHB4RSTR_CRCRST_Pos (19U)
19411#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)
19412#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk
19413#define RCC_AHB4RSTR_BDMARST_Pos (21U)
19414#define RCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)
19415#define RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk
19416#define RCC_AHB4RSTR_ADC3RST_Pos (24U)
19417#define RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)
19418#define RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk
19419#define RCC_AHB4RSTR_HSEMRST_Pos (25U)
19420#define RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)
19421#define RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk
19422
19423
19424/******************** Bit definition for RCC_APB3RSTR register ******************/
19425#define RCC_APB3RSTR_LTDCRST_Pos (3U)
19426#define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos)
19427#define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
19428#define RCC_APB3RSTR_DSIRST_Pos (4U)
19429#define RCC_APB3RSTR_DSIRST_Msk (0x1UL << RCC_APB3RSTR_DSIRST_Pos)
19430#define RCC_APB3RSTR_DSIRST RCC_APB3RSTR_DSIRST_Msk
19431
19432/******************** Bit definition for RCC_APB1LRSTR register ******************/
19433
19434#define RCC_APB1LRSTR_TIM2RST_Pos (0U)
19435#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos)
19436#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
19437#define RCC_APB1LRSTR_TIM3RST_Pos (1U)
19438#define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos)
19439#define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
19440#define RCC_APB1LRSTR_TIM4RST_Pos (2U)
19441#define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos)
19442#define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
19443#define RCC_APB1LRSTR_TIM5RST_Pos (3U)
19444#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos)
19445#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
19446#define RCC_APB1LRSTR_TIM6RST_Pos (4U)
19447#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos)
19448#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
19449#define RCC_APB1LRSTR_TIM7RST_Pos (5U)
19450#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos)
19451#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
19452#define RCC_APB1LRSTR_TIM12RST_Pos (6U)
19453#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos)
19454#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
19455#define RCC_APB1LRSTR_TIM13RST_Pos (7U)
19456#define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos)
19457#define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
19458#define RCC_APB1LRSTR_TIM14RST_Pos (8U)
19459#define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos)
19460#define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
19461#define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
19462#define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos)
19463#define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
19464#define RCC_APB1LRSTR_SPI2RST_Pos (14U)
19465#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos)
19466#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
19467#define RCC_APB1LRSTR_SPI3RST_Pos (15U)
19468#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos)
19469#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
19470#define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
19471#define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos)
19472#define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
19473#define RCC_APB1LRSTR_USART2RST_Pos (17U)
19474#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos)
19475#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
19476#define RCC_APB1LRSTR_USART3RST_Pos (18U)
19477#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos)
19478#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
19479#define RCC_APB1LRSTR_UART4RST_Pos (19U)
19480#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos)
19481#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
19482#define RCC_APB1LRSTR_UART5RST_Pos (20U)
19483#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos)
19484#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
19485#define RCC_APB1LRSTR_I2C1RST_Pos (21U)
19486#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos)
19487#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
19488#define RCC_APB1LRSTR_I2C2RST_Pos (22U)
19489#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos)
19490#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
19491#define RCC_APB1LRSTR_I2C3RST_Pos (23U)
19492#define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos)
19493#define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
19494#define RCC_APB1LRSTR_CECRST_Pos (27U)
19495#define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos)
19496#define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
19497#define RCC_APB1LRSTR_DAC12RST_Pos (29U)
19498#define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos)
19499#define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
19500#define RCC_APB1LRSTR_UART7RST_Pos (30U)
19501#define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos)
19502#define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
19503#define RCC_APB1LRSTR_UART8RST_Pos (31U)
19504#define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos)
19505#define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
19506
19507/* Legacy define */
19508#define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
19509#define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
19510#define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
19511/******************** Bit definition for RCC_APB1HRSTR register ******************/
19512#define RCC_APB1HRSTR_CRSRST_Pos (1U)
19513#define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos)
19514#define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
19515#define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
19516#define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos)
19517#define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
19518#define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
19519#define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos)
19520#define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
19521#define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
19522#define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos)
19523#define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
19524#define RCC_APB1HRSTR_FDCANRST_Pos (8U)
19525#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos)
19526#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
19527
19528/******************** Bit definition for RCC_APB2RSTR register ******************/
19529#define RCC_APB2RSTR_TIM1RST_Pos (0U)
19530#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
19531#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
19532#define RCC_APB2RSTR_TIM8RST_Pos (1U)
19533#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
19534#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
19535#define RCC_APB2RSTR_USART1RST_Pos (4U)
19536#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
19537#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
19538#define RCC_APB2RSTR_USART6RST_Pos (5U)
19539#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
19540#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
19541#define RCC_APB2RSTR_SPI1RST_Pos (12U)
19542#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
19543#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
19544#define RCC_APB2RSTR_SPI4RST_Pos (13U)
19545#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
19546#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
19547#define RCC_APB2RSTR_TIM15RST_Pos (16U)
19548#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
19549#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
19550#define RCC_APB2RSTR_TIM16RST_Pos (17U)
19551#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
19552#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
19553#define RCC_APB2RSTR_TIM17RST_Pos (18U)
19554#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
19555#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
19556#define RCC_APB2RSTR_SPI5RST_Pos (20U)
19557#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
19558#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
19559#define RCC_APB2RSTR_SAI1RST_Pos (22U)
19560#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
19561#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
19562#define RCC_APB2RSTR_SAI2RST_Pos (23U)
19563#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)
19564#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
19565#define RCC_APB2RSTR_SAI3RST_Pos (24U)
19566#define RCC_APB2RSTR_SAI3RST_Msk (0x1UL << RCC_APB2RSTR_SAI3RST_Pos)
19567#define RCC_APB2RSTR_SAI3RST RCC_APB2RSTR_SAI3RST_Msk
19568#define RCC_APB2RSTR_DFSDM1RST_Pos (28U)
19569#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
19570#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
19571#define RCC_APB2RSTR_HRTIMRST_Pos (29U)
19572#define RCC_APB2RSTR_HRTIMRST_Msk (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos)
19573#define RCC_APB2RSTR_HRTIMRST RCC_APB2RSTR_HRTIMRST_Msk
19574
19575/******************** Bit definition for RCC_APB4RSTR register ******************/
19576#define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
19577#define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos)
19578#define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
19579#define RCC_APB4RSTR_LPUART1RST_Pos (3U)
19580#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos)
19581#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
19582#define RCC_APB4RSTR_SPI6RST_Pos (5U)
19583#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos)
19584#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
19585#define RCC_APB4RSTR_I2C4RST_Pos (7U)
19586#define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos)
19587#define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
19588#define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
19589#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos)
19590#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
19591#define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
19592#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos)
19593#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
19594#define RCC_APB4RSTR_LPTIM4RST_Pos (11U)
19595#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos)
19596#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk
19597#define RCC_APB4RSTR_LPTIM5RST_Pos (12U)
19598#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos)
19599#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk
19600#define RCC_APB4RSTR_COMP12RST_Pos (14U)
19601#define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos)
19602#define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
19603#define RCC_APB4RSTR_VREFRST_Pos (15U)
19604#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos)
19605#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
19606#define RCC_APB4RSTR_SAI4RST_Pos (21U)
19607#define RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos)
19608#define RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk
19609
19610
19611/******************** Bit definition for RCC_GCR register ********************/
19612#define RCC_GCR_WW1RSC_Pos (0U)
19613#define RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos)
19614#define RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk
19615#define RCC_GCR_WW2RSC_Pos (1U)
19616#define RCC_GCR_WW2RSC_Msk (0x1UL << RCC_GCR_WW2RSC_Pos)
19617#define RCC_GCR_WW2RSC RCC_GCR_WW2RSC_Msk
19618#define RCC_GCR_BOOT_C1_Pos (2U)
19619#define RCC_GCR_BOOT_C1_Msk (0x1UL << RCC_GCR_BOOT_C1_Pos)
19620#define RCC_GCR_BOOT_C1 RCC_GCR_BOOT_C1_Msk
19621#define RCC_GCR_BOOT_C2_Pos (3U)
19622#define RCC_GCR_BOOT_C2_Msk (0x1UL << RCC_GCR_BOOT_C2_Pos)
19623#define RCC_GCR_BOOT_C2 RCC_GCR_BOOT_C2_Msk
19624
19625/******************** Bit definition for RCC_D3AMR register ********************/
19626#define RCC_D3AMR_BDMAAMEN_Pos (0U)
19627#define RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos)
19628#define RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk
19629#define RCC_D3AMR_LPUART1AMEN_Pos (3U)
19630#define RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos)
19631#define RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk
19632#define RCC_D3AMR_SPI6AMEN_Pos (5U)
19633#define RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos)
19634#define RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk
19635#define RCC_D3AMR_I2C4AMEN_Pos (7U)
19636#define RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos)
19637#define RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk
19638#define RCC_D3AMR_LPTIM2AMEN_Pos (9U)
19639#define RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos)
19640#define RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk
19641#define RCC_D3AMR_LPTIM3AMEN_Pos (10U)
19642#define RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos)
19643#define RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk
19644#define RCC_D3AMR_LPTIM4AMEN_Pos (11U)
19645#define RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos)
19646#define RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk
19647#define RCC_D3AMR_LPTIM5AMEN_Pos (12U)
19648#define RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos)
19649#define RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk
19650#define RCC_D3AMR_COMP12AMEN_Pos (14U)
19651#define RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos)
19652#define RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk
19653#define RCC_D3AMR_VREFAMEN_Pos (15U)
19654#define RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos)
19655#define RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk
19656#define RCC_D3AMR_RTCAMEN_Pos (16U)
19657#define RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos)
19658#define RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk
19659#define RCC_D3AMR_CRCAMEN_Pos (19U)
19660#define RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos)
19661#define RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk
19662#define RCC_D3AMR_SAI4AMEN_Pos (21U)
19663#define RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos)
19664#define RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk
19665#define RCC_D3AMR_ADC3AMEN_Pos (24U)
19666#define RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos)
19667#define RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk
19668
19669
19670#define RCC_D3AMR_BKPRAMAMEN_Pos (28U)
19671#define RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos)
19672#define RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk
19673#define RCC_D3AMR_SRAM4AMEN_Pos (29U)
19674#define RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos)
19675#define RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk
19676/******************** Bit definition for RCC_AHB3LPENR register **************/
19677#define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
19678#define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)
19679#define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
19680#define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
19681#define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)
19682#define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
19683#define RCC_AHB3LPENR_JPGDECLPEN_Pos (5U)
19684#define RCC_AHB3LPENR_JPGDECLPEN_Msk (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)
19685#define RCC_AHB3LPENR_JPGDECLPEN RCC_AHB3LPENR_JPGDECLPEN_Msk
19686#define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
19687#define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)
19688#define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
19689#define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
19690#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
19691#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
19692#define RCC_AHB3LPENR_QSPILPEN_Pos (14U)
19693#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
19694#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
19695#define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
19696#define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)
19697#define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
19698#define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
19699#define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)
19700#define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
19701#define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
19702#define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)
19703#define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
19704#define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
19705#define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)
19706#define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
19707#define RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U)
19708#define RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)
19709#define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk
19710
19711
19712/******************** Bit definition for RCC_AHB1LPENR register ***************/
19713#define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
19714#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
19715#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
19716#define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
19717#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
19718#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
19719#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
19720#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)
19721#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
19722#define RCC_AHB1LPENR_ARTLPEN_Pos (14U)
19723#define RCC_AHB1LPENR_ARTLPEN_Msk (0x1UL << RCC_AHB1LPENR_ARTLPEN_Pos)
19724#define RCC_AHB1LPENR_ARTLPEN RCC_AHB1LPENR_ARTLPEN_Msk
19725#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U)
19726#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos)
19727#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk
19728#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U)
19729#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos)
19730#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk
19731#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U)
19732#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos)
19733#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk
19734#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
19735#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos)
19736#define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
19737#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
19738#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos)
19739#define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
19740#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos (27U)
19741#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos)
19742#define RCC_AHB1LPENR_USB2OTGFSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
19743#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos (28U)
19744#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos)
19745#define RCC_AHB1LPENR_USB2OTGFSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
19746
19747/* Legacy define */
19748#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
19749#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
19750#define RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN
19751#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
19752#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
19753#define RCC_AHB1LPENR_USB2OTGHSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN
19754
19755/******************** Bit definition for RCC_AHB2LPENR register ***************/
19756#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
19757#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
19758#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
19759#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
19760#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
19761#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
19762#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
19763#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos)
19764#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
19765#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U)
19766#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos)
19767#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk
19768#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
19769#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos)
19770#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
19771#define RCC_AHB2LPENR_SRAM3LPEN_Pos (31U)
19772#define RCC_AHB2LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos)
19773#define RCC_AHB2LPENR_SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN_Msk
19774
19775/* Legacy define */
19776#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos RCC_AHB2LPENR_SRAM1LPEN_Pos
19777#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk RCC_AHB2LPENR_SRAM1LPEN_Msk
19778#define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN
19779#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos RCC_AHB2LPENR_SRAM2LPEN_Pos
19780#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk RCC_AHB2LPENR_SRAM2LPEN_Msk
19781#define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN
19782#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos RCC_AHB2LPENR_SRAM3LPEN_Pos
19783#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk RCC_AHB2LPENR_SRAM3LPEN_Msk
19784#define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN
19785
19786/******************** Bit definition for RCC_AHB4LPENR register ******************/
19787#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
19788#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)
19789#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
19790#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
19791#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)
19792#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
19793#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
19794#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)
19795#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
19796#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
19797#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)
19798#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
19799#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
19800#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)
19801#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
19802#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
19803#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)
19804#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
19805#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
19806#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)
19807#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
19808#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
19809#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)
19810#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
19811#define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)
19812#define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos)
19813#define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk
19814#define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
19815#define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos)
19816#define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
19817#define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
19818#define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos)
19819#define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
19820#define RCC_AHB4LPENR_CRCLPEN_Pos (19U)
19821#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos)
19822#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk
19823#define RCC_AHB4LPENR_BDMALPEN_Pos (21U)
19824#define RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos)
19825#define RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk
19826#define RCC_AHB4LPENR_ADC3LPEN_Pos (24U)
19827#define RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos)
19828#define RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk
19829#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
19830#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos)
19831#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
19832#define RCC_AHB4LPENR_SRAM4LPEN_Pos (29U)
19833#define RCC_AHB4LPENR_SRAM4LPEN_Msk (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos)
19834#define RCC_AHB4LPENR_SRAM4LPEN RCC_AHB4LPENR_SRAM4LPEN_Msk
19835
19836/* Legacy define */
19837#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos RCC_AHB4LPENR_SRAM4LPEN_Pos
19838#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk RCC_AHB4LPENR_SRAM4LPEN_Msk
19839#define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_SRAM4LPEN
19840/******************** Bit definition for RCC_APB3LPENR register ******************/
19841#define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
19842#define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos)
19843#define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
19844#define RCC_APB3LPENR_DSILPEN_Pos (4U)
19845#define RCC_APB3LPENR_DSILPEN_Msk (0x1UL << RCC_APB3LPENR_DSILPEN_Pos)
19846#define RCC_APB3LPENR_DSILPEN RCC_APB3LPENR_DSILPEN_Msk
19847#define RCC_APB3LPENR_WWDG1LPEN_Pos (6U)
19848#define RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos)
19849#define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk
19850
19851/******************** Bit definition for RCC_APB1LLPENR register ******************/
19852
19853#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
19854#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos)
19855#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
19856#define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
19857#define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos)
19858#define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
19859#define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
19860#define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos)
19861#define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
19862#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
19863#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos)
19864#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
19865#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
19866#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos)
19867#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
19868#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
19869#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos)
19870#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
19871#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
19872#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos)
19873#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
19874#define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
19875#define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos)
19876#define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
19877#define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
19878#define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos)
19879#define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
19880#define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
19881#define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos)
19882#define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
19883
19884#define RCC_APB1LLPENR_WWDG2LPEN_Pos (11U)
19885#define RCC_APB1LLPENR_WWDG2LPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDG2LPEN_Pos)
19886#define RCC_APB1LLPENR_WWDG2LPEN RCC_APB1LLPENR_WWDG2LPEN_Msk
19887
19888#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
19889#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos)
19890#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
19891#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
19892#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos)
19893#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
19894#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
19895#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos)
19896#define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
19897#define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
19898#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos)
19899#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
19900#define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
19901#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos)
19902#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
19903#define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
19904#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos)
19905#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
19906#define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
19907#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos)
19908#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
19909#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
19910#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos)
19911#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
19912#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
19913#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos)
19914#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
19915#define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
19916#define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos)
19917#define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
19918#define RCC_APB1LLPENR_CECLPEN_Pos (27U)
19919#define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos)
19920#define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
19921#define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
19922#define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos)
19923#define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
19924#define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
19925#define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos)
19926#define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
19927#define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
19928#define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos)
19929#define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
19930
19931/* Legacy define */
19932#define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
19933#define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
19934#define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
19935/******************** Bit definition for RCC_APB1HLPENR register ******************/
19936#define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
19937#define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos)
19938#define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
19939#define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
19940#define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos)
19941#define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
19942#define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
19943#define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos)
19944#define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
19945#define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
19946#define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos)
19947#define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
19948#define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
19949#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos)
19950#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
19951
19952/******************** Bit definition for RCC_APB2LPENR register ******************/
19953#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
19954#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
19955#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
19956#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
19957#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
19958#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
19959#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
19960#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
19961#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
19962#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
19963#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
19964#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
19965#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
19966#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
19967#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
19968#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
19969#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
19970#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
19971#define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
19972#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)
19973#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
19974#define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
19975#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)
19976#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
19977#define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
19978#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)
19979#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
19980#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
19981#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
19982#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
19983#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
19984#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
19985#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
19986#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
19987#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos)
19988#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
19989#define RCC_APB2LPENR_SAI3LPEN_Pos (24U)
19990#define RCC_APB2LPENR_SAI3LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos)
19991#define RCC_APB2LPENR_SAI3LPEN RCC_APB2LPENR_SAI3LPEN_Msk
19992#define RCC_APB2LPENR_DFSDM1LPEN_Pos (28U)
19993#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos)
19994#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
19995#define RCC_APB2LPENR_HRTIMLPEN_Pos (29U)
19996#define RCC_APB2LPENR_HRTIMLPEN_Msk (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos)
19997#define RCC_APB2LPENR_HRTIMLPEN RCC_APB2LPENR_HRTIMLPEN_Msk
19998
19999/******************** Bit definition for RCC_APB4LPENR register ******************/
20000#define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
20001#define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos)
20002#define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
20003#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
20004#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)
20005#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
20006#define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
20007#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos)
20008#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
20009#define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
20010#define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos)
20011#define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
20012#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
20013#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos)
20014#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
20015#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
20016#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos)
20017#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
20018#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U)
20019#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos)
20020#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk
20021#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U)
20022#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos)
20023#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk
20024#define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
20025#define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos)
20026#define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
20027#define RCC_APB4LPENR_VREFLPEN_Pos (15U)
20028#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos)
20029#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
20030#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
20031#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos)
20032#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
20033#define RCC_APB4LPENR_SAI4LPEN_Pos (21U)
20034#define RCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos)
20035#define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk
20036
20037/******************** Bit definition for RCC_D1CCIPR register ****************/
20038#define RCC_D1CCIPR_DSISRC_Pos (8U)
20039#define RCC_D1CCIPR_DSISRC_Msk (0x1UL << RCC_D1CCIPR_DSISRC_Pos)
20040#define RCC_D1CCIPR_DSISRC RCC_D1CCIPR_DSISRC_Msk
20041
20042/******************** Bit definition for RCC_RSR register *******************/
20043#define RCC_RSR_RMVF_Pos (16U)
20044#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos)
20045#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
20046#define RCC_RSR_C1RSTF_Pos (17U)
20047#define RCC_RSR_C1RSTF_Msk (0x1UL << RCC_RSR_C1RSTF_Pos)
20048#define RCC_RSR_C1RSTF RCC_RSR_C1RSTF_Msk
20049#define RCC_RSR_D1RSTF_Pos (19U)
20050#define RCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos)
20051#define RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk
20052#define RCC_RSR_D2RSTF_Pos (20U)
20053#define RCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos)
20054#define RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk
20055#define RCC_RSR_BORRSTF_Pos (21U)
20056#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos)
20057#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
20058#define RCC_RSR_PINRSTF_Pos (22U)
20059#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos)
20060#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
20061#define RCC_RSR_PORRSTF_Pos (23U)
20062#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos)
20063#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
20064#define RCC_RSR_SFT1RSTF_Pos (24U)
20065#define RCC_RSR_SFT1RSTF_Msk (0x1UL << RCC_RSR_SFT1RSTF_Pos)
20066#define RCC_RSR_SFT1RSTF RCC_RSR_SFT1RSTF_Msk
20067#define RCC_RSR_IWDG1RSTF_Pos (26U)
20068#define RCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos)
20069#define RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk
20070#define RCC_RSR_WWDG1RSTF_Pos (28U)
20071#define RCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos)
20072#define RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk
20073
20074#define RCC_RSR_WWDG2RSTF_Pos (29U)
20075#define RCC_RSR_WWDG2RSTF_Msk (0x1UL << RCC_RSR_WWDG2RSTF_Pos)
20076#define RCC_RSR_WWDG2RSTF RCC_RSR_WWDG2RSTF_Msk
20077#define RCC_RSR_IWDG2RSTF_Pos (27U)
20078#define RCC_RSR_IWDG2RSTF_Msk (0x1UL << RCC_RSR_IWDG2RSTF_Pos)
20079#define RCC_RSR_IWDG2RSTF RCC_RSR_IWDG2RSTF_Msk
20080#define RCC_RSR_SFT2RSTF_Pos (25U)
20081#define RCC_RSR_SFT2RSTF_Msk (0x1UL << RCC_RSR_SFT2RSTF_Pos)
20082#define RCC_RSR_SFT2RSTF RCC_RSR_SFT2RSTF_Msk
20083#define RCC_RSR_C2RSTF_Pos (18U)
20084#define RCC_RSR_C2RSTF_Msk (0x1UL << RCC_RSR_C2RSTF_Pos)
20085#define RCC_RSR_C2RSTF RCC_RSR_C2RSTF_Msk
20086#define RCC_RSR_LPWR1RSTF_Pos (30U)
20087#define RCC_RSR_LPWR1RSTF_Msk (0x1UL << RCC_RSR_LPWR1RSTF_Pos)
20088#define RCC_RSR_LPWR1RSTF RCC_RSR_LPWR1RSTF_Msk
20089#define RCC_RSR_LPWR2RSTF_Pos (31U)
20090#define RCC_RSR_LPWR2RSTF_Msk (0x1UL << RCC_RSR_LPWR2RSTF_Pos)
20091#define RCC_RSR_LPWR2RSTF RCC_RSR_LPWR2RSTF_Msk
20092
20093
20094/******************************************************************************/
20095/* */
20096/* RNG */
20097/* */
20098/******************************************************************************/
20099/******************** Bits definition for RNG_CR register *******************/
20100#define RNG_CR_RNGEN_Pos (2U)
20101#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
20102#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
20103#define RNG_CR_IE_Pos (3U)
20104#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
20105#define RNG_CR_IE RNG_CR_IE_Msk
20106#define RNG_CR_CED_Pos (5U)
20107#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos)
20108#define RNG_CR_CED RNG_CR_CED_Msk
20109
20110/******************** Bits definition for RNG_SR register *******************/
20111#define RNG_SR_DRDY_Pos (0U)
20112#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
20113#define RNG_SR_DRDY RNG_SR_DRDY_Msk
20114#define RNG_SR_CECS_Pos (1U)
20115#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
20116#define RNG_SR_CECS RNG_SR_CECS_Msk
20117#define RNG_SR_SECS_Pos (2U)
20118#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
20119#define RNG_SR_SECS RNG_SR_SECS_Msk
20120#define RNG_SR_CEIS_Pos (5U)
20121#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
20122#define RNG_SR_CEIS RNG_SR_CEIS_Msk
20123#define RNG_SR_SEIS_Pos (6U)
20124#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
20125#define RNG_SR_SEIS RNG_SR_SEIS_Msk
20126
20127/******************************************************************************/
20128/* */
20129/* Real-Time Clock (RTC) */
20130/* */
20131/******************************************************************************/
20132/******************** Bits definition for RTC_TR register *******************/
20133#define RTC_TR_PM_Pos (22U)
20134#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
20135#define RTC_TR_PM RTC_TR_PM_Msk
20136#define RTC_TR_HT_Pos (20U)
20137#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
20138#define RTC_TR_HT RTC_TR_HT_Msk
20139#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
20140#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
20141#define RTC_TR_HU_Pos (16U)
20142#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
20143#define RTC_TR_HU RTC_TR_HU_Msk
20144#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
20145#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
20146#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
20147#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
20148#define RTC_TR_MNT_Pos (12U)
20149#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
20150#define RTC_TR_MNT RTC_TR_MNT_Msk
20151#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
20152#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
20153#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
20154#define RTC_TR_MNU_Pos (8U)
20155#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
20156#define RTC_TR_MNU RTC_TR_MNU_Msk
20157#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
20158#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
20159#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
20160#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
20161#define RTC_TR_ST_Pos (4U)
20162#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
20163#define RTC_TR_ST RTC_TR_ST_Msk
20164#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
20165#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
20166#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
20167#define RTC_TR_SU_Pos (0U)
20168#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
20169#define RTC_TR_SU RTC_TR_SU_Msk
20170#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
20171#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
20172#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
20173#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
20175/******************** Bits definition for RTC_DR register *******************/
20176#define RTC_DR_YT_Pos (20U)
20177#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
20178#define RTC_DR_YT RTC_DR_YT_Msk
20179#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
20180#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
20181#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
20182#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
20183#define RTC_DR_YU_Pos (16U)
20184#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
20185#define RTC_DR_YU RTC_DR_YU_Msk
20186#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
20187#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
20188#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
20189#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
20190#define RTC_DR_WDU_Pos (13U)
20191#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
20192#define RTC_DR_WDU RTC_DR_WDU_Msk
20193#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
20194#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
20195#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
20196#define RTC_DR_MT_Pos (12U)
20197#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
20198#define RTC_DR_MT RTC_DR_MT_Msk
20199#define RTC_DR_MU_Pos (8U)
20200#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
20201#define RTC_DR_MU RTC_DR_MU_Msk
20202#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
20203#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
20204#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
20205#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
20206#define RTC_DR_DT_Pos (4U)
20207#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
20208#define RTC_DR_DT RTC_DR_DT_Msk
20209#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
20210#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
20211#define RTC_DR_DU_Pos (0U)
20212#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
20213#define RTC_DR_DU RTC_DR_DU_Msk
20214#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
20215#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
20216#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
20217#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
20219/******************** Bits definition for RTC_CR register *******************/
20220#define RTC_CR_ITSE_Pos (24U)
20221#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
20222#define RTC_CR_ITSE RTC_CR_ITSE_Msk
20223#define RTC_CR_COE_Pos (23U)
20224#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
20225#define RTC_CR_COE RTC_CR_COE_Msk
20226#define RTC_CR_OSEL_Pos (21U)
20227#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
20228#define RTC_CR_OSEL RTC_CR_OSEL_Msk
20229#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
20230#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
20231#define RTC_CR_POL_Pos (20U)
20232#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
20233#define RTC_CR_POL RTC_CR_POL_Msk
20234#define RTC_CR_COSEL_Pos (19U)
20235#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
20236#define RTC_CR_COSEL RTC_CR_COSEL_Msk
20237#define RTC_CR_BKP_Pos (18U)
20238#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
20239#define RTC_CR_BKP RTC_CR_BKP_Msk
20240#define RTC_CR_SUB1H_Pos (17U)
20241#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
20242#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
20243#define RTC_CR_ADD1H_Pos (16U)
20244#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
20245#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
20246#define RTC_CR_TSIE_Pos (15U)
20247#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
20248#define RTC_CR_TSIE RTC_CR_TSIE_Msk
20249#define RTC_CR_WUTIE_Pos (14U)
20250#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
20251#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
20252#define RTC_CR_ALRBIE_Pos (13U)
20253#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
20254#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
20255#define RTC_CR_ALRAIE_Pos (12U)
20256#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
20257#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
20258#define RTC_CR_TSE_Pos (11U)
20259#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
20260#define RTC_CR_TSE RTC_CR_TSE_Msk
20261#define RTC_CR_WUTE_Pos (10U)
20262#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
20263#define RTC_CR_WUTE RTC_CR_WUTE_Msk
20264#define RTC_CR_ALRBE_Pos (9U)
20265#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
20266#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
20267#define RTC_CR_ALRAE_Pos (8U)
20268#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
20269#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
20270#define RTC_CR_FMT_Pos (6U)
20271#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
20272#define RTC_CR_FMT RTC_CR_FMT_Msk
20273#define RTC_CR_BYPSHAD_Pos (5U)
20274#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
20275#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
20276#define RTC_CR_REFCKON_Pos (4U)
20277#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
20278#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
20279#define RTC_CR_TSEDGE_Pos (3U)
20280#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
20281#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
20282#define RTC_CR_WUCKSEL_Pos (0U)
20283#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
20284#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
20285#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
20286#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
20287#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
20289/******************** Bits definition for RTC_ISR register ******************/
20290#define RTC_ISR_ITSF_Pos (17U)
20291#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
20292#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
20293#define RTC_ISR_RECALPF_Pos (16U)
20294#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
20295#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
20296#define RTC_ISR_TAMP3F_Pos (15U)
20297#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
20298#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
20299#define RTC_ISR_TAMP2F_Pos (14U)
20300#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
20301#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
20302#define RTC_ISR_TAMP1F_Pos (13U)
20303#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
20304#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
20305#define RTC_ISR_TSOVF_Pos (12U)
20306#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
20307#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
20308#define RTC_ISR_TSF_Pos (11U)
20309#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
20310#define RTC_ISR_TSF RTC_ISR_TSF_Msk
20311#define RTC_ISR_WUTF_Pos (10U)
20312#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
20313#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
20314#define RTC_ISR_ALRBF_Pos (9U)
20315#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
20316#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
20317#define RTC_ISR_ALRAF_Pos (8U)
20318#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
20319#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
20320#define RTC_ISR_INIT_Pos (7U)
20321#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
20322#define RTC_ISR_INIT RTC_ISR_INIT_Msk
20323#define RTC_ISR_INITF_Pos (6U)
20324#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
20325#define RTC_ISR_INITF RTC_ISR_INITF_Msk
20326#define RTC_ISR_RSF_Pos (5U)
20327#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
20328#define RTC_ISR_RSF RTC_ISR_RSF_Msk
20329#define RTC_ISR_INITS_Pos (4U)
20330#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
20331#define RTC_ISR_INITS RTC_ISR_INITS_Msk
20332#define RTC_ISR_SHPF_Pos (3U)
20333#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
20334#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
20335#define RTC_ISR_WUTWF_Pos (2U)
20336#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
20337#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
20338#define RTC_ISR_ALRBWF_Pos (1U)
20339#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
20340#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
20341#define RTC_ISR_ALRAWF_Pos (0U)
20342#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
20343#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
20344
20345/******************** Bits definition for RTC_PRER register *****************/
20346#define RTC_PRER_PREDIV_A_Pos (16U)
20347#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
20348#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
20349#define RTC_PRER_PREDIV_S_Pos (0U)
20350#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
20351#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
20352
20353/******************** Bits definition for RTC_WUTR register *****************/
20354#define RTC_WUTR_WUT_Pos (0U)
20355#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
20356#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
20357
20358/******************** Bits definition for RTC_ALRMAR register ***************/
20359#define RTC_ALRMAR_MSK4_Pos (31U)
20360#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
20361#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
20362#define RTC_ALRMAR_WDSEL_Pos (30U)
20363#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
20364#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
20365#define RTC_ALRMAR_DT_Pos (28U)
20366#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
20367#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
20368#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
20369#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
20370#define RTC_ALRMAR_DU_Pos (24U)
20371#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
20372#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
20373#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
20374#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
20375#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
20376#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
20377#define RTC_ALRMAR_MSK3_Pos (23U)
20378#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
20379#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
20380#define RTC_ALRMAR_PM_Pos (22U)
20381#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
20382#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
20383#define RTC_ALRMAR_HT_Pos (20U)
20384#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
20385#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
20386#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
20387#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
20388#define RTC_ALRMAR_HU_Pos (16U)
20389#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
20390#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
20391#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
20392#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
20393#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
20394#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
20395#define RTC_ALRMAR_MSK2_Pos (15U)
20396#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
20397#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
20398#define RTC_ALRMAR_MNT_Pos (12U)
20399#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
20400#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
20401#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
20402#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
20403#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
20404#define RTC_ALRMAR_MNU_Pos (8U)
20405#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
20406#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
20407#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
20408#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
20409#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
20410#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
20411#define RTC_ALRMAR_MSK1_Pos (7U)
20412#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
20413#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
20414#define RTC_ALRMAR_ST_Pos (4U)
20415#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
20416#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
20417#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
20418#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
20419#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
20420#define RTC_ALRMAR_SU_Pos (0U)
20421#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
20422#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
20423#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
20424#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
20425#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
20426#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
20428/******************** Bits definition for RTC_ALRMBR register ***************/
20429#define RTC_ALRMBR_MSK4_Pos (31U)
20430#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
20431#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
20432#define RTC_ALRMBR_WDSEL_Pos (30U)
20433#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
20434#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
20435#define RTC_ALRMBR_DT_Pos (28U)
20436#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
20437#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
20438#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
20439#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
20440#define RTC_ALRMBR_DU_Pos (24U)
20441#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
20442#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
20443#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
20444#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
20445#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
20446#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
20447#define RTC_ALRMBR_MSK3_Pos (23U)
20448#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
20449#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
20450#define RTC_ALRMBR_PM_Pos (22U)
20451#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
20452#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
20453#define RTC_ALRMBR_HT_Pos (20U)
20454#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
20455#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
20456#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
20457#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
20458#define RTC_ALRMBR_HU_Pos (16U)
20459#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
20460#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
20461#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
20462#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
20463#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
20464#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
20465#define RTC_ALRMBR_MSK2_Pos (15U)
20466#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
20467#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
20468#define RTC_ALRMBR_MNT_Pos (12U)
20469#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
20470#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
20471#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
20472#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
20473#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
20474#define RTC_ALRMBR_MNU_Pos (8U)
20475#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
20476#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
20477#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
20478#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
20479#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
20480#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
20481#define RTC_ALRMBR_MSK1_Pos (7U)
20482#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
20483#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
20484#define RTC_ALRMBR_ST_Pos (4U)
20485#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
20486#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
20487#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
20488#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
20489#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
20490#define RTC_ALRMBR_SU_Pos (0U)
20491#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
20492#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
20493#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
20494#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
20495#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
20496#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
20498/******************** Bits definition for RTC_WPR register ******************/
20499#define RTC_WPR_KEY_Pos (0U)
20500#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
20501#define RTC_WPR_KEY RTC_WPR_KEY_Msk
20502
20503/******************** Bits definition for RTC_SSR register ******************/
20504#define RTC_SSR_SS_Pos (0U)
20505#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
20506#define RTC_SSR_SS RTC_SSR_SS_Msk
20507
20508/******************** Bits definition for RTC_SHIFTR register ***************/
20509#define RTC_SHIFTR_SUBFS_Pos (0U)
20510#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
20511#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
20512#define RTC_SHIFTR_ADD1S_Pos (31U)
20513#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
20514#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
20515
20516/******************** Bits definition for RTC_TSTR register *****************/
20517#define RTC_TSTR_PM_Pos (22U)
20518#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
20519#define RTC_TSTR_PM RTC_TSTR_PM_Msk
20520#define RTC_TSTR_HT_Pos (20U)
20521#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
20522#define RTC_TSTR_HT RTC_TSTR_HT_Msk
20523#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
20524#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
20525#define RTC_TSTR_HU_Pos (16U)
20526#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
20527#define RTC_TSTR_HU RTC_TSTR_HU_Msk
20528#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
20529#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
20530#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
20531#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
20532#define RTC_TSTR_MNT_Pos (12U)
20533#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
20534#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
20535#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
20536#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
20537#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
20538#define RTC_TSTR_MNU_Pos (8U)
20539#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
20540#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
20541#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
20542#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
20543#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
20544#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
20545#define RTC_TSTR_ST_Pos (4U)
20546#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
20547#define RTC_TSTR_ST RTC_TSTR_ST_Msk
20548#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
20549#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
20550#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
20551#define RTC_TSTR_SU_Pos (0U)
20552#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
20553#define RTC_TSTR_SU RTC_TSTR_SU_Msk
20554#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
20555#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
20556#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
20557#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
20559/******************** Bits definition for RTC_TSDR register *****************/
20560#define RTC_TSDR_WDU_Pos (13U)
20561#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
20562#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
20563#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
20564#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
20565#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
20566#define RTC_TSDR_MT_Pos (12U)
20567#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
20568#define RTC_TSDR_MT RTC_TSDR_MT_Msk
20569#define RTC_TSDR_MU_Pos (8U)
20570#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
20571#define RTC_TSDR_MU RTC_TSDR_MU_Msk
20572#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
20573#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
20574#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
20575#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
20576#define RTC_TSDR_DT_Pos (4U)
20577#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
20578#define RTC_TSDR_DT RTC_TSDR_DT_Msk
20579#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
20580#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
20581#define RTC_TSDR_DU_Pos (0U)
20582#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
20583#define RTC_TSDR_DU RTC_TSDR_DU_Msk
20584#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
20585#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
20586#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
20587#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
20589/******************** Bits definition for RTC_TSSSR register ****************/
20590#define RTC_TSSSR_SS_Pos (0U)
20591#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
20592#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
20593
20594/******************** Bits definition for RTC_CALR register *****************/
20595#define RTC_CALR_CALP_Pos (15U)
20596#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
20597#define RTC_CALR_CALP RTC_CALR_CALP_Msk
20598#define RTC_CALR_CALW8_Pos (14U)
20599#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
20600#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
20601#define RTC_CALR_CALW16_Pos (13U)
20602#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
20603#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
20604#define RTC_CALR_CALM_Pos (0U)
20605#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
20606#define RTC_CALR_CALM RTC_CALR_CALM_Msk
20607#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
20608#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
20609#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
20610#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
20611#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
20612#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
20613#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
20614#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
20615#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
20617/******************** Bits definition for RTC_TAMPCR register ***************/
20618#define RTC_TAMPCR_TAMP3MF_Pos (24U)
20619#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
20620#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
20621#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
20622#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
20623#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
20624#define RTC_TAMPCR_TAMP3IE_Pos (22U)
20625#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
20626#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
20627#define RTC_TAMPCR_TAMP2MF_Pos (21U)
20628#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
20629#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
20630#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
20631#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
20632#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
20633#define RTC_TAMPCR_TAMP2IE_Pos (19U)
20634#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
20635#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
20636#define RTC_TAMPCR_TAMP1MF_Pos (18U)
20637#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
20638#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
20639#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
20640#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
20641#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
20642#define RTC_TAMPCR_TAMP1IE_Pos (16U)
20643#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
20644#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
20645#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
20646#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
20647#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
20648#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
20649#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
20650#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
20651#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
20652#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
20653#define RTC_TAMPCR_TAMPFLT_Pos (11U)
20654#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
20655#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
20656#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
20657#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
20658#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
20659#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
20660#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
20661#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
20662#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
20663#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
20664#define RTC_TAMPCR_TAMPTS_Pos (7U)
20665#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
20666#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
20667#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
20668#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
20669#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
20670#define RTC_TAMPCR_TAMP3E_Pos (5U)
20671#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
20672#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
20673#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
20674#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
20675#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
20676#define RTC_TAMPCR_TAMP2E_Pos (3U)
20677#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
20678#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
20679#define RTC_TAMPCR_TAMPIE_Pos (2U)
20680#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
20681#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
20682#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
20683#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
20684#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
20685#define RTC_TAMPCR_TAMP1E_Pos (0U)
20686#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
20687#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
20688
20689/******************** Bits definition for RTC_ALRMASSR register *************/
20690#define RTC_ALRMASSR_MASKSS_Pos (24U)
20691#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
20692#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
20693#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
20694#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
20695#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
20696#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
20697#define RTC_ALRMASSR_SS_Pos (0U)
20698#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
20699#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
20700
20701/******************** Bits definition for RTC_ALRMBSSR register *************/
20702#define RTC_ALRMBSSR_MASKSS_Pos (24U)
20703#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
20704#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
20705#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
20706#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
20707#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
20708#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
20709#define RTC_ALRMBSSR_SS_Pos (0U)
20710#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
20711#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
20712
20713/******************** Bits definition for RTC_OR register *******************/
20714#define RTC_OR_OUT_RMP_Pos (1U)
20715#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos)
20716#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
20717#define RTC_OR_ALARMOUTTYPE_Pos (0U)
20718#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
20719#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
20720
20721/******************** Bits definition for RTC_BKP0R register ****************/
20722#define RTC_BKP0R_Pos (0U)
20723#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
20724#define RTC_BKP0R RTC_BKP0R_Msk
20725
20726/******************** Bits definition for RTC_BKP1R register ****************/
20727#define RTC_BKP1R_Pos (0U)
20728#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
20729#define RTC_BKP1R RTC_BKP1R_Msk
20730
20731/******************** Bits definition for RTC_BKP2R register ****************/
20732#define RTC_BKP2R_Pos (0U)
20733#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
20734#define RTC_BKP2R RTC_BKP2R_Msk
20735
20736/******************** Bits definition for RTC_BKP3R register ****************/
20737#define RTC_BKP3R_Pos (0U)
20738#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
20739#define RTC_BKP3R RTC_BKP3R_Msk
20740
20741/******************** Bits definition for RTC_BKP4R register ****************/
20742#define RTC_BKP4R_Pos (0U)
20743#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
20744#define RTC_BKP4R RTC_BKP4R_Msk
20745
20746/******************** Bits definition for RTC_BKP5R register ****************/
20747#define RTC_BKP5R_Pos (0U)
20748#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
20749#define RTC_BKP5R RTC_BKP5R_Msk
20750
20751/******************** Bits definition for RTC_BKP6R register ****************/
20752#define RTC_BKP6R_Pos (0U)
20753#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
20754#define RTC_BKP6R RTC_BKP6R_Msk
20755
20756/******************** Bits definition for RTC_BKP7R register ****************/
20757#define RTC_BKP7R_Pos (0U)
20758#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
20759#define RTC_BKP7R RTC_BKP7R_Msk
20760
20761/******************** Bits definition for RTC_BKP8R register ****************/
20762#define RTC_BKP8R_Pos (0U)
20763#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
20764#define RTC_BKP8R RTC_BKP8R_Msk
20765
20766/******************** Bits definition for RTC_BKP9R register ****************/
20767#define RTC_BKP9R_Pos (0U)
20768#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
20769#define RTC_BKP9R RTC_BKP9R_Msk
20770
20771/******************** Bits definition for RTC_BKP10R register ***************/
20772#define RTC_BKP10R_Pos (0U)
20773#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
20774#define RTC_BKP10R RTC_BKP10R_Msk
20775
20776/******************** Bits definition for RTC_BKP11R register ***************/
20777#define RTC_BKP11R_Pos (0U)
20778#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
20779#define RTC_BKP11R RTC_BKP11R_Msk
20780
20781/******************** Bits definition for RTC_BKP12R register ***************/
20782#define RTC_BKP12R_Pos (0U)
20783#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
20784#define RTC_BKP12R RTC_BKP12R_Msk
20785
20786/******************** Bits definition for RTC_BKP13R register ***************/
20787#define RTC_BKP13R_Pos (0U)
20788#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
20789#define RTC_BKP13R RTC_BKP13R_Msk
20790
20791/******************** Bits definition for RTC_BKP14R register ***************/
20792#define RTC_BKP14R_Pos (0U)
20793#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
20794#define RTC_BKP14R RTC_BKP14R_Msk
20795
20796/******************** Bits definition for RTC_BKP15R register ***************/
20797#define RTC_BKP15R_Pos (0U)
20798#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
20799#define RTC_BKP15R RTC_BKP15R_Msk
20800
20801/******************** Bits definition for RTC_BKP16R register ***************/
20802#define RTC_BKP16R_Pos (0U)
20803#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
20804#define RTC_BKP16R RTC_BKP16R_Msk
20805
20806/******************** Bits definition for RTC_BKP17R register ***************/
20807#define RTC_BKP17R_Pos (0U)
20808#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
20809#define RTC_BKP17R RTC_BKP17R_Msk
20810
20811/******************** Bits definition for RTC_BKP18R register ***************/
20812#define RTC_BKP18R_Pos (0U)
20813#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
20814#define RTC_BKP18R RTC_BKP18R_Msk
20815
20816/******************** Bits definition for RTC_BKP19R register ***************/
20817#define RTC_BKP19R_Pos (0U)
20818#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
20819#define RTC_BKP19R RTC_BKP19R_Msk
20820
20821/******************** Bits definition for RTC_BKP20R register ***************/
20822#define RTC_BKP20R_Pos (0U)
20823#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
20824#define RTC_BKP20R RTC_BKP20R_Msk
20825
20826/******************** Bits definition for RTC_BKP21R register ***************/
20827#define RTC_BKP21R_Pos (0U)
20828#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
20829#define RTC_BKP21R RTC_BKP21R_Msk
20830
20831/******************** Bits definition for RTC_BKP22R register ***************/
20832#define RTC_BKP22R_Pos (0U)
20833#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
20834#define RTC_BKP22R RTC_BKP22R_Msk
20835
20836/******************** Bits definition for RTC_BKP23R register ***************/
20837#define RTC_BKP23R_Pos (0U)
20838#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
20839#define RTC_BKP23R RTC_BKP23R_Msk
20840
20841/******************** Bits definition for RTC_BKP24R register ***************/
20842#define RTC_BKP24R_Pos (0U)
20843#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
20844#define RTC_BKP24R RTC_BKP24R_Msk
20845
20846/******************** Bits definition for RTC_BKP25R register ***************/
20847#define RTC_BKP25R_Pos (0U)
20848#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
20849#define RTC_BKP25R RTC_BKP25R_Msk
20850
20851/******************** Bits definition for RTC_BKP26R register ***************/
20852#define RTC_BKP26R_Pos (0U)
20853#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
20854#define RTC_BKP26R RTC_BKP26R_Msk
20855
20856/******************** Bits definition for RTC_BKP27R register ***************/
20857#define RTC_BKP27R_Pos (0U)
20858#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
20859#define RTC_BKP27R RTC_BKP27R_Msk
20860
20861/******************** Bits definition for RTC_BKP28R register ***************/
20862#define RTC_BKP28R_Pos (0U)
20863#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
20864#define RTC_BKP28R RTC_BKP28R_Msk
20865
20866/******************** Bits definition for RTC_BKP29R register ***************/
20867#define RTC_BKP29R_Pos (0U)
20868#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
20869#define RTC_BKP29R RTC_BKP29R_Msk
20870
20871/******************** Bits definition for RTC_BKP30R register ***************/
20872#define RTC_BKP30R_Pos (0U)
20873#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
20874#define RTC_BKP30R RTC_BKP30R_Msk
20875
20876/******************** Bits definition for RTC_BKP31R register ***************/
20877#define RTC_BKP31R_Pos (0U)
20878#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
20879#define RTC_BKP31R RTC_BKP31R_Msk
20880
20881/******************** Number of backup registers ******************************/
20882#define RTC_BKP_NUMBER_Pos (5U)
20883#define RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos)
20884#define RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk
20885
20886/******************************************************************************/
20887/* */
20888/* SPDIF-RX Interface */
20889/* */
20890/******************************************************************************/
20891/******************** Bit definition for SPDIF_CR register ******************/
20892#define SPDIFRX_CR_SPDIFEN_Pos (0U)
20893#define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)
20894#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk
20895#define SPDIFRX_CR_RXDMAEN_Pos (2U)
20896#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)
20897#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk
20898#define SPDIFRX_CR_RXSTEO_Pos (3U)
20899#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos)
20900#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk
20901#define SPDIFRX_CR_DRFMT_Pos (4U)
20902#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos)
20903#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk
20904#define SPDIFRX_CR_PMSK_Pos (6U)
20905#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos)
20906#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk
20907#define SPDIFRX_CR_VMSK_Pos (7U)
20908#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos)
20909#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk
20910#define SPDIFRX_CR_CUMSK_Pos (8U)
20911#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos)
20912#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk
20913#define SPDIFRX_CR_PTMSK_Pos (9U)
20914#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos)
20915#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk
20916#define SPDIFRX_CR_CBDMAEN_Pos (10U)
20917#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)
20918#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk
20919#define SPDIFRX_CR_CHSEL_Pos (11U)
20920#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos)
20921#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk
20922#define SPDIFRX_CR_NBTR_Pos (12U)
20923#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos)
20924#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk
20925#define SPDIFRX_CR_WFA_Pos (14U)
20926#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos)
20927#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk
20928#define SPDIFRX_CR_INSEL_Pos (16U)
20929#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos)
20930#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk
20931#define SPDIFRX_CR_CKSEN_Pos (20U)
20932#define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos)
20933#define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk
20934#define SPDIFRX_CR_CKSBKPEN_Pos (21U)
20935#define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)
20936#define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk
20938/******************* Bit definition for SPDIFRX_IMR register *******************/
20939#define SPDIFRX_IMR_RXNEIE_Pos (0U)
20940#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)
20941#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk
20942#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
20943#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)
20944#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk
20945#define SPDIFRX_IMR_PERRIE_Pos (2U)
20946#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos)
20947#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk
20948#define SPDIFRX_IMR_OVRIE_Pos (3U)
20949#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos)
20950#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk
20951#define SPDIFRX_IMR_SBLKIE_Pos (4U)
20952#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)
20953#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk
20954#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
20955#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)
20956#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk
20957#define SPDIFRX_IMR_IFEIE_Pos (6U)
20958#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos)
20959#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk
20961/******************* Bit definition for SPDIFRX_SR register *******************/
20962#define SPDIFRX_SR_RXNE_Pos (0U)
20963#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos)
20964#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk
20965#define SPDIFRX_SR_CSRNE_Pos (1U)
20966#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos)
20967#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk
20968#define SPDIFRX_SR_PERR_Pos (2U)
20969#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos)
20970#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk
20971#define SPDIFRX_SR_OVR_Pos (3U)
20972#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos)
20973#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk
20974#define SPDIFRX_SR_SBD_Pos (4U)
20975#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos)
20976#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk
20977#define SPDIFRX_SR_SYNCD_Pos (5U)
20978#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos)
20979#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk
20980#define SPDIFRX_SR_FERR_Pos (6U)
20981#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos)
20982#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk
20983#define SPDIFRX_SR_SERR_Pos (7U)
20984#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos)
20985#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk
20986#define SPDIFRX_SR_TERR_Pos (8U)
20987#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos)
20988#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk
20989#define SPDIFRX_SR_WIDTH5_Pos (16U)
20990#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)
20991#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk
20993/******************* Bit definition for SPDIFRX_IFCR register *******************/
20994#define SPDIFRX_IFCR_PERRCF_Pos (2U)
20995#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)
20996#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk
20997#define SPDIFRX_IFCR_OVRCF_Pos (3U)
20998#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)
20999#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk
21000#define SPDIFRX_IFCR_SBDCF_Pos (4U)
21001#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)
21002#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk
21003#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
21004#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)
21005#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk
21007/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
21008#define SPDIFRX_DR0_DR_Pos (0U)
21009#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)
21010#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk
21011#define SPDIFRX_DR0_PE_Pos (24U)
21012#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos)
21013#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk
21014#define SPDIFRX_DR0_V_Pos (25U)
21015#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos)
21016#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk
21017#define SPDIFRX_DR0_U_Pos (26U)
21018#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos)
21019#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk
21020#define SPDIFRX_DR0_C_Pos (27U)
21021#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos)
21022#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk
21023#define SPDIFRX_DR0_PT_Pos (28U)
21024#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos)
21025#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk
21027/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
21028#define SPDIFRX_DR1_DR_Pos (8U)
21029#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)
21030#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk
21031#define SPDIFRX_DR1_PT_Pos (4U)
21032#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos)
21033#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk
21034#define SPDIFRX_DR1_C_Pos (3U)
21035#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos)
21036#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk
21037#define SPDIFRX_DR1_U_Pos (2U)
21038#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos)
21039#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk
21040#define SPDIFRX_DR1_V_Pos (1U)
21041#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos)
21042#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk
21043#define SPDIFRX_DR1_PE_Pos (0U)
21044#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos)
21045#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk
21047/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
21048#define SPDIFRX_DR1_DRNL1_Pos (16U)
21049#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)
21050#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk
21051#define SPDIFRX_DR1_DRNL2_Pos (0U)
21052#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)
21053#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk
21055/******************* Bit definition for SPDIFRX_CSR register *******************/
21056#define SPDIFRX_CSR_USR_Pos (0U)
21057#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos)
21058#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk
21059#define SPDIFRX_CSR_CS_Pos (16U)
21060#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos)
21061#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk
21062#define SPDIFRX_CSR_SOB_Pos (24U)
21063#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos)
21064#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk
21066/******************* Bit definition for SPDIFRX_DIR register *******************/
21067#define SPDIFRX_DIR_THI_Pos (0U)
21068#define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos)
21069#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk
21070#define SPDIFRX_DIR_TLO_Pos (16U)
21071#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)
21072#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk
21074/******************* Bit definition for SPDIFRX_VERR register *******************/
21075#define SPDIFRX_VERR_MINREV_Pos (0U)
21076#define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos)
21077#define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk
21078#define SPDIFRX_VERR_MAJREV_Pos (4U)
21079#define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos)
21080#define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk
21082/******************* Bit definition for SPDIFRX_IDR register *******************/
21083#define SPDIFRX_IDR_ID_Pos (0U)
21084#define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)
21085#define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk
21087/******************* Bit definition for SPDIFRX_SIDR register *******************/
21088#define SPDIFRX_SIDR_SID_Pos (0U)
21089#define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)
21090#define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk
21092/******************************************************************************/
21093/* */
21094/* Serial Audio Interface */
21095/* */
21096/******************************************************************************/
21097/******************************* SAI VERSION ********************************/
21098#define SAI_VER_V2_X
21099
21100/******************** Bit definition for SAI_GCR register *******************/
21101#define SAI_GCR_SYNCIN_Pos (0U)
21102#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
21103#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
21104#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
21105#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
21107#define SAI_GCR_SYNCOUT_Pos (4U)
21108#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
21109#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
21110#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
21111#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
21113/******************* Bit definition for SAI_xCR1 register *******************/
21114#define SAI_xCR1_MODE_Pos (0U)
21115#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
21116#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
21117#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
21118#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
21120#define SAI_xCR1_PRTCFG_Pos (2U)
21121#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
21122#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
21123#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
21124#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
21126#define SAI_xCR1_DS_Pos (5U)
21127#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
21128#define SAI_xCR1_DS SAI_xCR1_DS_Msk
21129#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
21130#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
21131#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
21133#define SAI_xCR1_LSBFIRST_Pos (8U)
21134#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
21135#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
21136#define SAI_xCR1_CKSTR_Pos (9U)
21137#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
21138#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
21140#define SAI_xCR1_SYNCEN_Pos (10U)
21141#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
21142#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
21143#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
21144#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
21146#define SAI_xCR1_MONO_Pos (12U)
21147#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
21148#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
21149#define SAI_xCR1_OUTDRIV_Pos (13U)
21150#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
21151#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
21152#define SAI_xCR1_SAIEN_Pos (16U)
21153#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
21154#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
21155#define SAI_xCR1_DMAEN_Pos (17U)
21156#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
21157#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
21158#define SAI_xCR1_NODIV_Pos (19U)
21159#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
21160#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
21162#define SAI_xCR1_MCKDIV_Pos (20U)
21163#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos)
21164#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
21165#define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos)
21166#define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos)
21167#define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos)
21168#define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos)
21169#define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos)
21170#define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos)
21172#define SAI_xCR1_MCKEN_Pos (27U)
21173#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos)
21174#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk
21176#define SAI_xCR1_OSR_Pos (26U)
21177#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos)
21178#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk
21180/* Legacy define */
21181#define SAI_xCR1_NOMCK SAI_xCR1_NODIV
21182
21183/******************* Bit definition for SAI_xCR2 register *******************/
21184#define SAI_xCR2_FTH_Pos (0U)
21185#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
21186#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
21187#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
21188#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
21189#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
21191#define SAI_xCR2_FFLUSH_Pos (3U)
21192#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
21193#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
21194#define SAI_xCR2_TRIS_Pos (4U)
21195#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
21196#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
21197#define SAI_xCR2_MUTE_Pos (5U)
21198#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
21199#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
21200#define SAI_xCR2_MUTEVAL_Pos (6U)
21201#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
21202#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
21204#define SAI_xCR2_MUTECNT_Pos (7U)
21205#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
21206#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
21207#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
21208#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
21209#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
21210#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
21211#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
21212#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
21214#define SAI_xCR2_CPL_Pos (13U)
21215#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
21216#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
21218#define SAI_xCR2_COMP_Pos (14U)
21219#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
21220#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
21221#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
21222#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
21224/****************** Bit definition for SAI_xFRCR register *******************/
21225#define SAI_xFRCR_FRL_Pos (0U)
21226#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
21227#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
21228#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
21229#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
21230#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
21231#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
21232#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
21233#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
21234#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
21235#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
21237#define SAI_xFRCR_FSALL_Pos (8U)
21238#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
21239#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
21240#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
21241#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
21242#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
21243#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
21244#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
21245#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
21246#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
21248#define SAI_xFRCR_FSDEF_Pos (16U)
21249#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
21250#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
21251#define SAI_xFRCR_FSPOL_Pos (17U)
21252#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
21253#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
21254#define SAI_xFRCR_FSOFF_Pos (18U)
21255#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
21256#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
21258/* Legacy define */
21259#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
21260
21261/****************** Bit definition for SAI_xSLOTR register *******************/
21262#define SAI_xSLOTR_FBOFF_Pos (0U)
21263#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
21264#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
21265#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
21266#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
21267#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
21268#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
21269#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
21271#define SAI_xSLOTR_SLOTSZ_Pos (6U)
21272#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
21273#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
21274#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
21275#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
21277#define SAI_xSLOTR_NBSLOT_Pos (8U)
21278#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
21279#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
21280#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
21281#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
21282#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
21283#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
21285#define SAI_xSLOTR_SLOTEN_Pos (16U)
21286#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
21287#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
21289/******************* Bit definition for SAI_xIMR register *******************/
21290#define SAI_xIMR_OVRUDRIE_Pos (0U)
21291#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
21292#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
21293#define SAI_xIMR_MUTEDETIE_Pos (1U)
21294#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
21295#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
21296#define SAI_xIMR_WCKCFGIE_Pos (2U)
21297#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
21298#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
21299#define SAI_xIMR_FREQIE_Pos (3U)
21300#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
21301#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
21302#define SAI_xIMR_CNRDYIE_Pos (4U)
21303#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
21304#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
21305#define SAI_xIMR_AFSDETIE_Pos (5U)
21306#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
21307#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
21308#define SAI_xIMR_LFSDETIE_Pos (6U)
21309#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
21310#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
21312/******************** Bit definition for SAI_xSR register *******************/
21313#define SAI_xSR_OVRUDR_Pos (0U)
21314#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
21315#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
21316#define SAI_xSR_MUTEDET_Pos (1U)
21317#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
21318#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
21319#define SAI_xSR_WCKCFG_Pos (2U)
21320#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
21321#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
21322#define SAI_xSR_FREQ_Pos (3U)
21323#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
21324#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
21325#define SAI_xSR_CNRDY_Pos (4U)
21326#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
21327#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
21328#define SAI_xSR_AFSDET_Pos (5U)
21329#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
21330#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
21331#define SAI_xSR_LFSDET_Pos (6U)
21332#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
21333#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
21335#define SAI_xSR_FLVL_Pos (16U)
21336#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
21337#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
21338#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
21339#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
21340#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
21342/****************** Bit definition for SAI_xCLRFR register ******************/
21343#define SAI_xCLRFR_COVRUDR_Pos (0U)
21344#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
21345#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
21346#define SAI_xCLRFR_CMUTEDET_Pos (1U)
21347#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
21348#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
21349#define SAI_xCLRFR_CWCKCFG_Pos (2U)
21350#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
21351#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
21352#define SAI_xCLRFR_CFREQ_Pos (3U)
21353#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
21354#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
21355#define SAI_xCLRFR_CCNRDY_Pos (4U)
21356#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
21357#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
21358#define SAI_xCLRFR_CAFSDET_Pos (5U)
21359#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
21360#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
21361#define SAI_xCLRFR_CLFSDET_Pos (6U)
21362#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
21363#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
21365/****************** Bit definition for SAI_xDR register *********************/
21366#define SAI_xDR_DATA_Pos (0U)
21367#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
21368#define SAI_xDR_DATA SAI_xDR_DATA_Msk
21369
21370/******************* Bit definition for SAI_PDMCR register ******************/
21371#define SAI_PDMCR_PDMEN_Pos (0U)
21372#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos)
21373#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk
21375#define SAI_PDMCR_MICNBR_Pos (4U)
21376#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos)
21377#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk
21378#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos)
21379#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos)
21381#define SAI_PDMCR_CKEN1_Pos (8U)
21382#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos)
21383#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk
21384#define SAI_PDMCR_CKEN2_Pos (9U)
21385#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos)
21386#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk
21387#define SAI_PDMCR_CKEN3_Pos (10U)
21388#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos)
21389#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk
21390#define SAI_PDMCR_CKEN4_Pos (11U)
21391#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos)
21392#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk
21394/****************** Bit definition for SAI_PDMDLY register ******************/
21395#define SAI_PDMDLY_DLYM1L_Pos (0U)
21396#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos)
21397#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk
21398#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)
21399#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)
21400#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)
21402#define SAI_PDMDLY_DLYM1R_Pos (4U)
21403#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos)
21404#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk
21405#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)
21406#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)
21407#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)
21409#define SAI_PDMDLY_DLYM2L_Pos (8U)
21410#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos)
21411#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk
21412#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)
21413#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)
21414#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)
21416#define SAI_PDMDLY_DLYM2R_Pos (12U)
21417#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos)
21418#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk
21419#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)
21420#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)
21421#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)
21423#define SAI_PDMDLY_DLYM3L_Pos (16U)
21424#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos)
21425#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk
21426#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)
21427#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)
21428#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)
21430#define SAI_PDMDLY_DLYM3R_Pos (20U)
21431#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos)
21432#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk
21433#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)
21434#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)
21435#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)
21437#define SAI_PDMDLY_DLYM4L_Pos (24U)
21438#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos)
21439#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk
21440#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)
21441#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)
21442#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)
21444#define SAI_PDMDLY_DLYM4R_Pos (28U)
21445#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos)
21446#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk
21447#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)
21448#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)
21449#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)
21451/******************************************************************************/
21452/* */
21453/* SDMMC Interface */
21454/* */
21455/******************************************************************************/
21456/****************** Bit definition for SDMMC_POWER register ******************/
21457#define SDMMC_POWER_PWRCTRL_Pos (0U)
21458#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
21459#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
21460#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
21461#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
21462#define SDMMC_POWER_VSWITCH_Pos (2U)
21463#define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos)
21464#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk
21465#define SDMMC_POWER_VSWITCHEN_Pos (3U)
21466#define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)
21467#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk
21468#define SDMMC_POWER_DIRPOL_Pos (4U)
21469#define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos)
21470#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk
21472/****************** Bit definition for SDMMC_CLKCR register ******************/
21473#define SDMMC_CLKCR_CLKDIV_Pos (0U)
21474#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)
21475#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
21476#define SDMMC_CLKCR_PWRSAV_Pos (12U)
21477#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
21478#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
21480#define SDMMC_CLKCR_WIDBUS_Pos (14U)
21481#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
21482#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
21483#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
21484#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
21486#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
21487#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
21488#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
21489#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
21490#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
21491#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
21492#define SDMMC_CLKCR_DDR_Pos (18U)
21493#define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos)
21494#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk
21495#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
21496#define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)
21497#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk
21498#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
21499#define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)
21500#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk
21501#define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)
21502#define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)
21504/******************* Bit definition for SDMMC_ARG register *******************/
21505#define SDMMC_ARG_CMDARG_Pos (0U)
21506#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
21507#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
21509/******************* Bit definition for SDMMC_CMD register *******************/
21510#define SDMMC_CMD_CMDINDEX_Pos (0U)
21511#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
21512#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
21513#define SDMMC_CMD_CMDTRANS_Pos (6U)
21514#define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos)
21515#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk
21516#define SDMMC_CMD_CMDSTOP_Pos (7U)
21517#define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos)
21518#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk
21520#define SDMMC_CMD_WAITRESP_Pos (8U)
21521#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
21522#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
21523#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
21524#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
21526#define SDMMC_CMD_WAITINT_Pos (10U)
21527#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
21528#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
21529#define SDMMC_CMD_WAITPEND_Pos (11U)
21530#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
21531#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
21532#define SDMMC_CMD_CPSMEN_Pos (12U)
21533#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
21534#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
21535#define SDMMC_CMD_DTHOLD_Pos (13U)
21536#define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos)
21537#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk
21538#define SDMMC_CMD_BOOTMODE_Pos (14U)
21539#define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos)
21540#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk
21541#define SDMMC_CMD_BOOTEN_Pos (15U)
21542#define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos)
21543#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk
21544#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
21545#define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)
21546#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk
21548/***************** Bit definition for SDMMC_RESPCMD register *****************/
21549#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
21550#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
21551#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
21553/****************** Bit definition for SDMMC_RESP0 register ******************/
21554#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
21555#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos)
21556#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk
21558/****************** Bit definition for SDMMC_RESP1 register ******************/
21559#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
21560#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
21561#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
21563/****************** Bit definition for SDMMC_RESP2 register ******************/
21564#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
21565#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
21566#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
21568/****************** Bit definition for SDMMC_RESP3 register ******************/
21569#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
21570#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
21571#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
21573/****************** Bit definition for SDMMC_RESP4 register ******************/
21574#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
21575#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
21576#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
21578/****************** Bit definition for SDMMC_DTIMER register *****************/
21579#define SDMMC_DTIMER_DATATIME_Pos (0U)
21580#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
21581#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
21583/****************** Bit definition for SDMMC_DLEN register *******************/
21584#define SDMMC_DLEN_DATALENGTH_Pos (0U)
21585#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
21586#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
21588/****************** Bit definition for SDMMC_DCTRL register ******************/
21589#define SDMMC_DCTRL_DTEN_Pos (0U)
21590#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
21591#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
21592#define SDMMC_DCTRL_DTDIR_Pos (1U)
21593#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
21594#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
21595#define SDMMC_DCTRL_DTMODE_Pos (2U)
21596#define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos)
21597#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
21598#define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
21599#define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos)
21601#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
21602#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
21603#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
21604#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
21605#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
21606#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
21607#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
21609#define SDMMC_DCTRL_RWSTART_Pos (8U)
21610#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
21611#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
21612#define SDMMC_DCTRL_RWSTOP_Pos (9U)
21613#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
21614#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
21615#define SDMMC_DCTRL_RWMOD_Pos (10U)
21616#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
21617#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
21618#define SDMMC_DCTRL_SDIOEN_Pos (11U)
21619#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
21620#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
21621#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
21622#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)
21623#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk
21624#define SDMMC_DCTRL_FIFORST_Pos (13U)
21625#define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos)
21626#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk
21628/****************** Bit definition for SDMMC_DCOUNT register *****************/
21629#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
21630#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
21631#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
21633/****************** Bit definition for SDMMC_STA register ********************/
21634#define SDMMC_STA_CCRCFAIL_Pos (0U)
21635#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
21636#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
21637#define SDMMC_STA_DCRCFAIL_Pos (1U)
21638#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
21639#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
21640#define SDMMC_STA_CTIMEOUT_Pos (2U)
21641#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
21642#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
21643#define SDMMC_STA_DTIMEOUT_Pos (3U)
21644#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
21645#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
21646#define SDMMC_STA_TXUNDERR_Pos (4U)
21647#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
21648#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
21649#define SDMMC_STA_RXOVERR_Pos (5U)
21650#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
21651#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
21652#define SDMMC_STA_CMDREND_Pos (6U)
21653#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
21654#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
21655#define SDMMC_STA_CMDSENT_Pos (7U)
21656#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
21657#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
21658#define SDMMC_STA_DATAEND_Pos (8U)
21659#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
21660#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
21661#define SDMMC_STA_DHOLD_Pos (9U)
21662#define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos)
21663#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk
21664#define SDMMC_STA_DBCKEND_Pos (10U)
21665#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
21666#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
21667#define SDMMC_STA_DABORT_Pos (11U)
21668#define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos)
21669#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk
21670#define SDMMC_STA_DPSMACT_Pos (12U)
21671#define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos)
21672#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk
21673#define SDMMC_STA_CPSMACT_Pos (13U)
21674#define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos)
21675#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk
21676#define SDMMC_STA_TXFIFOHE_Pos (14U)
21677#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
21678#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
21679#define SDMMC_STA_RXFIFOHF_Pos (15U)
21680#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
21681#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
21682#define SDMMC_STA_TXFIFOF_Pos (16U)
21683#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
21684#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
21685#define SDMMC_STA_RXFIFOF_Pos (17U)
21686#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
21687#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
21688#define SDMMC_STA_TXFIFOE_Pos (18U)
21689#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
21690#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
21691#define SDMMC_STA_RXFIFOE_Pos (19U)
21692#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
21693#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
21694#define SDMMC_STA_BUSYD0_Pos (20U)
21695#define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos)
21696#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk
21697#define SDMMC_STA_BUSYD0END_Pos (21U)
21698#define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos)
21699#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk
21700#define SDMMC_STA_SDIOIT_Pos (22U)
21701#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
21702#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
21703#define SDMMC_STA_ACKFAIL_Pos (23U)
21704#define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos)
21705#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk
21706#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
21707#define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)
21708#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk
21709#define SDMMC_STA_VSWEND_Pos (25U)
21710#define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos)
21711#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk
21712#define SDMMC_STA_CKSTOP_Pos (26U)
21713#define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos)
21714#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk
21715#define SDMMC_STA_IDMATE_Pos (27U)
21716#define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos)
21717#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk
21718#define SDMMC_STA_IDMABTC_Pos (28U)
21719#define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos)
21720#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk
21722/******************* Bit definition for SDMMC_ICR register *******************/
21723#define SDMMC_ICR_CCRCFAILC_Pos (0U)
21724#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
21725#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
21726#define SDMMC_ICR_DCRCFAILC_Pos (1U)
21727#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
21728#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
21729#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
21730#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
21731#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
21732#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
21733#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
21734#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
21735#define SDMMC_ICR_TXUNDERRC_Pos (4U)
21736#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
21737#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
21738#define SDMMC_ICR_RXOVERRC_Pos (5U)
21739#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
21740#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
21741#define SDMMC_ICR_CMDRENDC_Pos (6U)
21742#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
21743#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
21744#define SDMMC_ICR_CMDSENTC_Pos (7U)
21745#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
21746#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
21747#define SDMMC_ICR_DATAENDC_Pos (8U)
21748#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
21749#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
21750#define SDMMC_ICR_DHOLDC_Pos (9U)
21751#define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos)
21752#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk
21753#define SDMMC_ICR_DBCKENDC_Pos (10U)
21754#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
21755#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
21756#define SDMMC_ICR_DABORTC_Pos (11U)
21757#define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos)
21758#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk
21759#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
21760#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)
21761#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk
21762#define SDMMC_ICR_SDIOITC_Pos (22U)
21763#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
21764#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
21765#define SDMMC_ICR_ACKFAILC_Pos (23U)
21766#define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos)
21767#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk
21768#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
21769#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)
21770#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk
21771#define SDMMC_ICR_VSWENDC_Pos (25U)
21772#define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos)
21773#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk
21774#define SDMMC_ICR_CKSTOPC_Pos (26U)
21775#define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos)
21776#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk
21777#define SDMMC_ICR_IDMATEC_Pos (27U)
21778#define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos)
21779#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk
21780#define SDMMC_ICR_IDMABTCC_Pos (28U)
21781#define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos)
21782#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk
21784/****************** Bit definition for SDMMC_MASK register *******************/
21785#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
21786#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
21787#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
21788#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
21789#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
21790#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
21791#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
21792#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
21793#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
21794#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
21795#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
21796#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
21797#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
21798#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
21799#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
21800#define SDMMC_MASK_RXOVERRIE_Pos (5U)
21801#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
21802#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
21803#define SDMMC_MASK_CMDRENDIE_Pos (6U)
21804#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
21805#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
21806#define SDMMC_MASK_CMDSENTIE_Pos (7U)
21807#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
21808#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
21809#define SDMMC_MASK_DATAENDIE_Pos (8U)
21810#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
21811#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
21812#define SDMMC_MASK_DHOLDIE_Pos (9U)
21813#define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos)
21814#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk
21815#define SDMMC_MASK_DBCKENDIE_Pos (10U)
21816#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
21817#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
21818#define SDMMC_MASK_DABORTIE_Pos (11U)
21819#define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos)
21820#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk
21822#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
21823#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
21824#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
21825#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
21826#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
21827#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
21829#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
21830#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
21831#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
21832#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
21833#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
21834#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
21836#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
21837#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)
21838#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk
21839#define SDMMC_MASK_SDIOITIE_Pos (22U)
21840#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
21841#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
21842#define SDMMC_MASK_ACKFAILIE_Pos (23U)
21843#define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)
21844#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk
21845#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
21846#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)
21847#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk
21848#define SDMMC_MASK_VSWENDIE_Pos (25U)
21849#define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos)
21850#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk
21851#define SDMMC_MASK_CKSTOPIE_Pos (26U)
21852#define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)
21853#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk
21854#define SDMMC_MASK_IDMABTCIE_Pos (28U)
21855#define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)
21856#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk
21858/***************** Bit definition for SDMMC_ACKTIME register *****************/
21859#define SDMMC_ACKTIME_ACKTIME_Pos (0U)
21860#define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos)
21861#define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk
21863/****************** Bit definition for SDMMC_FIFO register *******************/
21864#define SDMMC_FIFO_FIFODATA_Pos (0U)
21865#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
21866#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
21868/****************** Bit definition for SDMMC_IDMACTRL register ****************/
21869#define SDMMC_IDMA_IDMAEN_Pos (0U)
21870#define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos)
21871#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk
21872#define SDMMC_IDMA_IDMABMODE_Pos (1U)
21873#define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)
21874#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk
21875#define SDMMC_IDMA_IDMABACT_Pos (2U)
21876#define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos)
21877#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk
21879/***************** Bit definition for SDMMC_IDMABSIZE register ***************/
21880#define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
21881#define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos)
21882#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk
21884/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
21885#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU)
21887/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
21888#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU)
21890/******************************************************************************/
21891/* */
21892/* Delay Block Interface (DLYB) */
21893/* */
21894/******************************************************************************/
21895/******************* Bit definition for DLYB_CR register ********************/
21896#define DLYB_CR_DEN_Pos (0U)
21897#define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos)
21898#define DLYB_CR_DEN DLYB_CR_DEN_Msk
21899#define DLYB_CR_SEN_Pos (1U)
21900#define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos)
21901#define DLYB_CR_SEN DLYB_CR_SEN_Msk
21904/******************* Bit definition for DLYB_CFGR register ********************/
21905#define DLYB_CFGR_SEL_Pos (0U)
21906#define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos)
21907#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk
21908#define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos)
21909#define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos)
21910#define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos)
21911#define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos)
21913#define DLYB_CFGR_UNIT_Pos (8U)
21914#define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos)
21915#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk
21916#define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos)
21917#define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos)
21918#define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos)
21919#define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos)
21920#define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos)
21921#define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos)
21922#define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos)
21924#define DLYB_CFGR_LNG_Pos (16U)
21925#define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos)
21926#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk
21927#define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos)
21928#define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos)
21929#define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos)
21930#define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos)
21931#define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos)
21932#define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos)
21933#define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos)
21934#define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos)
21935#define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos)
21936#define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos)
21937#define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos)
21938#define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos)
21940#define DLYB_CFGR_LNGF_Pos (31U)
21941#define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos)
21942#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk
21944/******************************************************************************/
21945/* */
21946/* Serial Peripheral Interface (SPI/I2S) */
21947/* */
21948/******************************************************************************/
21949/******************* Bit definition for SPI_CR1 register ********************/
21950#define SPI_CR1_SPE_Pos (0U)
21951#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
21952#define SPI_CR1_SPE SPI_CR1_SPE_Msk
21953#define SPI_CR1_MASRX_Pos (8U)
21954#define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos)
21955#define SPI_CR1_MASRX SPI_CR1_MASRX_Msk
21956#define SPI_CR1_CSTART_Pos (9U)
21957#define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos)
21958#define SPI_CR1_CSTART SPI_CR1_CSTART_Msk
21959#define SPI_CR1_CSUSP_Pos (10U)
21960#define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos)
21961#define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk
21962#define SPI_CR1_HDDIR_Pos (11U)
21963#define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos)
21964#define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk
21965#define SPI_CR1_SSI_Pos (12U)
21966#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
21967#define SPI_CR1_SSI SPI_CR1_SSI_Msk
21968#define SPI_CR1_CRC33_17_Pos (13U)
21969#define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos)
21970#define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk
21971#define SPI_CR1_RCRCINI_Pos (14U)
21972#define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos)
21973#define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk
21974#define SPI_CR1_TCRCINI_Pos (15U)
21975#define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos)
21976#define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk
21977#define SPI_CR1_IOLOCK_Pos (16U)
21978#define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos)
21979#define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk
21981/******************* Bit definition for SPI_CR2 register ********************/
21982#define SPI_CR2_TSER_Pos (16U)
21983#define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos)
21984#define SPI_CR2_TSER SPI_CR2_TSER_Msk
21985#define SPI_CR2_TSIZE_Pos (0U)
21986#define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos)
21987#define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk
21989/******************* Bit definition for SPI_CFG1 register ********************/
21990#define SPI_CFG1_DSIZE_Pos (0U)
21991#define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos)
21992#define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk
21993#define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos)
21994#define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos)
21995#define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos)
21996#define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos)
21997#define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos)
21999#define SPI_CFG1_FTHLV_Pos (5U)
22000#define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos)
22001#define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk
22002#define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos)
22003#define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos)
22004#define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos)
22005#define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos)
22007#define SPI_CFG1_UDRCFG_Pos (9U)
22008#define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos)
22009#define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk
22010#define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos)
22011#define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos)
22014#define SPI_CFG1_UDRDET_Pos (11U)
22015#define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos)
22016#define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk
22017#define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos)
22018#define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos)
22020#define SPI_CFG1_RXDMAEN_Pos (14U)
22021#define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos)
22022#define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk
22023#define SPI_CFG1_TXDMAEN_Pos (15U)
22024#define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos)
22025#define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk
22027#define SPI_CFG1_CRCSIZE_Pos (16U)
22028#define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos)
22029#define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk
22030#define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos)
22031#define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos)
22032#define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos)
22033#define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos)
22034#define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos)
22036#define SPI_CFG1_CRCEN_Pos (22U)
22037#define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos)
22038#define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk
22040#define SPI_CFG1_MBR_Pos (28U)
22041#define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos)
22042#define SPI_CFG1_MBR SPI_CFG1_MBR_Msk
22043#define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos)
22044#define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos)
22045#define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos)
22047/******************* Bit definition for SPI_CFG2 register ********************/
22048#define SPI_CFG2_MSSI_Pos (0U)
22049#define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos)
22050#define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk
22051#define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos)
22052#define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos)
22053#define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos)
22054#define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos)
22056#define SPI_CFG2_MIDI_Pos (4U)
22057#define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos)
22058#define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk
22059#define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos)
22060#define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos)
22061#define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos)
22062#define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos)
22064#define SPI_CFG2_IOSWP_Pos (15U)
22065#define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos)
22066#define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk
22068#define SPI_CFG2_COMM_Pos (17U)
22069#define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos)
22070#define SPI_CFG2_COMM SPI_CFG2_COMM_Msk
22071#define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos)
22072#define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos)
22074#define SPI_CFG2_SP_Pos (19U)
22075#define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos)
22076#define SPI_CFG2_SP SPI_CFG2_SP_Msk
22077#define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos)
22078#define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos)
22079#define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos)
22081#define SPI_CFG2_MASTER_Pos (22U)
22082#define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos)
22083#define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk
22084#define SPI_CFG2_LSBFRST_Pos (23U)
22085#define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos)
22086#define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk
22087#define SPI_CFG2_CPHA_Pos (24U)
22088#define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos)
22089#define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk
22090#define SPI_CFG2_CPOL_Pos (25U)
22091#define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos)
22092#define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk
22093#define SPI_CFG2_SSM_Pos (26U)
22094#define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos)
22095#define SPI_CFG2_SSM SPI_CFG2_SSM_Msk
22097#define SPI_CFG2_SSIOP_Pos (28U)
22098#define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos)
22099#define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk
22100#define SPI_CFG2_SSOE_Pos (29U)
22101#define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos)
22102#define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk
22103#define SPI_CFG2_SSOM_Pos (30U)
22104#define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos)
22105#define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk
22107#define SPI_CFG2_AFCNTR_Pos (31U)
22108#define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos)
22109#define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk
22111/******************* Bit definition for SPI_IER register ********************/
22112#define SPI_IER_RXPIE_Pos (0U)
22113#define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos)
22114#define SPI_IER_RXPIE SPI_IER_RXPIE_Msk
22115#define SPI_IER_TXPIE_Pos (1U)
22116#define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos)
22117#define SPI_IER_TXPIE SPI_IER_TXPIE_Msk
22118#define SPI_IER_DXPIE_Pos (2U)
22119#define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos)
22120#define SPI_IER_DXPIE SPI_IER_DXPIE_Msk
22121#define SPI_IER_EOTIE_Pos (3U)
22122#define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos)
22123#define SPI_IER_EOTIE SPI_IER_EOTIE_Msk
22124#define SPI_IER_TXTFIE_Pos (4U)
22125#define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos)
22126#define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk
22127#define SPI_IER_UDRIE_Pos (5U)
22128#define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos)
22129#define SPI_IER_UDRIE SPI_IER_UDRIE_Msk
22130#define SPI_IER_OVRIE_Pos (6U)
22131#define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos)
22132#define SPI_IER_OVRIE SPI_IER_OVRIE_Msk
22133#define SPI_IER_CRCEIE_Pos (7U)
22134#define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos)
22135#define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk
22136#define SPI_IER_TIFREIE_Pos (8U)
22137#define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos)
22138#define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk
22139#define SPI_IER_MODFIE_Pos (9U)
22140#define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos)
22141#define SPI_IER_MODFIE SPI_IER_MODFIE_Msk
22142#define SPI_IER_TSERFIE_Pos (10U)
22143#define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos)
22144#define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk
22146/******************* Bit definition for SPI_SR register ********************/
22147#define SPI_SR_RXP_Pos (0U)
22148#define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos)
22149#define SPI_SR_RXP SPI_SR_RXP_Msk
22150#define SPI_SR_TXP_Pos (1U)
22151#define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos)
22152#define SPI_SR_TXP SPI_SR_TXP_Msk
22153#define SPI_SR_DXP_Pos (2U)
22154#define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos)
22155#define SPI_SR_DXP SPI_SR_DXP_Msk
22156#define SPI_SR_EOT_Pos (3U)
22157#define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos)
22158#define SPI_SR_EOT SPI_SR_EOT_Msk
22159#define SPI_SR_TXTF_Pos (4U)
22160#define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos)
22161#define SPI_SR_TXTF SPI_SR_TXTF_Msk
22162#define SPI_SR_UDR_Pos (5U)
22163#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
22164#define SPI_SR_UDR SPI_SR_UDR_Msk
22165#define SPI_SR_OVR_Pos (6U)
22166#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
22167#define SPI_SR_OVR SPI_SR_OVR_Msk
22168#define SPI_SR_CRCE_Pos (7U)
22169#define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos)
22170#define SPI_SR_CRCE SPI_SR_CRCE_Msk
22171#define SPI_SR_TIFRE_Pos (8U)
22172#define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos)
22173#define SPI_SR_TIFRE SPI_SR_TIFRE_Msk
22174#define SPI_SR_MODF_Pos (9U)
22175#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
22176#define SPI_SR_MODF SPI_SR_MODF_Msk
22177#define SPI_SR_TSERF_Pos (10U)
22178#define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos)
22179#define SPI_SR_TSERF SPI_SR_TSERF_Msk
22180#define SPI_SR_SUSP_Pos (11U)
22181#define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos)
22182#define SPI_SR_SUSP SPI_SR_SUSP_Msk
22183#define SPI_SR_TXC_Pos (12U)
22184#define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos)
22185#define SPI_SR_TXC SPI_SR_TXC_Msk
22186#define SPI_SR_RXPLVL_Pos (13U)
22187#define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos)
22188#define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk
22189#define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos)
22190#define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos)
22191#define SPI_SR_RXWNE_Pos (15U)
22192#define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos)
22193#define SPI_SR_RXWNE SPI_SR_RXWNE_Msk
22194#define SPI_SR_CTSIZE_Pos (16U)
22195#define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos)
22196#define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk
22198/******************* Bit definition for SPI_IFCR register ********************/
22199#define SPI_IFCR_EOTC_Pos (3U)
22200#define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos)
22201#define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk
22202#define SPI_IFCR_TXTFC_Pos (4U)
22203#define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos)
22204#define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk
22205#define SPI_IFCR_UDRC_Pos (5U)
22206#define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos)
22207#define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk
22208#define SPI_IFCR_OVRC_Pos (6U)
22209#define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos)
22210#define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk
22211#define SPI_IFCR_CRCEC_Pos (7U)
22212#define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos)
22213#define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk
22214#define SPI_IFCR_TIFREC_Pos (8U)
22215#define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos)
22216#define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk
22217#define SPI_IFCR_MODFC_Pos (9U)
22218#define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos)
22219#define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk
22220#define SPI_IFCR_TSERFC_Pos (10U)
22221#define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos)
22222#define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk
22223#define SPI_IFCR_SUSPC_Pos (11U)
22224#define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos)
22225#define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk
22227/******************* Bit definition for SPI_TXDR register ********************/
22228#define SPI_TXDR_TXDR_Pos (0U)
22229#define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)
22230#define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
22231
22232/******************* Bit definition for SPI_RXDR register ********************/
22233#define SPI_RXDR_RXDR_Pos (0U)
22234#define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)
22235#define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
22236
22237/******************* Bit definition for SPI_CRCPOLY register ********************/
22238#define SPI_CRCPOLY_CRCPOLY_Pos (0U)
22239#define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)
22240#define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
22241
22242/******************* Bit definition for SPI_TXCRC register ********************/
22243#define SPI_TXCRC_TXCRC_Pos (0U)
22244#define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)
22245#define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
22246
22247/******************* Bit definition for SPI_RXCRC register ********************/
22248#define SPI_RXCRC_RXCRC_Pos (0U)
22249#define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)
22250#define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
22251
22252/******************* Bit definition for SPI_UDRDR register ********************/
22253#define SPI_UDRDR_UDRDR_Pos (0U)
22254#define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)
22255#define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
22256
22257/****************** Bit definition for SPI_I2SCFGR register *****************/
22258#define SPI_I2SCFGR_I2SMOD_Pos (0U)
22259#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
22260#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
22261#define SPI_I2SCFGR_I2SCFG_Pos (1U)
22262#define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)
22263#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
22264#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
22265#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
22266#define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)
22267#define SPI_I2SCFGR_I2SSTD_Pos (4U)
22268#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
22269#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
22270#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
22271#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
22272#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
22273#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
22274#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
22275#define SPI_I2SCFGR_DATLEN_Pos (8U)
22276#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
22277#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
22278#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
22279#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
22280#define SPI_I2SCFGR_CHLEN_Pos (10U)
22281#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
22282#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
22283#define SPI_I2SCFGR_CKPOL_Pos (11U)
22284#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
22285#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
22286#define SPI_I2SCFGR_FIXCH_Pos (12U)
22287#define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos)
22288#define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk
22289#define SPI_I2SCFGR_WSINV_Pos (13U)
22290#define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos)
22291#define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk
22292#define SPI_I2SCFGR_DATFMT_Pos (14U)
22293#define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos)
22294#define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk
22295#define SPI_I2SCFGR_I2SDIV_Pos (16U)
22296#define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)
22297#define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk
22298#define SPI_I2SCFGR_ODD_Pos (24U)
22299#define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos)
22300#define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk
22301#define SPI_I2SCFGR_MCKOE_Pos (25U)
22302#define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos)
22303#define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk
22306/******************************************************************************/
22307/* */
22308/* QUADSPI */
22309/* */
22310/******************************************************************************/
22311/***************** Bit definition for QUADSPI_CR register *******************/
22312#define QUADSPI_CR_EN_Pos (0U)
22313#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
22314#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
22315#define QUADSPI_CR_ABORT_Pos (1U)
22316#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
22317#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
22318#define QUADSPI_CR_DMAEN_Pos (2U)
22319#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
22320#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
22321#define QUADSPI_CR_TCEN_Pos (3U)
22322#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
22323#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
22324#define QUADSPI_CR_SSHIFT_Pos (4U)
22325#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
22326#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
22327#define QUADSPI_CR_DFM_Pos (6U)
22328#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
22329#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
22330#define QUADSPI_CR_FSEL_Pos (7U)
22331#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
22332#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
22333#define QUADSPI_CR_FTHRES_Pos (8U)
22334#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
22335#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
22336#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos)
22337#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos)
22338#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos)
22339#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos)
22340#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
22341#define QUADSPI_CR_TEIE_Pos (16U)
22342#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
22343#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
22344#define QUADSPI_CR_TCIE_Pos (17U)
22345#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
22346#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
22347#define QUADSPI_CR_FTIE_Pos (18U)
22348#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
22349#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
22350#define QUADSPI_CR_SMIE_Pos (19U)
22351#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
22352#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
22353#define QUADSPI_CR_TOIE_Pos (20U)
22354#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
22355#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
22356#define QUADSPI_CR_APMS_Pos (22U)
22357#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
22358#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
22359#define QUADSPI_CR_PMM_Pos (23U)
22360#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
22361#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
22362#define QUADSPI_CR_PRESCALER_Pos (24U)
22363#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
22364#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
22365#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
22366#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
22367#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
22368#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
22369#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
22370#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
22371#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
22372#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
22374/***************** Bit definition for QUADSPI_DCR register ******************/
22375#define QUADSPI_DCR_CKMODE_Pos (0U)
22376#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
22377#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
22378#define QUADSPI_DCR_CSHT_Pos (8U)
22379#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
22380#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
22381#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
22382#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
22383#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
22384#define QUADSPI_DCR_FSIZE_Pos (16U)
22385#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
22386#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
22387#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
22388#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
22389#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
22390#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
22391#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
22393/****************** Bit definition for QUADSPI_SR register *******************/
22394#define QUADSPI_SR_TEF_Pos (0U)
22395#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
22396#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
22397#define QUADSPI_SR_TCF_Pos (1U)
22398#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
22399#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
22400#define QUADSPI_SR_FTF_Pos (2U)
22401#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
22402#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
22403#define QUADSPI_SR_SMF_Pos (3U)
22404#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
22405#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
22406#define QUADSPI_SR_TOF_Pos (4U)
22407#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
22408#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
22409#define QUADSPI_SR_BUSY_Pos (5U)
22410#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
22411#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
22412#define QUADSPI_SR_FLEVEL_Pos (8U)
22413#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
22414#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
22415#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
22416#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
22417#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
22418#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
22419#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
22420#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
22422/****************** Bit definition for QUADSPI_FCR register ******************/
22423#define QUADSPI_FCR_CTEF_Pos (0U)
22424#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
22425#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
22426#define QUADSPI_FCR_CTCF_Pos (1U)
22427#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
22428#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
22429#define QUADSPI_FCR_CSMF_Pos (3U)
22430#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
22431#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
22432#define QUADSPI_FCR_CTOF_Pos (4U)
22433#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
22434#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
22436/****************** Bit definition for QUADSPI_DLR register ******************/
22437#define QUADSPI_DLR_DL_Pos (0U)
22438#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
22439#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
22441/****************** Bit definition for QUADSPI_CCR register ******************/
22442#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
22443#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
22444#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
22445#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
22446#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
22447#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
22448#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
22449#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
22450#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
22451#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
22452#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
22453#define QUADSPI_CCR_IMODE_Pos (8U)
22454#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
22455#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
22456#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
22457#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
22458#define QUADSPI_CCR_ADMODE_Pos (10U)
22459#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
22460#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
22461#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
22462#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
22463#define QUADSPI_CCR_ADSIZE_Pos (12U)
22464#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
22465#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
22466#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
22467#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
22468#define QUADSPI_CCR_ABMODE_Pos (14U)
22469#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
22470#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
22471#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
22472#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
22473#define QUADSPI_CCR_ABSIZE_Pos (16U)
22474#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
22475#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
22476#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
22477#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
22478#define QUADSPI_CCR_DCYC_Pos (18U)
22479#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
22480#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
22481#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
22482#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
22483#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
22484#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
22485#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
22486#define QUADSPI_CCR_DMODE_Pos (24U)
22487#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
22488#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
22489#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
22490#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
22491#define QUADSPI_CCR_FMODE_Pos (26U)
22492#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
22493#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
22494#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
22495#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
22496#define QUADSPI_CCR_SIOO_Pos (28U)
22497#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
22498#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
22499#define QUADSPI_CCR_DHHC_Pos (30U)
22500#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
22501#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
22502#define QUADSPI_CCR_DDRM_Pos (31U)
22503#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
22504#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
22506/****************** Bit definition for QUADSPI_AR register *******************/
22507#define QUADSPI_AR_ADDRESS_Pos (0U)
22508#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
22509#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
22511/****************** Bit definition for QUADSPI_ABR register ******************/
22512#define QUADSPI_ABR_ALTERNATE_Pos (0U)
22513#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
22514#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
22516/****************** Bit definition for QUADSPI_DR register *******************/
22517#define QUADSPI_DR_DATA_Pos (0U)
22518#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
22519#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
22521/****************** Bit definition for QUADSPI_PSMKR register ****************/
22522#define QUADSPI_PSMKR_MASK_Pos (0U)
22523#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
22524#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
22526/****************** Bit definition for QUADSPI_PSMAR register ****************/
22527#define QUADSPI_PSMAR_MATCH_Pos (0U)
22528#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
22529#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
22531/****************** Bit definition for QUADSPI_PIR register *****************/
22532#define QUADSPI_PIR_INTERVAL_Pos (0U)
22533#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
22534#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
22536/****************** Bit definition for QUADSPI_LPTR register *****************/
22537#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
22538#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
22539#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
22541/******************************************************************************/
22542/* */
22543/* SYSCFG */
22544/* */
22545/******************************************************************************/
22546
22547/****************** Bit definition for SYSCFG_PMCR register ******************/
22548#define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
22549#define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)
22550#define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk
22551#define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
22552#define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)
22553#define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk
22554#define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
22555#define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)
22556#define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk
22557#define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
22558#define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)
22559#define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk
22560#define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
22561#define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos)
22562#define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk
22563#define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
22564#define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos)
22565#define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk
22566#define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
22567#define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos)
22568#define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk
22569#define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
22570#define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos)
22571#define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk
22572#define SYSCFG_PMCR_BOOSTEN_Pos (8U)
22573#define SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)
22574#define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk
22576#define SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U)
22577#define SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos)
22578#define SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk
22580#define SYSCFG_PMCR_EPIS_SEL_Pos (21U)
22581#define SYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)
22582#define SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk
22583#define SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)
22584#define SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)
22585#define SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)
22586#define SYSCFG_PMCR_PA0SO_Pos (24U)
22587#define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos)
22588#define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk
22589#define SYSCFG_PMCR_PA1SO_Pos (25U)
22590#define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos)
22591#define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk
22592#define SYSCFG_PMCR_PC2SO_Pos (26U)
22593#define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos)
22594#define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk
22595#define SYSCFG_PMCR_PC3SO_Pos (27U)
22596#define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos)
22597#define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk
22599/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
22600#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
22601#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
22602#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
22603#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
22604#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
22605#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
22606#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
22607#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
22608#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
22609#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
22610#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
22611#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
22615#define SYSCFG_EXTICR1_EXTI0_PA (0U)
22616#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)
22617#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)
22618#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)
22619#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)
22620#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)
22621#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U)
22622#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U)
22623#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U)
22624#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U)
22625#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU)
22630#define SYSCFG_EXTICR1_EXTI1_PA (0U)
22631#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)
22632#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)
22633#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)
22634#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)
22635#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)
22636#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U)
22637#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U)
22638#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U)
22639#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U)
22640#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U)
22644#define SYSCFG_EXTICR1_EXTI2_PA (0U)
22645#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)
22646#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)
22647#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)
22648#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)
22649#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)
22650#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U)
22651#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U)
22652#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U)
22653#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U)
22654#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U)
22659#define SYSCFG_EXTICR1_EXTI3_PA (0U)
22660#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)
22661#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)
22662#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)
22663#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)
22664#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U)
22665#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U)
22666#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U)
22667#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U)
22668#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U)
22669#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U)
22671/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
22672#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
22673#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
22674#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
22675#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
22676#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
22677#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
22678#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
22679#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
22680#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
22681#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
22682#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
22683#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
22687#define SYSCFG_EXTICR2_EXTI4_PA (0U)
22688#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)
22689#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)
22690#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)
22691#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)
22692#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)
22693#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U)
22694#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U)
22695#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U)
22696#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U)
22697#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU)
22701#define SYSCFG_EXTICR2_EXTI5_PA (0U)
22702#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)
22703#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)
22704#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)
22705#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)
22706#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)
22707#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U)
22708#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U)
22709#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U)
22710#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U)
22711#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U)
22715#define SYSCFG_EXTICR2_EXTI6_PA (0U)
22716#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)
22717#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)
22718#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)
22719#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)
22720#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)
22721#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U)
22722#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U)
22723#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U)
22724#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U)
22725#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U)
22730#define SYSCFG_EXTICR2_EXTI7_PA (0U)
22731#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)
22732#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)
22733#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)
22734#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)
22735#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U)
22736#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U)
22737#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U)
22738#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U)
22739#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U)
22740#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U)
22742/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
22743#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
22744#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
22745#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
22746#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
22747#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
22748#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
22749#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
22750#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
22751#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
22752#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
22753#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
22754#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
22759#define SYSCFG_EXTICR3_EXTI8_PA (0U)
22760#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)
22761#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)
22762#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)
22763#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)
22764#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U)
22765#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U)
22766#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U)
22767#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U)
22768#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U)
22769#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU)
22774#define SYSCFG_EXTICR3_EXTI9_PA (0U)
22775#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)
22776#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)
22777#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)
22778#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)
22779#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)
22780#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U)
22781#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U)
22782#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U)
22783#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U)
22784#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U)
22789#define SYSCFG_EXTICR3_EXTI10_PA (0U)
22790#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)
22791#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)
22792#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)
22793#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)
22794#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)
22795#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U)
22796#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U)
22797#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U)
22798#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U)
22799#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U)
22804#define SYSCFG_EXTICR3_EXTI11_PA (0U)
22805#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)
22806#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)
22807#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)
22808#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)
22809#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U)
22810#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U)
22811#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U)
22812#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U)
22813#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U)
22814#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U)
22816/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
22817#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
22818#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
22819#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
22820#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
22821#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
22822#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
22823#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
22824#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
22825#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
22826#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
22827#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
22828#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
22832#define SYSCFG_EXTICR4_EXTI12_PA (0U)
22833#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)
22834#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)
22835#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)
22836#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)
22837#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U)
22838#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U)
22839#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U)
22840#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U)
22841#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U)
22842#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU)
22846#define SYSCFG_EXTICR4_EXTI13_PA (0U)
22847#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)
22848#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)
22849#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)
22850#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)
22851#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U)
22852#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U)
22853#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U)
22854#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U)
22855#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U)
22856#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U)
22860#define SYSCFG_EXTICR4_EXTI14_PA (0U)
22861#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)
22862#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)
22863#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)
22864#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)
22865#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U)
22866#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U)
22867#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U)
22868#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U)
22869#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U)
22870#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U)
22874#define SYSCFG_EXTICR4_EXTI15_PA (0U)
22875#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)
22876#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)
22877#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)
22878#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)
22879#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U)
22880#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U)
22881#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U)
22882#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U)
22883#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U)
22884#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U)
22886/****************** Bit definition for SYSCFG_CFGR register ******************/
22887#define SYSCFG_CFGR_CM4L_Pos (0U)
22888#define SYSCFG_CFGR_CM4L_Msk (0x1UL << SYSCFG_CFGR_CM4L_Pos)
22889#define SYSCFG_CFGR_CM4L SYSCFG_CFGR_CM4L_Msk
22890#define SYSCFG_CFGR_PVDL_Pos (2U)
22891#define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos)
22892#define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk
22893#define SYSCFG_CFGR_FLASHL_Pos (3U)
22894#define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos)
22895#define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk
22896#define SYSCFG_CFGR_CM7L_Pos (6U)
22897#define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos)
22898#define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk
22899#define SYSCFG_CFGR_BKRAML_Pos (7U)
22900#define SYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos)
22901#define SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk
22902#define SYSCFG_CFGR_SRAM4L_Pos (9U)
22903#define SYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)
22904#define SYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk
22905#define SYSCFG_CFGR_SRAM3L_Pos (10U)
22906#define SYSCFG_CFGR_SRAM3L_Msk (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)
22907#define SYSCFG_CFGR_SRAM3L SYSCFG_CFGR_SRAM3L_Msk
22908#define SYSCFG_CFGR_SRAM2L_Pos (11U)
22909#define SYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)
22910#define SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk
22911#define SYSCFG_CFGR_SRAM1L_Pos (12U)
22912#define SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)
22913#define SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk
22914#define SYSCFG_CFGR_DTCML_Pos (13U)
22915#define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos)
22916#define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk
22917#define SYSCFG_CFGR_ITCML_Pos (14U)
22918#define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos)
22919#define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk
22920#define SYSCFG_CFGR_AXISRAML_Pos (15U)
22921#define SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)
22922#define SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk
22924/****************** Bit definition for SYSCFG_CCCSR register ******************/
22925#define SYSCFG_CCCSR_EN_Pos (0U)
22926#define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos)
22927#define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk
22928#define SYSCFG_CCCSR_CS_Pos (1U)
22929#define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos)
22930#define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk
22931#define SYSCFG_CCCSR_READY_Pos (8U)
22932#define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos)
22933#define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk
22934#define SYSCFG_CCCSR_HSLV_Pos (16U)
22935#define SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos)
22936#define SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk
22938/****************** Bit definition for SYSCFG_CCVR register *******************/
22939#define SYSCFG_CCVR_NCV_Pos (0U)
22940#define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos)
22941#define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk
22942#define SYSCFG_CCVR_PCV_Pos (4U)
22943#define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos)
22944#define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk
22946/****************** Bit definition for SYSCFG_CCCR register *******************/
22947#define SYSCFG_CCCR_NCC_Pos (0U)
22948#define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos)
22949#define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk
22950#define SYSCFG_CCCR_PCC_Pos (4U)
22951#define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos)
22952#define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk
22953/****************** Bit definition for SYSCFG_PWRCR register *******************/
22954#define SYSCFG_PWRCR_ODEN_Pos (0U)
22955#define SYSCFG_PWRCR_ODEN_Msk (0x1UL << SYSCFG_PWRCR_ODEN_Pos)
22956#define SYSCFG_PWRCR_ODEN SYSCFG_PWRCR_ODEN_Msk
22958/****************** Bit definition for SYSCFG_PKGR register *******************/
22959#define SYSCFG_PKGR_PKG_Pos (0U)
22960#define SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos)
22961#define SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk
22963/****************** Bit definition for SYSCFG_UR0 register *******************/
22964#define SYSCFG_UR0_BKS_Pos (0U)
22965#define SYSCFG_UR0_BKS_Msk (0x1UL << SYSCFG_UR0_BKS_Pos)
22966#define SYSCFG_UR0_BKS SYSCFG_UR0_BKS_Msk
22967#define SYSCFG_UR0_RDP_Pos (16U)
22968#define SYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos)
22969#define SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk
22971/****************** Bit definition for SYSCFG_UR1 register *******************/
22972#define SYSCFG_UR1_BCM4_Pos (0U)
22973#define SYSCFG_UR1_BCM4_Msk (0x1UL << SYSCFG_UR1_BCM4_Pos)
22974#define SYSCFG_UR1_BCM4 SYSCFG_UR1_BCM4_Msk
22975#define SYSCFG_UR1_BCM7_Pos (16U)
22976#define SYSCFG_UR1_BCM7_Msk (0x1UL << SYSCFG_UR1_BCM7_Pos)
22977#define SYSCFG_UR1_BCM7 SYSCFG_UR1_BCM7_Msk
22978/****************** Bit definition for SYSCFG_UR2 register *******************/
22979#define SYSCFG_UR2_BORH_Pos (0U)
22980#define SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos)
22981#define SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk
22982#define SYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos)
22983#define SYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos)
22984#define SYSCFG_UR2_BCM7_ADD0_Pos (16U)
22985#define SYSCFG_UR2_BCM7_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BCM7_ADD0_Pos)
22986#define SYSCFG_UR2_BCM7_ADD0 SYSCFG_UR2_BCM7_ADD0_Msk
22987/****************** Bit definition for SYSCFG_UR3 register *******************/
22988#define SYSCFG_UR3_BCM7_ADD1_Pos (0U)
22989#define SYSCFG_UR3_BCM7_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BCM7_ADD1_Pos)
22990#define SYSCFG_UR3_BCM7_ADD1 SYSCFG_UR3_BCM7_ADD1_Msk
22992#define SYSCFG_UR3_BCM4_ADD0_Pos (16U)
22993#define SYSCFG_UR3_BCM4_ADD0_Msk (0xFFFFUL << SYSCFG_UR3_BCM4_ADD0_Pos)
22994#define SYSCFG_UR3_BCM4_ADD0 SYSCFG_UR3_BCM4_ADD0_Msk
22996/****************** Bit definition for SYSCFG_UR4 register *******************/
22997
22998#define SYSCFG_UR4_BCM4_ADD1_Pos (0U)
22999#define SYSCFG_UR4_BCM4_ADD1_Msk (0xFFFFUL << SYSCFG_UR4_BCM4_ADD1_Pos)
23000#define SYSCFG_UR4_BCM4_ADD1 SYSCFG_UR4_BCM4_ADD1_Msk
23002#define SYSCFG_UR4_MEPAD_BANK1_Pos (16U)
23003#define SYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)
23004#define SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk
23006/****************** Bit definition for SYSCFG_UR5 register *******************/
23007#define SYSCFG_UR5_MESAD_BANK1_Pos (0U)
23008#define SYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)
23009#define SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk
23010#define SYSCFG_UR5_WRPN_BANK1_Pos (16U)
23011#define SYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)
23012#define SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk
23014/****************** Bit definition for SYSCFG_UR6 register *******************/
23015#define SYSCFG_UR6_PABEG_BANK1_Pos (0U)
23016#define SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos)
23017#define SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk
23018#define SYSCFG_UR6_PAEND_BANK1_Pos (16U)
23019#define SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos)
23020#define SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk
23022/****************** Bit definition for SYSCFG_UR7 register *******************/
23023#define SYSCFG_UR7_SABEG_BANK1_Pos (0U)
23024#define SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos)
23025#define SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk
23026#define SYSCFG_UR7_SAEND_BANK1_Pos (16U)
23027#define SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos)
23028#define SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk
23030/****************** Bit definition for SYSCFG_UR8 register *******************/
23031#define SYSCFG_UR8_MEPAD_BANK2_Pos (0U)
23032#define SYSCFG_UR8_MEPAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)
23033#define SYSCFG_UR8_MEPAD_BANK2 SYSCFG_UR8_MEPAD_BANK2_Msk
23034#define SYSCFG_UR8_MESAD_BANK2_Pos (16U)
23035#define SYSCFG_UR8_MESAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)
23036#define SYSCFG_UR8_MESAD_BANK2 SYSCFG_UR8_MESAD_BANK2_Msk
23038/****************** Bit definition for SYSCFG_UR9 register *******************/
23039#define SYSCFG_UR9_WRPN_BANK2_Pos (0U)
23040#define SYSCFG_UR9_WRPN_BANK2_Msk (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)
23041#define SYSCFG_UR9_WRPN_BANK2 SYSCFG_UR9_WRPN_BANK2_Msk
23042#define SYSCFG_UR9_PABEG_BANK2_Pos (16U)
23043#define SYSCFG_UR9_PABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos)
23044#define SYSCFG_UR9_PABEG_BANK2 SYSCFG_UR9_PABEG_BANK2_Msk
23046/****************** Bit definition for SYSCFG_UR10 register *******************/
23047#define SYSCFG_UR10_PAEND_BANK2_Pos (0U)
23048#define SYSCFG_UR10_PAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos)
23049#define SYSCFG_UR10_PAEND_BANK2 SYSCFG_UR10_PAEND_BANK2_Msk
23050#define SYSCFG_UR10_SABEG_BANK2_Pos (16U)
23051#define SYSCFG_UR10_SABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos)
23052#define SYSCFG_UR10_SABEG_BANK2 SYSCFG_UR10_SABEG_BANK2_Msk
23054/****************** Bit definition for SYSCFG_UR11 register *******************/
23055#define SYSCFG_UR11_SAEND_BANK2_Pos (0U)
23056#define SYSCFG_UR11_SAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos)
23057#define SYSCFG_UR11_SAEND_BANK2 SYSCFG_UR11_SAEND_BANK2_Msk
23058#define SYSCFG_UR11_IWDG1M_Pos (16U)
23059#define SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos)
23060#define SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk
23062/****************** Bit definition for SYSCFG_UR12 register *******************/
23063#define SYSCFG_UR12_IWDG2M_Pos (0U)
23064#define SYSCFG_UR12_IWDG2M_Msk (0x1UL << SYSCFG_UR12_IWDG2M_Pos)
23065#define SYSCFG_UR12_IWDG2M SYSCFG_UR12_IWDG2M_Msk
23067#define SYSCFG_UR12_SECURE_Pos (16U)
23068#define SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos)
23069#define SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk
23071/****************** Bit definition for SYSCFG_UR13 register *******************/
23072#define SYSCFG_UR13_SDRS_Pos (0U)
23073#define SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos)
23074#define SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk
23075#define SYSCFG_UR13_D1SBRST_Pos (16U)
23076#define SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos)
23077#define SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk
23079/****************** Bit definition for SYSCFG_UR14 register *******************/
23080#define SYSCFG_UR14_D1STPRST_Pos (0U)
23081#define SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos)
23082#define SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk
23083#define SYSCFG_UR14_D2SBRST_Pos (16U)
23084#define SYSCFG_UR14_D2SBRST_Msk (0x1UL << SYSCFG_UR14_D2SBRST_Pos)
23085#define SYSCFG_UR14_D2SBRST SYSCFG_UR14_D2SBRST_Msk
23087/****************** Bit definition for SYSCFG_UR15 register *******************/
23088#define SYSCFG_UR15_D2STPRST_Pos (0U)
23089#define SYSCFG_UR15_D2STPRST_Msk (0x1UL << SYSCFG_UR15_D2STPRST_Pos)
23090#define SYSCFG_UR15_D2STPRST SYSCFG_UR15_D2STPRST_Msk
23091#define SYSCFG_UR15_FZIWDGSTB_Pos (16U)
23092#define SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)
23093#define SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk
23095/****************** Bit definition for SYSCFG_UR16 register *******************/
23096#define SYSCFG_UR16_FZIWDGSTP_Pos (0U)
23097#define SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)
23098#define SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk
23099#define SYSCFG_UR16_PKP_Pos (16U)
23100#define SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos)
23101#define SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk
23103/****************** Bit definition for SYSCFG_UR17 register *******************/
23104#define SYSCFG_UR17_IOHSLV_Pos (0U)
23105#define SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos)
23106#define SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk
23109/******************************************************************************/
23110/* */
23111/* TIM */
23112/* */
23113/******************************************************************************/
23114#define TIM_BREAK_INPUT_SUPPORT
23116/******************* Bit definition for TIM_CR1 register ********************/
23117#define TIM_CR1_CEN_Pos (0U)
23118#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
23119#define TIM_CR1_CEN TIM_CR1_CEN_Msk
23120#define TIM_CR1_UDIS_Pos (1U)
23121#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
23122#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
23123#define TIM_CR1_URS_Pos (2U)
23124#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
23125#define TIM_CR1_URS TIM_CR1_URS_Msk
23126#define TIM_CR1_OPM_Pos (3U)
23127#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
23128#define TIM_CR1_OPM TIM_CR1_OPM_Msk
23129#define TIM_CR1_DIR_Pos (4U)
23130#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
23131#define TIM_CR1_DIR TIM_CR1_DIR_Msk
23133#define TIM_CR1_CMS_Pos (5U)
23134#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
23135#define TIM_CR1_CMS TIM_CR1_CMS_Msk
23136#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
23137#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
23139#define TIM_CR1_ARPE_Pos (7U)
23140#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
23141#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
23143#define TIM_CR1_CKD_Pos (8U)
23144#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
23145#define TIM_CR1_CKD TIM_CR1_CKD_Msk
23146#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
23147#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
23149#define TIM_CR1_UIFREMAP_Pos (11U)
23150#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
23151#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
23153/******************* Bit definition for TIM_CR2 register ********************/
23154#define TIM_CR2_CCPC_Pos (0U)
23155#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
23156#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
23157#define TIM_CR2_CCUS_Pos (2U)
23158#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
23159#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
23160#define TIM_CR2_CCDS_Pos (3U)
23161#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
23162#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
23164#define TIM_CR2_MMS_Pos (4U)
23165#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
23166#define TIM_CR2_MMS TIM_CR2_MMS_Msk
23167#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
23168#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
23169#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
23171#define TIM_CR2_TI1S_Pos (7U)
23172#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
23173#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
23174#define TIM_CR2_OIS1_Pos (8U)
23175#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
23176#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
23177#define TIM_CR2_OIS1N_Pos (9U)
23178#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
23179#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
23180#define TIM_CR2_OIS2_Pos (10U)
23181#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
23182#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
23183#define TIM_CR2_OIS2N_Pos (11U)
23184#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
23185#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
23186#define TIM_CR2_OIS3_Pos (12U)
23187#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
23188#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
23189#define TIM_CR2_OIS3N_Pos (13U)
23190#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
23191#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
23192#define TIM_CR2_OIS4_Pos (14U)
23193#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
23194#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
23195#define TIM_CR2_OIS5_Pos (16U)
23196#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
23197#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
23198#define TIM_CR2_OIS6_Pos (18U)
23199#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
23200#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
23202#define TIM_CR2_MMS2_Pos (20U)
23203#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
23204#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
23205#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
23206#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
23207#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
23208#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
23210/******************* Bit definition for TIM_SMCR register *******************/
23211#define TIM_SMCR_SMS_Pos (0U)
23212#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
23213#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
23214#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
23215#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
23216#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
23217#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
23219#define TIM_SMCR_TS_Pos (4U)
23220#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos)
23221#define TIM_SMCR_TS TIM_SMCR_TS_Msk
23222#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos)
23223#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos)
23224#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos)
23225#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos)
23226#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos)
23228#define TIM_SMCR_MSM_Pos (7U)
23229#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
23230#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
23232#define TIM_SMCR_ETF_Pos (8U)
23233#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
23234#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
23235#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
23236#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
23237#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
23238#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
23240#define TIM_SMCR_ETPS_Pos (12U)
23241#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
23242#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
23243#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
23244#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
23246#define TIM_SMCR_ECE_Pos (14U)
23247#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
23248#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
23249#define TIM_SMCR_ETP_Pos (15U)
23250#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
23251#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
23253/******************* Bit definition for TIM_DIER register *******************/
23254#define TIM_DIER_UIE_Pos (0U)
23255#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
23256#define TIM_DIER_UIE TIM_DIER_UIE_Msk
23257#define TIM_DIER_CC1IE_Pos (1U)
23258#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
23259#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
23260#define TIM_DIER_CC2IE_Pos (2U)
23261#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
23262#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
23263#define TIM_DIER_CC3IE_Pos (3U)
23264#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
23265#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
23266#define TIM_DIER_CC4IE_Pos (4U)
23267#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
23268#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
23269#define TIM_DIER_COMIE_Pos (5U)
23270#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
23271#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
23272#define TIM_DIER_TIE_Pos (6U)
23273#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
23274#define TIM_DIER_TIE TIM_DIER_TIE_Msk
23275#define TIM_DIER_BIE_Pos (7U)
23276#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
23277#define TIM_DIER_BIE TIM_DIER_BIE_Msk
23278#define TIM_DIER_UDE_Pos (8U)
23279#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
23280#define TIM_DIER_UDE TIM_DIER_UDE_Msk
23281#define TIM_DIER_CC1DE_Pos (9U)
23282#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
23283#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
23284#define TIM_DIER_CC2DE_Pos (10U)
23285#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
23286#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
23287#define TIM_DIER_CC3DE_Pos (11U)
23288#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
23289#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
23290#define TIM_DIER_CC4DE_Pos (12U)
23291#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
23292#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
23293#define TIM_DIER_COMDE_Pos (13U)
23294#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
23295#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
23296#define TIM_DIER_TDE_Pos (14U)
23297#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
23298#define TIM_DIER_TDE TIM_DIER_TDE_Msk
23300/******************** Bit definition for TIM_SR register ********************/
23301#define TIM_SR_UIF_Pos (0U)
23302#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
23303#define TIM_SR_UIF TIM_SR_UIF_Msk
23304#define TIM_SR_CC1IF_Pos (1U)
23305#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
23306#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
23307#define TIM_SR_CC2IF_Pos (2U)
23308#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
23309#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
23310#define TIM_SR_CC3IF_Pos (3U)
23311#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
23312#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
23313#define TIM_SR_CC4IF_Pos (4U)
23314#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
23315#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
23316#define TIM_SR_COMIF_Pos (5U)
23317#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
23318#define TIM_SR_COMIF TIM_SR_COMIF_Msk
23319#define TIM_SR_TIF_Pos (6U)
23320#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
23321#define TIM_SR_TIF TIM_SR_TIF_Msk
23322#define TIM_SR_BIF_Pos (7U)
23323#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
23324#define TIM_SR_BIF TIM_SR_BIF_Msk
23325#define TIM_SR_B2IF_Pos (8U)
23326#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
23327#define TIM_SR_B2IF TIM_SR_B2IF_Msk
23328#define TIM_SR_CC1OF_Pos (9U)
23329#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
23330#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
23331#define TIM_SR_CC2OF_Pos (10U)
23332#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
23333#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
23334#define TIM_SR_CC3OF_Pos (11U)
23335#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
23336#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
23337#define TIM_SR_CC4OF_Pos (12U)
23338#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
23339#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
23340#define TIM_SR_CC5IF_Pos (16U)
23341#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
23342#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
23343#define TIM_SR_CC6IF_Pos (17U)
23344#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
23345#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
23346#define TIM_SR_SBIF_Pos (13U)
23347#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
23348#define TIM_SR_SBIF TIM_SR_SBIF_Msk
23350/******************* Bit definition for TIM_EGR register ********************/
23351#define TIM_EGR_UG_Pos (0U)
23352#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
23353#define TIM_EGR_UG TIM_EGR_UG_Msk
23354#define TIM_EGR_CC1G_Pos (1U)
23355#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
23356#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
23357#define TIM_EGR_CC2G_Pos (2U)
23358#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
23359#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
23360#define TIM_EGR_CC3G_Pos (3U)
23361#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
23362#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
23363#define TIM_EGR_CC4G_Pos (4U)
23364#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
23365#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
23366#define TIM_EGR_COMG_Pos (5U)
23367#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
23368#define TIM_EGR_COMG TIM_EGR_COMG_Msk
23369#define TIM_EGR_TG_Pos (6U)
23370#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
23371#define TIM_EGR_TG TIM_EGR_TG_Msk
23372#define TIM_EGR_BG_Pos (7U)
23373#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
23374#define TIM_EGR_BG TIM_EGR_BG_Msk
23375#define TIM_EGR_B2G_Pos (8U)
23376#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
23377#define TIM_EGR_B2G TIM_EGR_B2G_Msk
23380/****************** Bit definition for TIM_CCMR1 register *******************/
23381#define TIM_CCMR1_CC1S_Pos (0U)
23382#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
23383#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
23384#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
23385#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
23387#define TIM_CCMR1_OC1FE_Pos (2U)
23388#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
23389#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
23390#define TIM_CCMR1_OC1PE_Pos (3U)
23391#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
23392#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
23394#define TIM_CCMR1_OC1M_Pos (4U)
23395#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
23396#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
23397#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
23398#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
23399#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
23400#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
23402#define TIM_CCMR1_OC1CE_Pos (7U)
23403#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
23404#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
23406#define TIM_CCMR1_CC2S_Pos (8U)
23407#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
23408#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
23409#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
23410#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
23412#define TIM_CCMR1_OC2FE_Pos (10U)
23413#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
23414#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
23415#define TIM_CCMR1_OC2PE_Pos (11U)
23416#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
23417#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
23419#define TIM_CCMR1_OC2M_Pos (12U)
23420#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
23421#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
23422#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
23423#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
23424#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
23425#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
23427#define TIM_CCMR1_OC2CE_Pos (15U)
23428#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
23429#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
23431/*----------------------------------------------------------------------------*/
23432
23433#define TIM_CCMR1_IC1PSC_Pos (2U)
23434#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
23435#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
23436#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
23437#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
23439#define TIM_CCMR1_IC1F_Pos (4U)
23440#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
23441#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
23442#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
23443#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
23444#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
23445#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
23447#define TIM_CCMR1_IC2PSC_Pos (10U)
23448#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
23449#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
23450#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
23451#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
23453#define TIM_CCMR1_IC2F_Pos (12U)
23454#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
23455#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
23456#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
23457#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
23458#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
23459#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
23461/****************** Bit definition for TIM_CCMR2 register *******************/
23462#define TIM_CCMR2_CC3S_Pos (0U)
23463#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
23464#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
23465#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
23466#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
23468#define TIM_CCMR2_OC3FE_Pos (2U)
23469#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
23470#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
23471#define TIM_CCMR2_OC3PE_Pos (3U)
23472#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
23473#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
23475#define TIM_CCMR2_OC3M_Pos (4U)
23476#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
23477#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
23478#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
23479#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
23480#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
23481#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
23483#define TIM_CCMR2_OC3CE_Pos (7U)
23484#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
23485#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
23487#define TIM_CCMR2_CC4S_Pos (8U)
23488#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
23489#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
23490#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
23491#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
23493#define TIM_CCMR2_OC4FE_Pos (10U)
23494#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
23495#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
23496#define TIM_CCMR2_OC4PE_Pos (11U)
23497#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
23498#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
23500#define TIM_CCMR2_OC4M_Pos (12U)
23501#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
23502#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
23503#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
23504#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
23505#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
23506#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
23508#define TIM_CCMR2_OC4CE_Pos (15U)
23509#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
23510#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
23512/*----------------------------------------------------------------------------*/
23513
23514#define TIM_CCMR2_IC3PSC_Pos (2U)
23515#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
23516#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
23517#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
23518#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
23520#define TIM_CCMR2_IC3F_Pos (4U)
23521#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
23522#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
23523#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
23524#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
23525#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
23526#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
23528#define TIM_CCMR2_IC4PSC_Pos (10U)
23529#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
23530#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
23531#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
23532#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
23534#define TIM_CCMR2_IC4F_Pos (12U)
23535#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
23536#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
23537#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
23538#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
23539#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
23540#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
23542/******************* Bit definition for TIM_CCER register *******************/
23543#define TIM_CCER_CC1E_Pos (0U)
23544#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
23545#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
23546#define TIM_CCER_CC1P_Pos (1U)
23547#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
23548#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
23549#define TIM_CCER_CC1NE_Pos (2U)
23550#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
23551#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
23552#define TIM_CCER_CC1NP_Pos (3U)
23553#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
23554#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
23555#define TIM_CCER_CC2E_Pos (4U)
23556#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
23557#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
23558#define TIM_CCER_CC2P_Pos (5U)
23559#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
23560#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
23561#define TIM_CCER_CC2NE_Pos (6U)
23562#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
23563#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
23564#define TIM_CCER_CC2NP_Pos (7U)
23565#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
23566#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
23567#define TIM_CCER_CC3E_Pos (8U)
23568#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
23569#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
23570#define TIM_CCER_CC3P_Pos (9U)
23571#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
23572#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
23573#define TIM_CCER_CC3NE_Pos (10U)
23574#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
23575#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
23576#define TIM_CCER_CC3NP_Pos (11U)
23577#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
23578#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
23579#define TIM_CCER_CC4E_Pos (12U)
23580#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
23581#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
23582#define TIM_CCER_CC4P_Pos (13U)
23583#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
23584#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
23585#define TIM_CCER_CC4NP_Pos (15U)
23586#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
23587#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
23588#define TIM_CCER_CC5E_Pos (16U)
23589#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
23590#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
23591#define TIM_CCER_CC5P_Pos (17U)
23592#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
23593#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
23594#define TIM_CCER_CC6E_Pos (20U)
23595#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
23596#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
23597#define TIM_CCER_CC6P_Pos (21U)
23598#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
23599#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
23600/******************* Bit definition for TIM_CNT register ********************/
23601#define TIM_CNT_CNT_Pos (0U)
23602#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
23603#define TIM_CNT_CNT TIM_CNT_CNT_Msk
23604#define TIM_CNT_UIFCPY_Pos (31U)
23605#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
23606#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
23607/******************* Bit definition for TIM_PSC register ********************/
23608#define TIM_PSC_PSC_Pos (0U)
23609#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
23610#define TIM_PSC_PSC TIM_PSC_PSC_Msk
23612/******************* Bit definition for TIM_ARR register ********************/
23613#define TIM_ARR_ARR_Pos (0U)
23614#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
23615#define TIM_ARR_ARR TIM_ARR_ARR_Msk
23617/******************* Bit definition for TIM_RCR register ********************/
23618#define TIM_RCR_REP_Pos (0U)
23619#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
23620#define TIM_RCR_REP TIM_RCR_REP_Msk
23622/******************* Bit definition for TIM_CCR1 register *******************/
23623#define TIM_CCR1_CCR1_Pos (0U)
23624#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
23625#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
23627/******************* Bit definition for TIM_CCR2 register *******************/
23628#define TIM_CCR2_CCR2_Pos (0U)
23629#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
23630#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
23632/******************* Bit definition for TIM_CCR3 register *******************/
23633#define TIM_CCR3_CCR3_Pos (0U)
23634#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
23635#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
23637/******************* Bit definition for TIM_CCR4 register *******************/
23638#define TIM_CCR4_CCR4_Pos (0U)
23639#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
23640#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
23642/******************* Bit definition for TIM_CCR5 register *******************/
23643#define TIM_CCR5_CCR5_Pos (0U)
23644#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
23645#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
23646#define TIM_CCR5_GC5C1_Pos (29U)
23647#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
23648#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
23649#define TIM_CCR5_GC5C2_Pos (30U)
23650#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
23651#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
23652#define TIM_CCR5_GC5C3_Pos (31U)
23653#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
23654#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
23656/******************* Bit definition for TIM_CCR6 register *******************/
23657#define TIM_CCR6_CCR6_Pos (0U)
23658#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)
23659#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk
23661/******************* Bit definition for TIM_BDTR register *******************/
23662#define TIM_BDTR_DTG_Pos (0U)
23663#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
23664#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
23665#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
23666#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
23667#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
23668#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
23669#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
23670#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
23671#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
23672#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
23674#define TIM_BDTR_LOCK_Pos (8U)
23675#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
23676#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
23677#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
23678#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
23680#define TIM_BDTR_OSSI_Pos (10U)
23681#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
23682#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
23683#define TIM_BDTR_OSSR_Pos (11U)
23684#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
23685#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
23686#define TIM_BDTR_BKE_Pos (12U)
23687#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
23688#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
23689#define TIM_BDTR_BKP_Pos (13U)
23690#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
23691#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
23692#define TIM_BDTR_AOE_Pos (14U)
23693#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
23694#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
23695#define TIM_BDTR_MOE_Pos (15U)
23696#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
23697#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
23699#define TIM_BDTR_BKF_Pos (16U)
23700#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
23701#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
23702#define TIM_BDTR_BK2F_Pos (20U)
23703#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
23704#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
23706#define TIM_BDTR_BK2E_Pos (24U)
23707#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
23708#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
23709#define TIM_BDTR_BK2P_Pos (25U)
23710#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
23711#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
23713/******************* Bit definition for TIM_DCR register ********************/
23714#define TIM_DCR_DBA_Pos (0U)
23715#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
23716#define TIM_DCR_DBA TIM_DCR_DBA_Msk
23717#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
23718#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
23719#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
23720#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
23721#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
23723#define TIM_DCR_DBL_Pos (8U)
23724#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
23725#define TIM_DCR_DBL TIM_DCR_DBL_Msk
23726#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
23727#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
23728#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
23729#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
23730#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
23732/******************* Bit definition for TIM_DMAR register *******************/
23733#define TIM_DMAR_DMAB_Pos (0U)
23734#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
23735#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
23737/****************** Bit definition for TIM_CCMR3 register *******************/
23738#define TIM_CCMR3_OC5FE_Pos (2U)
23739#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
23740#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
23741#define TIM_CCMR3_OC5PE_Pos (3U)
23742#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
23743#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
23745#define TIM_CCMR3_OC5M_Pos (4U)
23746#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
23747#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
23748#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos)
23749#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos)
23750#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos)
23751#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
23753#define TIM_CCMR3_OC5CE_Pos (7U)
23754#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
23755#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
23757#define TIM_CCMR3_OC6FE_Pos (10U)
23758#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
23759#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
23760#define TIM_CCMR3_OC6PE_Pos (11U)
23761#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
23762#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
23764#define TIM_CCMR3_OC6M_Pos (12U)
23765#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
23766#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
23767#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos)
23768#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos)
23769#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos)
23770#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
23772#define TIM_CCMR3_OC6CE_Pos (15U)
23773#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
23774#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
23775/******************* Bit definition for TIM1_AF1 register *********************/
23776#define TIM1_AF1_BKINE_Pos (0U)
23777#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)
23778#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk
23779#define TIM1_AF1_BKCMP1E_Pos (1U)
23780#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos)
23781#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk
23782#define TIM1_AF1_BKCMP2E_Pos (2U)
23783#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos)
23784#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk
23785#define TIM1_AF1_BKDF1BK0E_Pos (8U)
23786#define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)
23787#define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk
23788#define TIM1_AF1_BKINP_Pos (9U)
23789#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)
23790#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk
23791#define TIM1_AF1_BKCMP1P_Pos (10U)
23792#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos)
23793#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk
23794#define TIM1_AF1_BKCMP2P_Pos (11U)
23795#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos)
23796#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk
23798#define TIM1_AF1_ETRSEL_Pos (14U)
23799#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos)
23800#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk
23801#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos)
23802#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos)
23803#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos)
23804#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos)
23806/******************* Bit definition for TIM1_AF2 register *********************/
23807#define TIM1_AF2_BK2INE_Pos (0U)
23808#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)
23809#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk
23810#define TIM1_AF2_BK2CMP1E_Pos (1U)
23811#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos)
23812#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk
23813#define TIM1_AF2_BK2CMP2E_Pos (2U)
23814#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos)
23815#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk
23816#define TIM1_AF2_BK2DFBK1E_Pos (8U)
23817#define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)
23818#define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk
23819#define TIM1_AF2_BK2INP_Pos (9U)
23820#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)
23821#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk
23822#define TIM1_AF2_BK2CMP1P_Pos (10U)
23823#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos)
23824#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk
23825#define TIM1_AF2_BK2CMP2P_Pos (11U)
23826#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos)
23827#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk
23829/******************* Bit definition for TIM_TISEL register *********************/
23830#define TIM_TISEL_TI1SEL_Pos (0U)
23831#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos)
23832#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk
23833#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos)
23834#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos)
23835#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos)
23836#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos)
23838#define TIM_TISEL_TI2SEL_Pos (8U)
23839#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos)
23840#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk
23841#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos)
23842#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos)
23843#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos)
23844#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos)
23846#define TIM_TISEL_TI3SEL_Pos (16U)
23847#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos)
23848#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk
23849#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos)
23850#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos)
23851#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos)
23852#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos)
23854#define TIM_TISEL_TI4SEL_Pos (24U)
23855#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos)
23856#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk
23857#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos)
23858#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos)
23859#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos)
23860#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos)
23862/******************* Bit definition for TIM8_AF1 register *********************/
23863#define TIM8_AF1_BKINE_Pos (0U)
23864#define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos)
23865#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk
23866#define TIM8_AF1_BKCMP1E_Pos (1U)
23867#define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos)
23868#define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk
23869#define TIM8_AF1_BKCMP2E_Pos (2U)
23870#define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos)
23871#define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk
23872#define TIM8_AF1_BKDFBK2E_Pos (8U)
23873#define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos)
23874#define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk
23875#define TIM8_AF1_BKINP_Pos (9U)
23876#define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos)
23877#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk
23878#define TIM8_AF1_BKCMP1P_Pos (10U)
23879#define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos)
23880#define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk
23881#define TIM8_AF1_BKCMP2P_Pos (11U)
23882#define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos)
23883#define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk
23885#define TIM8_AF1_ETRSEL_Pos (14U)
23886#define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos)
23887#define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk
23888#define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos)
23889#define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos)
23890#define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos)
23891#define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos)
23892/******************* Bit definition for TIM8_AF2 register *********************/
23893#define TIM8_AF2_BK2INE_Pos (0U)
23894#define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos)
23895#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk
23896#define TIM8_AF2_BK2CMP1E_Pos (1U)
23897#define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos)
23898#define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk
23899#define TIM8_AF2_BK2CMP2E_Pos (2U)
23900#define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos)
23901#define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk
23902#define TIM8_AF2_BK2DFBK3E_Pos (8U)
23903#define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)
23904#define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk
23905#define TIM8_AF2_BK2INP_Pos (9U)
23906#define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos)
23907#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk
23908#define TIM8_AF2_BK2CMP1P_Pos (10U)
23909#define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos)
23910#define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk
23911#define TIM8_AF2_BK2CMP2P_Pos (11U)
23912#define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos)
23913#define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk
23915/******************* Bit definition for TIM2_AF1 register *********************/
23916#define TIM2_AF1_ETRSEL_Pos (14U)
23917#define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos)
23918#define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk
23919#define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos)
23920#define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos)
23921#define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos)
23922#define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos)
23924/******************* Bit definition for TIM3_AF1 register *********************/
23925#define TIM3_AF1_ETRSEL_Pos (14U)
23926#define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos)
23927#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk
23928#define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos)
23929#define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos)
23930#define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos)
23931#define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos)
23933/******************* Bit definition for TIM5_AF1 register *********************/
23934#define TIM5_AF1_ETRSEL_Pos (14U)
23935#define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos)
23936#define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk
23937#define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos)
23938#define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos)
23939#define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos)
23940#define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos)
23942/******************* Bit definition for TIM15_AF1 register *********************/
23943#define TIM15_AF1_BKINE_Pos (0U)
23944#define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos)
23945#define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk
23946#define TIM15_AF1_BKCMP1E_Pos (1U)
23947#define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos)
23948#define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk
23949#define TIM15_AF1_BKCMP2E_Pos (2U)
23950#define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos)
23951#define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk
23952#define TIM15_AF1_BKDF1BK2E_Pos (8U)
23953#define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)
23954#define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk
23955#define TIM15_AF1_BKINP_Pos (9U)
23956#define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos)
23957#define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk
23958#define TIM15_AF1_BKCMP1P_Pos (10U)
23959#define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos)
23960#define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk
23961#define TIM15_AF1_BKCMP2P_Pos (11U)
23962#define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos)
23963#define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk
23965/******************* Bit definition for TIM16_ register *********************/
23966#define TIM16_AF1_BKINE_Pos (0U)
23967#define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos)
23968#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk
23969#define TIM16_AF1_BKCMP1E_Pos (1U)
23970#define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos)
23971#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk
23972#define TIM16_AF1_BKCMP2E_Pos (2U)
23973#define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos)
23974#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk
23975#define TIM16_AF1_BKDF1BK2E_Pos (8U)
23976#define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)
23977#define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk
23978#define TIM16_AF1_BKINP_Pos (9U)
23979#define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos)
23980#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk
23981#define TIM16_AF1_BKCMP1P_Pos (10U)
23982#define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos)
23983#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk
23984#define TIM16_AF1_BKCMP2P_Pos (11U)
23985#define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos)
23986#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk
23988/******************* Bit definition for TIM17_AF1 register *********************/
23989#define TIM17_AF1_BKINE_Pos (0U)
23990#define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos)
23991#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk
23992#define TIM17_AF1_BKCMP1E_Pos (1U)
23993#define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos)
23994#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk
23995#define TIM17_AF1_BKCMP2E_Pos (2U)
23996#define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos)
23997#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk
23998#define TIM17_AF1_BKDF1BK2E_Pos (8U)
23999#define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)
24000#define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk
24001#define TIM17_AF1_BKINP_Pos (9U)
24002#define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos)
24003#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk
24004#define TIM17_AF1_BKCMP1P_Pos (10U)
24005#define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos)
24006#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk
24007#define TIM17_AF1_BKCMP2P_Pos (11U)
24008#define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos)
24009#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk
24011/******************************************************************************/
24012/* */
24013/* Low Power Timer (LPTTIM) */
24014/* */
24015/******************************************************************************/
24016/****************** Bit definition for LPTIM_ISR register *******************/
24017#define LPTIM_ISR_CMPM_Pos (0U)
24018#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
24019#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
24020#define LPTIM_ISR_ARRM_Pos (1U)
24021#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
24022#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
24023#define LPTIM_ISR_EXTTRIG_Pos (2U)
24024#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
24025#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
24026#define LPTIM_ISR_CMPOK_Pos (3U)
24027#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
24028#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
24029#define LPTIM_ISR_ARROK_Pos (4U)
24030#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
24031#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
24032#define LPTIM_ISR_UP_Pos (5U)
24033#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
24034#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
24035#define LPTIM_ISR_DOWN_Pos (6U)
24036#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
24037#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
24039/****************** Bit definition for LPTIM_ICR register *******************/
24040#define LPTIM_ICR_CMPMCF_Pos (0U)
24041#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
24042#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
24043#define LPTIM_ICR_ARRMCF_Pos (1U)
24044#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
24045#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
24046#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
24047#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
24048#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
24049#define LPTIM_ICR_CMPOKCF_Pos (3U)
24050#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
24051#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
24052#define LPTIM_ICR_ARROKCF_Pos (4U)
24053#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
24054#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
24055#define LPTIM_ICR_UPCF_Pos (5U)
24056#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
24057#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
24058#define LPTIM_ICR_DOWNCF_Pos (6U)
24059#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
24060#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
24062/****************** Bit definition for LPTIM_IER register ********************/
24063#define LPTIM_IER_CMPMIE_Pos (0U)
24064#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
24065#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
24066#define LPTIM_IER_ARRMIE_Pos (1U)
24067#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
24068#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
24069#define LPTIM_IER_EXTTRIGIE_Pos (2U)
24070#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
24071#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
24072#define LPTIM_IER_CMPOKIE_Pos (3U)
24073#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
24074#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
24075#define LPTIM_IER_ARROKIE_Pos (4U)
24076#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
24077#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
24078#define LPTIM_IER_UPIE_Pos (5U)
24079#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
24080#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
24081#define LPTIM_IER_DOWNIE_Pos (6U)
24082#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
24083#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
24085/****************** Bit definition for LPTIM_CFGR register *******************/
24086#define LPTIM_CFGR_CKSEL_Pos (0U)
24087#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
24088#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
24090#define LPTIM_CFGR_CKPOL_Pos (1U)
24091#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
24092#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
24093#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
24094#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
24096#define LPTIM_CFGR_CKFLT_Pos (3U)
24097#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
24098#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
24099#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
24100#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
24102#define LPTIM_CFGR_TRGFLT_Pos (6U)
24103#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
24104#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
24105#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
24106#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
24108#define LPTIM_CFGR_PRESC_Pos (9U)
24109#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
24110#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
24111#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
24112#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
24113#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
24115#define LPTIM_CFGR_TRIGSEL_Pos (13U)
24116#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
24117#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
24118#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
24119#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
24120#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
24122#define LPTIM_CFGR_TRIGEN_Pos (17U)
24123#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
24124#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
24125#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
24126#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
24128#define LPTIM_CFGR_TIMOUT_Pos (19U)
24129#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
24130#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
24131#define LPTIM_CFGR_WAVE_Pos (20U)
24132#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
24133#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
24134#define LPTIM_CFGR_WAVPOL_Pos (21U)
24135#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
24136#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
24137#define LPTIM_CFGR_PRELOAD_Pos (22U)
24138#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
24139#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
24140#define LPTIM_CFGR_COUNTMODE_Pos (23U)
24141#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
24142#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
24143#define LPTIM_CFGR_ENC_Pos (24U)
24144#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
24145#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
24147/****************** Bit definition for LPTIM_CR register ********************/
24148#define LPTIM_CR_ENABLE_Pos (0U)
24149#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
24150#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
24151#define LPTIM_CR_SNGSTRT_Pos (1U)
24152#define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos)
24153#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
24154#define LPTIM_CR_CNTSTRT_Pos (2U)
24155#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
24156#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
24157#define LPTIM_CR_COUNTRST_Pos (3U)
24158#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos)
24159#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk
24160#define LPTIM_CR_RSTARE_Pos (4U)
24161#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos)
24162#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk
24165/****************** Bit definition for LPTIM_CMP register *******************/
24166#define LPTIM_CMP_CMP_Pos (0U)
24167#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
24168#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
24170/****************** Bit definition for LPTIM_ARR register *******************/
24171#define LPTIM_ARR_ARR_Pos (0U)
24172#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
24173#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
24175/****************** Bit definition for LPTIM_CNT register *******************/
24176#define LPTIM_CNT_CNT_Pos (0U)
24177#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
24178#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
24180/****************** Bit definition for LPTIM_CFGR2 register *****************/
24181#define LPTIM_CFGR2_IN1SEL_Pos (0U)
24182#define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)
24183#define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk
24184#define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)
24185#define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)
24186#define LPTIM_CFGR2_IN2SEL_Pos (4U)
24187#define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)
24188#define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk
24189#define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)
24190#define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)
24192/******************************************************************************/
24193/* */
24194/* Analog Comparators (COMP) */
24195/* */
24196/******************************************************************************/
24197
24198/******************* Bit definition for COMP_SR register ********************/
24199#define COMP_SR_C1VAL_Pos (0U)
24200#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos)
24201#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
24202#define COMP_SR_C2VAL_Pos (1U)
24203#define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos)
24204#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
24205#define COMP_SR_C1IF_Pos (16U)
24206#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos)
24207#define COMP_SR_C1IF COMP_SR_C1IF_Msk
24208#define COMP_SR_C2IF_Pos (17U)
24209#define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos)
24210#define COMP_SR_C2IF COMP_SR_C2IF_Msk
24211/******************* Bit definition for COMP_ICFR register ********************/
24212#define COMP_ICFR_C1IF_Pos (16U)
24213#define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos)
24214#define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
24215#define COMP_ICFR_C2IF_Pos (17U)
24216#define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos)
24217#define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
24218/******************* Bit definition for COMP_OR register ********************/
24219#define COMP_OR_AFOPA6_Pos (0U)
24220#define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos)
24221#define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
24222#define COMP_OR_AFOPA8_Pos (1U)
24223#define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos)
24224#define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
24225#define COMP_OR_AFOPB12_Pos (2U)
24226#define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos)
24227#define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
24228#define COMP_OR_AFOPE6_Pos (3U)
24229#define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos)
24230#define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
24231#define COMP_OR_AFOPE15_Pos (4U)
24232#define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos)
24233#define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
24234#define COMP_OR_AFOPG2_Pos (5U)
24235#define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos)
24236#define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
24237#define COMP_OR_AFOPG3_Pos (6U)
24238#define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos)
24239#define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
24240#define COMP_OR_AFOPG4_Pos (7U)
24241#define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos)
24242#define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
24243#define COMP_OR_AFOPI1_Pos (8U)
24244#define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos)
24245#define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
24246#define COMP_OR_AFOPI4_Pos (9U)
24247#define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos)
24248#define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
24249#define COMP_OR_AFOPK2_Pos (10U)
24250#define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos)
24251#define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
24252
24254#define COMP_CFGRx_EN_Pos (0U)
24255#define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos)
24256#define COMP_CFGRx_EN COMP_CFGRx_EN_Msk
24257#define COMP_CFGRx_BRGEN_Pos (1U)
24258#define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos)
24259#define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk
24260#define COMP_CFGRx_SCALEN_Pos (2U)
24261#define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos)
24262#define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk
24263#define COMP_CFGRx_POLARITY_Pos (3U)
24264#define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos)
24265#define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk
24266#define COMP_CFGRx_WINMODE_Pos (4U)
24267#define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos)
24268#define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk
24269#define COMP_CFGRx_ITEN_Pos (6U)
24270#define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos)
24271#define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk
24272#define COMP_CFGRx_HYST_Pos (8U)
24273#define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos)
24274#define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk
24275#define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos)
24276#define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos)
24277#define COMP_CFGRx_PWRMODE_Pos (12U)
24278#define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos)
24279#define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk
24280#define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos)
24281#define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos)
24282#define COMP_CFGRx_INMSEL_Pos (16U)
24283#define COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos)
24284#define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk
24285#define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos)
24286#define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos)
24287#define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos)
24288#define COMP_CFGRx_INPSEL_Pos (20U)
24289#define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos)
24290#define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk
24291#define COMP_CFGRx_BLANKING_Pos (24U)
24292#define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos)
24293#define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk
24294#define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos)
24295#define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos)
24296#define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos)
24297#define COMP_CFGRx_LOCK_Pos (31U)
24298#define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos)
24299#define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk
24302/******************************************************************************/
24303/* */
24304/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
24305/* */
24306/******************************************************************************/
24307/****************** Bit definition for USART_CR1 register *******************/
24308#define USART_CR1_UE_Pos (0U)
24309#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
24310#define USART_CR1_UE USART_CR1_UE_Msk
24311#define USART_CR1_UESM_Pos (1U)
24312#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
24313#define USART_CR1_UESM USART_CR1_UESM_Msk
24314#define USART_CR1_RE_Pos (2U)
24315#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
24316#define USART_CR1_RE USART_CR1_RE_Msk
24317#define USART_CR1_TE_Pos (3U)
24318#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
24319#define USART_CR1_TE USART_CR1_TE_Msk
24320#define USART_CR1_IDLEIE_Pos (4U)
24321#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
24322#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
24323#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
24324#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos)
24325#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk
24326#define USART_CR1_TCIE_Pos (6U)
24327#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
24328#define USART_CR1_TCIE USART_CR1_TCIE_Msk
24329#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
24330#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)
24331#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk
24332#define USART_CR1_PEIE_Pos (8U)
24333#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
24334#define USART_CR1_PEIE USART_CR1_PEIE_Msk
24335#define USART_CR1_PS_Pos (9U)
24336#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
24337#define USART_CR1_PS USART_CR1_PS_Msk
24338#define USART_CR1_PCE_Pos (10U)
24339#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
24340#define USART_CR1_PCE USART_CR1_PCE_Msk
24341#define USART_CR1_WAKE_Pos (11U)
24342#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
24343#define USART_CR1_WAKE USART_CR1_WAKE_Msk
24344#define USART_CR1_M_Pos (12U)
24345#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
24346#define USART_CR1_M USART_CR1_M_Msk
24347#define USART_CR1_M0_Pos (12U)
24348#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
24349#define USART_CR1_M0 USART_CR1_M0_Msk
24350#define USART_CR1_MME_Pos (13U)
24351#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
24352#define USART_CR1_MME USART_CR1_MME_Msk
24353#define USART_CR1_CMIE_Pos (14U)
24354#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
24355#define USART_CR1_CMIE USART_CR1_CMIE_Msk
24356#define USART_CR1_OVER8_Pos (15U)
24357#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
24358#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
24359#define USART_CR1_DEDT_Pos (16U)
24360#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
24361#define USART_CR1_DEDT USART_CR1_DEDT_Msk
24362#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
24363#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
24364#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
24365#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
24366#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
24367#define USART_CR1_DEAT_Pos (21U)
24368#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
24369#define USART_CR1_DEAT USART_CR1_DEAT_Msk
24370#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
24371#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
24372#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
24373#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
24374#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
24375#define USART_CR1_RTOIE_Pos (26U)
24376#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
24377#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
24378#define USART_CR1_EOBIE_Pos (27U)
24379#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
24380#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
24381#define USART_CR1_M1_Pos (28U)
24382#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
24383#define USART_CR1_M1 USART_CR1_M1_Msk
24384#define USART_CR1_FIFOEN_Pos (29U)
24385#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos)
24386#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk
24387#define USART_CR1_TXFEIE_Pos (30U)
24388#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos)
24389#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk
24390#define USART_CR1_RXFFIE_Pos (31U)
24391#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos)
24392#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk
24394/* Legacy define */
24395#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
24396#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
24397
24398/****************** Bit definition for USART_CR2 register *******************/
24399#define USART_CR2_SLVEN_Pos (0U)
24400#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos)
24401#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk
24402#define USART_CR2_DIS_NSS_Pos (3U)
24403#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos)
24404#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk
24405#define USART_CR2_ADDM7_Pos (4U)
24406#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
24407#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
24408#define USART_CR2_LBDL_Pos (5U)
24409#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
24410#define USART_CR2_LBDL USART_CR2_LBDL_Msk
24411#define USART_CR2_LBDIE_Pos (6U)
24412#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
24413#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
24414#define USART_CR2_LBCL_Pos (8U)
24415#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
24416#define USART_CR2_LBCL USART_CR2_LBCL_Msk
24417#define USART_CR2_CPHA_Pos (9U)
24418#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
24419#define USART_CR2_CPHA USART_CR2_CPHA_Msk
24420#define USART_CR2_CPOL_Pos (10U)
24421#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
24422#define USART_CR2_CPOL USART_CR2_CPOL_Msk
24423#define USART_CR2_CLKEN_Pos (11U)
24424#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
24425#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
24426#define USART_CR2_STOP_Pos (12U)
24427#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
24428#define USART_CR2_STOP USART_CR2_STOP_Msk
24429#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
24430#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
24431#define USART_CR2_LINEN_Pos (14U)
24432#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
24433#define USART_CR2_LINEN USART_CR2_LINEN_Msk
24434#define USART_CR2_SWAP_Pos (15U)
24435#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
24436#define USART_CR2_SWAP USART_CR2_SWAP_Msk
24437#define USART_CR2_RXINV_Pos (16U)
24438#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
24439#define USART_CR2_RXINV USART_CR2_RXINV_Msk
24440#define USART_CR2_TXINV_Pos (17U)
24441#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
24442#define USART_CR2_TXINV USART_CR2_TXINV_Msk
24443#define USART_CR2_DATAINV_Pos (18U)
24444#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
24445#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
24446#define USART_CR2_MSBFIRST_Pos (19U)
24447#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
24448#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
24449#define USART_CR2_ABREN_Pos (20U)
24450#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
24451#define USART_CR2_ABREN USART_CR2_ABREN_Msk
24452#define USART_CR2_ABRMODE_Pos (21U)
24453#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
24454#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
24455#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
24456#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
24457#define USART_CR2_RTOEN_Pos (23U)
24458#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
24459#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
24460#define USART_CR2_ADD_Pos (24U)
24461#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
24462#define USART_CR2_ADD USART_CR2_ADD_Msk
24464/****************** Bit definition for USART_CR3 register *******************/
24465#define USART_CR3_EIE_Pos (0U)
24466#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
24467#define USART_CR3_EIE USART_CR3_EIE_Msk
24468#define USART_CR3_IREN_Pos (1U)
24469#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
24470#define USART_CR3_IREN USART_CR3_IREN_Msk
24471#define USART_CR3_IRLP_Pos (2U)
24472#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
24473#define USART_CR3_IRLP USART_CR3_IRLP_Msk
24474#define USART_CR3_HDSEL_Pos (3U)
24475#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
24476#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
24477#define USART_CR3_NACK_Pos (4U)
24478#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
24479#define USART_CR3_NACK USART_CR3_NACK_Msk
24480#define USART_CR3_SCEN_Pos (5U)
24481#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
24482#define USART_CR3_SCEN USART_CR3_SCEN_Msk
24483#define USART_CR3_DMAR_Pos (6U)
24484#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
24485#define USART_CR3_DMAR USART_CR3_DMAR_Msk
24486#define USART_CR3_DMAT_Pos (7U)
24487#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
24488#define USART_CR3_DMAT USART_CR3_DMAT_Msk
24489#define USART_CR3_RTSE_Pos (8U)
24490#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
24491#define USART_CR3_RTSE USART_CR3_RTSE_Msk
24492#define USART_CR3_CTSE_Pos (9U)
24493#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
24494#define USART_CR3_CTSE USART_CR3_CTSE_Msk
24495#define USART_CR3_CTSIE_Pos (10U)
24496#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
24497#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
24498#define USART_CR3_ONEBIT_Pos (11U)
24499#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
24500#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
24501#define USART_CR3_OVRDIS_Pos (12U)
24502#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
24503#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
24504#define USART_CR3_DDRE_Pos (13U)
24505#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
24506#define USART_CR3_DDRE USART_CR3_DDRE_Msk
24507#define USART_CR3_DEM_Pos (14U)
24508#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
24509#define USART_CR3_DEM USART_CR3_DEM_Msk
24510#define USART_CR3_DEP_Pos (15U)
24511#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
24512#define USART_CR3_DEP USART_CR3_DEP_Msk
24513#define USART_CR3_SCARCNT_Pos (17U)
24514#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
24515#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
24516#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
24517#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
24518#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
24519#define USART_CR3_WUS_Pos (20U)
24520#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
24521#define USART_CR3_WUS USART_CR3_WUS_Msk
24522#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
24523#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
24524#define USART_CR3_WUFIE_Pos (22U)
24525#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
24526#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
24527#define USART_CR3_TXFTIE_Pos (23U)
24528#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos)
24529#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk
24530#define USART_CR3_TCBGTIE_Pos (24U)
24531#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)
24532#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk
24533#define USART_CR3_RXFTCFG_Pos (25U)
24534#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos)
24535#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk
24536#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos)
24537#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos)
24538#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos)
24539#define USART_CR3_RXFTIE_Pos (28U)
24540#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos)
24541#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk
24542#define USART_CR3_TXFTCFG_Pos (29U)
24543#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos)
24544#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk
24545#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos)
24546#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos)
24547#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos)
24549/****************** Bit definition for USART_BRR register *******************/
24550#define USART_BRR_DIV_FRACTION_Pos (0U)
24551#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
24552#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
24553#define USART_BRR_DIV_MANTISSA_Pos (4U)
24554#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
24555#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
24557/****************** Bit definition for USART_GTPR register ******************/
24558#define USART_GTPR_PSC_Pos (0U)
24559#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
24560#define USART_GTPR_PSC USART_GTPR_PSC_Msk
24561#define USART_GTPR_GT_Pos (8U)
24562#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
24563#define USART_GTPR_GT USART_GTPR_GT_Msk
24565/******************* Bit definition for USART_RTOR register *****************/
24566#define USART_RTOR_RTO_Pos (0U)
24567#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
24568#define USART_RTOR_RTO USART_RTOR_RTO_Msk
24569#define USART_RTOR_BLEN_Pos (24U)
24570#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
24571#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
24573/******************* Bit definition for USART_RQR register ******************/
24574#define USART_RQR_ABRRQ_Pos (0U)
24575#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
24576#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
24577#define USART_RQR_SBKRQ_Pos (1U)
24578#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
24579#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
24580#define USART_RQR_MMRQ_Pos (2U)
24581#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
24582#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
24583#define USART_RQR_RXFRQ_Pos (3U)
24584#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
24585#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
24586#define USART_RQR_TXFRQ_Pos (4U)
24587#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
24588#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
24590/******************* Bit definition for USART_ISR register ******************/
24591#define USART_ISR_PE_Pos (0U)
24592#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
24593#define USART_ISR_PE USART_ISR_PE_Msk
24594#define USART_ISR_FE_Pos (1U)
24595#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
24596#define USART_ISR_FE USART_ISR_FE_Msk
24597#define USART_ISR_NE_Pos (2U)
24598#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
24599#define USART_ISR_NE USART_ISR_NE_Msk
24600#define USART_ISR_ORE_Pos (3U)
24601#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
24602#define USART_ISR_ORE USART_ISR_ORE_Msk
24603#define USART_ISR_IDLE_Pos (4U)
24604#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
24605#define USART_ISR_IDLE USART_ISR_IDLE_Msk
24606#define USART_ISR_RXNE_RXFNE_Pos (5U)
24607#define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos)
24608#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk
24609#define USART_ISR_TC_Pos (6U)
24610#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
24611#define USART_ISR_TC USART_ISR_TC_Msk
24612#define USART_ISR_TXE_TXFNF_Pos (7U)
24613#define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos)
24614#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk
24615#define USART_ISR_LBDF_Pos (8U)
24616#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
24617#define USART_ISR_LBDF USART_ISR_LBDF_Msk
24618#define USART_ISR_CTSIF_Pos (9U)
24619#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
24620#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
24621#define USART_ISR_CTS_Pos (10U)
24622#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
24623#define USART_ISR_CTS USART_ISR_CTS_Msk
24624#define USART_ISR_RTOF_Pos (11U)
24625#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
24626#define USART_ISR_RTOF USART_ISR_RTOF_Msk
24627#define USART_ISR_EOBF_Pos (12U)
24628#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
24629#define USART_ISR_EOBF USART_ISR_EOBF_Msk
24630#define USART_ISR_UDR_Pos (13U)
24631#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos)
24632#define USART_ISR_UDR USART_ISR_UDR_Msk
24633#define USART_ISR_ABRE_Pos (14U)
24634#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
24635#define USART_ISR_ABRE USART_ISR_ABRE_Msk
24636#define USART_ISR_ABRF_Pos (15U)
24637#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
24638#define USART_ISR_ABRF USART_ISR_ABRF_Msk
24639#define USART_ISR_BUSY_Pos (16U)
24640#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
24641#define USART_ISR_BUSY USART_ISR_BUSY_Msk
24642#define USART_ISR_CMF_Pos (17U)
24643#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
24644#define USART_ISR_CMF USART_ISR_CMF_Msk
24645#define USART_ISR_SBKF_Pos (18U)
24646#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
24647#define USART_ISR_SBKF USART_ISR_SBKF_Msk
24648#define USART_ISR_RWU_Pos (19U)
24649#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
24650#define USART_ISR_RWU USART_ISR_RWU_Msk
24651#define USART_ISR_WUF_Pos (20U)
24652#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
24653#define USART_ISR_WUF USART_ISR_WUF_Msk
24654#define USART_ISR_TEACK_Pos (21U)
24655#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
24656#define USART_ISR_TEACK USART_ISR_TEACK_Msk
24657#define USART_ISR_REACK_Pos (22U)
24658#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
24659#define USART_ISR_REACK USART_ISR_REACK_Msk
24660#define USART_ISR_TXFE_Pos (23U)
24661#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos)
24662#define USART_ISR_TXFE USART_ISR_TXFE_Msk
24663#define USART_ISR_RXFF_Pos (24U)
24664#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos)
24665#define USART_ISR_RXFF USART_ISR_RXFF_Msk
24666#define USART_ISR_TCBGT_Pos (25U)
24667#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)
24668#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk
24669#define USART_ISR_RXFT_Pos (26U)
24670#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos)
24671#define USART_ISR_RXFT USART_ISR_RXFT_Msk
24672#define USART_ISR_TXFT_Pos (27U)
24673#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos)
24674#define USART_ISR_TXFT USART_ISR_TXFT_Msk
24676/******************* Bit definition for USART_ICR register ******************/
24677#define USART_ICR_PECF_Pos (0U)
24678#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
24679#define USART_ICR_PECF USART_ICR_PECF_Msk
24680#define USART_ICR_FECF_Pos (1U)
24681#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
24682#define USART_ICR_FECF USART_ICR_FECF_Msk
24683#define USART_ICR_NECF_Pos (2U)
24684#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)
24685#define USART_ICR_NECF USART_ICR_NECF_Msk
24686#define USART_ICR_ORECF_Pos (3U)
24687#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
24688#define USART_ICR_ORECF USART_ICR_ORECF_Msk
24689#define USART_ICR_IDLECF_Pos (4U)
24690#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
24691#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
24692#define USART_ICR_TXFECF_Pos (5U)
24693#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos)
24694#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk
24695#define USART_ICR_TCCF_Pos (6U)
24696#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
24697#define USART_ICR_TCCF USART_ICR_TCCF_Msk
24698#define USART_ICR_TCBGTCF_Pos (7U)
24699#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)
24700#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk
24701#define USART_ICR_LBDCF_Pos (8U)
24702#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
24703#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
24704#define USART_ICR_CTSCF_Pos (9U)
24705#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
24706#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
24707#define USART_ICR_RTOCF_Pos (11U)
24708#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
24709#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
24710#define USART_ICR_EOBCF_Pos (12U)
24711#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
24712#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
24713#define USART_ICR_UDRCF_Pos (13U)
24714#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos)
24715#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk
24716#define USART_ICR_CMCF_Pos (17U)
24717#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
24718#define USART_ICR_CMCF USART_ICR_CMCF_Msk
24719#define USART_ICR_WUCF_Pos (20U)
24720#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
24721#define USART_ICR_WUCF USART_ICR_WUCF_Msk
24723/******************* Bit definition for USART_RDR register ******************/
24724#define USART_RDR_RDR_Pos (0U)
24725#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
24726#define USART_RDR_RDR USART_RDR_RDR_Msk
24728/******************* Bit definition for USART_TDR register ******************/
24729#define USART_TDR_TDR_Pos (0U)
24730#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
24731#define USART_TDR_TDR USART_TDR_TDR_Msk
24733/******************* Bit definition for USART_PRESC register ******************/
24734#define USART_PRESC_PRESCALER_Pos (0U)
24735#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos)
24736#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk
24737#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos)
24738#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos)
24739#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos)
24740#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos)
24742/******************************************************************************/
24743/* */
24744/* Single Wire Protocol Master Interface (SWPMI) */
24745/* */
24746/******************************************************************************/
24747
24748/******************* Bit definition for SWPMI_CR register ********************/
24749#define SWPMI_CR_RXDMA_Pos (0U)
24750#define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos)
24751#define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk
24752#define SWPMI_CR_TXDMA_Pos (1U)
24753#define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos)
24754#define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk
24755#define SWPMI_CR_RXMODE_Pos (2U)
24756#define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos)
24757#define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk
24758#define SWPMI_CR_TXMODE_Pos (3U)
24759#define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos)
24760#define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk
24761#define SWPMI_CR_LPBK_Pos (4U)
24762#define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos)
24763#define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk
24764#define SWPMI_CR_SWPACT_Pos (5U)
24765#define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos)
24766#define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk
24767#define SWPMI_CR_DEACT_Pos (10U)
24768#define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos)
24769#define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk
24770#define SWPMI_CR_SWPEN_Pos (11U)
24771#define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos)
24772#define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk
24774/******************* Bit definition for SWPMI_BRR register ********************/
24775#define SWPMI_BRR_BR_Pos (0U)
24776#define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos)
24777#define SWPMI_BRR_BR SWPMI_BRR_BR_Msk
24779/******************* Bit definition for SWPMI_ISR register ********************/
24780#define SWPMI_ISR_RXBFF_Pos (0U)
24781#define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos)
24782#define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk
24783#define SWPMI_ISR_TXBEF_Pos (1U)
24784#define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos)
24785#define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk
24786#define SWPMI_ISR_RXBERF_Pos (2U)
24787#define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos)
24788#define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk
24789#define SWPMI_ISR_RXOVRF_Pos (3U)
24790#define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos)
24791#define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk
24792#define SWPMI_ISR_TXUNRF_Pos (4U)
24793#define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos)
24794#define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk
24795#define SWPMI_ISR_RXNE_Pos (5U)
24796#define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos)
24797#define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk
24798#define SWPMI_ISR_TXE_Pos (6U)
24799#define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos)
24800#define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk
24801#define SWPMI_ISR_TCF_Pos (7U)
24802#define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos)
24803#define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk
24804#define SWPMI_ISR_SRF_Pos (8U)
24805#define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos)
24806#define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk
24807#define SWPMI_ISR_SUSP_Pos (9U)
24808#define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos)
24809#define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk
24810#define SWPMI_ISR_DEACTF_Pos (10U)
24811#define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos)
24812#define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk
24813#define SWPMI_ISR_RDYF_Pos (11U)
24814#define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos)
24815#define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk
24817/******************* Bit definition for SWPMI_ICR register ********************/
24818#define SWPMI_ICR_CRXBFF_Pos (0U)
24819#define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos)
24820#define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk
24821#define SWPMI_ICR_CTXBEF_Pos (1U)
24822#define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos)
24823#define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk
24824#define SWPMI_ICR_CRXBERF_Pos (2U)
24825#define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos)
24826#define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk
24827#define SWPMI_ICR_CRXOVRF_Pos (3U)
24828#define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos)
24829#define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk
24830#define SWPMI_ICR_CTXUNRF_Pos (4U)
24831#define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos)
24832#define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk
24833#define SWPMI_ICR_CTCF_Pos (7U)
24834#define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos)
24835#define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk
24836#define SWPMI_ICR_CSRF_Pos (8U)
24837#define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos)
24838#define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk
24839#define SWPMI_ICR_CRDYF_Pos (11U)
24840#define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos)
24841#define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk
24843/******************* Bit definition for SWPMI_IER register ********************/
24844#define SWPMI_IER_RXBFIE_Pos (0U)
24845#define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos)
24846#define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk
24847#define SWPMI_IER_TXBEIE_Pos (1U)
24848#define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos)
24849#define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk
24850#define SWPMI_IER_RXBERIE_Pos (2U)
24851#define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos)
24852#define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk
24853#define SWPMI_IER_RXOVRIE_Pos (3U)
24854#define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos)
24855#define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk
24856#define SWPMI_IER_TXUNRIE_Pos (4U)
24857#define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos)
24858#define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk
24859#define SWPMI_IER_RIE_Pos (5U)
24860#define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos)
24861#define SWPMI_IER_RIE SWPMI_IER_RIE_Msk
24862#define SWPMI_IER_TIE_Pos (6U)
24863#define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos)
24864#define SWPMI_IER_TIE SWPMI_IER_TIE_Msk
24865#define SWPMI_IER_TCIE_Pos (7U)
24866#define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos)
24867#define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk
24868#define SWPMI_IER_SRIE_Pos (8U)
24869#define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos)
24870#define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk
24871#define SWPMI_IER_RDYIE_Pos (11U)
24872#define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos)
24873#define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk
24875/******************* Bit definition for SWPMI_RFL register ********************/
24876#define SWPMI_RFL_RFL_Pos (0U)
24877#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos)
24878#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk
24879#define SWPMI_RFL_RFL_0_1 (0x00000003U)
24881/******************* Bit definition for SWPMI_TDR register ********************/
24882#define SWPMI_TDR_TD_Pos (0U)
24883#define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)
24884#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk
24886/******************* Bit definition for SWPMI_RDR register ********************/
24887#define SWPMI_RDR_RD_Pos (0U)
24888#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)
24889#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk
24892/******************* Bit definition for SWPMI_OR register ********************/
24893#define SWPMI_OR_TBYP_Pos (0U)
24894#define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos)
24895#define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk
24896#define SWPMI_OR_CLASS_Pos (1U)
24897#define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos)
24898#define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk
24900/******************************************************************************/
24901/* */
24902/* Window WATCHDOG */
24903/* */
24904/******************************************************************************/
24905/******************* Bit definition for WWDG_CR register ********************/
24906#define WWDG_CR_T_Pos (0U)
24907#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
24908#define WWDG_CR_T WWDG_CR_T_Msk
24909#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
24910#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
24911#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
24912#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
24913#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
24914#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
24915#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
24917#define WWDG_CR_WDGA_Pos (7U)
24918#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
24919#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
24921/******************* Bit definition for WWDG_CFR register *******************/
24922#define WWDG_CFR_W_Pos (0U)
24923#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
24924#define WWDG_CFR_W WWDG_CFR_W_Msk
24925#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
24926#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
24927#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
24928#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
24929#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
24930#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
24931#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
24933#define WWDG_CFR_EWI_Pos (9U)
24934#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
24935#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
24937#define WWDG_CFR_WDGTB_Pos (11U)
24938#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos)
24939#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
24940#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
24941#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
24942#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos)
24944/******************* Bit definition for WWDG_SR register ********************/
24945#define WWDG_SR_EWIF_Pos (0U)
24946#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
24947#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
24950/******************************************************************************/
24951/* */
24952/* DBG */
24953/* */
24954/******************************************************************************/
24955/********************************* DEVICE ID ********************************/
24956#define STM32H7_DEV_ID 0x450UL
24957
24958/******************** Bit definition for DBGMCU_IDCODE register *************/
24959#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
24960#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
24961#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
24962#define DBGMCU_IDCODE_REV_ID_Pos (16U)
24963#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
24964#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
24965
24966/******************** Bit definition for DBGMCU_CR register *****************/
24967#define DBGMCU_CR_DBG_SLEEPD1_Pos (0U)
24968#define DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos)
24969#define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk
24970#define DBGMCU_CR_DBG_STOPD1_Pos (1U)
24971#define DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)
24972#define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk
24973#define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
24974#define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos)
24975#define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
24976#define DBGMCU_CR_DBG_SLEEPD2_Pos (3U)
24977#define DBGMCU_CR_DBG_SLEEPD2_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD2_Pos)
24978#define DBGMCU_CR_DBG_SLEEPD2 DBGMCU_CR_DBG_SLEEPD2_Msk
24979#define DBGMCU_CR_DBG_STOPD2_Pos (4U)
24980#define DBGMCU_CR_DBG_STOPD2_Msk (0x1UL << DBGMCU_CR_DBG_STOPD2_Pos)
24981#define DBGMCU_CR_DBG_STOPD2 DBGMCU_CR_DBG_STOPD2_Msk
24982#define DBGMCU_CR_DBG_STANDBYD2_Pos (5U)
24983#define DBGMCU_CR_DBG_STANDBYD2_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos)
24984#define DBGMCU_CR_DBG_STANDBYD2 DBGMCU_CR_DBG_STANDBYD2_Msk
24985#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
24986#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos)
24987#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
24988#define DBGMCU_CR_DBG_CKD1EN_Pos (21U)
24989#define DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)
24990#define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk
24991#define DBGMCU_CR_DBG_CKD3EN_Pos (22U)
24992#define DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)
24993#define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk
24994#define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
24995#define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)
24996#define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
24997
24998/******************** Bit definition for APB3FZ1 register ************/
24999#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
25000#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos)
25001#define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
25002/******************** Bit definition for APB3FZ2 register ************/
25003#define DBGMCU_APB3FZ2_DBG_WWDG1_Pos (6U)
25004#define DBGMCU_APB3FZ2_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ2_DBG_WWDG1_Pos)
25005#define DBGMCU_APB3FZ2_DBG_WWDG1 DBGMCU_APB3FZ2_DBG_WWDG1_Msk
25006/******************** Bit definition for APB1LFZ1 register ************/
25007#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
25008#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos)
25009#define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
25010#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
25011#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos)
25012#define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
25013#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
25014#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos)
25015#define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
25016#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
25017#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos)
25018#define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
25019#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
25020#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos)
25021#define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
25022#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
25023#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos)
25024#define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
25025#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
25026#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos)
25027#define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
25028#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
25029#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos)
25030#define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
25031#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
25032#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos)
25033#define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
25034#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
25035#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos)
25036#define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
25037#define DBGMCU_APB1LFZ1_DBG_WWDG2_Pos (11U)
25038#define DBGMCU_APB1LFZ1_DBG_WWDG2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG2_Pos)
25039#define DBGMCU_APB1LFZ1_DBG_WWDG2 DBGMCU_APB1LFZ1_DBG_WWDG2_Msk
25040#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
25041#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos)
25042#define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
25043#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
25044#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos)
25045#define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
25046#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
25047#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos)
25048#define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
25049
25050/******************** Bit definition for APB1LFZ2 register ************/
25051#define DBGMCU_APB1LFZ2_DBG_TIM2_Pos (0U)
25052#define DBGMCU_APB1LFZ2_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM2_Pos)
25053#define DBGMCU_APB1LFZ2_DBG_TIM2 DBGMCU_APB1LFZ2_DBG_TIM2_Msk
25054#define DBGMCU_APB1LFZ2_DBG_TIM3_Pos (1U)
25055#define DBGMCU_APB1LFZ2_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM3_Pos)
25056#define DBGMCU_APB1LFZ2_DBG_TIM3 DBGMCU_APB1LFZ2_DBG_TIM3_Msk
25057#define DBGMCU_APB1LFZ2_DBG_TIM4_Pos (2U)
25058#define DBGMCU_APB1LFZ2_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM4_Pos)
25059#define DBGMCU_APB1LFZ2_DBG_TIM4 DBGMCU_APB1LFZ2_DBG_TIM4_Msk
25060#define DBGMCU_APB1LFZ2_DBG_TIM5_Pos (3U)
25061#define DBGMCU_APB1LFZ2_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM5_Pos)
25062#define DBGMCU_APB1LFZ2_DBG_TIM5 DBGMCU_APB1LFZ2_DBG_TIM5_Msk
25063#define DBGMCU_APB1LFZ2_DBG_TIM6_Pos (4U)
25064#define DBGMCU_APB1LFZ2_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM6_Pos)
25065#define DBGMCU_APB1LFZ2_DBG_TIM6 DBGMCU_APB1LFZ2_DBG_TIM6_Msk
25066#define DBGMCU_APB1LFZ2_DBG_TIM7_Pos (5U)
25067#define DBGMCU_APB1LFZ2_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM7_Pos)
25068#define DBGMCU_APB1LFZ2_DBG_TIM7 DBGMCU_APB1LFZ2_DBG_TIM7_Msk
25069#define DBGMCU_APB1LFZ2_DBG_TIM12_Pos (6U)
25070#define DBGMCU_APB1LFZ2_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM12_Pos)
25071#define DBGMCU_APB1LFZ2_DBG_TIM12 DBGMCU_APB1LFZ2_DBG_TIM12_Msk
25072#define DBGMCU_APB1LFZ2_DBG_TIM13_Pos (7U)
25073#define DBGMCU_APB1LFZ2_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM13_Pos)
25074#define DBGMCU_APB1LFZ2_DBG_TIM13 DBGMCU_APB1LFZ2_DBG_TIM13_Msk
25075#define DBGMCU_APB1LFZ2_DBG_TIM14_Pos (8U)
25076#define DBGMCU_APB1LFZ2_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM14_Pos)
25077#define DBGMCU_APB1LFZ2_DBG_TIM14 DBGMCU_APB1LFZ2_DBG_TIM14_Msk
25078#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos (9U)
25079#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos)
25080#define DBGMCU_APB1LFZ2_DBG_LPTIM1 DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk
25081#define DBGMCU_APB1LFZ2_DBG_WWDG2_Pos (11U)
25082#define DBGMCU_APB1LFZ2_DBG_WWDG2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_WWDG2_Pos)
25083#define DBGMCU_APB1LFZ2_DBG_WWDG2 DBGMCU_APB1LFZ2_DBG_WWDG2_Msk
25084#define DBGMCU_APB1LFZ2_DBG_I2C1_Pos (21U)
25085#define DBGMCU_APB1LFZ2_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C1_Pos)
25086#define DBGMCU_APB1LFZ2_DBG_I2C1 DBGMCU_APB1LFZ2_DBG_I2C1_Msk
25087#define DBGMCU_APB1LFZ2_DBG_I2C2_Pos (22U)
25088#define DBGMCU_APB1LFZ2_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C2_Pos)
25089#define DBGMCU_APB1LFZ2_DBG_I2C2 DBGMCU_APB1LFZ2_DBG_I2C2_Msk
25090#define DBGMCU_APB1LFZ2_DBG_I2C3_Pos (23U)
25091#define DBGMCU_APB1LFZ2_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C3_Pos)
25092#define DBGMCU_APB1LFZ2_DBG_I2C3 DBGMCU_APB1LFZ2_DBG_I2C3_Msk
25093/******************** Bit definition for APB1HFZ1 register ************/
25094#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos (8U)
25095#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos)
25096#define DBGMCU_APB1HFZ1_DBG_FDCAN DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
25097/******************** Bit definition for APB1HFZ2 register ************/
25098#define DBGMCU_APB1HFZ2_DBG_FDCAN_Pos (8U)
25099#define DBGMCU_APB1HFZ2_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ2_DBG_FDCAN_Pos)
25100#define DBGMCU_APB1HFZ2_DBG_FDCAN DBGMCU_APB1HFZ2_DBG_FDCAN_Msk
25101
25102/******************** Bit definition for APB2FZ1 register ************/
25103#define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
25104#define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos)
25105#define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
25106#define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
25107#define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos)
25108#define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
25109#define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
25110#define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos)
25111#define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
25112#define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
25113#define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos)
25114#define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
25115#define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
25116#define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos)
25117#define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
25118#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos (29U)
25119#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos)
25120#define DBGMCU_APB2FZ1_DBG_HRTIM DBGMCU_APB2FZ1_DBG_HRTIM_Msk
25121
25122/******************** Bit definition for APB2FZ2 register ************/
25123#define DBGMCU_APB2FZ2_DBG_TIM1_Pos (0U)
25124#define DBGMCU_APB2FZ2_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM1_Pos)
25125#define DBGMCU_APB2FZ2_DBG_TIM1 DBGMCU_APB2FZ2_DBG_TIM1_Msk
25126#define DBGMCU_APB2FZ2_DBG_TIM8_Pos (1U)
25127#define DBGMCU_APB2FZ2_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM8_Pos)
25128#define DBGMCU_APB2FZ2_DBG_TIM8 DBGMCU_APB2FZ2_DBG_TIM8_Msk
25129#define DBGMCU_APB2FZ2_DBG_TIM15_Pos (16U)
25130#define DBGMCU_APB2FZ2_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM15_Pos)
25131#define DBGMCU_APB2FZ2_DBG_TIM15 DBGMCU_APB2FZ2_DBG_TIM15_Msk
25132#define DBGMCU_APB2FZ2_DBG_TIM16_Pos (17U)
25133#define DBGMCU_APB2FZ2_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM16_Pos)
25134#define DBGMCU_APB2FZ2_DBG_TIM16 DBGMCU_APB2FZ2_DBG_TIM16_Msk
25135#define DBGMCU_APB2FZ2_DBG_TIM17_Pos (18U)
25136#define DBGMCU_APB2FZ2_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM17_Pos)
25137#define DBGMCU_APB2FZ2_DBG_TIM17 DBGMCU_APB2FZ2_DBG_TIM17_Msk
25138#define DBGMCU_APB2FZ2_DBG_HRTIM_Pos (29U)
25139#define DBGMCU_APB2FZ2_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_HRTIM_Pos)
25140#define DBGMCU_APB2FZ2_DBG_HRTIM DBGMCU_APB2FZ2_DBG_HRTIM_Msk
25141/******************** Bit definition for APB4FZ1 register ************/
25142#define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
25143#define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos)
25144#define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
25145#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
25146#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos)
25147#define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
25148#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
25149#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos)
25150#define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
25151#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U)
25152#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos)
25153#define DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
25154#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U)
25155#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos)
25156#define DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
25157#define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
25158#define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos)
25159#define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
25160#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
25161#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos)
25162#define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
25163#define DBGMCU_APB4FZ1_DBG_IWDG2_Pos (19U)
25164#define DBGMCU_APB4FZ1_DBG_IWDG2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG2_Pos)
25165#define DBGMCU_APB4FZ1_DBG_IWDG2 DBGMCU_APB4FZ1_DBG_IWDG2_Msk
25166/******************** Bit definition for APB4FZ2 register ************/
25167#define DBGMCU_APB4FZ2_DBG_I2C4_Pos (7U)
25168#define DBGMCU_APB4FZ2_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_I2C4_Pos)
25169#define DBGMCU_APB4FZ2_DBG_I2C4 DBGMCU_APB4FZ2_DBG_I2C4_Msk
25170#define DBGMCU_APB4FZ2_DBG_LPTIM2_Pos (9U)
25171#define DBGMCU_APB4FZ2_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM2_Pos)
25172#define DBGMCU_APB4FZ2_DBG_LPTIM2 DBGMCU_APB4FZ2_DBG_LPTIM2_Msk
25173#define DBGMCU_APB4FZ2_DBG_LPTIM3_Pos (10U)
25174#define DBGMCU_APB4FZ2_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM3_Pos)
25175#define DBGMCU_APB4FZ2_DBG_LPTIM3 DBGMCU_APB4FZ2_DBG_LPTIM3_Msk
25176#define DBGMCU_APB4FZ2_DBG_LPTIM4_Pos (11U)
25177#define DBGMCU_APB4FZ2_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM4_Pos)
25178#define DBGMCU_APB4FZ2_DBG_LPTIM4 DBGMCU_APB4FZ2_DBG_LPTIM4_Msk
25179#define DBGMCU_APB4FZ2_DBG_LPTIM5_Pos (12U)
25180#define DBGMCU_APB4FZ2_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM5_Pos)
25181#define DBGMCU_APB4FZ2_DBG_LPTIM5 DBGMCU_APB4FZ2_DBG_LPTIM5_Msk
25182#define DBGMCU_APB4FZ2_DBG_RTC_Pos (16U)
25183#define DBGMCU_APB4FZ2_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_RTC_Pos)
25184#define DBGMCU_APB4FZ2_DBG_RTC DBGMCU_APB4FZ2_DBG_RTC_Msk
25185#define DBGMCU_APB4FZ2_DBG_IWDG1_Pos (18U)
25186#define DBGMCU_APB4FZ2_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG1_Pos)
25187#define DBGMCU_APB4FZ2_DBG_IWDG1 DBGMCU_APB4FZ2_DBG_IWDG1_Msk
25188#define DBGMCU_APB4FZ2_DBG_IWDG2_Pos (19U)
25189#define DBGMCU_APB4FZ2_DBG_IWDG2_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG2_Pos)
25190#define DBGMCU_APB4FZ2_DBG_IWDG2 DBGMCU_APB4FZ2_DBG_IWDG2_Msk
25191/******************************************************************************/
25192/* */
25193/* High Resolution Timer (HRTIM) */
25194/* */
25195/******************************************************************************/
25196/******************** Master Timer control register ***************************/
25197#define HRTIM_MCR_CK_PSC_Pos (0U)
25198#define HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos)
25199#define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk
25200#define HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos)
25201#define HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos)
25202#define HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos)
25204#define HRTIM_MCR_CONT_Pos (3U)
25205#define HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos)
25206#define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk
25207#define HRTIM_MCR_RETRIG_Pos (4U)
25208#define HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos)
25209#define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk
25210#define HRTIM_MCR_HALF_Pos (5U)
25211#define HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos)
25212#define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk
25214#define HRTIM_MCR_SYNC_IN_Pos (8U)
25215#define HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos)
25216#define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk
25217#define HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos)
25218#define HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos)
25219#define HRTIM_MCR_SYNCRSTM_Pos (10U)
25220#define HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)
25221#define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk
25222#define HRTIM_MCR_SYNCSTRTM_Pos (11U)
25223#define HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)
25224#define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk
25225#define HRTIM_MCR_SYNC_OUT_Pos (12U)
25226#define HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)
25227#define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk
25228#define HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)
25229#define HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)
25230#define HRTIM_MCR_SYNC_SRC_Pos (14U)
25231#define HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)
25232#define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk
25233#define HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)
25234#define HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)
25236#define HRTIM_MCR_MCEN_Pos (16U)
25237#define HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos)
25238#define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk
25239#define HRTIM_MCR_TACEN_Pos (17U)
25240#define HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos)
25241#define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk
25242#define HRTIM_MCR_TBCEN_Pos (18U)
25243#define HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos)
25244#define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk
25245#define HRTIM_MCR_TCCEN_Pos (19U)
25246#define HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos)
25247#define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk
25248#define HRTIM_MCR_TDCEN_Pos (20U)
25249#define HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos)
25250#define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk
25251#define HRTIM_MCR_TECEN_Pos (21U)
25252#define HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos)
25253#define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk
25255#define HRTIM_MCR_DACSYNC_Pos (25U)
25256#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos)
25257#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk
25258#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos)
25259#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos)
25261#define HRTIM_MCR_PREEN_Pos (27U)
25262#define HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos)
25263#define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk
25264#define HRTIM_MCR_MREPU_Pos (29U)
25265#define HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos)
25266#define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk
25268#define HRTIM_MCR_BRSTDMA_Pos (30U)
25269#define HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos)
25270#define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk
25271#define HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos)
25272#define HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos)
25274/******************** Master Timer Interrupt status register ******************/
25275#define HRTIM_MISR_MCMP1_Pos (0U)
25276#define HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos)
25277#define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk
25278#define HRTIM_MISR_MCMP2_Pos (1U)
25279#define HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos)
25280#define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk
25281#define HRTIM_MISR_MCMP3_Pos (2U)
25282#define HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos)
25283#define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk
25284#define HRTIM_MISR_MCMP4_Pos (3U)
25285#define HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos)
25286#define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk
25287#define HRTIM_MISR_MREP_Pos (4U)
25288#define HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos)
25289#define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk
25290#define HRTIM_MISR_SYNC_Pos (5U)
25291#define HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos)
25292#define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk
25293#define HRTIM_MISR_MUPD_Pos (6U)
25294#define HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos)
25295#define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk
25297/******************** Master Timer Interrupt clear register *******************/
25298#define HRTIM_MICR_MCMP1_Pos (0U)
25299#define HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos)
25300#define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk
25301#define HRTIM_MICR_MCMP2_Pos (1U)
25302#define HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos)
25303#define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk
25304#define HRTIM_MICR_MCMP3_Pos (2U)
25305#define HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos)
25306#define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk
25307#define HRTIM_MICR_MCMP4_Pos (3U)
25308#define HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos)
25309#define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk
25310#define HRTIM_MICR_MREP_Pos (4U)
25311#define HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos)
25312#define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk
25313#define HRTIM_MICR_SYNC_Pos (5U)
25314#define HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos)
25315#define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk
25316#define HRTIM_MICR_MUPD_Pos (6U)
25317#define HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos)
25318#define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk
25320/******************** Master Timer DMA/Interrupt enable register **************/
25321#define HRTIM_MDIER_MCMP1IE_Pos (0U)
25322#define HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)
25323#define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk
25324#define HRTIM_MDIER_MCMP2IE_Pos (1U)
25325#define HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)
25326#define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk
25327#define HRTIM_MDIER_MCMP3IE_Pos (2U)
25328#define HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)
25329#define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk
25330#define HRTIM_MDIER_MCMP4IE_Pos (3U)
25331#define HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)
25332#define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk
25333#define HRTIM_MDIER_MREPIE_Pos (4U)
25334#define HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos)
25335#define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk
25336#define HRTIM_MDIER_SYNCIE_Pos (5U)
25337#define HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos)
25338#define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk
25339#define HRTIM_MDIER_MUPDIE_Pos (6U)
25340#define HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos)
25341#define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk
25343#define HRTIM_MDIER_MCMP1DE_Pos (16U)
25344#define HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)
25345#define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk
25346#define HRTIM_MDIER_MCMP2DE_Pos (17U)
25347#define HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)
25348#define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk
25349#define HRTIM_MDIER_MCMP3DE_Pos (18U)
25350#define HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)
25351#define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk
25352#define HRTIM_MDIER_MCMP4DE_Pos (19U)
25353#define HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)
25354#define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk
25355#define HRTIM_MDIER_MREPDE_Pos (20U)
25356#define HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos)
25357#define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk
25358#define HRTIM_MDIER_SYNCDE_Pos (21U)
25359#define HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos)
25360#define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk
25361#define HRTIM_MDIER_MUPDDE_Pos (22U)
25362#define HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos)
25363#define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk
25365/******************* Bit definition for HRTIM_MCNTR register ****************/
25366#define HRTIM_MCNTR_MCNTR_Pos (0U)
25367#define HRTIM_MCNTR_MCNTR_Msk (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)
25368#define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk
25370/******************* Bit definition for HRTIM_MPER register *****************/
25371#define HRTIM_MPER_MPER_Pos (0U)
25372#define HRTIM_MPER_MPER_Msk (0xFFFFUL << HRTIM_MPER_MPER_Pos)
25373#define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk
25375/******************* Bit definition for HRTIM_MREP register *****************/
25376#define HRTIM_MREP_MREP_Pos (0U)
25377#define HRTIM_MREP_MREP_Msk (0xFFUL << HRTIM_MREP_MREP_Pos)
25378#define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk
25380/******************* Bit definition for HRTIM_MCMP1R register *****************/
25381#define HRTIM_MCMP1R_MCMP1R_Pos (0U)
25382#define HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)
25383#define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk
25385/******************* Bit definition for HRTIM_MCMP2R register *****************/
25386#define HRTIM_MCMP1R_MCMP2R_Pos (0U)
25387#define HRTIM_MCMP1R_MCMP2R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)
25388#define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP1R_MCMP2R_Msk
25390/******************* Bit definition for HRTIM_MCMP3R register *****************/
25391#define HRTIM_MCMP1R_MCMP3R_Pos (0U)
25392#define HRTIM_MCMP1R_MCMP3R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)
25393#define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP1R_MCMP3R_Msk
25395/******************* Bit definition for HRTIM_MCMP4R register *****************/
25396#define HRTIM_MCMP1R_MCMP4R_Pos (0U)
25397#define HRTIM_MCMP1R_MCMP4R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)
25398#define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP1R_MCMP4R_Msk
25400/******************** Slave control register **********************************/
25401#define HRTIM_TIMCR_CK_PSC_Pos (0U)
25402#define HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)
25403#define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk
25404#define HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)
25405#define HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)
25406#define HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)
25408#define HRTIM_TIMCR_CONT_Pos (3U)
25409#define HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos)
25410#define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk
25411#define HRTIM_TIMCR_RETRIG_Pos (4U)
25412#define HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos)
25413#define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk
25414#define HRTIM_TIMCR_HALF_Pos (5U)
25415#define HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos)
25416#define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk
25417#define HRTIM_TIMCR_PSHPLL_Pos (6U)
25418#define HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)
25419#define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk
25421#define HRTIM_TIMCR_SYNCRST_Pos (10U)
25422#define HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)
25423#define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk
25424#define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
25425#define HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)
25426#define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk
25428#define HRTIM_TIMCR_DELCMP2_Pos (12U)
25429#define HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)
25430#define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk
25431#define HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)
25432#define HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)
25433#define HRTIM_TIMCR_DELCMP4_Pos (14U)
25434#define HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)
25435#define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk
25436#define HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)
25437#define HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)
25439#define HRTIM_TIMCR_TREPU_Pos (17U)
25440#define HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos)
25441#define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk
25442#define HRTIM_TIMCR_TRSTU_Pos (18U)
25443#define HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos)
25444#define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk
25445#define HRTIM_TIMCR_TAU_Pos (19U)
25446#define HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos)
25447#define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk
25448#define HRTIM_TIMCR_TBU_Pos (20U)
25449#define HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos)
25450#define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk
25451#define HRTIM_TIMCR_TCU_Pos (21U)
25452#define HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos)
25453#define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk
25454#define HRTIM_TIMCR_TDU_Pos (22U)
25455#define HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos)
25456#define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk
25457#define HRTIM_TIMCR_TEU_Pos (23U)
25458#define HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos)
25459#define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk
25460#define HRTIM_TIMCR_MSTU_Pos (24U)
25461#define HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos)
25462#define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk
25464#define HRTIM_TIMCR_DACSYNC_Pos (25U)
25465#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)
25466#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk
25467#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)
25468#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)
25469#define HRTIM_TIMCR_PREEN_Pos (27U)
25470#define HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos)
25471#define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk
25473#define HRTIM_TIMCR_UPDGAT_Pos (28U)
25474#define HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)
25475#define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk
25476#define HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)
25477#define HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)
25478#define HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)
25479#define HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)
25481/******************** Slave Interrupt status register **************************/
25482#define HRTIM_TIMISR_CMP1_Pos (0U)
25483#define HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos)
25484#define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk
25485#define HRTIM_TIMISR_CMP2_Pos (1U)
25486#define HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos)
25487#define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk
25488#define HRTIM_TIMISR_CMP3_Pos (2U)
25489#define HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos)
25490#define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk
25491#define HRTIM_TIMISR_CMP4_Pos (3U)
25492#define HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos)
25493#define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk
25494#define HRTIM_TIMISR_REP_Pos (4U)
25495#define HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos)
25496#define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk
25497#define HRTIM_TIMISR_UPD_Pos (6U)
25498#define HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos)
25499#define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk
25500#define HRTIM_TIMISR_CPT1_Pos (7U)
25501#define HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos)
25502#define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk
25503#define HRTIM_TIMISR_CPT2_Pos (8U)
25504#define HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos)
25505#define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk
25506#define HRTIM_TIMISR_SET1_Pos (9U)
25507#define HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos)
25508#define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk
25509#define HRTIM_TIMISR_RST1_Pos (10U)
25510#define HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos)
25511#define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk
25512#define HRTIM_TIMISR_SET2_Pos (11U)
25513#define HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos)
25514#define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk
25515#define HRTIM_TIMISR_RST2_Pos (12U)
25516#define HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos)
25517#define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk
25518#define HRTIM_TIMISR_RST_Pos (13U)
25519#define HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos)
25520#define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk
25521#define HRTIM_TIMISR_DLYPRT_Pos (14U)
25522#define HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)
25523#define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk
25524#define HRTIM_TIMISR_CPPSTAT_Pos (16U)
25525#define HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)
25526#define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk
25527#define HRTIM_TIMISR_IPPSTAT_Pos (17U)
25528#define HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)
25529#define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk
25530#define HRTIM_TIMISR_O1STAT_Pos (18U)
25531#define HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos)
25532#define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk
25533#define HRTIM_TIMISR_O2STAT_Pos (19U)
25534#define HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos)
25535#define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk
25536#define HRTIM_TIMISR_O1CPY_Pos (20U)
25537#define HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos)
25538#define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk
25539#define HRTIM_TIMISR_O2CPY_Pos (21U)
25540#define HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos)
25541#define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk
25543/******************** Slave Interrupt clear register **************************/
25544#define HRTIM_TIMICR_CMP1C_Pos (0U)
25545#define HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos)
25546#define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk
25547#define HRTIM_TIMICR_CMP2C_Pos (1U)
25548#define HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos)
25549#define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk
25550#define HRTIM_TIMICR_CMP3C_Pos (2U)
25551#define HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos)
25552#define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk
25553#define HRTIM_TIMICR_CMP4C_Pos (3U)
25554#define HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos)
25555#define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk
25556#define HRTIM_TIMICR_REPC_Pos (4U)
25557#define HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos)
25558#define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk
25559#define HRTIM_TIMICR_UPDC_Pos (6U)
25560#define HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos)
25561#define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk
25562#define HRTIM_TIMICR_CPT1C_Pos (7U)
25563#define HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos)
25564#define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk
25565#define HRTIM_TIMICR_CPT2C_Pos (8U)
25566#define HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos)
25567#define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk
25568#define HRTIM_TIMICR_SET1C_Pos (9U)
25569#define HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos)
25570#define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk
25571#define HRTIM_TIMICR_RST1C_Pos (10U)
25572#define HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos)
25573#define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk
25574#define HRTIM_TIMICR_SET2C_Pos (11U)
25575#define HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos)
25576#define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk
25577#define HRTIM_TIMICR_RST2C_Pos (12U)
25578#define HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos)
25579#define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk
25580#define HRTIM_TIMICR_RSTC_Pos (13U)
25581#define HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos)
25582#define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk
25583#define HRTIM_TIMICR_DLYPRTC_Pos (14U)
25584#define HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)
25585#define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk
25587/******************** Slave DMA/Interrupt enable register *********************/
25588#define HRTIM_TIMDIER_CMP1IE_Pos (0U)
25589#define HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)
25590#define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk
25591#define HRTIM_TIMDIER_CMP2IE_Pos (1U)
25592#define HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)
25593#define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk
25594#define HRTIM_TIMDIER_CMP3IE_Pos (2U)
25595#define HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)
25596#define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk
25597#define HRTIM_TIMDIER_CMP4IE_Pos (3U)
25598#define HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)
25599#define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk
25600#define HRTIM_TIMDIER_REPIE_Pos (4U)
25601#define HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos)
25602#define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk
25603#define HRTIM_TIMDIER_UPDIE_Pos (6U)
25604#define HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)
25605#define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk
25606#define HRTIM_TIMDIER_CPT1IE_Pos (7U)
25607#define HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)
25608#define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk
25609#define HRTIM_TIMDIER_CPT2IE_Pos (8U)
25610#define HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)
25611#define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk
25612#define HRTIM_TIMDIER_SET1IE_Pos (9U)
25613#define HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)
25614#define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk
25615#define HRTIM_TIMDIER_RST1IE_Pos (10U)
25616#define HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)
25617#define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk
25618#define HRTIM_TIMDIER_SET2IE_Pos (11U)
25619#define HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)
25620#define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk
25621#define HRTIM_TIMDIER_RST2IE_Pos (12U)
25622#define HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)
25623#define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk
25624#define HRTIM_TIMDIER_RSTIE_Pos (13U)
25625#define HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)
25626#define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk
25627#define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
25628#define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)
25629#define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk
25631#define HRTIM_TIMDIER_CMP1DE_Pos (16U)
25632#define HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)
25633#define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk
25634#define HRTIM_TIMDIER_CMP2DE_Pos (17U)
25635#define HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)
25636#define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk
25637#define HRTIM_TIMDIER_CMP3DE_Pos (18U)
25638#define HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)
25639#define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk
25640#define HRTIM_TIMDIER_CMP4DE_Pos (19U)
25641#define HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)
25642#define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk
25643#define HRTIM_TIMDIER_REPDE_Pos (20U)
25644#define HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos)
25645#define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk
25646#define HRTIM_TIMDIER_UPDDE_Pos (22U)
25647#define HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)
25648#define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk
25649#define HRTIM_TIMDIER_CPT1DE_Pos (23U)
25650#define HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)
25651#define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk
25652#define HRTIM_TIMDIER_CPT2DE_Pos (24U)
25653#define HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)
25654#define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk
25655#define HRTIM_TIMDIER_SET1DE_Pos (25U)
25656#define HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)
25657#define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk
25658#define HRTIM_TIMDIER_RST1DE_Pos (26U)
25659#define HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)
25660#define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk
25661#define HRTIM_TIMDIER_SET2DE_Pos (27U)
25662#define HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)
25663#define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk
25664#define HRTIM_TIMDIER_RST2DE_Pos (28U)
25665#define HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)
25666#define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk
25667#define HRTIM_TIMDIER_RSTDE_Pos (29U)
25668#define HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)
25669#define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk
25670#define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
25671#define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)
25672#define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk
25674/****************** Bit definition for HRTIM_CNTR register ****************/
25675#define HRTIM_CNTR_CNTR_Pos (0U)
25676#define HRTIM_CNTR_CNTR_Msk (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)
25677#define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk
25679/******************* Bit definition for HRTIM_PER register *****************/
25680#define HRTIM_PER_PER_Pos (0U)
25681#define HRTIM_PER_PER_Msk (0xFFFFUL << HRTIM_PER_PER_Pos)
25682#define HRTIM_PER_PER HRTIM_PER_PER_Msk
25684/******************* Bit definition for HRTIM_REP register *****************/
25685#define HRTIM_REP_REP_Pos (0U)
25686#define HRTIM_REP_REP_Msk (0xFFUL << HRTIM_REP_REP_Pos)
25687#define HRTIM_REP_REP HRTIM_REP_REP_Msk
25689/******************* Bit definition for HRTIM_CMP1R register *****************/
25690#define HRTIM_CMP1R_CMP1R_Pos (0U)
25691#define HRTIM_CMP1R_CMP1R_Msk (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)
25692#define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk
25694/******************* Bit definition for HRTIM_CMP1CR register *****************/
25695#define HRTIM_CMP1CR_CMP1CR_Pos (0U)
25696#define HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos)
25697#define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk
25699/******************* Bit definition for HRTIM_CMP2R register *****************/
25700#define HRTIM_CMP2R_CMP2R_Pos (0U)
25701#define HRTIM_CMP2R_CMP2R_Msk (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)
25702#define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk
25704/******************* Bit definition for HRTIM_CMP3R register *****************/
25705#define HRTIM_CMP3R_CMP3R_Pos (0U)
25706#define HRTIM_CMP3R_CMP3R_Msk (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)
25707#define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk
25709/******************* Bit definition for HRTIM_CMP4R register *****************/
25710#define HRTIM_CMP4R_CMP4R_Pos (0U)
25711#define HRTIM_CMP4R_CMP4R_Msk (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)
25712#define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk
25714/******************* Bit definition for HRTIM_CPT1R register ****************/
25715#define HRTIM_CPT1R_CPT1R_Pos (0U)
25716#define HRTIM_CPT1R_CPT1R_Msk (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)
25717#define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk
25719/******************* Bit definition for HRTIM_CPT2R register ****************/
25720#define HRTIM_CPT2R_CPT2R_Pos (0U)
25721#define HRTIM_CPT2R_CPT2R_Msk (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)
25722#define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk
25724/******************** Bit definition for Slave Deadtime register **************/
25725#define HRTIM_DTR_DTR_Pos (0U)
25726#define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos)
25727#define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk
25728#define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos)
25729#define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos)
25730#define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos)
25731#define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos)
25732#define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos)
25733#define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos)
25734#define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos)
25735#define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos)
25736#define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos)
25737#define HRTIM_DTR_SDTR_Pos (9U)
25738#define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos)
25739#define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk
25740#define HRTIM_DTR_DTPRSC_Pos (10U)
25741#define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos)
25742#define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk
25743#define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos)
25744#define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos)
25745#define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos)
25746#define HRTIM_DTR_DTRSLK_Pos (14U)
25747#define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos)
25748#define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk
25749#define HRTIM_DTR_DTRLK_Pos (15U)
25750#define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos)
25751#define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk
25752#define HRTIM_DTR_DTF_Pos (16U)
25753#define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos)
25754#define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk
25755#define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos)
25756#define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos)
25757#define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos)
25758#define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos)
25759#define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos)
25760#define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos)
25761#define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos)
25762#define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos)
25763#define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos)
25764#define HRTIM_DTR_SDTF_Pos (25U)
25765#define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos)
25766#define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk
25767#define HRTIM_DTR_DTFSLK_Pos (30U)
25768#define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos)
25769#define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk
25770#define HRTIM_DTR_DTFLK_Pos (31U)
25771#define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos)
25772#define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk
25774/**** Bit definition for Slave Output 1 set register **************************/
25775#define HRTIM_SET1R_SST_Pos (0U)
25776#define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos)
25777#define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk
25778#define HRTIM_SET1R_RESYNC_Pos (1U)
25779#define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos)
25780#define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk
25781#define HRTIM_SET1R_PER_Pos (2U)
25782#define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos)
25783#define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk
25784#define HRTIM_SET1R_CMP1_Pos (3U)
25785#define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos)
25786#define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk
25787#define HRTIM_SET1R_CMP2_Pos (4U)
25788#define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos)
25789#define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk
25790#define HRTIM_SET1R_CMP3_Pos (5U)
25791#define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos)
25792#define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk
25793#define HRTIM_SET1R_CMP4_Pos (6U)
25794#define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos)
25795#define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk
25797#define HRTIM_SET1R_MSTPER_Pos (7U)
25798#define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos)
25799#define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk
25800#define HRTIM_SET1R_MSTCMP1_Pos (8U)
25801#define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)
25802#define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk
25803#define HRTIM_SET1R_MSTCMP2_Pos (9U)
25804#define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)
25805#define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk
25806#define HRTIM_SET1R_MSTCMP3_Pos (10U)
25807#define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)
25808#define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk
25809#define HRTIM_SET1R_MSTCMP4_Pos (11U)
25810#define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)
25811#define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk
25813#define HRTIM_SET1R_TIMEVNT1_Pos (12U)
25814#define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)
25815#define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk
25816#define HRTIM_SET1R_TIMEVNT2_Pos (13U)
25817#define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)
25818#define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk
25819#define HRTIM_SET1R_TIMEVNT3_Pos (14U)
25820#define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)
25821#define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk
25822#define HRTIM_SET1R_TIMEVNT4_Pos (15U)
25823#define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)
25824#define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk
25825#define HRTIM_SET1R_TIMEVNT5_Pos (16U)
25826#define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)
25827#define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk
25828#define HRTIM_SET1R_TIMEVNT6_Pos (17U)
25829#define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)
25830#define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk
25831#define HRTIM_SET1R_TIMEVNT7_Pos (18U)
25832#define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)
25833#define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk
25834#define HRTIM_SET1R_TIMEVNT8_Pos (19U)
25835#define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)
25836#define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk
25837#define HRTIM_SET1R_TIMEVNT9_Pos (20U)
25838#define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)
25839#define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk
25841#define HRTIM_SET1R_EXTVNT1_Pos (21U)
25842#define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)
25843#define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk
25844#define HRTIM_SET1R_EXTVNT2_Pos (22U)
25845#define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)
25846#define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk
25847#define HRTIM_SET1R_EXTVNT3_Pos (23U)
25848#define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)
25849#define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk
25850#define HRTIM_SET1R_EXTVNT4_Pos (24U)
25851#define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)
25852#define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk
25853#define HRTIM_SET1R_EXTVNT5_Pos (25U)
25854#define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)
25855#define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk
25856#define HRTIM_SET1R_EXTVNT6_Pos (26U)
25857#define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)
25858#define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk
25859#define HRTIM_SET1R_EXTVNT7_Pos (27U)
25860#define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)
25861#define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk
25862#define HRTIM_SET1R_EXTVNT8_Pos (28U)
25863#define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)
25864#define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk
25865#define HRTIM_SET1R_EXTVNT9_Pos (29U)
25866#define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)
25867#define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk
25868#define HRTIM_SET1R_EXTVNT10_Pos (30U)
25869#define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)
25870#define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk
25872#define HRTIM_SET1R_UPDATE_Pos (31U)
25873#define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos)
25874#define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk
25876/**** Bit definition for Slave Output 1 reset register ************************/
25877#define HRTIM_RST1R_SRT_Pos (0U)
25878#define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos)
25879#define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk
25880#define HRTIM_RST1R_RESYNC_Pos (1U)
25881#define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos)
25882#define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk
25883#define HRTIM_RST1R_PER_Pos (2U)
25884#define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos)
25885#define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk
25886#define HRTIM_RST1R_CMP1_Pos (3U)
25887#define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos)
25888#define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk
25889#define HRTIM_RST1R_CMP2_Pos (4U)
25890#define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos)
25891#define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk
25892#define HRTIM_RST1R_CMP3_Pos (5U)
25893#define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos)
25894#define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk
25895#define HRTIM_RST1R_CMP4_Pos (6U)
25896#define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos)
25897#define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk
25899#define HRTIM_RST1R_MSTPER_Pos (7U)
25900#define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos)
25901#define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk
25902#define HRTIM_RST1R_MSTCMP1_Pos (8U)
25903#define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)
25904#define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk
25905#define HRTIM_RST1R_MSTCMP2_Pos (9U)
25906#define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)
25907#define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk
25908#define HRTIM_RST1R_MSTCMP3_Pos (10U)
25909#define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)
25910#define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk
25911#define HRTIM_RST1R_MSTCMP4_Pos (11U)
25912#define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)
25913#define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk
25915#define HRTIM_RST1R_TIMEVNT1_Pos (12U)
25916#define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)
25917#define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk
25918#define HRTIM_RST1R_TIMEVNT2_Pos (13U)
25919#define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)
25920#define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk
25921#define HRTIM_RST1R_TIMEVNT3_Pos (14U)
25922#define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)
25923#define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk
25924#define HRTIM_RST1R_TIMEVNT4_Pos (15U)
25925#define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)
25926#define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk
25927#define HRTIM_RST1R_TIMEVNT5_Pos (16U)
25928#define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)
25929#define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk
25930#define HRTIM_RST1R_TIMEVNT6_Pos (17U)
25931#define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)
25932#define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk
25933#define HRTIM_RST1R_TIMEVNT7_Pos (18U)
25934#define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)
25935#define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk
25936#define HRTIM_RST1R_TIMEVNT8_Pos (19U)
25937#define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)
25938#define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk
25939#define HRTIM_RST1R_TIMEVNT9_Pos (20U)
25940#define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)
25941#define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk
25943#define HRTIM_RST1R_EXTVNT1_Pos (21U)
25944#define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)
25945#define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk
25946#define HRTIM_RST1R_EXTVNT2_Pos (22U)
25947#define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)
25948#define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk
25949#define HRTIM_RST1R_EXTVNT3_Pos (23U)
25950#define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)
25951#define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk
25952#define HRTIM_RST1R_EXTVNT4_Pos (24U)
25953#define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)
25954#define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk
25955#define HRTIM_RST1R_EXTVNT5_Pos (25U)
25956#define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)
25957#define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk
25958#define HRTIM_RST1R_EXTVNT6_Pos (26U)
25959#define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)
25960#define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk
25961#define HRTIM_RST1R_EXTVNT7_Pos (27U)
25962#define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)
25963#define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk
25964#define HRTIM_RST1R_EXTVNT8_Pos (28U)
25965#define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)
25966#define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk
25967#define HRTIM_RST1R_EXTVNT9_Pos (29U)
25968#define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)
25969#define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk
25970#define HRTIM_RST1R_EXTVNT10_Pos (30U)
25971#define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)
25972#define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk
25974#define HRTIM_RST1R_UPDATE_Pos (31U)
25975#define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos)
25976#define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk
25979/**** Bit definition for Slave Output 2 set register **************************/
25980#define HRTIM_SET2R_SST_Pos (0U)
25981#define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos)
25982#define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk
25983#define HRTIM_SET2R_RESYNC_Pos (1U)
25984#define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos)
25985#define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk
25986#define HRTIM_SET2R_PER_Pos (2U)
25987#define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos)
25988#define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk
25989#define HRTIM_SET2R_CMP1_Pos (3U)
25990#define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos)
25991#define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk
25992#define HRTIM_SET2R_CMP2_Pos (4U)
25993#define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos)
25994#define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk
25995#define HRTIM_SET2R_CMP3_Pos (5U)
25996#define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos)
25997#define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk
25998#define HRTIM_SET2R_CMP4_Pos (6U)
25999#define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos)
26000#define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk
26002#define HRTIM_SET2R_MSTPER_Pos (7U)
26003#define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos)
26004#define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk
26005#define HRTIM_SET2R_MSTCMP1_Pos (8U)
26006#define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)
26007#define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk
26008#define HRTIM_SET2R_MSTCMP2_Pos (9U)
26009#define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)
26010#define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk
26011#define HRTIM_SET2R_MSTCMP3_Pos (10U)
26012#define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)
26013#define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk
26014#define HRTIM_SET2R_MSTCMP4_Pos (11U)
26015#define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)
26016#define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk
26018#define HRTIM_SET2R_TIMEVNT1_Pos (12U)
26019#define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)
26020#define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk
26021#define HRTIM_SET2R_TIMEVNT2_Pos (13U)
26022#define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)
26023#define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk
26024#define HRTIM_SET2R_TIMEVNT3_Pos (14U)
26025#define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)
26026#define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk
26027#define HRTIM_SET2R_TIMEVNT4_Pos (15U)
26028#define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)
26029#define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk
26030#define HRTIM_SET2R_TIMEVNT5_Pos (16U)
26031#define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)
26032#define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk
26033#define HRTIM_SET2R_TIMEVNT6_Pos (17U)
26034#define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)
26035#define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk
26036#define HRTIM_SET2R_TIMEVNT7_Pos (18U)
26037#define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)
26038#define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk
26039#define HRTIM_SET2R_TIMEVNT8_Pos (19U)
26040#define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)
26041#define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk
26042#define HRTIM_SET2R_TIMEVNT9_Pos (20U)
26043#define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)
26044#define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk
26046#define HRTIM_SET2R_EXTVNT1_Pos (21U)
26047#define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)
26048#define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk
26049#define HRTIM_SET2R_EXTVNT2_Pos (22U)
26050#define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)
26051#define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk
26052#define HRTIM_SET2R_EXTVNT3_Pos (23U)
26053#define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)
26054#define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk
26055#define HRTIM_SET2R_EXTVNT4_Pos (24U)
26056#define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)
26057#define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk
26058#define HRTIM_SET2R_EXTVNT5_Pos (25U)
26059#define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)
26060#define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk
26061#define HRTIM_SET2R_EXTVNT6_Pos (26U)
26062#define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)
26063#define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk
26064#define HRTIM_SET2R_EXTVNT7_Pos (27U)
26065#define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)
26066#define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk
26067#define HRTIM_SET2R_EXTVNT8_Pos (28U)
26068#define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)
26069#define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk
26070#define HRTIM_SET2R_EXTVNT9_Pos (29U)
26071#define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)
26072#define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk
26073#define HRTIM_SET2R_EXTVNT10_Pos (30U)
26074#define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)
26075#define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk
26077#define HRTIM_SET2R_UPDATE_Pos (31U)
26078#define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos)
26079#define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk
26081/**** Bit definition for Slave Output 2 reset register ************************/
26082#define HRTIM_RST2R_SRT_Pos (0U)
26083#define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos)
26084#define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk
26085#define HRTIM_RST2R_RESYNC_Pos (1U)
26086#define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos)
26087#define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk
26088#define HRTIM_RST2R_PER_Pos (2U)
26089#define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos)
26090#define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk
26091#define HRTIM_RST2R_CMP1_Pos (3U)
26092#define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos)
26093#define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk
26094#define HRTIM_RST2R_CMP2_Pos (4U)
26095#define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos)
26096#define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk
26097#define HRTIM_RST2R_CMP3_Pos (5U)
26098#define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos)
26099#define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk
26100#define HRTIM_RST2R_CMP4_Pos (6U)
26101#define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos)
26102#define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk
26104#define HRTIM_RST2R_MSTPER_Pos (7U)
26105#define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos)
26106#define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk
26107#define HRTIM_RST2R_MSTCMP1_Pos (8U)
26108#define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)
26109#define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk
26110#define HRTIM_RST2R_MSTCMP2_Pos (9U)
26111#define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)
26112#define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk
26113#define HRTIM_RST2R_MSTCMP3_Pos (10U)
26114#define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)
26115#define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk
26116#define HRTIM_RST2R_MSTCMP4_Pos (11U)
26117#define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)
26118#define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk
26120#define HRTIM_RST2R_TIMEVNT1_Pos (12U)
26121#define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)
26122#define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk
26123#define HRTIM_RST2R_TIMEVNT2_Pos (13U)
26124#define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)
26125#define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk
26126#define HRTIM_RST2R_TIMEVNT3_Pos (14U)
26127#define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)
26128#define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk
26129#define HRTIM_RST2R_TIMEVNT4_Pos (15U)
26130#define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)
26131#define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk
26132#define HRTIM_RST2R_TIMEVNT5_Pos (16U)
26133#define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)
26134#define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk
26135#define HRTIM_RST2R_TIMEVNT6_Pos (17U)
26136#define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)
26137#define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk
26138#define HRTIM_RST2R_TIMEVNT7_Pos (18U)
26139#define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)
26140#define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk
26141#define HRTIM_RST2R_TIMEVNT8_Pos (19U)
26142#define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)
26143#define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk
26144#define HRTIM_RST2R_TIMEVNT9_Pos (20U)
26145#define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)
26146#define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk
26148#define HRTIM_RST2R_EXTVNT1_Pos (21U)
26149#define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)
26150#define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk
26151#define HRTIM_RST2R_EXTVNT2_Pos (22U)
26152#define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)
26153#define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk
26154#define HRTIM_RST2R_EXTVNT3_Pos (23U)
26155#define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)
26156#define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk
26157#define HRTIM_RST2R_EXTVNT4_Pos (24U)
26158#define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)
26159#define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk
26160#define HRTIM_RST2R_EXTVNT5_Pos (25U)
26161#define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)
26162#define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk
26163#define HRTIM_RST2R_EXTVNT6_Pos (26U)
26164#define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)
26165#define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk
26166#define HRTIM_RST2R_EXTVNT7_Pos (27U)
26167#define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)
26168#define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk
26169#define HRTIM_RST2R_EXTVNT8_Pos (28U)
26170#define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)
26171#define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk
26172#define HRTIM_RST2R_EXTVNT9_Pos (29U)
26173#define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)
26174#define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk
26175#define HRTIM_RST2R_EXTVNT10_Pos (30U)
26176#define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)
26177#define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk
26179#define HRTIM_RST2R_UPDATE_Pos (31U)
26180#define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos)
26181#define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk
26183/**** Bit definition for Slave external event filtering register 1 ***********/
26184#define HRTIM_EEFR1_EE1LTCH_Pos (0U)
26185#define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)
26186#define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk
26187#define HRTIM_EEFR1_EE1FLTR_Pos (1U)
26188#define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)
26189#define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk
26190#define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)
26191#define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)
26192#define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)
26193#define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)
26195#define HRTIM_EEFR1_EE2LTCH_Pos (6U)
26196#define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)
26197#define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk
26198#define HRTIM_EEFR1_EE2FLTR_Pos (7U)
26199#define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)
26200#define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk
26201#define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)
26202#define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)
26203#define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)
26204#define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)
26206#define HRTIM_EEFR1_EE3LTCH_Pos (12U)
26207#define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)
26208#define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk
26209#define HRTIM_EEFR1_EE3FLTR_Pos (13U)
26210#define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)
26211#define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk
26212#define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)
26213#define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)
26214#define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)
26215#define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)
26217#define HRTIM_EEFR1_EE4LTCH_Pos (18U)
26218#define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)
26219#define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk
26220#define HRTIM_EEFR1_EE4FLTR_Pos (19U)
26221#define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)
26222#define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk
26223#define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)
26224#define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)
26225#define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)
26226#define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)
26228#define HRTIM_EEFR1_EE5LTCH_Pos (24U)
26229#define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)
26230#define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk
26231#define HRTIM_EEFR1_EE5FLTR_Pos (25U)
26232#define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)
26233#define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk
26234#define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)
26235#define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)
26236#define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)
26237#define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)
26239/**** Bit definition for Slave external event filtering register 2 ***********/
26240#define HRTIM_EEFR2_EE6LTCH_Pos (0U)
26241#define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)
26242#define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk
26243#define HRTIM_EEFR2_EE6FLTR_Pos (1U)
26244#define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)
26245#define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk
26246#define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)
26247#define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)
26248#define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)
26249#define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)
26251#define HRTIM_EEFR2_EE7LTCH_Pos (6U)
26252#define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)
26253#define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk
26254#define HRTIM_EEFR2_EE7FLTR_Pos (7U)
26255#define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)
26256#define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk
26257#define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)
26258#define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)
26259#define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)
26260#define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)
26262#define HRTIM_EEFR2_EE8LTCH_Pos (12U)
26263#define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)
26264#define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk
26265#define HRTIM_EEFR2_EE8FLTR_Pos (13U)
26266#define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)
26267#define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk
26268#define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)
26269#define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)
26270#define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)
26271#define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)
26273#define HRTIM_EEFR2_EE9LTCH_Pos (18U)
26274#define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)
26275#define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk
26276#define HRTIM_EEFR2_EE9FLTR_Pos (19U)
26277#define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)
26278#define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk
26279#define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)
26280#define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)
26281#define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)
26282#define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)
26284#define HRTIM_EEFR2_EE10LTCH_Pos (24U)
26285#define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)
26286#define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk
26287#define HRTIM_EEFR2_EE10FLTR_Pos (25U)
26288#define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)
26289#define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk
26290#define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)
26291#define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)
26292#define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)
26293#define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)
26295/**** Bit definition for Slave Timer reset register ***************************/
26296#define HRTIM_RSTR_UPDATE_Pos (1U)
26297#define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos)
26298#define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk
26299#define HRTIM_RSTR_CMP2_Pos (2U)
26300#define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos)
26301#define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk
26302#define HRTIM_RSTR_CMP4_Pos (3U)
26303#define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos)
26304#define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk
26306#define HRTIM_RSTR_MSTPER_Pos (4U)
26307#define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos)
26308#define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk
26309#define HRTIM_RSTR_MSTCMP1_Pos (5U)
26310#define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)
26311#define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk
26312#define HRTIM_RSTR_MSTCMP2_Pos (6U)
26313#define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)
26314#define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk
26315#define HRTIM_RSTR_MSTCMP3_Pos (7U)
26316#define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)
26317#define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk
26318#define HRTIM_RSTR_MSTCMP4_Pos (8U)
26319#define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)
26320#define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk
26322#define HRTIM_RSTR_EXTEVNT1_Pos (9U)
26323#define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)
26324#define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk
26325#define HRTIM_RSTR_EXTEVNT2_Pos (10U)
26326#define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)
26327#define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk
26328#define HRTIM_RSTR_EXTEVNT3_Pos (11U)
26329#define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)
26330#define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk
26331#define HRTIM_RSTR_EXTEVNT4_Pos (12U)
26332#define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)
26333#define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk
26334#define HRTIM_RSTR_EXTEVNT5_Pos (13U)
26335#define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)
26336#define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk
26337#define HRTIM_RSTR_EXTEVNT6_Pos (14U)
26338#define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)
26339#define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk
26340#define HRTIM_RSTR_EXTEVNT7_Pos (15U)
26341#define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)
26342#define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk
26343#define HRTIM_RSTR_EXTEVNT8_Pos (16U)
26344#define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)
26345#define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk
26346#define HRTIM_RSTR_EXTEVNT9_Pos (17U)
26347#define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)
26348#define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk
26349#define HRTIM_RSTR_EXTEVNT10_Pos (18U)
26350#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)
26351#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk
26353/* Slave Timer A reset enable bits upon other slave timers events */
26354#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
26355#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)
26356#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk
26357#define HRTIM_RSTR_TIMBCMP2_Pos (20U)
26358#define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)
26359#define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk
26360#define HRTIM_RSTR_TIMBCMP4_Pos (21U)
26361#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)
26362#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk
26364#define HRTIM_RSTR_TIMCCMP1_Pos (22U)
26365#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)
26366#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk
26367#define HRTIM_RSTR_TIMCCMP2_Pos (23U)
26368#define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)
26369#define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk
26370#define HRTIM_RSTR_TIMCCMP4_Pos (24U)
26371#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)
26372#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk
26374#define HRTIM_RSTR_TIMDCMP1_Pos (25U)
26375#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)
26376#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk
26377#define HRTIM_RSTR_TIMDCMP2_Pos (26U)
26378#define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)
26379#define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk
26380#define HRTIM_RSTR_TIMDCMP4_Pos (27U)
26381#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)
26382#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk
26384#define HRTIM_RSTR_TIMECMP1_Pos (28U)
26385#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)
26386#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk
26387#define HRTIM_RSTR_TIMECMP2_Pos (29U)
26388#define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)
26389#define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk
26390#define HRTIM_RSTR_TIMECMP4_Pos (30U)
26391#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)
26392#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk
26394/* Slave Timer B reset enable bits upon other slave timers events */
26395#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
26396#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)
26397#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk
26398#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
26399#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)
26400#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk
26401#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
26402#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)
26403#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk
26405#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
26406#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)
26407#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk
26408#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
26409#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)
26410#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk
26411#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
26412#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)
26413#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk
26415#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
26416#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)
26417#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk
26418#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
26419#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)
26420#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk
26421#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
26422#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)
26423#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk
26425#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
26426#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)
26427#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk
26428#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
26429#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)
26430#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk
26431#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
26432#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)
26433#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk
26435/* Slave Timer C reset enable bits upon other slave timers events */
26436#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
26437#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)
26438#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk
26439#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
26440#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)
26441#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk
26442#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
26443#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)
26444#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk
26446#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
26447#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)
26448#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk
26449#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
26450#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)
26451#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk
26452#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
26453#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)
26454#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk
26456#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
26457#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)
26458#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk
26459#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
26460#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)
26461#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk
26462#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
26463#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)
26464#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk
26466#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
26467#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)
26468#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk
26469#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
26470#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)
26471#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk
26472#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
26473#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)
26474#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk
26476/* Slave Timer D reset enable bits upon other slave timers events */
26477#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
26478#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)
26479#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk
26480#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
26481#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)
26482#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk
26483#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
26484#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)
26485#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk
26487#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
26488#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)
26489#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk
26490#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
26491#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)
26492#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk
26493#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
26494#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)
26495#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk
26497#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
26498#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)
26499#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk
26500#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
26501#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)
26502#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk
26503#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
26504#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)
26505#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk
26507#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
26508#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)
26509#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk
26510#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
26511#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)
26512#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk
26513#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
26514#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)
26515#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk
26517/* Slave Timer E reset enable bits upon other slave timers events */
26518#define HRTIM_RSTER_TIMACMP1_Pos (19U)
26519#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)
26520#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk
26521#define HRTIM_RSTER_TIMACMP2_Pos (20U)
26522#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)
26523#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk
26524#define HRTIM_RSTER_TIMACMP4_Pos (21U)
26525#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)
26526#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk
26528#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
26529#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)
26530#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk
26531#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
26532#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)
26533#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk
26534#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
26535#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)
26536#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk
26538#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
26539#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)
26540#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk
26541#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
26542#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)
26543#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk
26544#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
26545#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)
26546#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk
26548#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
26549#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)
26550#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk
26551#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
26552#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)
26553#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk
26554#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
26555#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)
26556#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk
26558/**** Bit definition for Slave Timer Chopper register *************************/
26559#define HRTIM_CHPR_CARFRQ_Pos (0U)
26560#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos)
26561#define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk
26562#define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos)
26563#define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos)
26564#define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos)
26565#define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos)
26567#define HRTIM_CHPR_CARDTY_Pos (4U)
26568#define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos)
26569#define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk
26570#define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos)
26571#define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos)
26572#define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos)
26574#define HRTIM_CHPR_STRPW_Pos (7U)
26575#define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos)
26576#define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk
26577#define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos)
26578#define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos)
26579#define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos)
26580#define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos)
26582/**** Bit definition for Slave Timer Capture 1 control register ***************/
26583#define HRTIM_CPT1CR_SWCPT_Pos (0U)
26584#define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)
26585#define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk
26586#define HRTIM_CPT1CR_UPDCPT_Pos (1U)
26587#define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)
26588#define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk
26589#define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
26590#define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)
26591#define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk
26592#define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
26593#define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)
26594#define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk
26595#define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
26596#define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)
26597#define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk
26598#define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
26599#define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)
26600#define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk
26601#define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
26602#define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)
26603#define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk
26604#define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
26605#define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)
26606#define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk
26607#define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
26608#define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)
26609#define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk
26610#define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
26611#define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)
26612#define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk
26613#define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
26614#define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)
26615#define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk
26616#define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
26617#define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)
26618#define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk
26620#define HRTIM_CPT1CR_TA1SET_Pos (12U)
26621#define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)
26622#define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk
26623#define HRTIM_CPT1CR_TA1RST_Pos (13U)
26624#define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)
26625#define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk
26626#define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
26627#define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)
26628#define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk
26629#define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
26630#define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)
26631#define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk
26633#define HRTIM_CPT1CR_TB1SET_Pos (16U)
26634#define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)
26635#define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk
26636#define HRTIM_CPT1CR_TB1RST_Pos (17U)
26637#define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)
26638#define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk
26639#define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
26640#define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)
26641#define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk
26642#define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
26643#define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)
26644#define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk
26646#define HRTIM_CPT1CR_TC1SET_Pos (20U)
26647#define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)
26648#define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk
26649#define HRTIM_CPT1CR_TC1RST_Pos (21U)
26650#define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)
26651#define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk
26652#define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
26653#define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)
26654#define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk
26655#define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
26656#define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)
26657#define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk
26659#define HRTIM_CPT1CR_TD1SET_Pos (24U)
26660#define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)
26661#define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk
26662#define HRTIM_CPT1CR_TD1RST_Pos (25U)
26663#define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)
26664#define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk
26665#define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
26666#define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)
26667#define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk
26668#define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
26669#define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)
26670#define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk
26672#define HRTIM_CPT1CR_TE1SET_Pos (28U)
26673#define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)
26674#define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk
26675#define HRTIM_CPT1CR_TE1RST_Pos (29U)
26676#define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)
26677#define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk
26678#define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
26679#define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)
26680#define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk
26681#define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
26682#define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)
26683#define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk
26685/**** Bit definition for Slave Timer Capture 2 control register ***************/
26686#define HRTIM_CPT2CR_SWCPT_Pos (0U)
26687#define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)
26688#define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk
26689#define HRTIM_CPT2CR_UPDCPT_Pos (1U)
26690#define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)
26691#define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk
26692#define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
26693#define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)
26694#define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk
26695#define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
26696#define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)
26697#define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk
26698#define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
26699#define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)
26700#define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk
26701#define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
26702#define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)
26703#define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk
26704#define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
26705#define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)
26706#define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk
26707#define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
26708#define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)
26709#define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk
26710#define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
26711#define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)
26712#define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk
26713#define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
26714#define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)
26715#define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk
26716#define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
26717#define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)
26718#define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk
26719#define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
26720#define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)
26721#define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk
26723#define HRTIM_CPT2CR_TA1SET_Pos (12U)
26724#define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)
26725#define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk
26726#define HRTIM_CPT2CR_TA1RST_Pos (13U)
26727#define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)
26728#define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk
26729#define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
26730#define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)
26731#define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk
26732#define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
26733#define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)
26734#define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk
26736#define HRTIM_CPT2CR_TB1SET_Pos (16U)
26737#define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)
26738#define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk
26739#define HRTIM_CPT2CR_TB1RST_Pos (17U)
26740#define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)
26741#define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk
26742#define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
26743#define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)
26744#define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk
26745#define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
26746#define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)
26747#define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk
26749#define HRTIM_CPT2CR_TC1SET_Pos (20U)
26750#define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)
26751#define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk
26752#define HRTIM_CPT2CR_TC1RST_Pos (21U)
26753#define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)
26754#define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk
26755#define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
26756#define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)
26757#define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk
26758#define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
26759#define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)
26760#define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk
26762#define HRTIM_CPT2CR_TD1SET_Pos (24U)
26763#define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)
26764#define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk
26765#define HRTIM_CPT2CR_TD1RST_Pos (25U)
26766#define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)
26767#define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk
26768#define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
26769#define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)
26770#define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk
26771#define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
26772#define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)
26773#define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk
26775#define HRTIM_CPT2CR_TE1SET_Pos (28U)
26776#define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)
26777#define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk
26778#define HRTIM_CPT2CR_TE1RST_Pos (29U)
26779#define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)
26780#define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk
26781#define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
26782#define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)
26783#define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk
26784#define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
26785#define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)
26786#define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk
26788/**** Bit definition for Slave Timer Output register **************************/
26789#define HRTIM_OUTR_POL1_Pos (1U)
26790#define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos)
26791#define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk
26792#define HRTIM_OUTR_IDLM1_Pos (2U)
26793#define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos)
26794#define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk
26795#define HRTIM_OUTR_IDLES1_Pos (3U)
26796#define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos)
26797#define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk
26798#define HRTIM_OUTR_FAULT1_Pos (4U)
26799#define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos)
26800#define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk
26801#define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos)
26802#define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos)
26803#define HRTIM_OUTR_CHP1_Pos (6U)
26804#define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos)
26805#define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk
26806#define HRTIM_OUTR_DIDL1_Pos (7U)
26807#define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos)
26808#define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk
26810#define HRTIM_OUTR_DTEN_Pos (8U)
26811#define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos)
26812#define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk
26813#define HRTIM_OUTR_DLYPRTEN_Pos (9U)
26814#define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)
26815#define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk
26816#define HRTIM_OUTR_DLYPRT_Pos (10U)
26817#define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos)
26818#define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk
26819#define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos)
26820#define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos)
26821#define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos)
26823#define HRTIM_OUTR_POL2_Pos (17U)
26824#define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos)
26825#define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk
26826#define HRTIM_OUTR_IDLM2_Pos (18U)
26827#define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos)
26828#define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk
26829#define HRTIM_OUTR_IDLES2_Pos (19U)
26830#define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos)
26831#define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk
26832#define HRTIM_OUTR_FAULT2_Pos (20U)
26833#define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos)
26834#define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk
26835#define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos)
26836#define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos)
26837#define HRTIM_OUTR_CHP2_Pos (22U)
26838#define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos)
26839#define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk
26840#define HRTIM_OUTR_DIDL2_Pos (23U)
26841#define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos)
26842#define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk
26844/**** Bit definition for Slave Timer Fault register ***************************/
26845#define HRTIM_FLTR_FLT1EN_Pos (0U)
26846#define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos)
26847#define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk
26848#define HRTIM_FLTR_FLT2EN_Pos (1U)
26849#define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos)
26850#define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk
26851#define HRTIM_FLTR_FLT3EN_Pos (2U)
26852#define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos)
26853#define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk
26854#define HRTIM_FLTR_FLT4EN_Pos (3U)
26855#define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos)
26856#define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk
26857#define HRTIM_FLTR_FLT5EN_Pos (4U)
26858#define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos)
26859#define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk
26860#define HRTIM_FLTR_FLTLCK_Pos (31U)
26861#define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos)
26862#define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk
26864/**** Bit definition for Common HRTIM Timer control register 1 ****************/
26865#define HRTIM_CR1_MUDIS_Pos (0U)
26866#define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos)
26867#define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk
26868#define HRTIM_CR1_TAUDIS_Pos (1U)
26869#define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos)
26870#define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk
26871#define HRTIM_CR1_TBUDIS_Pos (2U)
26872#define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos)
26873#define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk
26874#define HRTIM_CR1_TCUDIS_Pos (3U)
26875#define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos)
26876#define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk
26877#define HRTIM_CR1_TDUDIS_Pos (4U)
26878#define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos)
26879#define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk
26880#define HRTIM_CR1_TEUDIS_Pos (5U)
26881#define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos)
26882#define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk
26883#define HRTIM_CR1_ADC1USRC_Pos (16U)
26884#define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos)
26885#define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk
26886#define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos)
26887#define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos)
26888#define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos)
26889#define HRTIM_CR1_ADC2USRC_Pos (19U)
26890#define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos)
26891#define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk
26892#define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos)
26893#define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos)
26894#define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos)
26895#define HRTIM_CR1_ADC3USRC_Pos (22U)
26896#define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos)
26897#define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk
26898#define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos)
26899#define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos)
26900#define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos)
26901#define HRTIM_CR1_ADC4USRC_Pos (25U)
26902#define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos)
26903#define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk
26904#define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos)
26905#define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos)
26906#define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos)
26908/**** Bit definition for Common HRTIM Timer control register 2 ****************/
26909#define HRTIM_CR2_MSWU_Pos (0U)
26910#define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos)
26911#define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk
26912#define HRTIM_CR2_TASWU_Pos (1U)
26913#define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos)
26914#define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk
26915#define HRTIM_CR2_TBSWU_Pos (2U)
26916#define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos)
26917#define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk
26918#define HRTIM_CR2_TCSWU_Pos (3U)
26919#define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos)
26920#define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk
26921#define HRTIM_CR2_TDSWU_Pos (4U)
26922#define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos)
26923#define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk
26924#define HRTIM_CR2_TESWU_Pos (5U)
26925#define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos)
26926#define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk
26927#define HRTIM_CR2_MRST_Pos (8U)
26928#define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos)
26929#define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk
26930#define HRTIM_CR2_TARST_Pos (9U)
26931#define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos)
26932#define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk
26933#define HRTIM_CR2_TBRST_Pos (10U)
26934#define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos)
26935#define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk
26936#define HRTIM_CR2_TCRST_Pos (11U)
26937#define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos)
26938#define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk
26939#define HRTIM_CR2_TDRST_Pos (12U)
26940#define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos)
26941#define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk
26942#define HRTIM_CR2_TERST_Pos (13U)
26943#define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos)
26944#define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk
26946/**** Bit definition for Common HRTIM Timer interrupt status register *********/
26947#define HRTIM_ISR_FLT1_Pos (0U)
26948#define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos)
26949#define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk
26950#define HRTIM_ISR_FLT2_Pos (1U)
26951#define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos)
26952#define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk
26953#define HRTIM_ISR_FLT3_Pos (2U)
26954#define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos)
26955#define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk
26956#define HRTIM_ISR_FLT4_Pos (3U)
26957#define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos)
26958#define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk
26959#define HRTIM_ISR_FLT5_Pos (4U)
26960#define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos)
26961#define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk
26962#define HRTIM_ISR_SYSFLT_Pos (5U)
26963#define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos)
26964#define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk
26965#define HRTIM_ISR_BMPER_Pos (17U)
26966#define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos)
26967#define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk
26969/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
26970#define HRTIM_ICR_FLT1C_Pos (0U)
26971#define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos)
26972#define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk
26973#define HRTIM_ICR_FLT2C_Pos (1U)
26974#define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos)
26975#define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk
26976#define HRTIM_ICR_FLT3C_Pos (2U)
26977#define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos)
26978#define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk
26979#define HRTIM_ICR_FLT4C_Pos (3U)
26980#define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos)
26981#define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk
26982#define HRTIM_ICR_FLT5C_Pos (4U)
26983#define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos)
26984#define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk
26985#define HRTIM_ICR_SYSFLTC_Pos (5U)
26986#define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos)
26987#define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk
26988#define HRTIM_ICR_BMPERC_Pos (17U)
26989#define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos)
26990#define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk
26992/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
26993#define HRTIM_IER_FLT1_Pos (0U)
26994#define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos)
26995#define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk
26996#define HRTIM_IER_FLT2_Pos (1U)
26997#define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos)
26998#define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk
26999#define HRTIM_IER_FLT3_Pos (2U)
27000#define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos)
27001#define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk
27002#define HRTIM_IER_FLT4_Pos (3U)
27003#define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos)
27004#define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk
27005#define HRTIM_IER_FLT5_Pos (4U)
27006#define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos)
27007#define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk
27008#define HRTIM_IER_SYSFLT_Pos (5U)
27009#define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos)
27010#define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk
27011#define HRTIM_IER_BMPER_Pos (17U)
27012#define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos)
27013#define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk
27015/**** Bit definition for Common HRTIM Timer output enable register ************/
27016#define HRTIM_OENR_TA1OEN_Pos (0U)
27017#define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos)
27018#define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk
27019#define HRTIM_OENR_TA2OEN_Pos (1U)
27020#define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos)
27021#define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk
27022#define HRTIM_OENR_TB1OEN_Pos (2U)
27023#define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos)
27024#define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk
27025#define HRTIM_OENR_TB2OEN_Pos (3U)
27026#define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos)
27027#define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk
27028#define HRTIM_OENR_TC1OEN_Pos (4U)
27029#define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos)
27030#define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk
27031#define HRTIM_OENR_TC2OEN_Pos (5U)
27032#define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos)
27033#define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk
27034#define HRTIM_OENR_TD1OEN_Pos (6U)
27035#define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos)
27036#define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk
27037#define HRTIM_OENR_TD2OEN_Pos (7U)
27038#define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos)
27039#define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk
27040#define HRTIM_OENR_TE1OEN_Pos (8U)
27041#define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos)
27042#define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk
27043#define HRTIM_OENR_TE2OEN_Pos (9U)
27044#define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos)
27045#define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk
27047/**** Bit definition for Common HRTIM Timer output disable register ***********/
27048#define HRTIM_ODISR_TA1ODIS_Pos (0U)
27049#define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)
27050#define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk
27051#define HRTIM_ODISR_TA2ODIS_Pos (1U)
27052#define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)
27053#define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk
27054#define HRTIM_ODISR_TB1ODIS_Pos (2U)
27055#define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)
27056#define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk
27057#define HRTIM_ODISR_TB2ODIS_Pos (3U)
27058#define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)
27059#define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk
27060#define HRTIM_ODISR_TC1ODIS_Pos (4U)
27061#define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)
27062#define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk
27063#define HRTIM_ODISR_TC2ODIS_Pos (5U)
27064#define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)
27065#define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk
27066#define HRTIM_ODISR_TD1ODIS_Pos (6U)
27067#define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)
27068#define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk
27069#define HRTIM_ODISR_TD2ODIS_Pos (7U)
27070#define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)
27071#define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk
27072#define HRTIM_ODISR_TE1ODIS_Pos (8U)
27073#define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)
27074#define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk
27075#define HRTIM_ODISR_TE2ODIS_Pos (9U)
27076#define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)
27077#define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk
27079/**** Bit definition for Common HRTIM Timer output disable status register *****/
27080#define HRTIM_ODSR_TA1ODS_Pos (0U)
27081#define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos)
27082#define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk
27083#define HRTIM_ODSR_TA2ODS_Pos (1U)
27084#define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos)
27085#define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk
27086#define HRTIM_ODSR_TB1ODS_Pos (2U)
27087#define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos)
27088#define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk
27089#define HRTIM_ODSR_TB2ODS_Pos (3U)
27090#define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos)
27091#define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk
27092#define HRTIM_ODSR_TC1ODS_Pos (4U)
27093#define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos)
27094#define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk
27095#define HRTIM_ODSR_TC2ODS_Pos (5U)
27096#define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos)
27097#define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk
27098#define HRTIM_ODSR_TD1ODS_Pos (6U)
27099#define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos)
27100#define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk
27101#define HRTIM_ODSR_TD2ODS_Pos (7U)
27102#define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos)
27103#define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk
27104#define HRTIM_ODSR_TE1ODS_Pos (8U)
27105#define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos)
27106#define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk
27107#define HRTIM_ODSR_TE2ODS_Pos (9U)
27108#define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos)
27109#define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk
27111/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
27112#define HRTIM_BMCR_BME_Pos (0U)
27113#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos)
27114#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk
27115#define HRTIM_BMCR_BMOM_Pos (1U)
27116#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos)
27117#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk
27118#define HRTIM_BMCR_BMCLK_Pos (2U)
27119#define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos)
27120#define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk
27121#define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos)
27122#define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos)
27123#define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos)
27124#define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos)
27125#define HRTIM_BMCR_BMPRSC_Pos (6U)
27126#define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos)
27127#define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk
27128#define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos)
27129#define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos)
27130#define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos)
27131#define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos)
27132#define HRTIM_BMCR_BMPREN_Pos (10U)
27133#define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos)
27134#define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk
27135#define HRTIM_BMCR_MTBM_Pos (16U)
27136#define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos)
27137#define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk
27138#define HRTIM_BMCR_TABM_Pos (17U)
27139#define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos)
27140#define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk
27141#define HRTIM_BMCR_TBBM_Pos (18U)
27142#define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos)
27143#define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk
27144#define HRTIM_BMCR_TCBM_Pos (19U)
27145#define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos)
27146#define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk
27147#define HRTIM_BMCR_TDBM_Pos (20U)
27148#define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos)
27149#define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk
27150#define HRTIM_BMCR_TEBM_Pos (21U)
27151#define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos)
27152#define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk
27153#define HRTIM_BMCR_BMSTAT_Pos (31U)
27154#define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos)
27155#define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk
27157/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
27158#define HRTIM_BMTRGR_SW_Pos (0U)
27159#define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos)
27160#define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk
27161#define HRTIM_BMTRGR_MSTRST_Pos (1U)
27162#define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)
27163#define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk
27164#define HRTIM_BMTRGR_MSTREP_Pos (2U)
27165#define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)
27166#define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk
27167#define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
27168#define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)
27169#define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk
27170#define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
27171#define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)
27172#define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk
27173#define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
27174#define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)
27175#define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk
27176#define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
27177#define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)
27178#define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk
27179#define HRTIM_BMTRGR_TARST_Pos (7U)
27180#define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos)
27181#define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk
27182#define HRTIM_BMTRGR_TAREP_Pos (8U)
27183#define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos)
27184#define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk
27185#define HRTIM_BMTRGR_TACMP1_Pos (9U)
27186#define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)
27187#define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk
27188#define HRTIM_BMTRGR_TACMP2_Pos (10U)
27189#define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)
27190#define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk
27191#define HRTIM_BMTRGR_TBRST_Pos (11U)
27192#define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos)
27193#define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk
27194#define HRTIM_BMTRGR_TBREP_Pos (12U)
27195#define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos)
27196#define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk
27197#define HRTIM_BMTRGR_TBCMP1_Pos (13U)
27198#define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)
27199#define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk
27200#define HRTIM_BMTRGR_TBCMP2_Pos (14U)
27201#define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)
27202#define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk
27203#define HRTIM_BMTRGR_TCRST_Pos (15U)
27204#define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos)
27205#define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk
27206#define HRTIM_BMTRGR_TCREP_Pos (16U)
27207#define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos)
27208#define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk
27209#define HRTIM_BMTRGR_TCCMP1_Pos (17U)
27210#define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)
27211#define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk
27212#define HRTIM_BMTRGR_TCCMP2_Pos (18U)
27213#define HRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)
27214#define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk
27215#define HRTIM_BMTRGR_TDRST_Pos (19U)
27216#define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos)
27217#define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk
27218#define HRTIM_BMTRGR_TDREP_Pos (20U)
27219#define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos)
27220#define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk
27221#define HRTIM_BMTRGR_TDCMP1_Pos (21U)
27222#define HRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)
27223#define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk
27224#define HRTIM_BMTRGR_TDCMP2_Pos (22U)
27225#define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)
27226#define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk
27227#define HRTIM_BMTRGR_TERST_Pos (23U)
27228#define HRTIM_BMTRGR_TERST_Msk (0x1UL << HRTIM_BMTRGR_TERST_Pos)
27229#define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk
27230#define HRTIM_BMTRGR_TEREP_Pos (24U)
27231#define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos)
27232#define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk
27233#define HRTIM_BMTRGR_TECMP1_Pos (25U)
27234#define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)
27235#define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk
27236#define HRTIM_BMTRGR_TECMP2_Pos (26U)
27237#define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)
27238#define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk
27239#define HRTIM_BMTRGR_TAEEV7_Pos (27U)
27240#define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)
27241#define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk
27242#define HRTIM_BMTRGR_TDEEV8_Pos (28U)
27243#define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)
27244#define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk
27245#define HRTIM_BMTRGR_EEV7_Pos (29U)
27246#define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos)
27247#define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk
27248#define HRTIM_BMTRGR_EEV8_Pos (30U)
27249#define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos)
27250#define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk
27251#define HRTIM_BMTRGR_OCHPEV_Pos (31U)
27252#define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)
27253#define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk
27255/******************* Bit definition for HRTIM_BMCMPR register ***************/
27256#define HRTIM_BMCMPR_BMCMPR_Pos (0U)
27257#define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)
27258#define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk
27260/******************* Bit definition for HRTIM_BMPER register ****************/
27261#define HRTIM_BMPER_BMPER_Pos (0U)
27262#define HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)
27263#define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk
27265/******************* Bit definition for HRTIM_EECR1 register ****************/
27266#define HRTIM_EECR1_EE1SRC_Pos (0U)
27267#define HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos)
27268#define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk
27269#define HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos)
27270#define HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos)
27271#define HRTIM_EECR1_EE1POL_Pos (2U)
27272#define HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos)
27273#define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk
27274#define HRTIM_EECR1_EE1SNS_Pos (3U)
27275#define HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos)
27276#define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk
27277#define HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos)
27278#define HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos)
27279#define HRTIM_EECR1_EE1FAST_Pos (5U)
27280#define HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos)
27281#define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk
27283#define HRTIM_EECR1_EE2SRC_Pos (6U)
27284#define HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos)
27285#define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk
27286#define HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos)
27287#define HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos)
27288#define HRTIM_EECR1_EE2POL_Pos (8U)
27289#define HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos)
27290#define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk
27291#define HRTIM_EECR1_EE2SNS_Pos (9U)
27292#define HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos)
27293#define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk
27294#define HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos)
27295#define HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos)
27296#define HRTIM_EECR1_EE2FAST_Pos (11U)
27297#define HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos)
27298#define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk
27300#define HRTIM_EECR1_EE3SRC_Pos (12U)
27301#define HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos)
27302#define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk
27303#define HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos)
27304#define HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos)
27305#define HRTIM_EECR1_EE3POL_Pos (14U)
27306#define HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos)
27307#define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk
27308#define HRTIM_EECR1_EE3SNS_Pos (15U)
27309#define HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos)
27310#define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk
27311#define HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos)
27312#define HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos)
27313#define HRTIM_EECR1_EE3FAST_Pos (17U)
27314#define HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos)
27315#define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk
27317#define HRTIM_EECR1_EE4SRC_Pos (18U)
27318#define HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos)
27319#define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk
27320#define HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos)
27321#define HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos)
27322#define HRTIM_EECR1_EE4POL_Pos (20U)
27323#define HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos)
27324#define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk
27325#define HRTIM_EECR1_EE4SNS_Pos (21U)
27326#define HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos)
27327#define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk
27328#define HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos)
27329#define HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos)
27330#define HRTIM_EECR1_EE4FAST_Pos (23U)
27331#define HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos)
27332#define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk
27334#define HRTIM_EECR1_EE5SRC_Pos (24U)
27335#define HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos)
27336#define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk
27337#define HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos)
27338#define HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos)
27339#define HRTIM_EECR1_EE5POL_Pos (26U)
27340#define HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos)
27341#define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk
27342#define HRTIM_EECR1_EE5SNS_Pos (27U)
27343#define HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos)
27344#define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk
27345#define HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos)
27346#define HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos)
27347#define HRTIM_EECR1_EE5FAST_Pos (29U)
27348#define HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos)
27349#define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk
27351/******************* Bit definition for HRTIM_EECR2 register ****************/
27352#define HRTIM_EECR2_EE6SRC_Pos (0U)
27353#define HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos)
27354#define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk
27355#define HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos)
27356#define HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos)
27357#define HRTIM_EECR2_EE6POL_Pos (2U)
27358#define HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos)
27359#define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk
27360#define HRTIM_EECR2_EE6SNS_Pos (3U)
27361#define HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos)
27362#define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk
27363#define HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos)
27364#define HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos)
27366#define HRTIM_EECR2_EE7SRC_Pos (6U)
27367#define HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos)
27368#define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk
27369#define HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos)
27370#define HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos)
27371#define HRTIM_EECR2_EE7POL_Pos (8U)
27372#define HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos)
27373#define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk
27374#define HRTIM_EECR2_EE7SNS_Pos (9U)
27375#define HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos)
27376#define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk
27377#define HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos)
27378#define HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos)
27380#define HRTIM_EECR2_EE8SRC_Pos (12U)
27381#define HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos)
27382#define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk
27383#define HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos)
27384#define HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos)
27385#define HRTIM_EECR2_EE8POL_Pos (14U)
27386#define HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos)
27387#define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk
27388#define HRTIM_EECR2_EE8SNS_Pos (15U)
27389#define HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos)
27390#define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk
27391#define HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos)
27392#define HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos)
27394#define HRTIM_EECR2_EE9SRC_Pos (18U)
27395#define HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos)
27396#define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk
27397#define HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos)
27398#define HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos)
27399#define HRTIM_EECR2_EE9POL_Pos (20U)
27400#define HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos)
27401#define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk
27402#define HRTIM_EECR2_EE9SNS_Pos (21U)
27403#define HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos)
27404#define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk
27405#define HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos)
27406#define HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos)
27408#define HRTIM_EECR2_EE10SRC_Pos (24U)
27409#define HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos)
27410#define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk
27411#define HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos)
27412#define HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos)
27413#define HRTIM_EECR2_EE10POL_Pos (26U)
27414#define HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos)
27415#define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk
27416#define HRTIM_EECR2_EE10SNS_Pos (27U)
27417#define HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos)
27418#define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk
27419#define HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos)
27420#define HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos)
27422/******************* Bit definition for HRTIM_EECR3 register ****************/
27423#define HRTIM_EECR3_EE6F_Pos (0U)
27424#define HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos)
27425#define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk
27426#define HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos)
27427#define HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos)
27428#define HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos)
27429#define HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos)
27430#define HRTIM_EECR3_EE7F_Pos (6U)
27431#define HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos)
27432#define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk
27433#define HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos)
27434#define HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos)
27435#define HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos)
27436#define HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos)
27437#define HRTIM_EECR3_EE8F_Pos (12U)
27438#define HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos)
27439#define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk
27440#define HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos)
27441#define HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos)
27442#define HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos)
27443#define HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos)
27444#define HRTIM_EECR3_EE9F_Pos (18U)
27445#define HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos)
27446#define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk
27447#define HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos)
27448#define HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos)
27449#define HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos)
27450#define HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos)
27451#define HRTIM_EECR3_EE10F_Pos (24U)
27452#define HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos)
27453#define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk
27454#define HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos)
27455#define HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos)
27456#define HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos)
27457#define HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos)
27458#define HRTIM_EECR3_EEVSD_Pos (30U)
27459#define HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos)
27460#define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk
27461#define HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos)
27462#define HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos)
27464/******************* Bit definition for HRTIM_ADC1R register ****************/
27465#define HRTIM_ADC1R_AD1MC1_Pos (0U)
27466#define HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)
27467#define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk
27468#define HRTIM_ADC1R_AD1MC2_Pos (1U)
27469#define HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)
27470#define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk
27471#define HRTIM_ADC1R_AD1MC3_Pos (2U)
27472#define HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)
27473#define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk
27474#define HRTIM_ADC1R_AD1MC4_Pos (3U)
27475#define HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)
27476#define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk
27477#define HRTIM_ADC1R_AD1MPER_Pos (4U)
27478#define HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)
27479#define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk
27480#define HRTIM_ADC1R_AD1EEV1_Pos (5U)
27481#define HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)
27482#define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk
27483#define HRTIM_ADC1R_AD1EEV2_Pos (6U)
27484#define HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)
27485#define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk
27486#define HRTIM_ADC1R_AD1EEV3_Pos (7U)
27487#define HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)
27488#define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk
27489#define HRTIM_ADC1R_AD1EEV4_Pos (8U)
27490#define HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)
27491#define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk
27492#define HRTIM_ADC1R_AD1EEV5_Pos (9U)
27493#define HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)
27494#define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk
27495#define HRTIM_ADC1R_AD1TAC2_Pos (10U)
27496#define HRTIM_ADC1R_AD1TAC2_Msk (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)
27497#define HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk
27498#define HRTIM_ADC1R_AD1TAC3_Pos (11U)
27499#define HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)
27500#define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk
27501#define HRTIM_ADC1R_AD1TAC4_Pos (12U)
27502#define HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)
27503#define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk
27504#define HRTIM_ADC1R_AD1TAPER_Pos (13U)
27505#define HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)
27506#define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk
27507#define HRTIM_ADC1R_AD1TARST_Pos (14U)
27508#define HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)
27509#define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk
27510#define HRTIM_ADC1R_AD1TBC2_Pos (15U)
27511#define HRTIM_ADC1R_AD1TBC2_Msk (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)
27512#define HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk
27513#define HRTIM_ADC1R_AD1TBC3_Pos (16U)
27514#define HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)
27515#define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk
27516#define HRTIM_ADC1R_AD1TBC4_Pos (17U)
27517#define HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)
27518#define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk
27519#define HRTIM_ADC1R_AD1TBPER_Pos (18U)
27520#define HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)
27521#define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk
27522#define HRTIM_ADC1R_AD1TBRST_Pos (19U)
27523#define HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)
27524#define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk
27525#define HRTIM_ADC1R_AD1TCC2_Pos (20U)
27526#define HRTIM_ADC1R_AD1TCC2_Msk (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)
27527#define HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk
27528#define HRTIM_ADC1R_AD1TCC3_Pos (21U)
27529#define HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)
27530#define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk
27531#define HRTIM_ADC1R_AD1TCC4_Pos (22U)
27532#define HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)
27533#define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk
27534#define HRTIM_ADC1R_AD1TCPER_Pos (23U)
27535#define HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)
27536#define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk
27537#define HRTIM_ADC1R_AD1TDC2_Pos (24U)
27538#define HRTIM_ADC1R_AD1TDC2_Msk (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)
27539#define HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk
27540#define HRTIM_ADC1R_AD1TDC3_Pos (25U)
27541#define HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)
27542#define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk
27543#define HRTIM_ADC1R_AD1TDC4_Pos (26U)
27544#define HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)
27545#define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk
27546#define HRTIM_ADC1R_AD1TDPER_Pos (27U)
27547#define HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)
27548#define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk
27549#define HRTIM_ADC1R_AD1TEC2_Pos (28U)
27550#define HRTIM_ADC1R_AD1TEC2_Msk (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)
27551#define HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk
27552#define HRTIM_ADC1R_AD1TEC3_Pos (29U)
27553#define HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)
27554#define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk
27555#define HRTIM_ADC1R_AD1TEC4_Pos (30U)
27556#define HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)
27557#define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk
27558#define HRTIM_ADC1R_AD1TEPER_Pos (31U)
27559#define HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)
27560#define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk
27562/******************* Bit definition for HRTIM_ADC2R register ****************/
27563#define HRTIM_ADC2R_AD2MC1_Pos (0U)
27564#define HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)
27565#define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk
27566#define HRTIM_ADC2R_AD2MC2_Pos (1U)
27567#define HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)
27568#define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk
27569#define HRTIM_ADC2R_AD2MC3_Pos (2U)
27570#define HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)
27571#define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk
27572#define HRTIM_ADC2R_AD2MC4_Pos (3U)
27573#define HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)
27574#define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk
27575#define HRTIM_ADC2R_AD2MPER_Pos (4U)
27576#define HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)
27577#define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk
27578#define HRTIM_ADC2R_AD2EEV6_Pos (5U)
27579#define HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)
27580#define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk
27581#define HRTIM_ADC2R_AD2EEV7_Pos (6U)
27582#define HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)
27583#define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk
27584#define HRTIM_ADC2R_AD2EEV8_Pos (7U)
27585#define HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)
27586#define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk
27587#define HRTIM_ADC2R_AD2EEV9_Pos (8U)
27588#define HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)
27589#define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk
27590#define HRTIM_ADC2R_AD2EEV10_Pos (9U)
27591#define HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)
27592#define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk
27593#define HRTIM_ADC2R_AD2TAC2_Pos (10U)
27594#define HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)
27595#define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk
27596#define HRTIM_ADC2R_AD2TAC3_Pos (11U)
27597#define HRTIM_ADC2R_AD2TAC3_Msk (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)
27598#define HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk
27599#define HRTIM_ADC2R_AD2TAC4_Pos (12U)
27600#define HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)
27601#define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk
27602#define HRTIM_ADC2R_AD2TAPER_Pos (13U)
27603#define HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)
27604#define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk
27605#define HRTIM_ADC2R_AD2TBC2_Pos (14U)
27606#define HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)
27607#define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk
27608#define HRTIM_ADC2R_AD2TBC3_Pos (15U)
27609#define HRTIM_ADC2R_AD2TBC3_Msk (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)
27610#define HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk
27611#define HRTIM_ADC2R_AD2TBC4_Pos (16U)
27612#define HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)
27613#define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk
27614#define HRTIM_ADC2R_AD2TBPER_Pos (17U)
27615#define HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)
27616#define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk
27617#define HRTIM_ADC2R_AD2TCC2_Pos (18U)
27618#define HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)
27619#define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk
27620#define HRTIM_ADC2R_AD2TCC3_Pos (19U)
27621#define HRTIM_ADC2R_AD2TCC3_Msk (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)
27622#define HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk
27623#define HRTIM_ADC2R_AD2TCC4_Pos (20U)
27624#define HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)
27625#define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk
27626#define HRTIM_ADC2R_AD2TCPER_Pos (21U)
27627#define HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)
27628#define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk
27629#define HRTIM_ADC2R_AD2TCRST_Pos (22U)
27630#define HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)
27631#define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk
27632#define HRTIM_ADC2R_AD2TDC2_Pos (23U)
27633#define HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)
27634#define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk
27635#define HRTIM_ADC2R_AD2TDC3_Pos (24U)
27636#define HRTIM_ADC2R_AD2TDC3_Msk (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)
27637#define HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk
27638#define HRTIM_ADC2R_AD2TDC4_Pos (25U)
27639#define HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)
27640#define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk
27641#define HRTIM_ADC2R_AD2TDPER_Pos (26U)
27642#define HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)
27643#define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk
27644#define HRTIM_ADC2R_AD2TDRST_Pos (27U)
27645#define HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)
27646#define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk
27647#define HRTIM_ADC2R_AD2TEC2_Pos (28U)
27648#define HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)
27649#define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk
27650#define HRTIM_ADC2R_AD2TEC3_Pos (29U)
27651#define HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)
27652#define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk
27653#define HRTIM_ADC2R_AD2TEC4_Pos (30U)
27654#define HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)
27655#define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk
27656#define HRTIM_ADC2R_AD2TERST_Pos (31U)
27657#define HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)
27658#define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk
27660/******************* Bit definition for HRTIM_ADC3R register ****************/
27661#define HRTIM_ADC3R_AD3MC1_Pos (0U)
27662#define HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)
27663#define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk
27664#define HRTIM_ADC3R_AD3MC2_Pos (1U)
27665#define HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)
27666#define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk
27667#define HRTIM_ADC3R_AD3MC3_Pos (2U)
27668#define HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)
27669#define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk
27670#define HRTIM_ADC3R_AD3MC4_Pos (3U)
27671#define HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)
27672#define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk
27673#define HRTIM_ADC3R_AD3MPER_Pos (4U)
27674#define HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)
27675#define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk
27676#define HRTIM_ADC3R_AD3EEV1_Pos (5U)
27677#define HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)
27678#define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk
27679#define HRTIM_ADC3R_AD3EEV2_Pos (6U)
27680#define HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)
27681#define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk
27682#define HRTIM_ADC3R_AD3EEV3_Pos (7U)
27683#define HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)
27684#define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk
27685#define HRTIM_ADC3R_AD3EEV4_Pos (8U)
27686#define HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)
27687#define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk
27688#define HRTIM_ADC3R_AD3EEV5_Pos (9U)
27689#define HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)
27690#define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk
27691#define HRTIM_ADC3R_AD3TAC2_Pos (10U)
27692#define HRTIM_ADC3R_AD3TAC2_Msk (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)
27693#define HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk
27694#define HRTIM_ADC3R_AD3TAC3_Pos (11U)
27695#define HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)
27696#define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk
27697#define HRTIM_ADC3R_AD3TAC4_Pos (12U)
27698#define HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)
27699#define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk
27700#define HRTIM_ADC3R_AD3TAPER_Pos (13U)
27701#define HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)
27702#define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk
27703#define HRTIM_ADC3R_AD3TARST_Pos (14U)
27704#define HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)
27705#define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk
27706#define HRTIM_ADC3R_AD3TBC2_Pos (15U)
27707#define HRTIM_ADC3R_AD3TBC2_Msk (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)
27708#define HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk
27709#define HRTIM_ADC3R_AD3TBC3_Pos (16U)
27710#define HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)
27711#define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk
27712#define HRTIM_ADC3R_AD3TBC4_Pos (17U)
27713#define HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)
27714#define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk
27715#define HRTIM_ADC3R_AD3TBPER_Pos (18U)
27716#define HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)
27717#define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk
27718#define HRTIM_ADC3R_AD3TBRST_Pos (19U)
27719#define HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)
27720#define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk
27721#define HRTIM_ADC3R_AD3TCC2_Pos (20U)
27722#define HRTIM_ADC3R_AD3TCC2_Msk (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)
27723#define HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk
27724#define HRTIM_ADC3R_AD3TCC3_Pos (21U)
27725#define HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)
27726#define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk
27727#define HRTIM_ADC3R_AD3TCC4_Pos (22U)
27728#define HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)
27729#define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk
27730#define HRTIM_ADC3R_AD3TCPER_Pos (23U)
27731#define HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)
27732#define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk
27733#define HRTIM_ADC3R_AD3TDC2_Pos (24U)
27734#define HRTIM_ADC3R_AD3TDC2_Msk (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)
27735#define HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk
27736#define HRTIM_ADC3R_AD3TDC3_Pos (25U)
27737#define HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)
27738#define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk
27739#define HRTIM_ADC3R_AD3TDC4_Pos (26U)
27740#define HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)
27741#define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk
27742#define HRTIM_ADC3R_AD3TDPER_Pos (27U)
27743#define HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)
27744#define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk
27745#define HRTIM_ADC3R_AD3TEC2_Pos (28U)
27746#define HRTIM_ADC3R_AD3TEC2_Msk (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)
27747#define HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk
27748#define HRTIM_ADC3R_AD3TEC3_Pos (29U)
27749#define HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)
27750#define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk
27751#define HRTIM_ADC3R_AD3TEC4_Pos (30U)
27752#define HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)
27753#define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk
27754#define HRTIM_ADC3R_AD3TEPER_Pos (31U)
27755#define HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)
27756#define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk
27758/******************* Bit definition for HRTIM_ADC4R register ****************/
27759#define HRTIM_ADC4R_AD4MC1_Pos (0U)
27760#define HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)
27761#define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk
27762#define HRTIM_ADC4R_AD4MC2_Pos (1U)
27763#define HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)
27764#define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk
27765#define HRTIM_ADC4R_AD4MC3_Pos (2U)
27766#define HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)
27767#define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk
27768#define HRTIM_ADC4R_AD4MC4_Pos (3U)
27769#define HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)
27770#define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk
27771#define HRTIM_ADC4R_AD4MPER_Pos (4U)
27772#define HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)
27773#define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk
27774#define HRTIM_ADC4R_AD4EEV6_Pos (5U)
27775#define HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)
27776#define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk
27777#define HRTIM_ADC4R_AD4EEV7_Pos (6U)
27778#define HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)
27779#define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk
27780#define HRTIM_ADC4R_AD4EEV8_Pos (7U)
27781#define HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)
27782#define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk
27783#define HRTIM_ADC4R_AD4EEV9_Pos (8U)
27784#define HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)
27785#define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk
27786#define HRTIM_ADC4R_AD4EEV10_Pos (9U)
27787#define HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)
27788#define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk
27789#define HRTIM_ADC4R_AD4TAC2_Pos (10U)
27790#define HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)
27791#define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk
27792#define HRTIM_ADC4R_AD4TAC3_Pos (11U)
27793#define HRTIM_ADC4R_AD4TAC3_Msk (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)
27794#define HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk
27795#define HRTIM_ADC4R_AD4TAC4_Pos (12U)
27796#define HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)
27797#define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk
27798#define HRTIM_ADC4R_AD4TAPER_Pos (13U)
27799#define HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)
27800#define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk
27801#define HRTIM_ADC4R_AD4TBC2_Pos (14U)
27802#define HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)
27803#define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk
27804#define HRTIM_ADC4R_AD4TBC3_Pos (15U)
27805#define HRTIM_ADC4R_AD4TBC3_Msk (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)
27806#define HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk
27807#define HRTIM_ADC4R_AD4TBC4_Pos (16U)
27808#define HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)
27809#define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk
27810#define HRTIM_ADC4R_AD4TBPER_Pos (17U)
27811#define HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)
27812#define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk
27813#define HRTIM_ADC4R_AD4TCC2_Pos (18U)
27814#define HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)
27815#define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk
27816#define HRTIM_ADC4R_AD4TCC3_Pos (19U)
27817#define HRTIM_ADC4R_AD4TCC3_Msk (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)
27818#define HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk
27819#define HRTIM_ADC4R_AD4TCC4_Pos (20U)
27820#define HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)
27821#define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk
27822#define HRTIM_ADC4R_AD4TCPER_Pos (21U)
27823#define HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)
27824#define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk
27825#define HRTIM_ADC4R_AD4TCRST_Pos (22U)
27826#define HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)
27827#define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk
27828#define HRTIM_ADC4R_AD4TDC2_Pos (23U)
27829#define HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)
27830#define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk
27831#define HRTIM_ADC4R_AD4TDC3_Pos (24U)
27832#define HRTIM_ADC4R_AD4TDC3_Msk (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)
27833#define HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk
27834#define HRTIM_ADC4R_AD4TDC4_Pos (25U)
27835#define HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)
27836#define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk
27837#define HRTIM_ADC4R_AD4TDPER_Pos (26U)
27838#define HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)
27839#define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk
27840#define HRTIM_ADC4R_AD4TDRST_Pos (27U)
27841#define HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)
27842#define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk
27843#define HRTIM_ADC4R_AD4TEC2_Pos (28U)
27844#define HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)
27845#define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk
27846#define HRTIM_ADC4R_AD4TEC3_Pos (29U)
27847#define HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)
27848#define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk
27849#define HRTIM_ADC4R_AD4TEC4_Pos (30U)
27850#define HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)
27851#define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk
27852#define HRTIM_ADC4R_AD4TERST_Pos (31U)
27853#define HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)
27854#define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk
27856/******************* Bit definition for HRTIM_FLTINR1 register ***************/
27857#define HRTIM_FLTINR1_FLT1E_Pos (0U)
27858#define HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)
27859#define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk
27860#define HRTIM_FLTINR1_FLT1P_Pos (1U)
27861#define HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)
27862#define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk
27863#define HRTIM_FLTINR1_FLT1SRC_Pos (2U)
27864#define HRTIM_FLTINR1_FLT1SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)
27865#define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk
27866#define HRTIM_FLTINR1_FLT1F_Pos (3U)
27867#define HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)
27868#define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk
27869#define HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)
27870#define HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)
27871#define HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)
27872#define HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)
27873#define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
27874#define HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)
27875#define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk
27877#define HRTIM_FLTINR1_FLT2E_Pos (8U)
27878#define HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)
27879#define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk
27880#define HRTIM_FLTINR1_FLT2P_Pos (9U)
27881#define HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)
27882#define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk
27883#define HRTIM_FLTINR1_FLT2SRC_Pos (10U)
27884#define HRTIM_FLTINR1_FLT2SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)
27885#define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk
27886#define HRTIM_FLTINR1_FLT2F_Pos (11U)
27887#define HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)
27888#define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk
27889#define HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)
27890#define HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)
27891#define HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)
27892#define HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)
27893#define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
27894#define HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)
27895#define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk
27897#define HRTIM_FLTINR1_FLT3E_Pos (16U)
27898#define HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)
27899#define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk
27900#define HRTIM_FLTINR1_FLT3P_Pos (17U)
27901#define HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)
27902#define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk
27903#define HRTIM_FLTINR1_FLT3SRC_Pos (18U)
27904#define HRTIM_FLTINR1_FLT3SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)
27905#define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk
27906#define HRTIM_FLTINR1_FLT3F_Pos (19U)
27907#define HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)
27908#define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk
27909#define HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)
27910#define HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)
27911#define HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)
27912#define HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)
27913#define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
27914#define HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)
27915#define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk
27917#define HRTIM_FLTINR1_FLT4E_Pos (24U)
27918#define HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)
27919#define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk
27920#define HRTIM_FLTINR1_FLT4P_Pos (25U)
27921#define HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)
27922#define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk
27923#define HRTIM_FLTINR1_FLT4SRC_Pos (26U)
27924#define HRTIM_FLTINR1_FLT4SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)
27925#define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk
27926#define HRTIM_FLTINR1_FLT4F_Pos (27U)
27927#define HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)
27928#define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk
27929#define HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)
27930#define HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)
27931#define HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)
27932#define HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)
27933#define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
27934#define HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)
27935#define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk
27937/******************* Bit definition for HRTIM_FLTINR2 register ***************/
27938#define HRTIM_FLTINR2_FLT5E_Pos (0U)
27939#define HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)
27940#define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk
27941#define HRTIM_FLTINR2_FLT5P_Pos (1U)
27942#define HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)
27943#define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk
27944#define HRTIM_FLTINR2_FLT5SRC_Pos (2U)
27945#define HRTIM_FLTINR2_FLT5SRC_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)
27946#define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk
27947#define HRTIM_FLTINR2_FLT5F_Pos (3U)
27948#define HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)
27949#define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk
27950#define HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)
27951#define HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)
27952#define HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)
27953#define HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)
27954#define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
27955#define HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)
27956#define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk
27957#define HRTIM_FLTINR2_FLTSD_Pos (24U)
27958#define HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)
27959#define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk
27960#define HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)
27961#define HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)
27963/******************* Bit definition for HRTIM_BDMUPR register ***************/
27964#define HRTIM_BDMUPR_MCR_Pos (0U)
27965#define HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos)
27966#define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk
27967#define HRTIM_BDMUPR_MICR_Pos (1U)
27968#define HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos)
27969#define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk
27970#define HRTIM_BDMUPR_MDIER_Pos (2U)
27971#define HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos)
27972#define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk
27973#define HRTIM_BDMUPR_MCNT_Pos (3U)
27974#define HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos)
27975#define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk
27976#define HRTIM_BDMUPR_MPER_Pos (4U)
27977#define HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos)
27978#define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk
27979#define HRTIM_BDMUPR_MREP_Pos (5U)
27980#define HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos)
27981#define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk
27982#define HRTIM_BDMUPR_MCMP1_Pos (6U)
27983#define HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)
27984#define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk
27985#define HRTIM_BDMUPR_MCMP2_Pos (7U)
27986#define HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)
27987#define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk
27988#define HRTIM_BDMUPR_MCMP3_Pos (8U)
27989#define HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)
27990#define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk
27991#define HRTIM_BDMUPR_MCMP4_Pos (9U)
27992#define HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)
27993#define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk
27995/******************* Bit definition for HRTIM_BDTUPR register ***************/
27996#define HRTIM_BDTUPR_TIMCR_Pos (0U)
27997#define HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)
27998#define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk
27999#define HRTIM_BDTUPR_TIMICR_Pos (1U)
28000#define HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)
28001#define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk
28002#define HRTIM_BDTUPR_TIMDIER_Pos (2U)
28003#define HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)
28004#define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk
28005#define HRTIM_BDTUPR_TIMCNT_Pos (3U)
28006#define HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)
28007#define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk
28008#define HRTIM_BDTUPR_TIMPER_Pos (4U)
28009#define HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)
28010#define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk
28011#define HRTIM_BDTUPR_TIMREP_Pos (5U)
28012#define HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)
28013#define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk
28014#define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
28015#define HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)
28016#define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk
28017#define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
28018#define HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)
28019#define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk
28020#define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
28021#define HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)
28022#define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk
28023#define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
28024#define HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)
28025#define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk
28026#define HRTIM_BDTUPR_TIMDTR_Pos (10U)
28027#define HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)
28028#define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk
28029#define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
28030#define HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)
28031#define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk
28032#define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
28033#define HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)
28034#define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk
28035#define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
28036#define HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)
28037#define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk
28038#define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
28039#define HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)
28040#define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk
28041#define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
28042#define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)
28043#define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk
28044#define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
28045#define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)
28046#define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk
28047#define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
28048#define HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)
28049#define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk
28050#define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
28051#define HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)
28052#define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk
28053#define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
28054#define HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)
28055#define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk
28056#define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
28057#define HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)
28058#define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk
28060/******************* Bit definition for HRTIM_BDMADR register ***************/
28061#define HRTIM_BDMADR_BDMADR_Pos (0U)
28062#define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos)
28063#define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk
28065/******************************************************************************/
28066/* */
28067/* RAM ECC monitoring */
28068/* */
28069/******************************************************************************/
28070/****************** Bit definition for RAMECC_IER register ******************/
28071#define RAMECC_IER_GECCDEBWIE_Pos (3U)
28072#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)
28073#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk
28074#define RAMECC_IER_GECCDEIE_Pos (2U)
28075#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos)
28076#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk
28077#define RAMECC_IER_GECCSEIE_Pos (1U)
28078#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos)
28079#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk
28080#define RAMECC_IER_GIE_Pos (0U)
28081#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos)
28082#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk
28084/******************* Bit definition for RAMECC_CR register ******************/
28085#define RAMECC_CR_ECCELEN_Pos (5U)
28086#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos)
28087#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk
28088#define RAMECC_CR_ECCDEBWIE_Pos (4U)
28089#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)
28090#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk
28091#define RAMECC_CR_ECCDEIE_Pos (3U)
28092#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos)
28093#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk
28094#define RAMECC_CR_ECCSEIE_Pos (2U)
28095#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos)
28096#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk
28098/******************* Bit definition for RAMECC_SR register ******************/
28099#define RAMECC_SR_DEBWDF_Pos (2U)
28100#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos)
28101#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk
28102#define RAMECC_SR_DEDF_Pos (1U)
28103#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos)
28104#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk
28105#define RAMECC_SR_SEDCF_Pos (0U)
28106#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos)
28107#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk
28109/****************** Bit definition for RAMECC_FAR register ******************/
28110#define RAMECC_FAR_FADD_Pos (0U)
28111#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)
28112#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk
28114/****************** Bit definition for RAMECC_FDRL register *****************/
28115#define RAMECC_FAR_FDATAL_Pos (0U)
28116#define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)
28117#define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk
28119/****************** Bit definition for RAMECC_FDRH register *****************/
28120#define RAMECC_FAR_FDATAH_Pos (0U)
28121#define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)
28122#define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
28123
28124/***************** Bit definition for RAMECC_FECR register ******************/
28125#define RAMECC_FECR_FEC_Pos (0U)
28126#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)
28127#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk
28129/******************************************************************************/
28130/* */
28131/* MDIOS */
28132/* */
28133/******************************************************************************/
28134/******************** Bit definition for MDIOS_CR register *******************/
28135#define MDIOS_CR_EN_Pos (0U)
28136#define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos)
28137#define MDIOS_CR_EN MDIOS_CR_EN_Msk
28138#define MDIOS_CR_WRIE_Pos (1U)
28139#define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos)
28140#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk
28141#define MDIOS_CR_RDIE_Pos (2U)
28142#define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos)
28143#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk
28144#define MDIOS_CR_EIE_Pos (3U)
28145#define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos)
28146#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk
28147#define MDIOS_CR_DPC_Pos (7U)
28148#define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos)
28149#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk
28150#define MDIOS_CR_PORT_ADDRESS_Pos (8U)
28151#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)
28152#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk
28153#define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)
28154#define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)
28155#define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)
28156#define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)
28157#define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)
28159/******************** Bit definition for MDIOS_SR register *******************/
28160#define MDIOS_SR_PERF_Pos (0U)
28161#define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos)
28162#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk
28163#define MDIOS_SR_SERF_Pos (1U)
28164#define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos)
28165#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk
28166#define MDIOS_SR_TERF_Pos (2U)
28167#define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos)
28168#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk
28170/******************** Bit definition for MDIOS_CLRFR register *******************/
28171#define MDIOS_SR_CPERF_Pos (0U)
28172#define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos)
28173#define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk
28174#define MDIOS_SR_CSERF_Pos (1U)
28175#define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos)
28176#define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk
28177#define MDIOS_SR_CTERF_Pos (2U)
28178#define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos)
28179#define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk
28181/******************************************************************************/
28182/* */
28183/* USB_OTG */
28184/* */
28185/******************************************************************************/
28186/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
28187#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
28188#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
28189#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
28190#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
28191#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
28192#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
28193#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
28194#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
28195#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
28196#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
28197#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
28198#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
28199#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
28200#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
28201#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
28202#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
28203#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
28204#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
28205#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
28206#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
28207#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
28208#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
28209#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
28210#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
28211#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
28212#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
28213#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
28214#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
28215#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
28216#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
28217#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
28218#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
28219#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
28220#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
28221#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
28222#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
28223#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
28224#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
28225#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
28226#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
28227#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
28228#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
28229#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
28230#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
28231#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
28232#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
28233#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
28234#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
28235#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
28236#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
28237#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
28238#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
28239#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
28240#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
28242/******************** Bit definition forUSB_OTG_HCFG register ********************/
28243
28244#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
28245#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
28246#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
28247#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
28248#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
28249#define USB_OTG_HCFG_FSLSS_Pos (2U)
28250#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
28251#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
28253/******************** Bit definition forUSB_OTG_DCFG register ********************/
28254
28255#define USB_OTG_DCFG_DSPD_Pos (0U)
28256#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
28257#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
28258#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
28259#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
28260#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
28261#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
28262#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
28264#define USB_OTG_DCFG_DAD_Pos (4U)
28265#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
28266#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
28267#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
28268#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
28269#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
28270#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
28271#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
28272#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
28273#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
28275#define USB_OTG_DCFG_PFIVL_Pos (11U)
28276#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
28277#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
28278#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
28279#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
28281#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
28282#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
28283#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
28284#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
28285#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
28287/******************** Bit definition forUSB_OTG_PCGCR register ********************/
28288#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
28289#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
28290#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
28291#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
28292#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
28293#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
28294#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
28295#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
28296#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
28298/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
28299#define USB_OTG_GOTGINT_SEDET_Pos (2U)
28300#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
28301#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
28302#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
28303#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
28304#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
28305#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
28306#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
28307#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
28308#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
28309#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
28310#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
28311#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
28312#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
28313#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
28314#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
28315#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
28316#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
28318/******************** Bit definition forUSB_OTG_DCTL register ********************/
28319#define USB_OTG_DCTL_RWUSIG_Pos (0U)
28320#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
28321#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
28322#define USB_OTG_DCTL_SDIS_Pos (1U)
28323#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
28324#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
28325#define USB_OTG_DCTL_GINSTS_Pos (2U)
28326#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
28327#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
28328#define USB_OTG_DCTL_GONSTS_Pos (3U)
28329#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
28330#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
28332#define USB_OTG_DCTL_TCTL_Pos (4U)
28333#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
28334#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
28335#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
28336#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
28337#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
28338#define USB_OTG_DCTL_SGINAK_Pos (7U)
28339#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
28340#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
28341#define USB_OTG_DCTL_CGINAK_Pos (8U)
28342#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
28343#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
28344#define USB_OTG_DCTL_SGONAK_Pos (9U)
28345#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
28346#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
28347#define USB_OTG_DCTL_CGONAK_Pos (10U)
28348#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
28349#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
28350#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
28351#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
28352#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
28354/******************** Bit definition forUSB_OTG_HFIR register ********************/
28355#define USB_OTG_HFIR_FRIVL_Pos (0U)
28356#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
28357#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
28359/******************** Bit definition forUSB_OTG_HFNUM register ********************/
28360#define USB_OTG_HFNUM_FRNUM_Pos (0U)
28361#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
28362#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
28363#define USB_OTG_HFNUM_FTREM_Pos (16U)
28364#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
28365#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
28367/******************** Bit definition forUSB_OTG_DSTS register ********************/
28368#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
28369#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
28370#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
28372#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
28373#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
28374#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
28375#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
28376#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
28377#define USB_OTG_DSTS_EERR_Pos (3U)
28378#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
28379#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
28380#define USB_OTG_DSTS_FNSOF_Pos (8U)
28381#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
28382#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
28384/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
28385#define USB_OTG_GAHBCFG_GINT_Pos (0U)
28386#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
28387#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
28389#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
28390#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
28391#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
28392#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
28393#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
28394#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
28395#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
28396#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
28397#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
28398#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
28399#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
28400#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
28401#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
28402#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
28403#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
28404#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
28405#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
28407/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
28408
28409#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
28410#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
28411#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
28412#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
28413#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
28414#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
28415#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
28416#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
28417#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
28418#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
28419#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
28420#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
28421#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
28422#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
28423#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
28425#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
28426#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
28427#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
28428#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
28429#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
28430#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
28431#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
28432#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
28433#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
28434#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
28435#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
28436#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
28437#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
28438#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
28439#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
28440#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
28441#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
28442#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
28443#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
28444#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
28445#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
28446#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
28447#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
28448#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
28449#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
28450#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
28451#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
28452#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
28453#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
28454#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
28455#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
28456#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
28457#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
28458#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
28459#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
28460#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
28461#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
28462#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
28463#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
28464#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
28465#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
28466#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
28467#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
28468#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
28469#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
28470#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
28472/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
28473#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
28474#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
28475#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
28476#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
28477#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
28478#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
28479#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
28480#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
28481#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
28482#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
28483#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
28484#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
28485#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
28486#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
28487#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
28489#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
28490#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
28491#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
28492#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
28493#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
28494#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
28495#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
28496#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
28497#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
28498#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
28499#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
28500#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
28501#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
28502#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
28504/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
28505#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
28506#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
28507#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
28508#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
28509#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
28510#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
28511#define USB_OTG_DIEPMSK_TOM_Pos (3U)
28512#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
28513#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
28514#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
28515#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
28516#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
28517#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
28518#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
28519#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
28520#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
28521#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
28522#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
28523#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
28524#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
28525#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
28526#define USB_OTG_DIEPMSK_BIM_Pos (9U)
28527#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
28528#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
28530/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
28531#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
28532#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
28533#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
28535#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
28536#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
28537#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
28538#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
28539#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
28540#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
28541#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
28542#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
28543#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
28544#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
28545#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
28547#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
28548#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
28549#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
28550#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
28551#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
28552#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
28553#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
28554#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
28555#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
28556#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
28557#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
28559/******************** Bit definition forUSB_OTG_HAINT register ********************/
28560#define USB_OTG_HAINT_HAINT_Pos (0U)
28561#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
28562#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
28564/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
28565#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
28566#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
28567#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
28568#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
28569#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
28570#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
28571#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
28572#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
28573#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
28574#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
28575#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
28576#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
28577#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
28578#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
28579#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
28580#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
28581#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
28582#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
28583#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
28584#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
28585#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
28586#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
28587#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
28588#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
28589#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
28590#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
28591#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
28592#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
28593#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
28594#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
28595#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
28596#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
28597#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
28598#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
28599#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
28600#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
28602/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
28603#define USB_OTG_GINTSTS_CMOD_Pos (0U)
28604#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
28605#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
28606#define USB_OTG_GINTSTS_MMIS_Pos (1U)
28607#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
28608#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
28609#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
28610#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
28611#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
28612#define USB_OTG_GINTSTS_SOF_Pos (3U)
28613#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
28614#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
28615#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
28616#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
28617#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
28618#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
28619#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
28620#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
28621#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
28622#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
28623#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
28624#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
28625#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
28626#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
28627#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
28628#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
28629#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
28630#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
28631#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
28632#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
28633#define USB_OTG_GINTSTS_USBRST_Pos (12U)
28634#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
28635#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
28636#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
28637#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
28638#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
28639#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
28640#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
28641#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
28642#define USB_OTG_GINTSTS_EOPF_Pos (15U)
28643#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
28644#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
28645#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
28646#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
28647#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
28648#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
28649#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
28650#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
28651#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
28652#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
28653#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
28654#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
28655#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
28656#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
28657#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
28658#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
28659#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
28660#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
28661#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
28662#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
28663#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
28664#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
28665#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
28666#define USB_OTG_GINTSTS_HCINT_Pos (25U)
28667#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
28668#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
28669#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
28670#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
28671#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
28672#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
28673#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
28674#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
28675#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
28676#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
28677#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
28678#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
28679#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
28680#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
28681#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
28682#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
28683#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
28684#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
28685#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
28686#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
28688/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
28689#define USB_OTG_GINTMSK_MMISM_Pos (1U)
28690#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
28691#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
28692#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
28693#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
28694#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
28695#define USB_OTG_GINTMSK_SOFM_Pos (3U)
28696#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
28697#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
28698#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
28699#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
28700#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
28701#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
28702#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
28703#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
28704#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
28705#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
28706#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
28707#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
28708#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
28709#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
28710#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
28711#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
28712#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
28713#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
28714#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
28715#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
28716#define USB_OTG_GINTMSK_USBRST_Pos (12U)
28717#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
28718#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
28719#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
28720#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
28721#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
28722#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
28723#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
28724#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
28725#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
28726#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
28727#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
28728#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
28729#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
28730#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
28731#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
28732#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
28733#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
28734#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
28735#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
28736#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
28737#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
28738#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
28739#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
28740#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
28741#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
28742#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
28743#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
28744#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
28745#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
28746#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
28747#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
28748#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
28749#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
28750#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
28751#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
28752#define USB_OTG_GINTMSK_HCIM_Pos (25U)
28753#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
28754#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
28755#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
28756#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
28757#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
28758#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
28759#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
28760#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
28761#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
28762#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
28763#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
28764#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
28765#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
28766#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
28767#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
28768#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
28769#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
28770#define USB_OTG_GINTMSK_WUIM_Pos (31U)
28771#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
28772#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
28774/******************** Bit definition forUSB_OTG_DAINT register ********************/
28775#define USB_OTG_DAINT_IEPINT_Pos (0U)
28776#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
28777#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
28778#define USB_OTG_DAINT_OEPINT_Pos (16U)
28779#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
28780#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
28782/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
28783#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
28784#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
28785#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
28787/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
28788#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
28789#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
28790#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
28791#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
28792#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
28793#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
28794#define USB_OTG_GRXSTSP_DPID_Pos (15U)
28795#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
28796#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
28797#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
28798#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
28799#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
28801/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
28802#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
28803#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
28804#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
28805#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
28806#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
28807#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
28809/******************** Bit definition for OTG register ********************/
28810
28811#define USB_OTG_CHNUM_Pos (0U)
28812#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
28813#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
28814#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
28815#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
28816#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
28817#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
28818#define USB_OTG_BCNT_Pos (4U)
28819#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
28820#define USB_OTG_BCNT USB_OTG_BCNT_Msk
28822#define USB_OTG_DPID_Pos (15U)
28823#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
28824#define USB_OTG_DPID USB_OTG_DPID_Msk
28825#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
28826#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
28828#define USB_OTG_PKTSTS_Pos (17U)
28829#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
28830#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
28831#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
28832#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
28833#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
28834#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
28836#define USB_OTG_EPNUM_Pos (0U)
28837#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
28838#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
28839#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
28840#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
28841#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
28842#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
28844#define USB_OTG_FRMNUM_Pos (21U)
28845#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
28846#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
28847#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
28848#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
28849#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
28850#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
28852/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
28853#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
28854#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
28855#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
28857/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
28858#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
28859#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
28860#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
28862/******************** Bit definition for OTG register ********************/
28863#define USB_OTG_NPTXFSA_Pos (0U)
28864#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
28865#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
28866#define USB_OTG_NPTXFD_Pos (16U)
28867#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
28868#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
28869#define USB_OTG_TX0FSA_Pos (0U)
28870#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
28871#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
28872#define USB_OTG_TX0FD_Pos (16U)
28873#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
28874#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
28876/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
28877#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
28878#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
28879#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
28881/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
28882#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
28883#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
28884#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
28886#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
28887#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
28888#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
28889#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
28890#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
28891#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
28892#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
28893#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
28894#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
28895#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
28896#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
28898#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
28899#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
28900#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
28901#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
28902#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
28903#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
28904#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
28905#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
28906#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
28907#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
28909/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
28910#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
28911#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
28912#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
28913#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
28914#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
28915#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
28917#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
28918#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
28919#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
28920#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
28921#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
28922#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
28923#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
28924#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
28925#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
28926#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
28927#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
28928#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
28929#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
28930#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
28931#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
28933#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
28934#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
28935#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
28936#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
28937#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
28938#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
28939#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
28940#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
28941#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
28942#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
28943#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
28944#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
28945#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
28946#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
28947#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
28949/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
28950#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
28951#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
28952#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
28954/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
28955#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
28956#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
28957#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
28958#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
28959#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
28960#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
28962/******************** Bit definition forUSB_OTG_GCCFG register ********************/
28963#define USB_OTG_GCCFG_DCDET_Pos (0U)
28964#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos)
28965#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk
28966#define USB_OTG_GCCFG_PDET_Pos (1U)
28967#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos)
28968#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk
28969#define USB_OTG_GCCFG_SDET_Pos (2U)
28970#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos)
28971#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk
28972#define USB_OTG_GCCFG_PS2DET_Pos (3U)
28973#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos)
28974#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk
28975#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
28976#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
28977#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
28978#define USB_OTG_GCCFG_BCDEN_Pos (17U)
28979#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos)
28980#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk
28981#define USB_OTG_GCCFG_DCDEN_Pos (18U)
28982#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos)
28983#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk
28984#define USB_OTG_GCCFG_PDEN_Pos (19U)
28985#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos)
28986#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk
28987#define USB_OTG_GCCFG_SDEN_Pos (20U)
28988#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos)
28989#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk
28990#define USB_OTG_GCCFG_VBDEN_Pos (21U)
28991#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
28992#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
28994/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
28995#define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
28996#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos)
28997#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk
28998#define USB_OTG_GPWRDN_ADPIF_Pos (23U)
28999#define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos)
29000#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk
29002/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
29003#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
29004#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
29005#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
29006#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
29007#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
29008#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
29010/******************** Bit definition forUSB_OTG_CID register ********************/
29011#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
29012#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
29013#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
29015/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
29016#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
29017#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
29018#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
29019#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
29020#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
29021#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
29022#define USB_OTG_GLPMCFG_BESL_Pos (2U)
29023#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
29024#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
29025#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
29026#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
29027#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
29028#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
29029#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
29030#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
29031#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
29032#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
29033#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
29034#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
29035#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
29036#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
29037#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
29038#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
29039#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
29040#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
29041#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
29042#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
29043#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
29044#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
29045#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
29046#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
29047#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
29048#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
29049#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
29050#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
29051#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
29052#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
29053#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
29054#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
29055#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
29056#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
29057#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
29058#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
29059#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
29060#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
29062/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
29063#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
29064#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
29065#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
29066#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
29067#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
29068#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
29069#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
29070#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
29071#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
29072#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
29073#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
29074#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
29075#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
29076#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
29077#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
29078#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
29079#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
29080#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
29081#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
29082#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
29083#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
29084#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
29085#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
29086#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
29087#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
29088#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
29089#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
29091/******************** Bit definition forUSB_OTG_HPRT register ********************/
29092#define USB_OTG_HPRT_PCSTS_Pos (0U)
29093#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
29094#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
29095#define USB_OTG_HPRT_PCDET_Pos (1U)
29096#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
29097#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
29098#define USB_OTG_HPRT_PENA_Pos (2U)
29099#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
29100#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
29101#define USB_OTG_HPRT_PENCHNG_Pos (3U)
29102#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
29103#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
29104#define USB_OTG_HPRT_POCA_Pos (4U)
29105#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
29106#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
29107#define USB_OTG_HPRT_POCCHNG_Pos (5U)
29108#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
29109#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
29110#define USB_OTG_HPRT_PRES_Pos (6U)
29111#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
29112#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
29113#define USB_OTG_HPRT_PSUSP_Pos (7U)
29114#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
29115#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
29116#define USB_OTG_HPRT_PRST_Pos (8U)
29117#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
29118#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
29120#define USB_OTG_HPRT_PLSTS_Pos (10U)
29121#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
29122#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
29123#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
29124#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
29125#define USB_OTG_HPRT_PPWR_Pos (12U)
29126#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
29127#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
29129#define USB_OTG_HPRT_PTCTL_Pos (13U)
29130#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
29131#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
29132#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
29133#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
29134#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
29135#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
29137#define USB_OTG_HPRT_PSPD_Pos (17U)
29138#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
29139#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
29140#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
29141#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
29143/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
29144#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
29145#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
29146#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
29147#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
29148#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
29149#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
29150#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
29151#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
29152#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
29153#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
29154#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
29155#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
29156#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
29157#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
29158#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
29159#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
29160#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
29161#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
29162#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
29163#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
29164#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
29165#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
29166#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
29167#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
29168#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
29169#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
29170#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
29171#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
29172#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
29173#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
29174#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
29175#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
29176#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
29178/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
29179#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
29180#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
29181#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
29182#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
29183#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
29184#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
29186/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
29187#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
29188#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
29189#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
29190#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
29191#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
29192#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
29193#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
29194#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
29195#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
29196#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
29197#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
29198#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
29200#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
29201#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
29202#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
29203#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
29204#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
29205#define USB_OTG_DIEPCTL_STALL_Pos (21U)
29206#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
29207#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
29209#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
29210#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
29211#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
29212#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
29213#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
29214#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
29215#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
29216#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
29217#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
29218#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
29219#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
29220#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
29221#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
29222#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
29223#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
29224#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
29225#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
29226#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
29227#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
29228#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
29229#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
29230#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
29231#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
29232#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
29233#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
29235/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
29236#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
29237#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
29238#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
29240#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
29241#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
29242#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
29243#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
29244#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
29245#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
29246#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
29247#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
29248#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
29249#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
29250#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
29251#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
29252#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
29254#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
29255#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
29256#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
29257#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
29258#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
29260#define USB_OTG_HCCHAR_MC_Pos (20U)
29261#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
29262#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
29263#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
29264#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
29266#define USB_OTG_HCCHAR_DAD_Pos (22U)
29267#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
29268#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
29269#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
29270#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
29271#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
29272#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
29273#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
29274#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
29275#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
29276#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
29277#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
29278#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
29279#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
29280#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
29281#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
29282#define USB_OTG_HCCHAR_CHENA_Pos (31U)
29283#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
29284#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
29286/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
29287
29288#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
29289#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
29290#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
29291#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
29292#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
29293#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
29294#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
29295#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
29296#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
29297#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
29299#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
29300#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
29301#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
29302#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
29303#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
29304#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
29305#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
29306#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
29307#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
29308#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
29310#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
29311#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
29312#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
29313#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
29314#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
29315#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
29316#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
29317#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
29318#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
29319#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
29320#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
29322/******************** Bit definition forUSB_OTG_HCINT register ********************/
29323#define USB_OTG_HCINT_XFRC_Pos (0U)
29324#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
29325#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
29326#define USB_OTG_HCINT_CHH_Pos (1U)
29327#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
29328#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
29329#define USB_OTG_HCINT_AHBERR_Pos (2U)
29330#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
29331#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
29332#define USB_OTG_HCINT_STALL_Pos (3U)
29333#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
29334#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
29335#define USB_OTG_HCINT_NAK_Pos (4U)
29336#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
29337#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
29338#define USB_OTG_HCINT_ACK_Pos (5U)
29339#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
29340#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
29341#define USB_OTG_HCINT_NYET_Pos (6U)
29342#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
29343#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
29344#define USB_OTG_HCINT_TXERR_Pos (7U)
29345#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
29346#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
29347#define USB_OTG_HCINT_BBERR_Pos (8U)
29348#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
29349#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
29350#define USB_OTG_HCINT_FRMOR_Pos (9U)
29351#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
29352#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
29353#define USB_OTG_HCINT_DTERR_Pos (10U)
29354#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
29355#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
29357/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
29358#define USB_OTG_DIEPINT_XFRC_Pos (0U)
29359#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
29360#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
29361#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
29362#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
29363#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
29364#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
29365#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
29366#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
29367#define USB_OTG_DIEPINT_TOC_Pos (3U)
29368#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
29369#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
29370#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
29371#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
29372#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
29373#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
29374#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
29375#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
29376#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
29377#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
29378#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
29379#define USB_OTG_DIEPINT_TXFE_Pos (7U)
29380#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
29381#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
29382#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
29383#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
29384#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
29385#define USB_OTG_DIEPINT_BNA_Pos (9U)
29386#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
29387#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
29388#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
29389#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
29390#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
29391#define USB_OTG_DIEPINT_BERR_Pos (12U)
29392#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
29393#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
29394#define USB_OTG_DIEPINT_NAK_Pos (13U)
29395#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
29396#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
29398/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
29399#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
29400#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
29401#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
29402#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
29403#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
29404#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
29405#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
29406#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
29407#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
29408#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
29409#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
29410#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
29411#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
29412#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
29413#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
29414#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
29415#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
29416#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
29417#define USB_OTG_HCINTMSK_NYET_Pos (6U)
29418#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
29419#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
29420#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
29421#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
29422#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
29423#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
29424#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
29425#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
29426#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
29427#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
29428#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
29429#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
29430#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
29431#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
29433/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
29434
29435#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
29436#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
29437#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
29438#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
29439#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
29440#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
29441#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
29442#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
29443#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
29444/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
29445#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
29446#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
29447#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
29448#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
29449#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
29450#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
29451#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
29452#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
29453#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
29454#define USB_OTG_HCTSIZ_DPID_Pos (29U)
29455#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
29456#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
29457#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
29458#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
29460/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
29461#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
29462#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
29463#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
29465/******************** Bit definition forUSB_OTG_HCDMA register ********************/
29466#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
29467#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
29468#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
29470/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
29471#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
29472#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
29473#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
29475/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
29476#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
29477#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
29478#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
29479#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
29480#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
29481#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
29483/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
29484
29485#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
29486#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
29487#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
29488#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
29489#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
29490#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
29491#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
29492#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
29493#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
29494#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
29495#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
29496#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
29497#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
29498#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
29499#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
29500#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
29501#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
29502#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
29503#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
29504#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
29505#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
29506#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
29507#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
29508#define USB_OTG_DOEPCTL_STALL_Pos (21U)
29509#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
29510#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
29511#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
29512#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
29513#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
29514#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
29515#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
29516#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
29517#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
29518#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
29519#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
29520#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
29521#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
29522#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
29524/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
29525#define USB_OTG_DOEPINT_XFRC_Pos (0U)
29526#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
29527#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
29528#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
29529#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
29530#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
29531#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
29532#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
29533#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
29534#define USB_OTG_DOEPINT_STUP_Pos (3U)
29535#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
29536#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
29537#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
29538#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
29539#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
29540#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
29541#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
29542#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
29543#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
29544#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
29545#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
29546#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
29547#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
29548#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
29549#define USB_OTG_DOEPINT_BERR_Pos (12U)
29550#define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos)
29551#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk
29552#define USB_OTG_DOEPINT_NAK_Pos (13U)
29553#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
29554#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
29555#define USB_OTG_DOEPINT_NYET_Pos (14U)
29556#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
29557#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
29558#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
29559#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
29560#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
29562/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
29563
29564#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
29565#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
29566#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
29567#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
29568#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
29569#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
29571#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
29572#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
29573#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
29574#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
29575#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
29577/******************** Bit definition for PCGCCTL register ********************/
29578#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
29579#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
29580#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
29581#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
29582#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
29583#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
29584#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
29585#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
29586#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
29600/******************************* ADC Instances ********************************/
29601#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
29602 ((INSTANCE) == ADC2) || \
29603 ((INSTANCE) == ADC3))
29604
29605#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
29606
29607#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
29608 ((INSTANCE) == ADC3_COMMON))
29609
29610/******************************** COMP Instances ******************************/
29611#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
29612 ((INSTANCE) == COMP2))
29613
29614#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
29615/******************** COMP Instances with window mode capability **************/
29616#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
29617
29618
29619/******************************* CRC Instances ********************************/
29620#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
29621
29622/******************************* DAC Instances ********************************/
29623#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
29624/******************************* DCMI Instances *******************************/
29625#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
29626
29627/******************************* DELAYBLOCK Instances *******************************/
29628#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
29629 ((INSTANCE) == DLYB_SDMMC2) || \
29630 ((INSTANCE) == DLYB_QUADSPI))
29631/****************************** DFSDM Instances *******************************/
29632#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
29633 ((INSTANCE) == DFSDM1_Filter1) || \
29634 ((INSTANCE) == DFSDM1_Filter2) || \
29635 ((INSTANCE) == DFSDM1_Filter3))
29636
29637#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
29638 ((INSTANCE) == DFSDM1_Channel1) || \
29639 ((INSTANCE) == DFSDM1_Channel2) || \
29640 ((INSTANCE) == DFSDM1_Channel3) || \
29641 ((INSTANCE) == DFSDM1_Channel4) || \
29642 ((INSTANCE) == DFSDM1_Channel5) || \
29643 ((INSTANCE) == DFSDM1_Channel6) || \
29644 ((INSTANCE) == DFSDM1_Channel7))
29645/****************************** RAMECC Instances ******************************/
29646#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1) || \
29647 ((INSTANCE) == RAMECC1_Monitor2) || \
29648 ((INSTANCE) == RAMECC1_Monitor3) || \
29649 ((INSTANCE) == RAMECC1_Monitor4) || \
29650 ((INSTANCE) == RAMECC1_Monitor5) || \
29651 ((INSTANCE) == RAMECC2_Monitor1) || \
29652 ((INSTANCE) == RAMECC2_Monitor2) || \
29653 ((INSTANCE) == RAMECC2_Monitor3) || \
29654 ((INSTANCE) == RAMECC2_Monitor4) || \
29655 ((INSTANCE) == RAMECC2_Monitor5) || \
29656 ((INSTANCE) == RAMECC3_Monitor1) || \
29657 ((INSTANCE) == RAMECC3_Monitor2))
29658
29659/******************************** DMA Instances *******************************/
29660#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
29661 ((INSTANCE) == DMA1_Stream1) || \
29662 ((INSTANCE) == DMA1_Stream2) || \
29663 ((INSTANCE) == DMA1_Stream3) || \
29664 ((INSTANCE) == DMA1_Stream4) || \
29665 ((INSTANCE) == DMA1_Stream5) || \
29666 ((INSTANCE) == DMA1_Stream6) || \
29667 ((INSTANCE) == DMA1_Stream7) || \
29668 ((INSTANCE) == DMA2_Stream0) || \
29669 ((INSTANCE) == DMA2_Stream1) || \
29670 ((INSTANCE) == DMA2_Stream2) || \
29671 ((INSTANCE) == DMA2_Stream3) || \
29672 ((INSTANCE) == DMA2_Stream4) || \
29673 ((INSTANCE) == DMA2_Stream5) || \
29674 ((INSTANCE) == DMA2_Stream6) || \
29675 ((INSTANCE) == DMA2_Stream7) || \
29676 ((INSTANCE) == BDMA_Channel0) || \
29677 ((INSTANCE) == BDMA_Channel1) || \
29678 ((INSTANCE) == BDMA_Channel2) || \
29679 ((INSTANCE) == BDMA_Channel3) || \
29680 ((INSTANCE) == BDMA_Channel4) || \
29681 ((INSTANCE) == BDMA_Channel5) || \
29682 ((INSTANCE) == BDMA_Channel6) || \
29683 ((INSTANCE) == BDMA_Channel7))
29684
29685/****************************** BDMA CHANNEL Instances ***************************/
29686#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
29687 ((INSTANCE) == BDMA_Channel1) || \
29688 ((INSTANCE) == BDMA_Channel2) || \
29689 ((INSTANCE) == BDMA_Channel3) || \
29690 ((INSTANCE) == BDMA_Channel4) || \
29691 ((INSTANCE) == BDMA_Channel5) || \
29692 ((INSTANCE) == BDMA_Channel6) || \
29693 ((INSTANCE) == BDMA_Channel7))
29694
29695/****************************** DMA DMAMUX ALL Instances ***************************/
29696#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
29697 ((INSTANCE) == DMA1_Stream1) || \
29698 ((INSTANCE) == DMA1_Stream2) || \
29699 ((INSTANCE) == DMA1_Stream3) || \
29700 ((INSTANCE) == DMA1_Stream4) || \
29701 ((INSTANCE) == DMA1_Stream5) || \
29702 ((INSTANCE) == DMA1_Stream6) || \
29703 ((INSTANCE) == DMA1_Stream7) || \
29704 ((INSTANCE) == DMA2_Stream0) || \
29705 ((INSTANCE) == DMA2_Stream1) || \
29706 ((INSTANCE) == DMA2_Stream2) || \
29707 ((INSTANCE) == DMA2_Stream3) || \
29708 ((INSTANCE) == DMA2_Stream4) || \
29709 ((INSTANCE) == DMA2_Stream5) || \
29710 ((INSTANCE) == DMA2_Stream6) || \
29711 ((INSTANCE) == DMA2_Stream7) || \
29712 ((INSTANCE) == BDMA_Channel0) || \
29713 ((INSTANCE) == BDMA_Channel1) || \
29714 ((INSTANCE) == BDMA_Channel2) || \
29715 ((INSTANCE) == BDMA_Channel3) || \
29716 ((INSTANCE) == BDMA_Channel4) || \
29717 ((INSTANCE) == BDMA_Channel5) || \
29718 ((INSTANCE) == BDMA_Channel6) || \
29719 ((INSTANCE) == BDMA_Channel7))
29720
29721/****************************** BDMA DMAMUX Instances ***************************/
29722#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
29723 ((INSTANCE) == BDMA_Channel1) || \
29724 ((INSTANCE) == BDMA_Channel2) || \
29725 ((INSTANCE) == BDMA_Channel3) || \
29726 ((INSTANCE) == BDMA_Channel4) || \
29727 ((INSTANCE) == BDMA_Channel5) || \
29728 ((INSTANCE) == BDMA_Channel6) || \
29729 ((INSTANCE) == BDMA_Channel7))
29730
29731/****************************** DMA STREAM Instances ***************************/
29732#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
29733 ((INSTANCE) == DMA1_Stream1) || \
29734 ((INSTANCE) == DMA1_Stream2) || \
29735 ((INSTANCE) == DMA1_Stream3) || \
29736 ((INSTANCE) == DMA1_Stream4) || \
29737 ((INSTANCE) == DMA1_Stream5) || \
29738 ((INSTANCE) == DMA1_Stream6) || \
29739 ((INSTANCE) == DMA1_Stream7) || \
29740 ((INSTANCE) == DMA2_Stream0) || \
29741 ((INSTANCE) == DMA2_Stream1) || \
29742 ((INSTANCE) == DMA2_Stream2) || \
29743 ((INSTANCE) == DMA2_Stream3) || \
29744 ((INSTANCE) == DMA2_Stream4) || \
29745 ((INSTANCE) == DMA2_Stream5) || \
29746 ((INSTANCE) == DMA2_Stream6) || \
29747 ((INSTANCE) == DMA2_Stream7))
29748
29749/****************************** DMA DMAMUX Instances ***************************/
29750#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
29751 ((INSTANCE) == DMA1_Stream1) || \
29752 ((INSTANCE) == DMA1_Stream2) || \
29753 ((INSTANCE) == DMA1_Stream3) || \
29754 ((INSTANCE) == DMA1_Stream4) || \
29755 ((INSTANCE) == DMA1_Stream5) || \
29756 ((INSTANCE) == DMA1_Stream6) || \
29757 ((INSTANCE) == DMA1_Stream7) || \
29758 ((INSTANCE) == DMA2_Stream0) || \
29759 ((INSTANCE) == DMA2_Stream1) || \
29760 ((INSTANCE) == DMA2_Stream2) || \
29761 ((INSTANCE) == DMA2_Stream3) || \
29762 ((INSTANCE) == DMA2_Stream4) || \
29763 ((INSTANCE) == DMA2_Stream5) || \
29764 ((INSTANCE) == DMA2_Stream6) || \
29765 ((INSTANCE) == DMA2_Stream7))
29766
29767/******************************** DMA Request Generator Instances **************/
29768#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
29769 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
29770 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
29771 ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
29772 ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
29773 ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
29774 ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
29775 ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
29776 ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
29777 ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
29778 ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
29779 ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
29780 ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
29781 ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
29782 ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
29783 ((INSTANCE) == DMAMUX2_RequestGenerator7))
29784
29785/******************************* DMA2D Instances *******************************/
29786#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
29787
29788/******************************** MDMA Request Generator Instances **************/
29789#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
29790 ((INSTANCE) == MDMA_Channel1) || \
29791 ((INSTANCE) == MDMA_Channel2) || \
29792 ((INSTANCE) == MDMA_Channel3) || \
29793 ((INSTANCE) == MDMA_Channel4) || \
29794 ((INSTANCE) == MDMA_Channel5) || \
29795 ((INSTANCE) == MDMA_Channel6) || \
29796 ((INSTANCE) == MDMA_Channel7) || \
29797 ((INSTANCE) == MDMA_Channel8) || \
29798 ((INSTANCE) == MDMA_Channel9) || \
29799 ((INSTANCE) == MDMA_Channel10) || \
29800 ((INSTANCE) == MDMA_Channel11) || \
29801 ((INSTANCE) == MDMA_Channel12) || \
29802 ((INSTANCE) == MDMA_Channel13) || \
29803 ((INSTANCE) == MDMA_Channel14) || \
29804 ((INSTANCE) == MDMA_Channel15))
29805
29806/******************************* QUADSPI Instances *******************************/
29807#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
29808
29809/******************************* FDCAN Instances ******************************/
29810#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
29811 ((__INSTANCE__) == FDCAN2))
29812
29813#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
29814
29815/******************************* GPIO Instances *******************************/
29816#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
29817 ((INSTANCE) == GPIOB) || \
29818 ((INSTANCE) == GPIOC) || \
29819 ((INSTANCE) == GPIOD) || \
29820 ((INSTANCE) == GPIOE) || \
29821 ((INSTANCE) == GPIOF) || \
29822 ((INSTANCE) == GPIOG) || \
29823 ((INSTANCE) == GPIOH) || \
29824 ((INSTANCE) == GPIOI) || \
29825 ((INSTANCE) == GPIOJ) || \
29826 ((INSTANCE) == GPIOK))
29827
29828/******************************* GPIO AF Instances ****************************/
29829#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
29830
29831/**************************** GPIO Lock Instances *****************************/
29832/* On H7, all GPIO Bank support the Lock mechanism */
29833#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
29834
29835/******************************** HSEM Instances *******************************/
29836#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
29837/******************** Bit definition for HSEM_CR register *****************/
29838#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
29839#define HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */
29840#define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
29841#define HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
29842#if defined(CORE_CM4)
29843#define HSEM_CR_COREID_CURRENT (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
29844#else /* CORE_CM7 */
29845#define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
29846#endif /* CORE_CM4 */
29847
29848#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
29849#define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
29850
29851#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
29852#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
29853
29854#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
29855#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
29856
29857/******************************** I2C Instances *******************************/
29858#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
29859 ((INSTANCE) == I2C2) || \
29860 ((INSTANCE) == I2C3) || \
29861 ((INSTANCE) == I2C4))
29862
29863/****************************** SMBUS Instances *******************************/
29864#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
29865 ((INSTANCE) == I2C2) || \
29866 ((INSTANCE) == I2C3) || \
29867 ((INSTANCE) == I2C4))
29868
29869/************** I2C Instances : wakeup capability from stop modes *************/
29870#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
29871
29872/******************************** I2S Instances *******************************/
29873#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
29874 ((INSTANCE) == SPI2) || \
29875 ((INSTANCE) == SPI3))
29876
29877/****************************** LTDC Instances ********************************/
29878#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
29879
29880/******************************* RNG Instances ********************************/
29881#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
29882
29883/****************************** RTC Instances *********************************/
29884#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
29885
29886/****************************** SDMMC Instances *********************************/
29887#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
29888 ((_INSTANCE_) == SDMMC2))
29889
29890/******************************** SPI Instances *******************************/
29891#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
29892 ((INSTANCE) == SPI2) || \
29893 ((INSTANCE) == SPI3) || \
29894 ((INSTANCE) == SPI4) || \
29895 ((INSTANCE) == SPI5) || \
29896 ((INSTANCE) == SPI6))
29897
29898#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
29899 ((INSTANCE) == SPI2) || \
29900 ((INSTANCE) == SPI3))
29901
29902/******************************** SWPMI Instances *****************************/
29903#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
29904
29905/****************** LPTIM Instances : All supported instances *****************/
29906#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
29907 ((INSTANCE) == LPTIM2) || \
29908 ((INSTANCE) == LPTIM3) || \
29909 ((INSTANCE) == LPTIM4) || \
29910 ((INSTANCE) == LPTIM5))
29911
29912/****************** LPTIM Instances : supporting encoder interface **************/
29913#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
29914 ((INSTANCE) == LPTIM2))
29915
29916/****************** TIM Instances : All supported instances *******************/
29917#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29918 ((INSTANCE) == TIM2) || \
29919 ((INSTANCE) == TIM3) || \
29920 ((INSTANCE) == TIM4) || \
29921 ((INSTANCE) == TIM5) || \
29922 ((INSTANCE) == TIM6) || \
29923 ((INSTANCE) == TIM7) || \
29924 ((INSTANCE) == TIM8) || \
29925 ((INSTANCE) == TIM12) || \
29926 ((INSTANCE) == TIM13) || \
29927 ((INSTANCE) == TIM14) || \
29928 ((INSTANCE) == TIM15) || \
29929 ((INSTANCE) == TIM16) || \
29930 ((INSTANCE) == TIM17))
29931
29932/************* TIM Instances : at least 1 capture/compare channel *************/
29933#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29934 ((INSTANCE) == TIM2) || \
29935 ((INSTANCE) == TIM3) || \
29936 ((INSTANCE) == TIM4) || \
29937 ((INSTANCE) == TIM5) || \
29938 ((INSTANCE) == TIM8) || \
29939 ((INSTANCE) == TIM12) || \
29940 ((INSTANCE) == TIM13) || \
29941 ((INSTANCE) == TIM14) || \
29942 ((INSTANCE) == TIM15) || \
29943 ((INSTANCE) == TIM16) || \
29944 ((INSTANCE) == TIM17))
29945
29946/************ TIM Instances : at least 2 capture/compare channels *************/
29947#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29948 ((INSTANCE) == TIM2) || \
29949 ((INSTANCE) == TIM3) || \
29950 ((INSTANCE) == TIM4) || \
29951 ((INSTANCE) == TIM5) || \
29952 ((INSTANCE) == TIM8) || \
29953 ((INSTANCE) == TIM12) || \
29954 ((INSTANCE) == TIM15))
29955
29956/************ TIM Instances : at least 3 capture/compare channels *************/
29957#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29958 ((INSTANCE) == TIM2) || \
29959 ((INSTANCE) == TIM3) || \
29960 ((INSTANCE) == TIM4) || \
29961 ((INSTANCE) == TIM5) || \
29962 ((INSTANCE) == TIM8))
29963
29964/************ TIM Instances : at least 4 capture/compare channels *************/
29965#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29966 ((INSTANCE) == TIM2) || \
29967 ((INSTANCE) == TIM3) || \
29968 ((INSTANCE) == TIM4) || \
29969 ((INSTANCE) == TIM5) || \
29970 ((INSTANCE) == TIM8))
29971
29972/************ TIM Instances : at least 5 capture/compare channels *************/
29973#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29974 ((INSTANCE) == TIM8))
29975/************ TIM Instances : at least 6 capture/compare channels *************/
29976#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29977 ((INSTANCE) == TIM8))
29978
29979/******************** TIM Instances : Advanced-control timers *****************/
29980#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
29981 ((__INSTANCE__) == TIM8))
29982
29983/******************** TIM Instances : Advanced-control timers *****************/
29984
29985/******************* TIM Instances : Timer input XOR function *****************/
29986#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29987 ((INSTANCE) == TIM2) || \
29988 ((INSTANCE) == TIM3) || \
29989 ((INSTANCE) == TIM4) || \
29990 ((INSTANCE) == TIM5) || \
29991 ((INSTANCE) == TIM8) || \
29992 ((INSTANCE) == TIM15))
29993
29994/****************** TIM Instances : DMA requests generation (UDE) *************/
29995#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29996 ((INSTANCE) == TIM2) || \
29997 ((INSTANCE) == TIM3) || \
29998 ((INSTANCE) == TIM4) || \
29999 ((INSTANCE) == TIM5) || \
30000 ((INSTANCE) == TIM6) || \
30001 ((INSTANCE) == TIM7) || \
30002 ((INSTANCE) == TIM8) || \
30003 ((INSTANCE) == TIM15) || \
30004 ((INSTANCE) == TIM16) || \
30005 ((INSTANCE) == TIM17))
30006
30007/************ TIM Instances : DMA requests generation (CCxDE) *****************/
30008#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30009 ((INSTANCE) == TIM2) || \
30010 ((INSTANCE) == TIM3) || \
30011 ((INSTANCE) == TIM4) || \
30012 ((INSTANCE) == TIM5) || \
30013 ((INSTANCE) == TIM8) || \
30014 ((INSTANCE) == TIM15) || \
30015 ((INSTANCE) == TIM16) || \
30016 ((INSTANCE) == TIM17))
30017
30018/************ TIM Instances : DMA requests generation (COMDE) *****************/
30019#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30020 ((INSTANCE) == TIM2) || \
30021 ((INSTANCE) == TIM3) || \
30022 ((INSTANCE) == TIM4) || \
30023 ((INSTANCE) == TIM5) || \
30024 ((INSTANCE) == TIM8) || \
30025 ((INSTANCE) == TIM15))
30026
30027/******************** TIM Instances : DMA burst feature ***********************/
30028#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30029 ((INSTANCE) == TIM2) || \
30030 ((INSTANCE) == TIM3) || \
30031 ((INSTANCE) == TIM4) || \
30032 ((INSTANCE) == TIM5) || \
30033 ((INSTANCE) == TIM8))
30034
30035/*************** TIM Instances : external trigger reamp input available *******/
30036#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30037 ((INSTANCE) == TIM2) || \
30038 ((INSTANCE) == TIM3) || \
30039 ((INSTANCE) == TIM4) || \
30040 ((INSTANCE) == TIM5) || \
30041 ((INSTANCE) == TIM8))
30042
30043/****************** TIM Instances : remapping capability **********************/
30044#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30045 ((INSTANCE) == TIM2) || \
30046 ((INSTANCE) == TIM3) || \
30047 ((INSTANCE) == TIM5) || \
30048 ((INSTANCE) == TIM8) || \
30049 ((INSTANCE) == TIM16) || \
30050 ((INSTANCE) == TIM17))
30051
30052/*************** TIM Instances : external trigger reamp input available *******/
30053#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30054 ((INSTANCE) == TIM2) || \
30055 ((INSTANCE) == TIM3) || \
30056 ((INSTANCE) == TIM5) || \
30057 ((INSTANCE) == TIM8))
30058
30059/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
30060#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30061 ((INSTANCE) == TIM2) || \
30062 ((INSTANCE) == TIM3) || \
30063 ((INSTANCE) == TIM4) || \
30064 ((INSTANCE) == TIM5) || \
30065 ((INSTANCE) == TIM6) || \
30066 ((INSTANCE) == TIM7) || \
30067 ((INSTANCE) == TIM8) || \
30068 ((INSTANCE) == TIM12) || \
30069 ((INSTANCE) == TIM15))
30070
30071/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
30072#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30073 ((INSTANCE) == TIM2) || \
30074 ((INSTANCE) == TIM3) || \
30075 ((INSTANCE) == TIM4) || \
30076 ((INSTANCE) == TIM5) || \
30077 ((INSTANCE) == TIM8) || \
30078 ((INSTANCE) == TIM12) || \
30079 ((INSTANCE) == TIM15))
30080
30081/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
30082#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30083 ((INSTANCE) == TIM8))
30084
30085/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
30086#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30087 ((INSTANCE) == TIM2) || \
30088 ((INSTANCE) == TIM3) || \
30089 ((INSTANCE) == TIM4) || \
30090 ((INSTANCE) == TIM5) || \
30091 ((INSTANCE) == TIM8) || \
30092 ((INSTANCE) == TIM15) || \
30093 ((INSTANCE) == TIM16) || \
30094 ((INSTANCE) == TIM17))
30095
30096/****************** TIM Instances : supporting commutation event *************/
30097#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30098 ((INSTANCE) == TIM8) || \
30099 ((INSTANCE) == TIM15) || \
30100 ((INSTANCE) == TIM16) || \
30101 ((INSTANCE) == TIM17))
30102
30103/****************** TIM Instances : supporting encoder interface **************/
30104#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
30105 ((__INSTANCE__) == TIM2) || \
30106 ((__INSTANCE__) == TIM3) || \
30107 ((__INSTANCE__) == TIM4) || \
30108 ((__INSTANCE__) == TIM5) || \
30109 ((__INSTANCE__) == TIM8))
30110
30111/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
30112#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30113 ((INSTANCE) == TIM8))
30114/******************* TIM Instances : output(s) available **********************/
30115#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
30116 ((((INSTANCE) == TIM1) && \
30117 (((CHANNEL) == TIM_CHANNEL_1) || \
30118 ((CHANNEL) == TIM_CHANNEL_2) || \
30119 ((CHANNEL) == TIM_CHANNEL_3) || \
30120 ((CHANNEL) == TIM_CHANNEL_4) || \
30121 ((CHANNEL) == TIM_CHANNEL_5) || \
30122 ((CHANNEL) == TIM_CHANNEL_6))) \
30123 || \
30124 (((INSTANCE) == TIM2) && \
30125 (((CHANNEL) == TIM_CHANNEL_1) || \
30126 ((CHANNEL) == TIM_CHANNEL_2) || \
30127 ((CHANNEL) == TIM_CHANNEL_3) || \
30128 ((CHANNEL) == TIM_CHANNEL_4))) \
30129 || \
30130 (((INSTANCE) == TIM3) && \
30131 (((CHANNEL) == TIM_CHANNEL_1)|| \
30132 ((CHANNEL) == TIM_CHANNEL_2) || \
30133 ((CHANNEL) == TIM_CHANNEL_3) || \
30134 ((CHANNEL) == TIM_CHANNEL_4))) \
30135 || \
30136 (((INSTANCE) == TIM4) && \
30137 (((CHANNEL) == TIM_CHANNEL_1) || \
30138 ((CHANNEL) == TIM_CHANNEL_2) || \
30139 ((CHANNEL) == TIM_CHANNEL_3) || \
30140 ((CHANNEL) == TIM_CHANNEL_4))) \
30141 || \
30142 (((INSTANCE) == TIM5) && \
30143 (((CHANNEL) == TIM_CHANNEL_1) || \
30144 ((CHANNEL) == TIM_CHANNEL_2) || \
30145 ((CHANNEL) == TIM_CHANNEL_3) || \
30146 ((CHANNEL) == TIM_CHANNEL_4))) \
30147 || \
30148 (((INSTANCE) == TIM8) && \
30149 (((CHANNEL) == TIM_CHANNEL_1) || \
30150 ((CHANNEL) == TIM_CHANNEL_2) || \
30151 ((CHANNEL) == TIM_CHANNEL_3) || \
30152 ((CHANNEL) == TIM_CHANNEL_4) || \
30153 ((CHANNEL) == TIM_CHANNEL_5) || \
30154 ((CHANNEL) == TIM_CHANNEL_6))) \
30155 || \
30156 (((INSTANCE) == TIM12) && \
30157 (((CHANNEL) == TIM_CHANNEL_1) || \
30158 ((CHANNEL) == TIM_CHANNEL_2))) \
30159 || \
30160 (((INSTANCE) == TIM13) && \
30161 (((CHANNEL) == TIM_CHANNEL_1))) \
30162 || \
30163 (((INSTANCE) == TIM14) && \
30164 (((CHANNEL) == TIM_CHANNEL_1))) \
30165 || \
30166 (((INSTANCE) == TIM15) && \
30167 (((CHANNEL) == TIM_CHANNEL_1) || \
30168 ((CHANNEL) == TIM_CHANNEL_2))) \
30169 || \
30170 (((INSTANCE) == TIM16) && \
30171 (((CHANNEL) == TIM_CHANNEL_1))) \
30172 || \
30173 (((INSTANCE) == TIM17) && \
30174 (((CHANNEL) == TIM_CHANNEL_1))))
30175
30176/****************** TIM Instances : supporting the break function *************/
30177#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
30178 (((INSTANCE) == TIM1) || \
30179 ((INSTANCE) == TIM8) || \
30180 ((INSTANCE) == TIM15) || \
30181 ((INSTANCE) == TIM16) || \
30182 ((INSTANCE) == TIM17))
30183
30184/************** TIM Instances : supporting Break source selection *************/
30185#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
30186 ((INSTANCE) == TIM8))
30187
30188/****************** TIM Instances : supporting complementary output(s) ********/
30189#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
30190 ((((INSTANCE) == TIM1) && \
30191 (((CHANNEL) == TIM_CHANNEL_1) || \
30192 ((CHANNEL) == TIM_CHANNEL_2) || \
30193 ((CHANNEL) == TIM_CHANNEL_3))) \
30194 || \
30195 (((INSTANCE) == TIM8) && \
30196 (((CHANNEL) == TIM_CHANNEL_1) || \
30197 ((CHANNEL) == TIM_CHANNEL_2) || \
30198 ((CHANNEL) == TIM_CHANNEL_3))) \
30199 || \
30200 (((INSTANCE) == TIM15) && \
30201 ((CHANNEL) == TIM_CHANNEL_1)) \
30202 || \
30203 (((INSTANCE) == TIM16) && \
30204 ((CHANNEL) == TIM_CHANNEL_1)) \
30205 || \
30206 (((INSTANCE) == TIM17) && \
30207 ((CHANNEL) == TIM_CHANNEL_1)))
30208
30209/****************** TIM Instances : supporting counting mode selection ********/
30210#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
30211 (((INSTANCE) == TIM1) || \
30212 ((INSTANCE) == TIM2) || \
30213 ((INSTANCE) == TIM3) || \
30214 ((INSTANCE) == TIM4) || \
30215 ((INSTANCE) == TIM5) || \
30216 ((INSTANCE) == TIM8))
30217
30218/****************** TIM Instances : supporting repetition counter *************/
30219#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
30220 (((INSTANCE) == TIM1) || \
30221 ((INSTANCE) == TIM8) || \
30222 ((INSTANCE) == TIM15) || \
30223 ((INSTANCE) == TIM16) || \
30224 ((INSTANCE) == TIM17))
30225
30226/****************** TIM Instances : supporting synchronization ****************/
30227#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
30228 (((__INSTANCE__) == TIM1) || \
30229 ((__INSTANCE__) == TIM2) || \
30230 ((__INSTANCE__) == TIM3) || \
30231 ((__INSTANCE__) == TIM4) || \
30232 ((__INSTANCE__) == TIM5) || \
30233 ((__INSTANCE__) == TIM6) || \
30234 ((__INSTANCE__) == TIM8) || \
30235 ((__INSTANCE__) == TIM12) || \
30236 ((__INSTANCE__) == TIM15))
30237
30238/****************** TIM Instances : supporting clock division *****************/
30239#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
30240 (((INSTANCE) == TIM1) || \
30241 ((INSTANCE) == TIM2) || \
30242 ((INSTANCE) == TIM3) || \
30243 ((INSTANCE) == TIM4) || \
30244 ((INSTANCE) == TIM5) || \
30245 ((INSTANCE) == TIM8) || \
30246 ((INSTANCE) == TIM15) || \
30247 ((INSTANCE) == TIM16) || \
30248 ((INSTANCE) == TIM17))
30249
30250/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
30251#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
30252 (((INSTANCE) == TIM1) || \
30253 ((INSTANCE) == TIM2) || \
30254 ((INSTANCE) == TIM3) || \
30255 ((INSTANCE) == TIM4) || \
30256 ((INSTANCE) == TIM5) || \
30257 ((INSTANCE) == TIM8))
30258
30259/****************** TIM Instances : supporting external clock mode 2 **********/
30260#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
30261 (((INSTANCE) == TIM1) || \
30262 ((INSTANCE) == TIM2) || \
30263 ((INSTANCE) == TIM3) || \
30264 ((INSTANCE) == TIM4) || \
30265 ((INSTANCE) == TIM5) || \
30266 ((INSTANCE) == TIM8))
30267
30268/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
30269#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
30270 (((INSTANCE) == TIM1) || \
30271 ((INSTANCE) == TIM2) || \
30272 ((INSTANCE) == TIM3) || \
30273 ((INSTANCE) == TIM4) || \
30274 ((INSTANCE) == TIM5) || \
30275 ((INSTANCE) == TIM8) || \
30276 ((INSTANCE) == TIM12) || \
30277 ((INSTANCE) == TIM15))
30278
30279/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
30280#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
30281 (((INSTANCE) == TIM1) || \
30282 ((INSTANCE) == TIM2) || \
30283 ((INSTANCE) == TIM3) || \
30284 ((INSTANCE) == TIM4) || \
30285 ((INSTANCE) == TIM5) || \
30286 ((INSTANCE) == TIM8) || \
30287 ((INSTANCE) == TIM12) || \
30288 ((INSTANCE) == TIM15))
30289
30290/****************** TIM Instances : supporting OCxREF clear *******************/
30291#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
30292 (((INSTANCE) == TIM1) || \
30293 ((INSTANCE) == TIM2) || \
30294 ((INSTANCE) == TIM3))
30295
30296/****************** TIM Instances : TIM_32B_COUNTER ***************************/
30297#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
30298 (((INSTANCE) == TIM2) || \
30299 ((INSTANCE) == TIM5))
30300
30301/****************** TIM Instances : TIM_BKIN2 ***************************/
30302#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
30303 (((INSTANCE) == TIM1) || \
30304 ((INSTANCE) == TIM8))
30305
30306/****************** TIM Instances : supporting Hall sensor interface **********/
30307#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
30308 ((__INSTANCE__) == TIM2) || \
30309 ((__INSTANCE__) == TIM3) || \
30310 ((__INSTANCE__) == TIM4) || \
30311 ((__INSTANCE__) == TIM5) || \
30312 ((__INSTANCE__) == TIM15) || \
30313 ((__INSTANCE__) == TIM8))
30314
30315/****************************** HRTIM Instances *******************************/
30316#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
30317
30318/******************** USART Instances : Synchronous mode **********************/
30319#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30320 ((INSTANCE) == USART2) || \
30321 ((INSTANCE) == USART3) || \
30322 ((INSTANCE) == USART6))
30323
30324/******************** USART Instances : SPI slave mode ************************/
30325#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30326 ((INSTANCE) == USART2) || \
30327 ((INSTANCE) == USART3) || \
30328 ((INSTANCE) == USART6))
30329
30330/******************** UART Instances : Asynchronous mode **********************/
30331#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30332 ((INSTANCE) == USART2) || \
30333 ((INSTANCE) == USART3) || \
30334 ((INSTANCE) == UART4) || \
30335 ((INSTANCE) == UART5) || \
30336 ((INSTANCE) == USART6) || \
30337 ((INSTANCE) == UART7) || \
30338 ((INSTANCE) == UART8))
30339
30340/******************** UART Instances : FIFO mode.******************************/
30341#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30342 ((INSTANCE) == USART2) || \
30343 ((INSTANCE) == USART3) || \
30344 ((INSTANCE) == UART4) || \
30345 ((INSTANCE) == UART5) || \
30346 ((INSTANCE) == USART6) || \
30347 ((INSTANCE) == UART7) || \
30348 ((INSTANCE) == UART8))
30349
30350/****************** UART Instances : Auto Baud Rate detection *****************/
30351#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30352 ((INSTANCE) == USART2) || \
30353 ((INSTANCE) == USART3) || \
30354 ((INSTANCE) == UART4) || \
30355 ((INSTANCE) == UART5) || \
30356 ((INSTANCE) == USART6) || \
30357 ((INSTANCE) == UART7) || \
30358 ((INSTANCE) == UART8))
30359
30360/*********************** UART Instances : Driver Enable ***********************/
30361#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30362 ((INSTANCE) == USART2) || \
30363 ((INSTANCE) == USART3) || \
30364 ((INSTANCE) == UART4) || \
30365 ((INSTANCE) == UART5) || \
30366 ((INSTANCE) == USART6) || \
30367 ((INSTANCE) == UART7) || \
30368 ((INSTANCE) == UART8) || \
30369 ((INSTANCE) == LPUART1))
30370
30371/********************* UART Instances : Half-Duplex mode **********************/
30372#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30373 ((INSTANCE) == USART2) || \
30374 ((INSTANCE) == USART3) || \
30375 ((INSTANCE) == UART4) || \
30376 ((INSTANCE) == UART5) || \
30377 ((INSTANCE) == USART6) || \
30378 ((INSTANCE) == UART7) || \
30379 ((INSTANCE) == UART8) || \
30380 ((INSTANCE) == LPUART1))
30381
30382/******************* UART Instances : Hardware Flow control *******************/
30383#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30384 ((INSTANCE) == USART2) || \
30385 ((INSTANCE) == USART3) || \
30386 ((INSTANCE) == UART4) || \
30387 ((INSTANCE) == UART5) || \
30388 ((INSTANCE) == USART6) || \
30389 ((INSTANCE) == UART7) || \
30390 ((INSTANCE) == UART8) || \
30391 ((INSTANCE) == LPUART1))
30392
30393/************************* UART Instances : LIN mode **************************/
30394#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30395 ((INSTANCE) == USART2) || \
30396 ((INSTANCE) == USART3) || \
30397 ((INSTANCE) == UART4) || \
30398 ((INSTANCE) == UART5) || \
30399 ((INSTANCE) == USART6) || \
30400 ((INSTANCE) == UART7) || \
30401 ((INSTANCE) == UART8))
30402
30403/****************** UART Instances : Wake-up from Stop mode *******************/
30404#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30405 ((INSTANCE) == USART2) || \
30406 ((INSTANCE) == USART3) || \
30407 ((INSTANCE) == UART4) || \
30408 ((INSTANCE) == UART5) || \
30409 ((INSTANCE) == USART6) || \
30410 ((INSTANCE) == UART7) || \
30411 ((INSTANCE) == UART8) || \
30412 ((INSTANCE) == LPUART1))
30413
30414/************************* UART Instances : IRDA mode *************************/
30415#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30416 ((INSTANCE) == USART2) || \
30417 ((INSTANCE) == USART3) || \
30418 ((INSTANCE) == UART4) || \
30419 ((INSTANCE) == UART5) || \
30420 ((INSTANCE) == USART6) || \
30421 ((INSTANCE) == UART7) || \
30422 ((INSTANCE) == UART8))
30423
30424/********************* USART Instances : Smard card mode **********************/
30425#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30426 ((INSTANCE) == USART2) || \
30427 ((INSTANCE) == USART3) || \
30428 ((INSTANCE) == USART6))
30429
30430/****************************** LPUART Instance *******************************/
30431#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
30432
30433/****************************** IWDG Instances ********************************/
30434#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))
30435/****************************** USB Instances ********************************/
30436#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
30437
30438/****************************** WWDG Instances ********************************/
30439#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG1) || \
30440 ((INSTANCE) == WWDG2))
30441/****************************** MDIOS Instances ********************************/
30442#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
30443
30444/****************************** CEC Instances *********************************/
30445#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
30446
30447/****************************** SAI Instances ********************************/
30448#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
30449 ((INSTANCE) == SAI1_Block_B) || \
30450 ((INSTANCE) == SAI2_Block_A) || \
30451 ((INSTANCE) == SAI2_Block_B) || \
30452 ((INSTANCE) == SAI3_Block_A) || \
30453 ((INSTANCE) == SAI3_Block_B) || \
30454 ((INSTANCE) == SAI4_Block_A) || \
30455 ((INSTANCE) == SAI4_Block_B))
30456
30457/****************************** SPDIFRX Instances ********************************/
30458#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
30459
30460/****************************** OPAMP Instances *******************************/
30461#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
30462 ((INSTANCE) == OPAMP2))
30463
30464#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
30465
30466/*********************** USB OTG PCD Instances ********************************/
30467#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
30468 ((INSTANCE) == USB_OTG_HS))
30469
30470/*********************** USB OTG HCD Instances ********************************/
30471#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
30472 ((INSTANCE) == USB_OTG_HS))
30473
30474/******************************************************************************/
30475/* For a painless codes migration between the STM32H7xx device product */
30476/* lines, or with STM32F7xx devices the aliases defined below are put */
30477/* in place to overcome the differences in the interrupt handlers and IRQn */
30478/* definitions. No need to update developed interrupt code when moving */
30479/* across product lines within the same STM32H7 Family */
30480/******************************************************************************/
30481
30482/* Aliases for __IRQn */
30483#define HASH_RNG_IRQn RNG_IRQn
30484#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
30485#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
30486#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
30487#define PVD_IRQn PVD_AVD_IRQn
30488
30489
30490
30491/* Aliases for __IRQHandler */
30492#define HASH_RNG_IRQHandler RNG_IRQHandler
30493#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
30494#define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
30495#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
30496#define PVD_IRQHandler PVD_AVD_IRQHandler
30497
30498/* Aliases for COMP __IRQHandler */
30499#define COMP_IRQHandler COMP1_IRQHandler
30500
30513#ifdef __cplusplus
30514}
30515#endif /* __cplusplus */
30516
30517#endif /* STM32H747xx_H */
30518
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
__IO
#define __IO
Definition: core_cm4.h:239
__I
#define __I
Definition: core_cm4.h:236
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h747xx.h:49
CRS_IRQn
@ CRS_IRQn
Definition: stm32h747xx.h:201
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32h747xx.h:58
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition: stm32h747xx.h:122
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32h747xx.h:69
MDIOS_IRQn
@ MDIOS_IRQn
Definition: stm32h747xx.h:177
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition: stm32h747xx.h:74
HRTIM1_TIMB_IRQn
@ HRTIM1_TIMB_IRQn
Definition: stm32h747xx.h:162
BDMA_Channel7_IRQn
@ BDMA_Channel7_IRQn
Definition: stm32h747xx.h:193
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32h747xx.h:64
SPDIF_RX_IRQn
@ SPDIF_RX_IRQn
Definition: stm32h747xx.h:154
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition: stm32h747xx.h:133
HRTIM1_Master_IRQn
@ HRTIM1_Master_IRQn
Definition: stm32h747xx.h:160
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition: stm32h747xx.h:116
BDMA_Channel3_IRQn
@ BDMA_Channel3_IRQn
Definition: stm32h747xx.h:189
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition: stm32h747xx.h:127
LPTIM3_IRQn
@ LPTIM3_IRQn
Definition: stm32h747xx.h:196
LPTIM4_IRQn
@ LPTIM4_IRQn
Definition: stm32h747xx.h:197
TIM15_IRQn
@ TIM15_IRQn
Definition: stm32h747xx.h:173
BDMA_Channel1_IRQn
@ BDMA_Channel1_IRQn
Definition: stm32h747xx.h:187
OTG_FS_EP1_IN_IRQn
@ OTG_FS_EP1_IN_IRQn
Definition: stm32h747xx.h:156
UART7_IRQn
@ UART7_IRQn
Definition: stm32h747xx.h:139
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32h747xx.h:93
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32h747xx.h:94
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32h747xx.h:53
TIM17_IRQn
@ TIM17_IRQn
Definition: stm32h747xx.h:175
SAI1_IRQn
@ SAI1_IRQn
Definition: stm32h747xx.h:144
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32h747xx.h:91
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32h747xx.h:89
LTDC_ER_IRQn
@ LTDC_ER_IRQn
Definition: stm32h747xx.h:146
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition: stm32h747xx.h:128
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition: stm32h747xx.h:103
FDCAN1_IT0_IRQn
@ FDCAN1_IT0_IRQn
Definition: stm32h747xx.h:80
USART2_IRQn
@ USART2_IRQn
Definition: stm32h747xx.h:99
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition: stm32h747xx.h:119
HOLD_CORE_IRQn
@ HOLD_CORE_IRQn
Definition: stm32h747xx.h:204
HRTIM1_FLT_IRQn
@ HRTIM1_FLT_IRQn
Definition: stm32h747xx.h:166
BDMA_Channel4_IRQn
@ BDMA_Channel4_IRQn
Definition: stm32h747xx.h:190
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32h747xx.h:56
ADC_IRQn
@ ADC_IRQn
Definition: stm32h747xx.h:79
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32h747xx.h:111
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32h747xx.h:97
TIM1_BRK_IRQn
@ TIM1_BRK_IRQn
Definition: stm32h747xx.h:85
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32h747xx.h:115
UART8_IRQn
@ UART8_IRQn
Definition: stm32h747xx.h:140
FDCAN2_IT0_IRQn
@ FDCAN2_IT0_IRQn
Definition: stm32h747xx.h:81
RCC_IRQn
@ RCC_IRQn
Definition: stm32h747xx.h:66
ADC3_IRQn
@ ADC3_IRQn
Definition: stm32h747xx.h:184
LPTIM2_IRQn
@ LPTIM2_IRQn
Definition: stm32h747xx.h:195
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32h747xx.h:114
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition: stm32h747xx.h:132
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32h747xx.h:95
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition: stm32h747xx.h:149
DFSDM1_FLT0_IRQn
@ DFSDM1_FLT0_IRQn
Definition: stm32h747xx.h:167
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32h747xx.h:106
JPEG_IRQn
@ JPEG_IRQn
Definition: stm32h747xx.h:178
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32h747xx.h:55
DMAMUX2_OVR_IRQn
@ DMAMUX2_OVR_IRQn
Definition: stm32h747xx.h:185
I2C4_ER_IRQn
@ I2C4_ER_IRQn
Definition: stm32h747xx.h:153
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32h747xx.h:59
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32h747xx.h:131
SAI4_IRQn
@ SAI4_IRQn
Definition: stm32h747xx.h:203
DFSDM1_FLT3_IRQn
@ DFSDM1_FLT3_IRQn
Definition: stm32h747xx.h:170
TIM1_UP_IRQn
@ TIM1_UP_IRQn
Definition: stm32h747xx.h:86
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32h747xx.h:130
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32h747xx.h:54
DMAMUX1_OVR_IRQn
@ DMAMUX1_OVR_IRQn
Definition: stm32h747xx.h:159
CEC_IRQn
@ CEC_IRQn
Definition: stm32h747xx.h:151
LPTIM5_IRQn
@ LPTIM5_IRQn
Definition: stm32h747xx.h:198
SPI5_IRQn
@ SPI5_IRQn
Definition: stm32h747xx.h:142
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32h747xx.h:57
RNG_IRQn
@ RNG_IRQn
Definition: stm32h747xx.h:137
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32h747xx.h:65
SWPMI1_IRQn
@ SWPMI1_IRQn
Definition: stm32h747xx.h:172
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition: stm32h747xx.h:126
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32h747xx.h:61
HRTIM1_TIMA_IRQn
@ HRTIM1_TIMA_IRQn
Definition: stm32h747xx.h:161
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32h747xx.h:92
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32h747xx.h:90
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition: stm32h747xx.h:117
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition: stm32h747xx.h:134
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition: stm32h747xx.h:109
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition: stm32h747xx.h:72
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32h747xx.h:101
SPI4_IRQn
@ SPI4_IRQn
Definition: stm32h747xx.h:141
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32h747xx.h:84
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition: stm32h747xx.h:73
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition: stm32h747xx.h:150
SPI6_IRQn
@ SPI6_IRQn
Definition: stm32h747xx.h:143
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition: stm32h747xx.h:158
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition: stm32h747xx.h:157
FPU_IRQn
@ FPU_IRQn
Definition: stm32h747xx.h:138
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition: stm32h747xx.h:104
USART6_IRQn
@ USART6_IRQn
Definition: stm32h747xx.h:129
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32h747xx.h:96
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition: stm32h747xx.h:135
HSEM1_IRQn
@ HSEM1_IRQn
Definition: stm32h747xx.h:182
OTG_FS_EP1_OUT_IRQn
@ OTG_FS_EP1_OUT_IRQn
Definition: stm32h747xx.h:155
DFSDM1_FLT2_IRQn
@ DFSDM1_FLT2_IRQn
Definition: stm32h747xx.h:169
HardFault_IRQn
@ HardFault_IRQn
Definition: stm32h747xx.h:52
BDMA_Channel6_IRQn
@ BDMA_Channel6_IRQn
Definition: stm32h747xx.h:192
CM7_SEV_IRQn
@ CM7_SEV_IRQn
Definition: stm32h747xx.h:124
FMC_IRQn
@ FMC_IRQn
Definition: stm32h747xx.h:108
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32h747xx.h:67
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32h747xx.h:71
CM4_SEV_IRQn
@ CM4_SEV_IRQn
Definition: stm32h747xx.h:125
DSI_IRQn
@ DSI_IRQn
Definition: stm32h747xx.h:180
HRTIM1_TIMD_IRQn
@ HRTIM1_TIMD_IRQn
Definition: stm32h747xx.h:164
SAI2_IRQn
@ SAI2_IRQn
Definition: stm32h747xx.h:148
HRTIM1_TIMC_IRQn
@ HRTIM1_TIMC_IRQn
Definition: stm32h747xx.h:163
FDCAN_CAL_IRQn
@ FDCAN_CAL_IRQn
Definition: stm32h747xx.h:123
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition: stm32h747xx.h:118
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32h747xx.h:63
TIM1_TRG_COM_IRQn
@ TIM1_TRG_COM_IRQn
Definition: stm32h747xx.h:87
UART5_IRQn
@ UART5_IRQn
Definition: stm32h747xx.h:113
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition: stm32h747xx.h:77
DMA2D_IRQn
@ DMA2D_IRQn
Definition: stm32h747xx.h:147
DCMI_IRQn
@ DCMI_IRQn
Definition: stm32h747xx.h:136
WWDG_RST_IRQn
@ WWDG_RST_IRQn
Definition: stm32h747xx.h:200
WAKEUP_PIN_IRQn
@ WAKEUP_PIN_IRQn
Definition: stm32h747xx.h:205
HSEM2_IRQn
@ HSEM2_IRQn
Definition: stm32h747xx.h:183
I2C4_EV_IRQn
@ I2C4_EV_IRQn
Definition: stm32h747xx.h:152
ECC_IRQn
@ ECC_IRQn
Definition: stm32h747xx.h:202
BDMA_Channel5_IRQn
@ BDMA_Channel5_IRQn
Definition: stm32h747xx.h:191
ETH_IRQn
@ ETH_IRQn
Definition: stm32h747xx.h:121
MDIOS_WKUP_IRQn
@ MDIOS_WKUP_IRQn
Definition: stm32h747xx.h:176
USART1_IRQn
@ USART1_IRQn
Definition: stm32h747xx.h:98
PVD_AVD_IRQn
@ PVD_AVD_IRQn
Definition: stm32h747xx.h:62
COMP_IRQn
@ COMP_IRQn
Definition: stm32h747xx.h:194
MDMA_IRQn
@ MDMA_IRQn
Definition: stm32h747xx.h:179
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32h747xx.h:70
BDMA_Channel0_IRQn
@ BDMA_Channel0_IRQn
Definition: stm32h747xx.h:186
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32h747xx.h:51
UART4_IRQn
@ UART4_IRQn
Definition: stm32h747xx.h:112
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition: stm32h747xx.h:105
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32h747xx.h:68
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition: stm32h747xx.h:120
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32h747xx.h:110
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition: stm32h747xx.h:107
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition: stm32h747xx.h:76
HRTIM1_TIME_IRQn
@ HRTIM1_TIME_IRQn
Definition: stm32h747xx.h:165
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition: stm32h747xx.h:78
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32h747xx.h:88
LTDC_IRQn
@ LTDC_IRQn
Definition: stm32h747xx.h:145
SAI3_IRQn
@ SAI3_IRQn
Definition: stm32h747xx.h:171
FDCAN1_IT1_IRQn
@ FDCAN1_IT1_IRQn
Definition: stm32h747xx.h:82
LPUART1_IRQn
@ LPUART1_IRQn
Definition: stm32h747xx.h:199
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition: stm32h747xx.h:75
SDMMC2_IRQn
@ SDMMC2_IRQn
Definition: stm32h747xx.h:181
BDMA_Channel2_IRQn
@ BDMA_Channel2_IRQn
Definition: stm32h747xx.h:188
USART3_IRQn
@ USART3_IRQn
Definition: stm32h747xx.h:100
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32h747xx.h:102
DFSDM1_FLT1_IRQn
@ DFSDM1_FLT1_IRQn
Definition: stm32h747xx.h:168
FDCAN2_IT1_IRQn
@ FDCAN2_IT1_IRQn
Definition: stm32h747xx.h:83
TIM16_IRQn
@ TIM16_IRQn
Definition: stm32h747xx.h:174
MCR
#define MCR
Modem Control Register.
Definition: uart.h:91
AFR
#define AFR
Alternate Function register.
Definition: uart.h:99
ADC_Common_TypeDef
Definition: stm32h723xx.h:289
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32h723xx.h:242
ART_TypeDef
ART.
Definition: stm32h745xg.h:327
BDMA_Channel_TypeDef
Definition: stm32h723xx.h:619
BDMA_TypeDef
Definition: stm32h723xx.h:628
CEC_TypeDef
Consumer Electronics Control.
Definition: stm32h723xx.h:418
COMPOPT_TypeDef
Comparator.
Definition: stm32h723xx.h:1576
COMP_Common_TypeDef
Definition: stm32h723xx.h:1588
COMP_TypeDef
Definition: stm32h723xx.h:1583
CRC_TypeDef
CRC calculation unit.
Definition: stm32h723xx.h:442
CRS_TypeDef
Clock Recovery System.
Definition: stm32h723xx.h:456
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32h723xx.h:469
DBGMCU_TypeDef
Debug MCU.
Definition: stm32h723xx.h:531
DCMI_TypeDef
DCMI.
Definition: stm32h723xx.h:561
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32h723xx.h:518
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32h723xx.h:496
DLYB_TypeDef
Delay Block DLYB.
Definition: stm32h723xx.h:1443
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32h723xx.h:686
DMAMUX_ChannelStatus_TypeDef
Definition: stm32h723xx.h:639
DMAMUX_Channel_TypeDef
Definition: stm32h723xx.h:634
DMAMUX_RequestGenStatus_TypeDef
Definition: stm32h723xx.h:650
DMAMUX_RequestGen_TypeDef
Definition: stm32h723xx.h:645
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32h723xx.h:601
DMA_TypeDef
Definition: stm32h723xx.h:611
DSI_TypeDef
DSI Controller.
Definition: stm32h747xg.h:710
ETH_TypeDef
Ethernet MAC.
Definition: stm32h723xx.h:717
EXTI_Core_TypeDef
This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx,...
Definition: stm32h723xx.h:936
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32h723xx.h:891
FDCAN_ClockCalibrationUnit_TypeDef
FD Controller Area Network.
Definition: stm32h723xx.h:403
FDCAN_GlobalTypeDef
FD Controller Area Network.
Definition: stm32h723xx.h:315
FLASH_TypeDef
FLASH Registers.
Definition: stm32h723xx.h:956
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32h723xx.h:1015
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32h723xx.h:1006
FMC_Bank2_TypeDef
Flexible Memory Controller Bank2.
Definition: stm32h723xx.h:1024
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32h723xx.h:1038
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5 and 6.
Definition: stm32h723xx.h:1053
GPIO_TypeDef
General Purpose I/O.
Definition: stm32h723xx.h:1066
GPV_TypeDef
Global Programmer View.
Definition: stm32h723xx.h:1966
HRTIM_Common_TypeDef
Definition: stm32h742xx.h:1630
HRTIM_Master_TypeDef
High resolution Timer (HRTIM)
Definition: stm32h742xx.h:1579
HRTIM_Timerx_TypeDef
Definition: stm32h742xx.h:1597
HRTIM_TypeDef
Definition: stm32h742xx.h:1663
HSEM_Common_TypeDef
Definition: stm32h723xx.h:1467
HSEM_TypeDef
HW Semaphore HSEM.
Definition: stm32h723xx.h:1453
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32h723xx.h:1133
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32h723xx.h:1152
JPEG_TypeDef
JPEG Codec.
Definition: stm32h743xx.h:1126
LPTIM_TypeDef
LPTIMIMER.
Definition: stm32h723xx.h:1559
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32h723xx.h:1191
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32h723xx.h:1166
MDIOS_TypeDef
MDIOS.
Definition: stm32h723xx.h:1681
MDMA_Channel_TypeDef
Definition: stm32h723xx.h:664
MDMA_TypeDef
MDMA Controller.
Definition: stm32h723xx.h:659
OPAMP_TypeDef
Operational Amplifier (OPAMP)
Definition: stm32h723xx.h:1083
PWR_TypeDef
Power Control.
Definition: stm32h723xx.h:1214
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32h742xx.h:1415
RAMECC_MonitorTypeDef
RAM_ECC_Specific_Registers.
Definition: stm32h723xx.h:1644
RAMECC_TypeDef
Definition: stm32h723xx.h:1654
RCC_Core_TypeDef
Definition: stm32h745xg.h:1347
RCC_TypeDef
Reset and Clock Control.
Definition: stm32h723xx.h:1233
RNG_TypeDef
RNG.
Definition: stm32h723xx.h:1668
RTC_TypeDef
Real-Time Clock.
Definition: stm32h723xx.h:1307
SAI_Block_TypeDef
Definition: stm32h723xx.h:1375
SAI_TypeDef
Serial Audio Interface.
Definition: stm32h723xx.h:1367
SDMMC_TypeDef
Secure digital input/output Interface.
Definition: stm32h723xx.h:1408
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition: stm32h723xx.h:1391
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32h723xx.h:1479
SWPMI_TypeDef
Single Wire Protocol Master Interface SPWMI.
Definition: stm32h723xx.h:1615
SYSCFG_TypeDef
System configuration controller.
Definition: stm32h723xx.h:1094
TIM_TypeDef
TIM.
Definition: stm32h723xx.h:1525
TTCAN_TypeDef
TTFD Controller Area Network.
Definition: stm32h723xx.h:376
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32h723xx.h:1596
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32h723xx.h:1796
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32h723xx.h:1761
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32h723xx.h:1869
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32h723xx.h:1855
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32h723xx.h:1824
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32h723xx.h:1840
VREFBUF_TypeDef
VREFBUF.
Definition: stm32h723xx.h:304
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32h723xx.h:1633
_pr
Definition: hexdump.h:39
system_stm32h7xx.h
CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
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