RTEMS 6.1-rc2
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stm32h730xx.h
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1
33#ifndef STM32H730xx_H
34#define STM32H730xx_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
48typedef enum
49{
50/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
51 NonMaskableInt_IRQn = -14,
52 HardFault_IRQn = -13,
53 MemoryManagement_IRQn = -12,
54 BusFault_IRQn = -11,
55 UsageFault_IRQn = -10,
56 SVCall_IRQn = -5,
57 DebugMonitor_IRQn = -4,
58 PendSV_IRQn = -2,
59 SysTick_IRQn = -1,
60/****** STM32 specific Interrupt Numbers **********************************************************************/
61 WWDG_IRQn = 0,
62 PVD_AVD_IRQn = 1,
63 TAMP_STAMP_IRQn = 2,
64 RTC_WKUP_IRQn = 3,
65 FLASH_IRQn = 4,
66 RCC_IRQn = 5,
67 EXTI0_IRQn = 6,
68 EXTI1_IRQn = 7,
69 EXTI2_IRQn = 8,
70 EXTI3_IRQn = 9,
71 EXTI4_IRQn = 10,
72 DMA1_Stream0_IRQn = 11,
73 DMA1_Stream1_IRQn = 12,
74 DMA1_Stream2_IRQn = 13,
75 DMA1_Stream3_IRQn = 14,
76 DMA1_Stream4_IRQn = 15,
77 DMA1_Stream5_IRQn = 16,
78 DMA1_Stream6_IRQn = 17,
79 ADC_IRQn = 18,
80 FDCAN1_IT0_IRQn = 19,
81 FDCAN2_IT0_IRQn = 20,
82 FDCAN1_IT1_IRQn = 21,
83 FDCAN2_IT1_IRQn = 22,
84 EXTI9_5_IRQn = 23,
85 TIM1_BRK_IRQn = 24,
86 TIM1_UP_IRQn = 25,
87 TIM1_TRG_COM_IRQn = 26,
88 TIM1_CC_IRQn = 27,
89 TIM2_IRQn = 28,
90 TIM3_IRQn = 29,
91 TIM4_IRQn = 30,
92 I2C1_EV_IRQn = 31,
93 I2C1_ER_IRQn = 32,
94 I2C2_EV_IRQn = 33,
95 I2C2_ER_IRQn = 34,
96 SPI1_IRQn = 35,
97 SPI2_IRQn = 36,
98 USART1_IRQn = 37,
99 USART2_IRQn = 38,
100 USART3_IRQn = 39,
101 EXTI15_10_IRQn = 40,
102 RTC_Alarm_IRQn = 41,
103 TIM8_BRK_TIM12_IRQn = 43,
104 TIM8_UP_TIM13_IRQn = 44,
105 TIM8_TRG_COM_TIM14_IRQn = 45,
106 TIM8_CC_IRQn = 46,
107 DMA1_Stream7_IRQn = 47,
108 FMC_IRQn = 48,
109 SDMMC1_IRQn = 49,
110 TIM5_IRQn = 50,
111 SPI3_IRQn = 51,
112 UART4_IRQn = 52,
113 UART5_IRQn = 53,
114 TIM6_DAC_IRQn = 54,
115 TIM7_IRQn = 55,
116 DMA2_Stream0_IRQn = 56,
117 DMA2_Stream1_IRQn = 57,
118 DMA2_Stream2_IRQn = 58,
119 DMA2_Stream3_IRQn = 59,
120 DMA2_Stream4_IRQn = 60,
121 ETH_IRQn = 61,
122 ETH_WKUP_IRQn = 62,
123 FDCAN_CAL_IRQn = 63,
124 DMA2_Stream5_IRQn = 68,
125 DMA2_Stream6_IRQn = 69,
126 DMA2_Stream7_IRQn = 70,
127 USART6_IRQn = 71,
128 I2C3_EV_IRQn = 72,
129 I2C3_ER_IRQn = 73,
130 OTG_HS_EP1_OUT_IRQn = 74,
131 OTG_HS_EP1_IN_IRQn = 75,
132 OTG_HS_WKUP_IRQn = 76,
133 OTG_HS_IRQn = 77,
134 DCMI_PSSI_IRQn = 78,
135 CRYP_IRQn = 79,
136 HASH_RNG_IRQn = 80,
137 FPU_IRQn = 81,
138 UART7_IRQn = 82,
139 UART8_IRQn = 83,
140 SPI4_IRQn = 84,
141 SPI5_IRQn = 85,
142 SPI6_IRQn = 86,
143 SAI1_IRQn = 87,
144 LTDC_IRQn = 88,
145 LTDC_ER_IRQn = 89,
146 DMA2D_IRQn = 90,
147 OCTOSPI1_IRQn = 92,
148 LPTIM1_IRQn = 93,
149 CEC_IRQn = 94,
150 I2C4_EV_IRQn = 95,
151 I2C4_ER_IRQn = 96,
152 SPDIF_RX_IRQn = 97,
153 DMAMUX1_OVR_IRQn = 102,
154 DFSDM1_FLT0_IRQn = 110,
155 DFSDM1_FLT1_IRQn = 111,
156 DFSDM1_FLT2_IRQn = 112,
157 DFSDM1_FLT3_IRQn = 113,
158 SWPMI1_IRQn = 115,
159 TIM15_IRQn = 116,
160 TIM16_IRQn = 117,
161 TIM17_IRQn = 118,
162 MDIOS_WKUP_IRQn = 119,
163 MDIOS_IRQn = 120,
164 MDMA_IRQn = 122,
165 SDMMC2_IRQn = 124,
166 HSEM1_IRQn = 125,
167 ADC3_IRQn = 127,
168 DMAMUX2_OVR_IRQn = 128,
169 BDMA_Channel0_IRQn = 129,
170 BDMA_Channel1_IRQn = 130,
171 BDMA_Channel2_IRQn = 131,
172 BDMA_Channel3_IRQn = 132,
173 BDMA_Channel4_IRQn = 133,
174 BDMA_Channel5_IRQn = 134,
175 BDMA_Channel6_IRQn = 135,
176 BDMA_Channel7_IRQn = 136,
177 COMP_IRQn = 137 ,
178 LPTIM2_IRQn = 138,
179 LPTIM3_IRQn = 139,
180 LPTIM4_IRQn = 140,
181 LPTIM5_IRQn = 141,
182 LPUART1_IRQn = 142,
183 CRS_IRQn = 144,
184 ECC_IRQn = 145,
185 SAI4_IRQn = 146,
186 DTS_IRQn = 147,
187 WAKEUP_PIN_IRQn = 149,
188 OCTOSPI2_IRQn = 150,
189 OTFDEC1_IRQn = 151,
190 OTFDEC2_IRQn = 152,
191 FMAC_IRQn = 153,
192 CORDIC_IRQn = 154,
193 UART9_IRQn = 155,
194 USART10_IRQn = 156,
195 I2C5_EV_IRQn = 157,
196 I2C5_ER_IRQn = 158,
197 FDCAN3_IT0_IRQn = 159,
198 FDCAN3_IT1_IRQn = 160,
199 TIM23_IRQn = 161,
200 TIM24_IRQn = 162,
201} IRQn_Type;
202
217#define __CM7_REV 0x0100U
218#define __MPU_PRESENT 1U
219#define __NVIC_PRIO_BITS 4U
220#define __Vendor_SysTickConfig 0U
221#define __FPU_PRESENT 1U
222#define __ICACHE_PRESENT 1U
223#define __DCACHE_PRESENT 1U
224#include "core_cm7.h"
233#include "system_stm32h7xx.h"
234#include <stdint.h>
235
244typedef struct
245{
246 __IO uint32_t ISR;
247 __IO uint32_t IER;
248 __IO uint32_t CR;
249 __IO uint32_t CFGR;
250 __IO uint32_t CFGR2;
251 __IO uint32_t SMPR1;
252 __IO uint32_t SMPR2;
253 __IO uint32_t PCSEL_RES0;
254 __IO uint32_t LTR1_TR1;
255 __IO uint32_t HTR1_TR2;
256 __IO uint32_t RES1_TR3;
257 uint32_t RESERVED2;
258 __IO uint32_t SQR1;
259 __IO uint32_t SQR2;
260 __IO uint32_t SQR3;
261 __IO uint32_t SQR4;
262 __IO uint32_t DR;
263 uint32_t RESERVED3;
264 uint32_t RESERVED4;
265 __IO uint32_t JSQR;
266 uint32_t RESERVED5[4];
267 __IO uint32_t OFR1;
268 __IO uint32_t OFR2;
269 __IO uint32_t OFR3;
270 __IO uint32_t OFR4;
271 uint32_t RESERVED6[4];
272 __IO uint32_t JDR1;
273 __IO uint32_t JDR2;
274 __IO uint32_t JDR3;
275 __IO uint32_t JDR4;
276 uint32_t RESERVED7[4];
277 __IO uint32_t AWD2CR;
278 __IO uint32_t AWD3CR;
279 uint32_t RESERVED8;
280 uint32_t RESERVED9;
281 __IO uint32_t LTR2_DIFSEL;
282 __IO uint32_t HTR2_CALFACT;
283 __IO uint32_t LTR3_RES10;
284 __IO uint32_t HTR3_RES11;
285 __IO uint32_t DIFSEL_RES12;
286 __IO uint32_t CALFACT_RES13;
287 __IO uint32_t CALFACT2_RES14;
288} ADC_TypeDef;
289
290
291typedef struct
292{
293__IO uint32_t CSR;
294uint32_t RESERVED;
295__IO uint32_t CCR;
296__IO uint32_t CDR;
297__IO uint32_t CDR2;
299} ADC_Common_TypeDef;
300
301
306typedef struct
307{
308 __IO uint32_t CSR;
309 __IO uint32_t CCR;
310} VREFBUF_TypeDef;
311
312
317typedef struct
318{
319 __IO uint32_t CREL;
320 __IO uint32_t ENDN;
321 __IO uint32_t RESERVED1;
322 __IO uint32_t DBTP;
323 __IO uint32_t TEST;
324 __IO uint32_t RWD;
325 __IO uint32_t CCCR;
326 __IO uint32_t NBTP;
327 __IO uint32_t TSCC;
328 __IO uint32_t TSCV;
329 __IO uint32_t TOCC;
330 __IO uint32_t TOCV;
331 __IO uint32_t RESERVED2[4];
332 __IO uint32_t ECR;
333 __IO uint32_t PSR;
334 __IO uint32_t TDCR;
335 __IO uint32_t RESERVED3;
336 __IO uint32_t IR;
337 __IO uint32_t IE;
338 __IO uint32_t ILS;
339 __IO uint32_t ILE;
340 __IO uint32_t RESERVED4[8];
341 __IO uint32_t GFC;
342 __IO uint32_t SIDFC;
343 __IO uint32_t XIDFC;
344 __IO uint32_t RESERVED5;
345 __IO uint32_t XIDAM;
346 __IO uint32_t HPMS;
347 __IO uint32_t NDAT1;
348 __IO uint32_t NDAT2;
349 __IO uint32_t RXF0C;
350 __IO uint32_t RXF0S;
351 __IO uint32_t RXF0A;
352 __IO uint32_t RXBC;
353 __IO uint32_t RXF1C;
354 __IO uint32_t RXF1S;
355 __IO uint32_t RXF1A;
356 __IO uint32_t RXESC;
357 __IO uint32_t TXBC;
358 __IO uint32_t TXFQS;
359 __IO uint32_t TXESC;
360 __IO uint32_t TXBRP;
361 __IO uint32_t TXBAR;
362 __IO uint32_t TXBCR;
363 __IO uint32_t TXBTO;
364 __IO uint32_t TXBCF;
365 __IO uint32_t TXBTIE;
366 __IO uint32_t TXBCIE;
367 __IO uint32_t RESERVED6[2];
368 __IO uint32_t TXEFC;
369 __IO uint32_t TXEFS;
370 __IO uint32_t TXEFA;
371 __IO uint32_t RESERVED7;
372} FDCAN_GlobalTypeDef;
373
378typedef struct
379{
380 __IO uint32_t TTTMC;
381 __IO uint32_t TTRMC;
382 __IO uint32_t TTOCF;
383 __IO uint32_t TTMLM;
384 __IO uint32_t TURCF;
385 __IO uint32_t TTOCN;
386 __IO uint32_t TTGTP;
387 __IO uint32_t TTTMK;
388 __IO uint32_t TTIR;
389 __IO uint32_t TTIE;
390 __IO uint32_t TTILS;
391 __IO uint32_t TTOST;
392 __IO uint32_t TURNA;
393 __IO uint32_t TTLGT;
394 __IO uint32_t TTCTC;
395 __IO uint32_t TTCPT;
396 __IO uint32_t TTCSM;
397 __IO uint32_t RESERVED1[111];
398 __IO uint32_t TTTS;
399} TTCAN_TypeDef;
400
405typedef struct
406{
407 __IO uint32_t CREL;
408 __IO uint32_t CCFG;
409 __IO uint32_t CSTAT;
410 __IO uint32_t CWD;
411 __IO uint32_t IR;
412 __IO uint32_t IE;
413} FDCAN_ClockCalibrationUnit_TypeDef;
414
415
420typedef struct
421{
422 __IO uint32_t CR;
423 __IO uint32_t CFGR;
424 __IO uint32_t TXDR;
425 __IO uint32_t RXDR;
426 __IO uint32_t ISR;
427 __IO uint32_t IER;
428}CEC_TypeDef;
429
433typedef struct
434{
435 __IO uint32_t CSR;
436 __IO uint32_t WDATA;
437 __IO uint32_t RDATA;
438} CORDIC_TypeDef;
439
444typedef struct
445{
446 __IO uint32_t DR;
447 __IO uint32_t IDR;
448 __IO uint32_t CR;
449 uint32_t RESERVED2;
450 __IO uint32_t INIT;
451 __IO uint32_t POL;
452} CRC_TypeDef;
453
454
458typedef struct
459{
460__IO uint32_t CR;
461__IO uint32_t CFGR;
462__IO uint32_t ISR;
463__IO uint32_t ICR;
464} CRS_TypeDef;
465
466
471typedef struct
472{
473 __IO uint32_t CR;
474 __IO uint32_t SWTRIGR;
475 __IO uint32_t DHR12R1;
476 __IO uint32_t DHR12L1;
477 __IO uint32_t DHR8R1;
478 __IO uint32_t DHR12R2;
479 __IO uint32_t DHR12L2;
480 __IO uint32_t DHR8R2;
481 __IO uint32_t DHR12RD;
482 __IO uint32_t DHR12LD;
483 __IO uint32_t DHR8RD;
484 __IO uint32_t DOR1;
485 __IO uint32_t DOR2;
486 __IO uint32_t SR;
487 __IO uint32_t CCR;
488 __IO uint32_t MCR;
489 __IO uint32_t SHSR1;
490 __IO uint32_t SHSR2;
491 __IO uint32_t SHHR;
492 __IO uint32_t SHRR;
493} DAC_TypeDef;
494
498typedef struct
499{
500 __IO uint32_t FLTCR1;
501 __IO uint32_t FLTCR2;
502 __IO uint32_t FLTISR;
503 __IO uint32_t FLTICR;
504 __IO uint32_t FLTJCHGR;
505 __IO uint32_t FLTFCR;
506 __IO uint32_t FLTJDATAR;
507 __IO uint32_t FLTRDATAR;
508 __IO uint32_t FLTAWHTR;
509 __IO uint32_t FLTAWLTR;
510 __IO uint32_t FLTAWSR;
511 __IO uint32_t FLTAWCFR;
512 __IO uint32_t FLTEXMAX;
513 __IO uint32_t FLTEXMIN;
514 __IO uint32_t FLTCNVTIMR;
515} DFSDM_Filter_TypeDef;
516
520typedef struct
521{
522 __IO uint32_t CHCFGR1;
523 __IO uint32_t CHCFGR2;
524 __IO uint32_t CHAWSCDR;
526 __IO uint32_t CHWDATAR;
527 __IO uint32_t CHDATINR;
528} DFSDM_Channel_TypeDef;
529
533typedef struct
534{
535 __IO uint32_t IDCODE;
536 __IO uint32_t CR;
537 uint32_t RESERVED4[11];
538 __IO uint32_t APB3FZ1;
539 uint32_t RESERVED5;
540 __IO uint32_t APB1LFZ1;
541 uint32_t RESERVED6;
542 __IO uint32_t APB1HFZ1;
543 uint32_t RESERVED7;
544 __IO uint32_t APB2FZ1;
545 uint32_t RESERVED8;
546 __IO uint32_t APB4FZ1;
547 __IO uint32_t RESERVED9[990];
548 __IO uint32_t PIDR4;
549 __IO uint32_t RESERVED10[3];
550 __IO uint32_t PIDR0;
551 __IO uint32_t PIDR1;
552 __IO uint32_t PIDR2;
553 __IO uint32_t PIDR3;
554 __IO uint32_t CIDR0;
555 __IO uint32_t CIDR1;
556 __IO uint32_t CIDR2;
557 __IO uint32_t CIDR3;
558}DBGMCU_TypeDef;
563typedef struct
564{
565 __IO uint32_t CR;
566 __IO uint32_t SR;
567 __IO uint32_t RISR;
568 __IO uint32_t IER;
569 __IO uint32_t MISR;
570 __IO uint32_t ICR;
571 __IO uint32_t ESCR;
572 __IO uint32_t ESUR;
573 __IO uint32_t CWSTRTR;
574 __IO uint32_t CWSIZER;
575 __IO uint32_t DR;
576} DCMI_TypeDef;
577
582typedef struct
583{
584 __IO uint32_t CR;
585 __IO uint32_t SR;
586 __IO uint32_t RIS;
587 __IO uint32_t IER;
588 __IO uint32_t MIS;
589 __IO uint32_t ICR;
590 __IO uint32_t RESERVED1[4];
591 __IO uint32_t DR;
592 __IO uint32_t RESERVED2[241];
593 __IO uint32_t HWCFGR;
594 __IO uint32_t VERR;
595 __IO uint32_t IPIDR;
596 __IO uint32_t SIDR;
597} PSSI_TypeDef;
598
603typedef struct
604{
605 __IO uint32_t CR;
606 __IO uint32_t NDTR;
607 __IO uint32_t PAR;
608 __IO uint32_t M0AR;
609 __IO uint32_t M1AR;
610 __IO uint32_t FCR;
611} DMA_Stream_TypeDef;
612
613typedef struct
614{
615 __IO uint32_t LISR;
616 __IO uint32_t HISR;
617 __IO uint32_t LIFCR;
618 __IO uint32_t HIFCR;
619} DMA_TypeDef;
620
621typedef struct
622{
623 __IO uint32_t CCR;
624 __IO uint32_t CNDTR;
625 __IO uint32_t CPAR;
626 __IO uint32_t CM0AR;
627 __IO uint32_t CM1AR;
628} BDMA_Channel_TypeDef;
629
630typedef struct
631{
632 __IO uint32_t ISR;
633 __IO uint32_t IFCR;
634} BDMA_TypeDef;
635
636typedef struct
637{
638 __IO uint32_t CCR;
639}DMAMUX_Channel_TypeDef;
640
641typedef struct
642{
643 __IO uint32_t CSR;
644 __IO uint32_t CFR;
645}DMAMUX_ChannelStatus_TypeDef;
646
647typedef struct
648{
649 __IO uint32_t RGCR;
650}DMAMUX_RequestGen_TypeDef;
651
652typedef struct
653{
654 __IO uint32_t RGSR;
655 __IO uint32_t RGCFR;
656}DMAMUX_RequestGenStatus_TypeDef;
657
661typedef struct
662{
663 __IO uint32_t GISR0;
664}MDMA_TypeDef;
665
666typedef struct
667{
668 __IO uint32_t CISR;
669 __IO uint32_t CIFCR;
670 __IO uint32_t CESR;
671 __IO uint32_t CCR;
672 __IO uint32_t CTCR;
673 __IO uint32_t CBNDTR;
674 __IO uint32_t CSAR;
675 __IO uint32_t CDAR;
676 __IO uint32_t CBRUR;
677 __IO uint32_t CLAR;
678 __IO uint32_t CTBR;
679 uint32_t RESERVED0;
680 __IO uint32_t CMAR;
681 __IO uint32_t CMDR;
682}MDMA_Channel_TypeDef;
683
688typedef struct
689{
690 __IO uint32_t CR;
691 __IO uint32_t ISR;
692 __IO uint32_t IFCR;
693 __IO uint32_t FGMAR;
694 __IO uint32_t FGOR;
695 __IO uint32_t BGMAR;
696 __IO uint32_t BGOR;
697 __IO uint32_t FGPFCCR;
698 __IO uint32_t FGCOLR;
699 __IO uint32_t BGPFCCR;
700 __IO uint32_t BGCOLR;
701 __IO uint32_t FGCMAR;
702 __IO uint32_t BGCMAR;
703 __IO uint32_t OPFCCR;
704 __IO uint32_t OCOLR;
705 __IO uint32_t OMAR;
706 __IO uint32_t OOR;
707 __IO uint32_t NLR;
708 __IO uint32_t LWR;
709 __IO uint32_t AMTCR;
710 uint32_t RESERVED[236];
711 __IO uint32_t FGCLUT[256];
712 __IO uint32_t BGCLUT[256];
713} DMA2D_TypeDef;
714
715
719typedef struct
720{
721 __IO uint32_t MACCR;
722 __IO uint32_t MACECR;
723 __IO uint32_t MACPFR;
724 __IO uint32_t MACWTR;
725 __IO uint32_t MACHT0R;
726 __IO uint32_t MACHT1R;
727 uint32_t RESERVED1[14];
728 __IO uint32_t MACVTR;
729 uint32_t RESERVED2;
730 __IO uint32_t MACVHTR;
731 uint32_t RESERVED3;
732 __IO uint32_t MACVIR;
733 __IO uint32_t MACIVIR;
734 uint32_t RESERVED4[2];
735 __IO uint32_t MACTFCR;
736 uint32_t RESERVED5[7];
737 __IO uint32_t MACRFCR;
738 uint32_t RESERVED6[7];
739 __IO uint32_t MACISR;
740 __IO uint32_t MACIER;
741 __IO uint32_t MACRXTXSR;
742 uint32_t RESERVED7;
743 __IO uint32_t MACPCSR;
744 __IO uint32_t MACRWKPFR;
745 uint32_t RESERVED8[2];
746 __IO uint32_t MACLCSR;
747 __IO uint32_t MACLTCR;
748 __IO uint32_t MACLETR;
749 __IO uint32_t MAC1USTCR;
750 uint32_t RESERVED9[12];
751 __IO uint32_t MACVR;
752 __IO uint32_t MACDR;
753 uint32_t RESERVED10;
754 __IO uint32_t MACHWF0R;
755 __IO uint32_t MACHWF1R;
756 __IO uint32_t MACHWF2R;
757 uint32_t RESERVED11[54];
758 __IO uint32_t MACMDIOAR;
759 __IO uint32_t MACMDIODR;
760 uint32_t RESERVED12[2];
761 __IO uint32_t MACARPAR;
762 uint32_t RESERVED13[59];
763 __IO uint32_t MACA0HR;
764 __IO uint32_t MACA0LR;
765 __IO uint32_t MACA1HR;
766 __IO uint32_t MACA1LR;
767 __IO uint32_t MACA2HR;
768 __IO uint32_t MACA2LR;
769 __IO uint32_t MACA3HR;
770 __IO uint32_t MACA3LR;
771 uint32_t RESERVED14[248];
772 __IO uint32_t MMCCR;
773 __IO uint32_t MMCRIR;
774 __IO uint32_t MMCTIR;
775 __IO uint32_t MMCRIMR;
776 __IO uint32_t MMCTIMR;
777 uint32_t RESERVED15[14];
778 __IO uint32_t MMCTSCGPR;
779 __IO uint32_t MMCTMCGPR;
780 uint32_t RESERVED16[5];
781 __IO uint32_t MMCTPCGR;
782 uint32_t RESERVED17[10];
783 __IO uint32_t MMCRCRCEPR;
784 __IO uint32_t MMCRAEPR;
785 uint32_t RESERVED18[10];
786 __IO uint32_t MMCRUPGR;
787 uint32_t RESERVED19[9];
788 __IO uint32_t MMCTLPIMSTR;
789 __IO uint32_t MMCTLPITCR;
790 __IO uint32_t MMCRLPIMSTR;
791 __IO uint32_t MMCRLPITCR;
792 uint32_t RESERVED20[65];
793 __IO uint32_t MACL3L4C0R;
794 __IO uint32_t MACL4A0R;
795 uint32_t RESERVED21[2];
796 __IO uint32_t MACL3A0R0R;
797 __IO uint32_t MACL3A1R0R;
798 __IO uint32_t MACL3A2R0R;
799 __IO uint32_t MACL3A3R0R;
800 uint32_t RESERVED22[4];
801 __IO uint32_t MACL3L4C1R;
802 __IO uint32_t MACL4A1R;
803 uint32_t RESERVED23[2];
804 __IO uint32_t MACL3A0R1R;
805 __IO uint32_t MACL3A1R1R;
806 __IO uint32_t MACL3A2R1R;
807 __IO uint32_t MACL3A3R1R;
808 uint32_t RESERVED24[108];
809 __IO uint32_t MACTSCR;
810 __IO uint32_t MACSSIR;
811 __IO uint32_t MACSTSR;
812 __IO uint32_t MACSTNR;
813 __IO uint32_t MACSTSUR;
814 __IO uint32_t MACSTNUR;
815 __IO uint32_t MACTSAR;
816 uint32_t RESERVED25;
817 __IO uint32_t MACTSSR;
818 uint32_t RESERVED26[3];
819 __IO uint32_t MACTTSSNR;
820 __IO uint32_t MACTTSSSR;
821 uint32_t RESERVED27[2];
822 __IO uint32_t MACACR;
823 uint32_t RESERVED28;
824 __IO uint32_t MACATSNR;
825 __IO uint32_t MACATSSR;
826 __IO uint32_t MACTSIACR;
827 __IO uint32_t MACTSEACR;
828 __IO uint32_t MACTSICNR;
829 __IO uint32_t MACTSECNR;
830 uint32_t RESERVED29[4];
831 __IO uint32_t MACPPSCR;
832 uint32_t RESERVED30[3];
833 __IO uint32_t MACPPSTTSR;
834 __IO uint32_t MACPPSTTNR;
835 __IO uint32_t MACPPSIR;
836 __IO uint32_t MACPPSWR;
837 uint32_t RESERVED31[12];
838 __IO uint32_t MACPOCR;
839 __IO uint32_t MACSPI0R;
840 __IO uint32_t MACSPI1R;
841 __IO uint32_t MACSPI2R;
842 __IO uint32_t MACLMIR;
843 uint32_t RESERVED32[11];
844 __IO uint32_t MTLOMR;
845 uint32_t RESERVED33[7];
846 __IO uint32_t MTLISR;
847 uint32_t RESERVED34[55];
848 __IO uint32_t MTLTQOMR;
849 __IO uint32_t MTLTQUR;
850 __IO uint32_t MTLTQDR;
851 uint32_t RESERVED35[8];
852 __IO uint32_t MTLQICSR;
853 __IO uint32_t MTLRQOMR;
854 __IO uint32_t MTLRQMPOCR;
855 __IO uint32_t MTLRQDR;
856 uint32_t RESERVED36[177];
857 __IO uint32_t DMAMR;
858 __IO uint32_t DMASBMR;
859 __IO uint32_t DMAISR;
860 __IO uint32_t DMADSR;
861 uint32_t RESERVED37[60];
862 __IO uint32_t DMACCR;
863 __IO uint32_t DMACTCR;
864 __IO uint32_t DMACRCR;
865 uint32_t RESERVED38[2];
866 __IO uint32_t DMACTDLAR;
867 uint32_t RESERVED39;
868 __IO uint32_t DMACRDLAR;
869 __IO uint32_t DMACTDTPR;
870 uint32_t RESERVED40;
871 __IO uint32_t DMACRDTPR;
872 __IO uint32_t DMACTDRLR;
873 __IO uint32_t DMACRDRLR;
874 __IO uint32_t DMACIER;
875 __IO uint32_t DMACRIWTR;
876__IO uint32_t DMACSFCSR;
877 uint32_t RESERVED41;
878 __IO uint32_t DMACCATDR;
879 uint32_t RESERVED42;
880 __IO uint32_t DMACCARDR;
881 uint32_t RESERVED43;
882 __IO uint32_t DMACCATBR;
883 uint32_t RESERVED44;
884 __IO uint32_t DMACCARBR;
885 __IO uint32_t DMACSR;
886uint32_t RESERVED45[2];
887__IO uint32_t DMACMFCR;
888}ETH_TypeDef;
893typedef struct
894{
895__IO uint32_t RTSR1;
896__IO uint32_t FTSR1;
897__IO uint32_t SWIER1;
898__IO uint32_t D3PMR1;
899__IO uint32_t D3PCR1L;
900__IO uint32_t D3PCR1H;
901uint32_t RESERVED1[2];
902__IO uint32_t RTSR2;
903__IO uint32_t FTSR2;
904__IO uint32_t SWIER2;
905__IO uint32_t D3PMR2;
906__IO uint32_t D3PCR2L;
907__IO uint32_t D3PCR2H;
908uint32_t RESERVED2[2];
909__IO uint32_t RTSR3;
910__IO uint32_t FTSR3;
911__IO uint32_t SWIER3;
912__IO uint32_t D3PMR3;
913__IO uint32_t D3PCR3L;
914__IO uint32_t D3PCR3H;
915uint32_t RESERVED3[10];
916__IO uint32_t IMR1;
917__IO uint32_t EMR1;
918__IO uint32_t PR1;
919uint32_t RESERVED4;
920__IO uint32_t IMR2;
921__IO uint32_t EMR2;
922__IO uint32_t PR2;
923uint32_t RESERVED5;
924__IO uint32_t IMR3;
925__IO uint32_t EMR3;
926__IO uint32_t PR3;
927}EXTI_TypeDef;
928
938typedef struct
939{
940__IO uint32_t IMR1;
941__IO uint32_t EMR1;
942__IO uint32_t PR1;
943uint32_t RESERVED1;
944__IO uint32_t IMR2;
945__IO uint32_t EMR2;
946__IO uint32_t PR2;
947uint32_t RESERVED2;
948__IO uint32_t IMR3;
949__IO uint32_t EMR3;
950__IO uint32_t PR3;
951}EXTI_Core_TypeDef;
952
953
958typedef struct
959{
960 __IO uint32_t ACR;
961 __IO uint32_t KEYR1;
962 __IO uint32_t OPTKEYR;
963 __IO uint32_t CR1;
964 __IO uint32_t SR1;
965 __IO uint32_t CCR1;
966 __IO uint32_t OPTCR;
967 __IO uint32_t OPTSR_CUR;
968 __IO uint32_t OPTSR_PRG;
969 __IO uint32_t OPTCCR;
970 __IO uint32_t PRAR_CUR1;
971 __IO uint32_t PRAR_PRG1;
972 __IO uint32_t SCAR_CUR1;
973 __IO uint32_t SCAR_PRG1;
974 __IO uint32_t WPSN_CUR1;
975 __IO uint32_t WPSN_PRG1;
976 __IO uint32_t BOOT_CUR;
977 __IO uint32_t BOOT_PRG;
978 uint32_t RESERVED0[2];
979 __IO uint32_t CRCCR1;
980 __IO uint32_t CRCSADD1;
981 __IO uint32_t CRCEADD1;
982 __IO uint32_t CRCDATA;
983 __IO uint32_t ECC_FA1;
984 uint32_t RESERVED[3];
985 __IO uint32_t OPTSR2_CUR;
986 __IO uint32_t OPTSR2_PRG;
987} FLASH_TypeDef;
988
992typedef struct
993{
994 __IO uint32_t X1BUFCFG;
995 __IO uint32_t X2BUFCFG;
996 __IO uint32_t YBUFCFG;
997 __IO uint32_t PARAM;
998 __IO uint32_t CR;
999 __IO uint32_t SR;
1000 __IO uint32_t WDATA;
1001 __IO uint32_t RDATA;
1002} FMAC_TypeDef;
1003
1008typedef struct
1009{
1010 __IO uint32_t BTCR[8];
1011} FMC_Bank1_TypeDef;
1012
1017typedef struct
1018{
1019 __IO uint32_t BWTR[7];
1020} FMC_Bank1E_TypeDef;
1021
1026typedef struct
1027{
1028 __IO uint32_t PCR2;
1029 __IO uint32_t SR2;
1030 __IO uint32_t PMEM2;
1031 __IO uint32_t PATT2;
1032 uint32_t RESERVED0;
1033 __IO uint32_t ECCR2;
1034} FMC_Bank2_TypeDef;
1035
1040typedef struct
1041{
1042 __IO uint32_t PCR;
1043 __IO uint32_t SR;
1044 __IO uint32_t PMEM;
1045 __IO uint32_t PATT;
1046 uint32_t RESERVED;
1047 __IO uint32_t ECCR;
1048} FMC_Bank3_TypeDef;
1049
1055typedef struct
1056{
1057 __IO uint32_t SDCR[2];
1058 __IO uint32_t SDTR[2];
1059 __IO uint32_t SDCMR;
1060 __IO uint32_t SDRTR;
1061 __IO uint32_t SDSR;
1062} FMC_Bank5_6_TypeDef;
1063
1068typedef struct
1069{
1070 __IO uint32_t MODER;
1071 __IO uint32_t OTYPER;
1072 __IO uint32_t OSPEEDR;
1073 __IO uint32_t PUPDR;
1074 __IO uint32_t IDR;
1075 __IO uint32_t ODR;
1076 __IO uint32_t BSRR;
1077 __IO uint32_t LCKR;
1078 __IO uint32_t AFR[2];
1079} GPIO_TypeDef;
1080
1085typedef struct
1086{
1087 __IO uint32_t CSR;
1088 __IO uint32_t OTR;
1089 __IO uint32_t HSOTR;
1090} OPAMP_TypeDef;
1091
1096typedef struct
1097{
1098 uint32_t RESERVED1;
1099 __IO uint32_t PMCR;
1100 __IO uint32_t EXTICR[4];
1101 __IO uint32_t CFGR;
1102 uint32_t RESERVED2;
1103 __IO uint32_t CCCSR;
1104 __IO uint32_t CCVR;
1105 __IO uint32_t CCCR;
1106 uint32_t RESERVED3;
1107 __IO uint32_t ADC2ALT;
1108 uint32_t RESERVED4[60];
1109 __IO uint32_t PKGR;
1110 uint32_t RESERVED5[118];
1111 __IO uint32_t UR0;
1112 __IO uint32_t UR1;
1113 __IO uint32_t UR2;
1114 __IO uint32_t UR3;
1115 __IO uint32_t UR4;
1116 __IO uint32_t UR5;
1117 __IO uint32_t UR6;
1118 __IO uint32_t UR7;
1119 uint32_t RESERVED6[3];
1120 __IO uint32_t UR11;
1121 __IO uint32_t UR12;
1122 __IO uint32_t UR13;
1123 __IO uint32_t UR14;
1124 __IO uint32_t UR15;
1125 __IO uint32_t UR16;
1126 __IO uint32_t UR17;
1127 __IO uint32_t UR18;
1129} SYSCFG_TypeDef;
1130
1135typedef struct
1136{
1137 __IO uint32_t CR1;
1138 __IO uint32_t CR2;
1139 __IO uint32_t OAR1;
1140 __IO uint32_t OAR2;
1141 __IO uint32_t TIMINGR;
1142 __IO uint32_t TIMEOUTR;
1143 __IO uint32_t ISR;
1144 __IO uint32_t ICR;
1145 __IO uint32_t PECR;
1146 __IO uint32_t RXDR;
1147 __IO uint32_t TXDR;
1148} I2C_TypeDef;
1149
1154typedef struct
1155{
1156 __IO uint32_t KR;
1157 __IO uint32_t PR;
1158 __IO uint32_t RLR;
1159 __IO uint32_t SR;
1160 __IO uint32_t WINR;
1161} IWDG_TypeDef;
1162
1163
1168typedef struct
1169{
1170 uint32_t RESERVED0[2];
1171 __IO uint32_t SSCR;
1172 __IO uint32_t BPCR;
1173 __IO uint32_t AWCR;
1174 __IO uint32_t TWCR;
1175 __IO uint32_t GCR;
1176 uint32_t RESERVED1[2];
1177 __IO uint32_t SRCR;
1178 uint32_t RESERVED2[1];
1179 __IO uint32_t BCCR;
1180 uint32_t RESERVED3[1];
1181 __IO uint32_t IER;
1182 __IO uint32_t ISR;
1183 __IO uint32_t ICR;
1184 __IO uint32_t LIPCR;
1185 __IO uint32_t CPSR;
1186 __IO uint32_t CDSR;
1187} LTDC_TypeDef;
1188
1193typedef struct
1194{
1195 __IO uint32_t CR;
1196 __IO uint32_t WHPCR;
1197 __IO uint32_t WVPCR;
1198 __IO uint32_t CKCR;
1199 __IO uint32_t PFCR;
1200 __IO uint32_t CACR;
1201 __IO uint32_t DCCR;
1202 __IO uint32_t BFCR;
1203 uint32_t RESERVED0[2];
1204 __IO uint32_t CFBAR;
1205 __IO uint32_t CFBLR;
1206 __IO uint32_t CFBLNR;
1207 uint32_t RESERVED1[3];
1208 __IO uint32_t CLUTWR;
1210} LTDC_Layer_TypeDef;
1211
1216typedef struct
1217{
1218 __IO uint32_t CR1;
1219 __IO uint32_t CSR1;
1220 __IO uint32_t CR2;
1221 __IO uint32_t CR3;
1222 __IO uint32_t CPUCR;
1223 uint32_t RESERVED0;
1224 __IO uint32_t D3CR;
1225 uint32_t RESERVED1;
1226 __IO uint32_t WKUPCR;
1227 __IO uint32_t WKUPFR;
1228 __IO uint32_t WKUPEPR;
1229} PWR_TypeDef;
1230
1235typedef struct
1236{
1237 __IO uint32_t CR;
1238 __IO uint32_t HSICFGR;
1239 __IO uint32_t CRRCR;
1240 __IO uint32_t CSICFGR;
1241 __IO uint32_t CFGR;
1242 uint32_t RESERVED1;
1243 __IO uint32_t D1CFGR;
1244 __IO uint32_t D2CFGR;
1245 __IO uint32_t D3CFGR;
1246 uint32_t RESERVED2;
1247 __IO uint32_t PLLCKSELR;
1248 __IO uint32_t PLLCFGR;
1249 __IO uint32_t PLL1DIVR;
1250 __IO uint32_t PLL1FRACR;
1251 __IO uint32_t PLL2DIVR;
1252 __IO uint32_t PLL2FRACR;
1253 __IO uint32_t PLL3DIVR;
1254 __IO uint32_t PLL3FRACR;
1255 uint32_t RESERVED3;
1256 __IO uint32_t D1CCIPR;
1257 __IO uint32_t D2CCIP1R;
1258 __IO uint32_t D2CCIP2R;
1259 __IO uint32_t D3CCIPR;
1260 uint32_t RESERVED4;
1261 __IO uint32_t CIER;
1262 __IO uint32_t CIFR;
1263 __IO uint32_t CICR;
1264 uint32_t RESERVED5;
1265 __IO uint32_t BDCR;
1266 __IO uint32_t CSR;
1267 uint32_t RESERVED6;
1268 __IO uint32_t AHB3RSTR;
1269 __IO uint32_t AHB1RSTR;
1270 __IO uint32_t AHB2RSTR;
1271 __IO uint32_t AHB4RSTR;
1272 __IO uint32_t APB3RSTR;
1273 __IO uint32_t APB1LRSTR;
1274 __IO uint32_t APB1HRSTR;
1275 __IO uint32_t APB2RSTR;
1276 __IO uint32_t APB4RSTR;
1277 __IO uint32_t GCR;
1278 uint32_t RESERVED8;
1279 __IO uint32_t D3AMR;
1280 uint32_t RESERVED11[9];
1281 __IO uint32_t RSR;
1282 __IO uint32_t AHB3ENR;
1283 __IO uint32_t AHB1ENR;
1284 __IO uint32_t AHB2ENR;
1285 __IO uint32_t AHB4ENR;
1286 __IO uint32_t APB3ENR;
1287 __IO uint32_t APB1LENR;
1288 __IO uint32_t APB1HENR;
1289 __IO uint32_t APB2ENR;
1290 __IO uint32_t APB4ENR;
1291 uint32_t RESERVED12;
1292 __IO uint32_t AHB3LPENR;
1293 __IO uint32_t AHB1LPENR;
1294 __IO uint32_t AHB2LPENR;
1295 __IO uint32_t AHB4LPENR;
1296 __IO uint32_t APB3LPENR;
1297 __IO uint32_t APB1LLPENR;
1298 __IO uint32_t APB1HLPENR;
1299 __IO uint32_t APB2LPENR;
1300 __IO uint32_t APB4LPENR;
1301 uint32_t RESERVED13[4];
1303} RCC_TypeDef;
1304
1305
1309typedef struct
1310{
1311 __IO uint32_t TR;
1312 __IO uint32_t DR;
1313 __IO uint32_t CR;
1314 __IO uint32_t ISR;
1315 __IO uint32_t PRER;
1316 __IO uint32_t WUTR;
1317 uint32_t RESERVED;
1318 __IO uint32_t ALRMAR;
1319 __IO uint32_t ALRMBR;
1320 __IO uint32_t WPR;
1321 __IO uint32_t SSR;
1322 __IO uint32_t SHIFTR;
1323 __IO uint32_t TSTR;
1324 __IO uint32_t TSDR;
1325 __IO uint32_t TSSSR;
1326 __IO uint32_t CALR;
1327 __IO uint32_t TAMPCR;
1328 __IO uint32_t ALRMASSR;
1329 __IO uint32_t ALRMBSSR;
1330 __IO uint32_t OR;
1331 __IO uint32_t BKP0R;
1332 __IO uint32_t BKP1R;
1333 __IO uint32_t BKP2R;
1334 __IO uint32_t BKP3R;
1335 __IO uint32_t BKP4R;
1336 __IO uint32_t BKP5R;
1337 __IO uint32_t BKP6R;
1338 __IO uint32_t BKP7R;
1339 __IO uint32_t BKP8R;
1340 __IO uint32_t BKP9R;
1341 __IO uint32_t BKP10R;
1342 __IO uint32_t BKP11R;
1343 __IO uint32_t BKP12R;
1344 __IO uint32_t BKP13R;
1345 __IO uint32_t BKP14R;
1346 __IO uint32_t BKP15R;
1347 __IO uint32_t BKP16R;
1348 __IO uint32_t BKP17R;
1349 __IO uint32_t BKP18R;
1350 __IO uint32_t BKP19R;
1351 __IO uint32_t BKP20R;
1352 __IO uint32_t BKP21R;
1353 __IO uint32_t BKP22R;
1354 __IO uint32_t BKP23R;
1355 __IO uint32_t BKP24R;
1356 __IO uint32_t BKP25R;
1357 __IO uint32_t BKP26R;
1358 __IO uint32_t BKP27R;
1359 __IO uint32_t BKP28R;
1360 __IO uint32_t BKP29R;
1361 __IO uint32_t BKP30R;
1362 __IO uint32_t BKP31R;
1363} RTC_TypeDef;
1364
1369typedef struct
1370{
1371 __IO uint32_t GCR;
1372 uint32_t RESERVED0[16];
1373 __IO uint32_t PDMCR;
1374 __IO uint32_t PDMDLY;
1375} SAI_TypeDef;
1376
1377typedef struct
1378{
1379 __IO uint32_t CR1;
1380 __IO uint32_t CR2;
1381 __IO uint32_t FRCR;
1382 __IO uint32_t SLOTR;
1383 __IO uint32_t IMR;
1384 __IO uint32_t SR;
1385 __IO uint32_t CLRFR;
1386 __IO uint32_t DR;
1387} SAI_Block_TypeDef;
1388
1393typedef struct
1394{
1395 __IO uint32_t CR;
1396 __IO uint32_t IMR;
1397 __IO uint32_t SR;
1398 __IO uint32_t IFCR;
1399 __IO uint32_t DR;
1400 __IO uint32_t CSR;
1401 __IO uint32_t DIR;
1402 uint32_t RESERVED2;
1403} SPDIFRX_TypeDef;
1404
1405
1410typedef struct
1411{
1412 __IO uint32_t POWER;
1413 __IO uint32_t CLKCR;
1414 __IO uint32_t ARG;
1415 __IO uint32_t CMD;
1416 __I uint32_t RESPCMD;
1417 __I uint32_t RESP1;
1418 __I uint32_t RESP2;
1419 __I uint32_t RESP3;
1420 __I uint32_t RESP4;
1421 __IO uint32_t DTIMER;
1422 __IO uint32_t DLEN;
1423 __IO uint32_t DCTRL;
1424 __I uint32_t DCOUNT;
1425 __I uint32_t STA;
1426 __IO uint32_t ICR;
1427 __IO uint32_t MASK;
1428 __IO uint32_t ACKTIME;
1429 uint32_t RESERVED0[3];
1430 __IO uint32_t IDMACTRL;
1431 __IO uint32_t IDMABSIZE;
1432 __IO uint32_t IDMABASE0;
1433 __IO uint32_t IDMABASE1;
1434 uint32_t RESERVED1[8];
1435 __IO uint32_t FIFO;
1436 uint32_t RESERVED2[222];
1437 __IO uint32_t IPVR;
1438} SDMMC_TypeDef;
1439
1440
1445typedef struct
1446{
1447 __IO uint32_t CR;
1448 __IO uint32_t CFGR;
1449} DLYB_TypeDef;
1450
1455typedef struct
1456{
1457 __IO uint32_t R[32];
1458 __IO uint32_t RLR[32];
1459 __IO uint32_t C1IER;
1460 __IO uint32_t C1ICR;
1461 __IO uint32_t C1ISR;
1462 __IO uint32_t C1MISR;
1463 uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
1464 __IO uint32_t CR;
1465 __IO uint32_t KEYR;
1467} HSEM_TypeDef;
1468
1469typedef struct
1470{
1471 __IO uint32_t IER;
1472 __IO uint32_t ICR;
1473 __IO uint32_t ISR;
1474 __IO uint32_t MISR;
1475} HSEM_Common_TypeDef;
1476
1481typedef struct
1482{
1483 __IO uint32_t CR1;
1484 __IO uint32_t CR2;
1485 __IO uint32_t CFG1;
1486 __IO uint32_t CFG2;
1487 __IO uint32_t IER;
1488 __IO uint32_t SR;
1489 __IO uint32_t IFCR;
1490 uint32_t RESERVED0;
1491 __IO uint32_t TXDR;
1492 uint32_t RESERVED1[3];
1493 __IO uint32_t RXDR;
1494 uint32_t RESERVED2[3];
1495 __IO uint32_t CRCPOLY;
1496 __IO uint32_t TXCRC;
1497 __IO uint32_t RXCRC;
1498 __IO uint32_t UDRDR;
1499 __IO uint32_t I2SCFGR;
1501} SPI_TypeDef;
1502
1506typedef struct
1507{
1508 __IO uint32_t CFGR1;
1509 uint32_t RESERVED0;
1510 __IO uint32_t T0VALR1;
1511 uint32_t RESERVED1;
1512 __IO uint32_t RAMPVALR;
1513 __IO uint32_t ITR1;
1514 uint32_t RESERVED2;
1515 __IO uint32_t DR;
1516 __IO uint32_t SR;
1517 __IO uint32_t ITENR;
1518 __IO uint32_t ICIFR;
1519 __IO uint32_t OR;
1520}
1521DTS_TypeDef;
1522
1527typedef struct
1528{
1529 __IO uint32_t CR1;
1530 __IO uint32_t CR2;
1531 __IO uint32_t SMCR;
1532 __IO uint32_t DIER;
1533 __IO uint32_t SR;
1534 __IO uint32_t EGR;
1535 __IO uint32_t CCMR1;
1536 __IO uint32_t CCMR2;
1537 __IO uint32_t CCER;
1538 __IO uint32_t CNT;
1539 __IO uint32_t PSC;
1540 __IO uint32_t ARR;
1541 __IO uint32_t RCR;
1542 __IO uint32_t CCR1;
1543 __IO uint32_t CCR2;
1544 __IO uint32_t CCR3;
1545 __IO uint32_t CCR4;
1546 __IO uint32_t BDTR;
1547 __IO uint32_t DCR;
1548 __IO uint32_t DMAR;
1549 uint32_t RESERVED1;
1550 __IO uint32_t CCMR3;
1551 __IO uint32_t CCR5;
1552 __IO uint32_t CCR6;
1553 __IO uint32_t AF1;
1554 __IO uint32_t AF2;
1555 __IO uint32_t TISEL;
1556} TIM_TypeDef;
1557
1561typedef struct
1562{
1563 __IO uint32_t ISR;
1564 __IO uint32_t ICR;
1565 __IO uint32_t IER;
1566 __IO uint32_t CFGR;
1567 __IO uint32_t CR;
1568 __IO uint32_t CMP;
1569 __IO uint32_t ARR;
1570 __IO uint32_t CNT;
1571 uint32_t RESERVED1;
1572 __IO uint32_t CFGR2;
1573} LPTIM_TypeDef;
1574
1578typedef struct
1579{
1580 __IO uint32_t SR;
1581 __IO uint32_t ICFR;
1582 __IO uint32_t OR;
1583} COMPOPT_TypeDef;
1584
1585typedef struct
1586{
1587 __IO uint32_t CFGR;
1588} COMP_TypeDef;
1589
1590typedef struct
1591{
1592 __IO uint32_t CFGR;
1593} COMP_Common_TypeDef;
1598typedef struct
1599{
1600 __IO uint32_t CR1;
1601 __IO uint32_t CR2;
1602 __IO uint32_t CR3;
1603 __IO uint32_t BRR;
1604 __IO uint32_t GTPR;
1605 __IO uint32_t RTOR;
1606 __IO uint32_t RQR;
1607 __IO uint32_t ISR;
1608 __IO uint32_t ICR;
1609 __IO uint32_t RDR;
1610 __IO uint32_t TDR;
1611 __IO uint32_t PRESC;
1612} USART_TypeDef;
1613
1617typedef struct
1618{
1619 __IO uint32_t CR;
1620 __IO uint32_t BRR;
1621 uint32_t RESERVED1;
1622 __IO uint32_t ISR;
1623 __IO uint32_t ICR;
1624 __IO uint32_t IER;
1625 __IO uint32_t RFL;
1626 __IO uint32_t TDR;
1627 __IO uint32_t RDR;
1628 __IO uint32_t OR;
1629} SWPMI_TypeDef;
1630
1635typedef struct
1636{
1637 __IO uint32_t CR;
1638 __IO uint32_t CFR;
1639 __IO uint32_t SR;
1640} WWDG_TypeDef;
1641
1642
1646typedef struct
1647{
1648 __IO uint32_t CR;
1649 __IO uint32_t SR;
1650 __IO uint32_t FAR;
1651 __IO uint32_t FDRL;
1652 __IO uint32_t FDRH;
1653 __IO uint32_t FECR;
1654} RAMECC_MonitorTypeDef;
1655
1656typedef struct
1657{
1658 __IO uint32_t IER;
1659} RAMECC_TypeDef;
1669typedef struct
1670{
1671 __IO uint32_t CR;
1672 __IO uint32_t SR;
1673 __IO uint32_t DIN;
1674 __IO uint32_t DOUT;
1675 __IO uint32_t DMACR;
1676 __IO uint32_t IMSCR;
1677 __IO uint32_t RISR;
1678 __IO uint32_t MISR;
1679 __IO uint32_t K0LR;
1680 __IO uint32_t K0RR;
1681 __IO uint32_t K1LR;
1682 __IO uint32_t K1RR;
1683 __IO uint32_t K2LR;
1684 __IO uint32_t K2RR;
1685 __IO uint32_t K3LR;
1686 __IO uint32_t K3RR;
1687 __IO uint32_t IV0LR;
1688 __IO uint32_t IV0RR;
1689 __IO uint32_t IV1LR;
1690 __IO uint32_t IV1RR;
1691 __IO uint32_t CSGCMCCM0R;
1692 __IO uint32_t CSGCMCCM1R;
1693 __IO uint32_t CSGCMCCM2R;
1694 __IO uint32_t CSGCMCCM3R;
1695 __IO uint32_t CSGCMCCM4R;
1696 __IO uint32_t CSGCMCCM5R;
1697 __IO uint32_t CSGCMCCM6R;
1698 __IO uint32_t CSGCMCCM7R;
1699 __IO uint32_t CSGCM0R;
1700 __IO uint32_t CSGCM1R;
1701 __IO uint32_t CSGCM2R;
1702 __IO uint32_t CSGCM3R;
1703 __IO uint32_t CSGCM4R;
1704 __IO uint32_t CSGCM5R;
1705 __IO uint32_t CSGCM6R;
1706 __IO uint32_t CSGCM7R;
1707} CRYP_TypeDef;
1708
1713typedef struct
1714{
1715 __IO uint32_t CR;
1716 __IO uint32_t DIN;
1717 __IO uint32_t STR;
1718 __IO uint32_t HR[5];
1719 __IO uint32_t IMR;
1720 __IO uint32_t SR;
1721 uint32_t RESERVED[52];
1722 __IO uint32_t CSR[54];
1723} HASH_TypeDef;
1724
1729typedef struct
1730{
1731 __IO uint32_t HR[8];
1732} HASH_DIGEST_TypeDef;
1733
1734
1739typedef struct
1740{
1741 __IO uint32_t CR;
1742 __IO uint32_t SR;
1743 __IO uint32_t DR;
1744 uint32_t RESERVED;
1745 __IO uint32_t HTCR;
1746} RNG_TypeDef;
1747
1752typedef struct
1753{
1754 __IO uint32_t CR;
1755 __IO uint32_t WRFR;
1756 __IO uint32_t CWRFR;
1757 __IO uint32_t RDFR;
1758 __IO uint32_t CRDFR;
1759 __IO uint32_t SR;
1760 __IO uint32_t CLRFR;
1761 uint32_t RESERVED[57];
1762 __IO uint32_t DINR0;
1763 __IO uint32_t DINR1;
1764 __IO uint32_t DINR2;
1765 __IO uint32_t DINR3;
1766 __IO uint32_t DINR4;
1767 __IO uint32_t DINR5;
1768 __IO uint32_t DINR6;
1769 __IO uint32_t DINR7;
1770 __IO uint32_t DINR8;
1771 __IO uint32_t DINR9;
1772 __IO uint32_t DINR10;
1773 __IO uint32_t DINR11;
1774 __IO uint32_t DINR12;
1775 __IO uint32_t DINR13;
1776 __IO uint32_t DINR14;
1777 __IO uint32_t DINR15;
1778 __IO uint32_t DINR16;
1779 __IO uint32_t DINR17;
1780 __IO uint32_t DINR18;
1781 __IO uint32_t DINR19;
1782 __IO uint32_t DINR20;
1783 __IO uint32_t DINR21;
1784 __IO uint32_t DINR22;
1785 __IO uint32_t DINR23;
1786 __IO uint32_t DINR24;
1787 __IO uint32_t DINR25;
1788 __IO uint32_t DINR26;
1789 __IO uint32_t DINR27;
1790 __IO uint32_t DINR28;
1791 __IO uint32_t DINR29;
1792 __IO uint32_t DINR30;
1793 __IO uint32_t DINR31;
1794 __IO uint32_t DOUTR0;
1795 __IO uint32_t DOUTR1;
1796 __IO uint32_t DOUTR2;
1797 __IO uint32_t DOUTR3;
1798 __IO uint32_t DOUTR4;
1799 __IO uint32_t DOUTR5;
1800 __IO uint32_t DOUTR6;
1801 __IO uint32_t DOUTR7;
1802 __IO uint32_t DOUTR8;
1803 __IO uint32_t DOUTR9;
1804 __IO uint32_t DOUTR10;
1805 __IO uint32_t DOUTR11;
1806 __IO uint32_t DOUTR12;
1807 __IO uint32_t DOUTR13;
1808 __IO uint32_t DOUTR14;
1809 __IO uint32_t DOUTR15;
1810 __IO uint32_t DOUTR16;
1811 __IO uint32_t DOUTR17;
1812 __IO uint32_t DOUTR18;
1813 __IO uint32_t DOUTR19;
1814 __IO uint32_t DOUTR20;
1815 __IO uint32_t DOUTR21;
1816 __IO uint32_t DOUTR22;
1817 __IO uint32_t DOUTR23;
1818 __IO uint32_t DOUTR24;
1819 __IO uint32_t DOUTR25;
1820 __IO uint32_t DOUTR26;
1821 __IO uint32_t DOUTR27;
1822 __IO uint32_t DOUTR28;
1823 __IO uint32_t DOUTR29;
1824 __IO uint32_t DOUTR30;
1825 __IO uint32_t DOUTR31;
1826} MDIOS_TypeDef;
1827
1828
1832typedef struct
1833{
1834 __IO uint32_t GOTGCTL;
1835 __IO uint32_t GOTGINT;
1836 __IO uint32_t GAHBCFG;
1837 __IO uint32_t GUSBCFG;
1838 __IO uint32_t GRSTCTL;
1839 __IO uint32_t GINTSTS;
1840 __IO uint32_t GINTMSK;
1841 __IO uint32_t GRXSTSR;
1842 __IO uint32_t GRXSTSP;
1843 __IO uint32_t GRXFSIZ;
1844 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1845 __IO uint32_t HNPTXSTS;
1846 uint32_t Reserved30[2];
1847 __IO uint32_t GCCFG;
1848 __IO uint32_t CID;
1849 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1850 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1851 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1852 __IO uint32_t GHWCFG3;
1853 uint32_t Reserved6;
1854 __IO uint32_t GLPMCFG;
1855 __IO uint32_t GPWRDN;
1856 __IO uint32_t GDFIFOCFG;
1857 __IO uint32_t GADPCTL;
1858 uint32_t Reserved43[39];
1859 __IO uint32_t HPTXFSIZ;
1860 __IO uint32_t DIEPTXF[0x0F];
1861} USB_OTG_GlobalTypeDef;
1862
1863
1867typedef struct
1868{
1869 __IO uint32_t DCFG;
1870 __IO uint32_t DCTL;
1871 __IO uint32_t DSTS;
1872 uint32_t Reserved0C;
1873 __IO uint32_t DIEPMSK;
1874 __IO uint32_t DOEPMSK;
1875 __IO uint32_t DAINT;
1876 __IO uint32_t DAINTMSK;
1877 uint32_t Reserved20;
1878 uint32_t Reserved9;
1879 __IO uint32_t DVBUSDIS;
1880 __IO uint32_t DVBUSPULSE;
1881 __IO uint32_t DTHRCTL;
1882 __IO uint32_t DIEPEMPMSK;
1883 __IO uint32_t DEACHINT;
1884 __IO uint32_t DEACHMSK;
1885 uint32_t Reserved40;
1886 __IO uint32_t DINEP1MSK;
1887 uint32_t Reserved44[15];
1888 __IO uint32_t DOUTEP1MSK;
1889} USB_OTG_DeviceTypeDef;
1890
1891
1895typedef struct
1896{
1897 __IO uint32_t DIEPCTL;
1898 uint32_t Reserved04;
1899 __IO uint32_t DIEPINT;
1900 uint32_t Reserved0C;
1901 __IO uint32_t DIEPTSIZ;
1902 __IO uint32_t DIEPDMA;
1903 __IO uint32_t DTXFSTS;
1904 uint32_t Reserved18;
1905} USB_OTG_INEndpointTypeDef;
1906
1907
1911typedef struct
1912{
1913 __IO uint32_t DOEPCTL;
1914 uint32_t Reserved04;
1915 __IO uint32_t DOEPINT;
1916 uint32_t Reserved0C;
1917 __IO uint32_t DOEPTSIZ;
1918 __IO uint32_t DOEPDMA;
1919 uint32_t Reserved18[2];
1920} USB_OTG_OUTEndpointTypeDef;
1921
1922
1926typedef struct
1927{
1928 __IO uint32_t HCFG;
1929 __IO uint32_t HFIR;
1930 __IO uint32_t HFNUM;
1931 uint32_t Reserved40C;
1932 __IO uint32_t HPTXSTS;
1933 __IO uint32_t HAINT;
1934 __IO uint32_t HAINTMSK;
1935} USB_OTG_HostTypeDef;
1936
1940typedef struct
1941{
1942 __IO uint32_t HCCHAR;
1943 __IO uint32_t HCSPLT;
1944 __IO uint32_t HCINT;
1945 __IO uint32_t HCINTMSK;
1946 __IO uint32_t HCTSIZ;
1947 __IO uint32_t HCDMA;
1948 uint32_t Reserved[2];
1949} USB_OTG_HostChannelTypeDef;
1958typedef struct
1959{
1960 __IO uint32_t CR;
1961 uint32_t RESERVED;
1962 __IO uint32_t DCR1;
1963 __IO uint32_t DCR2;
1964 __IO uint32_t DCR3;
1965 __IO uint32_t DCR4;
1966 uint32_t RESERVED1[2];
1967 __IO uint32_t SR;
1968 __IO uint32_t FCR;
1969 uint32_t RESERVED2[6];
1970 __IO uint32_t DLR;
1971 uint32_t RESERVED3;
1972 __IO uint32_t AR;
1973 uint32_t RESERVED4;
1974 __IO uint32_t DR;
1975 uint32_t RESERVED5[11];
1976 __IO uint32_t PSMKR;
1977 uint32_t RESERVED6;
1978 __IO uint32_t PSMAR;
1979 uint32_t RESERVED7;
1980 __IO uint32_t PIR;
1981 uint32_t RESERVED8[27];
1982 __IO uint32_t CCR;
1983 uint32_t RESERVED9;
1984 __IO uint32_t TCR;
1985 uint32_t RESERVED10;
1986 __IO uint32_t IR;
1987 uint32_t RESERVED11[3];
1988 __IO uint32_t ABR;
1989 uint32_t RESERVED12[3];
1990 __IO uint32_t LPTR;
1991 uint32_t RESERVED13[3];
1992 __IO uint32_t WPCCR;
1993 uint32_t RESERVED14;
1994 __IO uint32_t WPTCR;
1995 uint32_t RESERVED15;
1996 __IO uint32_t WPIR;
1997 uint32_t RESERVED16[3];
1998 __IO uint32_t WPABR;
1999 uint32_t RESERVED17[7];
2000 __IO uint32_t WCCR;
2001 uint32_t RESERVED18;
2002 __IO uint32_t WTCR;
2003 uint32_t RESERVED19;
2004 __IO uint32_t WIR;
2005 uint32_t RESERVED20[3];
2006 __IO uint32_t WABR;
2007 uint32_t RESERVED21[23];
2008 __IO uint32_t HLCR;
2009 uint32_t RESERVED22[122];
2010 __IO uint32_t HWCFGR;
2011 __IO uint32_t VER;
2012 __IO uint32_t ID;
2013 __IO uint32_t MID;
2014} OCTOSPI_TypeDef;
2015
2023typedef struct
2024{
2025 __IO uint32_t CR;
2026 __IO uint32_t PCR[3];
2027} OCTOSPIM_TypeDef;
2028
2036typedef struct
2037{
2038 __IO uint32_t REG_CONFIGR;
2039 __IO uint32_t REG_START_ADDR;
2040 __IO uint32_t REG_END_ADDR;
2041 __IO uint32_t REG_NONCER0;
2042 __IO uint32_t REG_NONCER1;
2043 __IO uint32_t REG_KEYR0;
2044 __IO uint32_t REG_KEYR1;
2045 __IO uint32_t REG_KEYR2;
2046 __IO uint32_t REG_KEYR3;
2047} OTFDEC_Region_TypeDef;
2048
2049typedef struct
2050{
2051 __IO uint32_t CR;
2052 uint32_t RESERVED1[191];
2053 __IO uint32_t ISR;
2054 __IO uint32_t ICR;
2055 __IO uint32_t IER;
2056 uint32_t RESERVED2[56];
2057 __IO uint32_t HWCFGR2;
2058 __IO uint32_t HWCFGR1;
2059 __IO uint32_t VERR;
2060 __IO uint32_t IPIDR;
2061 __IO uint32_t SIDR;
2062} OTFDEC_TypeDef;
2071typedef struct
2072{
2073 uint32_t RESERVED0[2036];
2074 __IO uint32_t AXI_PERIPH_ID_4;
2075 uint32_t AXI_PERIPH_ID_5;
2076 uint32_t AXI_PERIPH_ID_6;
2077 uint32_t AXI_PERIPH_ID_7;
2078 __IO uint32_t AXI_PERIPH_ID_0;
2079 __IO uint32_t AXI_PERIPH_ID_1;
2080 __IO uint32_t AXI_PERIPH_ID_2;
2081 __IO uint32_t AXI_PERIPH_ID_3;
2082 __IO uint32_t AXI_COMP_ID_0;
2083 __IO uint32_t AXI_COMP_ID_1;
2084 __IO uint32_t AXI_COMP_ID_2;
2085 __IO uint32_t AXI_COMP_ID_3;
2086 uint32_t RESERVED1[2];
2087 __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM;
2088 uint32_t RESERVED2[6];
2089 __IO uint32_t AXI_TARG1_FN_MOD2;
2090 uint32_t RESERVED3;
2091 __IO uint32_t AXI_TARG1_FN_MOD_LB;
2092 uint32_t RESERVED4[54];
2093 __IO uint32_t AXI_TARG1_FN_MOD;
2094 uint32_t RESERVED5[959];
2095 __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM;
2096 uint32_t RESERVED6[6];
2097 __IO uint32_t AXI_TARG2_FN_MOD2;
2098 uint32_t RESERVED7;
2099 __IO uint32_t AXI_TARG2_FN_MOD_LB;
2100 uint32_t RESERVED8[54];
2101 __IO uint32_t AXI_TARG2_FN_MOD;
2102 uint32_t RESERVED9[959];
2103 __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM;
2104 uint32_t RESERVED10[1023];
2105 __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM;
2106 uint32_t RESERVED11[1023];
2107 __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM;
2108 uint32_t RESERVED12[1023];
2109 __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM;
2110 uint32_t RESERVED13[1023];
2111 __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM;
2112 uint32_t RESERVED14[6];
2113 __IO uint32_t AXI_TARG7_FN_MOD2;
2114 uint32_t RESERVED15;
2115 __IO uint32_t AXI_TARG7_FN_MOD_LB;
2116 uint32_t RESERVED16[54];
2117 __IO uint32_t AXI_TARG7_FN_MOD;
2118 uint32_t RESERVED17[959];
2119 __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM;
2120 uint32_t RESERVED117[6];
2121 __IO uint32_t AXI_TARG8_FN_MOD2;
2122 uint32_t RESERVED118[56];
2123 __IO uint32_t AXI_TARG8_FN_MOD;
2124 uint32_t RESERVED119[58310];
2125 __IO uint32_t AXI_INI1_FN_MOD2;
2126 __IO uint32_t AXI_INI1_FN_MOD_AHB;
2127 uint32_t RESERVED18[53];
2128 __IO uint32_t AXI_INI1_READ_QOS;
2129 __IO uint32_t AXI_INI1_WRITE_QOS;
2130 __IO uint32_t AXI_INI1_FN_MOD;
2131 uint32_t RESERVED19[1021];
2132 __IO uint32_t AXI_INI2_READ_QOS;
2133 __IO uint32_t AXI_INI2_WRITE_QOS;
2134 __IO uint32_t AXI_INI2_FN_MOD;
2135 uint32_t RESERVED20[966];
2136 __IO uint32_t AXI_INI3_FN_MOD2;
2137 __IO uint32_t AXI_INI3_FN_MOD_AHB;
2138 uint32_t RESERVED21[53];
2139 __IO uint32_t AXI_INI3_READ_QOS;
2140 __IO uint32_t AXI_INI3_WRITE_QOS;
2141 __IO uint32_t AXI_INI3_FN_MOD;
2142 uint32_t RESERVED22[1021];
2143 __IO uint32_t AXI_INI4_READ_QOS;
2144 __IO uint32_t AXI_INI4_WRITE_QOS;
2145 __IO uint32_t AXI_INI4_FN_MOD;
2146 uint32_t RESERVED23[1021];
2147 __IO uint32_t AXI_INI5_READ_QOS;
2148 __IO uint32_t AXI_INI5_WRITE_QOS;
2149 __IO uint32_t AXI_INI5_FN_MOD;
2150 uint32_t RESERVED24[1021];
2151 __IO uint32_t AXI_INI6_READ_QOS;
2152 __IO uint32_t AXI_INI6_WRITE_QOS;
2153 __IO uint32_t AXI_INI6_FN_MOD;
2155} GPV_TypeDef;
2156
2160#define D1_ITCMRAM_BASE (0x00000000UL)
2161#define D1_ITCMICP_BASE (0x00100000UL)
2162#define D1_DTCMRAM_BASE (0x20000000UL)
2163#define D1_AXIFLASH_BASE (0x08000000UL)
2164#define D1_AXIICP_BASE (0x1FF00000UL)
2165#define D1_AXISRAM1_BASE (0x24000000UL)
2166#define D1_AXISRAM2_BASE (0x24020000UL)
2167#define D1_AXISRAM_BASE D1_AXISRAM1_BASE
2169#define D2_AHBSRAM1_BASE (0x30000000UL)
2170#define D2_AHBSRAM2_BASE (0x30004000UL)
2171#define D2_AHBSRAM_BASE D2_AHBSRAM1_BASE
2173#define D3_BKPSRAM_BASE (0x38800000UL)
2174#define D3_SRAM_BASE (0x38000000UL)
2176#define PERIPH_BASE (0x40000000UL)
2177#define OCTOSPI1_BASE (0x90000000UL)
2178#define OCTOSPI2_BASE (0x70000000UL)
2180#define FLASH_BANK1_BASE (0x08000000UL)
2181#define FLASH_END (0x0801FFFFUL)
2184/* Legacy define */
2185#define FLASH_BASE FLASH_BANK1_BASE
2186
2188#define UID_BASE (0x1FF1E800UL)
2189#define FLASHSIZE_BASE (0x1FF1E880UL)
2193#define D2_APB1PERIPH_BASE PERIPH_BASE
2194#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2195#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2196#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
2197
2198#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
2199#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
2200
2201#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
2202#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
2203
2205#define APB1PERIPH_BASE PERIPH_BASE
2206#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2207#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2208#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
2209
2210
2213#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
2214#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
2215#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
2216#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
2217#define OCTOSPI1_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
2218#define DLYB_OCTOSPI1_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
2219#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
2220#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
2221#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
2222#define OCTOSPI2_R_BASE (D1_AHB1PERIPH_BASE + 0xA000UL)
2223#define DLYB_OCTOSPI2_BASE (D1_AHB1PERIPH_BASE + 0xB000UL)
2224#define OCTOSPIM_BASE (D1_AHB1PERIPH_BASE + 0xB400UL)
2225
2226#define OTFDEC1_BASE (D1_AHB1PERIPH_BASE + 0xB800UL)
2227#define OTFDEC1_REGION1_BASE (OTFDEC1_BASE + 0x20UL)
2228#define OTFDEC1_REGION2_BASE (OTFDEC1_BASE + 0x50UL)
2229#define OTFDEC1_REGION3_BASE (OTFDEC1_BASE + 0x80UL)
2230#define OTFDEC1_REGION4_BASE (OTFDEC1_BASE + 0xB0UL)
2231#define OTFDEC2_BASE (D1_AHB1PERIPH_BASE + 0xBC00UL)
2232#define OTFDEC2_REGION1_BASE (OTFDEC2_BASE + 0x20UL)
2233#define OTFDEC2_REGION2_BASE (OTFDEC2_BASE + 0x50UL)
2234#define OTFDEC2_REGION3_BASE (OTFDEC2_BASE + 0x80UL)
2235#define OTFDEC2_REGION4_BASE (OTFDEC2_BASE + 0xB0UL)
2236
2239#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
2240#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
2241#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
2242#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
2243#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
2244#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
2245#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
2246#define ETH_MAC_BASE (ETH_BASE)
2247
2249#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2250#define USB_OTG_GLOBAL_BASE (0x000UL)
2251#define USB_OTG_DEVICE_BASE (0x800UL)
2252#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2253#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2254#define USB_OTG_EP_REG_SIZE (0x20UL)
2255#define USB_OTG_HOST_BASE (0x400UL)
2256#define USB_OTG_HOST_PORT_BASE (0x440UL)
2257#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2258#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2259#define USB_OTG_PCGCCTL_BASE (0xE00UL)
2260#define USB_OTG_FIFO_BASE (0x1000UL)
2261#define USB_OTG_FIFO_SIZE (0x1000UL)
2262
2265#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
2266#define PSSI_BASE (D2_AHB2PERIPH_BASE + 0x0400UL)
2267#define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000UL)
2268#define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400UL)
2269#define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710UL)
2270#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
2271#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
2272#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
2273#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
2274#define FMAC_BASE (D2_AHB2PERIPH_BASE + 0x4000UL)
2275#define CORDIC_BASE (D2_AHB2PERIPH_BASE + 0x4400UL)
2276
2278#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
2279#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
2280#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
2281#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
2282#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
2283#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
2284#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
2285#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
2286#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
2287#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
2288#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
2289#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
2290#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
2291#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
2292#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
2293#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
2294#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
2295#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
2296#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
2297
2299#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
2300#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
2301#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
2302#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
2303
2305#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
2306#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
2307#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
2308#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
2309#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
2310#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
2311#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
2312#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
2313#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
2314#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
2315
2316
2317#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
2318#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
2319#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
2320#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
2321#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
2322#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
2323#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
2324#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
2325#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
2326#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
2327#define I2C5_BASE (D2_APB1PERIPH_BASE + 0x6400UL)
2328#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
2329#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
2330#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
2331#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
2332#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
2333#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
2334#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2335#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2336#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
2337#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
2338#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
2339#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
2340#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
2341#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
2342#define FDCAN3_BASE (D2_APB1PERIPH_BASE + 0xD400UL)
2343#define TIM23_BASE (D2_APB1PERIPH_BASE + 0xE000UL)
2344#define TIM24_BASE (D2_APB1PERIPH_BASE + 0xE400UL)
2345
2348#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
2349#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
2350#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
2351#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
2352#define UART9_BASE (D2_APB2PERIPH_BASE + 0x1800UL)
2353#define USART10_BASE (D2_APB2PERIPH_BASE + 0x1C00UL)
2354#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
2355#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
2356#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
2357#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
2358#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
2359#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
2360#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
2361#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2362#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2363#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7800UL)
2364#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2365#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2366#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2367#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2368#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2369#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2370#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2371#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2372#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2373#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2374#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2375#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2376
2377
2379#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
2380#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2381#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
2382#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
2383#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
2384#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
2385#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
2386#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
2387#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
2388#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
2389#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
2390#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
2391#define COMP1_BASE (COMP12_BASE + 0x0CUL)
2392#define COMP2_BASE (COMP12_BASE + 0x10UL)
2393#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
2394#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
2395#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
2396
2397
2398#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
2399#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
2400#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
2401
2402#define DTS_BASE (D3_APB1PERIPH_BASE + 0x6800UL)
2403
2404
2405
2406#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
2407#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
2408#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
2409#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
2410#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
2411#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
2412#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
2413#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
2414
2415#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2416#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2417#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2418#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2419#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2420#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2421#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2422#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2423
2424#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2425#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2426#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2427#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2428#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2429#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2430#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2431#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2432
2433#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2434#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2435
2436#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2437#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2438#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2439#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2440#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2441#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2442#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2443#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2444
2445#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2446#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2447#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2448#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2449#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2450#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2451#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2452#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2453
2454#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2455#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2456#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2457#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2458#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2459#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2460#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2461#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2462#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2463#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2464#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2465#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2466#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2467#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2468#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2469#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2470
2471#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2472#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2473#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2474#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2475#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2476#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2477#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2478#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2479
2480#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2481#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2482
2484#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2485#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2486#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2487#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2488#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2489
2490/* Debug MCU registers base address */
2491#define DBGMCU_BASE (0x5C001000UL)
2492
2493#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2494#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2495#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2496#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2497#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2498#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2499#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2500#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2501#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2502#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2503#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2504#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2505#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2506#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2507#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2508#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2509
2510#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
2511#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
2512#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
2513#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
2514#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
2515#define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL)
2516
2517#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
2518#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
2519#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
2520
2521#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
2522#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
2523
2524
2525
2526#define GPV_BASE (PERIPH_BASE + 0x11000000UL)
2535#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2536#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2537#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2538#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2539#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2540#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2541#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2542#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2543#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2544#define RTC ((RTC_TypeDef *) RTC_BASE)
2545#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2546
2547
2548#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2549#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2550#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2551#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2552#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2553#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2554#define USART2 ((USART_TypeDef *) USART2_BASE)
2555#define USART3 ((USART_TypeDef *) USART3_BASE)
2556#define USART6 ((USART_TypeDef *) USART6_BASE)
2557#define USART10 ((USART_TypeDef *) USART10_BASE)
2558#define UART7 ((USART_TypeDef *) UART7_BASE)
2559#define UART8 ((USART_TypeDef *) UART8_BASE)
2560#define UART9 ((USART_TypeDef *) UART9_BASE)
2561#define CRS ((CRS_TypeDef *) CRS_BASE)
2562#define UART4 ((USART_TypeDef *) UART4_BASE)
2563#define UART5 ((USART_TypeDef *) UART5_BASE)
2564#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2565#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2566#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2567#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2568#define I2C5 ((I2C_TypeDef *) I2C5_BASE)
2569#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2570#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2571#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2572#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
2573#define TIM23 ((TIM_TypeDef *) TIM23_BASE)
2574#define TIM24 ((TIM_TypeDef *) TIM24_BASE)
2575#define CEC ((CEC_TypeDef *) CEC_BASE)
2576#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2577#define PWR ((PWR_TypeDef *) PWR_BASE)
2578#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2579#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2580#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2581#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2582#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2583#define DTS ((DTS_TypeDef *) DTS_BASE)
2584#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
2585#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
2586
2587#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2588#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2589#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2590#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2591#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2592#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2593#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2594#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2595
2596
2597#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2598#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2599#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
2600#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2601#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2602#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2603#define USART1 ((USART_TypeDef *) USART1_BASE)
2604#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2605#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2606#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2607#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2608#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2609#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2610#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2611#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
2612#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
2613#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
2614
2615#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2616#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2617#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2618#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2619#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2620#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2621#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2622#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2623#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2624#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2625#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2626#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2627#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2628#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2629#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2630#define PSSI ((PSSI_TypeDef *) PSSI_BASE)
2631#define RCC ((RCC_TypeDef *) RCC_BASE)
2632#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2633#define CRC ((CRC_TypeDef *) CRC_BASE)
2634
2635#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2636#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2637#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2638#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2639#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2640#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2641#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2642#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2643#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2644#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2645
2646#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2647#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2648#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
2649#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
2650#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2651
2652#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
2653#define HASH ((HASH_TypeDef *) HASH_BASE)
2654#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
2655#define RNG ((RNG_TypeDef *) RNG_BASE)
2656#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2657#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2658#define FMAC ((FMAC_TypeDef *) FMAC_BASE)
2659#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
2660
2661#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
2662#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
2663#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
2664#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
2665#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
2666#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
2667#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
2668#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
2669#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
2670
2671#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
2672#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
2673#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
2674#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
2675#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
2676#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
2677#define RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE)
2678
2679#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
2680#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
2681#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
2682#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
2683
2684#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
2685#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
2686#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
2687
2688#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2689#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2690#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2691#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2692#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2693#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2694#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2695#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2696#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2697
2698
2699#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2700#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2701#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2702#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2703#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2704#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2705#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2706#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2707
2708#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2709#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2710
2711#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2712#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2713#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2714#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2715#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2716#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2717#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2718#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2719#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2720
2721#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2722#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2723#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2724#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2725#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2726#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2727#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2728#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2729#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2730
2731
2732#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2733#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2734#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2735#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2736#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2737#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2738#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2739#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2740#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2741#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2742#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2743#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2744#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2745#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2746#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2747#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2748#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2749
2750#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2751#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2752#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2753#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2754#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2755#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2756#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2757#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2758
2759#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2760#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2761
2762
2763#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2764#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2765#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2766#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2767#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2768
2769#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
2770#define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)
2771#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
2772#define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)
2773#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
2774
2775#define OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)
2776#define OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)
2777#define OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)
2778#define OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)
2779#define OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)
2780
2781#define OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)
2782#define OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)
2783#define OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)
2784#define OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)
2785#define OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)
2786
2787#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2788#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2789
2790#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2791
2792#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2793#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2794
2795#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2796#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2797#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2798
2799#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2800
2801#define ETH ((ETH_TypeDef *)ETH_BASE)
2802#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2803#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2804#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2805#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2806#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2807#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2808#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2809#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2810#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2811#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2812#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2813#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2814#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2815#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2816#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2817#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2818#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2819
2820
2821#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2822
2823/* Legacy defines */
2824#define USB_OTG_HS USB1_OTG_HS
2825#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2826
2827#define GPV ((GPV_TypeDef *) GPV_BASE)
2828
2840#define LSI_STARTUP_TIME 130U
2850/******************************************************************************/
2851/* Peripheral Registers_Bits_Definition */
2852/******************************************************************************/
2853
2854/******************************************************************************/
2855/* */
2856/* Analog to Digital Converter */
2857/* */
2858/******************************************************************************/
2859/******************************* ADC VERSION ********************************/
2860#define ADC_VER_V5_V90
2861/******************** Bit definition for ADC_ISR register ********************/
2862#define ADC_ISR_ADRDY_Pos (0U)
2863#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
2864#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
2865#define ADC_ISR_EOSMP_Pos (1U)
2866#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
2867#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
2868#define ADC_ISR_EOC_Pos (2U)
2869#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
2870#define ADC_ISR_EOC ADC_ISR_EOC_Msk
2871#define ADC_ISR_EOS_Pos (3U)
2872#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
2873#define ADC_ISR_EOS ADC_ISR_EOS_Msk
2874#define ADC_ISR_OVR_Pos (4U)
2875#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
2876#define ADC_ISR_OVR ADC_ISR_OVR_Msk
2877#define ADC_ISR_JEOC_Pos (5U)
2878#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)
2879#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk
2880#define ADC_ISR_JEOS_Pos (6U)
2881#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)
2882#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk
2883#define ADC_ISR_AWD1_Pos (7U)
2884#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
2885#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
2886#define ADC_ISR_AWD2_Pos (8U)
2887#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)
2888#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk
2889#define ADC_ISR_AWD3_Pos (9U)
2890#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)
2891#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk
2892#define ADC_ISR_JQOVF_Pos (10U)
2893#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)
2894#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk
2895#define ADC_ISR_LDORDY_Pos (12U)
2896#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos)
2897#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk
2899/******************** Bit definition for ADC_IER register ********************/
2900#define ADC_IER_ADRDYIE_Pos (0U)
2901#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
2902#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
2903#define ADC_IER_EOSMPIE_Pos (1U)
2904#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
2905#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
2906#define ADC_IER_EOCIE_Pos (2U)
2907#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
2908#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
2909#define ADC_IER_EOSIE_Pos (3U)
2910#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
2911#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
2912#define ADC_IER_OVRIE_Pos (4U)
2913#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
2914#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
2915#define ADC_IER_JEOCIE_Pos (5U)
2916#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)
2917#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk
2918#define ADC_IER_JEOSIE_Pos (6U)
2919#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)
2920#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk
2921#define ADC_IER_AWD1IE_Pos (7U)
2922#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
2923#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
2924#define ADC_IER_AWD2IE_Pos (8U)
2925#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)
2926#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk
2927#define ADC_IER_AWD3IE_Pos (9U)
2928#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)
2929#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk
2930#define ADC_IER_JQOVFIE_Pos (10U)
2931#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)
2932#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk
2934/******************** Bit definition for ADC_CR register ********************/
2935#define ADC_CR_ADEN_Pos (0U)
2936#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
2937#define ADC_CR_ADEN ADC_CR_ADEN_Msk
2938#define ADC_CR_ADDIS_Pos (1U)
2939#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
2940#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
2941#define ADC_CR_ADSTART_Pos (2U)
2942#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
2943#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
2944#define ADC_CR_JADSTART_Pos (3U)
2945#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)
2946#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk
2947#define ADC_CR_ADSTP_Pos (4U)
2948#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
2949#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
2950#define ADC_CR_JADSTP_Pos (5U)
2951#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)
2952#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk
2953#define ADC_CR_BOOST_Pos (8U)
2954#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos)
2955#define ADC_CR_BOOST ADC_CR_BOOST_Msk
2956#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos)
2957#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos)
2958#define ADC_CR_ADCALLIN_Pos (16U)
2959#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos)
2960#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk
2961#define ADC_CR_LINCALRDYW1_Pos (22U)
2962#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos)
2963#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk
2964#define ADC_CR_LINCALRDYW2_Pos (23U)
2965#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos)
2966#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk
2967#define ADC_CR_LINCALRDYW3_Pos (24U)
2968#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos)
2969#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk
2970#define ADC_CR_LINCALRDYW4_Pos (25U)
2971#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos)
2972#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk
2973#define ADC_CR_LINCALRDYW5_Pos (26U)
2974#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos)
2975#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk
2976#define ADC_CR_LINCALRDYW6_Pos (27U)
2977#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos)
2978#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk
2979#define ADC_CR_ADVREGEN_Pos (28U)
2980#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)
2981#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
2982#define ADC_CR_DEEPPWD_Pos (29U)
2983#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)
2984#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk
2985#define ADC_CR_ADCALDIF_Pos (30U)
2986#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)
2987#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk
2988#define ADC_CR_ADCAL_Pos (31U)
2989#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
2990#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
2992/******************** Bit definition for ADC_CFGR register ********************/
2993#define ADC_CFGR_DMNGT_Pos (0U)
2994#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos)
2995#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk
2996#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos)
2997#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos)
2999#define ADC_CFGR_RES_Pos (2U)
3000#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos)
3001#define ADC_CFGR_RES ADC_CFGR_RES_Msk
3002#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)
3003#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)
3004#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos)
3006#define ADC_CFGR_EXTSEL_Pos (5U)
3007#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos)
3008#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk
3009#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos)
3010#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos)
3011#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos)
3012#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos)
3013#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos)
3015#define ADC_CFGR_EXTEN_Pos (10U)
3016#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)
3017#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk
3018#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)
3019#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)
3021#define ADC_CFGR_OVRMOD_Pos (12U)
3022#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)
3023#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk
3024#define ADC_CFGR_CONT_Pos (13U)
3025#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)
3026#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk
3027#define ADC_CFGR_AUTDLY_Pos (14U)
3028#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)
3029#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk
3031#define ADC_CFGR_DISCEN_Pos (16U)
3032#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)
3033#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk
3035#define ADC_CFGR_DISCNUM_Pos (17U)
3036#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)
3037#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk
3038#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)
3039#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)
3040#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)
3042#define ADC_CFGR_JDISCEN_Pos (20U)
3043#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)
3044#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk
3045#define ADC_CFGR_JQM_Pos (21U)
3046#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)
3047#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk
3048#define ADC_CFGR_AWD1SGL_Pos (22U)
3049#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)
3050#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk
3051#define ADC_CFGR_AWD1EN_Pos (23U)
3052#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)
3053#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk
3054#define ADC_CFGR_JAWD1EN_Pos (24U)
3055#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)
3056#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk
3057#define ADC_CFGR_JAUTO_Pos (25U)
3058#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)
3059#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk
3061#define ADC_CFGR_AWD1CH_Pos (26U)
3062#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)
3063#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk
3064#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)
3065#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)
3066#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)
3067#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)
3068#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)
3070#define ADC_CFGR_JQDIS_Pos (31U)
3071#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)
3072#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk
3074#define ADC3_CFGR_DMAEN_Pos (0U)
3075#define ADC3_CFGR_DMAEN_Msk (0x1UL << ADC3_CFGR_DMAEN_Pos)
3076#define ADC3_CFGR_DMAEN ADC3_CFGR_DMAEN_Msk
3077#define ADC3_CFGR_DMACFG_Pos (1U)
3078#define ADC3_CFGR_DMACFG_Msk (0x1UL << ADC3_CFGR_DMACFG_Pos)
3079#define ADC3_CFGR_DMACFG ADC3_CFGR_DMACFG_Msk
3081#define ADC3_CFGR_RES_Pos (3U)
3082#define ADC3_CFGR_RES_Msk (0x3UL << ADC3_CFGR_RES_Pos)
3083#define ADC3_CFGR_RES ADC3_CFGR_RES_Msk
3084#define ADC3_CFGR_RES_0 (0x1UL << ADC3_CFGR_RES_Pos)
3085#define ADC3_CFGR_RES_1 (0x2UL << ADC3_CFGR_RES_Pos)
3087#define ADC3_CFGR_ALIGN_Pos (15U)
3088#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos)
3089#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk
3090/******************** Bit definition for ADC_CFGR2 register ********************/
3091#define ADC_CFGR2_ROVSE_Pos (0U)
3092#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)
3093#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk
3094#define ADC_CFGR2_JOVSE_Pos (1U)
3095#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)
3096#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk
3098#define ADC_CFGR2_OVSS_Pos (5U)
3099#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)
3100#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk
3101#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)
3102#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)
3103#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)
3104#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)
3106#define ADC_CFGR2_TROVS_Pos (9U)
3107#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)
3108#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk
3109#define ADC_CFGR2_ROVSM_Pos (10U)
3110#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)
3111#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk
3113#define ADC_CFGR2_RSHIFT1_Pos (11U)
3114#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos)
3115#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk
3116#define ADC_CFGR2_RSHIFT2_Pos (12U)
3117#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos)
3118#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk
3119#define ADC_CFGR2_RSHIFT3_Pos (13U)
3120#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos)
3121#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk
3122#define ADC_CFGR2_RSHIFT4_Pos (14U)
3123#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos)
3124#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk
3126#define ADC_CFGR2_OVSR_Pos (16U)
3127#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos)
3128#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk
3129#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos)
3130#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos)
3131#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos)
3132#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos)
3133#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos)
3134#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos)
3135#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos)
3136#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos)
3137#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos)
3138#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos)
3140#define ADC_CFGR2_LSHIFT_Pos (28U)
3141#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos)
3142#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk
3143#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos)
3144#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos)
3145#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos)
3146#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos)
3148#define ADC3_CFGR2_OVSR_Pos (2U)
3149#define ADC3_CFGR2_OVSR_Msk (0x7UL << ADC3_CFGR2_OVSR_Pos)
3150#define ADC3_CFGR2_OVSR ADC3_CFGR2_OVSR_Msk
3151#define ADC3_CFGR2_OVSR_0 (0x1UL << ADC3_CFGR2_OVSR_Pos)
3152#define ADC3_CFGR2_OVSR_1 (0x2UL << ADC3_CFGR2_OVSR_Pos)
3153#define ADC3_CFGR2_OVSR_2 (0x4UL << ADC3_CFGR2_OVSR_Pos)
3155#define ADC3_CFGR2_SWTRIG_Pos (25U)
3156#define ADC3_CFGR2_SWTRIG_Msk (0x1UL << ADC3_CFGR2_SWTRIG_Pos)
3157#define ADC3_CFGR2_SWTRIG ADC3_CFGR2_SWTRIG_Msk
3158#define ADC3_CFGR2_BULB_Pos (26U)
3159#define ADC3_CFGR2_BULB_Msk (0x1UL << ADC3_CFGR2_BULB_Pos)
3160#define ADC3_CFGR2_BULB ADC3_CFGR2_BULB_Msk
3161#define ADC3_CFGR2_SMPTRIG_Pos (27U)
3162#define ADC3_CFGR2_SMPTRIG_Msk (0x1UL << ADC3_CFGR2_SMPTRIG_Pos)
3163#define ADC3_CFGR2_SMPTRIG ADC3_CFGR2_SMPTRIG_Msk
3164/******************** Bit definition for ADC_SMPR1 register ********************/
3165#define ADC_SMPR1_SMP0_Pos (0U)
3166#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)
3167#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk
3168#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)
3169#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)
3170#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)
3172#define ADC_SMPR1_SMP1_Pos (3U)
3173#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)
3174#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk
3175#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)
3176#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)
3177#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)
3179#define ADC_SMPR1_SMP2_Pos (6U)
3180#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)
3181#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk
3182#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)
3183#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)
3184#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)
3186#define ADC_SMPR1_SMP3_Pos (9U)
3187#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)
3188#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk
3189#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)
3190#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)
3191#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)
3193#define ADC_SMPR1_SMP4_Pos (12U)
3194#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)
3195#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk
3196#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)
3197#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)
3198#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)
3200#define ADC_SMPR1_SMP5_Pos (15U)
3201#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)
3202#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk
3203#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)
3204#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)
3205#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)
3207#define ADC_SMPR1_SMP6_Pos (18U)
3208#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)
3209#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk
3210#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)
3211#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)
3212#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)
3214#define ADC_SMPR1_SMP7_Pos (21U)
3215#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)
3216#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk
3217#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)
3218#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)
3219#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)
3221#define ADC_SMPR1_SMP8_Pos (24U)
3222#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)
3223#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk
3224#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)
3225#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)
3226#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)
3228#define ADC_SMPR1_SMP9_Pos (27U)
3229#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)
3230#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk
3231#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
3232#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)
3233#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)
3235/******************** Bit definition for ADC_SMPR2 register ********************/
3236#define ADC_SMPR2_SMP10_Pos (0U)
3237#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)
3238#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk
3239#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)
3240#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)
3241#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
3243#define ADC_SMPR2_SMP11_Pos (3U)
3244#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)
3245#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk
3246#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)
3247#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)
3248#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
3250#define ADC_SMPR2_SMP12_Pos (6U)
3251#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)
3252#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk
3253#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)
3254#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)
3255#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
3257#define ADC_SMPR2_SMP13_Pos (9U)
3258#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)
3259#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk
3260#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)
3261#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)
3262#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
3264#define ADC_SMPR2_SMP14_Pos (12U)
3265#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)
3266#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk
3267#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)
3268#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)
3269#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
3271#define ADC_SMPR2_SMP15_Pos (15U)
3272#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)
3273#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk
3274#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)
3275#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)
3276#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)
3278#define ADC_SMPR2_SMP16_Pos (18U)
3279#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)
3280#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk
3281#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)
3282#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)
3283#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
3285#define ADC_SMPR2_SMP17_Pos (21U)
3286#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)
3287#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk
3288#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)
3289#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)
3290#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
3292#define ADC_SMPR2_SMP18_Pos (24U)
3293#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)
3294#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk
3295#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)
3296#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)
3297#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
3299#define ADC_SMPR2_SMP19_Pos (27U)
3300#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos)
3301#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk
3302#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos)
3303#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos)
3304#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos)
3306/******************** Bit definition for ADC_PCSEL register ********************/
3307#define ADC_PCSEL_PCSEL_Pos (0U)
3308#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)
3309#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk
3310#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos)
3311#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos)
3312#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos)
3313#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos)
3314#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos)
3315#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos)
3316#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos)
3317#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos)
3318#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos)
3319#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos)
3320#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos)
3321#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos)
3322#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos)
3323#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos)
3324#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos)
3325#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos)
3326#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos)
3327#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos)
3328#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos)
3329#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos)
3331/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3332#define ADC_LTR_LT_Pos (0U)
3333#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos)
3334#define ADC_LTR_LT ADC_LTR_LT_Msk
3336/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3337#define ADC_HTR_HT_Pos (0U)
3338#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos)
3339#define ADC_HTR_HT ADC_HTR_HT_Msk
3341/******************** Bit definition for ADC3_TR1 register *******************/
3342#define ADC3_TR1_LT1_Pos (0U)
3343#define ADC3_TR1_LT1_Msk (0xFFFUL << ADC3_TR1_LT1_Pos)
3344#define ADC3_TR1_LT1 ADC3_TR1_LT1_Msk
3346#define ADC3_TR1_AWDFILT_Pos (12U)
3347#define ADC3_TR1_AWDFILT_Msk (0x7UL << ADC3_TR1_AWDFILT_Pos)
3348#define ADC3_TR1_AWDFILT ADC3_TR1_AWDFILT_Msk
3349#define ADC3_TR1_AWDFILT_0 (0x1UL << ADC3_TR1_AWDFILT_Pos)
3350#define ADC3_TR1_AWDFILT_1 (0x2UL << ADC3_TR1_AWDFILT_Pos)
3351#define ADC3_TR1_AWDFILT_2 (0x4UL << ADC3_TR1_AWDFILT_Pos)
3353#define ADC3_TR1_HT1_Pos (16U)
3354#define ADC3_TR1_HT1_Msk (0xFFFUL << ADC3_TR1_HT1_Pos)
3355#define ADC3_TR1_HT1 ADC3_TR1_HT1_Msk
3357/******************** Bit definition for ADC3_TR2 register *******************/
3358#define ADC3_TR2_LT2_Pos (0U)
3359#define ADC3_TR2_LT2_Msk (0xFFUL << ADC3_TR2_LT2_Pos)
3360#define ADC3_TR2_LT2 ADC3_TR2_LT2_Msk
3362#define ADC3_TR2_HT2_Pos (16U)
3363#define ADC3_TR2_HT2_Msk (0xFFUL << ADC3_TR2_HT2_Pos)
3364#define ADC3_TR2_HT2 ADC3_TR2_HT2_Msk
3366/******************** Bit definition for ADC3_TR3 register *******************/
3367#define ADC3_TR3_LT3_Pos (0U)
3368#define ADC3_TR3_LT3_Msk (0xFFUL << ADC3_TR3_LT3_Pos)
3369#define ADC3_TR3_LT3 ADC3_TR3_LT3_Msk
3371#define ADC3_TR3_HT3_Pos (16U)
3372#define ADC3_TR3_HT3_Msk (0xFFUL << ADC3_TR3_HT3_Pos)
3373#define ADC3_TR3_HT3 ADC3_TR3_HT3_Msk
3375/******************** Bit definition for ADC_SQR1 register ********************/
3376#define ADC_SQR1_L_Pos (0U)
3377#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
3378#define ADC_SQR1_L ADC_SQR1_L_Msk
3379#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
3380#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
3381#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
3382#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
3384#define ADC_SQR1_SQ1_Pos (6U)
3385#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)
3386#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk
3387#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)
3388#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)
3389#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)
3390#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)
3391#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
3393#define ADC_SQR1_SQ2_Pos (12U)
3394#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)
3395#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk
3396#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)
3397#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)
3398#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)
3399#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)
3400#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)
3402#define ADC_SQR1_SQ3_Pos (18U)
3403#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)
3404#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk
3405#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)
3406#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)
3407#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)
3408#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)
3409#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)
3411#define ADC_SQR1_SQ4_Pos (24U)
3412#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)
3413#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk
3414#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)
3415#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)
3416#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)
3417#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)
3418#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)
3420/******************** Bit definition for ADC_SQR2 register ********************/
3421#define ADC_SQR2_SQ5_Pos (0U)
3422#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)
3423#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk
3424#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)
3425#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)
3426#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)
3427#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)
3428#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)
3430#define ADC_SQR2_SQ6_Pos (6U)
3431#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)
3432#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk
3433#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)
3434#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)
3435#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)
3436#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)
3437#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)
3439#define ADC_SQR2_SQ7_Pos (12U)
3440#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
3441#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
3442#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
3443#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
3444#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
3445#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
3446#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
3448#define ADC_SQR2_SQ8_Pos (18U)
3449#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
3450#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
3451#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
3452#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
3453#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
3454#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
3455#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
3457#define ADC_SQR2_SQ9_Pos (24U)
3458#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
3459#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
3460#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
3461#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
3462#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
3463#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
3464#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
3466/******************** Bit definition for ADC_SQR3 register ********************/
3467#define ADC_SQR3_SQ10_Pos (0U)
3468#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)
3469#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk
3470#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)
3471#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)
3472#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)
3473#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)
3474#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)
3476#define ADC_SQR3_SQ11_Pos (6U)
3477#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)
3478#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk
3479#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)
3480#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)
3481#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)
3482#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)
3483#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)
3485#define ADC_SQR3_SQ12_Pos (12U)
3486#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)
3487#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk
3488#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)
3489#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)
3490#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)
3491#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)
3492#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)
3494#define ADC_SQR3_SQ13_Pos (18U)
3495#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)
3496#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk
3497#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)
3498#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)
3499#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)
3500#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)
3501#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)
3503#define ADC_SQR3_SQ14_Pos (24U)
3504#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)
3505#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk
3506#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)
3507#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)
3508#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)
3509#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)
3510#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)
3512/******************** Bit definition for ADC_SQR4 register ********************/
3513#define ADC_SQR4_SQ15_Pos (0U)
3514#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)
3515#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk
3516#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)
3517#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)
3518#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)
3519#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)
3520#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)
3522#define ADC_SQR4_SQ16_Pos (6U)
3523#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)
3524#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk
3525#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)
3526#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)
3527#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)
3528#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)
3529#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)
3530/******************** Bit definition for ADC_DR register ********************/
3531#define ADC_DR_RDATA_Pos (0U)
3532#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)
3533#define ADC_DR_RDATA ADC_DR_RDATA_Msk
3535/******************** Bit definition for ADC_JSQR register ********************/
3536#define ADC_JSQR_JL_Pos (0U)
3537#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
3538#define ADC_JSQR_JL ADC_JSQR_JL_Msk
3539#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
3540#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
3542#define ADC_JSQR_JEXTSEL_Pos (2U)
3543#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos)
3544#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk
3545#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos)
3546#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos)
3547#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos)
3548#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos)
3549#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos)
3551#define ADC_JSQR_JEXTEN_Pos (7U)
3552#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)
3553#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk
3554#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)
3555#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)
3557#define ADC_JSQR_JSQ1_Pos (9U)
3558#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
3559#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
3560#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
3561#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
3562#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
3563#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
3564#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
3566#define ADC_JSQR_JSQ2_Pos (15U)
3567#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
3568#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
3569#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
3570#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
3571#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
3572#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
3573#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
3575#define ADC_JSQR_JSQ3_Pos (21U)
3576#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
3577#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
3578#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
3579#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
3580#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
3581#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
3582#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
3584#define ADC_JSQR_JSQ4_Pos (27U)
3585#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
3586#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
3587#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
3588#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
3589#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
3590#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
3591#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
3593/******************** Bit definition for ADC_OFR1 register ********************/
3594#define ADC_OFR1_OFFSET1_Pos (0U)
3595#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos)
3596#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk
3597#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos)
3598#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos)
3599#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos)
3600#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos)
3601#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos)
3602#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos)
3603#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos)
3604#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos)
3605#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos)
3606#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos)
3607#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos)
3608#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos)
3609#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos)
3610#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos)
3611#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos)
3612#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos)
3613#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos)
3614#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos)
3615#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos)
3616#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos)
3617#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos)
3618#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos)
3619#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos)
3620#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos)
3621#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos)
3622#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos)
3624#define ADC_OFR1_OFFSET1_CH_Pos (26U)
3625#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
3626#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk
3627#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
3628#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
3629#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
3630#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
3631#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
3633#define ADC_OFR1_SSATE_Pos (31U)
3634#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos)
3635#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk
3637#define ADC3_OFR1_OFFSET1_Pos (0U)
3638#define ADC3_OFR1_OFFSET1_Msk (0xFFFUL << ADC3_OFR1_OFFSET1_Pos)
3639#define ADC3_OFR1_OFFSET1 ADC3_OFR1_OFFSET1_Msk
3641#define ADC3_OFR1_OFFSETPOS_Pos (24U)
3642#define ADC3_OFR1_OFFSETPOS_Msk (0x1UL << ADC3_OFR1_OFFSETPOS_Pos)
3643#define ADC3_OFR1_OFFSETPOS ADC3_OFR1_OFFSETPOS_Msk
3644#define ADC3_OFR1_SATEN_Pos (25U)
3645#define ADC3_OFR1_SATEN_Msk (0x1UL << ADC3_OFR1_SATEN_Pos)
3646#define ADC3_OFR1_SATEN ADC3_OFR1_SATEN_Msk
3648#define ADC3_OFR1_OFFSET1_EN_Pos (31U)
3649#define ADC3_OFR1_OFFSET1_EN_Msk (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos)
3650#define ADC3_OFR1_OFFSET1_EN ADC3_OFR1_OFFSET1_EN_Msk
3652/******************** Bit definition for ADC_OFR2 register ********************/
3653#define ADC_OFR2_OFFSET2_Pos (0U)
3654#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos)
3655#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk
3656#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos)
3657#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos)
3658#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos)
3659#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos)
3660#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos)
3661#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos)
3662#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos)
3663#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos)
3664#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos)
3665#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos)
3666#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos)
3667#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos)
3668#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos)
3669#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos)
3670#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos)
3671#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos)
3672#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos)
3673#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos)
3674#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos)
3675#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos)
3676#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos)
3677#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos)
3678#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos)
3679#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos)
3680#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos)
3681#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos)
3683#define ADC_OFR2_OFFSET2_CH_Pos (26U)
3684#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
3685#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk
3686#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
3687#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
3688#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
3689#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
3690#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
3692#define ADC_OFR2_SSATE_Pos (31U)
3693#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos)
3694#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk
3696#define ADC3_OFR2_OFFSET2_Pos (0U)
3697#define ADC3_OFR2_OFFSET2_Msk (0xFFFUL << ADC3_OFR2_OFFSET2_Pos)
3698#define ADC3_OFR2_OFFSET2 ADC3_OFR2_OFFSET2_Msk
3700#define ADC3_OFR2_OFFSETPOS_Pos (24U)
3701#define ADC3_OFR2_OFFSETPOS_Msk (0x1UL << ADC3_OFR2_OFFSETPOS_Pos)
3702#define ADC3_OFR2_OFFSETPOS ADC3_OFR2_OFFSETPOS_Msk
3703#define ADC3_OFR2_SATEN_Pos (25U)
3704#define ADC3_OFR2_SATEN_Msk (0x1UL << ADC3_OFR2_SATEN_Pos)
3705#define ADC3_OFR2_SATEN ADC3_OFR2_SATEN_Msk
3707#define ADC3_OFR2_OFFSET2_EN_Pos (31U)
3708#define ADC3_OFR2_OFFSET2_EN_Msk (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos)
3709#define ADC3_OFR2_OFFSET2_EN ADC3_OFR2_OFFSET2_EN_Msk
3711/******************** Bit definition for ADC_OFR3 register ********************/
3712#define ADC_OFR3_OFFSET3_Pos (0U)
3713#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos)
3714#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk
3715#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos)
3716#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos)
3717#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos)
3718#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos)
3719#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos)
3720#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos)
3721#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos)
3722#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos)
3723#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos)
3724#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos)
3725#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos)
3726#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos)
3727#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos)
3728#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos)
3729#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos)
3730#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos)
3731#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos)
3732#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos)
3733#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos)
3734#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos)
3735#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos)
3736#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos)
3737#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos)
3738#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos)
3739#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos)
3740#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos)
3742#define ADC_OFR3_OFFSET3_CH_Pos (26U)
3743#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
3744#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk
3745#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
3746#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
3747#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
3748#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
3749#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
3751#define ADC_OFR3_SSATE_Pos (31U)
3752#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos)
3753#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk
3755#define ADC3_OFR3_OFFSET3_Pos (0U)
3756#define ADC3_OFR3_OFFSET3_Msk (0xFFFUL << ADC3_OFR3_OFFSET3_Pos)
3757#define ADC3_OFR3_OFFSET3 ADC3_OFR3_OFFSET3_Msk
3759#define ADC3_OFR3_OFFSETPOS_Pos (24U)
3760#define ADC3_OFR3_OFFSETPOS_Msk (0x1UL << ADC3_OFR3_OFFSETPOS_Pos)
3761#define ADC3_OFR3_OFFSETPOS ADC3_OFR3_OFFSETPOS_Msk
3762#define ADC3_OFR3_SATEN_Pos (25U)
3763#define ADC3_OFR3_SATEN_Msk (0x1UL << ADC3_OFR3_SATEN_Pos)
3764#define ADC3_OFR3_SATEN ADC3_OFR3_SATEN_Msk
3766#define ADC3_OFR3_OFFSET3_EN_Pos (31U)
3767#define ADC3_OFR3_OFFSET3_EN_Msk (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos)
3768#define ADC3_OFR3_OFFSET3_EN ADC3_OFR3_OFFSET3_EN_Msk
3770/******************** Bit definition for ADC_OFR4 register ********************/
3771#define ADC_OFR4_OFFSET4_Pos (0U)
3772#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos)
3773#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk
3774#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos)
3775#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos)
3776#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos)
3777#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos)
3778#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos)
3779#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos)
3780#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos)
3781#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos)
3782#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos)
3783#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos)
3784#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos)
3785#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos)
3786#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos)
3787#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos)
3788#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos)
3789#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos)
3790#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos)
3791#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos)
3792#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos)
3793#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos)
3794#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos)
3795#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos)
3796#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos)
3797#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos)
3798#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos)
3799#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos)
3801#define ADC_OFR4_OFFSET4_CH_Pos (26U)
3802#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
3803#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk
3804#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
3805#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
3806#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
3807#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
3808#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
3810#define ADC_OFR4_SSATE_Pos (31U)
3811#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos)
3812#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk
3814#define ADC3_OFR4_OFFSET4_Pos (0U)
3815#define ADC3_OFR4_OFFSET4_Msk (0xFFFUL << ADC3_OFR4_OFFSET4_Pos)
3816#define ADC3_OFR4_OFFSET4 ADC3_OFR4_OFFSET4_Msk
3818#define ADC3_OFR4_OFFSETPOS_Pos (24U)
3819#define ADC3_OFR4_OFFSETPOS_Msk (0x1UL << ADC3_OFR4_OFFSETPOS_Pos)
3820#define ADC3_OFR4_OFFSETPOS ADC3_OFR4_OFFSETPOS_Msk
3821#define ADC3_OFR4_SATEN_Pos (25U)
3822#define ADC3_OFR4_SATEN_Msk (0x1UL << ADC3_OFR4_SATEN_Pos)
3823#define ADC3_OFR4_SATEN ADC3_OFR4_SATEN_Msk
3825#define ADC3_OFR4_OFFSET4_EN_Pos (31U)
3826#define ADC3_OFR4_OFFSET4_EN_Msk (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos)
3827#define ADC3_OFR4_OFFSET4_EN ADC3_OFR4_OFFSET4_EN_Msk
3829/******************** Bit definition for ADC_JDR1 register ********************/
3830#define ADC_JDR1_JDATA_Pos (0U)
3831#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)
3832#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
3833#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos)
3834#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos)
3835#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos)
3836#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos)
3837#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos)
3838#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos)
3839#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos)
3840#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos)
3841#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos)
3842#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos)
3843#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos)
3844#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos)
3845#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos)
3846#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos)
3847#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos)
3848#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos)
3849#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos)
3850#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos)
3851#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos)
3852#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos)
3853#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos)
3854#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos)
3855#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos)
3856#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos)
3857#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos)
3858#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos)
3859#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos)
3860#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos)
3861#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos)
3862#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos)
3863#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos)
3864#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos)
3866/******************** Bit definition for ADC_JDR2 register ********************/
3867#define ADC_JDR2_JDATA_Pos (0U)
3868#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)
3869#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
3870#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos)
3871#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos)
3872#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos)
3873#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos)
3874#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos)
3875#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos)
3876#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos)
3877#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos)
3878#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos)
3879#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos)
3880#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos)
3881#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos)
3882#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos)
3883#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos)
3884#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos)
3885#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos)
3886#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos)
3887#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos)
3888#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos)
3889#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos)
3890#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos)
3891#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos)
3892#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos)
3893#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos)
3894#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos)
3895#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos)
3896#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos)
3897#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos)
3898#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos)
3899#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos)
3900#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos)
3901#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos)
3903/******************** Bit definition for ADC_JDR3 register ********************/
3904#define ADC_JDR3_JDATA_Pos (0U)
3905#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)
3906#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
3907#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos)
3908#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos)
3909#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos)
3910#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos)
3911#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos)
3912#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos)
3913#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos)
3914#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos)
3915#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos)
3916#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos)
3917#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos)
3918#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos)
3919#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos)
3920#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos)
3921#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos)
3922#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos)
3923#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos)
3924#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos)
3925#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos)
3926#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos)
3927#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos)
3928#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos)
3929#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos)
3930#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos)
3931#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos)
3932#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos)
3933#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos)
3934#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos)
3935#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos)
3936#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos)
3937#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos)
3938#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos)
3940/******************** Bit definition for ADC_JDR4 register ********************/
3941#define ADC_JDR4_JDATA_Pos (0U)
3942#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)
3943#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
3944#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos)
3945#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos)
3946#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos)
3947#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos)
3948#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos)
3949#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos)
3950#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos)
3951#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos)
3952#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos)
3953#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos)
3954#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos)
3955#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos)
3956#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos)
3957#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos)
3958#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos)
3959#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos)
3960#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos)
3961#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos)
3962#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos)
3963#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos)
3964#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos)
3965#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos)
3966#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos)
3967#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos)
3968#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos)
3969#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos)
3970#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos)
3971#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos)
3972#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos)
3973#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos)
3974#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos)
3975#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos)
3977/******************** Bit definition for ADC_AWD2CR register ********************/
3978#define ADC_AWD2CR_AWD2CH_Pos (0U)
3979#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)
3980#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk
3981#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
3982#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
3983#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
3984#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
3985#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
3986#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
3987#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
3988#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
3989#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
3990#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
3991#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
3992#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
3993#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
3994#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
3995#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
3996#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
3997#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
3998#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
3999#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)
4000#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)
4002/******************** Bit definition for ADC_AWD3CR register ********************/
4003#define ADC_AWD3CR_AWD3CH_Pos (0U)
4004#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)
4005#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk
4006#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
4007#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
4008#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
4009#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
4010#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
4011#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
4012#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
4013#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
4014#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
4015#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
4016#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
4017#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
4018#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
4019#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
4020#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
4021#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
4022#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
4023#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
4024#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)
4025#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)
4027/******************** Bit definition for ADC_DIFSEL register ********************/
4028#define ADC_DIFSEL_DIFSEL_Pos (0U)
4029#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)
4030#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk
4031#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
4032#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
4033#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
4034#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
4035#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
4036#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
4037#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
4038#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
4039#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
4040#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
4041#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
4042#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
4043#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
4044#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
4045#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
4046#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
4047#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
4048#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
4049#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)
4050#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)
4052/******************** Bit definition for ADC_CALFACT register ********************/
4053#define ADC_CALFACT_CALFACT_S_Pos (0U)
4054#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos)
4055#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk
4056#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos)
4057#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos)
4058#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos)
4059#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos)
4060#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos)
4061#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos)
4062#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos)
4063#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos)
4064#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos)
4065#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos)
4066#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos)
4067#define ADC_CALFACT_CALFACT_D_Pos (16U)
4068#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos)
4069#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk
4070#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos)
4071#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos)
4072#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos)
4073#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos)
4074#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos)
4075#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos)
4076#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos)
4077#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos)
4078#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos)
4079#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos)
4080#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos)
4082/******************** Bit definition for ADC_CALFACT2 register ********************/
4083#define ADC_CALFACT2_LINCALFACT_Pos (0U)
4084#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos)
4085#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk
4086#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos)
4087#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos)
4088#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos)
4089#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos)
4090#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos)
4091#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos)
4092#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos)
4093#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos)
4094#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos)
4095#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos)
4096#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos)
4097#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos)
4098#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos)
4099#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos)
4100#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos)
4101#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos)
4102#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos)
4103#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos)
4104#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos)
4105#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos)
4106#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos)
4107#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos)
4108#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos)
4109#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos)
4110#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4111#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4112#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4113#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4114#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4115#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos)
4117/************************* ADC Common registers *****************************/
4118/******************** Bit definition for ADC_CSR register ********************/
4119#define ADC_CSR_ADRDY_MST_Pos (0U)
4120#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)
4121#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk
4122#define ADC_CSR_EOSMP_MST_Pos (1U)
4123#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)
4124#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk
4125#define ADC_CSR_EOC_MST_Pos (2U)
4126#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)
4127#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk
4128#define ADC_CSR_EOS_MST_Pos (3U)
4129#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)
4130#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk
4131#define ADC_CSR_OVR_MST_Pos (4U)
4132#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)
4133#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk
4134#define ADC_CSR_JEOC_MST_Pos (5U)
4135#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)
4136#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk
4137#define ADC_CSR_JEOS_MST_Pos (6U)
4138#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)
4139#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk
4140#define ADC_CSR_AWD1_MST_Pos (7U)
4141#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)
4142#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk
4143#define ADC_CSR_AWD2_MST_Pos (8U)
4144#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)
4145#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk
4146#define ADC_CSR_AWD3_MST_Pos (9U)
4147#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)
4148#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk
4149#define ADC_CSR_JQOVF_MST_Pos (10U)
4150#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)
4151#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk
4152#define ADC_CSR_ADRDY_SLV_Pos (16U)
4153#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)
4154#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk
4155#define ADC_CSR_EOSMP_SLV_Pos (17U)
4156#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)
4157#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk
4158#define ADC_CSR_EOC_SLV_Pos (18U)
4159#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)
4160#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk
4161#define ADC_CSR_EOS_SLV_Pos (19U)
4162#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)
4163#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk
4164#define ADC_CSR_OVR_SLV_Pos (20U)
4165#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)
4166#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk
4167#define ADC_CSR_JEOC_SLV_Pos (21U)
4168#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)
4169#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk
4170#define ADC_CSR_JEOS_SLV_Pos (22U)
4171#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)
4172#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk
4173#define ADC_CSR_AWD1_SLV_Pos (23U)
4174#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)
4175#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk
4176#define ADC_CSR_AWD2_SLV_Pos (24U)
4177#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)
4178#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk
4179#define ADC_CSR_AWD3_SLV_Pos (25U)
4180#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)
4181#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk
4182#define ADC_CSR_JQOVF_SLV_Pos (26U)
4183#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)
4184#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk
4186/******************** Bit definition for ADC_CCR register ********************/
4187#define ADC_CCR_DUAL_Pos (0U)
4188#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)
4189#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk
4190#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)
4191#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)
4192#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)
4193#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)
4194#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)
4196#define ADC_CCR_DELAY_Pos (8U)
4197#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
4198#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
4199#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
4200#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
4201#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
4202#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
4205#define ADC_CCR_DAMDF_Pos (14U)
4206#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos)
4207#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk
4208#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos)
4209#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos)
4211#define ADC_CCR_CKMODE_Pos (16U)
4212#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)
4213#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk
4214#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)
4215#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
4217#define ADC_CCR_PRESC_Pos (18U)
4218#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)
4219#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk
4220#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)
4221#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)
4222#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)
4223#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)
4225#define ADC_CCR_VREFEN_Pos (22U)
4226#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
4227#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
4228#define ADC_CCR_TSEN_Pos (23U)
4229#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
4230#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk
4231#define ADC_CCR_VBATEN_Pos (24U)
4232#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)
4233#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk
4235/******************** Bit definition for ADC_CDR register *******************/
4236#define ADC_CDR_RDATA_MST_Pos (0U)
4237#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)
4238#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk
4240#define ADC_CDR_RDATA_SLV_Pos (16U)
4241#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)
4242#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk
4244/******************** Bit definition for ADC_CDR2 register ******************/
4245#define ADC_CDR2_RDATA_ALT_Pos (0U)
4246#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos)
4247#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk
4250/******************************************************************************/
4251/* */
4252/* VREFBUF */
4253/* */
4254/******************************************************************************/
4255/******************* Bit definition for VREFBUF_CSR register ****************/
4256#define VREFBUF_CSR_ENVR_Pos (0U)
4257#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)
4258#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk
4259#define VREFBUF_CSR_HIZ_Pos (1U)
4260#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)
4261#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk
4262#define VREFBUF_CSR_VRR_Pos (3U)
4263#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)
4264#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk
4265#define VREFBUF_CSR_VRS_Pos (4U)
4266#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos)
4267#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk
4269#define VREFBUF_CSR_VRS_OUT1 (0U)
4270#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
4271#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)
4272#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk
4273#define VREFBUF_CSR_VRS_OUT3_Pos (5U)
4274#define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)
4275#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk
4276#define VREFBUF_CSR_VRS_OUT4_Pos (4U)
4277#define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)
4278#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk
4280/******************* Bit definition for VREFBUF_CCR register ****************/
4281#define VREFBUF_CCR_TRIM_Pos (0U)
4282#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)
4283#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk
4285/******************************************************************************/
4286/* */
4287/* Flexible Datarate Controller Area Network */
4288/* */
4289/******************************************************************************/
4291/***************** Bit definition for FDCAN_CREL register *******************/
4292#define FDCAN_CREL_DAY_Pos (0U)
4293#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos)
4294#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk
4295#define FDCAN_CREL_MON_Pos (8U)
4296#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos)
4297#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk
4298#define FDCAN_CREL_YEAR_Pos (16U)
4299#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos)
4300#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk
4301#define FDCAN_CREL_SUBSTEP_Pos (20U)
4302#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos)
4303#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk
4304#define FDCAN_CREL_STEP_Pos (24U)
4305#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos)
4306#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk
4307#define FDCAN_CREL_REL_Pos (28U)
4308#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos)
4309#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk
4311/***************** Bit definition for FDCAN_ENDN register *******************/
4312#define FDCAN_ENDN_ETV_Pos (0U)
4313#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)
4314#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk
4316/***************** Bit definition for FDCAN_DBTP register *******************/
4317#define FDCAN_DBTP_DSJW_Pos (0U)
4318#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos)
4319#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk
4320#define FDCAN_DBTP_DTSEG2_Pos (4U)
4321#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos)
4322#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk
4323#define FDCAN_DBTP_DTSEG1_Pos (8U)
4324#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)
4325#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk
4326#define FDCAN_DBTP_DBRP_Pos (16U)
4327#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos)
4328#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk
4329#define FDCAN_DBTP_TDC_Pos (23U)
4330#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos)
4331#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk
4333/***************** Bit definition for FDCAN_TEST register *******************/
4334#define FDCAN_TEST_LBCK_Pos (4U)
4335#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos)
4336#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk
4337#define FDCAN_TEST_TX_Pos (5U)
4338#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos)
4339#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk
4340#define FDCAN_TEST_RX_Pos (7U)
4341#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos)
4342#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk
4344/***************** Bit definition for FDCAN_RWD register ********************/
4345#define FDCAN_RWD_WDC_Pos (0U)
4346#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos)
4347#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk
4348#define FDCAN_RWD_WDV_Pos (8U)
4349#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos)
4350#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk
4352/***************** Bit definition for FDCAN_CCCR register ********************/
4353#define FDCAN_CCCR_INIT_Pos (0U)
4354#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos)
4355#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk
4356#define FDCAN_CCCR_CCE_Pos (1U)
4357#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos)
4358#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk
4359#define FDCAN_CCCR_ASM_Pos (2U)
4360#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos)
4361#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk
4362#define FDCAN_CCCR_CSA_Pos (3U)
4363#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos)
4364#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk
4365#define FDCAN_CCCR_CSR_Pos (4U)
4366#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos)
4367#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk
4368#define FDCAN_CCCR_MON_Pos (5U)
4369#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos)
4370#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk
4371#define FDCAN_CCCR_DAR_Pos (6U)
4372#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos)
4373#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk
4374#define FDCAN_CCCR_TEST_Pos (7U)
4375#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos)
4376#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk
4377#define FDCAN_CCCR_FDOE_Pos (8U)
4378#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos)
4379#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk
4380#define FDCAN_CCCR_BRSE_Pos (9U)
4381#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos)
4382#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk
4383#define FDCAN_CCCR_PXHD_Pos (12U)
4384#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos)
4385#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk
4386#define FDCAN_CCCR_EFBI_Pos (13U)
4387#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos)
4388#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk
4389#define FDCAN_CCCR_TXP_Pos (14U)
4390#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos)
4391#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk
4392#define FDCAN_CCCR_NISO_Pos (15U)
4393#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos)
4394#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk
4396/***************** Bit definition for FDCAN_NBTP register ********************/
4397#define FDCAN_NBTP_NTSEG2_Pos (0U)
4398#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)
4399#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk
4400#define FDCAN_NBTP_NTSEG1_Pos (8U)
4401#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)
4402#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk
4403#define FDCAN_NBTP_NBRP_Pos (16U)
4404#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos)
4405#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk
4406#define FDCAN_NBTP_NSJW_Pos (25U)
4407#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos)
4408#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk
4410/***************** Bit definition for FDCAN_TSCC register ********************/
4411#define FDCAN_TSCC_TSS_Pos (0U)
4412#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos)
4413#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk
4414#define FDCAN_TSCC_TCP_Pos (16U)
4415#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos)
4416#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk
4418/***************** Bit definition for FDCAN_TSCV register ********************/
4419#define FDCAN_TSCV_TSC_Pos (0U)
4420#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos)
4421#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk
4423/***************** Bit definition for FDCAN_TOCC register ********************/
4424#define FDCAN_TOCC_ETOC_Pos (0U)
4425#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos)
4426#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk
4427#define FDCAN_TOCC_TOS_Pos (1U)
4428#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos)
4429#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk
4430#define FDCAN_TOCC_TOP_Pos (16U)
4431#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos)
4432#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk
4434/***************** Bit definition for FDCAN_TOCV register ********************/
4435#define FDCAN_TOCV_TOC_Pos (0U)
4436#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos)
4437#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk
4439/***************** Bit definition for FDCAN_ECR register *********************/
4440#define FDCAN_ECR_TEC_Pos (0U)
4441#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos)
4442#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk
4443#define FDCAN_ECR_REC_Pos (8U)
4444#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos)
4445#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk
4446#define FDCAN_ECR_RP_Pos (15U)
4447#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos)
4448#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk
4449#define FDCAN_ECR_CEL_Pos (16U)
4450#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos)
4451#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk
4453/***************** Bit definition for FDCAN_PSR register *********************/
4454#define FDCAN_PSR_LEC_Pos (0U)
4455#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos)
4456#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk
4457#define FDCAN_PSR_ACT_Pos (3U)
4458#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos)
4459#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk
4460#define FDCAN_PSR_EP_Pos (5U)
4461#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos)
4462#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk
4463#define FDCAN_PSR_EW_Pos (6U)
4464#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos)
4465#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk
4466#define FDCAN_PSR_BO_Pos (7U)
4467#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos)
4468#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk
4469#define FDCAN_PSR_DLEC_Pos (8U)
4470#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos)
4471#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk
4472#define FDCAN_PSR_RESI_Pos (11U)
4473#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos)
4474#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk
4475#define FDCAN_PSR_RBRS_Pos (12U)
4476#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos)
4477#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk
4478#define FDCAN_PSR_REDL_Pos (13U)
4479#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos)
4480#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk
4481#define FDCAN_PSR_PXE_Pos (14U)
4482#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos)
4483#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk
4484#define FDCAN_PSR_TDCV_Pos (16U)
4485#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos)
4486#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk
4488/***************** Bit definition for FDCAN_TDCR register ********************/
4489#define FDCAN_TDCR_TDCF_Pos (0U)
4490#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos)
4491#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk
4492#define FDCAN_TDCR_TDCO_Pos (8U)
4493#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos)
4494#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk
4496/***************** Bit definition for FDCAN_IR register **********************/
4497#define FDCAN_IR_RF0N_Pos (0U)
4498#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos)
4499#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk
4500#define FDCAN_IR_RF0W_Pos (1U)
4501#define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos)
4502#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk
4503#define FDCAN_IR_RF0F_Pos (2U)
4504#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos)
4505#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk
4506#define FDCAN_IR_RF0L_Pos (3U)
4507#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos)
4508#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk
4509#define FDCAN_IR_RF1N_Pos (4U)
4510#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos)
4511#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk
4512#define FDCAN_IR_RF1W_Pos (5U)
4513#define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos)
4514#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk
4515#define FDCAN_IR_RF1F_Pos (6U)
4516#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos)
4517#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk
4518#define FDCAN_IR_RF1L_Pos (7U)
4519#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos)
4520#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk
4521#define FDCAN_IR_HPM_Pos (8U)
4522#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos)
4523#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk
4524#define FDCAN_IR_TC_Pos (9U)
4525#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos)
4526#define FDCAN_IR_TC FDCAN_IR_TC_Msk
4527#define FDCAN_IR_TCF_Pos (10U)
4528#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos)
4529#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk
4530#define FDCAN_IR_TFE_Pos (11U)
4531#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos)
4532#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk
4533#define FDCAN_IR_TEFN_Pos (12U)
4534#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos)
4535#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk
4536#define FDCAN_IR_TEFW_Pos (13U)
4537#define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos)
4538#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk
4539#define FDCAN_IR_TEFF_Pos (14U)
4540#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos)
4541#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk
4542#define FDCAN_IR_TEFL_Pos (15U)
4543#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos)
4544#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk
4545#define FDCAN_IR_TSW_Pos (16U)
4546#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos)
4547#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk
4548#define FDCAN_IR_MRAF_Pos (17U)
4549#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos)
4550#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk
4551#define FDCAN_IR_TOO_Pos (18U)
4552#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos)
4553#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk
4554#define FDCAN_IR_DRX_Pos (19U)
4555#define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos)
4556#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk
4557#define FDCAN_IR_ELO_Pos (22U)
4558#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos)
4559#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk
4560#define FDCAN_IR_EP_Pos (23U)
4561#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos)
4562#define FDCAN_IR_EP FDCAN_IR_EP_Msk
4563#define FDCAN_IR_EW_Pos (24U)
4564#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos)
4565#define FDCAN_IR_EW FDCAN_IR_EW_Msk
4566#define FDCAN_IR_BO_Pos (25U)
4567#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos)
4568#define FDCAN_IR_BO FDCAN_IR_BO_Msk
4569#define FDCAN_IR_WDI_Pos (26U)
4570#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos)
4571#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk
4572#define FDCAN_IR_PEA_Pos (27U)
4573#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos)
4574#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk
4575#define FDCAN_IR_PED_Pos (28U)
4576#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos)
4577#define FDCAN_IR_PED FDCAN_IR_PED_Msk
4578#define FDCAN_IR_ARA_Pos (29U)
4579#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos)
4580#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk
4582/***************** Bit definition for FDCAN_IE register **********************/
4583#define FDCAN_IE_RF0NE_Pos (0U)
4584#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos)
4585#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk
4586#define FDCAN_IE_RF0WE_Pos (1U)
4587#define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos)
4588#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk
4589#define FDCAN_IE_RF0FE_Pos (2U)
4590#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos)
4591#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk
4592#define FDCAN_IE_RF0LE_Pos (3U)
4593#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos)
4594#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk
4595#define FDCAN_IE_RF1NE_Pos (4U)
4596#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos)
4597#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk
4598#define FDCAN_IE_RF1WE_Pos (5U)
4599#define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos)
4600#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk
4601#define FDCAN_IE_RF1FE_Pos (6U)
4602#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos)
4603#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk
4604#define FDCAN_IE_RF1LE_Pos (7U)
4605#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos)
4606#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk
4607#define FDCAN_IE_HPME_Pos (8U)
4608#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos)
4609#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk
4610#define FDCAN_IE_TCE_Pos (9U)
4611#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos)
4612#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk
4613#define FDCAN_IE_TCFE_Pos (10U)
4614#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos)
4615#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk
4616#define FDCAN_IE_TFEE_Pos (11U)
4617#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos)
4618#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk
4619#define FDCAN_IE_TEFNE_Pos (12U)
4620#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos)
4621#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk
4622#define FDCAN_IE_TEFWE_Pos (13U)
4623#define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos)
4624#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk
4625#define FDCAN_IE_TEFFE_Pos (14U)
4626#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos)
4627#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk
4628#define FDCAN_IE_TEFLE_Pos (15U)
4629#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos)
4630#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk
4631#define FDCAN_IE_TSWE_Pos (16U)
4632#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos)
4633#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk
4634#define FDCAN_IE_MRAFE_Pos (17U)
4635#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos)
4636#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk
4637#define FDCAN_IE_TOOE_Pos (18U)
4638#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos)
4639#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk
4640#define FDCAN_IE_DRXE_Pos (19U)
4641#define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos)
4642#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk
4643#define FDCAN_IE_BECE_Pos (20U)
4644#define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos)
4645#define FDCAN_IE_BECE FDCAN_IE_BECE_Msk
4646#define FDCAN_IE_BEUE_Pos (21U)
4647#define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos)
4648#define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk
4649#define FDCAN_IE_ELOE_Pos (22U)
4650#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos)
4651#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk
4652#define FDCAN_IE_EPE_Pos (23U)
4653#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos)
4654#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk
4655#define FDCAN_IE_EWE_Pos (24U)
4656#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos)
4657#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk
4658#define FDCAN_IE_BOE_Pos (25U)
4659#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos)
4660#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk
4661#define FDCAN_IE_WDIE_Pos (26U)
4662#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos)
4663#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk
4664#define FDCAN_IE_PEAE_Pos (27U)
4665#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos)
4666#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk
4667#define FDCAN_IE_PEDE_Pos (28U)
4668#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos)
4669#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk
4670#define FDCAN_IE_ARAE_Pos (29U)
4671#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos)
4672#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk
4674/***************** Bit definition for FDCAN_ILS register **********************/
4675#define FDCAN_ILS_RF0NL_Pos (0U)
4676#define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos)
4677#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk
4678#define FDCAN_ILS_RF0WL_Pos (1U)
4679#define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos)
4680#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk
4681#define FDCAN_ILS_RF0FL_Pos (2U)
4682#define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos)
4683#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk
4684#define FDCAN_ILS_RF0LL_Pos (3U)
4685#define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos)
4686#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk
4687#define FDCAN_ILS_RF1NL_Pos (4U)
4688#define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos)
4689#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk
4690#define FDCAN_ILS_RF1WL_Pos (5U)
4691#define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos)
4692#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk
4693#define FDCAN_ILS_RF1FL_Pos (6U)
4694#define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos)
4695#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk
4696#define FDCAN_ILS_RF1LL_Pos (7U)
4697#define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos)
4698#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk
4699#define FDCAN_ILS_HPML_Pos (8U)
4700#define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos)
4701#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk
4702#define FDCAN_ILS_TCL_Pos (9U)
4703#define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos)
4704#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk
4705#define FDCAN_ILS_TCFL_Pos (10U)
4706#define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos)
4707#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk
4708#define FDCAN_ILS_TFEL_Pos (11U)
4709#define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos)
4710#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk
4711#define FDCAN_ILS_TEFNL_Pos (12U)
4712#define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos)
4713#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk
4714#define FDCAN_ILS_TEFWL_Pos (13U)
4715#define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos)
4716#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk
4717#define FDCAN_ILS_TEFFL_Pos (14U)
4718#define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos)
4719#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk
4720#define FDCAN_ILS_TEFLL_Pos (15U)
4721#define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos)
4722#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk
4723#define FDCAN_ILS_TSWL_Pos (16U)
4724#define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos)
4725#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk
4726#define FDCAN_ILS_MRAFE_Pos (17U)
4727#define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos)
4728#define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk
4729#define FDCAN_ILS_TOOE_Pos (18U)
4730#define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos)
4731#define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk
4732#define FDCAN_ILS_DRXE_Pos (19U)
4733#define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos)
4734#define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk
4735#define FDCAN_ILS_BECE_Pos (20U)
4736#define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos)
4737#define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk
4738#define FDCAN_ILS_BEUE_Pos (21U)
4739#define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos)
4740#define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk
4741#define FDCAN_ILS_ELOE_Pos (22U)
4742#define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos)
4743#define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk
4744#define FDCAN_ILS_EPE_Pos (23U)
4745#define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos)
4746#define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk
4747#define FDCAN_ILS_EWE_Pos (24U)
4748#define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos)
4749#define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk
4750#define FDCAN_ILS_BOE_Pos (25U)
4751#define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos)
4752#define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk
4753#define FDCAN_ILS_WDIE_Pos (26U)
4754#define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos)
4755#define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk
4756#define FDCAN_ILS_PEAE_Pos (27U)
4757#define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos)
4758#define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk
4759#define FDCAN_ILS_PEDE_Pos (28U)
4760#define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos)
4761#define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk
4762#define FDCAN_ILS_ARAE_Pos (29U)
4763#define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos)
4764#define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk
4766/***************** Bit definition for FDCAN_ILE register **********************/
4767#define FDCAN_ILE_EINT0_Pos (0U)
4768#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos)
4769#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk
4770#define FDCAN_ILE_EINT1_Pos (1U)
4771#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos)
4772#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk
4774/***************** Bit definition for FDCAN_GFC register **********************/
4775#define FDCAN_GFC_RRFE_Pos (0U)
4776#define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos)
4777#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk
4778#define FDCAN_GFC_RRFS_Pos (1U)
4779#define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos)
4780#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk
4781#define FDCAN_GFC_ANFE_Pos (2U)
4782#define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos)
4783#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk
4784#define FDCAN_GFC_ANFS_Pos (4U)
4785#define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos)
4786#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk
4788/***************** Bit definition for FDCAN_SIDFC register ********************/
4789#define FDCAN_SIDFC_FLSSA_Pos (2U)
4790#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)
4791#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk
4792#define FDCAN_SIDFC_LSS_Pos (16U)
4793#define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos)
4794#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk
4796/***************** Bit definition for FDCAN_XIDFC register ********************/
4797#define FDCAN_XIDFC_FLESA_Pos (2U)
4798#define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)
4799#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk
4800#define FDCAN_XIDFC_LSE_Pos (16U)
4801#define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos)
4802#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk
4804/***************** Bit definition for FDCAN_XIDAM register ********************/
4805#define FDCAN_XIDAM_EIDM_Pos (0U)
4806#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)
4807#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk
4809/***************** Bit definition for FDCAN_HPMS register *********************/
4810#define FDCAN_HPMS_BIDX_Pos (0U)
4811#define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos)
4812#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk
4813#define FDCAN_HPMS_MSI_Pos (6U)
4814#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos)
4815#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk
4816#define FDCAN_HPMS_FIDX_Pos (8U)
4817#define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos)
4818#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk
4819#define FDCAN_HPMS_FLST_Pos (15U)
4820#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos)
4821#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk
4823/***************** Bit definition for FDCAN_NDAT1 register ********************/
4824#define FDCAN_NDAT1_ND0_Pos (0U)
4825#define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos)
4826#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk
4827#define FDCAN_NDAT1_ND1_Pos (1U)
4828#define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos)
4829#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk
4830#define FDCAN_NDAT1_ND2_Pos (2U)
4831#define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos)
4832#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk
4833#define FDCAN_NDAT1_ND3_Pos (3U)
4834#define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos)
4835#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk
4836#define FDCAN_NDAT1_ND4_Pos (4U)
4837#define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos)
4838#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk
4839#define FDCAN_NDAT1_ND5_Pos (5U)
4840#define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos)
4841#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk
4842#define FDCAN_NDAT1_ND6_Pos (6U)
4843#define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos)
4844#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk
4845#define FDCAN_NDAT1_ND7_Pos (7U)
4846#define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos)
4847#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk
4848#define FDCAN_NDAT1_ND8_Pos (8U)
4849#define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos)
4850#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk
4851#define FDCAN_NDAT1_ND9_Pos (9U)
4852#define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos)
4853#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk
4854#define FDCAN_NDAT1_ND10_Pos (10U)
4855#define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos)
4856#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk
4857#define FDCAN_NDAT1_ND11_Pos (11U)
4858#define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos)
4859#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk
4860#define FDCAN_NDAT1_ND12_Pos (12U)
4861#define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos)
4862#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk
4863#define FDCAN_NDAT1_ND13_Pos (13U)
4864#define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos)
4865#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk
4866#define FDCAN_NDAT1_ND14_Pos (14U)
4867#define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos)
4868#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk
4869#define FDCAN_NDAT1_ND15_Pos (15U)
4870#define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos)
4871#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk
4872#define FDCAN_NDAT1_ND16_Pos (16U)
4873#define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos)
4874#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk
4875#define FDCAN_NDAT1_ND17_Pos (17U)
4876#define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos)
4877#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk
4878#define FDCAN_NDAT1_ND18_Pos (18U)
4879#define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos)
4880#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk
4881#define FDCAN_NDAT1_ND19_Pos (19U)
4882#define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos)
4883#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk
4884#define FDCAN_NDAT1_ND20_Pos (20U)
4885#define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos)
4886#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk
4887#define FDCAN_NDAT1_ND21_Pos (21U)
4888#define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos)
4889#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk
4890#define FDCAN_NDAT1_ND22_Pos (22U)
4891#define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos)
4892#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk
4893#define FDCAN_NDAT1_ND23_Pos (23U)
4894#define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos)
4895#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk
4896#define FDCAN_NDAT1_ND24_Pos (24U)
4897#define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos)
4898#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk
4899#define FDCAN_NDAT1_ND25_Pos (25U)
4900#define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos)
4901#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk
4902#define FDCAN_NDAT1_ND26_Pos (26U)
4903#define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos)
4904#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk
4905#define FDCAN_NDAT1_ND27_Pos (27U)
4906#define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos)
4907#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk
4908#define FDCAN_NDAT1_ND28_Pos (28U)
4909#define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos)
4910#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk
4911#define FDCAN_NDAT1_ND29_Pos (29U)
4912#define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos)
4913#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk
4914#define FDCAN_NDAT1_ND30_Pos (30U)
4915#define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos)
4916#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk
4917#define FDCAN_NDAT1_ND31_Pos (31U)
4918#define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos)
4919#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk
4921/***************** Bit definition for FDCAN_NDAT2 register ********************/
4922#define FDCAN_NDAT2_ND32_Pos (0U)
4923#define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos)
4924#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk
4925#define FDCAN_NDAT2_ND33_Pos (1U)
4926#define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos)
4927#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk
4928#define FDCAN_NDAT2_ND34_Pos (2U)
4929#define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos)
4930#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk
4931#define FDCAN_NDAT2_ND35_Pos (3U)
4932#define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos)
4933#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk
4934#define FDCAN_NDAT2_ND36_Pos (4U)
4935#define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos)
4936#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk
4937#define FDCAN_NDAT2_ND37_Pos (5U)
4938#define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos)
4939#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk
4940#define FDCAN_NDAT2_ND38_Pos (6U)
4941#define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos)
4942#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk
4943#define FDCAN_NDAT2_ND39_Pos (7U)
4944#define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos)
4945#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk
4946#define FDCAN_NDAT2_ND40_Pos (8U)
4947#define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos)
4948#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk
4949#define FDCAN_NDAT2_ND41_Pos (9U)
4950#define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos)
4951#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk
4952#define FDCAN_NDAT2_ND42_Pos (10U)
4953#define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos)
4954#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk
4955#define FDCAN_NDAT2_ND43_Pos (11U)
4956#define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos)
4957#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk
4958#define FDCAN_NDAT2_ND44_Pos (12U)
4959#define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos)
4960#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk
4961#define FDCAN_NDAT2_ND45_Pos (13U)
4962#define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos)
4963#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk
4964#define FDCAN_NDAT2_ND46_Pos (14U)
4965#define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos)
4966#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk
4967#define FDCAN_NDAT2_ND47_Pos (15U)
4968#define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos)
4969#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk
4970#define FDCAN_NDAT2_ND48_Pos (16U)
4971#define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos)
4972#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk
4973#define FDCAN_NDAT2_ND49_Pos (17U)
4974#define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos)
4975#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk
4976#define FDCAN_NDAT2_ND50_Pos (18U)
4977#define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos)
4978#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk
4979#define FDCAN_NDAT2_ND51_Pos (19U)
4980#define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos)
4981#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk
4982#define FDCAN_NDAT2_ND52_Pos (20U)
4983#define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos)
4984#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk
4985#define FDCAN_NDAT2_ND53_Pos (21U)
4986#define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos)
4987#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk
4988#define FDCAN_NDAT2_ND54_Pos (22U)
4989#define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos)
4990#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk
4991#define FDCAN_NDAT2_ND55_Pos (23U)
4992#define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos)
4993#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk
4994#define FDCAN_NDAT2_ND56_Pos (24U)
4995#define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos)
4996#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk
4997#define FDCAN_NDAT2_ND57_Pos (25U)
4998#define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos)
4999#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk
5000#define FDCAN_NDAT2_ND58_Pos (26U)
5001#define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos)
5002#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk
5003#define FDCAN_NDAT2_ND59_Pos (27U)
5004#define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos)
5005#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk
5006#define FDCAN_NDAT2_ND60_Pos (28U)
5007#define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos)
5008#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk
5009#define FDCAN_NDAT2_ND61_Pos (29U)
5010#define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos)
5011#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk
5012#define FDCAN_NDAT2_ND62_Pos (30U)
5013#define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos)
5014#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk
5015#define FDCAN_NDAT2_ND63_Pos (31U)
5016#define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos)
5017#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk
5019/***************** Bit definition for FDCAN_RXF0C register ********************/
5020#define FDCAN_RXF0C_F0SA_Pos (2U)
5021#define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)
5022#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk
5023#define FDCAN_RXF0C_F0S_Pos (16U)
5024#define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos)
5025#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk
5026#define FDCAN_RXF0C_F0WM_Pos (24U)
5027#define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos)
5028#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk
5029#define FDCAN_RXF0C_F0OM_Pos (31U)
5030#define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos)
5031#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk
5033/***************** Bit definition for FDCAN_RXF0S register ********************/
5034#define FDCAN_RXF0S_F0FL_Pos (0U)
5035#define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos)
5036#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk
5037#define FDCAN_RXF0S_F0GI_Pos (8U)
5038#define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos)
5039#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk
5040#define FDCAN_RXF0S_F0PI_Pos (16U)
5041#define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos)
5042#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk
5043#define FDCAN_RXF0S_F0F_Pos (24U)
5044#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos)
5045#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk
5046#define FDCAN_RXF0S_RF0L_Pos (25U)
5047#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos)
5048#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk
5050/***************** Bit definition for FDCAN_RXF0A register ********************/
5051#define FDCAN_RXF0A_F0AI_Pos (0U)
5052#define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos)
5053#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk
5055/***************** Bit definition for FDCAN_RXBC register ********************/
5056#define FDCAN_RXBC_RBSA_Pos (2U)
5057#define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)
5058#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk
5060/***************** Bit definition for FDCAN_RXF1C register ********************/
5061#define FDCAN_RXF1C_F1SA_Pos (2U)
5062#define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)
5063#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk
5064#define FDCAN_RXF1C_F1S_Pos (16U)
5065#define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos)
5066#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk
5067#define FDCAN_RXF1C_F1WM_Pos (24U)
5068#define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos)
5069#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk
5070#define FDCAN_RXF1C_F1OM_Pos (31U)
5071#define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos)
5072#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk
5074/***************** Bit definition for FDCAN_RXF1S register ********************/
5075#define FDCAN_RXF1S_F1FL_Pos (0U)
5076#define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos)
5077#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk
5078#define FDCAN_RXF1S_F1GI_Pos (8U)
5079#define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos)
5080#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk
5081#define FDCAN_RXF1S_F1PI_Pos (16U)
5082#define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos)
5083#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk
5084#define FDCAN_RXF1S_F1F_Pos (24U)
5085#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos)
5086#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk
5087#define FDCAN_RXF1S_RF1L_Pos (25U)
5088#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos)
5089#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk
5091/***************** Bit definition for FDCAN_RXF1A register ********************/
5092#define FDCAN_RXF1A_F1AI_Pos (0U)
5093#define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos)
5094#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk
5096/***************** Bit definition for FDCAN_RXESC register ********************/
5097#define FDCAN_RXESC_F0DS_Pos (0U)
5098#define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos)
5099#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk
5100#define FDCAN_RXESC_F1DS_Pos (4U)
5101#define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos)
5102#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk
5103#define FDCAN_RXESC_RBDS_Pos (8U)
5104#define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos)
5105#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk
5107/***************** Bit definition for FDCAN_TXBC register *********************/
5108#define FDCAN_TXBC_TBSA_Pos (2U)
5109#define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)
5110#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk
5111#define FDCAN_TXBC_NDTB_Pos (16U)
5112#define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos)
5113#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk
5114#define FDCAN_TXBC_TFQS_Pos (24U)
5115#define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos)
5116#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk
5117#define FDCAN_TXBC_TFQM_Pos (30U)
5118#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos)
5119#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk
5121/***************** Bit definition for FDCAN_TXFQS register *********************/
5122#define FDCAN_TXFQS_TFFL_Pos (0U)
5123#define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos)
5124#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk
5125#define FDCAN_TXFQS_TFGI_Pos (8U)
5126#define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos)
5127#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk
5128#define FDCAN_TXFQS_TFQPI_Pos (16U)
5129#define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)
5130#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk
5131#define FDCAN_TXFQS_TFQF_Pos (21U)
5132#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos)
5133#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk
5135/***************** Bit definition for FDCAN_TXESC register *********************/
5136#define FDCAN_TXESC_TBDS_Pos (0U)
5137#define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos)
5138#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk
5140/***************** Bit definition for FDCAN_TXBRP register *********************/
5141#define FDCAN_TXBRP_TRP_Pos (0U)
5142#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)
5143#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk
5145/***************** Bit definition for FDCAN_TXBAR register *********************/
5146#define FDCAN_TXBAR_AR_Pos (0U)
5147#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)
5148#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk
5150/***************** Bit definition for FDCAN_TXBCR register *********************/
5151#define FDCAN_TXBCR_CR_Pos (0U)
5152#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)
5153#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk
5155/***************** Bit definition for FDCAN_TXBTO register *********************/
5156#define FDCAN_TXBTO_TO_Pos (0U)
5157#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)
5158#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk
5160/***************** Bit definition for FDCAN_TXBCF register *********************/
5161#define FDCAN_TXBCF_CF_Pos (0U)
5162#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)
5163#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk
5165/***************** Bit definition for FDCAN_TXBTIE register ********************/
5166#define FDCAN_TXBTIE_TIE_Pos (0U)
5167#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)
5168#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk
5170/***************** Bit definition for FDCAN_ TXBCIE register *******************/
5171#define FDCAN_TXBCIE_CFIE_Pos (0U)
5172#define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)
5173#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk
5175/***************** Bit definition for FDCAN_TXEFC register *********************/
5176#define FDCAN_TXEFC_EFSA_Pos (2U)
5177#define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)
5178#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk
5179#define FDCAN_TXEFC_EFS_Pos (16U)
5180#define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos)
5181#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk
5182#define FDCAN_TXEFC_EFWM_Pos (24U)
5183#define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos)
5184#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk
5186/***************** Bit definition for FDCAN_TXEFS register *********************/
5187#define FDCAN_TXEFS_EFFL_Pos (0U)
5188#define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos)
5189#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk
5190#define FDCAN_TXEFS_EFGI_Pos (8U)
5191#define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos)
5192#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk
5193#define FDCAN_TXEFS_EFPI_Pos (16U)
5194#define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos)
5195#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk
5196#define FDCAN_TXEFS_EFF_Pos (24U)
5197#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos)
5198#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk
5199#define FDCAN_TXEFS_TEFL_Pos (25U)
5200#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos)
5201#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk
5203/***************** Bit definition for FDCAN_TXEFA register *********************/
5204#define FDCAN_TXEFA_EFAI_Pos (0U)
5205#define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos)
5206#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk
5208/***************** Bit definition for FDCAN_TTTMC register *********************/
5209#define FDCAN_TTTMC_TMSA_Pos (2U)
5210#define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)
5211#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk
5212#define FDCAN_TTTMC_TME_Pos (16U)
5213#define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos)
5214#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk
5216/***************** Bit definition for FDCAN_TTRMC register *********************/
5217#define FDCAN_TTRMC_RID_Pos (0U)
5218#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)
5219#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk
5220#define FDCAN_TTRMC_XTD_Pos (30U)
5221#define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos)
5222#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk
5223#define FDCAN_TTRMC_RMPS_Pos (31U)
5224#define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos)
5225#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk
5227/***************** Bit definition for FDCAN_TTOCF register *********************/
5228#define FDCAN_TTOCF_OM_Pos (0U)
5229#define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos)
5230#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk
5231#define FDCAN_TTOCF_GEN_Pos (3U)
5232#define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos)
5233#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk
5234#define FDCAN_TTOCF_TM_Pos (4U)
5235#define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos)
5236#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk
5237#define FDCAN_TTOCF_LDSDL_Pos (5U)
5238#define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos)
5239#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk
5240#define FDCAN_TTOCF_IRTO_Pos (8U)
5241#define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos)
5242#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk
5243#define FDCAN_TTOCF_EECS_Pos (15U)
5244#define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos)
5245#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk
5246#define FDCAN_TTOCF_AWL_Pos (16U)
5247#define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos)
5248#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk
5249#define FDCAN_TTOCF_EGTF_Pos (24U)
5250#define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos)
5251#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk
5252#define FDCAN_TTOCF_ECC_Pos (25U)
5253#define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos)
5254#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk
5255#define FDCAN_TTOCF_EVTP_Pos (26U)
5256#define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos)
5257#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk
5259/***************** Bit definition for FDCAN_TTMLM register *********************/
5260#define FDCAN_TTMLM_CCM_Pos (0U)
5261#define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos)
5262#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk
5263#define FDCAN_TTMLM_CSS_Pos (6U)
5264#define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos)
5265#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk
5266#define FDCAN_TTMLM_TXEW_Pos (8U)
5267#define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos)
5268#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk
5269#define FDCAN_TTMLM_ENTT_Pos (16U)
5270#define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)
5271#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk
5273/***************** Bit definition for FDCAN_TURCF register *********************/
5274#define FDCAN_TURCF_NCL_Pos (0U)
5275#define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos)
5276#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk
5277#define FDCAN_TURCF_DC_Pos (16U)
5278#define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos)
5279#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk
5280#define FDCAN_TURCF_ELT_Pos (31U)
5281#define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos)
5282#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk
5284/***************** Bit definition for FDCAN_TTOCN register ********************/
5285#define FDCAN_TTOCN_SGT_Pos (0U)
5286#define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos)
5287#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk
5288#define FDCAN_TTOCN_ECS_Pos (1U)
5289#define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos)
5290#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk
5291#define FDCAN_TTOCN_SWP_Pos (2U)
5292#define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos)
5293#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk
5294#define FDCAN_TTOCN_SWS_Pos (3U)
5295#define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos)
5296#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk
5297#define FDCAN_TTOCN_RTIE_Pos (5U)
5298#define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos)
5299#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk
5300#define FDCAN_TTOCN_TMC_Pos (6U)
5301#define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos)
5302#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk
5303#define FDCAN_TTOCN_TTIE_Pos (8U)
5304#define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos)
5305#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk
5306#define FDCAN_TTOCN_GCS_Pos (9U)
5307#define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos)
5308#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk
5309#define FDCAN_TTOCN_FGP_Pos (10U)
5310#define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos)
5311#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk
5312#define FDCAN_TTOCN_TMG_Pos (11U)
5313#define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos)
5314#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk
5315#define FDCAN_TTOCN_NIG_Pos (12U)
5316#define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos)
5317#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk
5318#define FDCAN_TTOCN_ESCN_Pos (13U)
5319#define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos)
5320#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk
5321#define FDCAN_TTOCN_LCKC_Pos (15U)
5322#define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos)
5323#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk
5325/***************** Bit definition for FDCAN_TTGTP register ********************/
5326#define FDCAN_TTGTP_TP_Pos (0U)
5327#define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos)
5328#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk
5329#define FDCAN_TTGTP_CTP_Pos (16U)
5330#define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)
5331#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk
5333/***************** Bit definition for FDCAN_TTTMK register ********************/
5334#define FDCAN_TTTMK_TM_Pos (0U)
5335#define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos)
5336#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk
5337#define FDCAN_TTTMK_TICC_Pos (16U)
5338#define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos)
5339#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk
5340#define FDCAN_TTTMK_LCKM_Pos (31U)
5341#define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos)
5342#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk
5344/***************** Bit definition for FDCAN_TTIR register ********************/
5345#define FDCAN_TTIR_SBC_Pos (0U)
5346#define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos)
5347#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk
5348#define FDCAN_TTIR_SMC_Pos (1U)
5349#define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos)
5350#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk
5351#define FDCAN_TTIR_CSM_Pos (2U)
5352#define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos)
5353#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk
5354#define FDCAN_TTIR_SOG_Pos (3U)
5355#define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos)
5356#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk
5357#define FDCAN_TTIR_RTMI_Pos (4U)
5358#define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos)
5359#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk
5360#define FDCAN_TTIR_TTMI_Pos (5U)
5361#define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos)
5362#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk
5363#define FDCAN_TTIR_SWE_Pos (6U)
5364#define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos)
5365#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk
5366#define FDCAN_TTIR_GTW_Pos (7U)
5367#define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos)
5368#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk
5369#define FDCAN_TTIR_GTD_Pos (8U)
5370#define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos)
5371#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk
5372#define FDCAN_TTIR_GTE_Pos (9U)
5373#define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos)
5374#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk
5375#define FDCAN_TTIR_TXU_Pos (10U)
5376#define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos)
5377#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk
5378#define FDCAN_TTIR_TXO_Pos (11U)
5379#define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos)
5380#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk
5381#define FDCAN_TTIR_SE1_Pos (12U)
5382#define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos)
5383#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk
5384#define FDCAN_TTIR_SE2_Pos (13U)
5385#define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos)
5386#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk
5387#define FDCAN_TTIR_ELC_Pos (14U)
5388#define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos)
5389#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk
5390#define FDCAN_TTIR_IWT_Pos (15U)
5391#define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos)
5392#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk
5393#define FDCAN_TTIR_WT_Pos (16U)
5394#define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos)
5395#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk
5396#define FDCAN_TTIR_AW_Pos (17U)
5397#define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos)
5398#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk
5399#define FDCAN_TTIR_CER_Pos (18U)
5400#define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos)
5401#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk
5403/***************** Bit definition for FDCAN_TTIE register ********************/
5404#define FDCAN_TTIE_SBCE_Pos (0U)
5405#define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos)
5406#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk
5407#define FDCAN_TTIE_SMCE_Pos (1U)
5408#define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos)
5409#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk
5410#define FDCAN_TTIE_CSME_Pos (2U)
5411#define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos)
5412#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk
5413#define FDCAN_TTIE_SOGE_Pos (3U)
5414#define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos)
5415#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk
5416#define FDCAN_TTIE_RTMIE_Pos (4U)
5417#define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos)
5418#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk
5419#define FDCAN_TTIE_TTMIE_Pos (5U)
5420#define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos)
5421#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk
5422#define FDCAN_TTIE_SWEE_Pos (6U)
5423#define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos)
5424#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk
5425#define FDCAN_TTIE_GTWE_Pos (7U)
5426#define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos)
5427#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk
5428#define FDCAN_TTIE_GTDE_Pos (8U)
5429#define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos)
5430#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk
5431#define FDCAN_TTIE_GTEE_Pos (9U)
5432#define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos)
5433#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk
5434#define FDCAN_TTIE_TXUE_Pos (10U)
5435#define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos)
5436#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk
5437#define FDCAN_TTIE_TXOE_Pos (11U)
5438#define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos)
5439#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk
5440#define FDCAN_TTIE_SE1E_Pos (12U)
5441#define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos)
5442#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk
5443#define FDCAN_TTIE_SE2E_Pos (13U)
5444#define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos)
5445#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk
5446#define FDCAN_TTIE_ELCE_Pos (14U)
5447#define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos)
5448#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk
5449#define FDCAN_TTIE_IWTE_Pos (15U)
5450#define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos)
5451#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk
5452#define FDCAN_TTIE_WTE_Pos (16U)
5453#define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos)
5454#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk
5455#define FDCAN_TTIE_AWE_Pos (17U)
5456#define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos)
5457#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk
5458#define FDCAN_TTIE_CERE_Pos (18U)
5459#define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos)
5460#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk
5462/***************** Bit definition for FDCAN_TTILS register ********************/
5463#define FDCAN_TTILS_SBCS_Pos (0U)
5464#define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos)
5465#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk
5466#define FDCAN_TTILS_SMCS_Pos (1U)
5467#define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos)
5468#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk
5469#define FDCAN_TTILS_CSMS_Pos (2U)
5470#define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos)
5471#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk
5472#define FDCAN_TTILS_SOGS_Pos (3U)
5473#define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos)
5474#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk
5475#define FDCAN_TTILS_RTMIS_Pos (4U)
5476#define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos)
5477#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk
5478#define FDCAN_TTILS_TTMIS_Pos (5U)
5479#define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos)
5480#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk
5481#define FDCAN_TTILS_SWES_Pos (6U)
5482#define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos)
5483#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk
5484#define FDCAN_TTILS_GTWS_Pos (7U)
5485#define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos)
5486#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk
5487#define FDCAN_TTILS_GTDS_Pos (8U)
5488#define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos)
5489#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk
5490#define FDCAN_TTILS_GTES_Pos (9U)
5491#define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos)
5492#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk
5493#define FDCAN_TTILS_TXUS_Pos (10U)
5494#define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos)
5495#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk
5496#define FDCAN_TTILS_TXOS_Pos (11U)
5497#define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos)
5498#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk
5499#define FDCAN_TTILS_SE1S_Pos (12U)
5500#define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos)
5501#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk
5502#define FDCAN_TTILS_SE2S_Pos (13U)
5503#define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos)
5504#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk
5505#define FDCAN_TTILS_ELCS_Pos (14U)
5506#define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos)
5507#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk
5508#define FDCAN_TTILS_IWTS_Pos (15U)
5509#define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos)
5510#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk
5511#define FDCAN_TTILS_WTS_Pos (16U)
5512#define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos)
5513#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk
5514#define FDCAN_TTILS_AWS_Pos (17U)
5515#define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos)
5516#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk
5517#define FDCAN_TTILS_CERS_Pos (18U)
5518#define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos)
5519#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk
5521/***************** Bit definition for FDCAN_TTOST register ********************/
5522#define FDCAN_TTOST_EL_Pos (0U)
5523#define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos)
5524#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk
5525#define FDCAN_TTOST_MS_Pos (2U)
5526#define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos)
5527#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk
5528#define FDCAN_TTOST_SYS_Pos (4U)
5529#define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos)
5530#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk
5531#define FDCAN_TTOST_QGTP_Pos (6U)
5532#define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos)
5533#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk
5534#define FDCAN_TTOST_QCS_Pos (7U)
5535#define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos)
5536#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk
5537#define FDCAN_TTOST_RTO_Pos (8U)
5538#define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos)
5539#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk
5540#define FDCAN_TTOST_WGTD_Pos (22U)
5541#define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos)
5542#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk
5543#define FDCAN_TTOST_GFI_Pos (23U)
5544#define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos)
5545#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk
5546#define FDCAN_TTOST_TMP_Pos (24U)
5547#define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos)
5548#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk
5549#define FDCAN_TTOST_GSI_Pos (27U)
5550#define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos)
5551#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk
5552#define FDCAN_TTOST_WFE_Pos (28U)
5553#define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos)
5554#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk
5555#define FDCAN_TTOST_AWE_Pos (29U)
5556#define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos)
5557#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk
5558#define FDCAN_TTOST_WECS_Pos (30U)
5559#define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos)
5560#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk
5561#define FDCAN_TTOST_SPL_Pos (31U)
5562#define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos)
5563#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk
5565/***************** Bit definition for FDCAN_TURNA register ********************/
5566#define FDCAN_TURNA_NAV_Pos (0U)
5567#define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)
5568#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk
5570/***************** Bit definition for FDCAN_TTLGT register ********************/
5571#define FDCAN_TTLGT_LT_Pos (0U)
5572#define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos)
5573#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk
5574#define FDCAN_TTLGT_GT_Pos (16U)
5575#define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos)
5576#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk
5578/***************** Bit definition for FDCAN_TTCTC register ********************/
5579#define FDCAN_TTCTC_CT_Pos (0U)
5580#define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos)
5581#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk
5582#define FDCAN_TTCTC_CC_Pos (16U)
5583#define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos)
5584#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk
5586/***************** Bit definition for FDCAN_TTCPT register ********************/
5587#define FDCAN_TTCPT_CCV_Pos (0U)
5588#define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos)
5589#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk
5590#define FDCAN_TTCPT_SWV_Pos (16U)
5591#define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)
5592#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk
5594/***************** Bit definition for FDCAN_TTCSM register ********************/
5595#define FDCAN_TTCSM_CSM_Pos (0U)
5596#define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)
5597#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk
5599/***************** Bit definition for FDCAN_TTTS register *********************/
5600#define FDCAN_TTTS_SWTSEL_Pos (0U)
5601#define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos)
5602#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk
5603#define FDCAN_TTTS_EVTSEL_Pos (4U)
5604#define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos)
5605#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk
5607/********************************************************************************/
5608/* */
5609/* FDCANCCU (Clock Calibration unit) */
5610/* */
5611/********************************************************************************/
5612
5613/***************** Bit definition for FDCANCCU_CREL register ******************/
5614#define FDCANCCU_CREL_DAY_Pos (0U)
5615#define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos)
5616#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk
5617#define FDCANCCU_CREL_MON_Pos (8U)
5618#define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos)
5619#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk
5620#define FDCANCCU_CREL_YEAR_Pos (16U)
5621#define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos)
5622#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk
5623#define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5624#define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)
5625#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk
5626#define FDCANCCU_CREL_STEP_Pos (24U)
5627#define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos)
5628#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk
5629#define FDCANCCU_CREL_REL_Pos (28U)
5630#define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos)
5631#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk
5633/***************** Bit definition for FDCANCCU_CCFG register ******************/
5634#define FDCANCCU_CCFG_TQBT_Pos (0U)
5635#define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)
5636#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk
5637#define FDCANCCU_CCFG_BCC_Pos (6U)
5638#define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos)
5639#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk
5640#define FDCANCCU_CCFG_CFL_Pos (7U)
5641#define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos)
5642#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk
5643#define FDCANCCU_CCFG_OCPM_Pos (8U)
5644#define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)
5645#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk
5646#define FDCANCCU_CCFG_CDIV_Pos (16U)
5647#define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos)
5648#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk
5649#define FDCANCCU_CCFG_SWR_Pos (31U)
5650#define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos)
5651#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk
5653/***************** Bit definition for FDCANCCU_CSTAT register *****************/
5654#define FDCANCCU_CSTAT_OCPC_Pos (0U)
5655#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)
5656#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk
5657#define FDCANCCU_CSTAT_TQC_Pos (18U)
5658#define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)
5659#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk
5660#define FDCANCCU_CSTAT_CALS_Pos (30U)
5661#define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos)
5662#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk
5664/****************** Bit definition for FDCANCCU_CWD register ******************/
5665#define FDCANCCU_CWD_WDC_Pos (0U)
5666#define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)
5667#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk
5668#define FDCANCCU_CWD_WDV_Pos (16U)
5669#define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)
5670#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk
5672/****************** Bit definition for FDCANCCU_IR register *******************/
5673#define FDCANCCU_IR_CWE_Pos (0U)
5674#define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos)
5675#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk
5676#define FDCANCCU_IR_CSC_Pos (1U)
5677#define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos)
5678#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk
5680/****************** Bit definition for FDCANCCU_IE register *******************/
5681#define FDCANCCU_IE_CWEE_Pos (0U)
5682#define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos)
5683#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk
5684#define FDCANCCU_IE_CSCE_Pos (1U)
5685#define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos)
5686#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk
5688/******************************************************************************/
5689/* */
5690/* HDMI-CEC (CEC) */
5691/* */
5692/******************************************************************************/
5693
5694/******************* Bit definition for CEC_CR register *********************/
5695#define CEC_CR_CECEN_Pos (0U)
5696#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos)
5697#define CEC_CR_CECEN CEC_CR_CECEN_Msk
5698#define CEC_CR_TXSOM_Pos (1U)
5699#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos)
5700#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk
5701#define CEC_CR_TXEOM_Pos (2U)
5702#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos)
5703#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk
5705/******************* Bit definition for CEC_CFGR register *******************/
5706#define CEC_CFGR_SFT_Pos (0U)
5707#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos)
5708#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk
5709#define CEC_CFGR_RXTOL_Pos (3U)
5710#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos)
5711#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk
5712#define CEC_CFGR_BRESTP_Pos (4U)
5713#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos)
5714#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk
5715#define CEC_CFGR_BREGEN_Pos (5U)
5716#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos)
5717#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk
5718#define CEC_CFGR_LBPEGEN_Pos (6U)
5719#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos)
5720#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk
5721#define CEC_CFGR_SFTOPT_Pos (8U)
5722#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos)
5723#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk
5724#define CEC_CFGR_BRDNOGEN_Pos (7U)
5725#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos)
5726#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk
5727#define CEC_CFGR_OAR_Pos (16U)
5728#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos)
5729#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk
5730#define CEC_CFGR_LSTN_Pos (31U)
5731#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos)
5732#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk
5734/******************* Bit definition for CEC_TXDR register *******************/
5735#define CEC_TXDR_TXD_Pos (0U)
5736#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos)
5737#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk
5739/******************* Bit definition for CEC_RXDR register *******************/
5740#define CEC_RXDR_RXD_Pos (0U)
5741#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos)
5742#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk
5744/******************* Bit definition for CEC_ISR register ********************/
5745#define CEC_ISR_RXBR_Pos (0U)
5746#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos)
5747#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk
5748#define CEC_ISR_RXEND_Pos (1U)
5749#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos)
5750#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk
5751#define CEC_ISR_RXOVR_Pos (2U)
5752#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos)
5753#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk
5754#define CEC_ISR_BRE_Pos (3U)
5755#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos)
5756#define CEC_ISR_BRE CEC_ISR_BRE_Msk
5757#define CEC_ISR_SBPE_Pos (4U)
5758#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos)
5759#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk
5760#define CEC_ISR_LBPE_Pos (5U)
5761#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos)
5762#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk
5763#define CEC_ISR_RXACKE_Pos (6U)
5764#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos)
5765#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk
5766#define CEC_ISR_ARBLST_Pos (7U)
5767#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos)
5768#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk
5769#define CEC_ISR_TXBR_Pos (8U)
5770#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos)
5771#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk
5772#define CEC_ISR_TXEND_Pos (9U)
5773#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos)
5774#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk
5775#define CEC_ISR_TXUDR_Pos (10U)
5776#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos)
5777#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk
5778#define CEC_ISR_TXERR_Pos (11U)
5779#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos)
5780#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk
5781#define CEC_ISR_TXACKE_Pos (12U)
5782#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos)
5783#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk
5785/******************* Bit definition for CEC_IER register ********************/
5786#define CEC_IER_RXBRIE_Pos (0U)
5787#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos)
5788#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk
5789#define CEC_IER_RXENDIE_Pos (1U)
5790#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos)
5791#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk
5792#define CEC_IER_RXOVRIE_Pos (2U)
5793#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos)
5794#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk
5795#define CEC_IER_BREIE_Pos (3U)
5796#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos)
5797#define CEC_IER_BREIE CEC_IER_BREIE_Msk
5798#define CEC_IER_SBPEIE_Pos (4U)
5799#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos)
5800#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk
5801#define CEC_IER_LBPEIE_Pos (5U)
5802#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos)
5803#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk
5804#define CEC_IER_RXACKEIE_Pos (6U)
5805#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos)
5806#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk
5807#define CEC_IER_ARBLSTIE_Pos (7U)
5808#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos)
5809#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk
5810#define CEC_IER_TXBRIE_Pos (8U)
5811#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos)
5812#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk
5813#define CEC_IER_TXENDIE_Pos (9U)
5814#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos)
5815#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk
5816#define CEC_IER_TXUDRIE_Pos (10U)
5817#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos)
5818#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk
5819#define CEC_IER_TXERRIE_Pos (11U)
5820#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos)
5821#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk
5822#define CEC_IER_TXACKEIE_Pos (12U)
5823#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos)
5824#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk
5826/******************************************************************************/
5827/* */
5828/* CORDIC calculation unit */
5829/* */
5830/******************************************************************************/
5831/******************* Bit definition for CORDIC_CSR register *****************/
5832#define CORDIC_CSR_FUNC_Pos (0U)
5833#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos)
5834#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk
5835#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos)
5836#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos)
5837#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos)
5838#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos)
5839#define CORDIC_CSR_PRECISION_Pos (4U)
5840#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)
5841#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk
5842#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos)
5843#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos)
5844#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos)
5845#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos)
5846#define CORDIC_CSR_SCALE_Pos (8U)
5847#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos)
5848#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk
5849#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos)
5850#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos)
5851#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos)
5852#define CORDIC_CSR_IEN_Pos (16U)
5853#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos)
5854#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk
5855#define CORDIC_CSR_DMAREN_Pos (17U)
5856#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos)
5857#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk
5858#define CORDIC_CSR_DMAWEN_Pos (18U)
5859#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos)
5860#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk
5861#define CORDIC_CSR_NRES_Pos (19U)
5862#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos)
5863#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk
5864#define CORDIC_CSR_NARGS_Pos (20U)
5865#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos)
5866#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk
5867#define CORDIC_CSR_RESSIZE_Pos (21U)
5868#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos)
5869#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk
5870#define CORDIC_CSR_ARGSIZE_Pos (22U)
5871#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos)
5872#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk
5873#define CORDIC_CSR_RRDY_Pos (31U)
5874#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos)
5875#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk
5877/******************* Bit definition for CORDIC_WDATA register ***************/
5878#define CORDIC_WDATA_ARG_Pos (0U)
5879#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)
5880#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk
5882/******************* Bit definition for CORDIC_RDATA register ***************/
5883#define CORDIC_RDATA_RES_Pos (0U)
5884#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)
5885#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk
5887/******************************************************************************/
5888/* */
5889/* CRC calculation unit */
5890/* */
5891/******************************************************************************/
5892/******************* Bit definition for CRC_DR register *********************/
5893#define CRC_DR_DR_Pos (0U)
5894#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5895#define CRC_DR_DR CRC_DR_DR_Msk
5897/******************* Bit definition for CRC_IDR register ********************/
5898#define CRC_IDR_IDR_Pos (0U)
5899#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)
5900#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5902/******************** Bit definition for CRC_CR register ********************/
5903#define CRC_CR_RESET_Pos (0U)
5904#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5905#define CRC_CR_RESET CRC_CR_RESET_Msk
5906#define CRC_CR_POLYSIZE_Pos (3U)
5907#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
5908#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
5909#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
5910#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
5911#define CRC_CR_REV_IN_Pos (5U)
5912#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
5913#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
5914#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
5915#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
5916#define CRC_CR_REV_OUT_Pos (7U)
5917#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
5918#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
5920/******************* Bit definition for CRC_INIT register *******************/
5921#define CRC_INIT_INIT_Pos (0U)
5922#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
5923#define CRC_INIT_INIT CRC_INIT_INIT_Msk
5925/******************* Bit definition for CRC_POL register ********************/
5926#define CRC_POL_POL_Pos (0U)
5927#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
5928#define CRC_POL_POL CRC_POL_POL_Msk
5930/******************************************************************************/
5931/* */
5932/* CRS Clock Recovery System */
5933/******************************************************************************/
5934
5935/******************* Bit definition for CRS_CR register *********************/
5936#define CRS_CR_SYNCOKIE_Pos (0U)
5937#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos)
5938#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk
5939#define CRS_CR_SYNCWARNIE_Pos (1U)
5940#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos)
5941#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk
5942#define CRS_CR_ERRIE_Pos (2U)
5943#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos)
5944#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk
5945#define CRS_CR_ESYNCIE_Pos (3U)
5946#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos)
5947#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk
5948#define CRS_CR_CEN_Pos (5U)
5949#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos)
5950#define CRS_CR_CEN CRS_CR_CEN_Msk
5951#define CRS_CR_AUTOTRIMEN_Pos (6U)
5952#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos)
5953#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk
5954#define CRS_CR_SWSYNC_Pos (7U)
5955#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos)
5956#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk
5957#define CRS_CR_TRIM_Pos (8U)
5958#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos)
5959#define CRS_CR_TRIM CRS_CR_TRIM_Msk
5961/******************* Bit definition for CRS_CFGR register *********************/
5962#define CRS_CFGR_RELOAD_Pos (0U)
5963#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos)
5964#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk
5965#define CRS_CFGR_FELIM_Pos (16U)
5966#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos)
5967#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk
5969#define CRS_CFGR_SYNCDIV_Pos (24U)
5970#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos)
5971#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk
5972#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos)
5973#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos)
5974#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos)
5976#define CRS_CFGR_SYNCSRC_Pos (28U)
5977#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos)
5978#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk
5979#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos)
5980#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos)
5982#define CRS_CFGR_SYNCPOL_Pos (31U)
5983#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos)
5984#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk
5986/******************* Bit definition for CRS_ISR register *********************/
5987#define CRS_ISR_SYNCOKF_Pos (0U)
5988#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos)
5989#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk
5990#define CRS_ISR_SYNCWARNF_Pos (1U)
5991#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos)
5992#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk
5993#define CRS_ISR_ERRF_Pos (2U)
5994#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos)
5995#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk
5996#define CRS_ISR_ESYNCF_Pos (3U)
5997#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos)
5998#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk
5999#define CRS_ISR_SYNCERR_Pos (8U)
6000#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos)
6001#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk
6002#define CRS_ISR_SYNCMISS_Pos (9U)
6003#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos)
6004#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk
6005#define CRS_ISR_TRIMOVF_Pos (10U)
6006#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos)
6007#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk
6008#define CRS_ISR_FEDIR_Pos (15U)
6009#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos)
6010#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk
6011#define CRS_ISR_FECAP_Pos (16U)
6012#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos)
6013#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk
6015/******************* Bit definition for CRS_ICR register *********************/
6016#define CRS_ICR_SYNCOKC_Pos (0U)
6017#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos)
6018#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk
6019#define CRS_ICR_SYNCWARNC_Pos (1U)
6020#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos)
6021#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk
6022#define CRS_ICR_ERRC_Pos (2U)
6023#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos)
6024#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk
6025#define CRS_ICR_ESYNCC_Pos (3U)
6026#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos)
6027#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk
6029/******************************************************************************/
6030/* */
6031/* Crypto Processor */
6032/* */
6033/******************************************************************************/
6034/******************************** CRYP VER **********************************/
6035#define CRYP_VER_2_2
6036/******************* Bits definition for CRYP_CR register ********************/
6037#define CRYP_CR_ALGODIR_Pos (2U)
6038#define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos)
6039#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
6040
6041#define CRYP_CR_ALGOMODE_Pos (3U)
6042#define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos)
6043#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
6044#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos)
6045#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos)
6046#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos)
6047#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
6048#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
6049#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos)
6050#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
6051#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
6052#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos)
6053#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
6054#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
6055#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos)
6056#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
6057#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
6058#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos)
6059#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
6060#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
6061#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos)
6062#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
6063#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
6064#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos)
6065#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
6066#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
6067#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos)
6068#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
6069#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
6070#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos)
6071#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
6072#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
6073#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos)
6074#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
6075
6076#define CRYP_CR_DATATYPE_Pos (6U)
6077#define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos)
6078#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
6079#define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos)
6080#define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos)
6081#define CRYP_CR_KEYSIZE_Pos (8U)
6082#define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos)
6083#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
6084#define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos)
6085#define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos)
6086#define CRYP_CR_FFLUSH_Pos (14U)
6087#define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos)
6088#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
6089#define CRYP_CR_CRYPEN_Pos (15U)
6090#define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos)
6091#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
6092
6093#define CRYP_CR_GCM_CCMPH_Pos (16U)
6094#define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos)
6095#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
6096#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos)
6097#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos)
6098#define CRYP_CR_ALGOMODE_3 (0x00080000U)
6099#define CRYP_CR_NPBLB_Pos (20U)
6100#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos)
6101#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
6102
6103/****************** Bits definition for CRYP_SR register *********************/
6104#define CRYP_SR_IFEM_Pos (0U)
6105#define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos)
6106#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
6107#define CRYP_SR_IFNF_Pos (1U)
6108#define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos)
6109#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
6110#define CRYP_SR_OFNE_Pos (2U)
6111#define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos)
6112#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
6113#define CRYP_SR_OFFU_Pos (3U)
6114#define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos)
6115#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
6116#define CRYP_SR_BUSY_Pos (4U)
6117#define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos)
6118#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
6119/****************** Bits definition for CRYP_DMACR register ******************/
6120#define CRYP_DMACR_DIEN_Pos (0U)
6121#define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos)
6122#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
6123#define CRYP_DMACR_DOEN_Pos (1U)
6124#define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos)
6125#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
6126/***************** Bits definition for CRYP_IMSCR register ******************/
6127#define CRYP_IMSCR_INIM_Pos (0U)
6128#define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos)
6129#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
6130#define CRYP_IMSCR_OUTIM_Pos (1U)
6131#define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos)
6132#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
6133/****************** Bits definition for CRYP_RISR register *******************/
6134#define CRYP_RISR_INRIS_Pos (0U)
6135#define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos)
6136#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
6137#define CRYP_RISR_OUTRIS_Pos (1U)
6138#define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos)
6139#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
6140/****************** Bits definition for CRYP_MISR register *******************/
6141#define CRYP_MISR_INMIS_Pos (0U)
6142#define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos)
6143#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
6144#define CRYP_MISR_OUTMIS_Pos (1U)
6145#define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos)
6146#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
6147
6148/******************************************************************************/
6149/* */
6150/* Digital to Analog Converter */
6151/* */
6152/******************************************************************************/
6153/******************** Bit definition for DAC_CR register ********************/
6154#define DAC_CR_EN1_Pos (0U)
6155#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
6156#define DAC_CR_EN1 DAC_CR_EN1_Msk
6157#define DAC_CR_TEN1_Pos (1U)
6158#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
6159#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
6161#define DAC_CR_TSEL1_Pos (2U)
6162#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos)
6163#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
6164#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
6165#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
6166#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
6167#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos)
6170#define DAC_CR_WAVE1_Pos (6U)
6171#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
6172#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
6173#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
6174#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
6176#define DAC_CR_MAMP1_Pos (8U)
6177#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
6178#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
6179#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
6180#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
6181#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
6182#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
6184#define DAC_CR_DMAEN1_Pos (12U)
6185#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
6186#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
6187#define DAC_CR_DMAUDRIE1_Pos (13U)
6188#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
6189#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
6190#define DAC_CR_CEN1_Pos (14U)
6191#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)
6192#define DAC_CR_CEN1 DAC_CR_CEN1_Msk
6194#define DAC_CR_EN2_Pos (16U)
6195#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
6196#define DAC_CR_EN2 DAC_CR_EN2_Msk
6197#define DAC_CR_TEN2_Pos (17U)
6198#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
6199#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
6201#define DAC_CR_TSEL2_Pos (18U)
6202#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos)
6203#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
6204#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
6205#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
6206#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
6207#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos)
6210#define DAC_CR_WAVE2_Pos (22U)
6211#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
6212#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
6213#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
6214#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
6216#define DAC_CR_MAMP2_Pos (24U)
6217#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
6218#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
6219#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
6220#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
6221#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
6222#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
6224#define DAC_CR_DMAEN2_Pos (28U)
6225#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
6226#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
6227#define DAC_CR_DMAUDRIE2_Pos (29U)
6228#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
6229#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
6230#define DAC_CR_CEN2_Pos (30U)
6231#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)
6232#define DAC_CR_CEN2 DAC_CR_CEN2_Msk
6234/***************** Bit definition for DAC_SWTRIGR register ******************/
6235#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6236#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
6237#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
6238#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6239#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
6240#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
6242/***************** Bit definition for DAC_DHR12R1 register ******************/
6243#define DAC_DHR12R1_DACC1DHR_Pos (0U)
6244#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
6245#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
6247/***************** Bit definition for DAC_DHR12L1 register ******************/
6248#define DAC_DHR12L1_DACC1DHR_Pos (4U)
6249#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
6250#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
6252/****************** Bit definition for DAC_DHR8R1 register ******************/
6253#define DAC_DHR8R1_DACC1DHR_Pos (0U)
6254#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
6255#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
6257/***************** Bit definition for DAC_DHR12R2 register ******************/
6258#define DAC_DHR12R2_DACC2DHR_Pos (0U)
6259#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
6260#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
6262/***************** Bit definition for DAC_DHR12L2 register ******************/
6263#define DAC_DHR12L2_DACC2DHR_Pos (4U)
6264#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
6265#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
6267/****************** Bit definition for DAC_DHR8R2 register ******************/
6268#define DAC_DHR8R2_DACC2DHR_Pos (0U)
6269#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
6270#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
6272/***************** Bit definition for DAC_DHR12RD register ******************/
6273#define DAC_DHR12RD_DACC1DHR_Pos (0U)
6274#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
6275#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
6276#define DAC_DHR12RD_DACC2DHR_Pos (16U)
6277#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
6278#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
6280/***************** Bit definition for DAC_DHR12LD register ******************/
6281#define DAC_DHR12LD_DACC1DHR_Pos (4U)
6282#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
6283#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
6284#define DAC_DHR12LD_DACC2DHR_Pos (20U)
6285#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
6286#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
6288/****************** Bit definition for DAC_DHR8RD register ******************/
6289#define DAC_DHR8RD_DACC1DHR_Pos (0U)
6290#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
6291#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
6292#define DAC_DHR8RD_DACC2DHR_Pos (8U)
6293#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
6294#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
6296/******************* Bit definition for DAC_DOR1 register *******************/
6297#define DAC_DOR1_DACC1DOR_Pos (0U)
6298#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
6299#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
6301/******************* Bit definition for DAC_DOR2 register *******************/
6302#define DAC_DOR2_DACC2DOR_Pos (0U)
6303#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
6304#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
6306/******************** Bit definition for DAC_SR register ********************/
6307#define DAC_SR_DMAUDR1_Pos (13U)
6308#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
6309#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
6310#define DAC_SR_CAL_FLAG1_Pos (14U)
6311#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)
6312#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk
6313#define DAC_SR_BWST1_Pos (15U)
6314#define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos)
6315#define DAC_SR_BWST1 DAC_SR_BWST1_Msk
6317#define DAC_SR_DMAUDR2_Pos (29U)
6318#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
6319#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
6320#define DAC_SR_CAL_FLAG2_Pos (30U)
6321#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)
6322#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk
6323#define DAC_SR_BWST2_Pos (31U)
6324#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)
6325#define DAC_SR_BWST2 DAC_SR_BWST2_Msk
6327/******************* Bit definition for DAC_CCR register ********************/
6328#define DAC_CCR_OTRIM1_Pos (0U)
6329#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)
6330#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk
6331#define DAC_CCR_OTRIM2_Pos (16U)
6332#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)
6333#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk
6335/******************* Bit definition for DAC_MCR register *******************/
6336#define DAC_MCR_MODE1_Pos (0U)
6337#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)
6338#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk
6339#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)
6340#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)
6341#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)
6343#define DAC_MCR_MODE2_Pos (16U)
6344#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)
6345#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk
6346#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)
6347#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)
6348#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)
6350/****************** Bit definition for DAC_SHSR1 register ******************/
6351#define DAC_SHSR1_TSAMPLE1_Pos (0U)
6352#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)
6353#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk
6355/****************** Bit definition for DAC_SHSR2 register ******************/
6356#define DAC_SHSR2_TSAMPLE2_Pos (0U)
6357#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)
6358#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk
6360/****************** Bit definition for DAC_SHHR register ******************/
6361#define DAC_SHHR_THOLD1_Pos (0U)
6362#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)
6363#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk
6364#define DAC_SHHR_THOLD2_Pos (16U)
6365#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)
6366#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk
6368/****************** Bit definition for DAC_SHRR register ******************/
6369#define DAC_SHRR_TREFRESH1_Pos (0U)
6370#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)
6371#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk
6372#define DAC_SHRR_TREFRESH2_Pos (16U)
6373#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)
6374#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk
6376/******************************************************************************/
6377/* */
6378/* DCMI */
6379/* */
6380/******************************************************************************/
6381/******************** Bits definition for DCMI_CR register ******************/
6382#define DCMI_CR_CAPTURE_Pos (0U)
6383#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
6384#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6385#define DCMI_CR_CM_Pos (1U)
6386#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
6387#define DCMI_CR_CM DCMI_CR_CM_Msk
6388#define DCMI_CR_CROP_Pos (2U)
6389#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
6390#define DCMI_CR_CROP DCMI_CR_CROP_Msk
6391#define DCMI_CR_JPEG_Pos (3U)
6392#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
6393#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6394#define DCMI_CR_ESS_Pos (4U)
6395#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
6396#define DCMI_CR_ESS DCMI_CR_ESS_Msk
6397#define DCMI_CR_PCKPOL_Pos (5U)
6398#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
6399#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6400#define DCMI_CR_HSPOL_Pos (6U)
6401#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
6402#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6403#define DCMI_CR_VSPOL_Pos (7U)
6404#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
6405#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6406#define DCMI_CR_FCRC_0 (0x00000100U)
6407#define DCMI_CR_FCRC_1 (0x00000200U)
6408#define DCMI_CR_EDM_0 (0x00000400U)
6409#define DCMI_CR_EDM_1 (0x00000800U)
6410#define DCMI_CR_CRE_Pos (12U)
6411#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
6412#define DCMI_CR_CRE DCMI_CR_CRE_Msk
6413#define DCMI_CR_ENABLE_Pos (14U)
6414#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
6415#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6416#define DCMI_CR_BSM_Pos (16U)
6417#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos)
6418#define DCMI_CR_BSM DCMI_CR_BSM_Msk
6419#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos)
6420#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos)
6421#define DCMI_CR_OEBS_Pos (18U)
6422#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
6423#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6424#define DCMI_CR_LSM_Pos (19U)
6425#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
6426#define DCMI_CR_LSM DCMI_CR_LSM_Msk
6427#define DCMI_CR_OELS_Pos (20U)
6428#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
6429#define DCMI_CR_OELS DCMI_CR_OELS_Msk
6430
6431/******************** Bits definition for DCMI_SR register ******************/
6432#define DCMI_SR_HSYNC_Pos (0U)
6433#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
6434#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6435#define DCMI_SR_VSYNC_Pos (1U)
6436#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
6437#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6438#define DCMI_SR_FNE_Pos (2U)
6439#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
6440#define DCMI_SR_FNE DCMI_SR_FNE_Msk
6441
6442/******************** Bits definition for DCMI_RIS register ****************/
6443#define DCMI_RIS_FRAME_RIS_Pos (0U)
6444#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
6445#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6446#define DCMI_RIS_OVR_RIS_Pos (1U)
6447#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
6448#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6449#define DCMI_RIS_ERR_RIS_Pos (2U)
6450#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
6451#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6452#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6453#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
6454#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6455#define DCMI_RIS_LINE_RIS_Pos (4U)
6456#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
6457#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6458
6459/******************** Bits definition for DCMI_IER register *****************/
6460#define DCMI_IER_FRAME_IE_Pos (0U)
6461#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
6462#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6463#define DCMI_IER_OVR_IE_Pos (1U)
6464#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
6465#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6466#define DCMI_IER_ERR_IE_Pos (2U)
6467#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
6468#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6469#define DCMI_IER_VSYNC_IE_Pos (3U)
6470#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
6471#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6472#define DCMI_IER_LINE_IE_Pos (4U)
6473#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
6474#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6475
6476
6477/******************** Bits definition for DCMI_MIS register *****************/
6478#define DCMI_MIS_FRAME_MIS_Pos (0U)
6479#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
6480#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6481#define DCMI_MIS_OVR_MIS_Pos (1U)
6482#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
6483#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6484#define DCMI_MIS_ERR_MIS_Pos (2U)
6485#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
6486#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6487#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6488#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
6489#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6490#define DCMI_MIS_LINE_MIS_Pos (4U)
6491#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
6492#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6493
6494
6495/******************** Bits definition for DCMI_ICR register *****************/
6496#define DCMI_ICR_FRAME_ISC_Pos (0U)
6497#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
6498#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6499#define DCMI_ICR_OVR_ISC_Pos (1U)
6500#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
6501#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6502#define DCMI_ICR_ERR_ISC_Pos (2U)
6503#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
6504#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6505#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6506#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
6507#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6508#define DCMI_ICR_LINE_ISC_Pos (4U)
6509#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
6510#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6511
6512
6513/******************** Bits definition for DCMI_ESCR register ******************/
6514#define DCMI_ESCR_FSC_Pos (0U)
6515#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
6516#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6517#define DCMI_ESCR_LSC_Pos (8U)
6518#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
6519#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6520#define DCMI_ESCR_LEC_Pos (16U)
6521#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
6522#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6523#define DCMI_ESCR_FEC_Pos (24U)
6524#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
6525#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6526
6527/******************** Bits definition for DCMI_ESUR register ******************/
6528#define DCMI_ESUR_FSU_Pos (0U)
6529#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
6530#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6531#define DCMI_ESUR_LSU_Pos (8U)
6532#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
6533#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6534#define DCMI_ESUR_LEU_Pos (16U)
6535#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
6536#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6537#define DCMI_ESUR_FEU_Pos (24U)
6538#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
6539#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6540
6541/******************** Bits definition for DCMI_CWSTRT register ******************/
6542#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6543#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
6544#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6545#define DCMI_CWSTRT_VST_Pos (16U)
6546#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
6547#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6548
6549/******************** Bits definition for DCMI_CWSIZE register ******************/
6550#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6551#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
6552#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6553#define DCMI_CWSIZE_VLINE_Pos (16U)
6554#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
6555#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6556
6557/******************** Bits definition for DCMI_DR register ******************/
6558#define DCMI_DR_BYTE0_Pos (0U)
6559#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
6560#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6561#define DCMI_DR_BYTE1_Pos (8U)
6562#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
6563#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6564#define DCMI_DR_BYTE2_Pos (16U)
6565#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
6566#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6567#define DCMI_DR_BYTE3_Pos (24U)
6568#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
6569#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6570
6571/******************************************************************************/
6572/* */
6573/* Digital Filter for Sigma Delta Modulators */
6574/* */
6575/******************************************************************************/
6576
6577/**************** DFSDM channel configuration registers ********************/
6578
6579/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6580#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6581#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
6582#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
6583#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6584#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
6585#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
6586#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6587#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
6588#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
6589#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6590#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
6591#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
6592#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
6593#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
6594#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6595#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
6596#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
6597#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
6598#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
6599#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6600#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
6601#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
6602#define DFSDM_CHCFGR1_CHEN_Pos (7U)
6603#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
6604#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
6605#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6606#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
6607#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
6608#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6609#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
6610#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
6611#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6612#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6613#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
6614#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6615#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6616#define DFSDM_CHCFGR1_SITP_Pos (0U)
6617#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
6618#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
6619#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
6620#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
6622/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6623#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6624#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
6625#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
6626#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6627#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
6628#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
6630/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6631#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6632#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6633#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
6634#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6635#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6636#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6637#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
6638#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
6639#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6640#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
6641#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
6642#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6643#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
6644#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
6646/**************** Bit definition for DFSDM_CHWDATR register *******************/
6647#define DFSDM_CHWDATR_WDATA_Pos (0U)
6648#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
6649#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
6651/**************** Bit definition for DFSDM_CHDATINR register *****************/
6652#define DFSDM_CHDATINR_INDAT0_Pos (0U)
6653#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
6654#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
6655#define DFSDM_CHDATINR_INDAT1_Pos (16U)
6656#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
6657#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
6659/************************ DFSDM module registers ****************************/
6660
6661/******************** Bit definition for DFSDM_FLTCR1 register *******************/
6662#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6663#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
6664#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
6665#define DFSDM_FLTCR1_FAST_Pos (29U)
6666#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
6667#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
6668#define DFSDM_FLTCR1_RCH_Pos (24U)
6669#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
6670#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
6671#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6672#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
6673#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
6674#define DFSDM_FLTCR1_RSYNC_Pos (19U)
6675#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
6676#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
6677#define DFSDM_FLTCR1_RCONT_Pos (18U)
6678#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
6679#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
6680#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6681#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
6682#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
6683#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6684#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
6685#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
6686#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
6687#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
6688#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6689#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)
6690#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
6691#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6692#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6693#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6694#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6695#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6697#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6698#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
6699#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
6700#define DFSDM_FLTCR1_JSCAN_Pos (4U)
6701#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
6702#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
6703#define DFSDM_FLTCR1_JSYNC_Pos (3U)
6704#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
6705#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
6706#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6707#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
6708#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
6709#define DFSDM_FLTCR1_DFEN_Pos (0U)
6710#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
6711#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
6713/******************** Bit definition for DFSDM_FLTCR2 register *******************/
6714#define DFSDM_FLTCR2_AWDCH_Pos (16U)
6715#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
6716#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
6717#define DFSDM_FLTCR2_EXCH_Pos (8U)
6718#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
6719#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
6720#define DFSDM_FLTCR2_CKABIE_Pos (6U)
6721#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
6722#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
6723#define DFSDM_FLTCR2_SCDIE_Pos (5U)
6724#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
6725#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
6726#define DFSDM_FLTCR2_AWDIE_Pos (4U)
6727#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
6728#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
6729#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6730#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
6731#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
6732#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6733#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
6734#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
6735#define DFSDM_FLTCR2_REOCIE_Pos (1U)
6736#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
6737#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
6738#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6739#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
6740#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
6742/******************** Bit definition for DFSDM_FLTISR register *******************/
6743#define DFSDM_FLTISR_SCDF_Pos (24U)
6744#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
6745#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
6746#define DFSDM_FLTISR_CKABF_Pos (16U)
6747#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
6748#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
6749#define DFSDM_FLTISR_RCIP_Pos (14U)
6750#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
6751#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
6752#define DFSDM_FLTISR_JCIP_Pos (13U)
6753#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
6754#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
6755#define DFSDM_FLTISR_AWDF_Pos (4U)
6756#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
6757#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
6758#define DFSDM_FLTISR_ROVRF_Pos (3U)
6759#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
6760#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
6761#define DFSDM_FLTISR_JOVRF_Pos (2U)
6762#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
6763#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
6764#define DFSDM_FLTISR_REOCF_Pos (1U)
6765#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
6766#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
6767#define DFSDM_FLTISR_JEOCF_Pos (0U)
6768#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
6769#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
6771/******************** Bit definition for DFSDM_FLTICR register *******************/
6772#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6773#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
6774#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
6775#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6776#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
6777#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
6778#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6779#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
6780#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
6781#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6782#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
6783#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
6785/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6786#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6787#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
6788#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
6790/******************** Bit definition for DFSDM_FLTFCR register *******************/
6791#define DFSDM_FLTFCR_FORD_Pos (29U)
6792#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
6793#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
6794#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
6795#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
6796#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
6797#define DFSDM_FLTFCR_FOSR_Pos (16U)
6798#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
6799#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
6800#define DFSDM_FLTFCR_IOSR_Pos (0U)
6801#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
6802#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
6804/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6805#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6806#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
6807#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
6808#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6809#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
6810#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
6812/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6813#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6814#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
6815#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
6816#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6817#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
6818#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
6819#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6820#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
6821#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
6823/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6824#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6825#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
6826#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
6827#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6828#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
6829#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
6831/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6832#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6833#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
6834#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
6835#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6836#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
6837#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
6839/****************** Bit definition for DFSDM_FLTAWSR register ******************/
6840#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6841#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
6842#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
6843#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6844#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
6845#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
6847/****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6848#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6849#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
6850#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
6851#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6852#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
6853#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
6855/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6856#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6857#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
6858#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
6859#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6860#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
6861#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
6863/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6864#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6865#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
6866#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
6867#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6868#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
6869#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
6871/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6872#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6873#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
6874#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
6876/******************************************************************************/
6877/* */
6878/* BDMA Controller */
6879/* */
6880/******************************************************************************/
6881
6882/******************* Bit definition for BDMA_ISR register ********************/
6883#define BDMA_ISR_GIF0_Pos (0U)
6884#define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos)
6885#define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk
6886#define BDMA_ISR_TCIF0_Pos (1U)
6887#define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos)
6888#define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk
6889#define BDMA_ISR_HTIF0_Pos (2U)
6890#define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos)
6891#define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk
6892#define BDMA_ISR_TEIF0_Pos (3U)
6893#define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos)
6894#define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk
6895#define BDMA_ISR_GIF1_Pos (4U)
6896#define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos)
6897#define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk
6898#define BDMA_ISR_TCIF1_Pos (5U)
6899#define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos)
6900#define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk
6901#define BDMA_ISR_HTIF1_Pos (6U)
6902#define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos)
6903#define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk
6904#define BDMA_ISR_TEIF1_Pos (7U)
6905#define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos)
6906#define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk
6907#define BDMA_ISR_GIF2_Pos (8U)
6908#define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos)
6909#define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk
6910#define BDMA_ISR_TCIF2_Pos (9U)
6911#define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos)
6912#define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk
6913#define BDMA_ISR_HTIF2_Pos (10U)
6914#define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos)
6915#define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk
6916#define BDMA_ISR_TEIF2_Pos (11U)
6917#define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos)
6918#define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk
6919#define BDMA_ISR_GIF3_Pos (12U)
6920#define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos)
6921#define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk
6922#define BDMA_ISR_TCIF3_Pos (13U)
6923#define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos)
6924#define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk
6925#define BDMA_ISR_HTIF3_Pos (14U)
6926#define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos)
6927#define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk
6928#define BDMA_ISR_TEIF3_Pos (15U)
6929#define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos)
6930#define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk
6931#define BDMA_ISR_GIF4_Pos (16U)
6932#define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos)
6933#define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk
6934#define BDMA_ISR_TCIF4_Pos (17U)
6935#define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos)
6936#define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk
6937#define BDMA_ISR_HTIF4_Pos (18U)
6938#define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos)
6939#define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk
6940#define BDMA_ISR_TEIF4_Pos (19U)
6941#define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos)
6942#define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk
6943#define BDMA_ISR_GIF5_Pos (20U)
6944#define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos)
6945#define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk
6946#define BDMA_ISR_TCIF5_Pos (21U)
6947#define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos)
6948#define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk
6949#define BDMA_ISR_HTIF5_Pos (22U)
6950#define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos)
6951#define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk
6952#define BDMA_ISR_TEIF5_Pos (23U)
6953#define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos)
6954#define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk
6955#define BDMA_ISR_GIF6_Pos (24U)
6956#define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos)
6957#define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk
6958#define BDMA_ISR_TCIF6_Pos (25U)
6959#define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos)
6960#define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk
6961#define BDMA_ISR_HTIF6_Pos (26U)
6962#define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos)
6963#define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk
6964#define BDMA_ISR_TEIF6_Pos (27U)
6965#define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos)
6966#define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk
6967#define BDMA_ISR_GIF7_Pos (28U)
6968#define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos)
6969#define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk
6970#define BDMA_ISR_TCIF7_Pos (29U)
6971#define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos)
6972#define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk
6973#define BDMA_ISR_HTIF7_Pos (30U)
6974#define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos)
6975#define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk
6976#define BDMA_ISR_TEIF7_Pos (31U)
6977#define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos)
6978#define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk
6980/******************* Bit definition for BDMA_IFCR register *******************/
6981#define BDMA_IFCR_CGIF0_Pos (0U)
6982#define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos)
6983#define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk
6984#define BDMA_IFCR_CTCIF0_Pos (1U)
6985#define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos)
6986#define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk
6987#define BDMA_IFCR_CHTIF0_Pos (2U)
6988#define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos)
6989#define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk
6990#define BDMA_IFCR_CTEIF0_Pos (3U)
6991#define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos)
6992#define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk
6993#define BDMA_IFCR_CGIF1_Pos (4U)
6994#define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos)
6995#define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk
6996#define BDMA_IFCR_CTCIF1_Pos (5U)
6997#define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos)
6998#define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk
6999#define BDMA_IFCR_CHTIF1_Pos (6U)
7000#define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos)
7001#define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk
7002#define BDMA_IFCR_CTEIF1_Pos (7U)
7003#define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos)
7004#define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk
7005#define BDMA_IFCR_CGIF2_Pos (8U)
7006#define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos)
7007#define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk
7008#define BDMA_IFCR_CTCIF2_Pos (9U)
7009#define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos)
7010#define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk
7011#define BDMA_IFCR_CHTIF2_Pos (10U)
7012#define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos)
7013#define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk
7014#define BDMA_IFCR_CTEIF2_Pos (11U)
7015#define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos)
7016#define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk
7017#define BDMA_IFCR_CGIF3_Pos (12U)
7018#define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos)
7019#define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk
7020#define BDMA_IFCR_CTCIF3_Pos (13U)
7021#define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos)
7022#define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk
7023#define BDMA_IFCR_CHTIF3_Pos (14U)
7024#define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos)
7025#define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk
7026#define BDMA_IFCR_CTEIF3_Pos (15U)
7027#define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos)
7028#define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk
7029#define BDMA_IFCR_CGIF4_Pos (16U)
7030#define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos)
7031#define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk
7032#define BDMA_IFCR_CTCIF4_Pos (17U)
7033#define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos)
7034#define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk
7035#define BDMA_IFCR_CHTIF4_Pos (18U)
7036#define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos)
7037#define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk
7038#define BDMA_IFCR_CTEIF4_Pos (19U)
7039#define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos)
7040#define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk
7041#define BDMA_IFCR_CGIF5_Pos (20U)
7042#define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos)
7043#define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk
7044#define BDMA_IFCR_CTCIF5_Pos (21U)
7045#define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos)
7046#define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk
7047#define BDMA_IFCR_CHTIF5_Pos (22U)
7048#define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos)
7049#define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk
7050#define BDMA_IFCR_CTEIF5_Pos (23U)
7051#define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos)
7052#define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk
7053#define BDMA_IFCR_CGIF6_Pos (24U)
7054#define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos)
7055#define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk
7056#define BDMA_IFCR_CTCIF6_Pos (25U)
7057#define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos)
7058#define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk
7059#define BDMA_IFCR_CHTIF6_Pos (26U)
7060#define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos)
7061#define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk
7062#define BDMA_IFCR_CTEIF6_Pos (27U)
7063#define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos)
7064#define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk
7065#define BDMA_IFCR_CGIF7_Pos (28U)
7066#define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos)
7067#define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk
7068#define BDMA_IFCR_CTCIF7_Pos (29U)
7069#define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos)
7070#define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk
7071#define BDMA_IFCR_CHTIF7_Pos (30U)
7072#define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos)
7073#define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk
7074#define BDMA_IFCR_CTEIF7_Pos (31U)
7075#define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos)
7076#define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk
7078/******************* Bit definition for BDMA_CCR register ********************/
7079#define BDMA_CCR_EN_Pos (0U)
7080#define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos)
7081#define BDMA_CCR_EN BDMA_CCR_EN_Msk
7082#define BDMA_CCR_TCIE_Pos (1U)
7083#define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos)
7084#define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk
7085#define BDMA_CCR_HTIE_Pos (2U)
7086#define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos)
7087#define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk
7088#define BDMA_CCR_TEIE_Pos (3U)
7089#define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos)
7090#define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk
7091#define BDMA_CCR_DIR_Pos (4U)
7092#define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos)
7093#define BDMA_CCR_DIR BDMA_CCR_DIR_Msk
7094#define BDMA_CCR_CIRC_Pos (5U)
7095#define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos)
7096#define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk
7097#define BDMA_CCR_PINC_Pos (6U)
7098#define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos)
7099#define BDMA_CCR_PINC BDMA_CCR_PINC_Msk
7100#define BDMA_CCR_MINC_Pos (7U)
7101#define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos)
7102#define BDMA_CCR_MINC BDMA_CCR_MINC_Msk
7104#define BDMA_CCR_PSIZE_Pos (8U)
7105#define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos)
7106#define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk
7107#define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos)
7108#define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos)
7110#define BDMA_CCR_MSIZE_Pos (10U)
7111#define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos)
7112#define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk
7113#define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos)
7114#define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos)
7116#define BDMA_CCR_PL_Pos (12U)
7117#define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos)
7118#define BDMA_CCR_PL BDMA_CCR_PL_Msk
7119#define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos)
7120#define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos)
7122#define BDMA_CCR_MEM2MEM_Pos (14U)
7123#define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos)
7124#define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk
7125#define BDMA_CCR_DBM_Pos (15U)
7126#define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos)
7127#define BDMA_CCR_DBM BDMA_CCR_DBM_Msk
7128#define BDMA_CCR_CT_Pos (16U)
7129#define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos)
7130#define BDMA_CCR_CT BDMA_CCR_CT_Msk
7132/****************** Bit definition for BDMA_CNDTR register *******************/
7133#define BDMA_CNDTR_NDT_Pos (0U)
7134#define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos)
7135#define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk
7137/****************** Bit definition for BDMA_CPAR register ********************/
7138#define BDMA_CPAR_PA_Pos (0U)
7139#define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)
7140#define BDMA_CPAR_PA BDMA_CPAR_PA_Msk
7142/****************** Bit definition for BDMA_CM0AR register ********************/
7143#define BDMA_CM0AR_MA_Pos (0U)
7144#define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)
7145#define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk
7147/****************** Bit definition for BDMA_CM1AR register ********************/
7148#define BDMA_CM1AR_MA_Pos (0U)
7149#define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)
7150#define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk
7152/******************************************************************************/
7153/* */
7154/* Ethernet MAC Registers bits definitions */
7155/* */
7156/******************************************************************************/
7157/* Bit definition for Ethernet MAC Configuration Register register */
7158#define ETH_MACCR_ARP_Pos (31U)
7159#define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos)
7160#define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
7161#define ETH_MACCR_SARC_Pos (28U)
7162#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos)
7163#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
7164#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
7165#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
7166#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos)
7167#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
7168#define ETH_MACCR_SARC_INSADDR1_Pos (29U)
7169#define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos)
7170#define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
7171#define ETH_MACCR_SARC_REPADDR0_Pos (28U)
7172#define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos)
7173#define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
7174#define ETH_MACCR_SARC_REPADDR1_Pos (28U)
7175#define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos)
7176#define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
7177#define ETH_MACCR_IPC_Pos (27U)
7178#define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos)
7179#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
7180#define ETH_MACCR_IPG_Pos (24U)
7181#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos)
7182#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
7183#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
7184#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
7185#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
7186#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
7187#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
7188#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
7189#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
7190#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
7191#define ETH_MACCR_GPSLCE_Pos (23U)
7192#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos)
7193#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
7194#define ETH_MACCR_S2KP_Pos (22U)
7195#define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos)
7196#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
7197#define ETH_MACCR_CST_Pos (21U)
7198#define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos)
7199#define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
7200#define ETH_MACCR_ACS_Pos (20U)
7201#define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos)
7202#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
7203#define ETH_MACCR_WD_Pos (19U)
7204#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
7205#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
7206#define ETH_MACCR_JD_Pos (17U)
7207#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
7208#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
7209#define ETH_MACCR_JE_Pos (16U)
7210#define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos)
7211#define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
7212#define ETH_MACCR_FES_Pos (14U)
7213#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
7214#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
7215#define ETH_MACCR_DM_Pos (13U)
7216#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
7217#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
7218#define ETH_MACCR_LM_Pos (12U)
7219#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
7220#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
7221#define ETH_MACCR_ECRSFD_Pos (11U)
7222#define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos)
7223#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
7224#define ETH_MACCR_DO_Pos (10U)
7225#define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos)
7226#define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
7227#define ETH_MACCR_DCRS_Pos (9U)
7228#define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos)
7229#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
7230#define ETH_MACCR_DR_Pos (8U)
7231#define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos)
7232#define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
7233#define ETH_MACCR_BL_Pos (5U)
7234#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
7235#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
7236#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos)
7237#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos)
7238#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos)
7239#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos)
7240#define ETH_MACCR_DC_Pos (4U)
7241#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
7242#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
7243#define ETH_MACCR_PRELEN_Pos (2U)
7244#define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos)
7245#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
7246#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos)
7247#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos)
7248#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos)
7249#define ETH_MACCR_TE_Pos (1U)
7250#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
7251#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
7252#define ETH_MACCR_RE_Pos (0U)
7253#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
7254#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
7255
7256/* Bit definition for Ethernet MAC Extended Configuration Register register */
7257#define ETH_MACECR_EIPG_Pos (25U)
7258#define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos)
7259#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
7260#define ETH_MACECR_EIPGEN_Pos (24U)
7261#define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos)
7262#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
7263#define ETH_MACECR_USP_Pos (18U)
7264#define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos)
7265#define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
7266#define ETH_MACECR_SPEN_Pos (17U)
7267#define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos)
7268#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
7269#define ETH_MACECR_DCRCC_Pos (16U)
7270#define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos)
7271#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
7272#define ETH_MACECR_GPSL_Pos (0U)
7273#define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos)
7274#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
7275
7276/* Bit definition for Ethernet MAC Packet Filter Register */
7277#define ETH_MACPFR_RA_Pos (31U)
7278#define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos)
7279#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
7280#define ETH_MACPFR_DNTU_Pos (21U)
7281#define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos)
7282#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
7283#define ETH_MACPFR_IPFE_Pos (20U)
7284#define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos)
7285#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
7286#define ETH_MACPFR_VTFE_Pos (16U)
7287#define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos)
7288#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
7289#define ETH_MACPFR_HPF_Pos (10U)
7290#define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos)
7291#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
7292#define ETH_MACPFR_SAF_Pos (9U)
7293#define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos)
7294#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
7295#define ETH_MACPFR_SAIF_Pos (8U)
7296#define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos)
7297#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
7298#define ETH_MACPFR_PCF_Pos (6U)
7299#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos)
7300#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
7301#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
7302#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
7303#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos)
7304#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
7305#define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
7306#define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos)
7307#define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
7308#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
7309#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos)
7310#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
7311#define ETH_MACPFR_DBF_Pos (5U)
7312#define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos)
7313#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
7314#define ETH_MACPFR_PM_Pos (4U)
7315#define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos)
7316#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
7317#define ETH_MACPFR_DAIF_Pos (3U)
7318#define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos)
7319#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
7320#define ETH_MACPFR_HMC_Pos (2U)
7321#define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos)
7322#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
7323#define ETH_MACPFR_HUC_Pos (1U)
7324#define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos)
7325#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
7326#define ETH_MACPFR_PR_Pos (0U)
7327#define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos)
7328#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
7329
7330/* Bit definition for Ethernet MAC Watchdog Timeout Register */
7331#define ETH_MACWTR_PWE_Pos (8U)
7332#define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos)
7333#define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
7334#define ETH_MACWTR_WTO_Pos (0U)
7335#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos)
7336#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
7337#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
7338#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
7339#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
7340#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
7341#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
7342#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
7343#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
7344#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
7345#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
7346#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
7347#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
7348#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
7349#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
7350#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
7351#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
7352
7353/* Bit definition for Ethernet MAC Hash Table High Register */
7354#define ETH_MACHTHR_HTH_Pos (0U)
7355#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
7356#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
7357
7358/* Bit definition for Ethernet MAC Hash Table Low Register */
7359#define ETH_MACHTLR_HTL_Pos (0U)
7360#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
7361#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
7362
7363/* Bit definition for Ethernet MAC VLAN Tag Register */
7364#define ETH_MACVTR_EIVLRXS_Pos (31U)
7365#define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos)
7366#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
7367#define ETH_MACVTR_EIVLS_Pos (28U)
7368#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos)
7369#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
7370#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
7371#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
7372#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos)
7373#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
7374#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)
7375#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos)
7376#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
7377#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)
7378#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos)
7379#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
7380#define ETH_MACVTR_ERIVLT_Pos (27U)
7381#define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos)
7382#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
7383#define ETH_MACVTR_EDVLP_Pos (26U)
7384#define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos)
7385#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
7386#define ETH_MACVTR_VTHM_Pos (25U)
7387#define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos)
7388#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
7389#define ETH_MACVTR_EVLRXS_Pos (24U)
7390#define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos)
7391#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
7392#define ETH_MACVTR_EVLS_Pos (21U)
7393#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos)
7394#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
7395#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
7396#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
7397#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos)
7398#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
7399#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)
7400#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos)
7401#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
7402#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)
7403#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos)
7404#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
7405#define ETH_MACVTR_DOVLTC_Pos (20U)
7406#define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos)
7407#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
7408#define ETH_MACVTR_ERSVLM_Pos (19U)
7409#define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos)
7410#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
7411#define ETH_MACVTR_ESVL_Pos (18U)
7412#define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos)
7413#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
7414#define ETH_MACVTR_VTIM_Pos (17U)
7415#define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos)
7416#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
7417#define ETH_MACVTR_ETV_Pos (16U)
7418#define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos)
7419#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
7420#define ETH_MACVTR_VL_Pos (0U)
7421#define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos)
7422#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
7423#define ETH_MACVTR_VL_UP_Pos (13U)
7424#define ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos)
7425#define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */
7426#define ETH_MACVTR_VL_CFIDEI_Pos (12U)
7427#define ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos)
7428#define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7429#define ETH_MACVTR_VL_VID_Pos (0U)
7430#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos)
7431#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
7432
7433/* Bit definition for Ethernet MAC VLAN Hash Table Register */
7434#define ETH_MACVHTR_VLHT_Pos (0U)
7435#define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos)
7436#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
7437
7438/* Bit definition for Ethernet MAC VLAN Incl Register */
7439#define ETH_MACVIR_VLTI_Pos (20U)
7440#define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos)
7441#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
7442#define ETH_MACVIR_CSVL_Pos (19U)
7443#define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos)
7444#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
7445#define ETH_MACVIR_VLP_Pos (18U)
7446#define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos)
7447#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
7448#define ETH_MACVIR_VLC_Pos (16U)
7449#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos)
7450#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
7451#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
7452#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
7453#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos)
7454#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
7455#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
7456#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos)
7457#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
7458#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
7459#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos)
7460#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
7461#define ETH_MACVIR_VLT_Pos (0U)
7462#define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos)
7463#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
7464#define ETH_MACVIR_VLT_UP_Pos (13U)
7465#define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos)
7466#define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
7467#define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
7468#define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos)
7469#define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7470#define ETH_MACVIR_VLT_VID_Pos (0U)
7471#define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos)
7472#define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
7473
7474/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
7475#define ETH_MACIVIR_VLTI_Pos (20U)
7476#define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos)
7477#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
7478#define ETH_MACIVIR_CSVL_Pos (19U)
7479#define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos)
7480#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
7481#define ETH_MACIVIR_VLP_Pos (18U)
7482#define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos)
7483#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
7484#define ETH_MACIVIR_VLC_Pos (16U)
7485#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos)
7486#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
7487#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
7488#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
7489#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos)
7490#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
7491#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
7492#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos)
7493#define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
7494#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
7495#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos)
7496#define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
7497#define ETH_MACIVIR_VLT_Pos (0U)
7498#define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos)
7499#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
7500#define ETH_MACIVIR_VLT_UP_Pos (13U)
7501#define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos)
7502#define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
7503#define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
7504#define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos)
7505#define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7506#define ETH_MACIVIR_VLT_VID_Pos (0U)
7507#define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos)
7508#define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
7509
7510/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
7511#define ETH_MACTFCR_PT_Pos (16U)
7512#define ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos)
7513#define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */
7514#define ETH_MACTFCR_DZPQ_Pos (7U)
7515#define ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos)
7516#define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
7517#define ETH_MACTFCR_PLT_Pos (4U)
7518#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos)
7519#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
7520#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
7521#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
7522#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos)
7523#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
7524#define ETH_MACTFCR_PLT_MINUS36_Pos (5U)
7525#define ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos)
7526#define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
7527#define ETH_MACTFCR_PLT_MINUS144_Pos (4U)
7528#define ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos)
7529#define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
7530#define ETH_MACTFCR_PLT_MINUS256_Pos (6U)
7531#define ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos)
7532#define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
7533#define ETH_MACTFCR_PLT_MINUS512_Pos (4U)
7534#define ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos)
7535#define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
7536#define ETH_MACTFCR_TFE_Pos (1U)
7537#define ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos)
7538#define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
7539#define ETH_MACTFCR_FCB_Pos (0U)
7540#define ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos)
7541#define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
7542
7543/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
7544#define ETH_MACRFCR_UP_Pos (1U)
7545#define ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos)
7546#define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
7547#define ETH_MACRFCR_RFE_Pos (0U)
7548#define ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos)
7549#define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
7550
7551/* Bit definition for Ethernet MAC Interrupt Status Register */
7552#define ETH_MACISR_RXSTSIS_Pos (14U)
7553#define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos)
7554#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
7555#define ETH_MACISR_TXSTSIS_Pos (13U)
7556#define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos)
7557#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
7558#define ETH_MACISR_TSIS_Pos (12U)
7559#define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos)
7560#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
7561#define ETH_MACISR_MMCTXIS_Pos (10U)
7562#define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos)
7563#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
7564#define ETH_MACISR_MMCRXIS_Pos (9U)
7565#define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos)
7566#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
7567#define ETH_MACISR_MMCIS_Pos (8U)
7568#define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos)
7569#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
7570#define ETH_MACISR_LPIIS_Pos (5U)
7571#define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos)
7572#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
7573#define ETH_MACISR_PMTIS_Pos (4U)
7574#define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos)
7575#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
7576#define ETH_MACISR_PHYIS_Pos (3U)
7577#define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos)
7578#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
7579
7580/* Bit definition for Ethernet MAC Interrupt Enable Register */
7581#define ETH_MACIER_RXSTSIE_Pos (14U)
7582#define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos)
7583#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
7584#define ETH_MACIER_TXSTSIE_Pos (13U)
7585#define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos)
7586#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
7587#define ETH_MACIER_TSIE_Pos (12U)
7588#define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos)
7589#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
7590#define ETH_MACIER_LPIIE_Pos (5U)
7591#define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos)
7592#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
7593#define ETH_MACIER_PMTIE_Pos (4U)
7594#define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos)
7595#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
7596#define ETH_MACIER_PHYIE_Pos (3U)
7597#define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos)
7598#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
7599
7600/* Bit definition for Ethernet MAC Rx Tx Status Register */
7601#define ETH_MACRXTXSR_RWT_Pos (8U)
7602#define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos)
7603#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
7604#define ETH_MACRXTXSR_EXCOL_Pos (5U)
7605#define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos)
7606#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
7607#define ETH_MACRXTXSR_LCOL_Pos (4U)
7608#define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos)
7609#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
7610#define ETH_MACRXTXSR_EXDEF_Pos (3U)
7611#define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos)
7612#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
7613#define ETH_MACRXTXSR_LCARR_Pos (2U)
7614#define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos)
7615#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
7616#define ETH_MACRXTXSR_NCARR_Pos (1U)
7617#define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos)
7618#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
7619#define ETH_MACRXTXSR_TJT_Pos (0U)
7620#define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos)
7621#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
7622
7623/* Bit definition for Ethernet MAC PMT Control Status Register */
7624#define ETH_MACPCSR_RWKFILTRST_Pos (31U)
7625#define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos)
7626#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
7627#define ETH_MACPCSR_RWKPTR_Pos (24U)
7628#define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos)
7629#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
7630#define ETH_MACPCSR_RWKPFE_Pos (10U)
7631#define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos)
7632#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
7633#define ETH_MACPCSR_GLBLUCAST_Pos (9U)
7634#define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos)
7635#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
7636#define ETH_MACPCSR_RWKPRCVD_Pos (6U)
7637#define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos)
7638#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
7639#define ETH_MACPCSR_MGKPRCVD_Pos (5U)
7640#define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos)
7641#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
7642#define ETH_MACPCSR_RWKPKTEN_Pos (2U)
7643#define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos)
7644#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
7645#define ETH_MACPCSR_MGKPKTEN_Pos (1U)
7646#define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos)
7647#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
7648#define ETH_MACPCSR_PWRDWN_Pos (0U)
7649#define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos)
7650#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
7651
7652/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
7653#define ETH_MACRWUPFR_D_Pos (0U)
7654#define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos)
7655#define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
7656
7657/* Bit definition for Ethernet MAC LPI Control Status Register */
7658#define ETH_MACLCSR_LPITCSE_Pos (21U)
7659#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos)
7660#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
7661#define ETH_MACLCSR_LPITE_Pos (20U)
7662#define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos)
7663#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
7664#define ETH_MACLCSR_LPITXA_Pos (19U)
7665#define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos)
7666#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
7667#define ETH_MACLCSR_PLS_Pos (17U)
7668#define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos)
7669#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
7670#define ETH_MACLCSR_LPIEN_Pos (16U)
7671#define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos)
7672#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
7673#define ETH_MACLCSR_RLPIST_Pos (9U)
7674#define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos)
7675#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
7676#define ETH_MACLCSR_TLPIST_Pos (8U)
7677#define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos)
7678#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
7679#define ETH_MACLCSR_RLPIEX_Pos (3U)
7680#define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos)
7681#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
7682#define ETH_MACLCSR_RLPIEN_Pos (2U)
7683#define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos)
7684#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
7685#define ETH_MACLCSR_TLPIEX_Pos (1U)
7686#define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos)
7687#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
7688#define ETH_MACLCSR_TLPIEN_Pos (0U)
7689#define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos)
7690#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
7691
7692/* Bit definition for Ethernet MAC LPI Timers Control Register */
7693#define ETH_MACLTCR_LST_Pos (16U)
7694#define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos)
7695#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
7696#define ETH_MACLTCR_TWT_Pos (0U)
7697#define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos)
7698#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
7699
7700/* Bit definition for Ethernet MAC LPI Entry Timer Register */
7701#define ETH_MACLETR_LPIET_Pos (0U)
7702#define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos)
7703#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
7704
7705/* Bit definition for Ethernet MAC 1US Tic Counter Register */
7706#define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
7707#define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos)
7708#define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
7709
7710/* Bit definition for Ethernet MAC Version Register */
7711#define ETH_MACVR_USERVER_Pos (8U)
7712#define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos)
7713#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
7714#define ETH_MACVR_SNPSVER_Pos (0U)
7715#define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos)
7716#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
7717
7718/* Bit definition for Ethernet MAC Debug Register */
7719#define ETH_MACDR_TFCSTS_Pos (17U)
7720#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos)
7721#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
7722#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
7723#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
7724#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos)
7725#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
7726#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
7727#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos)
7728#define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
7729#define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
7730#define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos)
7731#define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
7732#define ETH_MACDR_TPESTS_Pos (16U)
7733#define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos)
7734#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
7735#define ETH_MACDR_RFCFCSTS_Pos (1U)
7736#define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos)
7737#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
7738#define ETH_MACDR_RPESTS_Pos (0U)
7739#define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos)
7740#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
7741
7742/* Bit definition for Ethernet MAC HW Feature0 Register */
7743#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
7744#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos)
7745#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
7746#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
7747#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
7748#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos)
7749#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
7750#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)
7751#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos)
7752#define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
7753#define ETH_MACHWF0R_SAVLANINS_Pos (27U)
7754#define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos)
7755#define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
7756#define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
7757#define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos)
7758#define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
7759#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
7760#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos)
7761#define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
7762#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
7763#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos)
7764#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
7765#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
7766#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos)
7767#define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
7768#define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
7769#define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos)
7770#define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
7771#define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
7772#define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos)
7773#define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
7774#define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
7775#define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos)
7776#define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
7777#define ETH_MACHWF0R_RXCOESEL_Pos (16U)
7778#define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos)
7779#define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
7780#define ETH_MACHWF0R_TXCOESEL_Pos (14U)
7781#define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos)
7782#define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
7783#define ETH_MACHWF0R_EEESEL_Pos (13U)
7784#define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos)
7785#define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
7786#define ETH_MACHWF0R_TSSEL_Pos (12U)
7787#define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos)
7788#define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
7789#define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
7790#define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos)
7791#define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
7792#define ETH_MACHWF0R_MMCSEL_Pos (8U)
7793#define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos)
7794#define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
7795#define ETH_MACHWF0R_MGKSEL_Pos (7U)
7796#define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos)
7797#define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
7798#define ETH_MACHWF0R_RWKSEL_Pos (6U)
7799#define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos)
7800#define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
7801#define ETH_MACHWF0R_SMASEL_Pos (5U)
7802#define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos)
7803#define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
7804#define ETH_MACHWF0R_VLHASH_Pos (4U)
7805#define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos)
7806#define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
7807#define ETH_MACHWF0R_PCSSEL_Pos (3U)
7808#define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos)
7809#define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
7810#define ETH_MACHWF0R_HDSEL_Pos (2U)
7811#define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos)
7812#define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
7813#define ETH_MACHWF0R_GMIISEL_Pos (1U)
7814#define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos)
7815#define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
7816#define ETH_MACHWF0R_MIISEL_Pos (0U)
7817#define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos)
7818#define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
7819
7820/* Bit definition for Ethernet MAC HW Feature1 Register */
7821#define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
7822#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos)
7823#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
7824#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
7825#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos)
7826#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
7827#define ETH_MACHWF1R_AVSEL_Pos (20U)
7828#define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos)
7829#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
7830#define ETH_MACHWF1R_DBGMEMA_Pos (19U)
7831#define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos)
7832#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
7833#define ETH_MACHWF1R_TSOEN_Pos (18U)
7834#define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos)
7835#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
7836#define ETH_MACHWF1R_SPHEN_Pos (17U)
7837#define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos)
7838#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
7839#define ETH_MACHWF1R_DCBEN_Pos (16U)
7840#define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos)
7841#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
7842#define ETH_MACHWF1R_ADDR64_Pos (14U)
7843#define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos)
7844#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
7845#define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos)
7846#define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos)
7847#define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos)
7848#define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
7849#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos)
7850#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
7851#define ETH_MACHWF1R_PTOEN_Pos (12U)
7852#define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos)
7853#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
7854#define ETH_MACHWF1R_OSTEN_Pos (11U)
7855#define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos)
7856#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
7857#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
7858#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos)
7859#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
7860#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
7861#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos)
7862#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
7863
7864/* Bit definition for Ethernet MAC HW Feature2 Register */
7865#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
7866#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos)
7867#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
7868#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
7869#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos)
7870#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
7871#define ETH_MACHWF2R_TXCHCNT_Pos (18U)
7872#define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos)
7873#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
7874#define ETH_MACHWF2R_RXCHCNT_Pos (13U)
7875#define ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos)
7876#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
7877#define ETH_MACHWF2R_TXQCNT_Pos (6U)
7878#define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos)
7879#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
7880#define ETH_MACHWF2R_RXQCNT_Pos (0U)
7881#define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos)
7882#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
7883
7884/* Bit definition for Ethernet MAC MDIO Address Register */
7885#define ETH_MACMDIOAR_PSE_Pos (27U)
7886#define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos)
7887#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
7888#define ETH_MACMDIOAR_BTB_Pos (26U)
7889#define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos)
7890#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
7891#define ETH_MACMDIOAR_PA_Pos (21U)
7892#define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos)
7893#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
7894#define ETH_MACMDIOAR_RDA_Pos (16U)
7895#define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos)
7896#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
7897#define ETH_MACMDIOAR_NTC_Pos (12U)
7898#define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos)
7899#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
7900#define ETH_MACMDIOAR_CR_Pos (8U)
7901#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos)
7902#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
7903#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
7904#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
7905#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos)
7906#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
7907#define ETH_MACMDIOAR_CR_DIV16_Pos (9U)
7908#define ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos)
7909#define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
7910#define ETH_MACMDIOAR_CR_DIV26_Pos (8U)
7911#define ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos)
7912#define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
7913#define ETH_MACMDIOAR_CR_DIV102_Pos (10U)
7914#define ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos)
7915#define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
7916#define ETH_MACMDIOAR_CR_DIV124_Pos (8U)
7917#define ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos)
7918#define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
7919#define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)
7920#define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos)
7921#define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
7922#define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)
7923#define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos)
7924#define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
7925#define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)
7926#define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos)
7927#define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
7928#define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)
7929#define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos)
7930#define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
7931#define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)
7932#define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos)
7933#define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
7934#define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)
7935#define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos)
7936#define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
7937#define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)
7938#define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos)
7939#define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
7940#define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)
7941#define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos)
7942#define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
7943#define ETH_MACMDIOAR_SKAP_Pos (4U)
7944#define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos)
7945#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
7946#define ETH_MACMDIOAR_MOC_Pos (2U)
7947#define ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos)
7948#define ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */
7949#define ETH_MACMDIOAR_MOC_WR_Pos (2U)
7950#define ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos)
7951#define ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */
7952#define ETH_MACMDIOAR_MOC_PRDIA_Pos (3U)
7953#define ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos)
7954#define ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
7955#define ETH_MACMDIOAR_MOC_RD_Pos (2U)
7956#define ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos)
7957#define ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */
7958#define ETH_MACMDIOAR_C45E_Pos (1U)
7959#define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos)
7960#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
7961#define ETH_MACMDIOAR_MB_Pos (0U)
7962#define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos)
7963#define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */
7964
7965/* Bit definition for Ethernet MAC MDIO Data Register */
7966#define ETH_MACMDIODR_RA_Pos (16U)
7967#define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos)
7968#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */
7969#define ETH_MACMDIODR_MD_Pos (0U)
7970#define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos)
7971#define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */
7972
7973/* Bit definition for Ethernet ARP Address Register */
7974#define ETH_MACARPAR_ARPPA_Pos (0U)
7975#define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos)
7976#define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */
7977
7978/* Bit definition for Ethernet MAC Address 0 High Register */
7979#define ETH_MACA0HR_AE_Pos (31U)
7980#define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos)
7981#define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/
7982#define ETH_MACA0HR_ADDRHI_Pos (0U)
7983#define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos)
7984#define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/
7985
7986/* Bit definition for Ethernet MAC Address 0 Low Register */
7987#define ETH_MACA0LR_ADDRLO_Pos (0U)
7988#define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos)
7989#define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/
7990
7991/* Bit definition for Ethernet MAC Address 1 High Register */
7992#define ETH_MACA1HR_AE_Pos (31U)
7993#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
7994#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address Enable*/
7995#define ETH_MACA1HR_SA_Pos (30U)
7996#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
7997#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source Address */
7998#define ETH_MACA1HR_MBC_Pos (24U)
7999#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
8000#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
8001#define ETH_MACA1HR_ADDRHI_Pos (0U)
8002#define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos)
8003#define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/
8004
8005/* Bit definition for Ethernet MAC Address 1 Low Register */
8006#define ETH_MACA1LR_ADDRLO_Pos (0U)
8007#define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos)
8008#define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/
8009
8010/* Bit definition for Ethernet MAC Address 2 High Register */
8011#define ETH_MACA2HR_AE_Pos (31U)
8012#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
8013#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address Enable*/
8014#define ETH_MACA2HR_SA_Pos (30U)
8015#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
8016#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source Address */
8017#define ETH_MACA2HR_MBC_Pos (24U)
8018#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
8019#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
8020#define ETH_MACA2HR_ADDRHI_Pos (0U)
8021#define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos)
8022#define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/
8023
8024/* Bit definition for Ethernet MAC Address 2 Low Register */
8025#define ETH_MACA2LR_ADDRLO_Pos (0U)
8026#define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos)
8027#define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/
8028
8029/* Bit definition for Ethernet MAC Address 3 High Register */
8030#define ETH_MACA3HR_AE_Pos (31U)
8031#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
8032#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address Enable*/
8033#define ETH_MACA3HR_SA_Pos (30U)
8034#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
8035#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source Address */
8036#define ETH_MACA3HR_MBC_Pos (24U)
8037#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
8038#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
8039#define ETH_MACA3HR_ADDRHI_Pos (0U)
8040#define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos)
8041#define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/
8042
8043/* Bit definition for Ethernet MAC Address 3 Low Register */
8044#define ETH_MACA3LR_ADDRLO_Pos (0U)
8045#define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos)
8046#define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/
8047
8048/* Bit definition for Ethernet MAC Address High Register */
8049#define ETH_MACAHR_AE_Pos (31U)
8050#define ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos)
8051#define ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */
8052#define ETH_MACAHR_SA_Pos (30U)
8053#define ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos)
8054#define ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */
8055#define ETH_MACAHR_MBC_Pos (24U)
8056#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos)
8057#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
8058#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
8059#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
8060#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
8061#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
8062#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
8063#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
8064#define ETH_MACAHR_MACAH_Pos (0U)
8065#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos)
8066#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
8067
8068/* Bit definition for Ethernet MAC Address Low Register */
8069#define ETH_MACALR_MACAL_Pos (0U)
8070#define ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos)
8071#define ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */
8072
8073/* Bit definition for Ethernet MMC Control Register */
8074#define ETH_MMCCR_UCDBC_Pos (8U)
8075#define ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos)
8076#define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */
8077#define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
8078#define ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos)
8079#define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */
8080#define ETH_MMCCR_CNTPRST_Pos (4U)
8081#define ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos)
8082#define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */
8083#define ETH_MMCCR_CNTFREEZ_Pos (3U)
8084#define ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos)
8085#define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */
8086#define ETH_MMCCR_RSTONRD_Pos (2U)
8087#define ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos)
8088#define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */
8089#define ETH_MMCCR_CNTSTOPRO_Pos (1U)
8090#define ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos)
8091#define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */
8092#define ETH_MMCCR_CNTRST_Pos (0U)
8093#define ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos)
8094#define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */
8095
8096/* Bit definition for Ethernet MMC Rx Interrupt Register */
8097#define ETH_MMCRIR_RXLPITRCIS_Pos (27U)
8098#define ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos)
8099#define ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */
8100#define ETH_MMCRIR_RXLPIUSCIS_Pos (26U)
8101#define ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos)
8102#define ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */
8103#define ETH_MMCRIR_RXUCGPIS_Pos (17U)
8104#define ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos)
8105#define ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */
8106#define ETH_MMCRIR_RXALGNERPIS_Pos (6U)
8107#define ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos)
8108#define ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */
8109#define ETH_MMCRIR_RXCRCERPIS_Pos (5U)
8110#define ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos)
8111#define ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */
8112
8113/* Bit definition for Ethernet MMC Tx Interrupt Register */
8114#define ETH_MMCTIR_TXLPITRCIS_Pos (27U)
8115#define ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos)
8116#define ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */
8117#define ETH_MMCTIR_TXLPIUSCIS_Pos (26U)
8118#define ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos)
8119#define ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */
8120#define ETH_MMCTIR_TXGPKTIS_Pos (21U)
8121#define ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos)
8122#define ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */
8123#define ETH_MMCTIR_TXMCOLGPIS_Pos (15U)
8124#define ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos)
8125#define ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
8126#define ETH_MMCTIR_TXSCOLGPIS_Pos (14U)
8127#define ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos)
8128#define ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
8129
8130/* Bit definition for Ethernet MMC Rx interrupt Mask register */
8131#define ETH_MMCRIMR_RXLPITRCIM_Pos (27U)
8132#define ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos)
8133#define ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */
8134#define ETH_MMCRIMR_RXLPIUSCIM_Pos (26U)
8135#define ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos)
8136#define ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */
8137#define ETH_MMCRIMR_RXUCGPIM_Pos (17U)
8138#define ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos)
8139#define ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
8140#define ETH_MMCRIMR_RXALGNERPIM_Pos (6U)
8141#define ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos)
8142#define ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
8143#define ETH_MMCRIMR_RXCRCERPIM_Pos (5U)
8144#define ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos)
8145#define ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */
8146
8147/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
8148#define ETH_MMCTIMR_TXLPITRCIM_Pos (27U)
8149#define ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos)
8150#define ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/
8151#define ETH_MMCTIMR_TXLPIUSCIM_Pos (26U)
8152#define ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos)
8153#define ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/
8154#define ETH_MMCTIMR_TXGPKTIM_Pos (21U)
8155#define ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos)
8156#define ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/
8157#define ETH_MMCTIMR_TXMCOLGPIM_Pos (15U)
8158#define ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos)
8159#define ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
8160#define ETH_MMCTIMR_TXSCOLGPIM_Pos (14U)
8161#define ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos)
8162#define ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
8163
8164/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
8165#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U)
8166#define ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos)
8167#define ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
8168
8169/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
8170#define ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U)
8171#define ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos)
8172#define ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
8173
8174/* Bit definition for Ethernet MMC Tx Packet Count Good Register */
8175#define ETH_MMCTPCGR_TXPKTG_Pos (0U)
8176#define ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos)
8177#define ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
8178
8179/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
8180#define ETH_MMCRCRCEPR_RXCRCERR_Pos (0U)
8181#define ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos)
8182#define ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
8183
8184/* Bit definition for Ethernet MMC Rx alignment error packets register */
8185#define ETH_MMCRAEPR_RXALGNERR_Pos (0U)
8186#define ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos)
8187#define ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
8188
8189/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
8190#define ETH_MMCRUPGR_RXUCASTG_Pos (0U)
8191#define ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos)
8192#define ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
8193
8194/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
8195#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U)
8196#define ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos)
8197#define ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
8198
8199/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
8200#define ETH_MMCTLPITCR_TXLPITRC_Pos (0U)
8201#define ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos)
8202#define ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
8203
8204/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
8205#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U)
8206#define ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos)
8207#define ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
8208
8209/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
8210#define ETH_MMCRLPITCR_RXLPITRC_Pos (0U)
8211#define ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos)
8212#define ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
8213
8214/* Bit definition for Ethernet MAC L3 L4 Control Register */
8215#define ETH_MACL3L4CR_L4DPIM_Pos (21U)
8216#define ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos)
8217#define ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
8218#define ETH_MACL3L4CR_L4DPM_Pos (20U)
8219#define ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos)
8220#define ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */
8221#define ETH_MACL3L4CR_L4SPIM_Pos (19U)
8222#define ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos)
8223#define ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
8224#define ETH_MACL3L4CR_L4SPM_Pos (18U)
8225#define ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos)
8226#define ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */
8227#define ETH_MACL3L4CR_L4PEN_Pos (16U)
8228#define ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos)
8229#define ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */
8230#define ETH_MACL3L4CR_L3HDBM_Pos (11U)
8231#define ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos)
8232#define ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
8233#define ETH_MACL3L4CR_L3HSBM_Pos (6U)
8234#define ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos)
8235#define ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
8236#define ETH_MACL3L4CR_L3DAIM_Pos (5U)
8237#define ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos)
8238#define ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
8239#define ETH_MACL3L4CR_L3DAM_Pos (4U)
8240#define ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos)
8241#define ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */
8242#define ETH_MACL3L4CR_L3SAIM_Pos (3U)
8243#define ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos)
8244#define ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
8245#define ETH_MACL3L4CR_L3SAM_Pos (2U)
8246#define ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos)
8247#define ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/
8248#define ETH_MACL3L4CR_L3PEN_Pos (0U)
8249#define ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos)
8250#define ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */
8251
8252/* Bit definition for Ethernet MAC L4 Address Register */
8253#define ETH_MACL4AR_L4DP_Pos (16U)
8254#define ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos)
8255#define ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */
8256#define ETH_MACL4AR_L4SP_Pos (0U)
8257#define ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos)
8258#define ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */
8259
8260/* Bit definition for Ethernet MAC L3 Address0 Register */
8261#define ETH_MACL3A0R_L3A0_Pos (0U)
8262#define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos)
8263#define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
8264
8265/* Bit definition for Ethernet MAC L4 Address1 Register */
8266#define ETH_MACL3A1R_L3A1_Pos (0U)
8267#define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos)
8268#define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
8269
8270/* Bit definition for Ethernet MAC L4 Address2 Register */
8271#define ETH_MACL3A2R_L3A2_Pos (0U)
8272#define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos)
8273#define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
8274
8275/* Bit definition for Ethernet MAC L4 Address3 Register */
8276#define ETH_MACL3A3R_L3A3_Pos (0U)
8277#define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos)
8278#define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
8279
8280/* Bit definition for Ethernet MAC Timestamp Control Register */
8281#define ETH_MACTSCR_TXTSSTSM_Pos (24U)
8282#define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos)
8283#define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */
8284#define ETH_MACTSCR_CSC_Pos (19U)
8285#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos)
8286#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
8287#define ETH_MACTSCR_TSENMACADDR_Pos (18U)
8288#define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos)
8289#define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */
8290#define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
8291#define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos)
8292#define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */
8293#define ETH_MACTSCR_TSMSTRENA_Pos (15U)
8294#define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos)
8295#define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */
8296#define ETH_MACTSCR_TSEVNTENA_Pos (14U)
8297#define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos)
8298#define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */
8299#define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
8300#define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos)
8301#define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
8302#define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
8303#define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos)
8304#define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
8305#define ETH_MACTSCR_TSIPENA_Pos (11U)
8306#define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos)
8307#define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */
8308#define ETH_MACTSCR_TSVER2ENA_Pos (10U)
8309#define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos)
8310#define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */
8311#define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
8312#define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos)
8313#define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */
8314#define ETH_MACTSCR_TSENALL_Pos (8U)
8315#define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos)
8316#define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */
8317#define ETH_MACTSCR_TSADDREG_Pos (5U)
8318#define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos)
8319#define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */
8320#define ETH_MACTSCR_TSUPDT_Pos (3U)
8321#define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos)
8322#define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */
8323#define ETH_MACTSCR_TSINIT_Pos (2U)
8324#define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos)
8325#define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */
8326#define ETH_MACTSCR_TSCFUPDT_Pos (1U)
8327#define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos)
8328#define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/
8329#define ETH_MACTSCR_TSENA_Pos (0U)
8330#define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos)
8331#define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */
8332
8333/* Bit definition for Ethernet MAC Sub-second Increment Register */
8334#define ETH_MACMACSSIR_SSINC_Pos (16U)
8335#define ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos)
8336#define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */
8337#define ETH_MACMACSSIR_SNSINC_Pos (8U)
8338#define ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos)
8339#define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */
8340
8341/* Bit definition for Ethernet MAC System Time Seconds Register */
8342#define ETH_MACSTSR_TSS_Pos (0U)
8343#define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos)
8344#define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */
8345
8346/* Bit definition for Ethernet MAC System Time Nanoseconds Register */
8347#define ETH_MACSTNR_TSSS_Pos (0U)
8348#define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos)
8349#define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */
8350
8351/* Bit definition for Ethernet MAC System Time Seconds Update Register */
8352#define ETH_MACSTSUR_TSS_Pos (0U)
8353#define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos)
8354#define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */
8355
8356/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
8357#define ETH_MACSTNUR_ADDSUB_Pos (31U)
8358#define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos)
8359#define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */
8360#define ETH_MACSTNUR_TSSS_Pos (0U)
8361#define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos)
8362#define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */
8363
8364/* Bit definition for Ethernet MAC Timestamp Addend Register */
8365#define ETH_MACTSAR_TSAR_Pos (0U)
8366#define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos)
8367#define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */
8368
8369/* Bit definition for Ethernet MAC Timestamp Status Register */
8370#define ETH_MACTSSR_ATSNS_Pos (25U)
8371#define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos)
8372#define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */
8373#define ETH_MACTSSR_ATSSTM_Pos (24U)
8374#define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos)
8375#define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */
8376#define ETH_MACTSSR_ATSSTN_Pos (16U)
8377#define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos)
8378#define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */
8379#define ETH_MACTSSR_TXTSSIS_Pos (15U)
8380#define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos)
8381#define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */
8382#define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
8383#define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos)
8384#define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */
8385#define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
8386#define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos)
8387#define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/
8388#define ETH_MACTSSR_TSTARGT0_Pos (1U)
8389#define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos)
8390#define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */
8391#define ETH_MACTSSR_TSSOVF_Pos (0U)
8392#define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos)
8393#define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */
8394
8395/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
8396#define ETH_MACTTSSNR_TXTSSMIS_Pos (31U)
8397#define ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos)
8398#define ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */
8399#define ETH_MACTTSSNR_TXTSSLO_Pos (0U)
8400#define ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos)
8401#define ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */
8402
8403/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
8404#define ETH_MACTTSSSR_TXTSSHI_Pos (0U)
8405#define ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos)
8406#define ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */
8407
8408/* Bit definition for Ethernet MAC Auxiliary Control Register*/
8409#define ETH_MACACR_ATSEN3_Pos (7U)
8410#define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos)
8411#define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */
8412#define ETH_MACACR_ATSEN2_Pos (6U)
8413#define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos)
8414#define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */
8415#define ETH_MACACR_ATSEN1_Pos (5U)
8416#define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos)
8417#define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */
8418#define ETH_MACACR_ATSEN0_Pos (4U)
8419#define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos)
8420#define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */
8421#define ETH_MACACR_ATSFC_Pos (0U)
8422#define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos)
8423#define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */
8424
8425/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
8426#define ETH_MACATSNR_AUXTSLO_Pos (0U)
8427#define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos)
8428#define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */
8429
8430/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
8431#define ETH_MACATSSR_AUXTSHI_Pos (0U)
8432#define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos)
8433#define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */
8434
8435/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
8436#define ETH_MACTSIACR_OSTIAC_Pos (0U)
8437#define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos)
8438#define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */
8439
8440/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
8441#define ETH_MACTSEACR_OSTEAC_Pos (0U)
8442#define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos)
8443#define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */
8444
8445/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
8446#define ETH_MACTSICNR_TSIC_Pos (0U)
8447#define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos)
8448#define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */
8449
8450/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
8451#define ETH_MACTSECNR_TSEC_Pos (0U)
8452#define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos)
8453#define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */
8454
8455/* Bit definition for Ethernet MAC PPS Control Register */
8456#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
8457#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos)
8458#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */
8459#define ETH_MACPPSCR_PPSEN0_Pos (4U)
8460#define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos)
8461#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */
8462#define ETH_MACPPSCR_PPSCTRL_Pos (0U)
8463#define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos)
8464#define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */
8465
8466/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
8467#define ETH_MACPPSTTSR_TSTRH0_Pos (0U)
8468#define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos)
8469#define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */
8470
8471/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
8472#define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)
8473#define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos)
8474#define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */
8475#define ETH_MACPPSTTNR_TTSL0_Pos (0U)
8476#define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos)
8477#define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */
8478
8479/* Bit definition for Ethernet MAC PPS Interval Register */
8480#define ETH_MACPPSIR_PPSINT0_Pos (0U)
8481#define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos)
8482#define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */
8483
8484/* Bit definition for Ethernet MAC PPS Width Register */
8485#define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)
8486#define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos)
8487#define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */
8488
8489/* Bit definition for Ethernet MAC PTP Offload Control Register */
8490#define ETH_MACPOCR_DN_Pos (8U)
8491#define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos)
8492#define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */
8493#define ETH_MACPOCR_DRRDIS_Pos (6U)
8494#define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos)
8495#define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */
8496#define ETH_MACPOCR_APDREQTRIG_Pos (5U)
8497#define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos)
8498#define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */
8499#define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
8500#define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos)
8501#define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */
8502#define ETH_MACPOCR_APDREQEN_Pos (2U)
8503#define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos)
8504#define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */
8505#define ETH_MACPOCR_ASYNCEN_Pos (1U)
8506#define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos)
8507#define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */
8508#define ETH_MACPOCR_PTOEN_Pos (0U)
8509#define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos)
8510#define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */
8511
8512/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
8513#define ETH_MACSPI0R_SPI0_Pos (0U)
8514#define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos)
8515#define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */
8516
8517/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
8518#define ETH_MACSPI1R_SPI1_Pos (0U)
8519#define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos)
8520#define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */
8521
8522/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
8523#define ETH_MACSPI2R_SPI2_Pos (0U)
8524#define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos)
8525#define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */
8526
8527/* Bit definition for Ethernet MAC Log Message Interval Register */
8528#define ETH_MACLMIR_LMPDRI_Pos (24U)
8529#define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos)
8530#define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */
8531#define ETH_MACLMIR_DRSYNCR_Pos (8U)
8532#define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos)
8533#define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */
8534#define ETH_MACLMIR_LSI_Pos (0U)
8535#define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos)
8536#define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */
8537
8538/* Bit definition for Ethernet MTL Operation Mode Register */
8539#define ETH_MTLOMR_CNTCLR_Pos (9U)
8540#define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos)
8541#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
8542#define ETH_MTLOMR_CNTPRST_Pos (8U)
8543#define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos)
8544#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
8545#define ETH_MTLOMR_DTXSTS_Pos (1U)
8546#define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos)
8547#define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */
8548
8549/* Bit definition for Ethernet MTL Interrupt Status Register */
8550#define ETH_MTLISR_MACIS_Pos (16U)
8551#define ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos)
8552#define ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */
8553#define ETH_MTLISR_QIS_Pos (0U)
8554#define ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos)
8555#define ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */
8556
8557/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
8558#define ETH_MTLTQOMR_TTC_Pos (4U)
8559#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos)
8560#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
8561#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
8562#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
8563#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
8564#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
8565#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
8566#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
8567#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
8568#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
8569#define ETH_MTLTQOMR_TSF_Pos (1U)
8570#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos)
8571#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
8572#define ETH_MTLTQOMR_FTQ_Pos (0U)
8573#define ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos)
8574#define ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */
8575
8576/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
8577#define ETH_MTLTQUR_UFCNTOVF_Pos (11U)
8578#define ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos)
8579#define ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
8580#define ETH_MTLTQUR_UFPKTCNT_Pos (0U)
8581#define ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos)
8582#define ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
8583
8584/* Bit definition for Ethernet MTL Tx Queue Debug Register */
8585#define ETH_MTLTQDR_STXSTSF_Pos (20U)
8586#define ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos)
8587#define ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
8588#define ETH_MTLTQDR_PTXQ_Pos (16U)
8589#define ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos)
8590#define ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
8591#define ETH_MTLTQDR_TXSTSFSTS_Pos (5U)
8592#define ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos)
8593#define ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
8594#define ETH_MTLTQDR_TXQSTS_Pos (4U)
8595#define ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos)
8596#define ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
8597#define ETH_MTLTQDR_TWCSTS_Pos (3U)
8598#define ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos)
8599#define ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
8600#define ETH_MTLTQDR_TRCSTS_Pos (1U)
8601#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos)
8602#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
8603#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
8604#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
8605#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
8606#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
8607#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
8608#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos)
8609#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
8610
8611/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
8612#define ETH_MTLQICSR_RXOIE_Pos (24U)
8613#define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos)
8614#define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
8615#define ETH_MTLQICSR_RXOVFIS_Pos (16U)
8616#define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos)
8617#define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
8618#define ETH_MTLQICSR_TXUIE_Pos (8U)
8619#define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos)
8620#define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
8621#define ETH_MTLQICSR_TXUNFIS_Pos (0U)
8622#define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos)
8623#define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
8624
8625/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
8626#define ETH_MTLRQOMR_RQS_Pos (20U)
8627#define ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos)
8628#define ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
8629#define ETH_MTLRQOMR_RFD_Pos (14U)
8630#define ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos)
8631#define ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
8632#define ETH_MTLRQOMR_RFA_Pos (8U)
8633#define ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos)
8634#define ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
8635#define ETH_MTLRQOMR_EHFC_Pos (7U)
8636#define ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos)
8637#define ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
8638#define ETH_MTLRQOMR_DISTCPEF_Pos (6U)
8639#define ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos)
8640#define ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
8641#define ETH_MTLRQOMR_RSF_Pos (5U)
8642#define ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos)
8643#define ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */
8644#define ETH_MTLRQOMR_FEP_Pos (4U)
8645#define ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos)
8646#define ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */
8647#define ETH_MTLRQOMR_FUP_Pos (3U)
8648#define ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos)
8649#define ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */
8650#define ETH_MTLRQOMR_RTC_Pos (0U)
8651#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos)
8652#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
8653#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
8654#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
8655#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
8656#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
8657
8658/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
8659#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
8660#define ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos)
8661#define ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
8662#define ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U)
8663#define ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos)
8664#define ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
8665#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U)
8666#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos)
8667#define ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
8668#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U)
8669#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos)
8670#define ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
8671
8672/* Bit definition for Ethernet MTL Rx Queue Debug Register */
8673#define ETH_MTLRQDR_PRXQ_Pos (16U)
8674#define ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos)
8675#define ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */
8676#define ETH_MTLRQDR_RXQSTS_Pos (4U)
8677#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos)
8678#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
8679#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
8680#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
8681#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos)
8682#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
8683#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)
8684#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos)
8685#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
8686#define ETH_MTLRQDR_RXQSTS_FULL_Pos (4U)
8687#define ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos)
8688#define ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
8689#define ETH_MTLRQDR_RRCSTS_Pos (1U)
8690#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos)
8691#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
8692#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
8693#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
8694#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos)
8695#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
8696#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U)
8697#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos)
8698#define ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
8699#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U)
8700#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos)
8701#define ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
8702#define ETH_MTLRQDR_RWCSTS_Pos (0U)
8703#define ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos)
8704#define ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
8705
8706/* Bit definition for Ethernet MTL Rx Queue Control Register */
8707#define ETH_MTLRQCR_RQPA_Pos (3U)
8708#define ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos)
8709#define ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */
8710#define ETH_MTLRQCR_RQW_Pos (0U)
8711#define ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos)
8712#define ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */
8713
8714/* Bit definition for Ethernet DMA Mode Register */
8715#define ETH_DMAMR_INTM_Pos (16U)
8716#define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos)
8717#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
8718#define ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos)
8719#define ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos)
8720#define ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos)
8721#define ETH_DMAMR_PR_Pos (12U)
8722#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos)
8723#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
8724#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
8725#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
8726#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
8727#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
8728#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
8729#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
8730#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
8731#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
8732#define ETH_DMAMR_TXPR_Pos (11U)
8733#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos)
8734#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
8735#define ETH_DMAMR_DA_Pos (1U)
8736#define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos)
8737#define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */
8738#define ETH_DMAMR_SWR_Pos (0U)
8739#define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos)
8740#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */
8741
8742/* Bit definition for Ethernet DMA SysBus Mode Register */
8743#define ETH_DMASBMR_RB_Pos (15U)
8744#define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos)
8745#define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */
8746#define ETH_DMASBMR_MB_Pos (14U)
8747#define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos)
8748#define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */
8749#define ETH_DMASBMR_AAL_Pos (12U)
8750#define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos)
8751#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
8752#define ETH_DMASBMR_FB_Pos (0U)
8753#define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos)
8754#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
8755
8756/* Bit definition for Ethernet DMA Interrupt Status Register */
8757#define ETH_DMAISR_MACIS_Pos (17U)
8758#define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos)
8759#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
8760#define ETH_DMAISR_MTLIS_Pos (16U)
8761#define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos)
8762#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
8763#define ETH_DMAISR_DMACIS_Pos (0U)
8764#define ETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos)
8765#define ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */
8766
8767/* Bit definition for Ethernet DMA Debug Status Register */
8768#define ETH_DMADSR_TPS_Pos (12U)
8769#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos)
8770#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
8771#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
8772#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
8773#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos)
8774#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
8775#define ETH_DMADSR_TPS_WAITING_Pos (13U)
8776#define ETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos)
8777#define ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
8778#define ETH_DMADSR_TPS_READING_Pos (12U)
8779#define ETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos)
8780#define ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
8781#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U)
8782#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos)
8783#define ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8784#define ETH_DMADSR_TPS_SUSPENDED_Pos (13U)
8785#define ETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos)
8786#define ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
8787#define ETH_DMADSR_TPS_CLOSING_Pos (12U)
8788#define ETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos)
8789#define ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
8790#define ETH_DMADSR_RPS_Pos (8U)
8791#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos)
8792#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
8793#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
8794#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
8795#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos)
8796#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
8797#define ETH_DMADSR_RPS_WAITING_Pos (12U)
8798#define ETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos)
8799#define ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
8800#define ETH_DMADSR_RPS_SUSPENDED_Pos (14U)
8801#define ETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos)
8802#define ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
8803#define ETH_DMADSR_RPS_CLOSING_Pos (12U)
8804#define ETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos)
8805#define ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
8806#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U)
8807#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos)
8808#define ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8809#define ETH_DMADSR_RPS_TRANSFERRING_Pos (12U)
8810#define ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos)
8811#define ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
8812
8813/* Bit definition for Ethernet DMA Channel Control Register */
8814#define ETH_DMACCR_DSL_Pos (18U)
8815#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos)
8816#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
8817#define ETH_DMACCR_DSL_0BIT (0U)
8818#define ETH_DMACCR_DSL_32BIT (0x00040000U)
8819#define ETH_DMACCR_DSL_64BIT (0x00080000U)
8820#define ETH_DMACCR_DSL_128BIT (0x00100000U)
8821#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
8822#define ETH_DMACCR_MSS_Pos (0U)
8823#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos)
8824#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
8825
8826/* Bit definition for Ethernet DMA Channel Tx Control Register */
8827#define ETH_DMACTCR_TPBL_Pos (16U)
8828#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos)
8829#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
8830#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
8831#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
8832#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
8833#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
8834#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
8835#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
8836#define ETH_DMACTCR_TSE_Pos (12U)
8837#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos)
8838#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
8839#define ETH_DMACTCR_OSP_Pos (4U)
8840#define ETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos)
8841#define ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */
8842#define ETH_DMACTCR_ST_Pos (0U)
8843#define ETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos)
8844#define ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */
8845
8846/* Bit definition for Ethernet DMA Channel Rx Control Register */
8847#define ETH_DMACRCR_RPF_Pos (31U)
8848#define ETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos)
8849#define ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */
8850#define ETH_DMACRCR_RPBL_Pos (16U)
8851#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos)
8852#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
8853#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
8854#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
8855#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
8856#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
8857#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
8858#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
8859#define ETH_DMACRCR_RBSZ_Pos (1U)
8860#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos)
8861#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
8862#define ETH_DMACRCR_SR_Pos (0U)
8863#define ETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos)
8864#define ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */
8865
8866/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
8867#define ETH_DMACTDLAR_TDESLA_Pos (2U)
8868#define ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos)
8869#define ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
8870
8871/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
8872#define ETH_DMACRDLAR_RDESLA_Pos (2U)
8873#define ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos)
8874#define ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
8875
8876/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
8877#define ETH_DMACTDTPR_TDT_Pos (2U)
8878#define ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos)
8879#define ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
8880
8881/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
8882#define ETH_DMACRDTPR_RDT_Pos (2U)
8883#define ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos)
8884#define ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */
8885
8886/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
8887#define ETH_DMACTDRLR_TDRL_Pos (0U)
8888#define ETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos)
8889#define ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
8890
8891/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
8892#define ETH_DMACRDRLR_RDRL_Pos (0U)
8893#define ETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos)
8894#define ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */
8895
8896/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
8897#define ETH_DMACIER_NIE_Pos (15U)
8898#define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos)
8899#define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */
8900#define ETH_DMACIER_AIE_Pos (14U)
8901#define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos)
8902#define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
8903#define ETH_DMACIER_CDEE_Pos (13U)
8904#define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos)
8905#define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */
8906#define ETH_DMACIER_FBEE_Pos (12U)
8907#define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos)
8908#define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */
8909#define ETH_DMACIER_ERIE_Pos (11U)
8910#define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos)
8911#define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */
8912#define ETH_DMACIER_ETIE_Pos (10U)
8913#define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos)
8914#define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */
8915#define ETH_DMACIER_RWTE_Pos (9U)
8916#define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos)
8917#define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
8918#define ETH_DMACIER_RSE_Pos (8U)
8919#define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos)
8920#define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */
8921#define ETH_DMACIER_RBUE_Pos (7U)
8922#define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos)
8923#define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
8924#define ETH_DMACIER_RIE_Pos (6U)
8925#define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos)
8926#define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */
8927#define ETH_DMACIER_TBUE_Pos (2U)
8928#define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos)
8929#define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
8930#define ETH_DMACIER_TXSE_Pos (1U)
8931#define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos)
8932#define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */
8933#define ETH_DMACIER_TIE_Pos (0U)
8934#define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos)
8935#define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */
8936
8937/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
8938#define ETH_DMACRIWTR_RWT_Pos (0U)
8939#define ETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos)
8940#define ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
8941
8942/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
8943#define ETH_DMACCATDR_CURTDESAPTR_Pos (0U)
8944#define ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos)
8945#define ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
8946
8947/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
8948#define ETH_DMACCARDR_CURRDESAPTR_Pos (0U)
8949#define ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos)
8950#define ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
8951
8952/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
8953#define ETH_DMACCATBR_CURTBUFAPTR_Pos (0U)
8954#define ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos)
8955#define ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
8956
8957/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
8958#define ETH_DMACCARBR_CURRBUFAPTR_Pos (0U)
8959#define ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos)
8960#define ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
8961
8962/* Bit definition for Ethernet DMA Channel Status Register */
8963#define ETH_DMACSR_REB_Pos (19U)
8964#define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos)
8965#define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */
8966#define ETH_DMACSR_TEB_Pos (16U)
8967#define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos)
8968#define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */
8969#define ETH_DMACSR_NIS_Pos (15U)
8970#define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos)
8971#define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */
8972#define ETH_DMACSR_AIS_Pos (14U)
8973#define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos)
8974#define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */
8975#define ETH_DMACSR_CDE_Pos (13U)
8976#define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos)
8977#define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */
8978#define ETH_DMACSR_FBE_Pos (12U)
8979#define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos)
8980#define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */
8981#define ETH_DMACSR_ERI_Pos (11U)
8982#define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos)
8983#define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */
8984#define ETH_DMACSR_ETI_Pos (10U)
8985#define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos)
8986#define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */
8987#define ETH_DMACSR_RWT_Pos (9U)
8988#define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos)
8989#define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */
8990#define ETH_DMACSR_RPS_Pos (8U)
8991#define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos)
8992#define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */
8993#define ETH_DMACSR_RBU_Pos (7U)
8994#define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos)
8995#define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */
8996#define ETH_DMACSR_RI_Pos (6U)
8997#define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos)
8998#define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */
8999#define ETH_DMACSR_TBU_Pos (2U)
9000#define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos)
9001#define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */
9002#define ETH_DMACSR_TPS_Pos (1U)
9003#define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos)
9004#define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */
9005#define ETH_DMACSR_TI_Pos (0U)
9006#define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos)
9007#define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */
9008
9009/* Bit definition for Ethernet DMA Channel missed frame count register */
9010#define ETH_DMACMFCR_MFCO_Pos (15U)
9011#define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos)
9012#define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
9013#define ETH_DMACMFCR_MFC_Pos (0U)
9014#define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos)
9015#define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
9016
9017/******************************************************************************/
9018/* */
9019/* DMA Controller */
9020/* */
9021/******************************************************************************/
9022/******************** Bits definition for DMA_SxCR register *****************/
9023#define DMA_SxCR_MBURST_Pos (23U)
9024#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
9025#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
9026#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
9027#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
9028#define DMA_SxCR_PBURST_Pos (21U)
9029#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
9030#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
9031#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
9032#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
9033#define DMA_SxCR_TRBUFF_Pos (20U)
9034#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos)
9035#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk
9036#define DMA_SxCR_CT_Pos (19U)
9037#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
9038#define DMA_SxCR_CT DMA_SxCR_CT_Msk
9039#define DMA_SxCR_DBM_Pos (18U)
9040#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
9041#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
9042#define DMA_SxCR_PL_Pos (16U)
9043#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
9044#define DMA_SxCR_PL DMA_SxCR_PL_Msk
9045#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
9046#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
9047#define DMA_SxCR_PINCOS_Pos (15U)
9048#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
9049#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
9050#define DMA_SxCR_MSIZE_Pos (13U)
9051#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
9052#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
9053#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
9054#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
9055#define DMA_SxCR_PSIZE_Pos (11U)
9056#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
9057#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
9058#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
9059#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
9060#define DMA_SxCR_MINC_Pos (10U)
9061#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
9062#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
9063#define DMA_SxCR_PINC_Pos (9U)
9064#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
9065#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
9066#define DMA_SxCR_CIRC_Pos (8U)
9067#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
9068#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
9069#define DMA_SxCR_DIR_Pos (6U)
9070#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
9071#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
9072#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
9073#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
9074#define DMA_SxCR_PFCTRL_Pos (5U)
9075#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
9076#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
9077#define DMA_SxCR_TCIE_Pos (4U)
9078#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
9079#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
9080#define DMA_SxCR_HTIE_Pos (3U)
9081#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
9082#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
9083#define DMA_SxCR_TEIE_Pos (2U)
9084#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
9085#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
9086#define DMA_SxCR_DMEIE_Pos (1U)
9087#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
9088#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
9089#define DMA_SxCR_EN_Pos (0U)
9090#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
9091#define DMA_SxCR_EN DMA_SxCR_EN_Msk
9093/******************** Bits definition for DMA_SxCNDTR register **************/
9094#define DMA_SxNDT_Pos (0U)
9095#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
9096#define DMA_SxNDT DMA_SxNDT_Msk
9097#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
9098#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
9099#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
9100#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
9101#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
9102#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
9103#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
9104#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
9105#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
9106#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
9107#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
9108#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
9109#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
9110#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
9111#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
9112#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
9114/******************** Bits definition for DMA_SxFCR register ****************/
9115#define DMA_SxFCR_FEIE_Pos (7U)
9116#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
9117#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
9118#define DMA_SxFCR_FS_Pos (3U)
9119#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
9120#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
9121#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
9122#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
9123#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
9124#define DMA_SxFCR_DMDIS_Pos (2U)
9125#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
9126#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
9127#define DMA_SxFCR_FTH_Pos (0U)
9128#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
9129#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
9130#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
9131#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
9133/******************** Bits definition for DMA_LISR register *****************/
9134#define DMA_LISR_TCIF3_Pos (27U)
9135#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
9136#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
9137#define DMA_LISR_HTIF3_Pos (26U)
9138#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
9139#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
9140#define DMA_LISR_TEIF3_Pos (25U)
9141#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
9142#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
9143#define DMA_LISR_DMEIF3_Pos (24U)
9144#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
9145#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
9146#define DMA_LISR_FEIF3_Pos (22U)
9147#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
9148#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
9149#define DMA_LISR_TCIF2_Pos (21U)
9150#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
9151#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
9152#define DMA_LISR_HTIF2_Pos (20U)
9153#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
9154#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
9155#define DMA_LISR_TEIF2_Pos (19U)
9156#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
9157#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
9158#define DMA_LISR_DMEIF2_Pos (18U)
9159#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
9160#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
9161#define DMA_LISR_FEIF2_Pos (16U)
9162#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
9163#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
9164#define DMA_LISR_TCIF1_Pos (11U)
9165#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
9166#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
9167#define DMA_LISR_HTIF1_Pos (10U)
9168#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
9169#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
9170#define DMA_LISR_TEIF1_Pos (9U)
9171#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
9172#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
9173#define DMA_LISR_DMEIF1_Pos (8U)
9174#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
9175#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
9176#define DMA_LISR_FEIF1_Pos (6U)
9177#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
9178#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
9179#define DMA_LISR_TCIF0_Pos (5U)
9180#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
9181#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
9182#define DMA_LISR_HTIF0_Pos (4U)
9183#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
9184#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
9185#define DMA_LISR_TEIF0_Pos (3U)
9186#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
9187#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
9188#define DMA_LISR_DMEIF0_Pos (2U)
9189#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
9190#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
9191#define DMA_LISR_FEIF0_Pos (0U)
9192#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
9193#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
9195/******************** Bits definition for DMA_HISR register *****************/
9196#define DMA_HISR_TCIF7_Pos (27U)
9197#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
9198#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
9199#define DMA_HISR_HTIF7_Pos (26U)
9200#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
9201#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
9202#define DMA_HISR_TEIF7_Pos (25U)
9203#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
9204#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
9205#define DMA_HISR_DMEIF7_Pos (24U)
9206#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
9207#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
9208#define DMA_HISR_FEIF7_Pos (22U)
9209#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
9210#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
9211#define DMA_HISR_TCIF6_Pos (21U)
9212#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
9213#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
9214#define DMA_HISR_HTIF6_Pos (20U)
9215#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
9216#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
9217#define DMA_HISR_TEIF6_Pos (19U)
9218#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
9219#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
9220#define DMA_HISR_DMEIF6_Pos (18U)
9221#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
9222#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
9223#define DMA_HISR_FEIF6_Pos (16U)
9224#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
9225#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
9226#define DMA_HISR_TCIF5_Pos (11U)
9227#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
9228#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
9229#define DMA_HISR_HTIF5_Pos (10U)
9230#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
9231#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
9232#define DMA_HISR_TEIF5_Pos (9U)
9233#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
9234#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
9235#define DMA_HISR_DMEIF5_Pos (8U)
9236#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
9237#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
9238#define DMA_HISR_FEIF5_Pos (6U)
9239#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
9240#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
9241#define DMA_HISR_TCIF4_Pos (5U)
9242#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
9243#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
9244#define DMA_HISR_HTIF4_Pos (4U)
9245#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
9246#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
9247#define DMA_HISR_TEIF4_Pos (3U)
9248#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
9249#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
9250#define DMA_HISR_DMEIF4_Pos (2U)
9251#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
9252#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
9253#define DMA_HISR_FEIF4_Pos (0U)
9254#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
9255#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
9257/******************** Bits definition for DMA_LIFCR register ****************/
9258#define DMA_LIFCR_CTCIF3_Pos (27U)
9259#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
9260#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
9261#define DMA_LIFCR_CHTIF3_Pos (26U)
9262#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
9263#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
9264#define DMA_LIFCR_CTEIF3_Pos (25U)
9265#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
9266#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
9267#define DMA_LIFCR_CDMEIF3_Pos (24U)
9268#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
9269#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
9270#define DMA_LIFCR_CFEIF3_Pos (22U)
9271#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
9272#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
9273#define DMA_LIFCR_CTCIF2_Pos (21U)
9274#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
9275#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
9276#define DMA_LIFCR_CHTIF2_Pos (20U)
9277#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
9278#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
9279#define DMA_LIFCR_CTEIF2_Pos (19U)
9280#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
9281#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
9282#define DMA_LIFCR_CDMEIF2_Pos (18U)
9283#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
9284#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
9285#define DMA_LIFCR_CFEIF2_Pos (16U)
9286#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
9287#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
9288#define DMA_LIFCR_CTCIF1_Pos (11U)
9289#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
9290#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
9291#define DMA_LIFCR_CHTIF1_Pos (10U)
9292#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
9293#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
9294#define DMA_LIFCR_CTEIF1_Pos (9U)
9295#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
9296#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
9297#define DMA_LIFCR_CDMEIF1_Pos (8U)
9298#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
9299#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
9300#define DMA_LIFCR_CFEIF1_Pos (6U)
9301#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
9302#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
9303#define DMA_LIFCR_CTCIF0_Pos (5U)
9304#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
9305#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
9306#define DMA_LIFCR_CHTIF0_Pos (4U)
9307#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
9308#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
9309#define DMA_LIFCR_CTEIF0_Pos (3U)
9310#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
9311#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
9312#define DMA_LIFCR_CDMEIF0_Pos (2U)
9313#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
9314#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
9315#define DMA_LIFCR_CFEIF0_Pos (0U)
9316#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
9317#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
9319/******************** Bits definition for DMA_HIFCR register ****************/
9320#define DMA_HIFCR_CTCIF7_Pos (27U)
9321#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
9322#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
9323#define DMA_HIFCR_CHTIF7_Pos (26U)
9324#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
9325#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
9326#define DMA_HIFCR_CTEIF7_Pos (25U)
9327#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
9328#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
9329#define DMA_HIFCR_CDMEIF7_Pos (24U)
9330#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
9331#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
9332#define DMA_HIFCR_CFEIF7_Pos (22U)
9333#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
9334#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
9335#define DMA_HIFCR_CTCIF6_Pos (21U)
9336#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
9337#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
9338#define DMA_HIFCR_CHTIF6_Pos (20U)
9339#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
9340#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
9341#define DMA_HIFCR_CTEIF6_Pos (19U)
9342#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
9343#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
9344#define DMA_HIFCR_CDMEIF6_Pos (18U)
9345#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
9346#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
9347#define DMA_HIFCR_CFEIF6_Pos (16U)
9348#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
9349#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
9350#define DMA_HIFCR_CTCIF5_Pos (11U)
9351#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
9352#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
9353#define DMA_HIFCR_CHTIF5_Pos (10U)
9354#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
9355#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
9356#define DMA_HIFCR_CTEIF5_Pos (9U)
9357#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
9358#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
9359#define DMA_HIFCR_CDMEIF5_Pos (8U)
9360#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
9361#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
9362#define DMA_HIFCR_CFEIF5_Pos (6U)
9363#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
9364#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
9365#define DMA_HIFCR_CTCIF4_Pos (5U)
9366#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
9367#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
9368#define DMA_HIFCR_CHTIF4_Pos (4U)
9369#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
9370#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
9371#define DMA_HIFCR_CTEIF4_Pos (3U)
9372#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
9373#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
9374#define DMA_HIFCR_CDMEIF4_Pos (2U)
9375#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
9376#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
9377#define DMA_HIFCR_CFEIF4_Pos (0U)
9378#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
9379#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
9381/****************** Bit definition for DMA_SxPAR register ********************/
9382#define DMA_SxPAR_PA_Pos (0U)
9383#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
9384#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
9386/****************** Bit definition for DMA_SxM0AR register ********************/
9387#define DMA_SxM0AR_M0A_Pos (0U)
9388#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
9389#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
9391/****************** Bit definition for DMA_SxM1AR register ********************/
9392#define DMA_SxM1AR_M1A_Pos (0U)
9393#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
9394#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
9396/******************************************************************************/
9397/* */
9398/* DMAMUX Controller */
9399/* */
9400/******************************************************************************/
9401/******************** Bits definition for DMAMUX_CxCR register **************/
9402#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
9403#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9404#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
9405#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9406#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9407#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9408#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9409#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9410#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9411#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9412#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9413#define DMAMUX_CxCR_SOIE_Pos (8U)
9414#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)
9415#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
9416#define DMAMUX_CxCR_EGE_Pos (9U)
9417#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)
9418#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
9419#define DMAMUX_CxCR_SE_Pos (16U)
9420#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)
9421#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
9422#define DMAMUX_CxCR_SPOL_Pos (17U)
9423#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)
9424#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
9425#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)
9426#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)
9427#define DMAMUX_CxCR_NBREQ_Pos (19U)
9428#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)
9429#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
9430#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)
9431#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)
9432#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)
9433#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)
9434#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)
9435#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
9436#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)
9437#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
9438#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)
9439#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)
9440#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)
9441#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)
9442#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)
9444/******************** Bits definition for DMAMUX_CSR register **************/
9445#define DMAMUX_CSR_SOF0_Pos (0U)
9446#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)
9447#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
9448#define DMAMUX_CSR_SOF1_Pos (1U)
9449#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)
9450#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
9451#define DMAMUX_CSR_SOF2_Pos (2U)
9452#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)
9453#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
9454#define DMAMUX_CSR_SOF3_Pos (3U)
9455#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)
9456#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
9457#define DMAMUX_CSR_SOF4_Pos (4U)
9458#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)
9459#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
9460#define DMAMUX_CSR_SOF5_Pos (5U)
9461#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)
9462#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
9463#define DMAMUX_CSR_SOF6_Pos (6U)
9464#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)
9465#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
9466#define DMAMUX_CSR_SOF7_Pos (7U)
9467#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)
9468#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
9469#define DMAMUX_CSR_SOF8_Pos (8U)
9470#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)
9471#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
9472#define DMAMUX_CSR_SOF9_Pos (9U)
9473#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)
9474#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
9475#define DMAMUX_CSR_SOF10_Pos (10U)
9476#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)
9477#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
9478#define DMAMUX_CSR_SOF11_Pos (11U)
9479#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)
9480#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
9481#define DMAMUX_CSR_SOF12_Pos (12U)
9482#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)
9483#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
9484#define DMAMUX_CSR_SOF13_Pos (13U)
9485#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)
9486#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
9487#define DMAMUX_CSR_SOF14_Pos (14U)
9488#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)
9489#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
9490#define DMAMUX_CSR_SOF15_Pos (15U)
9491#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)
9492#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
9494/******************** Bits definition for DMAMUX_CFR register **************/
9495#define DMAMUX_CFR_CSOF0_Pos (0U)
9496#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)
9497#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
9498#define DMAMUX_CFR_CSOF1_Pos (1U)
9499#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)
9500#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
9501#define DMAMUX_CFR_CSOF2_Pos (2U)
9502#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)
9503#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
9504#define DMAMUX_CFR_CSOF3_Pos (3U)
9505#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)
9506#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
9507#define DMAMUX_CFR_CSOF4_Pos (4U)
9508#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)
9509#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
9510#define DMAMUX_CFR_CSOF5_Pos (5U)
9511#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)
9512#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
9513#define DMAMUX_CFR_CSOF6_Pos (6U)
9514#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)
9515#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
9516#define DMAMUX_CFR_CSOF7_Pos (7U)
9517#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)
9518#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
9519#define DMAMUX_CFR_CSOF8_Pos (8U)
9520#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)
9521#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
9522#define DMAMUX_CFR_CSOF9_Pos (9U)
9523#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)
9524#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
9525#define DMAMUX_CFR_CSOF10_Pos (10U)
9526#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)
9527#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
9528#define DMAMUX_CFR_CSOF11_Pos (11U)
9529#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)
9530#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
9531#define DMAMUX_CFR_CSOF12_Pos (12U)
9532#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)
9533#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
9534#define DMAMUX_CFR_CSOF13_Pos (13U)
9535#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)
9536#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
9537#define DMAMUX_CFR_CSOF14_Pos (14U)
9538#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)
9539#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
9540#define DMAMUX_CFR_CSOF15_Pos (15U)
9541#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)
9542#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
9544/******************** Bits definition for DMAMUX_RGxCR register ************/
9545#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
9546#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)
9547#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
9548#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)
9549#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)
9550#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)
9551#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)
9552#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)
9553#define DMAMUX_RGxCR_OIE_Pos (8U)
9554#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)
9555#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
9556#define DMAMUX_RGxCR_GE_Pos (16U)
9557#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)
9558#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
9559#define DMAMUX_RGxCR_GPOL_Pos (17U)
9560#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)
9561#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
9562#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)
9563#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)
9564#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
9565#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)
9566#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
9567#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)
9568#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)
9569#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)
9570#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)
9571#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)
9573/******************** Bits definition for DMAMUX_RGSR register **************/
9574#define DMAMUX_RGSR_OF0_Pos (0U)
9575#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)
9576#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
9577#define DMAMUX_RGSR_OF1_Pos (1U)
9578#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)
9579#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
9580#define DMAMUX_RGSR_OF2_Pos (2U)
9581#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)
9582#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
9583#define DMAMUX_RGSR_OF3_Pos (3U)
9584#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)
9585#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
9586#define DMAMUX_RGSR_OF4_Pos (4U)
9587#define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos)
9588#define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk
9589#define DMAMUX_RGSR_OF5_Pos (5U)
9590#define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos)
9591#define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk
9592#define DMAMUX_RGSR_OF6_Pos (6U)
9593#define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos)
9594#define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk
9595#define DMAMUX_RGSR_OF7_Pos (7U)
9596#define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos)
9597#define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk
9599/******************** Bits definition for DMAMUX_RGCFR register **************/
9600#define DMAMUX_RGCFR_COF0_Pos (0U)
9601#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)
9602#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
9603#define DMAMUX_RGCFR_COF1_Pos (1U)
9604#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)
9605#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
9606#define DMAMUX_RGCFR_COF2_Pos (2U)
9607#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)
9608#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
9609#define DMAMUX_RGCFR_COF3_Pos (3U)
9610#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)
9611#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
9612#define DMAMUX_RGCFR_COF4_Pos (4U)
9613#define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos)
9614#define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk
9615#define DMAMUX_RGCFR_COF5_Pos (5U)
9616#define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos)
9617#define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk
9618#define DMAMUX_RGCFR_COF6_Pos (6U)
9619#define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos)
9620#define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk
9621#define DMAMUX_RGCFR_COF7_Pos (7U)
9622#define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos)
9623#define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk
9625/******************************************************************************/
9626/* */
9627/* AHB Master DMA2D Controller (DMA2D) */
9628/* */
9629/******************************************************************************/
9630
9631/******************** Bit definition for DMA2D_CR register ******************/
9632
9633#define DMA2D_CR_START_Pos (0U)
9634#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
9635#define DMA2D_CR_START DMA2D_CR_START_Msk
9636#define DMA2D_CR_SUSP_Pos (1U)
9637#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
9638#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
9639#define DMA2D_CR_ABORT_Pos (2U)
9640#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
9641#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
9642#define DMA2D_CR_LOM_Pos (6U)
9643#define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos)
9644#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk
9645#define DMA2D_CR_TEIE_Pos (8U)
9646#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
9647#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
9648#define DMA2D_CR_TCIE_Pos (9U)
9649#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
9650#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
9651#define DMA2D_CR_TWIE_Pos (10U)
9652#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
9653#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
9654#define DMA2D_CR_CAEIE_Pos (11U)
9655#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
9656#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
9657#define DMA2D_CR_CTCIE_Pos (12U)
9658#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
9659#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
9660#define DMA2D_CR_CEIE_Pos (13U)
9661#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
9662#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
9663#define DMA2D_CR_MODE_Pos (16U)
9664#define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos)
9665#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
9666#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
9667#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
9668#define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos)
9670/******************** Bit definition for DMA2D_ISR register *****************/
9671
9672#define DMA2D_ISR_TEIF_Pos (0U)
9673#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
9674#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
9675#define DMA2D_ISR_TCIF_Pos (1U)
9676#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
9677#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
9678#define DMA2D_ISR_TWIF_Pos (2U)
9679#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
9680#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
9681#define DMA2D_ISR_CAEIF_Pos (3U)
9682#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
9683#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
9684#define DMA2D_ISR_CTCIF_Pos (4U)
9685#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
9686#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
9687#define DMA2D_ISR_CEIF_Pos (5U)
9688#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
9689#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
9691/******************** Bit definition for DMA2D_IFCR register ****************/
9692
9693#define DMA2D_IFCR_CTEIF_Pos (0U)
9694#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
9695#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
9696#define DMA2D_IFCR_CTCIF_Pos (1U)
9697#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
9698#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
9699#define DMA2D_IFCR_CTWIF_Pos (2U)
9700#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
9701#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
9702#define DMA2D_IFCR_CAECIF_Pos (3U)
9703#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
9704#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
9705#define DMA2D_IFCR_CCTCIF_Pos (4U)
9706#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
9707#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
9708#define DMA2D_IFCR_CCEIF_Pos (5U)
9709#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
9710#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
9712/******************** Bit definition for DMA2D_FGMAR register ***************/
9713
9714#define DMA2D_FGMAR_MA_Pos (0U)
9715#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
9716#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
9718/******************** Bit definition for DMA2D_FGOR register ****************/
9719
9720#define DMA2D_FGOR_LO_Pos (0U)
9721#define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos)
9722#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
9724/******************** Bit definition for DMA2D_BGMAR register ***************/
9725
9726#define DMA2D_BGMAR_MA_Pos (0U)
9727#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
9728#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
9730/******************** Bit definition for DMA2D_BGOR register ****************/
9731
9732#define DMA2D_BGOR_LO_Pos (0U)
9733#define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos)
9734#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
9736/******************** Bit definition for DMA2D_FGPFCCR register *************/
9737
9738#define DMA2D_FGPFCCR_CM_Pos (0U)
9739#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
9740#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
9741#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
9742#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
9743#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
9744#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
9745#define DMA2D_FGPFCCR_CCM_Pos (4U)
9746#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
9747#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
9748#define DMA2D_FGPFCCR_START_Pos (5U)
9749#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
9750#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
9751#define DMA2D_FGPFCCR_CS_Pos (8U)
9752#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
9753#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
9754#define DMA2D_FGPFCCR_AM_Pos (16U)
9755#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
9756#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
9757#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
9758#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
9759#define DMA2D_FGPFCCR_CSS_Pos (18U)
9760#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos)
9761#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
9762#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos)
9763#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos)
9764#define DMA2D_FGPFCCR_AI_Pos (20U)
9765#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos)
9766#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk
9767#define DMA2D_FGPFCCR_RBS_Pos (21U)
9768#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos)
9769#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk
9770#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
9771#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
9772#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
9774/******************** Bit definition for DMA2D_FGCOLR register **************/
9775
9776#define DMA2D_FGCOLR_BLUE_Pos (0U)
9777#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
9778#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
9779#define DMA2D_FGCOLR_GREEN_Pos (8U)
9780#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
9781#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
9782#define DMA2D_FGCOLR_RED_Pos (16U)
9783#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
9784#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
9786/******************** Bit definition for DMA2D_BGPFCCR register *************/
9787
9788#define DMA2D_BGPFCCR_CM_Pos (0U)
9789#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
9790#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
9791#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
9792#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
9793#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
9794#define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos)
9795#define DMA2D_BGPFCCR_CCM_Pos (4U)
9796#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
9797#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
9798#define DMA2D_BGPFCCR_START_Pos (5U)
9799#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
9800#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
9801#define DMA2D_BGPFCCR_CS_Pos (8U)
9802#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
9803#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
9804#define DMA2D_BGPFCCR_AM_Pos (16U)
9805#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
9806#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
9807#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
9808#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
9809#define DMA2D_BGPFCCR_AI_Pos (20U)
9810#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos)
9811#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk
9812#define DMA2D_BGPFCCR_RBS_Pos (21U)
9813#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos)
9814#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk
9815#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
9816#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
9817#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
9819/******************** Bit definition for DMA2D_BGCOLR register **************/
9820
9821#define DMA2D_BGCOLR_BLUE_Pos (0U)
9822#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
9823#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
9824#define DMA2D_BGCOLR_GREEN_Pos (8U)
9825#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
9826#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
9827#define DMA2D_BGCOLR_RED_Pos (16U)
9828#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
9829#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
9831/******************** Bit definition for DMA2D_FGCMAR register **************/
9832
9833#define DMA2D_FGCMAR_MA_Pos (0U)
9834#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
9835#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
9837/******************** Bit definition for DMA2D_BGCMAR register **************/
9838
9839#define DMA2D_BGCMAR_MA_Pos (0U)
9840#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
9841#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
9843/******************** Bit definition for DMA2D_OPFCCR register **************/
9844
9845#define DMA2D_OPFCCR_CM_Pos (0U)
9846#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
9847#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
9848#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
9849#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
9850#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
9851#define DMA2D_OPFCCR_SB_Pos (8U)
9852#define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos)
9853#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk
9854#define DMA2D_OPFCCR_AI_Pos (20U)
9855#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos)
9856#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk
9857#define DMA2D_OPFCCR_RBS_Pos (21U)
9858#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos)
9859#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk
9861/******************** Bit definition for DMA2D_OCOLR register ***************/
9862
9865#define DMA2D_OCOLR_BLUE_1_Pos (0U)
9866#define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
9867#define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk
9868#define DMA2D_OCOLR_GREEN_1_Pos (8U)
9869#define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
9870#define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk
9871#define DMA2D_OCOLR_RED_1_Pos (16U)
9872#define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
9873#define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk
9874#define DMA2D_OCOLR_ALPHA_1_Pos (24U)
9875#define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
9876#define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk
9879#define DMA2D_OCOLR_BLUE_2_Pos (0U)
9880#define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
9881#define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk
9882#define DMA2D_OCOLR_GREEN_2_Pos (5U)
9883#define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
9884#define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk
9885#define DMA2D_OCOLR_RED_2_Pos (11U)
9886#define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
9887#define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk
9890#define DMA2D_OCOLR_BLUE_3_Pos (0U)
9891#define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
9892#define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk
9893#define DMA2D_OCOLR_GREEN_3_Pos (5U)
9894#define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
9895#define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk
9896#define DMA2D_OCOLR_RED_3_Pos (10U)
9897#define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
9898#define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk
9899#define DMA2D_OCOLR_ALPHA_3_Pos (15U)
9900#define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
9901#define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk
9904#define DMA2D_OCOLR_BLUE_4_Pos (0U)
9905#define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
9906#define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk
9907#define DMA2D_OCOLR_GREEN_4_Pos (4U)
9908#define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
9909#define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk
9910#define DMA2D_OCOLR_RED_4_Pos (8U)
9911#define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
9912#define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk
9913#define DMA2D_OCOLR_ALPHA_4_Pos (12U)
9914#define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
9915#define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk
9917/******************** Bit definition for DMA2D_OMAR register ****************/
9918
9919#define DMA2D_OMAR_MA_Pos (0U)
9920#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
9921#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
9923/******************** Bit definition for DMA2D_OOR register *****************/
9924
9925#define DMA2D_OOR_LO_Pos (0U)
9926#define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos)
9927#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
9929/******************** Bit definition for DMA2D_NLR register *****************/
9930
9931#define DMA2D_NLR_NL_Pos (0U)
9932#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
9933#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
9934#define DMA2D_NLR_PL_Pos (16U)
9935#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
9936#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
9938/******************** Bit definition for DMA2D_LWR register *****************/
9939
9940#define DMA2D_LWR_LW_Pos (0U)
9941#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
9942#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
9944/******************** Bit definition for DMA2D_AMTCR register ***************/
9945
9946#define DMA2D_AMTCR_EN_Pos (0U)
9947#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
9948#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
9949#define DMA2D_AMTCR_DT_Pos (8U)
9950#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
9951#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
9954/******************** Bit definition for DMA2D_FGCLUT register **************/
9955
9956/******************** Bit definition for DMA2D_BGCLUT register **************/
9957
9958
9959/******************************************************************************/
9960/* */
9961/* External Interrupt/Event Controller */
9962/* */
9963/******************************************************************************/
9964/****************** Bit definition for EXTI_RTSR1 register *******************/
9965#define EXTI_RTSR1_TR_Pos (0U)
9966#define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)
9967#define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk
9968#define EXTI_RTSR1_TR0_Pos (0U)
9969#define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos)
9970#define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk
9971#define EXTI_RTSR1_TR1_Pos (1U)
9972#define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos)
9973#define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk
9974#define EXTI_RTSR1_TR2_Pos (2U)
9975#define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos)
9976#define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk
9977#define EXTI_RTSR1_TR3_Pos (3U)
9978#define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos)
9979#define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk
9980#define EXTI_RTSR1_TR4_Pos (4U)
9981#define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos)
9982#define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk
9983#define EXTI_RTSR1_TR5_Pos (5U)
9984#define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos)
9985#define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk
9986#define EXTI_RTSR1_TR6_Pos (6U)
9987#define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos)
9988#define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk
9989#define EXTI_RTSR1_TR7_Pos (7U)
9990#define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos)
9991#define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk
9992#define EXTI_RTSR1_TR8_Pos (8U)
9993#define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos)
9994#define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk
9995#define EXTI_RTSR1_TR9_Pos (9U)
9996#define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos)
9997#define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk
9998#define EXTI_RTSR1_TR10_Pos (10U)
9999#define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos)
10000#define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk
10001#define EXTI_RTSR1_TR11_Pos (11U)
10002#define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos)
10003#define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk
10004#define EXTI_RTSR1_TR12_Pos (12U)
10005#define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos)
10006#define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk
10007#define EXTI_RTSR1_TR13_Pos (13U)
10008#define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos)
10009#define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk
10010#define EXTI_RTSR1_TR14_Pos (14U)
10011#define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos)
10012#define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk
10013#define EXTI_RTSR1_TR15_Pos (15U)
10014#define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos)
10015#define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk
10016#define EXTI_RTSR1_TR16_Pos (16U)
10017#define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos)
10018#define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk
10019#define EXTI_RTSR1_TR17_Pos (17U)
10020#define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos)
10021#define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk
10022#define EXTI_RTSR1_TR18_Pos (18U)
10023#define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos)
10024#define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk
10025#define EXTI_RTSR1_TR19_Pos (19U)
10026#define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos)
10027#define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk
10028#define EXTI_RTSR1_TR20_Pos (20U)
10029#define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos)
10030#define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk
10031#define EXTI_RTSR1_TR21_Pos (21U)
10032#define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos)
10033#define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk
10035/****************** Bit definition for EXTI_FTSR1 register *******************/
10036#define EXTI_FTSR1_TR_Pos (0U)
10037#define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)
10038#define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk
10039#define EXTI_FTSR1_TR0_Pos (0U)
10040#define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos)
10041#define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk
10042#define EXTI_FTSR1_TR1_Pos (1U)
10043#define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos)
10044#define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk
10045#define EXTI_FTSR1_TR2_Pos (2U)
10046#define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos)
10047#define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk
10048#define EXTI_FTSR1_TR3_Pos (3U)
10049#define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos)
10050#define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk
10051#define EXTI_FTSR1_TR4_Pos (4U)
10052#define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos)
10053#define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk
10054#define EXTI_FTSR1_TR5_Pos (5U)
10055#define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos)
10056#define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk
10057#define EXTI_FTSR1_TR6_Pos (6U)
10058#define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos)
10059#define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk
10060#define EXTI_FTSR1_TR7_Pos (7U)
10061#define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos)
10062#define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk
10063#define EXTI_FTSR1_TR8_Pos (8U)
10064#define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos)
10065#define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk
10066#define EXTI_FTSR1_TR9_Pos (9U)
10067#define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos)
10068#define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk
10069#define EXTI_FTSR1_TR10_Pos (10U)
10070#define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos)
10071#define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk
10072#define EXTI_FTSR1_TR11_Pos (11U)
10073#define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos)
10074#define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk
10075#define EXTI_FTSR1_TR12_Pos (12U)
10076#define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos)
10077#define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk
10078#define EXTI_FTSR1_TR13_Pos (13U)
10079#define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos)
10080#define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk
10081#define EXTI_FTSR1_TR14_Pos (14U)
10082#define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos)
10083#define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk
10084#define EXTI_FTSR1_TR15_Pos (15U)
10085#define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos)
10086#define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk
10087#define EXTI_FTSR1_TR16_Pos (16U)
10088#define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos)
10089#define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk
10090#define EXTI_FTSR1_TR17_Pos (17U)
10091#define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos)
10092#define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk
10093#define EXTI_FTSR1_TR18_Pos (18U)
10094#define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos)
10095#define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk
10096#define EXTI_FTSR1_TR19_Pos (19U)
10097#define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos)
10098#define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk
10099#define EXTI_FTSR1_TR20_Pos (20U)
10100#define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos)
10101#define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk
10102#define EXTI_FTSR1_TR21_Pos (21U)
10103#define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos)
10104#define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk
10106/****************** Bit definition for EXTI_SWIER1 register ******************/
10107#define EXTI_SWIER1_SWIER0_Pos (0U)
10108#define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos)
10109#define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk
10110#define EXTI_SWIER1_SWIER1_Pos (1U)
10111#define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos)
10112#define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk
10113#define EXTI_SWIER1_SWIER2_Pos (2U)
10114#define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos)
10115#define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk
10116#define EXTI_SWIER1_SWIER3_Pos (3U)
10117#define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos)
10118#define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk
10119#define EXTI_SWIER1_SWIER4_Pos (4U)
10120#define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos)
10121#define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk
10122#define EXTI_SWIER1_SWIER5_Pos (5U)
10123#define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos)
10124#define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk
10125#define EXTI_SWIER1_SWIER6_Pos (6U)
10126#define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos)
10127#define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk
10128#define EXTI_SWIER1_SWIER7_Pos (7U)
10129#define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos)
10130#define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk
10131#define EXTI_SWIER1_SWIER8_Pos (8U)
10132#define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos)
10133#define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk
10134#define EXTI_SWIER1_SWIER9_Pos (9U)
10135#define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos)
10136#define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk
10137#define EXTI_SWIER1_SWIER10_Pos (10U)
10138#define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos)
10139#define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk
10140#define EXTI_SWIER1_SWIER11_Pos (11U)
10141#define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos)
10142#define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk
10143#define EXTI_SWIER1_SWIER12_Pos (12U)
10144#define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos)
10145#define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk
10146#define EXTI_SWIER1_SWIER13_Pos (13U)
10147#define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos)
10148#define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk
10149#define EXTI_SWIER1_SWIER14_Pos (14U)
10150#define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos)
10151#define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk
10152#define EXTI_SWIER1_SWIER15_Pos (15U)
10153#define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos)
10154#define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk
10155#define EXTI_SWIER1_SWIER16_Pos (16U)
10156#define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos)
10157#define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk
10158#define EXTI_SWIER1_SWIER17_Pos (17U)
10159#define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos)
10160#define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk
10161#define EXTI_SWIER1_SWIER18_Pos (18U)
10162#define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos)
10163#define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk
10164#define EXTI_SWIER1_SWIER19_Pos (19U)
10165#define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos)
10166#define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk
10167#define EXTI_SWIER1_SWIER20_Pos (20U)
10168#define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos)
10169#define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk
10170#define EXTI_SWIER1_SWIER21_Pos (21U)
10171#define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos)
10172#define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk
10174/****************** Bit definition for EXTI_D3PMR1 register ******************/
10175#define EXTI_D3PMR1_MR0_Pos (0U)
10176#define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos)
10177#define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk
10178#define EXTI_D3PMR1_MR1_Pos (1U)
10179#define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos)
10180#define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk
10181#define EXTI_D3PMR1_MR2_Pos (2U)
10182#define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos)
10183#define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk
10184#define EXTI_D3PMR1_MR3_Pos (3U)
10185#define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos)
10186#define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk
10187#define EXTI_D3PMR1_MR4_Pos (4U)
10188#define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos)
10189#define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk
10190#define EXTI_D3PMR1_MR5_Pos (5U)
10191#define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos)
10192#define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk
10193#define EXTI_D3PMR1_MR6_Pos (6U)
10194#define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos)
10195#define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk
10196#define EXTI_D3PMR1_MR7_Pos (7U)
10197#define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos)
10198#define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk
10199#define EXTI_D3PMR1_MR8_Pos (8U)
10200#define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos)
10201#define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk
10202#define EXTI_D3PMR1_MR9_Pos (9U)
10203#define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos)
10204#define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk
10205#define EXTI_D3PMR1_MR10_Pos (10U)
10206#define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos)
10207#define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk
10208#define EXTI_D3PMR1_MR11_Pos (11U)
10209#define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos)
10210#define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk
10211#define EXTI_D3PMR1_MR12_Pos (12U)
10212#define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos)
10213#define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk
10214#define EXTI_D3PMR1_MR13_Pos (13U)
10215#define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos)
10216#define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk
10217#define EXTI_D3PMR1_MR14_Pos (14U)
10218#define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos)
10219#define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk
10220#define EXTI_D3PMR1_MR15_Pos (15U)
10221#define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos)
10222#define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk
10223#define EXTI_D3PMR1_MR19_Pos (19U)
10224#define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos)
10225#define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk
10226#define EXTI_D3PMR1_MR20_Pos (20U)
10227#define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos)
10228#define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk
10229#define EXTI_D3PMR1_MR21_Pos (21U)
10230#define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos)
10231#define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk
10232#define EXTI_D3PMR1_MR25_Pos (24U)
10233#define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos)
10234#define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk
10236/******************* Bit definition for EXTI_D3PCR1L register ****************/
10237#define EXTI_D3PCR1L_PCS0_Pos (0U)
10238#define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos)
10239#define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk
10240#define EXTI_D3PCR1L_PCS1_Pos (2U)
10241#define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos)
10242#define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk
10243#define EXTI_D3PCR1L_PCS2_Pos (4U)
10244#define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos)
10245#define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk
10246#define EXTI_D3PCR1L_PCS3_Pos (6U)
10247#define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos)
10248#define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk
10249#define EXTI_D3PCR1L_PCS4_Pos (8U)
10250#define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos)
10251#define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk
10252#define EXTI_D3PCR1L_PCS5_Pos (10U)
10253#define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos)
10254#define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk
10255#define EXTI_D3PCR1L_PCS6_Pos (12U)
10256#define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos)
10257#define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk
10258#define EXTI_D3PCR1L_PCS7_Pos (14U)
10259#define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos)
10260#define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk
10261#define EXTI_D3PCR1L_PCS8_Pos (16U)
10262#define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos)
10263#define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk
10264#define EXTI_D3PCR1L_PCS9_Pos (18U)
10265#define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos)
10266#define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk
10267#define EXTI_D3PCR1L_PCS10_Pos (20U)
10268#define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos)
10269#define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk
10270#define EXTI_D3PCR1L_PCS11_Pos (22U)
10271#define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos)
10272#define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk
10273#define EXTI_D3PCR1L_PCS12_Pos (24U)
10274#define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos)
10275#define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk
10276#define EXTI_D3PCR1L_PCS13_Pos (26U)
10277#define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos)
10278#define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk
10279#define EXTI_D3PCR1L_PCS14_Pos (28U)
10280#define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos)
10281#define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk
10282#define EXTI_D3PCR1L_PCS15_Pos (30U)
10283#define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos)
10284#define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk
10286/******************* Bit definition for EXTI_D3PCR1H register ****************/
10287#define EXTI_D3PCR1H_PCS19_Pos (6U)
10288#define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos)
10289#define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk
10290#define EXTI_D3PCR1H_PCS20_Pos (8U)
10291#define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos)
10292#define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk
10293#define EXTI_D3PCR1H_PCS21_Pos (10U)
10294#define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos)
10295#define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk
10296#define EXTI_D3PCR1H_PCS25_Pos (18U)
10297#define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos)
10298#define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk
10300/****************** Bit definition for EXTI_RTSR2 register *******************/
10301#define EXTI_RTSR2_TR_Pos (17U)
10302#define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos)
10303#define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk
10304#define EXTI_RTSR2_TR49_Pos (17U)
10305#define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos)
10306#define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk
10307#define EXTI_RTSR2_TR51_Pos (19U)
10308#define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos)
10309#define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk
10311/****************** Bit definition for EXTI_FTSR2 register *******************/
10312#define EXTI_FTSR2_TR_Pos (17U)
10313#define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos)
10314#define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk
10315#define EXTI_FTSR2_TR49_Pos (17U)
10316#define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos)
10317#define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk
10318#define EXTI_FTSR2_TR51_Pos (19U)
10319#define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos)
10320#define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk
10322/****************** Bit definition for EXTI_SWIER2 register ******************/
10323#define EXTI_SWIER2_SWIER49_Pos (17U)
10324#define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos)
10325#define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk
10326#define EXTI_SWIER2_SWIER51_Pos (19U)
10327#define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos)
10328#define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk
10330/****************** Bit definition for EXTI_D3PMR2 register ******************/
10331#define EXTI_D3PMR2_MR34_Pos (2U)
10332#define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos)
10333#define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk
10334#define EXTI_D3PMR2_MR35_Pos (3U)
10335#define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos)
10336#define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk
10337#define EXTI_D3PMR2_MR41_Pos (9U)
10338#define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos)
10339#define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk
10340#define EXTI_D3PMR2_MR48_Pos (16U)
10341#define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos)
10342#define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk
10343#define EXTI_D3PMR2_MR49_Pos (17U)
10344#define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos)
10345#define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk
10346#define EXTI_D3PMR2_MR50_Pos (18U)
10347#define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos)
10348#define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk
10349#define EXTI_D3PMR2_MR51_Pos (19U)
10350#define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos)
10351#define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk
10352#define EXTI_D3PMR2_MR52_Pos (20U)
10353#define EXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos)
10354#define EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk
10355#define EXTI_D3PMR2_MR53_Pos (21U)
10356#define EXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos)
10357#define EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk
10358/******************* Bit definition for EXTI_D3PCR2L register ****************/
10359#define EXTI_D3PCR2L_PCS34_Pos (4U)
10360#define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos)
10361#define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk
10362#define EXTI_D3PCR2L_PCS35_Pos (6U)
10363#define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos)
10364#define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk
10365#define EXTI_D3PCR2L_PCS41_Pos (18U)
10366#define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos)
10367#define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk
10370/******************* Bit definition for EXTI_D3PCR2H register ****************/
10371#define EXTI_D3PCR2H_PCS48_Pos (0U)
10372#define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos)
10373#define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk
10374#define EXTI_D3PCR2H_PCS49_Pos (2U)
10375#define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos)
10376#define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk
10377#define EXTI_D3PCR2H_PCS50_Pos (4U)
10378#define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos)
10379#define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk
10380#define EXTI_D3PCR2H_PCS51_Pos (6U)
10381#define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos)
10382#define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk
10383#define EXTI_D3PCR2H_PCS52_Pos (8U)
10384#define EXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos)
10385#define EXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk
10386#define EXTI_D3PCR2H_PCS53_Pos (10U)
10387#define EXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos)
10388#define EXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk
10389/****************** Bit definition for EXTI_RTSR3 register *******************/
10390#define EXTI_RTSR3_TR_Pos (21U)
10391#define EXTI_RTSR3_TR_Msk (0x3UL << EXTI_RTSR3_TR_Pos)
10392#define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk
10393#define EXTI_RTSR3_TR85_Pos (21U)
10394#define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos)
10395#define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk
10396#define EXTI_RTSR3_TR86_Pos (22U)
10397#define EXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos)
10398#define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk
10400/****************** Bit definition for EXTI_FTSR3 register *******************/
10401#define EXTI_FTSR3_TR_Pos (21U)
10402#define EXTI_FTSR3_TR_Msk (0x3UL << EXTI_FTSR3_TR_Pos)
10403#define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk
10404#define EXTI_FTSR3_TR85_Pos (21U)
10405#define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos)
10406#define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk
10407#define EXTI_FTSR3_TR86_Pos (22U)
10408#define EXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos)
10409#define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk
10411/****************** Bit definition for EXTI_SWIER3 register ******************/
10412#define EXTI_SWIER3_SWI_Pos (21U)
10413#define EXTI_SWIER3_SWI_Msk (0x3UL << EXTI_SWIER3_SWI_Pos)
10414#define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk
10415#define EXTI_SWIER3_SWIER85_Pos (21U)
10416#define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos)
10417#define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk
10418#define EXTI_SWIER3_SWIER86_Pos (22U)
10419#define EXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos)
10420#define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk
10422/****************** Bit definition for EXTI_D3PMR3 register ******************/
10423#define EXTI_D3PMR3_MR88_Pos (24U)
10424#define EXTI_D3PMR3_MR88_Msk (0x1UL << EXTI_D3PMR3_MR88_Pos)
10425#define EXTI_D3PMR3_MR88 EXTI_D3PMR3_MR88_Msk
10427/******************* Bit definition for EXTI_D3PCR3H register ****************/
10428#define EXTI_D3PCR3H_PCS88_Pos (16U)
10429#define EXTI_D3PCR3H_PCS88_Msk (0x3UL << EXTI_D3PCR3H_PCS88_Pos)
10430#define EXTI_D3PCR3H_PCS88 EXTI_D3PCR3H_PCS88_Msk
10432/******************* Bit definition for EXTI_IMR1 register *******************/
10433#define EXTI_IMR1_IM_Pos (0U)
10434#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)
10435#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk
10436#define EXTI_IMR1_IM0_Pos (0U)
10437#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)
10438#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk
10439#define EXTI_IMR1_IM1_Pos (1U)
10440#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)
10441#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk
10442#define EXTI_IMR1_IM2_Pos (2U)
10443#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)
10444#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk
10445#define EXTI_IMR1_IM3_Pos (3U)
10446#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)
10447#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk
10448#define EXTI_IMR1_IM4_Pos (4U)
10449#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)
10450#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk
10451#define EXTI_IMR1_IM5_Pos (5U)
10452#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)
10453#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk
10454#define EXTI_IMR1_IM6_Pos (6U)
10455#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)
10456#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk
10457#define EXTI_IMR1_IM7_Pos (7U)
10458#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)
10459#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk
10460#define EXTI_IMR1_IM8_Pos (8U)
10461#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)
10462#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk
10463#define EXTI_IMR1_IM9_Pos (9U)
10464#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)
10465#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk
10466#define EXTI_IMR1_IM10_Pos (10U)
10467#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)
10468#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk
10469#define EXTI_IMR1_IM11_Pos (11U)
10470#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)
10471#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk
10472#define EXTI_IMR1_IM12_Pos (12U)
10473#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)
10474#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk
10475#define EXTI_IMR1_IM13_Pos (13U)
10476#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)
10477#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk
10478#define EXTI_IMR1_IM14_Pos (14U)
10479#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)
10480#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk
10481#define EXTI_IMR1_IM15_Pos (15U)
10482#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)
10483#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk
10484#define EXTI_IMR1_IM16_Pos (16U)
10485#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)
10486#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk
10487#define EXTI_IMR1_IM17_Pos (17U)
10488#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)
10489#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk
10490#define EXTI_IMR1_IM18_Pos (18U)
10491#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)
10492#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk
10493#define EXTI_IMR1_IM19_Pos (19U)
10494#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)
10495#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk
10496#define EXTI_IMR1_IM20_Pos (20U)
10497#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)
10498#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk
10499#define EXTI_IMR1_IM21_Pos (21U)
10500#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)
10501#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk
10502#define EXTI_IMR1_IM22_Pos (22U)
10503#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)
10504#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk
10505#define EXTI_IMR1_IM23_Pos (23U)
10506#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)
10507#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk
10508#define EXTI_IMR1_IM24_Pos (24U)
10509#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)
10510#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk
10511#define EXTI_IMR1_IM25_Pos (25U)
10512#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)
10513#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk
10514#define EXTI_IMR1_IM26_Pos (26U)
10515#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)
10516#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk
10517#define EXTI_IMR1_IM27_Pos (27U)
10518#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)
10519#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk
10520#define EXTI_IMR1_IM28_Pos (28U)
10521#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)
10522#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk
10523#define EXTI_IMR1_IM29_Pos (29U)
10524#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)
10525#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk
10526#define EXTI_IMR1_IM30_Pos (30U)
10527#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)
10528#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk
10529#define EXTI_IMR1_IM31_Pos (31U)
10530#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)
10531#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk
10533/******************* Bit definition for EXTI_EMR1 register *******************/
10534#define EXTI_EMR1_EM_Pos (0U)
10535#define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)
10536#define EXTI_EMR1_EM EXTI_EMR1_EM_Msk
10537#define EXTI_EMR1_EM0_Pos (0U)
10538#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)
10539#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk
10540#define EXTI_EMR1_EM1_Pos (1U)
10541#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)
10542#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk
10543#define EXTI_EMR1_EM2_Pos (2U)
10544#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)
10545#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk
10546#define EXTI_EMR1_EM3_Pos (3U)
10547#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)
10548#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk
10549#define EXTI_EMR1_EM4_Pos (4U)
10550#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)
10551#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk
10552#define EXTI_EMR1_EM5_Pos (5U)
10553#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)
10554#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk
10555#define EXTI_EMR1_EM6_Pos (6U)
10556#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)
10557#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk
10558#define EXTI_EMR1_EM7_Pos (7U)
10559#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)
10560#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk
10561#define EXTI_EMR1_EM8_Pos (8U)
10562#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)
10563#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk
10564#define EXTI_EMR1_EM9_Pos (9U)
10565#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)
10566#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk
10567#define EXTI_EMR1_EM10_Pos (10U)
10568#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)
10569#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk
10570#define EXTI_EMR1_EM11_Pos (11U)
10571#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)
10572#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk
10573#define EXTI_EMR1_EM12_Pos (12U)
10574#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)
10575#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk
10576#define EXTI_EMR1_EM13_Pos (13U)
10577#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)
10578#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk
10579#define EXTI_EMR1_EM14_Pos (14U)
10580#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)
10581#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk
10582#define EXTI_EMR1_EM15_Pos (15U)
10583#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)
10584#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk
10585#define EXTI_EMR1_EM16_Pos (16U)
10586#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)
10587#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk
10588#define EXTI_EMR1_EM17_Pos (17U)
10589#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)
10590#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk
10591#define EXTI_EMR1_EM18_Pos (18U)
10592#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)
10593#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk
10594#define EXTI_EMR1_EM20_Pos (20U)
10595#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)
10596#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk
10597#define EXTI_EMR1_EM21_Pos (21U)
10598#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)
10599#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk
10600#define EXTI_EMR1_EM22_Pos (22U)
10601#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)
10602#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk
10603#define EXTI_EMR1_EM23_Pos (23U)
10604#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)
10605#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk
10606#define EXTI_EMR1_EM24_Pos (24U)
10607#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)
10608#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk
10609#define EXTI_EMR1_EM25_Pos (25U)
10610#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)
10611#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk
10612#define EXTI_EMR1_EM26_Pos (26U)
10613#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)
10614#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk
10615#define EXTI_EMR1_EM27_Pos (27U)
10616#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)
10617#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk
10618#define EXTI_EMR1_EM28_Pos (28U)
10619#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)
10620#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk
10621#define EXTI_EMR1_EM29_Pos (29U)
10622#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos)
10623#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk
10624#define EXTI_EMR1_EM30_Pos (30U)
10625#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos)
10626#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk
10627#define EXTI_EMR1_EM31_Pos (31U)
10628#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)
10629#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk
10631/******************* Bit definition for EXTI_PR1 register ********************/
10632#define EXTI_PR1_PR_Pos (0U)
10633#define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos)
10634#define EXTI_PR1_PR EXTI_PR1_PR_Msk
10635#define EXTI_PR1_PR0_Pos (0U)
10636#define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos)
10637#define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk
10638#define EXTI_PR1_PR1_Pos (1U)
10639#define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos)
10640#define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk
10641#define EXTI_PR1_PR2_Pos (2U)
10642#define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos)
10643#define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk
10644#define EXTI_PR1_PR3_Pos (3U)
10645#define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos)
10646#define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk
10647#define EXTI_PR1_PR4_Pos (4U)
10648#define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos)
10649#define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk
10650#define EXTI_PR1_PR5_Pos (5U)
10651#define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos)
10652#define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk
10653#define EXTI_PR1_PR6_Pos (6U)
10654#define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos)
10655#define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk
10656#define EXTI_PR1_PR7_Pos (7U)
10657#define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos)
10658#define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk
10659#define EXTI_PR1_PR8_Pos (8U)
10660#define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos)
10661#define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk
10662#define EXTI_PR1_PR9_Pos (9U)
10663#define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos)
10664#define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk
10665#define EXTI_PR1_PR10_Pos (10U)
10666#define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos)
10667#define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk
10668#define EXTI_PR1_PR11_Pos (11U)
10669#define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos)
10670#define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk
10671#define EXTI_PR1_PR12_Pos (12U)
10672#define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos)
10673#define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk
10674#define EXTI_PR1_PR13_Pos (13U)
10675#define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos)
10676#define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk
10677#define EXTI_PR1_PR14_Pos (14U)
10678#define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos)
10679#define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk
10680#define EXTI_PR1_PR15_Pos (15U)
10681#define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos)
10682#define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk
10683#define EXTI_PR1_PR16_Pos (16U)
10684#define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos)
10685#define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk
10686#define EXTI_PR1_PR17_Pos (17U)
10687#define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos)
10688#define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk
10689#define EXTI_PR1_PR18_Pos (18U)
10690#define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos)
10691#define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk
10692#define EXTI_PR1_PR19_Pos (19U)
10693#define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos)
10694#define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk
10695#define EXTI_PR1_PR20_Pos (20U)
10696#define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos)
10697#define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk
10698#define EXTI_PR1_PR21_Pos (21U)
10699#define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos)
10700#define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk
10702/******************* Bit definition for EXTI_IMR2 register *******************/
10703#define EXTI_IMR2_IM_Pos (0U)
10704#define EXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)
10705#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
10706#define EXTI_IMR2_IM32_Pos (0U)
10707#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos)
10708#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk
10709#define EXTI_IMR2_IM33_Pos (1U)
10710#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos)
10711#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk
10712#define EXTI_IMR2_IM34_Pos (2U)
10713#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)
10714#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk
10715#define EXTI_IMR2_IM35_Pos (3U)
10716#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos)
10717#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk
10718#define EXTI_IMR2_IM36_Pos (4U)
10719#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)
10720#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk
10721#define EXTI_IMR2_IM37_Pos (5U)
10722#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)
10723#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk
10724#define EXTI_IMR2_IM38_Pos (6U)
10725#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)
10726#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk
10727#define EXTI_IMR2_IM39_Pos (7U)
10728#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos)
10729#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk
10730#define EXTI_IMR2_IM40_Pos (8U)
10731#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos)
10732#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk
10733#define EXTI_IMR2_IM41_Pos (9U)
10734#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos)
10735#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk
10736#define EXTI_IMR2_IM42_Pos (10U)
10737#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos)
10738#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk
10739#define EXTI_IMR2_IM43_Pos (11U)
10740#define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos)
10741#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk
10742#define EXTI_IMR2_IM47_Pos (15U)
10743#define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos)
10744#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk
10745#define EXTI_IMR2_IM48_Pos (16U)
10746#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos)
10747#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk
10748#define EXTI_IMR2_IM49_Pos (17U)
10749#define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos)
10750#define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk
10751#define EXTI_IMR2_IM50_Pos (18U)
10752#define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos)
10753#define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk
10754#define EXTI_IMR2_IM51_Pos (19U)
10755#define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos)
10756#define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk
10757#define EXTI_IMR2_IM52_Pos (20U)
10758#define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos)
10759#define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk
10760#define EXTI_IMR2_IM53_Pos (21U)
10761#define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos)
10762#define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk
10763#define EXTI_IMR2_IM54_Pos (22U)
10764#define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos)
10765#define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk
10766#define EXTI_IMR2_IM55_Pos (23U)
10767#define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos)
10768#define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk
10769#define EXTI_IMR2_IM56_Pos (24U)
10770#define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos)
10771#define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk
10772#define EXTI_IMR2_IM58_Pos (26U)
10773#define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos)
10774#define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk
10775#define EXTI_IMR2_IM60_Pos (28U)
10776#define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos)
10777#define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk
10778#define EXTI_IMR2_IM61_Pos (29U)
10779#define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos)
10780#define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk
10781#define EXTI_IMR2_IM62_Pos (30U)
10782#define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos)
10783#define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk
10784#define EXTI_IMR2_IM63_Pos (31U)
10785#define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos)
10786#define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk
10788/******************* Bit definition for EXTI_EMR2 register *******************/
10789#define EXTI_EMR2_EM_Pos (0U)
10790#define EXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)
10791#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
10792#define EXTI_EMR2_EM32_Pos (0U)
10793#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos)
10794#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk
10795#define EXTI_EMR2_EM33_Pos (1U)
10796#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos)
10797#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk
10798#define EXTI_EMR2_EM34_Pos (2U)
10799#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)
10800#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk
10801#define EXTI_EMR2_EM35_Pos (3U)
10802#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos)
10803#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk
10804#define EXTI_EMR2_EM36_Pos (4U)
10805#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos)
10806#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk
10807#define EXTI_EMR2_EM37_Pos (5U)
10808#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)
10809#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk
10810#define EXTI_EMR2_EM38_Pos (6U)
10811#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)
10812#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk
10813#define EXTI_EMR2_EM39_Pos (7U)
10814#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos)
10815#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk
10816#define EXTI_EMR2_EM40_Pos (8U)
10817#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos)
10818#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk
10819#define EXTI_EMR2_EM41_Pos (9U)
10820#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos)
10821#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk
10822#define EXTI_EMR2_EM42_Pos (10U)
10823#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos)
10824#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk
10825#define EXTI_EMR2_EM43_Pos (11U)
10826#define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos)
10827#define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk
10828#define EXTI_EMR2_EM47_Pos (15U)
10829#define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos)
10830#define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk
10831#define EXTI_EMR2_EM48_Pos (16U)
10832#define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos)
10833#define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk
10834#define EXTI_EMR2_EM49_Pos (17U)
10835#define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos)
10836#define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk
10837#define EXTI_EMR2_EM50_Pos (18U)
10838#define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos)
10839#define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk
10840#define EXTI_EMR2_EM51_Pos (19U)
10841#define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos)
10842#define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk
10843#define EXTI_EMR2_EM52_Pos (20U)
10844#define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos)
10845#define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk
10846#define EXTI_EMR2_EM53_Pos (21U)
10847#define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos)
10848#define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk
10849#define EXTI_EMR2_EM54_Pos (22U)
10850#define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos)
10851#define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk
10852#define EXTI_EMR2_EM55_Pos (23U)
10853#define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos)
10854#define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk
10855#define EXTI_EMR2_EM56_Pos (24U)
10856#define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos)
10857#define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk
10858#define EXTI_EMR2_EM58_Pos (26U)
10859#define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos)
10860#define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk
10861#define EXTI_EMR2_EM60_Pos (28U)
10862#define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos)
10863#define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk
10864#define EXTI_EMR2_EM61_Pos (29U)
10865#define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos)
10866#define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk
10867#define EXTI_EMR2_EM62_Pos (30U)
10868#define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos)
10869#define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk
10870#define EXTI_EMR2_EM63_Pos (31U)
10871#define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos)
10872#define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk
10874/******************* Bit definition for EXTI_PR2 register ********************/
10875#define EXTI_PR2_PR_Pos (17U)
10876#define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos)
10877#define EXTI_PR2_PR EXTI_PR2_PR_Msk
10878#define EXTI_PR2_PR49_Pos (17U)
10879#define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos)
10880#define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk
10881#define EXTI_PR2_PR51_Pos (19U)
10882#define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos)
10883#define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk
10885/******************* Bit definition for EXTI_IMR3 register *******************/
10886#define EXTI_IMR3_IM_Pos (0U)
10887#define EXTI_IMR3_IM_Msk (0x0FE17FFFUL << EXTI_IMR3_IM_Pos)
10888#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk
10889#define EXTI_IMR3_IM64_Pos (0U)
10890#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos)
10891#define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk
10892#define EXTI_IMR3_IM65_Pos (1U)
10893#define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos)
10894#define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk
10895#define EXTI_IMR3_IM66_Pos (2U)
10896#define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos)
10897#define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk
10898#define EXTI_IMR3_IM67_Pos (3U)
10899#define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos)
10900#define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk
10901#define EXTI_IMR3_IM68_Pos (4U)
10902#define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos)
10903#define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk
10904#define EXTI_IMR3_IM69_Pos (5U)
10905#define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos)
10906#define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk
10907#define EXTI_IMR3_IM70_Pos (6U)
10908#define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos)
10909#define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk
10910#define EXTI_IMR3_IM71_Pos (7U)
10911#define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos)
10912#define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk
10913#define EXTI_IMR3_IM72_Pos (8U)
10914#define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos)
10915#define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk
10916#define EXTI_IMR3_IM73_Pos (9U)
10917#define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos)
10918#define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk
10919#define EXTI_IMR3_IM74_Pos (10U)
10920#define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos)
10921#define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk
10922#define EXTI_IMR3_IM75_Pos (11U)
10923#define EXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos)
10924#define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk
10925#define EXTI_IMR3_IM76_Pos (12U)
10926#define EXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos)
10927#define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk
10928#define EXTI_IMR3_IM77_Pos (13U)
10929#define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos)
10930#define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk
10931#define EXTI_IMR3_IM78_Pos (14U)
10932#define EXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos)
10933#define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk
10934#define EXTI_IMR3_IM80_Pos (16U)
10935#define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos)
10936#define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk
10937#define EXTI_IMR3_IM85_Pos (21U)
10938#define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos)
10939#define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk
10940#define EXTI_IMR3_IM86_Pos (22U)
10941#define EXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos)
10942#define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk
10943#define EXTI_IMR3_IM87_Pos (23U)
10944#define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos)
10945#define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk
10948#define EXTI_IMR3_IM88_Pos (24U)
10949#define EXTI_IMR3_IM88_Msk (0x1UL << EXTI_IMR3_IM88_Pos)
10950#define EXTI_IMR3_IM88 EXTI_IMR3_IM88_Msk
10952#define EXTI_IMR3_IM89_Pos (25U)
10953#define EXTI_IMR3_IM89_Msk (0x1UL << EXTI_IMR3_IM89_Pos)
10954#define EXTI_IMR3_IM89 EXTI_IMR3_IM89_Msk
10955#define EXTI_IMR3_IM90_Pos (26U)
10956#define EXTI_IMR3_IM90_Msk (0x1UL << EXTI_IMR3_IM90_Pos)
10957#define EXTI_IMR3_IM90 EXTI_IMR3_IM90_Msk
10958#define EXTI_IMR3_IM91_Pos (27U)
10959#define EXTI_IMR3_IM91_Msk (0x1UL << EXTI_IMR3_IM91_Pos)
10960#define EXTI_IMR3_IM91 EXTI_IMR3_IM91_Msk
10962/******************* Bit definition for EXTI_EMR3 register *******************/
10963#define EXTI_EMR3_EM_Pos (0U)
10964#define EXTI_EMR3_EM_Msk (0x0FE17FFFUL << EXTI_EMR3_EM_Pos)
10965#define EXTI_EMR3_EM EXTI_EMR3_EM_Msk
10966#define EXTI_EMR3_EM64_Pos (0U)
10967#define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos)
10968#define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk
10969#define EXTI_EMR3_EM65_Pos (1U)
10970#define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos)
10971#define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk
10972#define EXTI_EMR3_EM66_Pos (2U)
10973#define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos)
10974#define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk
10975#define EXTI_EMR3_EM67_Pos (3U)
10976#define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos)
10977#define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk
10978#define EXTI_EMR3_EM68_Pos (4U)
10979#define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos)
10980#define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk
10981#define EXTI_EMR3_EM69_Pos (5U)
10982#define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos)
10983#define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk
10984#define EXTI_EMR3_EM70_Pos (6U)
10985#define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos)
10986#define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk
10987#define EXTI_EMR3_EM71_Pos (7U)
10988#define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos)
10989#define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk
10990#define EXTI_EMR3_EM72_Pos (8U)
10991#define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos)
10992#define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk
10993#define EXTI_EMR3_EM73_Pos (9U)
10994#define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos)
10995#define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk
10996#define EXTI_EMR3_EM74_Pos (10U)
10997#define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos)
10998#define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk
10999#define EXTI_EMR3_EM75_Pos (11U)
11000#define EXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos)
11001#define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk
11002#define EXTI_EMR3_EM76_Pos (12U)
11003#define EXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos)
11004#define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk
11005#define EXTI_EMR3_EM77_Pos (13U)
11006#define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos)
11007#define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk
11008#define EXTI_EMR3_EM78_Pos (14U)
11009#define EXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos)
11010#define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk
11011#define EXTI_EMR3_EM80_Pos (16U)
11012#define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos)
11013#define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk
11014#define EXTI_EMR3_EM85_Pos (21U)
11015#define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos)
11016#define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk
11017#define EXTI_EMR3_EM86_Pos (22U)
11018#define EXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos)
11019#define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk
11020#define EXTI_EMR3_EM87_Pos (23U)
11021#define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos)
11022#define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk
11024#define EXTI_EMR3_EM88_Pos (24U)
11025#define EXTI_EMR3_EM88_Msk (0x1UL << EXTI_EMR3_EM88_Pos)
11026#define EXTI_EMR3_EM88 EXTI_EMR3_EM88_Msk
11028#define EXTI_EMR3_EM89_Pos (25U)
11029#define EXTI_EMR3_EM89_Msk (0x1UL << EXTI_EMR3_EM89_Pos)
11030#define EXTI_EMR3_EM89 EXTI_EMR3_EM89_Msk
11031#define EXTI_EMR3_EM90_Pos (26U)
11032#define EXTI_EMR3_EM90_Msk (0x1UL << EXTI_EMR3_EM90_Pos)
11033#define EXTI_EMR3_EM90 EXTI_EMR3_EM90_Msk
11034#define EXTI_EMR3_EM91_Pos (27U)
11035#define EXTI_EMR3_EM91_Msk (0x1UL << EXTI_EMR3_EM91_Pos)
11036#define EXTI_EMR3_EM91 EXTI_EMR3_EM91_Msk
11038/******************* Bit definition for EXTI_PR3 register ********************/
11039#define EXTI_PR3_PR_Pos (20U)
11040#define EXTI_PR3_PR_Msk (0x7UL << EXTI_PR3_PR_Pos)
11041#define EXTI_PR3_PR EXTI_PR3_PR_Msk
11042#define EXTI_PR3_PR84_Pos (20U)
11043#define EXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos)
11044#define EXTI_PR3_PR84 EXTI_PR3_PR84_Msk
11045#define EXTI_PR3_PR85_Pos (21U)
11046#define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos)
11047#define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk
11048#define EXTI_PR3_PR86_Pos (22U)
11049#define EXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos)
11050#define EXTI_PR3_PR86 EXTI_PR3_PR86_Msk
11051/******************************************************************************/
11052/* */
11053/* FLASH */
11054/* */
11055/******************************************************************************/
11056/*
11057* @brief FLASH Global Defines
11058*/
11059#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
11060#define FLASH_SECTOR_TOTAL 1U /* 1 sector */
11061#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
11062#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x20000U : \
11063 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x20000U : \
11064 (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 128 KB */
11065#define FLASH_BANK_SIZE FLASH_SIZE /* 128 KB */
11066#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
11067#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
11068
11069/******************* Bits definition for FLASH_ACR register **********************/
11070#define FLASH_ACR_LATENCY_Pos (0U)
11071#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
11072#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
11073#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
11074#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
11075#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
11076#define FLASH_ACR_LATENCY_3WS (0x00000003UL)
11077#define FLASH_ACR_LATENCY_4WS (0x00000004UL)
11078#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
11079#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
11080#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
11081
11082#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
11083#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)
11084#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk
11085#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)
11086#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)
11088/* Legacy FLASH Latency defines */
11089#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
11090#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
11091#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
11092#define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
11093#define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
11094#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
11095#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
11096#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
11097/******************* Bits definition for FLASH_CR register ***********************/
11098#define FLASH_CR_LOCK_Pos (0U)
11099#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
11100#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
11101#define FLASH_CR_PG_Pos (1U)
11102#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
11103#define FLASH_CR_PG FLASH_CR_PG_Msk
11104#define FLASH_CR_SER_Pos (2U)
11105#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
11106#define FLASH_CR_SER FLASH_CR_SER_Msk
11107#define FLASH_CR_BER_Pos (3U)
11108#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos)
11109#define FLASH_CR_BER FLASH_CR_BER_Msk
11110#define FLASH_CR_PSIZE_Pos (4U)
11111#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
11112#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
11113#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
11114#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
11115#define FLASH_CR_FW_Pos (6U)
11116#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos)
11117#define FLASH_CR_FW FLASH_CR_FW_Msk
11118#define FLASH_CR_START_Pos (7U)
11119#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos)
11120#define FLASH_CR_START FLASH_CR_START_Msk
11121#define FLASH_CR_SNB_Pos (8U)
11122#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos)
11123#define FLASH_CR_SNB FLASH_CR_SNB_Msk
11124#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos)
11125#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos)
11126#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos)
11127#define FLASH_CR_CRC_EN_Pos (15U)
11128#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos)
11129#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk
11130#define FLASH_CR_EOPIE_Pos (16U)
11131#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
11132#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
11133#define FLASH_CR_WRPERRIE_Pos (17U)
11134#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos)
11135#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk
11136#define FLASH_CR_PGSERRIE_Pos (18U)
11137#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos)
11138#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk
11139#define FLASH_CR_STRBERRIE_Pos (19U)
11140#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos)
11141#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk
11142#define FLASH_CR_INCERRIE_Pos (21U)
11143#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos)
11144#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk
11145#define FLASH_CR_OPERRIE_Pos (22U)
11146#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos)
11147#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk
11148#define FLASH_CR_RDPERRIE_Pos (23U)
11149#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos)
11150#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk
11151#define FLASH_CR_RDSERRIE_Pos (24U)
11152#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos)
11153#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk
11154#define FLASH_CR_SNECCERRIE_Pos (25U)
11155#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos)
11156#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk
11157#define FLASH_CR_DBECCERRIE_Pos (26U)
11158#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos)
11159#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk
11160#define FLASH_CR_CRCENDIE_Pos (27U)
11161#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos)
11162#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk
11163#define FLASH_CR_CRCRDERRIE_Pos (28U)
11164#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos)
11165#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk
11167/******************* Bits definition for FLASH_SR register ***********************/
11168#define FLASH_SR_BSY_Pos (0U)
11169#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
11170#define FLASH_SR_BSY FLASH_SR_BSY_Msk
11171#define FLASH_SR_WBNE_Pos (1U)
11172#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos)
11173#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk
11174#define FLASH_SR_QW_Pos (2U)
11175#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos)
11176#define FLASH_SR_QW FLASH_SR_QW_Msk
11177#define FLASH_SR_CRC_BUSY_Pos (3U)
11178#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos)
11179#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk
11180#define FLASH_SR_EOP_Pos (16U)
11181#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
11182#define FLASH_SR_EOP FLASH_SR_EOP_Msk
11183#define FLASH_SR_WRPERR_Pos (17U)
11184#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
11185#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
11186#define FLASH_SR_PGSERR_Pos (18U)
11187#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
11188#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
11189#define FLASH_SR_STRBERR_Pos (19U)
11190#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos)
11191#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk
11192#define FLASH_SR_INCERR_Pos (21U)
11193#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos)
11194#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk
11195#define FLASH_SR_OPERR_Pos (22U)
11196#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
11197#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
11198#define FLASH_SR_RDPERR_Pos (23U)
11199#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos)
11200#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk
11201#define FLASH_SR_RDSERR_Pos (24U)
11202#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos)
11203#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk
11204#define FLASH_SR_SNECCERR_Pos (25U)
11205#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos)
11206#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk
11207#define FLASH_SR_DBECCERR_Pos (26U)
11208#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos)
11209#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk
11210#define FLASH_SR_CRCEND_Pos (27U)
11211#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos)
11212#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk
11213#define FLASH_SR_CRCRDERR_Pos (28U)
11214#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos)
11215#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk
11217/******************* Bits definition for FLASH_CCR register *******************/
11218#define FLASH_CCR_CLR_EOP_Pos (16U)
11219#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos)
11220#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk
11221#define FLASH_CCR_CLR_WRPERR_Pos (17U)
11222#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos)
11223#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk
11224#define FLASH_CCR_CLR_PGSERR_Pos (18U)
11225#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos)
11226#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk
11227#define FLASH_CCR_CLR_STRBERR_Pos (19U)
11228#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos)
11229#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk
11230#define FLASH_CCR_CLR_INCERR_Pos (21U)
11231#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos)
11232#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk
11233#define FLASH_CCR_CLR_OPERR_Pos (22U)
11234#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos)
11235#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk
11236#define FLASH_CCR_CLR_RDPERR_Pos (23U)
11237#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos)
11238#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk
11239#define FLASH_CCR_CLR_RDSERR_Pos (24U)
11240#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos)
11241#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk
11242#define FLASH_CCR_CLR_SNECCERR_Pos (25U)
11243#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos)
11244#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk
11245#define FLASH_CCR_CLR_DBECCERR_Pos (26U)
11246#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos)
11247#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk
11248#define FLASH_CCR_CLR_CRCEND_Pos (27U)
11249#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos)
11250#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk
11251#define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
11252#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos)
11253#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk
11255/******************* Bits definition for FLASH_OPTCR register *******************/
11256#define FLASH_OPTCR_OPTLOCK_Pos (0U)
11257#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
11258#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
11259#define FLASH_OPTCR_OPTSTART_Pos (1U)
11260#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos)
11261#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk
11262#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
11263#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos)
11264#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk
11266/******************* Bits definition for FLASH_OPTSR register ***************/
11267#define FLASH_OPTSR_OPT_BUSY_Pos (0U)
11268#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos)
11269#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk
11270#define FLASH_OPTSR_BOR_LEV_Pos (2U)
11271#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos)
11272#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk
11273#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos)
11274#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos)
11275#define FLASH_OPTSR_IWDG1_SW_Pos (4U)
11276#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos)
11277#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk
11278#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
11279#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos)
11280#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk
11281#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
11282#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos)
11283#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk
11284#define FLASH_OPTSR_RDP_Pos (8U)
11285#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos)
11286#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk
11287#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
11288#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos)
11289#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk
11290#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
11291#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos)
11292#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk
11293#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
11294#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
11295#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk
11296#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
11297#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
11298#define FLASH_OPTSR_SECURITY_Pos (21U)
11299#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos)
11300#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk
11301#define FLASH_OPTSR_NRST_STOP_D2_Pos (24U)
11302#define FLASH_OPTSR_NRST_STOP_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos)
11303#define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk
11304#define FLASH_OPTSR_NRST_STBY_D2_Pos (25U)
11305#define FLASH_OPTSR_NRST_STBY_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos)
11306#define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk
11307#define FLASH_OPTSR_IO_HSLV_Pos (29U)
11308#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos)
11309#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk
11310#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
11311#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos)
11312#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk
11314/******************* Bits definition for FLASH_OPTCCR register *******************/
11315#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
11316#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos)
11317#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk
11319/******************* Bits definition for FLASH_PRAR register *********************/
11320#define FLASH_PRAR_PROT_AREA_START_Pos (0U)
11321#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos)
11322#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk
11323#define FLASH_PRAR_PROT_AREA_END_Pos (16U)
11324#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos)
11325#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk
11326#define FLASH_PRAR_DMEP_Pos (31U)
11327#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos)
11328#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk
11330/******************* Bits definition for FLASH_SCAR register *********************/
11331#define FLASH_SCAR_SEC_AREA_START_Pos (0U)
11332#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos)
11333#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk
11334#define FLASH_SCAR_SEC_AREA_END_Pos (16U)
11335#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos)
11336#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk
11337#define FLASH_SCAR_DMES_Pos (31U)
11338#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos)
11339#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk
11341/******************* Bits definition for FLASH_WPSN register *********************/
11342#define FLASH_WPSN_WRPSN_Pos (0U)
11343#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos)
11344#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk
11346/******************* Bits definition for FLASH_BOOT_CUR register ****************/
11347#define FLASH_BOOT_ADD0_Pos (0U)
11348#define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos)
11349#define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk
11350#define FLASH_BOOT_ADD1_Pos (16U)
11351#define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos)
11352#define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk
11355/******************* Bits definition for FLASH_CRCCR register ********************/
11356#define FLASH_CRCCR_CRC_SECT_Pos (0U)
11357#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos)
11358#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk
11359#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
11360#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos)
11361#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk
11362#define FLASH_CRCCR_ADD_SECT_Pos (9U)
11363#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos)
11364#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk
11365#define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
11366#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos)
11367#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk
11368#define FLASH_CRCCR_START_CRC_Pos (16U)
11369#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos)
11370#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk
11371#define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
11372#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos)
11373#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk
11374#define FLASH_CRCCR_CRC_BURST_Pos (20U)
11375#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos)
11376#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk
11377#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos)
11378#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos)
11379#define FLASH_CRCCR_ALL_BANK_Pos (22U)
11380#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos)
11381#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk
11383/******************* Bits definition for FLASH_CRCSADD register ****************/
11384#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
11385#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos)
11386#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk
11388/******************* Bits definition for FLASH_CRCEADD register ****************/
11389#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
11390#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos)
11391#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk
11393/******************* Bits definition for FLASH_CRCDATA register ***************/
11394#define FLASH_CRCDATA_CRC_DATA_Pos (0U)
11395#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos)
11396#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk
11398/******************* Bits definition for FLASH_ECC_FA register *******************/
11399#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
11400#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos)
11401#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk
11403/******************* Bits definition for FLASH_OPTSR2 register *******************/
11404#define FLASH_OPTSR2_TCM_AXI_SHARED_Pos (0U)
11405#define FLASH_OPTSR2_TCM_AXI_SHARED_Msk (0x3UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos)
11406#define FLASH_OPTSR2_TCM_AXI_SHARED FLASH_OPTSR2_TCM_AXI_SHARED_Msk
11407#define FLASH_OPTSR2_TCM_AXI_SHARED_0 (0x1UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos)
11408#define FLASH_OPTSR2_TCM_AXI_SHARED_1 (0x2UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos)
11409#define FLASH_OPTSR2_CPUFREQ_BOOST_Pos (2U)
11410#define FLASH_OPTSR2_CPUFREQ_BOOST_Msk (0x1UL << FLASH_OPTSR2_CPUFREQ_BOOST_Pos)
11411#define FLASH_OPTSR2_CPUFREQ_BOOST FLASH_OPTSR2_CPUFREQ_BOOST_Msk
11413/******************************************************************************/
11414/* */
11415/* Filter Mathematical ACcelerator unit (FMAC) */
11416/* */
11417/******************************************************************************/
11418/***************** Bit definition for FMAC_X1BUFCFG register ****************/
11419#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
11420#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)
11421#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk
11422#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
11423#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)
11424#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk
11425#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
11426#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos)
11427#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk
11428/***************** Bit definition for FMAC_X2BUFCFG register ****************/
11429#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
11430#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)
11431#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk
11432#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
11433#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)
11434#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk
11435/***************** Bit definition for FMAC_YBUFCFG register *****************/
11436#define FMAC_YBUFCFG_Y_BASE_Pos (0U)
11437#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)
11438#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk
11439#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
11440#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)
11441#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk
11442#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
11443#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos)
11444#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk
11445/****************** Bit definition for FMAC_PARAM register ******************/
11446#define FMAC_PARAM_P_Pos (0U)
11447#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos)
11448#define FMAC_PARAM_P FMAC_PARAM_P_Msk
11449#define FMAC_PARAM_Q_Pos (8U)
11450#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos)
11451#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk
11452#define FMAC_PARAM_R_Pos (16U)
11453#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos)
11454#define FMAC_PARAM_R FMAC_PARAM_R_Msk
11455#define FMAC_PARAM_FUNC_Pos (24U)
11456#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos)
11457#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk
11458#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos)
11459#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos)
11460#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos)
11461#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos)
11462#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos)
11463#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos)
11464#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos)
11465#define FMAC_PARAM_START_Pos (31U)
11466#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos)
11467#define FMAC_PARAM_START FMAC_PARAM_START_Msk
11468/******************** Bit definition for FMAC_CR register *******************/
11469#define FMAC_CR_RIEN_Pos (0U)
11470#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos)
11471#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk
11472#define FMAC_CR_WIEN_Pos (1U)
11473#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos)
11474#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk
11475#define FMAC_CR_OVFLIEN_Pos (2U)
11476#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos)
11477#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk
11478#define FMAC_CR_UNFLIEN_Pos (3U)
11479#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos)
11480#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk
11481#define FMAC_CR_SATIEN_Pos (4U)
11482#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos)
11483#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk
11484#define FMAC_CR_DMAREN_Pos (8U)
11485#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos)
11486#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk
11487#define FMAC_CR_DMAWEN_Pos (9U)
11488#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos)
11489#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk
11490#define FMAC_CR_CLIPEN_Pos (15U)
11491#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos)
11492#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk
11493#define FMAC_CR_RESET_Pos (16U)
11494#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos)
11495#define FMAC_CR_RESET FMAC_CR_RESET_Msk
11496/******************* Bit definition for FMAC_SR register ********************/
11497#define FMAC_SR_YEMPTY_Pos (0U)
11498#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos)
11499#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk
11500#define FMAC_SR_X1FULL_Pos (1U)
11501#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos)
11502#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk
11503#define FMAC_SR_OVFL_Pos (8U)
11504#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos)
11505#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk
11506#define FMAC_SR_UNFL_Pos (9U)
11507#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos)
11508#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk
11509#define FMAC_SR_SAT_Pos (10U)
11510#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos)
11511#define FMAC_SR_SAT FMAC_SR_SAT_Msk
11512/****************** Bit definition for FMAC_WDATA register ******************/
11513#define FMAC_WDATA_WDATA_Pos (0U)
11514#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos)
11515#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk
11516/****************** Bit definition for FMACX_RDATA register *****************/
11517#define FMAC_RDATA_RDATA_Pos (0U)
11518#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos)
11519#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk
11521/******************************************************************************/
11522/* */
11523/* Flexible Memory Controller */
11524/* */
11525/******************************************************************************/
11526/****************** Bit definition for FMC_BCR1 register *******************/
11527#define FMC_BCR1_CCLKEN_Pos (20U)
11528#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
11529#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
11530#define FMC_BCR1_WFDIS_Pos (21U)
11531#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
11532#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
11534#define FMC_BCR1_BMAP_Pos (24U)
11535#define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos)
11536#define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk
11537#define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos)
11538#define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos)
11540#define FMC_BCR1_FMCEN_Pos (31U)
11541#define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos)
11542#define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk
11543/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
11544#define FMC_BCRx_MBKEN_Pos (0U)
11545#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)
11546#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk
11547#define FMC_BCRx_MUXEN_Pos (1U)
11548#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)
11549#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk
11551#define FMC_BCRx_MTYP_Pos (2U)
11552#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)
11553#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk
11554#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)
11555#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)
11557#define FMC_BCRx_MWID_Pos (4U)
11558#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)
11559#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk
11560#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)
11561#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)
11563#define FMC_BCRx_FACCEN_Pos (6U)
11564#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)
11565#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk
11566#define FMC_BCRx_BURSTEN_Pos (8U)
11567#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)
11568#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk
11569#define FMC_BCRx_WAITPOL_Pos (9U)
11570#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)
11571#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk
11572#define FMC_BCRx_WAITCFG_Pos (11U)
11573#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)
11574#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk
11575#define FMC_BCRx_WREN_Pos (12U)
11576#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)
11577#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk
11578#define FMC_BCRx_WAITEN_Pos (13U)
11579#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)
11580#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk
11581#define FMC_BCRx_EXTMOD_Pos (14U)
11582#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)
11583#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk
11584#define FMC_BCRx_ASYNCWAIT_Pos (15U)
11585#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)
11586#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk
11588#define FMC_BCRx_CPSIZE_Pos (16U)
11589#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos)
11590#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk
11591#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos)
11592#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos)
11593#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos)
11595#define FMC_BCRx_CBURSTRW_Pos (19U)
11596#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)
11597#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk
11599/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
11600#define FMC_BTRx_ADDSET_Pos (0U)
11601#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)
11602#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk
11603#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)
11604#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)
11605#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)
11606#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos)
11608#define FMC_BTRx_ADDHLD_Pos (4U)
11609#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)
11610#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk
11611#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)
11612#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)
11613#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)
11614#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)
11616#define FMC_BTRx_DATAST_Pos (8U)
11617#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)
11618#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk
11619#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos)
11620#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos)
11621#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos)
11622#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos)
11623#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos)
11624#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos)
11625#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos)
11626#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos)
11628#define FMC_BTRx_BUSTURN_Pos (16U)
11629#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)
11630#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk
11631#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)
11632#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)
11633#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)
11634#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)
11636#define FMC_BTRx_CLKDIV_Pos (20U)
11637#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)
11638#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk
11639#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)
11640#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)
11641#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)
11642#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)
11644#define FMC_BTRx_DATLAT_Pos (24U)
11645#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)
11646#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk
11647#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)
11648#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)
11649#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)
11650#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)
11652#define FMC_BTRx_ACCMOD_Pos (28U)
11653#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)
11654#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk
11655#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)
11656#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)
11658/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
11659#define FMC_BWTRx_ADDSET_Pos (0U)
11660#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)
11661#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk
11662#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)
11663#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)
11664#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)
11665#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)
11667#define FMC_BWTRx_ADDHLD_Pos (4U)
11668#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)
11669#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk
11670#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)
11671#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)
11672#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)
11673#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)
11675#define FMC_BWTRx_DATAST_Pos (8U)
11676#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)
11677#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk
11678#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)
11679#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)
11680#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)
11681#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)
11682#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)
11683#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)
11684#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)
11685#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)
11687#define FMC_BWTRx_BUSTURN_Pos (16U)
11688#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos)
11689#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk
11690#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos)
11691#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos)
11692#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos)
11693#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos)
11695#define FMC_BWTRx_ACCMOD_Pos (28U)
11696#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)
11697#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk
11698#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)
11699#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)
11701/****************** Bit definition for FMC_PCR register *******************/
11702#define FMC_PCR_PWAITEN_Pos (1U)
11703#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
11704#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
11705#define FMC_PCR_PBKEN_Pos (2U)
11706#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
11707#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
11709#define FMC_PCR_PWID_Pos (4U)
11710#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
11711#define FMC_PCR_PWID FMC_PCR_PWID_Msk
11712#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
11713#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
11715#define FMC_PCR_ECCEN_Pos (6U)
11716#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
11717#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
11719#define FMC_PCR_TCLR_Pos (9U)
11720#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
11721#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
11722#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
11723#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
11724#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
11725#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
11727#define FMC_PCR_TAR_Pos (13U)
11728#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
11729#define FMC_PCR_TAR FMC_PCR_TAR_Msk
11730#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
11731#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
11732#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
11733#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
11735#define FMC_PCR_ECCPS_Pos (17U)
11736#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
11737#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
11738#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
11739#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
11740#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
11742/******************* Bit definition for FMC_SR register *******************/
11743#define FMC_SR_IRS_Pos (0U)
11744#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
11745#define FMC_SR_IRS FMC_SR_IRS_Msk
11746#define FMC_SR_ILS_Pos (1U)
11747#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
11748#define FMC_SR_ILS FMC_SR_ILS_Msk
11749#define FMC_SR_IFS_Pos (2U)
11750#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
11751#define FMC_SR_IFS FMC_SR_IFS_Msk
11752#define FMC_SR_IREN_Pos (3U)
11753#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
11754#define FMC_SR_IREN FMC_SR_IREN_Msk
11755#define FMC_SR_ILEN_Pos (4U)
11756#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
11757#define FMC_SR_ILEN FMC_SR_ILEN_Msk
11758#define FMC_SR_IFEN_Pos (5U)
11759#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
11760#define FMC_SR_IFEN FMC_SR_IFEN_Msk
11761#define FMC_SR_FEMPT_Pos (6U)
11762#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
11763#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
11765/****************** Bit definition for FMC_PMEM register ******************/
11766#define FMC_PMEM_MEMSET_Pos (0U)
11767#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos)
11768#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk
11769#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos)
11770#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos)
11771#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos)
11772#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos)
11773#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos)
11774#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos)
11775#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos)
11776#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos)
11778#define FMC_PMEM_MEMWAIT_Pos (8U)
11779#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos)
11780#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk
11781#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos)
11782#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos)
11783#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos)
11784#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos)
11785#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos)
11786#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos)
11787#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos)
11788#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos)
11790#define FMC_PMEM_MEMHOLD_Pos (16U)
11791#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos)
11792#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk
11793#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos)
11794#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos)
11795#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos)
11796#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos)
11797#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos)
11798#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos)
11799#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos)
11800#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos)
11802#define FMC_PMEM_MEMHIZ_Pos (24U)
11803#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos)
11804#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk
11805#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos)
11806#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos)
11807#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos)
11808#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos)
11809#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos)
11810#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos)
11811#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos)
11812#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos)
11814/****************** Bit definition for FMC_PATT register ******************/
11815#define FMC_PATT_ATTSET_Pos (0U)
11816#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos)
11817#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk
11818#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos)
11819#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos)
11820#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos)
11821#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos)
11822#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos)
11823#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos)
11824#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos)
11825#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos)
11827#define FMC_PATT_ATTWAIT_Pos (8U)
11828#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos)
11829#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk
11830#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos)
11831#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos)
11832#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos)
11833#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos)
11834#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos)
11835#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos)
11836#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos)
11837#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos)
11839#define FMC_PATT_ATTHOLD_Pos (16U)
11840#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos)
11841#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk
11842#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos)
11843#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos)
11844#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos)
11845#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos)
11846#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos)
11847#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos)
11848#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos)
11849#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos)
11851#define FMC_PATT_ATTHIZ_Pos (24U)
11852#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos)
11853#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk
11854#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos)
11855#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos)
11856#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos)
11857#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos)
11858#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos)
11859#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos)
11860#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos)
11861#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos)
11863/****************** Bit definition for FMC_ECCR3 register ******************/
11864#define FMC_ECCR3_ECC3_Pos (0U)
11865#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)
11866#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk
11868/****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
11869#define FMC_SDCRx_NC_Pos (0U)
11870#define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos)
11871#define FMC_SDCRx_NC FMC_SDCRx_NC_Msk
11872#define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos)
11873#define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos)
11875#define FMC_SDCRx_NR_Pos (2U)
11876#define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos)
11877#define FMC_SDCRx_NR FMC_SDCRx_NR_Msk
11878#define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos)
11879#define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos)
11881#define FMC_SDCRx_MWID_Pos (4U)
11882#define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos)
11883#define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk
11884#define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos)
11885#define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos)
11887#define FMC_SDCRx_NB_Pos (6U)
11888#define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos)
11889#define FMC_SDCRx_NB FMC_SDCRx_NB_Msk
11891#define FMC_SDCRx_CAS_Pos (7U)
11892#define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos)
11893#define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk
11894#define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos)
11895#define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos)
11897#define FMC_SDCRx_WP_Pos (9U)
11898#define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos)
11899#define FMC_SDCRx_WP FMC_SDCRx_WP_Msk
11901#define FMC_SDCRx_SDCLK_Pos (10U)
11902#define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos)
11903#define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk
11904#define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos)
11905#define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos)
11907#define FMC_SDCRx_RBURST_Pos (12U)
11908#define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos)
11909#define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk
11911#define FMC_SDCRx_RPIPE_Pos (13U)
11912#define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos)
11913#define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk
11914#define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos)
11915#define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos)
11917/****************** Bit definition for FMC_SDTRx(1,2) register ******************/
11918#define FMC_SDTRx_TMRD_Pos (0U)
11919#define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos)
11920#define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk
11921#define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos)
11922#define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos)
11923#define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos)
11924#define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos)
11926#define FMC_SDTRx_TXSR_Pos (4U)
11927#define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos)
11928#define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk
11929#define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos)
11930#define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos)
11931#define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos)
11932#define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos)
11934#define FMC_SDTRx_TRAS_Pos (8U)
11935#define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos)
11936#define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk
11937#define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos)
11938#define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos)
11939#define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos)
11940#define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos)
11942#define FMC_SDTRx_TRC_Pos (12U)
11943#define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos)
11944#define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk
11945#define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos)
11946#define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos)
11947#define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos)
11949#define FMC_SDTRx_TWR_Pos (16U)
11950#define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos)
11951#define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk
11952#define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos)
11953#define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos)
11954#define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos)
11956#define FMC_SDTRx_TRP_Pos (20U)
11957#define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos)
11958#define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk
11959#define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos)
11960#define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos)
11961#define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos)
11963#define FMC_SDTRx_TRCD_Pos (24U)
11964#define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos)
11965#define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk
11966#define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos)
11967#define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos)
11968#define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos)
11970/****************** Bit definition for FMC_SDCMR register ******************/
11971#define FMC_SDCMR_MODE_Pos (0U)
11972#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
11973#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
11974#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
11975#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
11976#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos)
11978#define FMC_SDCMR_CTB2_Pos (3U)
11979#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
11980#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
11982#define FMC_SDCMR_CTB1_Pos (4U)
11983#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
11984#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
11986#define FMC_SDCMR_NRFS_Pos (5U)
11987#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
11988#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
11989#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
11990#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
11991#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
11992#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
11994#define FMC_SDCMR_MRD_Pos (9U)
11995#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
11996#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
11998/****************** Bit definition for FMC_SDRTR register ******************/
11999#define FMC_SDRTR_CRE_Pos (0U)
12000#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
12001#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
12003#define FMC_SDRTR_COUNT_Pos (1U)
12004#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
12005#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
12007#define FMC_SDRTR_REIE_Pos (14U)
12008#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
12009#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
12011/****************** Bit definition for FMC_SDSR register ******************/
12012#define FMC_SDSR_RE_Pos (0U)
12013#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
12014#define FMC_SDSR_RE FMC_SDSR_RE_Msk
12016#define FMC_SDSR_MODES1_Pos (1U)
12017#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
12018#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
12019#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
12020#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
12022#define FMC_SDSR_MODES2_Pos (3U)
12023#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
12024#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
12025#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
12026#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
12028/******************************************************************************/
12029/* */
12030/* General Purpose I/O */
12031/* */
12032/******************************************************************************/
12033/****************** Bits definition for GPIO_MODER register *****************/
12034#define GPIO_MODER_MODE0_Pos (0U)
12035#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
12036#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
12037#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
12038#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
12040#define GPIO_MODER_MODE1_Pos (2U)
12041#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)
12042#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
12043#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)
12044#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)
12046#define GPIO_MODER_MODE2_Pos (4U)
12047#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)
12048#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
12049#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)
12050#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)
12052#define GPIO_MODER_MODE3_Pos (6U)
12053#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)
12054#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
12055#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)
12056#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)
12058#define GPIO_MODER_MODE4_Pos (8U)
12059#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)
12060#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
12061#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)
12062#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)
12064#define GPIO_MODER_MODE5_Pos (10U)
12065#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)
12066#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
12067#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)
12068#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)
12070#define GPIO_MODER_MODE6_Pos (12U)
12071#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)
12072#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
12073#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)
12074#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)
12076#define GPIO_MODER_MODE7_Pos (14U)
12077#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)
12078#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
12079#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)
12080#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)
12082#define GPIO_MODER_MODE8_Pos (16U)
12083#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)
12084#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
12085#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)
12086#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)
12088#define GPIO_MODER_MODE9_Pos (18U)
12089#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)
12090#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
12091#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)
12092#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)
12094#define GPIO_MODER_MODE10_Pos (20U)
12095#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)
12096#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
12097#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)
12098#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)
12100#define GPIO_MODER_MODE11_Pos (22U)
12101#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)
12102#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
12103#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)
12104#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)
12106#define GPIO_MODER_MODE12_Pos (24U)
12107#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)
12108#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
12109#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)
12110#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)
12112#define GPIO_MODER_MODE13_Pos (26U)
12113#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)
12114#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
12115#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)
12116#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)
12118#define GPIO_MODER_MODE14_Pos (28U)
12119#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)
12120#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
12121#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)
12122#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)
12124#define GPIO_MODER_MODE15_Pos (30U)
12125#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)
12126#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
12127#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)
12128#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)
12130/****************** Bits definition for GPIO_OTYPER register ****************/
12131#define GPIO_OTYPER_OT0_Pos (0U)
12132#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
12133#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
12134#define GPIO_OTYPER_OT1_Pos (1U)
12135#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
12136#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
12137#define GPIO_OTYPER_OT2_Pos (2U)
12138#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
12139#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
12140#define GPIO_OTYPER_OT3_Pos (3U)
12141#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
12142#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
12143#define GPIO_OTYPER_OT4_Pos (4U)
12144#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
12145#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
12146#define GPIO_OTYPER_OT5_Pos (5U)
12147#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
12148#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
12149#define GPIO_OTYPER_OT6_Pos (6U)
12150#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
12151#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
12152#define GPIO_OTYPER_OT7_Pos (7U)
12153#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
12154#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
12155#define GPIO_OTYPER_OT8_Pos (8U)
12156#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
12157#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
12158#define GPIO_OTYPER_OT9_Pos (9U)
12159#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
12160#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
12161#define GPIO_OTYPER_OT10_Pos (10U)
12162#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
12163#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
12164#define GPIO_OTYPER_OT11_Pos (11U)
12165#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
12166#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
12167#define GPIO_OTYPER_OT12_Pos (12U)
12168#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
12169#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
12170#define GPIO_OTYPER_OT13_Pos (13U)
12171#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
12172#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
12173#define GPIO_OTYPER_OT14_Pos (14U)
12174#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
12175#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
12176#define GPIO_OTYPER_OT15_Pos (15U)
12177#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
12178#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
12179
12180/****************** Bits definition for GPIO_OSPEEDR register ***************/
12181#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
12182#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
12183#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
12184#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
12185#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
12187#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
12188#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
12189#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
12190#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
12191#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
12193#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
12194#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
12195#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
12196#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
12197#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
12199#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
12200#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
12201#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
12202#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
12203#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
12205#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
12206#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
12207#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
12208#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
12209#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
12211#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
12212#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
12213#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
12214#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
12215#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
12217#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
12218#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
12219#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
12220#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
12221#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
12223#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
12224#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
12225#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
12226#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
12227#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
12229#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
12230#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
12231#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
12232#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
12233#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
12235#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
12236#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
12237#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
12238#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
12239#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
12241#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
12242#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
12243#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
12244#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
12245#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
12247#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
12248#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
12249#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
12250#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
12251#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
12253#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
12254#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
12255#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
12256#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
12257#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
12259#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
12260#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
12261#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
12262#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
12263#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
12265#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
12266#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
12267#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
12268#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
12269#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
12271#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
12272#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
12273#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
12274#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
12275#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
12277/****************** Bits definition for GPIO_PUPDR register *****************/
12278#define GPIO_PUPDR_PUPD0_Pos (0U)
12279#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
12280#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
12281#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
12282#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
12284#define GPIO_PUPDR_PUPD1_Pos (2U)
12285#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
12286#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
12287#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
12288#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
12290#define GPIO_PUPDR_PUPD2_Pos (4U)
12291#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
12292#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
12293#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
12294#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
12296#define GPIO_PUPDR_PUPD3_Pos (6U)
12297#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
12298#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
12299#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
12300#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
12302#define GPIO_PUPDR_PUPD4_Pos (8U)
12303#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
12304#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
12305#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
12306#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
12308#define GPIO_PUPDR_PUPD5_Pos (10U)
12309#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
12310#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
12311#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
12312#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
12314#define GPIO_PUPDR_PUPD6_Pos (12U)
12315#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
12316#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
12317#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
12318#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
12320#define GPIO_PUPDR_PUPD7_Pos (14U)
12321#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
12322#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
12323#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
12324#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
12326#define GPIO_PUPDR_PUPD8_Pos (16U)
12327#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
12328#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
12329#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
12330#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
12332#define GPIO_PUPDR_PUPD9_Pos (18U)
12333#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
12334#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
12335#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
12336#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
12338#define GPIO_PUPDR_PUPD10_Pos (20U)
12339#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
12340#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
12341#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
12342#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
12344#define GPIO_PUPDR_PUPD11_Pos (22U)
12345#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
12346#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
12347#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
12348#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
12350#define GPIO_PUPDR_PUPD12_Pos (24U)
12351#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
12352#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
12353#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
12354#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
12356#define GPIO_PUPDR_PUPD13_Pos (26U)
12357#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
12358#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
12359#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
12360#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
12362#define GPIO_PUPDR_PUPD14_Pos (28U)
12363#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
12364#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
12365#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
12366#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
12368#define GPIO_PUPDR_PUPD15_Pos (30U)
12369#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
12370#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
12371#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
12372#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
12374/****************** Bits definition for GPIO_IDR register *******************/
12375#define GPIO_IDR_ID0_Pos (0U)
12376#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
12377#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
12378#define GPIO_IDR_ID1_Pos (1U)
12379#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
12380#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
12381#define GPIO_IDR_ID2_Pos (2U)
12382#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
12383#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
12384#define GPIO_IDR_ID3_Pos (3U)
12385#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
12386#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
12387#define GPIO_IDR_ID4_Pos (4U)
12388#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
12389#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
12390#define GPIO_IDR_ID5_Pos (5U)
12391#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
12392#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
12393#define GPIO_IDR_ID6_Pos (6U)
12394#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
12395#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
12396#define GPIO_IDR_ID7_Pos (7U)
12397#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
12398#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
12399#define GPIO_IDR_ID8_Pos (8U)
12400#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
12401#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
12402#define GPIO_IDR_ID9_Pos (9U)
12403#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
12404#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
12405#define GPIO_IDR_ID10_Pos (10U)
12406#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
12407#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
12408#define GPIO_IDR_ID11_Pos (11U)
12409#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
12410#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
12411#define GPIO_IDR_ID12_Pos (12U)
12412#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
12413#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
12414#define GPIO_IDR_ID13_Pos (13U)
12415#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
12416#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
12417#define GPIO_IDR_ID14_Pos (14U)
12418#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
12419#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
12420#define GPIO_IDR_ID15_Pos (15U)
12421#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
12422#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
12423
12424/****************** Bits definition for GPIO_ODR register *******************/
12425#define GPIO_ODR_OD0_Pos (0U)
12426#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
12427#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
12428#define GPIO_ODR_OD1_Pos (1U)
12429#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
12430#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
12431#define GPIO_ODR_OD2_Pos (2U)
12432#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
12433#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
12434#define GPIO_ODR_OD3_Pos (3U)
12435#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
12436#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
12437#define GPIO_ODR_OD4_Pos (4U)
12438#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
12439#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
12440#define GPIO_ODR_OD5_Pos (5U)
12441#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
12442#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
12443#define GPIO_ODR_OD6_Pos (6U)
12444#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
12445#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
12446#define GPIO_ODR_OD7_Pos (7U)
12447#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
12448#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
12449#define GPIO_ODR_OD8_Pos (8U)
12450#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
12451#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
12452#define GPIO_ODR_OD9_Pos (9U)
12453#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
12454#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
12455#define GPIO_ODR_OD10_Pos (10U)
12456#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
12457#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
12458#define GPIO_ODR_OD11_Pos (11U)
12459#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
12460#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
12461#define GPIO_ODR_OD12_Pos (12U)
12462#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
12463#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
12464#define GPIO_ODR_OD13_Pos (13U)
12465#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
12466#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
12467#define GPIO_ODR_OD14_Pos (14U)
12468#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
12469#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
12470#define GPIO_ODR_OD15_Pos (15U)
12471#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
12472#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
12473
12474/****************** Bits definition for GPIO_BSRR register ******************/
12475#define GPIO_BSRR_BS0_Pos (0U)
12476#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
12477#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
12478#define GPIO_BSRR_BS1_Pos (1U)
12479#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
12480#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
12481#define GPIO_BSRR_BS2_Pos (2U)
12482#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
12483#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
12484#define GPIO_BSRR_BS3_Pos (3U)
12485#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
12486#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
12487#define GPIO_BSRR_BS4_Pos (4U)
12488#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
12489#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
12490#define GPIO_BSRR_BS5_Pos (5U)
12491#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
12492#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
12493#define GPIO_BSRR_BS6_Pos (6U)
12494#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
12495#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
12496#define GPIO_BSRR_BS7_Pos (7U)
12497#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
12498#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
12499#define GPIO_BSRR_BS8_Pos (8U)
12500#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
12501#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
12502#define GPIO_BSRR_BS9_Pos (9U)
12503#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
12504#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
12505#define GPIO_BSRR_BS10_Pos (10U)
12506#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
12507#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
12508#define GPIO_BSRR_BS11_Pos (11U)
12509#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
12510#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
12511#define GPIO_BSRR_BS12_Pos (12U)
12512#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
12513#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
12514#define GPIO_BSRR_BS13_Pos (13U)
12515#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
12516#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
12517#define GPIO_BSRR_BS14_Pos (14U)
12518#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
12519#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
12520#define GPIO_BSRR_BS15_Pos (15U)
12521#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
12522#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
12523#define GPIO_BSRR_BR0_Pos (16U)
12524#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
12525#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
12526#define GPIO_BSRR_BR1_Pos (17U)
12527#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
12528#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
12529#define GPIO_BSRR_BR2_Pos (18U)
12530#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
12531#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
12532#define GPIO_BSRR_BR3_Pos (19U)
12533#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
12534#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
12535#define GPIO_BSRR_BR4_Pos (20U)
12536#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
12537#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
12538#define GPIO_BSRR_BR5_Pos (21U)
12539#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
12540#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
12541#define GPIO_BSRR_BR6_Pos (22U)
12542#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
12543#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
12544#define GPIO_BSRR_BR7_Pos (23U)
12545#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
12546#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
12547#define GPIO_BSRR_BR8_Pos (24U)
12548#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
12549#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
12550#define GPIO_BSRR_BR9_Pos (25U)
12551#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
12552#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
12553#define GPIO_BSRR_BR10_Pos (26U)
12554#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
12555#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
12556#define GPIO_BSRR_BR11_Pos (27U)
12557#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
12558#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
12559#define GPIO_BSRR_BR12_Pos (28U)
12560#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
12561#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
12562#define GPIO_BSRR_BR13_Pos (29U)
12563#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
12564#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
12565#define GPIO_BSRR_BR14_Pos (30U)
12566#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
12567#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
12568#define GPIO_BSRR_BR15_Pos (31U)
12569#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
12570#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
12571
12572/****************** Bit definition for GPIO_LCKR register *********************/
12573#define GPIO_LCKR_LCK0_Pos (0U)
12574#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
12575#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
12576#define GPIO_LCKR_LCK1_Pos (1U)
12577#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
12578#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
12579#define GPIO_LCKR_LCK2_Pos (2U)
12580#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
12581#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
12582#define GPIO_LCKR_LCK3_Pos (3U)
12583#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
12584#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
12585#define GPIO_LCKR_LCK4_Pos (4U)
12586#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
12587#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
12588#define GPIO_LCKR_LCK5_Pos (5U)
12589#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
12590#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
12591#define GPIO_LCKR_LCK6_Pos (6U)
12592#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
12593#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
12594#define GPIO_LCKR_LCK7_Pos (7U)
12595#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
12596#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
12597#define GPIO_LCKR_LCK8_Pos (8U)
12598#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
12599#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
12600#define GPIO_LCKR_LCK9_Pos (9U)
12601#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
12602#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
12603#define GPIO_LCKR_LCK10_Pos (10U)
12604#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
12605#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
12606#define GPIO_LCKR_LCK11_Pos (11U)
12607#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
12608#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
12609#define GPIO_LCKR_LCK12_Pos (12U)
12610#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
12611#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
12612#define GPIO_LCKR_LCK13_Pos (13U)
12613#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
12614#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
12615#define GPIO_LCKR_LCK14_Pos (14U)
12616#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
12617#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
12618#define GPIO_LCKR_LCK15_Pos (15U)
12619#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
12620#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
12621#define GPIO_LCKR_LCKK_Pos (16U)
12622#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
12623#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
12624
12625/****************** Bit definition for GPIO_AFRL register ********************/
12626#define GPIO_AFRL_AFSEL0_Pos (0U)
12627#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
12628#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
12629#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
12630#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
12631#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
12632#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
12633#define GPIO_AFRL_AFSEL1_Pos (4U)
12634#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
12635#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
12636#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
12637#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
12638#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
12639#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
12640#define GPIO_AFRL_AFSEL2_Pos (8U)
12641#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
12642#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
12643#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
12644#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
12645#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
12646#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
12647#define GPIO_AFRL_AFSEL3_Pos (12U)
12648#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
12649#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
12650#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
12651#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
12652#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
12653#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
12654#define GPIO_AFRL_AFSEL4_Pos (16U)
12655#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
12656#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
12657#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
12658#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
12659#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
12660#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
12661#define GPIO_AFRL_AFSEL5_Pos (20U)
12662#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
12663#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
12664#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
12665#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
12666#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
12667#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
12668#define GPIO_AFRL_AFSEL6_Pos (24U)
12669#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
12670#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
12671#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
12672#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
12673#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
12674#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
12675#define GPIO_AFRL_AFSEL7_Pos (28U)
12676#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
12677#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
12678#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
12679#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
12680#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
12681#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
12683/* Legacy defines */
12684#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
12685#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
12686#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
12687#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
12688#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
12689#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
12690#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
12691#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
12692
12693/****************** Bit definition for GPIO_AFRH register ********************/
12694#define GPIO_AFRH_AFSEL8_Pos (0U)
12695#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
12696#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
12697#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
12698#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
12699#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
12700#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
12701#define GPIO_AFRH_AFSEL9_Pos (4U)
12702#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
12703#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
12704#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
12705#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
12706#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
12707#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
12708#define GPIO_AFRH_AFSEL10_Pos (8U)
12709#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
12710#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
12711#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
12712#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
12713#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
12714#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
12715#define GPIO_AFRH_AFSEL11_Pos (12U)
12716#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
12717#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
12718#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
12719#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
12720#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
12721#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
12722#define GPIO_AFRH_AFSEL12_Pos (16U)
12723#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
12724#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
12725#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
12726#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
12727#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
12728#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
12729#define GPIO_AFRH_AFSEL13_Pos (20U)
12730#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
12731#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
12732#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
12733#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
12734#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
12735#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
12736#define GPIO_AFRH_AFSEL14_Pos (24U)
12737#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
12738#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
12739#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
12740#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
12741#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
12742#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
12743#define GPIO_AFRH_AFSEL15_Pos (28U)
12744#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
12745#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
12746#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
12747#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
12748#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
12749#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
12751/* Legacy defines */
12752#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
12753#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
12754#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
12755#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
12756#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
12757#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
12758#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
12759#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
12760
12761/******************************************************************************/
12762/* */
12763/* HSEM HW Semaphore */
12764/* */
12765/******************************************************************************/
12766/******************** Bit definition for HSEM_R register ********************/
12767#define HSEM_R_PROCID_Pos (0U)
12768#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos)
12769#define HSEM_R_PROCID HSEM_R_PROCID_Msk
12770#define HSEM_R_COREID_Pos (8U)
12771#define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos)
12772#define HSEM_R_COREID HSEM_R_COREID_Msk
12773#define HSEM_R_LOCK_Pos (31U)
12774#define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos)
12775#define HSEM_R_LOCK HSEM_R_LOCK_Msk
12777/******************** Bit definition for HSEM_RLR register ******************/
12778#define HSEM_RLR_PROCID_Pos (0U)
12779#define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos)
12780#define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk
12781#define HSEM_RLR_COREID_Pos (8U)
12782#define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos)
12783#define HSEM_RLR_COREID HSEM_RLR_COREID_Msk
12784#define HSEM_RLR_LOCK_Pos (31U)
12785#define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos)
12786#define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk
12788/******************** Bit definition for HSEM_C1IER register *****************/
12789#define HSEM_C1IER_ISE0_Pos (0U)
12790#define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos)
12791#define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk
12792#define HSEM_C1IER_ISE1_Pos (1U)
12793#define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos)
12794#define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk
12795#define HSEM_C1IER_ISE2_Pos (2U)
12796#define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos)
12797#define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk
12798#define HSEM_C1IER_ISE3_Pos (3U)
12799#define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos)
12800#define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk
12801#define HSEM_C1IER_ISE4_Pos (4U)
12802#define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos)
12803#define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk
12804#define HSEM_C1IER_ISE5_Pos (5U)
12805#define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos)
12806#define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk
12807#define HSEM_C1IER_ISE6_Pos (6U)
12808#define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos)
12809#define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk
12810#define HSEM_C1IER_ISE7_Pos (7U)
12811#define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos)
12812#define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk
12813#define HSEM_C1IER_ISE8_Pos (8U)
12814#define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos)
12815#define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk
12816#define HSEM_C1IER_ISE9_Pos (9U)
12817#define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos)
12818#define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk
12819#define HSEM_C1IER_ISE10_Pos (10U)
12820#define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos)
12821#define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk
12822#define HSEM_C1IER_ISE11_Pos (11U)
12823#define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos)
12824#define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk
12825#define HSEM_C1IER_ISE12_Pos (12U)
12826#define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos)
12827#define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk
12828#define HSEM_C1IER_ISE13_Pos (13U)
12829#define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos)
12830#define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk
12831#define HSEM_C1IER_ISE14_Pos (14U)
12832#define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos)
12833#define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk
12834#define HSEM_C1IER_ISE15_Pos (15U)
12835#define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos)
12836#define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk
12837#define HSEM_C1IER_ISE16_Pos (16U)
12838#define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos)
12839#define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk
12840#define HSEM_C1IER_ISE17_Pos (17U)
12841#define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos)
12842#define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk
12843#define HSEM_C1IER_ISE18_Pos (18U)
12844#define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos)
12845#define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk
12846#define HSEM_C1IER_ISE19_Pos (19U)
12847#define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos)
12848#define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk
12849#define HSEM_C1IER_ISE20_Pos (20U)
12850#define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos)
12851#define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk
12852#define HSEM_C1IER_ISE21_Pos (21U)
12853#define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos)
12854#define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk
12855#define HSEM_C1IER_ISE22_Pos (22U)
12856#define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos)
12857#define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk
12858#define HSEM_C1IER_ISE23_Pos (23U)
12859#define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos)
12860#define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk
12861#define HSEM_C1IER_ISE24_Pos (24U)
12862#define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos)
12863#define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk
12864#define HSEM_C1IER_ISE25_Pos (25U)
12865#define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos)
12866#define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk
12867#define HSEM_C1IER_ISE26_Pos (26U)
12868#define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos)
12869#define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk
12870#define HSEM_C1IER_ISE27_Pos (27U)
12871#define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos)
12872#define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk
12873#define HSEM_C1IER_ISE28_Pos (28U)
12874#define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos)
12875#define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk
12876#define HSEM_C1IER_ISE29_Pos (29U)
12877#define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos)
12878#define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk
12879#define HSEM_C1IER_ISE30_Pos (30U)
12880#define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos)
12881#define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk
12882#define HSEM_C1IER_ISE31_Pos (31U)
12883#define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos)
12884#define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk
12886/******************** Bit definition for HSEM_C1ICR register *****************/
12887#define HSEM_C1ICR_ISC0_Pos (0U)
12888#define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos)
12889#define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk
12890#define HSEM_C1ICR_ISC1_Pos (1U)
12891#define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos)
12892#define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk
12893#define HSEM_C1ICR_ISC2_Pos (2U)
12894#define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos)
12895#define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk
12896#define HSEM_C1ICR_ISC3_Pos (3U)
12897#define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos)
12898#define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk
12899#define HSEM_C1ICR_ISC4_Pos (4U)
12900#define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos)
12901#define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk
12902#define HSEM_C1ICR_ISC5_Pos (5U)
12903#define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos)
12904#define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk
12905#define HSEM_C1ICR_ISC6_Pos (6U)
12906#define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos)
12907#define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk
12908#define HSEM_C1ICR_ISC7_Pos (7U)
12909#define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos)
12910#define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk
12911#define HSEM_C1ICR_ISC8_Pos (8U)
12912#define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos)
12913#define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk
12914#define HSEM_C1ICR_ISC9_Pos (9U)
12915#define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos)
12916#define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk
12917#define HSEM_C1ICR_ISC10_Pos (10U)
12918#define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos)
12919#define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk
12920#define HSEM_C1ICR_ISC11_Pos (11U)
12921#define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos)
12922#define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk
12923#define HSEM_C1ICR_ISC12_Pos (12U)
12924#define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos)
12925#define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk
12926#define HSEM_C1ICR_ISC13_Pos (13U)
12927#define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos)
12928#define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk
12929#define HSEM_C1ICR_ISC14_Pos (14U)
12930#define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos)
12931#define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk
12932#define HSEM_C1ICR_ISC15_Pos (15U)
12933#define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos)
12934#define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk
12935#define HSEM_C1ICR_ISC16_Pos (16U)
12936#define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos)
12937#define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk
12938#define HSEM_C1ICR_ISC17_Pos (17U)
12939#define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos)
12940#define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk
12941#define HSEM_C1ICR_ISC18_Pos (18U)
12942#define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos)
12943#define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk
12944#define HSEM_C1ICR_ISC19_Pos (19U)
12945#define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos)
12946#define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk
12947#define HSEM_C1ICR_ISC20_Pos (20U)
12948#define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos)
12949#define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk
12950#define HSEM_C1ICR_ISC21_Pos (21U)
12951#define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos)
12952#define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk
12953#define HSEM_C1ICR_ISC22_Pos (22U)
12954#define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos)
12955#define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk
12956#define HSEM_C1ICR_ISC23_Pos (23U)
12957#define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos)
12958#define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk
12959#define HSEM_C1ICR_ISC24_Pos (24U)
12960#define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos)
12961#define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk
12962#define HSEM_C1ICR_ISC25_Pos (25U)
12963#define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos)
12964#define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk
12965#define HSEM_C1ICR_ISC26_Pos (26U)
12966#define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos)
12967#define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk
12968#define HSEM_C1ICR_ISC27_Pos (27U)
12969#define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos)
12970#define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk
12971#define HSEM_C1ICR_ISC28_Pos (28U)
12972#define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos)
12973#define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk
12974#define HSEM_C1ICR_ISC29_Pos (29U)
12975#define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos)
12976#define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk
12977#define HSEM_C1ICR_ISC30_Pos (30U)
12978#define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos)
12979#define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk
12980#define HSEM_C1ICR_ISC31_Pos (31U)
12981#define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos)
12982#define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk
12984/******************** Bit definition for HSEM_C1ISR register *****************/
12985#define HSEM_C1ISR_ISF0_Pos (0U)
12986#define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos)
12987#define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk
12988#define HSEM_C1ISR_ISF1_Pos (1U)
12989#define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos)
12990#define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk
12991#define HSEM_C1ISR_ISF2_Pos (2U)
12992#define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos)
12993#define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk
12994#define HSEM_C1ISR_ISF3_Pos (3U)
12995#define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos)
12996#define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk
12997#define HSEM_C1ISR_ISF4_Pos (4U)
12998#define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos)
12999#define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk
13000#define HSEM_C1ISR_ISF5_Pos (5U)
13001#define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos)
13002#define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk
13003#define HSEM_C1ISR_ISF6_Pos (6U)
13004#define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos)
13005#define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk
13006#define HSEM_C1ISR_ISF7_Pos (7U)
13007#define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos)
13008#define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk
13009#define HSEM_C1ISR_ISF8_Pos (8U)
13010#define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos)
13011#define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk
13012#define HSEM_C1ISR_ISF9_Pos (9U)
13013#define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos)
13014#define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk
13015#define HSEM_C1ISR_ISF10_Pos (10U)
13016#define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos)
13017#define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk
13018#define HSEM_C1ISR_ISF11_Pos (11U)
13019#define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos)
13020#define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk
13021#define HSEM_C1ISR_ISF12_Pos (12U)
13022#define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos)
13023#define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk
13024#define HSEM_C1ISR_ISF13_Pos (13U)
13025#define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos)
13026#define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk
13027#define HSEM_C1ISR_ISF14_Pos (14U)
13028#define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos)
13029#define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk
13030#define HSEM_C1ISR_ISF15_Pos (15U)
13031#define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos)
13032#define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk
13033#define HSEM_C1ISR_ISF16_Pos (16U)
13034#define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos)
13035#define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk
13036#define HSEM_C1ISR_ISF17_Pos (17U)
13037#define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos)
13038#define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk
13039#define HSEM_C1ISR_ISF18_Pos (18U)
13040#define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos)
13041#define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk
13042#define HSEM_C1ISR_ISF19_Pos (19U)
13043#define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos)
13044#define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk
13045#define HSEM_C1ISR_ISF20_Pos (20U)
13046#define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos)
13047#define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk
13048#define HSEM_C1ISR_ISF21_Pos (21U)
13049#define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos)
13050#define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk
13051#define HSEM_C1ISR_ISF22_Pos (22U)
13052#define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos)
13053#define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk
13054#define HSEM_C1ISR_ISF23_Pos (23U)
13055#define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos)
13056#define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk
13057#define HSEM_C1ISR_ISF24_Pos (24U)
13058#define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos)
13059#define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk
13060#define HSEM_C1ISR_ISF25_Pos (25U)
13061#define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos)
13062#define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk
13063#define HSEM_C1ISR_ISF26_Pos (26U)
13064#define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos)
13065#define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk
13066#define HSEM_C1ISR_ISF27_Pos (27U)
13067#define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos)
13068#define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk
13069#define HSEM_C1ISR_ISF28_Pos (28U)
13070#define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos)
13071#define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk
13072#define HSEM_C1ISR_ISF29_Pos (29U)
13073#define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos)
13074#define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk
13075#define HSEM_C1ISR_ISF30_Pos (30U)
13076#define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos)
13077#define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk
13078#define HSEM_C1ISR_ISF31_Pos (31U)
13079#define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos)
13080#define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk
13082/******************** Bit definition for HSEM_C1MISR register *****************/
13083#define HSEM_C1MISR_MISF0_Pos (0U)
13084#define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos)
13085#define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk
13086#define HSEM_C1MISR_MISF1_Pos (1U)
13087#define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos)
13088#define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk
13089#define HSEM_C1MISR_MISF2_Pos (2U)
13090#define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos)
13091#define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk
13092#define HSEM_C1MISR_MISF3_Pos (3U)
13093#define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos)
13094#define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk
13095#define HSEM_C1MISR_MISF4_Pos (4U)
13096#define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos)
13097#define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk
13098#define HSEM_C1MISR_MISF5_Pos (5U)
13099#define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos)
13100#define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk
13101#define HSEM_C1MISR_MISF6_Pos (6U)
13102#define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos)
13103#define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk
13104#define HSEM_C1MISR_MISF7_Pos (7U)
13105#define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos)
13106#define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk
13107#define HSEM_C1MISR_MISF8_Pos (8U)
13108#define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos)
13109#define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk
13110#define HSEM_C1MISR_MISF9_Pos (9U)
13111#define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos)
13112#define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk
13113#define HSEM_C1MISR_MISF10_Pos (10U)
13114#define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos)
13115#define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk
13116#define HSEM_C1MISR_MISF11_Pos (11U)
13117#define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos)
13118#define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk
13119#define HSEM_C1MISR_MISF12_Pos (12U)
13120#define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos)
13121#define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk
13122#define HSEM_C1MISR_MISF13_Pos (13U)
13123#define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos)
13124#define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk
13125#define HSEM_C1MISR_MISF14_Pos (14U)
13126#define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos)
13127#define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk
13128#define HSEM_C1MISR_MISF15_Pos (15U)
13129#define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos)
13130#define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk
13131#define HSEM_C1MISR_MISF16_Pos (16U)
13132#define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos)
13133#define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk
13134#define HSEM_C1MISR_MISF17_Pos (17U)
13135#define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos)
13136#define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk
13137#define HSEM_C1MISR_MISF18_Pos (18U)
13138#define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos)
13139#define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk
13140#define HSEM_C1MISR_MISF19_Pos (19U)
13141#define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos)
13142#define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk
13143#define HSEM_C1MISR_MISF20_Pos (20U)
13144#define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos)
13145#define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk
13146#define HSEM_C1MISR_MISF21_Pos (21U)
13147#define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos)
13148#define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk
13149#define HSEM_C1MISR_MISF22_Pos (22U)
13150#define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos)
13151#define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk
13152#define HSEM_C1MISR_MISF23_Pos (23U)
13153#define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos)
13154#define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk
13155#define HSEM_C1MISR_MISF24_Pos (24U)
13156#define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos)
13157#define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk
13158#define HSEM_C1MISR_MISF25_Pos (25U)
13159#define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos)
13160#define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk
13161#define HSEM_C1MISR_MISF26_Pos (26U)
13162#define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos)
13163#define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk
13164#define HSEM_C1MISR_MISF27_Pos (27U)
13165#define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos)
13166#define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk
13167#define HSEM_C1MISR_MISF28_Pos (28U)
13168#define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos)
13169#define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk
13170#define HSEM_C1MISR_MISF29_Pos (29U)
13171#define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos)
13172#define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk
13173#define HSEM_C1MISR_MISF30_Pos (30U)
13174#define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos)
13175#define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk
13176#define HSEM_C1MISR_MISF31_Pos (31U)
13177#define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos)
13178#define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk
13180/******************** Bit definition for HSEM_CR register *****************/
13181#define HSEM_CR_COREID_Pos (8U)
13182#define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos)
13183#define HSEM_CR_COREID HSEM_CR_COREID_Msk
13184#define HSEM_CR_KEY_Pos (16U)
13185#define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos)
13186#define HSEM_CR_KEY HSEM_CR_KEY_Msk
13188/******************** Bit definition for HSEM_KEYR register *****************/
13189#define HSEM_KEYR_KEY_Pos (16U)
13190#define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos)
13191#define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk
13193/******************************************************************************/
13194/* */
13195/* HASH */
13196/* */
13197/******************************************************************************/
13198/****************** Bits definition for HASH_CR register ********************/
13199#define HASH_CR_INIT_Pos (2U)
13200#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos)
13201#define HASH_CR_INIT HASH_CR_INIT_Msk
13202#define HASH_CR_DMAE_Pos (3U)
13203#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos)
13204#define HASH_CR_DMAE HASH_CR_DMAE_Msk
13205#define HASH_CR_DATATYPE_Pos (4U)
13206#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos)
13207#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
13208#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos)
13209#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos)
13210#define HASH_CR_MODE_Pos (6U)
13211#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos)
13212#define HASH_CR_MODE HASH_CR_MODE_Msk
13213#define HASH_CR_ALGO_Pos (7U)
13214#define HASH_CR_ALGO_Msk (0x801UL << HASH_CR_ALGO_Pos)
13215#define HASH_CR_ALGO HASH_CR_ALGO_Msk
13216#define HASH_CR_ALGO_0 (0x001UL << HASH_CR_ALGO_Pos)
13217#define HASH_CR_ALGO_1 (0x800UL << HASH_CR_ALGO_Pos)
13218#define HASH_CR_NBW_Pos (8U)
13219#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos)
13220#define HASH_CR_NBW HASH_CR_NBW_Msk
13221#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos)
13222#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos)
13223#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos)
13224#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos)
13225#define HASH_CR_DINNE_Pos (12U)
13226#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos)
13227#define HASH_CR_DINNE HASH_CR_DINNE_Msk
13228#define HASH_CR_MDMAT_Pos (13U)
13229#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos)
13230#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
13231#define HASH_CR_LKEY_Pos (16U)
13232#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos)
13233#define HASH_CR_LKEY HASH_CR_LKEY_Msk
13234
13235/****************** Bits definition for HASH_STR register *******************/
13236#define HASH_STR_NBLW_Pos (0U)
13237#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos)
13238#define HASH_STR_NBLW HASH_STR_NBLW_Msk
13239#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos)
13240#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos)
13241#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos)
13242#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos)
13243#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos)
13244#define HASH_STR_DCAL_Pos (8U)
13245#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos)
13246#define HASH_STR_DCAL HASH_STR_DCAL_Msk
13247
13248/****************** Bits definition for HASH_IMR register *******************/
13249#define HASH_IMR_DINIE_Pos (0U)
13250#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos)
13251#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
13252#define HASH_IMR_DCIE_Pos (1U)
13253#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos)
13254#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
13255
13256/****************** Bits definition for HASH_SR register ********************/
13257#define HASH_SR_DINIS_Pos (0U)
13258#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos)
13259#define HASH_SR_DINIS HASH_SR_DINIS_Msk
13260#define HASH_SR_DCIS_Pos (1U)
13261#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos)
13262#define HASH_SR_DCIS HASH_SR_DCIS_Msk
13263#define HASH_SR_DMAS_Pos (2U)
13264#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos)
13265#define HASH_SR_DMAS HASH_SR_DMAS_Msk
13266#define HASH_SR_BUSY_Pos (3U)
13267#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos)
13268#define HASH_SR_BUSY HASH_SR_BUSY_Msk
13269/******************************************************************************/
13270/* */
13271/* Inter-integrated Circuit Interface (I2C) */
13272/* */
13273/******************************************************************************/
13274/******************* Bit definition for I2C_CR1 register *******************/
13275#define I2C_CR1_PE_Pos (0U)
13276#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
13277#define I2C_CR1_PE I2C_CR1_PE_Msk
13278#define I2C_CR1_TXIE_Pos (1U)
13279#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
13280#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
13281#define I2C_CR1_RXIE_Pos (2U)
13282#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
13283#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
13284#define I2C_CR1_ADDRIE_Pos (3U)
13285#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
13286#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
13287#define I2C_CR1_NACKIE_Pos (4U)
13288#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
13289#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
13290#define I2C_CR1_STOPIE_Pos (5U)
13291#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
13292#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
13293#define I2C_CR1_TCIE_Pos (6U)
13294#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
13295#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
13296#define I2C_CR1_ERRIE_Pos (7U)
13297#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
13298#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
13299#define I2C_CR1_DNF_Pos (8U)
13300#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
13301#define I2C_CR1_DNF I2C_CR1_DNF_Msk
13302#define I2C_CR1_ANFOFF_Pos (12U)
13303#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
13304#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
13305#define I2C_CR1_TXDMAEN_Pos (14U)
13306#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
13307#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
13308#define I2C_CR1_RXDMAEN_Pos (15U)
13309#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
13310#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
13311#define I2C_CR1_SBC_Pos (16U)
13312#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
13313#define I2C_CR1_SBC I2C_CR1_SBC_Msk
13314#define I2C_CR1_NOSTRETCH_Pos (17U)
13315#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
13316#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
13317#define I2C_CR1_WUPEN_Pos (18U)
13318#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
13319#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
13320#define I2C_CR1_GCEN_Pos (19U)
13321#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
13322#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
13323#define I2C_CR1_SMBHEN_Pos (20U)
13324#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
13325#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
13326#define I2C_CR1_SMBDEN_Pos (21U)
13327#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
13328#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
13329#define I2C_CR1_ALERTEN_Pos (22U)
13330#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
13331#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
13332#define I2C_CR1_PECEN_Pos (23U)
13333#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
13334#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
13336/****************** Bit definition for I2C_CR2 register ********************/
13337#define I2C_CR2_SADD_Pos (0U)
13338#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
13339#define I2C_CR2_SADD I2C_CR2_SADD_Msk
13340#define I2C_CR2_RD_WRN_Pos (10U)
13341#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
13342#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
13343#define I2C_CR2_ADD10_Pos (11U)
13344#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
13345#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
13346#define I2C_CR2_HEAD10R_Pos (12U)
13347#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
13348#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
13349#define I2C_CR2_START_Pos (13U)
13350#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
13351#define I2C_CR2_START I2C_CR2_START_Msk
13352#define I2C_CR2_STOP_Pos (14U)
13353#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
13354#define I2C_CR2_STOP I2C_CR2_STOP_Msk
13355#define I2C_CR2_NACK_Pos (15U)
13356#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
13357#define I2C_CR2_NACK I2C_CR2_NACK_Msk
13358#define I2C_CR2_NBYTES_Pos (16U)
13359#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
13360#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
13361#define I2C_CR2_RELOAD_Pos (24U)
13362#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
13363#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
13364#define I2C_CR2_AUTOEND_Pos (25U)
13365#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
13366#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
13367#define I2C_CR2_PECBYTE_Pos (26U)
13368#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
13369#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
13371/******************* Bit definition for I2C_OAR1 register ******************/
13372#define I2C_OAR1_OA1_Pos (0U)
13373#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
13374#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
13375#define I2C_OAR1_OA1MODE_Pos (10U)
13376#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
13377#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
13378#define I2C_OAR1_OA1EN_Pos (15U)
13379#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
13380#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
13382/******************* Bit definition for I2C_OAR2 register ******************/
13383#define I2C_OAR2_OA2_Pos (1U)
13384#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
13385#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
13386#define I2C_OAR2_OA2MSK_Pos (8U)
13387#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
13388#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
13389#define I2C_OAR2_OA2NOMASK 0x00000000UL
13390#define I2C_OAR2_OA2MASK01_Pos (8U)
13391#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
13392#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
13393#define I2C_OAR2_OA2MASK02_Pos (9U)
13394#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
13395#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
13396#define I2C_OAR2_OA2MASK03_Pos (8U)
13397#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
13398#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
13399#define I2C_OAR2_OA2MASK04_Pos (10U)
13400#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
13401#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
13402#define I2C_OAR2_OA2MASK05_Pos (8U)
13403#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
13404#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
13405#define I2C_OAR2_OA2MASK06_Pos (9U)
13406#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
13407#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
13408#define I2C_OAR2_OA2MASK07_Pos (8U)
13409#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
13410#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
13411#define I2C_OAR2_OA2EN_Pos (15U)
13412#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
13413#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
13415/******************* Bit definition for I2C_TIMINGR register *******************/
13416#define I2C_TIMINGR_SCLL_Pos (0U)
13417#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
13418#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
13419#define I2C_TIMINGR_SCLH_Pos (8U)
13420#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
13421#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
13422#define I2C_TIMINGR_SDADEL_Pos (16U)
13423#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
13424#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
13425#define I2C_TIMINGR_SCLDEL_Pos (20U)
13426#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
13427#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
13428#define I2C_TIMINGR_PRESC_Pos (28U)
13429#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
13430#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
13432/******************* Bit definition for I2C_TIMEOUTR register *******************/
13433#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
13434#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
13435#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
13436#define I2C_TIMEOUTR_TIDLE_Pos (12U)
13437#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
13438#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
13439#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
13440#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
13441#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
13442#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
13443#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
13444#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
13445#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
13446#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
13447#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
13449/****************** Bit definition for I2C_ISR register *********************/
13450#define I2C_ISR_TXE_Pos (0U)
13451#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
13452#define I2C_ISR_TXE I2C_ISR_TXE_Msk
13453#define I2C_ISR_TXIS_Pos (1U)
13454#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
13455#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
13456#define I2C_ISR_RXNE_Pos (2U)
13457#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
13458#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
13459#define I2C_ISR_ADDR_Pos (3U)
13460#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
13461#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
13462#define I2C_ISR_NACKF_Pos (4U)
13463#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
13464#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
13465#define I2C_ISR_STOPF_Pos (5U)
13466#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
13467#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
13468#define I2C_ISR_TC_Pos (6U)
13469#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
13470#define I2C_ISR_TC I2C_ISR_TC_Msk
13471#define I2C_ISR_TCR_Pos (7U)
13472#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
13473#define I2C_ISR_TCR I2C_ISR_TCR_Msk
13474#define I2C_ISR_BERR_Pos (8U)
13475#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
13476#define I2C_ISR_BERR I2C_ISR_BERR_Msk
13477#define I2C_ISR_ARLO_Pos (9U)
13478#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
13479#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
13480#define I2C_ISR_OVR_Pos (10U)
13481#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
13482#define I2C_ISR_OVR I2C_ISR_OVR_Msk
13483#define I2C_ISR_PECERR_Pos (11U)
13484#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
13485#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
13486#define I2C_ISR_TIMEOUT_Pos (12U)
13487#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
13488#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
13489#define I2C_ISR_ALERT_Pos (13U)
13490#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
13491#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
13492#define I2C_ISR_BUSY_Pos (15U)
13493#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
13494#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
13495#define I2C_ISR_DIR_Pos (16U)
13496#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
13497#define I2C_ISR_DIR I2C_ISR_DIR_Msk
13498#define I2C_ISR_ADDCODE_Pos (17U)
13499#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
13500#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
13502/****************** Bit definition for I2C_ICR register *********************/
13503#define I2C_ICR_ADDRCF_Pos (3U)
13504#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
13505#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
13506#define I2C_ICR_NACKCF_Pos (4U)
13507#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
13508#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
13509#define I2C_ICR_STOPCF_Pos (5U)
13510#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
13511#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
13512#define I2C_ICR_BERRCF_Pos (8U)
13513#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
13514#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
13515#define I2C_ICR_ARLOCF_Pos (9U)
13516#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
13517#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
13518#define I2C_ICR_OVRCF_Pos (10U)
13519#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
13520#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
13521#define I2C_ICR_PECCF_Pos (11U)
13522#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
13523#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
13524#define I2C_ICR_TIMOUTCF_Pos (12U)
13525#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
13526#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
13527#define I2C_ICR_ALERTCF_Pos (13U)
13528#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
13529#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
13531/****************** Bit definition for I2C_PECR register *********************/
13532#define I2C_PECR_PEC_Pos (0U)
13533#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
13534#define I2C_PECR_PEC I2C_PECR_PEC_Msk
13536/****************** Bit definition for I2C_RXDR register *********************/
13537#define I2C_RXDR_RXDATA_Pos (0U)
13538#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
13539#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
13541/****************** Bit definition for I2C_TXDR register *********************/
13542#define I2C_TXDR_TXDATA_Pos (0U)
13543#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
13544#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
13546/******************************************************************************/
13547/* */
13548/* Independent WATCHDOG */
13549/* */
13550/******************************************************************************/
13551/******************* Bit definition for IWDG_KR register ********************/
13552#define IWDG_KR_KEY_Pos (0U)
13553#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
13554#define IWDG_KR_KEY IWDG_KR_KEY_Msk
13556/******************* Bit definition for IWDG_PR register ********************/
13557#define IWDG_PR_PR_Pos (0U)
13558#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
13559#define IWDG_PR_PR IWDG_PR_PR_Msk
13560#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
13561#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
13562#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
13564/******************* Bit definition for IWDG_RLR register *******************/
13565#define IWDG_RLR_RL_Pos (0U)
13566#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
13567#define IWDG_RLR_RL IWDG_RLR_RL_Msk
13569/******************* Bit definition for IWDG_SR register ********************/
13570#define IWDG_SR_PVU_Pos (0U)
13571#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
13572#define IWDG_SR_PVU IWDG_SR_PVU_Msk
13573#define IWDG_SR_RVU_Pos (1U)
13574#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
13575#define IWDG_SR_RVU IWDG_SR_RVU_Msk
13576#define IWDG_SR_WVU_Pos (2U)
13577#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
13578#define IWDG_SR_WVU IWDG_SR_WVU_Msk
13580/******************* Bit definition for IWDG_KR register ********************/
13581#define IWDG_WINR_WIN_Pos (0U)
13582#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
13583#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
13585/******************************************************************************/
13586/* */
13587/* LCD-TFT Display Controller (LTDC) */
13588/* */
13589/******************************************************************************/
13590
13591/******************** Bit definition for LTDC_SSCR register *****************/
13592
13593#define LTDC_SSCR_VSH_Pos (0U)
13594#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos)
13595#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk
13596#define LTDC_SSCR_HSW_Pos (16U)
13597#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos)
13598#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk
13600/******************** Bit definition for LTDC_BPCR register *****************/
13601
13602#define LTDC_BPCR_AVBP_Pos (0U)
13603#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos)
13604#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk
13605#define LTDC_BPCR_AHBP_Pos (16U)
13606#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos)
13607#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk
13609/******************** Bit definition for LTDC_AWCR register *****************/
13610
13611#define LTDC_AWCR_AAH_Pos (0U)
13612#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos)
13613#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk
13614#define LTDC_AWCR_AAW_Pos (16U)
13615#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos)
13616#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk
13618/******************** Bit definition for LTDC_TWCR register *****************/
13619
13620#define LTDC_TWCR_TOTALH_Pos (0U)
13621#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos)
13622#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk
13623#define LTDC_TWCR_TOTALW_Pos (16U)
13624#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos)
13625#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk
13627/******************** Bit definition for LTDC_GCR register ******************/
13628
13629#define LTDC_GCR_LTDCEN_Pos (0U)
13630#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos)
13631#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk
13632#define LTDC_GCR_DBW_Pos (4U)
13633#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos)
13634#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk
13635#define LTDC_GCR_DGW_Pos (8U)
13636#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos)
13637#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk
13638#define LTDC_GCR_DRW_Pos (12U)
13639#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos)
13640#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk
13641#define LTDC_GCR_DEN_Pos (16U)
13642#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos)
13643#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk
13644#define LTDC_GCR_PCPOL_Pos (28U)
13645#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos)
13646#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk
13647#define LTDC_GCR_DEPOL_Pos (29U)
13648#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos)
13649#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk
13650#define LTDC_GCR_VSPOL_Pos (30U)
13651#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos)
13652#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk
13653#define LTDC_GCR_HSPOL_Pos (31U)
13654#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos)
13655#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk
13658/******************** Bit definition for LTDC_SRCR register *****************/
13659
13660#define LTDC_SRCR_IMR_Pos (0U)
13661#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos)
13662#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk
13663#define LTDC_SRCR_VBR_Pos (1U)
13664#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos)
13665#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk
13667/******************** Bit definition for LTDC_BCCR register *****************/
13668
13669#define LTDC_BCCR_BCBLUE_Pos (0U)
13670#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos)
13671#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk
13672#define LTDC_BCCR_BCGREEN_Pos (8U)
13673#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos)
13674#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk
13675#define LTDC_BCCR_BCRED_Pos (16U)
13676#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos)
13677#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk
13679/******************** Bit definition for LTDC_IER register ******************/
13680
13681#define LTDC_IER_LIE_Pos (0U)
13682#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos)
13683#define LTDC_IER_LIE LTDC_IER_LIE_Msk
13684#define LTDC_IER_FUIE_Pos (1U)
13685#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos)
13686#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk
13687#define LTDC_IER_TERRIE_Pos (2U)
13688#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos)
13689#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk
13690#define LTDC_IER_RRIE_Pos (3U)
13691#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos)
13692#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk
13694/******************** Bit definition for LTDC_ISR register ******************/
13695
13696#define LTDC_ISR_LIF_Pos (0U)
13697#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos)
13698#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk
13699#define LTDC_ISR_FUIF_Pos (1U)
13700#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos)
13701#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk
13702#define LTDC_ISR_TERRIF_Pos (2U)
13703#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos)
13704#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk
13705#define LTDC_ISR_RRIF_Pos (3U)
13706#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos)
13707#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk
13709/******************** Bit definition for LTDC_ICR register ******************/
13710
13711#define LTDC_ICR_CLIF_Pos (0U)
13712#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos)
13713#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk
13714#define LTDC_ICR_CFUIF_Pos (1U)
13715#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos)
13716#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk
13717#define LTDC_ICR_CTERRIF_Pos (2U)
13718#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos)
13719#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk
13720#define LTDC_ICR_CRRIF_Pos (3U)
13721#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos)
13722#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk
13724/******************** Bit definition for LTDC_LIPCR register ****************/
13725
13726#define LTDC_LIPCR_LIPOS_Pos (0U)
13727#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)
13728#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk
13730/******************** Bit definition for LTDC_CPSR register *****************/
13731
13732#define LTDC_CPSR_CYPOS_Pos (0U)
13733#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)
13734#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk
13735#define LTDC_CPSR_CXPOS_Pos (16U)
13736#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)
13737#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk
13739/******************** Bit definition for LTDC_CDSR register *****************/
13740
13741#define LTDC_CDSR_VDES_Pos (0U)
13742#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos)
13743#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk
13744#define LTDC_CDSR_HDES_Pos (1U)
13745#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos)
13746#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk
13747#define LTDC_CDSR_VSYNCS_Pos (2U)
13748#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos)
13749#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk
13750#define LTDC_CDSR_HSYNCS_Pos (3U)
13751#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos)
13752#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk
13754/******************** Bit definition for LTDC_LxCR register *****************/
13755
13756#define LTDC_LxCR_LEN_Pos (0U)
13757#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos)
13758#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk
13759#define LTDC_LxCR_COLKEN_Pos (1U)
13760#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos)
13761#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk
13762#define LTDC_LxCR_CLUTEN_Pos (4U)
13763#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos)
13764#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk
13766/******************** Bit definition for LTDC_LxWHPCR register **************/
13767
13768#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
13769#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)
13770#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk
13771#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
13772#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)
13773#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk
13775/******************** Bit definition for LTDC_LxWVPCR register **************/
13776
13777#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
13778#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)
13779#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk
13780#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
13781#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)
13782#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk
13784/******************** Bit definition for LTDC_LxCKCR register ***************/
13785
13786#define LTDC_LxCKCR_CKBLUE_Pos (0U)
13787#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)
13788#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk
13789#define LTDC_LxCKCR_CKGREEN_Pos (8U)
13790#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)
13791#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk
13792#define LTDC_LxCKCR_CKRED_Pos (16U)
13793#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos)
13794#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk
13796/******************** Bit definition for LTDC_LxPFCR register ***************/
13797
13798#define LTDC_LxPFCR_PF_Pos (0U)
13799#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos)
13800#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk
13802/******************** Bit definition for LTDC_LxCACR register ***************/
13803
13804#define LTDC_LxCACR_CONSTA_Pos (0U)
13805#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos)
13806#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk
13808/******************** Bit definition for LTDC_LxDCCR register ***************/
13809
13810#define LTDC_LxDCCR_DCBLUE_Pos (0U)
13811#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)
13812#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk
13813#define LTDC_LxDCCR_DCGREEN_Pos (8U)
13814#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)
13815#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk
13816#define LTDC_LxDCCR_DCRED_Pos (16U)
13817#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos)
13818#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk
13819#define LTDC_LxDCCR_DCALPHA_Pos (24U)
13820#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)
13821#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk
13823/******************** Bit definition for LTDC_LxBFCR register ***************/
13824
13825#define LTDC_LxBFCR_BF2_Pos (0U)
13826#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos)
13827#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk
13828#define LTDC_LxBFCR_BF1_Pos (8U)
13829#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos)
13830#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk
13832/******************** Bit definition for LTDC_LxCFBAR register **************/
13833
13834#define LTDC_LxCFBAR_CFBADD_Pos (0U)
13835#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)
13836#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk
13838/******************** Bit definition for LTDC_LxCFBLR register **************/
13839
13840#define LTDC_LxCFBLR_CFBLL_Pos (0U)
13841#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)
13842#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk
13843#define LTDC_LxCFBLR_CFBP_Pos (16U)
13844#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)
13845#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk
13847/******************** Bit definition for LTDC_LxCFBLNR register *************/
13848
13849#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
13850#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
13851#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk
13853/******************** Bit definition for LTDC_LxCLUTWR register *************/
13854
13855#define LTDC_LxCLUTWR_BLUE_Pos (0U)
13856#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)
13857#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk
13858#define LTDC_LxCLUTWR_GREEN_Pos (8U)
13859#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)
13860#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk
13861#define LTDC_LxCLUTWR_RED_Pos (16U)
13862#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos)
13863#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk
13864#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
13865#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)
13866#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk
13868/******************************************************************************/
13869/* */
13870/* MDMA */
13871/* */
13872/******************************************************************************/
13873/******************** Bit definition for MDMA_GISR0 register ****************/
13874#define MDMA_GISR0_GIF0_Pos (0U)
13875#define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos)
13876#define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk
13877#define MDMA_GISR0_GIF1_Pos (1U)
13878#define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos)
13879#define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk
13880#define MDMA_GISR0_GIF2_Pos (2U)
13881#define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos)
13882#define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk
13883#define MDMA_GISR0_GIF3_Pos (3U)
13884#define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos)
13885#define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk
13886#define MDMA_GISR0_GIF4_Pos (4U)
13887#define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos)
13888#define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk
13889#define MDMA_GISR0_GIF5_Pos (5U)
13890#define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos)
13891#define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk
13892#define MDMA_GISR0_GIF6_Pos (6U)
13893#define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos)
13894#define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk
13895#define MDMA_GISR0_GIF7_Pos (7U)
13896#define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos)
13897#define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk
13898#define MDMA_GISR0_GIF8_Pos (8U)
13899#define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos)
13900#define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk
13901#define MDMA_GISR0_GIF9_Pos (9U)
13902#define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos)
13903#define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk
13904#define MDMA_GISR0_GIF10_Pos (10U)
13905#define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos)
13906#define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk
13907#define MDMA_GISR0_GIF11_Pos (11U)
13908#define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos)
13909#define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk
13910#define MDMA_GISR0_GIF12_Pos (12U)
13911#define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos)
13912#define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk
13913#define MDMA_GISR0_GIF13_Pos (13U)
13914#define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos)
13915#define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk
13916#define MDMA_GISR0_GIF14_Pos (14U)
13917#define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos)
13918#define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk
13919#define MDMA_GISR0_GIF15_Pos (15U)
13920#define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos)
13921#define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk
13923/******************** Bit definition for MDMA_CxISR register ****************/
13924#define MDMA_CISR_TEIF_Pos (0U)
13925#define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos)
13926#define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk
13927#define MDMA_CISR_CTCIF_Pos (1U)
13928#define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos)
13929#define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk
13930#define MDMA_CISR_BRTIF_Pos (2U)
13931#define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos)
13932#define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk
13933#define MDMA_CISR_BTIF_Pos (3U)
13934#define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos)
13935#define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk
13936#define MDMA_CISR_TCIF_Pos (4U)
13937#define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos)
13938#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk
13939#define MDMA_CISR_CRQA_Pos (16U)
13940#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos)
13941#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk
13943/******************** Bit definition for MDMA_CxIFCR register ****************/
13944#define MDMA_CIFCR_CTEIF_Pos (0U)
13945#define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos)
13946#define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk
13947#define MDMA_CIFCR_CCTCIF_Pos (1U)
13948#define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos)
13949#define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk
13950#define MDMA_CIFCR_CBRTIF_Pos (2U)
13951#define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos)
13952#define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk
13953#define MDMA_CIFCR_CBTIF_Pos (3U)
13954#define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos)
13955#define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk
13956#define MDMA_CIFCR_CLTCIF_Pos (4U)
13957#define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos)
13958#define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk
13960/******************** Bit definition for MDMA_CxESR register ****************/
13961#define MDMA_CESR_TEA_Pos (0U)
13962#define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos)
13963#define MDMA_CESR_TEA MDMA_CESR_TEA_Msk
13964#define MDMA_CESR_TED_Pos (7U)
13965#define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos)
13966#define MDMA_CESR_TED MDMA_CESR_TED_Msk
13967#define MDMA_CESR_TELD_Pos (8U)
13968#define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos)
13969#define MDMA_CESR_TELD MDMA_CESR_TELD_Msk
13970#define MDMA_CESR_TEMD_Pos (9U)
13971#define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos)
13972#define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk
13973#define MDMA_CESR_ASE_Pos (10U)
13974#define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos)
13975#define MDMA_CESR_ASE MDMA_CESR_ASE_Msk
13976#define MDMA_CESR_BSE_Pos (11U)
13977#define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos)
13978#define MDMA_CESR_BSE MDMA_CESR_BSE_Msk
13980/******************** Bit definition for MDMA_CxCR register ****************/
13981#define MDMA_CCR_EN_Pos (0U)
13982#define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos)
13983#define MDMA_CCR_EN MDMA_CCR_EN_Msk
13984#define MDMA_CCR_TEIE_Pos (1U)
13985#define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos)
13986#define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk
13987#define MDMA_CCR_CTCIE_Pos (2U)
13988#define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos)
13989#define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk
13990#define MDMA_CCR_BRTIE_Pos (3U)
13991#define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos)
13992#define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk
13993#define MDMA_CCR_BTIE_Pos (4U)
13994#define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos)
13995#define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk
13996#define MDMA_CCR_TCIE_Pos (5U)
13997#define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos)
13998#define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk
13999#define MDMA_CCR_PL_Pos (6U)
14000#define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos)
14001#define MDMA_CCR_PL MDMA_CCR_PL_Msk
14002#define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos)
14003#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos)
14004#define MDMA_CCR_BEX_Pos (12U)
14005#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos)
14006#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk
14007#define MDMA_CCR_HEX_Pos (13U)
14008#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos)
14009#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk
14010#define MDMA_CCR_WEX_Pos (14U)
14011#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos)
14012#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk
14013#define MDMA_CCR_SWRQ_Pos (16U)
14014#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos)
14015#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk
14017/******************** Bit definition for MDMA_CxTCR register ****************/
14018#define MDMA_CTCR_SINC_Pos (0U)
14019#define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos)
14020#define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk
14021#define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos)
14022#define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos)
14023#define MDMA_CTCR_DINC_Pos (2U)
14024#define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos)
14025#define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk
14026#define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos)
14027#define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos)
14028#define MDMA_CTCR_SSIZE_Pos (4U)
14029#define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos)
14030#define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk
14031#define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos)
14032#define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos)
14033#define MDMA_CTCR_DSIZE_Pos (6U)
14034#define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos)
14035#define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk
14036#define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos)
14037#define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos)
14038#define MDMA_CTCR_SINCOS_Pos (8U)
14039#define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos)
14040#define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk
14041#define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos)
14042#define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos)
14043#define MDMA_CTCR_DINCOS_Pos (10U)
14044#define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos)
14045#define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk
14046#define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos)
14047#define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos)
14048#define MDMA_CTCR_SBURST_Pos (12U)
14049#define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos)
14050#define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk
14051#define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos)
14052#define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos)
14053#define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos)
14054#define MDMA_CTCR_DBURST_Pos (15U)
14055#define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos)
14056#define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk
14057#define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos)
14058#define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos)
14059#define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos)
14060#define MDMA_CTCR_TLEN_Pos (18U)
14061#define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos)
14062#define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk
14063#define MDMA_CTCR_PKE_Pos (25U)
14064#define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos)
14065#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk
14066#define MDMA_CTCR_PAM_Pos (26U)
14067#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos)
14068#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk
14069#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos)
14070#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos)
14071#define MDMA_CTCR_TRGM_Pos (28U)
14072#define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos)
14073#define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk
14074#define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos)
14075#define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos)
14076#define MDMA_CTCR_SWRM_Pos (30U)
14077#define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos)
14078#define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk
14079#define MDMA_CTCR_BWM_Pos (31U)
14080#define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos)
14081#define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk
14083/******************** Bit definition for MDMA_CxBNDTR register ****************/
14084#define MDMA_CBNDTR_BNDT_Pos (0U)
14085#define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)
14086#define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk
14087#define MDMA_CBNDTR_BRSUM_Pos (18U)
14088#define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos)
14089#define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk
14090#define MDMA_CBNDTR_BRDUM_Pos (19U)
14091#define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos)
14092#define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk
14093#define MDMA_CBNDTR_BRC_Pos (20U)
14094#define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos)
14095#define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk
14097/******************** Bit definition for MDMA_CxSAR register ****************/
14098#define MDMA_CSAR_SAR_Pos (0U)
14099#define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)
14100#define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk
14102/******************** Bit definition for MDMA_CxDAR register ****************/
14103#define MDMA_CDAR_DAR_Pos (0U)
14104#define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)
14105#define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk
14107/******************** Bit definition for MDMA_CxBRUR ************************/
14108#define MDMA_CBRUR_SUV_Pos (0U)
14109#define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos)
14110#define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk
14111#define MDMA_CBRUR_DUV_Pos (16U)
14112#define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos)
14113#define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk
14115/******************** Bit definition for MDMA_CxLAR *************************/
14116#define MDMA_CLAR_LAR_Pos (0U)
14117#define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)
14118#define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk
14120/******************** Bit definition for MDMA_CxTBR) ************************/
14121#define MDMA_CTBR_TSEL_Pos (0U)
14122#define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos)
14123#define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk
14124#define MDMA_CTBR_SBUS_Pos (16U)
14125#define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos)
14126#define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk
14127#define MDMA_CTBR_DBUS_Pos (17U)
14128#define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos)
14129#define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk
14131/******************** Bit definition for MDMA_CxMAR) ************************/
14132#define MDMA_CMAR_MAR_Pos (0U)
14133#define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)
14134#define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk
14136/******************** Bit definition for MDMA_CxMDR) ************************/
14137#define MDMA_CMDR_MDR_Pos (0U)
14138#define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)
14139#define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk
14141/******************************************************************************/
14142/* */
14143/* Operational Amplifier (OPAMP) */
14144/* */
14145/******************************************************************************/
14146/********************* Bit definition for OPAMPx_CSR register ***************/
14147#define OPAMP_CSR_OPAMPxEN_Pos (0U)
14148#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
14149#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk
14150#define OPAMP_CSR_FORCEVP_Pos (1U)
14151#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)
14152#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk
14154#define OPAMP_CSR_VPSEL_Pos (2U)
14155#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)
14156#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk
14157#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)
14158#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)
14160#define OPAMP_CSR_VMSEL_Pos (5U)
14161#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)
14162#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk
14163#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)
14164#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)
14166#define OPAMP_CSR_OPAHSM_Pos (8U)
14167#define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos)
14168#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk
14169#define OPAMP_CSR_CALON_Pos (11U)
14170#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)
14171#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk
14173#define OPAMP_CSR_CALSEL_Pos (12U)
14174#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)
14175#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk
14176#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)
14177#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)
14179#define OPAMP_CSR_PGGAIN_Pos (14U)
14180#define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos)
14181#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk
14182#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)
14183#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)
14184#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)
14185#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)
14187#define OPAMP_CSR_USERTRIM_Pos (18U)
14188#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)
14189#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk
14190#define OPAMP_CSR_TSTREF_Pos (29U)
14191#define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos)
14192#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk
14193#define OPAMP_CSR_CALOUT_Pos (30U)
14194#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos)
14195#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk
14197/********************* Bit definition for OPAMP1_CSR register ***************/
14198#define OPAMP1_CSR_OPAEN_Pos (0U)
14199#define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos)
14200#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk
14201#define OPAMP1_CSR_FORCEVP_Pos (1U)
14202#define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos)
14203#define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk
14205#define OPAMP1_CSR_VPSEL_Pos (2U)
14206#define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos)
14207#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk
14208#define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos)
14209#define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos)
14211#define OPAMP1_CSR_VMSEL_Pos (5U)
14212#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)
14213#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk
14214#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)
14215#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)
14217#define OPAMP1_CSR_OPAHSM_Pos (8U)
14218#define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos)
14219#define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk
14220#define OPAMP1_CSR_CALON_Pos (11U)
14221#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)
14222#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk
14224#define OPAMP1_CSR_CALSEL_Pos (12U)
14225#define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos)
14226#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk
14227#define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos)
14228#define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos)
14230#define OPAMP1_CSR_PGGAIN_Pos (14U)
14231#define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos)
14232#define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk
14233#define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos)
14234#define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos)
14235#define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos)
14236#define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos)
14238#define OPAMP1_CSR_USERTRIM_Pos (18U)
14239#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)
14240#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk
14241#define OPAMP1_CSR_TSTREF_Pos (29U)
14242#define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos)
14243#define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk
14244#define OPAMP1_CSR_CALOUT_Pos (30U)
14245#define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos)
14246#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk
14248/********************* Bit definition for OPAMP2_CSR register ***************/
14249#define OPAMP2_CSR_OPAEN_Pos (0U)
14250#define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos)
14251#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk
14252#define OPAMP2_CSR_FORCEVP_Pos (1U)
14253#define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos)
14254#define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk
14256#define OPAMP2_CSR_VPSEL_Pos (2U)
14257#define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos)
14258#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk
14259#define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos)
14260#define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos)
14262#define OPAMP2_CSR_VMSEL_Pos (5U)
14263#define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)
14264#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk
14265#define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)
14266#define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)
14268#define OPAMP2_CSR_OPAHSM_Pos (8U)
14269#define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos)
14270#define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk
14271#define OPAMP2_CSR_CALON_Pos (11U)
14272#define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)
14273#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk
14275#define OPAMP2_CSR_CALSEL_Pos (12U)
14276#define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos)
14277#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk
14278#define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos)
14279#define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos)
14281#define OPAMP2_CSR_PGGAIN_Pos (14U)
14282#define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos)
14283#define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk
14284#define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos)
14285#define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos)
14286#define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos)
14287#define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos)
14289#define OPAMP2_CSR_USERTRIM_Pos (18U)
14290#define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)
14291#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk
14292#define OPAMP2_CSR_TSTREF_Pos (29U)
14293#define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos)
14294#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk
14295#define OPAMP2_CSR_CALOUT_Pos (30U)
14296#define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos)
14297#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk
14299/******************* Bit definition for OPAMP_OTR register ******************/
14300#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
14301#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)
14302#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk
14303#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
14304#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)
14305#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk
14307/******************* Bit definition for OPAMP1_OTR register ******************/
14308#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
14309#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos)
14310#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk
14311#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
14312#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos)
14313#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk
14315/******************* Bit definition for OPAMP2_OTR register ******************/
14316#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
14317#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos)
14318#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk
14319#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
14320#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos)
14321#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk
14323/******************* Bit definition for OPAMP_HSOTR register ****************/
14324#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
14325#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos)
14326#define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk
14327#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
14328#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos)
14329#define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk
14331/******************* Bit definition for OPAMP1_HSOTR register ****************/
14332#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
14333#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos)
14334#define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk
14335#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
14336#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos)
14337#define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk
14339/******************* Bit definition for OPAMP2_HSOTR register ****************/
14340#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
14341#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos)
14342#define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk
14343#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
14344#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos)
14345#define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk
14347/******************************************************************************/
14348/* */
14349/* Parallel Synchronous Slave Interface (PSSI ) */
14350/* */
14351/******************************************************************************/
14352
14353/******************** Bit definition for PSSI_CR register *******************/
14354#define PSSI_CR_OUTEN_Pos (31U)
14355#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos)
14356#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk
14357#define PSSI_CR_DMAEN_Pos (30U)
14358#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos)
14359#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk
14360#define PSSI_CR_DERDYCFG_Pos (18U)
14361#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos)
14362#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk
14363#define PSSI_CR_ENABLE_Pos (14U)
14364#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos)
14365#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk
14366#define PSSI_CR_EDM_Pos (10U)
14367#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos)
14368#define PSSI_CR_EDM PSSI_CR_EDM_Msk
14369#define PSSI_CR_RDYPOL_Pos (8U)
14370#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos)
14371#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk
14372#define PSSI_CR_DEPOL_Pos (6U)
14373#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos)
14374#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk
14375#define PSSI_CR_CKPOL_Pos (5U)
14376#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos)
14377#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk
14378/******************** Bit definition for PSSI_SR register *******************/
14379#define PSSI_SR_RTT1B_Pos (3U)
14380#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos)
14381#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk
14382#define PSSI_SR_RTT4B_Pos (2U)
14383#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos)
14384#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk
14385/******************** Bit definition for PSSI_RIS register *******************/
14386#define PSSI_RIS_OVR_RIS_Pos (1U)
14387#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos)
14388#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk
14389/******************** Bit definition for PSSI_IER register *******************/
14390#define PSSI_IER_OVR_IE_Pos (1U)
14391#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos)
14392#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk
14393/******************** Bit definition for PSSI_MIS register *******************/
14394#define PSSI_MIS_OVR_MIS_Pos (1U)
14395#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos)
14396#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk
14397/******************** Bit definition for PSSI_ICR register *******************/
14398#define PSSI_ICR_OVR_ISC_Pos (1U)
14399#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos)
14400#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk
14401/******************** Bit definition for PSSI_DR register *******************/
14402#define PSSI_DR_DR_Pos (0U)
14403#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos)
14404#define PSSI_DR_DR PSSI_DR_DR_Msk
14406/******************************************************************************/
14407/* */
14408/* On The Fly Decryption */
14409/* */
14410/******************************************************************************/
14411/****************** Bit definition for OTFDEC_CR register ******************/
14412#define OTFDEC_CR_ENC_Pos (0U)
14413#define OTFDEC_CR_ENC_Msk (0x1UL << OTFDEC_CR_ENC_Pos)
14414#define OTFDEC_CR_ENC OTFDEC_CR_ENC_Msk
14416/****************** Bit definition for OTFDEC_PRIVCFGR register ************/
14417#define OTFDEC_PRIVCFGR_PRIV_Pos (0U)
14418#define OTFDEC_PRIVCFGR_PRIV_Msk (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos)
14419#define OTFDEC_PRIVCFGR_PRIV OTFDEC_PRIVCFGR_PRIV_Msk
14421/****************** Bit definition for OTFDEC_REG_CONFIGR register *********/
14422#define OTFDEC_REG_CONFIGR_REG_EN_Pos (0U)
14423#define OTFDEC_REG_CONFIGR_REG_EN_Msk (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos)
14424#define OTFDEC_REG_CONFIGR_REG_EN OTFDEC_REG_CONFIGR_REG_EN_Msk
14426#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos (1U)
14427#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos)
14428#define OTFDEC_REG_CONFIGR_CONFIGLOCK OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk
14430#define OTFDEC_REG_CONFIGR_KEYLOCK_Pos (2U)
14431#define OTFDEC_REG_CONFIGR_KEYLOCK_Msk (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos)
14432#define OTFDEC_REG_CONFIGR_KEYLOCK OTFDEC_REG_CONFIGR_KEYLOCK_Msk
14434#define OTFDEC_REG_CONFIGR_MODE_Pos (4U)
14435#define OTFDEC_REG_CONFIGR_MODE_Msk (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos)
14436#define OTFDEC_REG_CONFIGR_MODE OTFDEC_REG_CONFIGR_MODE_Msk
14437#define OTFDEC_REG_CONFIGR_MODE_0 (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos)
14438#define OTFDEC_REG_CONFIGR_MODE_1 (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos)
14440#define OTFDEC_REG_CONFIGR_KEYCRC_Pos (8U)
14441#define OTFDEC_REG_CONFIGR_KEYCRC_Msk (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos)
14442#define OTFDEC_REG_CONFIGR_KEYCRC OTFDEC_REG_CONFIGR_KEYCRC_Msk
14444#define OTFDEC_REG_CONFIGR_VERSION_Pos (16U)
14445#define OTFDEC_REG_CONFIGR_VERSION_Msk (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos)
14446#define OTFDEC_REG_CONFIGR_VERSION OTFDEC_REG_CONFIGR_VERSION_Msk
14448/****************** Bit definition for OTFDEC_REG_START_ADDR register ******/
14449#define OTFDEC_REG_START_ADDR_Pos (0U)
14450#define OTFDEC_REG_START_ADDR_Msk (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos)
14451#define OTFDEC_REG_START_ADDR OTFDEC_REG_START_ADDR_Msk
14453/****************** Bit definition for OTFDEC_REG_END_ADDR register ********/
14454#define OTFDEC_REG_END_ADDR_Pos (0U)
14455#define OTFDEC_REG_END_ADDR_Msk (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos)
14456#define OTFDEC_REG_END_ADDR OTFDEC_REG_END_ADDR_Msk
14458/****************** Bit definition for OTFDEC_REG_NONCER0 register *********/
14459#define OTFDEC_REG_NONCER0_Pos (0U)
14460#define OTFDEC_REG_NONCER0_Msk (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos)
14461#define OTFDEC_REG_NONCER0 OTFDEC_REG_NONCER0_Msk
14463/****************** Bit definition for OTFDEC_REG_NONCER1 register *********/
14464#define OTFDEC_REG_NONCER1_Pos (0U)
14465#define OTFDEC_REG_NONCER1_Msk (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos)
14466#define OTFDEC_REG_NONCER1 OTFDEC_REG_NONCER1_Msk
14468/****************** Bit definition for OTFDEC_REG_KEYR0 register ***********/
14469#define OTFDEC_REG_KEYR0_Pos (0U)
14470#define OTFDEC_REG_KEYR0_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos)
14471#define OTFDEC_REG_KEYR0 OTFDEC_REG_KEYR0_Msk
14473/****************** Bit definition for OTFDEC_REG_KEYR1 register ***********/
14474#define OTFDEC_REG_KEYR1_Pos (0U)
14475#define OTFDEC_REG_KEYR1_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos)
14476#define OTFDEC_REG_KEYR1 OTFDEC_REG_KEYR1_Msk
14478/****************** Bit definition for OTFDEC_REG_KEYR2 register ***********/
14479#define OTFDEC_REG_KEYR2_Pos (0U)
14480#define OTFDEC_REG_KEYR2_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos)
14481#define OTFDEC_REG_KEYR2 OTFDEC_REG_KEYR2_Msk
14483/****************** Bit definition for OTFDEC_REG_KEYR3 register ***********/
14484#define OTFDEC_REG_KEYR3_Pos (0U)
14485#define OTFDEC_REG_KEYR3_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos)
14486#define OTFDEC_REG_KEYR3 OTFDEC_REG_KEYR3_Msk
14488/****************** Bit definition for OTFDEC_ISR register *****************/
14489#define OTFDEC_ISR_SEIF_Pos (0U)
14490#define OTFDEC_ISR_SEIF_Msk (0x1UL << OTFDEC_ISR_SEIF_Pos)
14491#define OTFDEC_ISR_SEIF OTFDEC_ISR_SEIF_Msk
14493#define OTFDEC_ISR_XONEIF_Pos (1U)
14494#define OTFDEC_ISR_XONEIF_Msk (0x1UL << OTFDEC_ISR_XONEIF_Pos)
14495#define OTFDEC_ISR_XONEIF OTFDEC_ISR_XONEIF_Msk
14497#define OTFDEC_ISR_KEIF_Pos (2U)
14498#define OTFDEC_ISR_KEIF_Msk (0x1UL << OTFDEC_ISR_KEIF_Pos)
14499#define OTFDEC_ISR_KEIF OTFDEC_ISR_KEIF_Msk
14501/****************** Bit definition for OTFDEC_ICR register *****************/
14502#define OTFDEC_ICR_SEIF_Pos (0U)
14503#define OTFDEC_ICR_SEIF_Msk (0x1UL << OTFDEC_ICR_SEIF_Pos)
14504#define OTFDEC_ICR_SEIF OTFDEC_ICR_SEIF_Msk
14506#define OTFDEC_ICR_XONEIF_Pos (1U)
14507#define OTFDEC_ICR_XONEIF_Msk (0x1UL << OTFDEC_ICR_XONEIF_Pos)
14508#define OTFDEC_ICR_XONEIF OTFDEC_ICR_XONEIF_Msk
14510#define OTFDEC_ICR_KEIF_Pos (2U)
14511#define OTFDEC_ICR_KEIF_Msk (0x1UL << OTFDEC_ICR_KEIF_Pos)
14512#define OTFDEC_ICR_KEIF OTFDEC_ICR_KEIF_Msk
14514/****************** Bit definition for OTFDEC_IER register *****************/
14515#define OTFDEC_IER_SEIE_Pos (0U)
14516#define OTFDEC_IER_SEIE_Msk (0x1UL << OTFDEC_IER_SEIE_Pos)
14517#define OTFDEC_IER_SEIE OTFDEC_IER_SEIE_Msk
14519#define OTFDEC_IER_XONEIE_Pos (1U)
14520#define OTFDEC_IER_XONEIE_Msk (0x1UL << OTFDEC_IER_XONEIE_Pos)
14521#define OTFDEC_IER_XONEIE OTFDEC_IER_XONEIE_Msk
14523#define OTFDEC_IER_KEIE_Pos (2U)
14524#define OTFDEC_IER_KEIE_Msk (0x1UL << OTFDEC_IER_KEIE_Pos)
14525#define OTFDEC_IER_KEIE OTFDEC_IER_KEIE_Msk
14526
14527/******************************************************************************/
14528/* */
14529/* Power Control */
14530/* */
14531/******************************************************************************/
14532/************************* NUMBER OF POWER DOMAINS **************************/
14533#define POWER_DOMAINS_NUMBER 3U
14535/******************** Bit definition for PWR_CR1 register *******************/
14536#define PWR_CR1_ALS_Pos (17U)
14537#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos)
14538#define PWR_CR1_ALS PWR_CR1_ALS_Msk
14539#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos)
14540#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos)
14541#define PWR_CR1_AVDEN_Pos (16U)
14542#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos)
14543#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk
14544#define PWR_CR1_SVOS_Pos (14U)
14545#define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos)
14546#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk
14547#define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos)
14548#define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos)
14549#define PWR_CR1_FLPS_Pos (9U)
14550#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos)
14551#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk
14552#define PWR_CR1_DBP_Pos (8U)
14553#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
14554#define PWR_CR1_DBP PWR_CR1_DBP_Msk
14555#define PWR_CR1_PLS_Pos (5U)
14556#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos)
14557#define PWR_CR1_PLS PWR_CR1_PLS_Msk
14558#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos)
14559#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos)
14560#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos)
14561#define PWR_CR1_PVDEN_Pos (4U)
14562#define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos)
14563#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk
14564#define PWR_CR1_LPDS_Pos (0U)
14565#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos)
14566#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk
14569#define PWR_CR1_PLS_LEV0 (0UL)
14570#define PWR_CR1_PLS_LEV1_Pos (5U)
14571#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos)
14572#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk
14573#define PWR_CR1_PLS_LEV2_Pos (6U)
14574#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos)
14575#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk
14576#define PWR_CR1_PLS_LEV3_Pos (5U)
14577#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos)
14578#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk
14579#define PWR_CR1_PLS_LEV4_Pos (7U)
14580#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos)
14581#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk
14582#define PWR_CR1_PLS_LEV5_Pos (5U)
14583#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos)
14584#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk
14585#define PWR_CR1_PLS_LEV6_Pos (6U)
14586#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos)
14587#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk
14588#define PWR_CR1_PLS_LEV7_Pos (5U)
14589#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos)
14590#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk
14593#define PWR_CR1_ALS_LEV0 (0UL)
14594#define PWR_CR1_ALS_LEV1_Pos (17U)
14595#define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos)
14596#define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk
14597#define PWR_CR1_ALS_LEV2_Pos (18U)
14598#define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos)
14599#define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk
14600#define PWR_CR1_ALS_LEV3_Pos (17U)
14601#define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos)
14602#define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk
14604/******************** Bit definition for PWR_CSR1 register ******************/
14605#define PWR_CSR1_AVDO_Pos (16U)
14606#define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos)
14607#define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk
14608#define PWR_CSR1_ACTVOS_Pos (14U)
14609#define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos)
14610#define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk
14611#define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos)
14612#define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos)
14613#define PWR_CSR1_ACTVOSRDY_Pos (13U)
14614#define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)
14615#define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk
14616#define PWR_CSR1_PVDO_Pos (4U)
14617#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos)
14618#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk
14620/******************** Bit definition for PWR_CR2 register *******************/
14621#define PWR_CR2_TEMPH_Pos (23U)
14622#define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos)
14623#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk
14624#define PWR_CR2_TEMPL_Pos (22U)
14625#define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos)
14626#define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk
14627#define PWR_CR2_VBATH_Pos (21U)
14628#define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos)
14629#define PWR_CR2_VBATH PWR_CR2_VBATH_Msk
14630#define PWR_CR2_VBATL_Pos (20U)
14631#define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos)
14632#define PWR_CR2_VBATL PWR_CR2_VBATL_Msk
14633#define PWR_CR2_BRRDY_Pos (16U)
14634#define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos)
14635#define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk
14636#define PWR_CR2_MONEN_Pos (4U)
14637#define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos)
14638#define PWR_CR2_MONEN PWR_CR2_MONEN_Msk
14639#define PWR_CR2_BREN_Pos (0U)
14640#define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos)
14641#define PWR_CR2_BREN PWR_CR2_BREN_Msk
14643/******************** Bit definition for PWR_CR3 register *******************/
14644#define PWR_CR3_USB33RDY_Pos (26U)
14645#define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos)
14646#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk
14647#define PWR_CR3_USBREGEN_Pos (25U)
14648#define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos)
14649#define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk
14650#define PWR_CR3_USB33DEN_Pos (24U)
14651#define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos)
14652#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk
14653#define PWR_CR3_VBRS_Pos (9U)
14654#define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos)
14655#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk
14656#define PWR_CR3_VBE_Pos (8U)
14657#define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos)
14658#define PWR_CR3_VBE PWR_CR3_VBE_Msk
14659#define PWR_CR3_SCUEN_Pos (2U)
14660#define PWR_CR3_SCUEN_Msk (0x1UL << PWR_CR3_SCUEN_Pos)
14661#define PWR_CR3_SCUEN PWR_CR3_SCUEN_Msk
14662#define PWR_CR3_LDOEN_Pos (1U)
14663#define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos)
14664#define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk
14665#define PWR_CR3_BYPASS_Pos (0U)
14666#define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos)
14667#define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk
14669/******************** Bit definition for PWR_CPUCR register *****************/
14670#define PWR_CPUCR_RUN_D3_Pos (11U)
14671#define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos)
14672#define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk
14673#define PWR_CPUCR_CSSF_Pos (9U)
14674#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos)
14675#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk
14676#define PWR_CPUCR_SBF_D2_Pos (8U)
14677#define PWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos)
14678#define PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk
14679#define PWR_CPUCR_SBF_D1_Pos (7U)
14680#define PWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos)
14681#define PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk
14682#define PWR_CPUCR_SBF_Pos (6U)
14683#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos)
14684#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk
14685#define PWR_CPUCR_STOPF_Pos (5U)
14686#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos)
14687#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk
14688#define PWR_CPUCR_PDDS_D3_Pos (2U)
14689#define PWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos)
14690#define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk
14691#define PWR_CPUCR_PDDS_D2_Pos (1U)
14692#define PWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos)
14693#define PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk
14694#define PWR_CPUCR_PDDS_D1_Pos (0U)
14695#define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos)
14696#define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk
14699/******************** Bit definition for PWR_D3CR register ******************/
14700#define PWR_D3CR_VOS_Pos (14U)
14701#define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos)
14702#define PWR_D3CR_VOS PWR_D3CR_VOS_Msk
14703#define PWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos)
14704#define PWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos)
14705#define PWR_D3CR_VOSRDY_Pos (13U)
14706#define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos)
14707#define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk
14709/****************** Bit definition for PWR_WKUPCR register ******************/
14710#define PWR_WKUPCR_WKUPC6_Pos (5U)
14711#define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos)
14712#define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk
14713#define PWR_WKUPCR_WKUPC4_Pos (3U)
14714#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos)
14715#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk
14716#define PWR_WKUPCR_WKUPC2_Pos (1U)
14717#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos)
14718#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk
14719#define PWR_WKUPCR_WKUPC1_Pos (0U)
14720#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos)
14721#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk
14723/******************** Bit definition for PWR_WKUPFR register ****************/
14724#define PWR_WKUPFR_WKUPF6_Pos (5U)
14725#define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos)
14726#define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk
14727#define PWR_WKUPFR_WKUPF4_Pos (3U)
14728#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos)
14729#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk
14730#define PWR_WKUPFR_WKUPF2_Pos (1U)
14731#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos)
14732#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk
14733#define PWR_WKUPFR_WKUPF1_Pos (0U)
14734#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos)
14735#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk
14737/****************** Bit definition for PWR_WKUPEPR register *****************/
14738#define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
14739#define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
14740#define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk
14741#define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
14742#define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
14743#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
14744#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
14745#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk
14746#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
14747#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
14748#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
14749#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
14750#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk
14751#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
14752#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
14753#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
14754#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
14755#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk
14756#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
14757#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
14758#define PWR_WKUPEPR_WKUPP6_Pos (13U)
14759#define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)
14760#define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk
14761#define PWR_WKUPEPR_WKUPP4_Pos (11U)
14762#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)
14763#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk
14764#define PWR_WKUPEPR_WKUPP2_Pos (9U)
14765#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)
14766#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk
14767#define PWR_WKUPEPR_WKUPP1_Pos (8U)
14768#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)
14769#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk
14770#define PWR_WKUPEPR_WKUPEN6_Pos (5U)
14771#define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)
14772#define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk
14773#define PWR_WKUPEPR_WKUPEN4_Pos (3U)
14774#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)
14775#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk
14776#define PWR_WKUPEPR_WKUPEN2_Pos (1U)
14777#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)
14778#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk
14779#define PWR_WKUPEPR_WKUPEN1_Pos (0U)
14780#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)
14781#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk
14782#define PWR_WKUPEPR_WKUPEN_Pos (0U)
14783#define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)
14784#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk
14786/******************************************************************************/
14787/* */
14788/* Reset and Clock Control */
14789/* */
14790/******************************************************************************/
14791/******************************* RCC VERSION ********************************/
14792#define RCC_VER_3_0
14793
14794/******************** Bit definition for RCC_CR register ********************/
14795#define RCC_CR_HSION_Pos (0U)
14796#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
14797#define RCC_CR_HSION RCC_CR_HSION_Msk
14798#define RCC_CR_HSIKERON_Pos (1U)
14799#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)
14800#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk
14801#define RCC_CR_HSIRDY_Pos (2U)
14802#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
14803#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
14804#define RCC_CR_HSIDIV_Pos (3U)
14805#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos)
14806#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk
14807#define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos)
14808#define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos)
14809#define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos)
14810#define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos)
14812#define RCC_CR_HSIDIVF_Pos (5U)
14813#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos)
14814#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk
14815#define RCC_CR_CSION_Pos (7U)
14816#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos)
14817#define RCC_CR_CSION RCC_CR_CSION_Msk
14818#define RCC_CR_CSIRDY_Pos (8U)
14819#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos)
14820#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk
14821#define RCC_CR_CSIKERON_Pos (9U)
14822#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos)
14823#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk
14824#define RCC_CR_HSI48ON_Pos (12U)
14825#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos)
14826#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk
14827#define RCC_CR_HSI48RDY_Pos (13U)
14828#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos)
14829#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk
14831#define RCC_CR_D1CKRDY_Pos (14U)
14832#define RCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos)
14833#define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk
14834#define RCC_CR_D2CKRDY_Pos (15U)
14835#define RCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos)
14836#define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk
14838#define RCC_CR_HSEON_Pos (16U)
14839#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
14840#define RCC_CR_HSEON RCC_CR_HSEON_Msk
14841#define RCC_CR_HSERDY_Pos (17U)
14842#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
14843#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
14844#define RCC_CR_HSEBYP_Pos (18U)
14845#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
14846#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
14847#define RCC_CR_CSSHSEON_Pos (19U)
14848#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos)
14849#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk
14852#define RCC_CR_PLL1ON_Pos (24U)
14853#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos)
14854#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk
14855#define RCC_CR_PLL1RDY_Pos (25U)
14856#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos)
14857#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk
14858#define RCC_CR_PLL2ON_Pos (26U)
14859#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos)
14860#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk
14861#define RCC_CR_PLL2RDY_Pos (27U)
14862#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos)
14863#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk
14864#define RCC_CR_PLL3ON_Pos (28U)
14865#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos)
14866#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk
14867#define RCC_CR_PLL3RDY_Pos (29U)
14868#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos)
14869#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk
14871/*Legacy */
14872#define RCC_CR_PLLON_Pos (24U)
14873#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
14874#define RCC_CR_PLLON RCC_CR_PLLON_Msk
14875#define RCC_CR_PLLRDY_Pos (25U)
14876#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
14877#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
14879/******************** Bit definition for RCC_HSICFGR register ***************/
14881#define RCC_HSICFGR_HSICAL_Pos (0U)
14882#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos)
14883#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk
14884#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos)
14885#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos)
14886#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos)
14887#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos)
14888#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos)
14889#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos)
14890#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos)
14891#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos)
14892#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos)
14893#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos)
14894#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos)
14895#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos)
14898#define RCC_HSICFGR_HSITRIM_Pos (24U)
14899#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)
14900#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk
14901#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos)
14902#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos)
14903#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos)
14904#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos)
14905#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos)
14906#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos)
14907#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos)
14910/******************** Bit definition for RCC_CRRCR register *****************/
14911
14913#define RCC_CRRCR_HSI48CAL_Pos (0U)
14914#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos)
14915#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk
14916#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)
14917#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)
14918#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)
14919#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)
14920#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)
14921#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)
14922#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)
14923#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)
14924#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)
14925#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos)
14928/******************** Bit definition for RCC_CSICFGR register *****************/
14930#define RCC_CSICFGR_CSICAL_Pos (0U)
14931#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos)
14932#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk
14933#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos)
14934#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos)
14935#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos)
14936#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos)
14937#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos)
14938#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos)
14939#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos)
14940#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos)
14943#define RCC_CSICFGR_CSITRIM_Pos (24U)
14944#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos)
14945#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk
14946#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos)
14947#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos)
14948#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos)
14949#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos)
14950#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos)
14951#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos)
14953/******************** Bit definition for RCC_CFGR register ******************/
14955#define RCC_CFGR_SW_Pos (0U)
14956#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos)
14957#define RCC_CFGR_SW RCC_CFGR_SW_Msk
14958#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
14959#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
14960#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos)
14962#define RCC_CFGR_SW_HSI (0x00000000UL)
14963#define RCC_CFGR_SW_CSI (0x00000001UL)
14964#define RCC_CFGR_SW_HSE (0x00000002UL)
14965#define RCC_CFGR_SW_PLL1 (0x00000003UL)
14968#define RCC_CFGR_SWS_Pos (3U)
14969#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos)
14970#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
14971#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
14972#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
14973#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos)
14975#define RCC_CFGR_SWS_HSI (0x00000000UL)
14976#define RCC_CFGR_SWS_CSI (0x00000008UL)
14977#define RCC_CFGR_SWS_HSE (0x00000010UL)
14978#define RCC_CFGR_SWS_PLL1 (0x00000018UL)
14980#define RCC_CFGR_STOPWUCK_Pos (6U)
14981#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)
14982#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk
14984#define RCC_CFGR_STOPKERWUCK_Pos (7U)
14985#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)
14986#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk
14989#define RCC_CFGR_RTCPRE_Pos (8U)
14990#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
14991#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
14992#define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos)
14993#define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos)
14994#define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos)
14995#define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos)
14996#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
14997#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos)
15001#define RCC_CFGR_TIMPRE_Pos (15U)
15002#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
15003#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk
15006#define RCC_CFGR_MCO1_Pos (22U)
15007#define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
15008#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
15009#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
15010#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
15011#define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos)
15013#define RCC_CFGR_MCO1PRE_Pos (18U)
15014#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
15015#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
15016#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
15017#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
15018#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
15019#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos)
15021#define RCC_CFGR_MCO2PRE_Pos (25U)
15022#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
15023#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
15024#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
15025#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
15026#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
15027#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos)
15029#define RCC_CFGR_MCO2_Pos (29U)
15030#define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
15031#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
15032#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
15033#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
15034#define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos)
15036/******************** Bit definition for RCC_D1CFGR register ******************/
15038#define RCC_D1CFGR_HPRE_Pos (0U)
15039#define RCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos)
15040#define RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk
15041#define RCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos)
15042#define RCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos)
15043#define RCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos)
15044#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos)
15047#define RCC_D1CFGR_HPRE_DIV1 (0U)
15048#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
15049#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos)
15050#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk
15051#define RCC_D1CFGR_HPRE_DIV4_Pos (0U)
15052#define RCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos)
15053#define RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk
15054#define RCC_D1CFGR_HPRE_DIV8_Pos (1U)
15055#define RCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos)
15056#define RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk
15057#define RCC_D1CFGR_HPRE_DIV16_Pos (0U)
15058#define RCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos)
15059#define RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk
15060#define RCC_D1CFGR_HPRE_DIV64_Pos (2U)
15061#define RCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos)
15062#define RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk
15063#define RCC_D1CFGR_HPRE_DIV128_Pos (0U)
15064#define RCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos)
15065#define RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk
15066#define RCC_D1CFGR_HPRE_DIV256_Pos (1U)
15067#define RCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos)
15068#define RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk
15069#define RCC_D1CFGR_HPRE_DIV512_Pos (0U)
15070#define RCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos)
15071#define RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk
15074#define RCC_D1CFGR_D1PPRE_Pos (4U)
15075#define RCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos)
15076#define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk
15077#define RCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos)
15078#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos)
15079#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos)
15081#define RCC_D1CFGR_D1PPRE_DIV1 (0U)
15082#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
15083#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos)
15084#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk
15085#define RCC_D1CFGR_D1PPRE_DIV4_Pos (4U)
15086#define RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos)
15087#define RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk
15088#define RCC_D1CFGR_D1PPRE_DIV8_Pos (5U)
15089#define RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos)
15090#define RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk
15091#define RCC_D1CFGR_D1PPRE_DIV16_Pos (4U)
15092#define RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos)
15093#define RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk
15095#define RCC_D1CFGR_D1CPRE_Pos (8U)
15096#define RCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos)
15097#define RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk
15098#define RCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos)
15099#define RCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos)
15100#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos)
15101#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos)
15103#define RCC_D1CFGR_D1CPRE_DIV1 (0U)
15104#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
15105#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos)
15106#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk
15107#define RCC_D1CFGR_D1CPRE_DIV4_Pos (8U)
15108#define RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos)
15109#define RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk
15110#define RCC_D1CFGR_D1CPRE_DIV8_Pos (9U)
15111#define RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos)
15112#define RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk
15113#define RCC_D1CFGR_D1CPRE_DIV16_Pos (8U)
15114#define RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos)
15115#define RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk
15116#define RCC_D1CFGR_D1CPRE_DIV64_Pos (10U)
15117#define RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos)
15118#define RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk
15119#define RCC_D1CFGR_D1CPRE_DIV128_Pos (8U)
15120#define RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos)
15121#define RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk
15122#define RCC_D1CFGR_D1CPRE_DIV256_Pos (9U)
15123#define RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos)
15124#define RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk
15125#define RCC_D1CFGR_D1CPRE_DIV512_Pos (8U)
15126#define RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos)
15127#define RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk
15129/******************** Bit definition for RCC_D2CFGR register ******************/
15131#define RCC_D2CFGR_D2PPRE1_Pos (4U)
15132#define RCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos)
15133#define RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk
15134#define RCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos)
15135#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos)
15136#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos)
15138#define RCC_D2CFGR_D2PPRE1_DIV1 (0U)
15139#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
15140#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos)
15141#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk
15142#define RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U)
15143#define RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos)
15144#define RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk
15145#define RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U)
15146#define RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos)
15147#define RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk
15148#define RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U)
15149#define RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos)
15150#define RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk
15153#define RCC_D2CFGR_D2PPRE2_Pos (8U)
15154#define RCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos)
15155#define RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk
15156#define RCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos)
15157#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos)
15158#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos)
15160#define RCC_D2CFGR_D2PPRE2_DIV1 (0U)
15161#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
15162#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos)
15163#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk
15164#define RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U)
15165#define RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos)
15166#define RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk
15167#define RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U)
15168#define RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos)
15169#define RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk
15170#define RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U)
15171#define RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos)
15172#define RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk
15174/******************** Bit definition for RCC_D3CFGR register ******************/
15176#define RCC_D3CFGR_D3PPRE_Pos (4U)
15177#define RCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos)
15178#define RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk
15179#define RCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos)
15180#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos)
15181#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos)
15183#define RCC_D3CFGR_D3PPRE_DIV1 (0U)
15184#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
15185#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos)
15186#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk
15187#define RCC_D3CFGR_D3PPRE_DIV4_Pos (4U)
15188#define RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos)
15189#define RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk
15190#define RCC_D3CFGR_D3PPRE_DIV8_Pos (5U)
15191#define RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos)
15192#define RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk
15193#define RCC_D3CFGR_D3PPRE_DIV16_Pos (4U)
15194#define RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos)
15195#define RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk
15197/******************** Bit definition for RCC_PLLCKSELR register *************/
15198
15199#define RCC_PLLCKSELR_PLLSRC_Pos (0U)
15200#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos)
15201#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
15202
15203#define RCC_PLLCKSELR_PLLSRC_HSI (0U)
15204#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
15205#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos)
15206#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk
15207#define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
15208#define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos)
15209#define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk
15210#define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
15211#define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos)
15212#define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk
15214#define RCC_PLLCKSELR_DIVM1_Pos (4U)
15215#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos)
15216#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
15217#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos)
15218#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos)
15219#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos)
15220#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos)
15221#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos)
15222#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos)
15224#define RCC_PLLCKSELR_DIVM2_Pos (12U)
15225#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos)
15226#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
15227#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos)
15228#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos)
15229#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos)
15230#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos)
15231#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos)
15232#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos)
15234#define RCC_PLLCKSELR_DIVM3_Pos (20U)
15235#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos)
15236#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
15237#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos)
15238#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos)
15239#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos)
15240#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos)
15241#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos)
15242#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos)
15244/******************** Bit definition for RCC_PLLCFGR register ***************/
15245
15246#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
15247#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos)
15248#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
15249#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
15250#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos)
15251#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
15252#define RCC_PLLCFGR_PLL1RGE_Pos (2U)
15253#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
15254#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
15255#define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos)
15256#define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos)
15257#define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos)
15258#define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
15260#define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
15261#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos)
15262#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
15263#define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
15264#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos)
15265#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
15266#define RCC_PLLCFGR_PLL2RGE_Pos (6U)
15267#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
15268#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
15269#define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos)
15270#define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos)
15271#define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos)
15272#define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
15274#define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
15275#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos)
15276#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
15277#define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
15278#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos)
15279#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
15280#define RCC_PLLCFGR_PLL3RGE_Pos (10U)
15281#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
15282#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
15283#define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos)
15284#define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos)
15285#define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos)
15286#define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
15288#define RCC_PLLCFGR_DIVP1EN_Pos (16U)
15289#define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos)
15290#define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
15291#define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
15292#define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos)
15293#define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
15294#define RCC_PLLCFGR_DIVR1EN_Pos (18U)
15295#define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos)
15296#define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
15297
15298#define RCC_PLLCFGR_DIVP2EN_Pos (19U)
15299#define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos)
15300#define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
15301#define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
15302#define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos)
15303#define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
15304#define RCC_PLLCFGR_DIVR2EN_Pos (21U)
15305#define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos)
15306#define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
15307
15308#define RCC_PLLCFGR_DIVP3EN_Pos (22U)
15309#define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos)
15310#define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
15311#define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
15312#define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos)
15313#define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
15314#define RCC_PLLCFGR_DIVR3EN_Pos (24U)
15315#define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos)
15316#define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
15317
15318
15319/******************** Bit definition for RCC_PLL1DIVR register ***************/
15320#define RCC_PLL1DIVR_N1_Pos (0U)
15321#define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos)
15322#define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
15323#define RCC_PLL1DIVR_P1_Pos (9U)
15324#define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos)
15325#define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
15326#define RCC_PLL1DIVR_Q1_Pos (16U)
15327#define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos)
15328#define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
15329#define RCC_PLL1DIVR_R1_Pos (24U)
15330#define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos)
15331#define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
15332
15333/******************** Bit definition for RCC_PLL1FRACR register ***************/
15334#define RCC_PLL1FRACR_FRACN1_Pos (3U)
15335#define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos)
15336#define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
15337
15338/******************** Bit definition for RCC_PLL2DIVR register ***************/
15339#define RCC_PLL2DIVR_N2_Pos (0U)
15340#define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos)
15341#define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
15342#define RCC_PLL2DIVR_P2_Pos (9U)
15343#define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos)
15344#define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
15345#define RCC_PLL2DIVR_Q2_Pos (16U)
15346#define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos)
15347#define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
15348#define RCC_PLL2DIVR_R2_Pos (24U)
15349#define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos)
15350#define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
15351
15352/******************** Bit definition for RCC_PLL2FRACR register ***************/
15353#define RCC_PLL2FRACR_FRACN2_Pos (3U)
15354#define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos)
15355#define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
15356
15357/******************** Bit definition for RCC_PLL3DIVR register ***************/
15358#define RCC_PLL3DIVR_N3_Pos (0U)
15359#define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos)
15360#define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
15361#define RCC_PLL3DIVR_P3_Pos (9U)
15362#define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos)
15363#define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
15364#define RCC_PLL3DIVR_Q3_Pos (16U)
15365#define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos)
15366#define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
15367#define RCC_PLL3DIVR_R3_Pos (24U)
15368#define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos)
15369#define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
15370
15371/******************** Bit definition for RCC_PLL3FRACR register ***************/
15372#define RCC_PLL3FRACR_FRACN3_Pos (3U)
15373#define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos)
15374#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
15375
15376/******************** Bit definition for RCC_D1CCIPR register ***************/
15377#define RCC_D1CCIPR_FMCSEL_Pos (0U)
15378#define RCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos)
15379#define RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk
15380#define RCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos)
15381#define RCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos)
15382#define RCC_D1CCIPR_OCTOSPISEL_Pos (4U)
15383#define RCC_D1CCIPR_OCTOSPISEL_Msk (0x3UL << RCC_D1CCIPR_OCTOSPISEL_Pos)
15384#define RCC_D1CCIPR_OCTOSPISEL RCC_D1CCIPR_OCTOSPISEL_Msk
15385#define RCC_D1CCIPR_OCTOSPISEL_0 (0x1UL << RCC_D1CCIPR_OCTOSPISEL_Pos)
15386#define RCC_D1CCIPR_OCTOSPISEL_1 (0x2UL << RCC_D1CCIPR_OCTOSPISEL_Pos)
15387#define RCC_D1CCIPR_SDMMCSEL_Pos (16U)
15388#define RCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos)
15389#define RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk
15390#define RCC_D1CCIPR_CKPERSEL_Pos (28U)
15391#define RCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos)
15392#define RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk
15393#define RCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos)
15394#define RCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos)
15396/******************** Bit definition for RCC_D2CCIP1R register ***************/
15397#define RCC_D2CCIP1R_SAI1SEL_Pos (0U)
15398#define RCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos)
15399#define RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk
15400#define RCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos)
15401#define RCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos)
15402#define RCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos)
15405#define RCC_D2CCIP1R_SPI123SEL_Pos (12U)
15406#define RCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos)
15407#define RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk
15408#define RCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos)
15409#define RCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos)
15410#define RCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos)
15412#define RCC_D2CCIP1R_SPI45SEL_Pos (16U)
15413#define RCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos)
15414#define RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk
15415#define RCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos)
15416#define RCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos)
15417#define RCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos)
15419#define RCC_D2CCIP1R_SPDIFSEL_Pos (20U)
15420#define RCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
15421#define RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk
15422#define RCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
15423#define RCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
15425#define RCC_D2CCIP1R_DFSDM1SEL_Pos (24U)
15426#define RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos)
15427#define RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk
15428
15429#define RCC_D2CCIP1R_FDCANSEL_Pos (28U)
15430#define RCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos)
15431#define RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk
15432#define RCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos)
15433#define RCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos)
15435#define RCC_D2CCIP1R_SWPSEL_Pos (31U)
15436#define RCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos)
15437#define RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk
15438
15439/******************** Bit definition for RCC_D2CCIP2R register ***************/
15440#define RCC_D2CCIP2R_USART16910SEL_Pos (3U)
15441#define RCC_D2CCIP2R_USART16910SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16910SEL_Pos)
15442#define RCC_D2CCIP2R_USART16910SEL RCC_D2CCIP2R_USART16910SEL_Msk
15443#define RCC_D2CCIP2R_USART16910SEL_0 (0x1UL << RCC_D2CCIP2R_USART16910SEL_Pos)
15444#define RCC_D2CCIP2R_USART16910SEL_1 (0x2UL << RCC_D2CCIP2R_USART16910SEL_Pos)
15445#define RCC_D2CCIP2R_USART16910SEL_2 (0x4UL << RCC_D2CCIP2R_USART16910SEL_Pos)
15447#define RCC_D2CCIP2R_USART28SEL_Pos (0U)
15448#define RCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos)
15449#define RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk
15450#define RCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos)
15451#define RCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos)
15452#define RCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos)
15454#define RCC_D2CCIP2R_RNGSEL_Pos (8U)
15455#define RCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos)
15456#define RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk
15457#define RCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos)
15458#define RCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos)
15460#define RCC_D2CCIP2R_I2C1235SEL_Pos (12U)
15461#define RCC_D2CCIP2R_I2C1235SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C1235SEL_Pos)
15462#define RCC_D2CCIP2R_I2C1235SEL RCC_D2CCIP2R_I2C1235SEL_Msk
15463#define RCC_D2CCIP2R_I2C1235SEL_0 (0x1UL << RCC_D2CCIP2R_I2C1235SEL_Pos)
15464#define RCC_D2CCIP2R_I2C1235SEL_1 (0x2UL << RCC_D2CCIP2R_I2C1235SEL_Pos)
15466#define RCC_D2CCIP2R_USBSEL_Pos (20U)
15467#define RCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos)
15468#define RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk
15469#define RCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos)
15470#define RCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos)
15472#define RCC_D2CCIP2R_CECSEL_Pos (22U)
15473#define RCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos)
15474#define RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk
15475#define RCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos)
15476#define RCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos)
15478#define RCC_D2CCIP2R_LPTIM1SEL_Pos (28U)
15479#define RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
15480#define RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk
15481#define RCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
15482#define RCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
15483#define RCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
15485/******************** Bit definition for RCC_D3CCIPR register ***************/
15486#define RCC_D3CCIPR_LPUART1SEL_Pos (0U)
15487#define RCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos)
15488#define RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk
15489#define RCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos)
15490#define RCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos)
15491#define RCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos)
15493#define RCC_D3CCIPR_I2C4SEL_Pos (8U)
15494#define RCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos)
15495#define RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk
15496#define RCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos)
15497#define RCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos)
15499#define RCC_D3CCIPR_LPTIM2SEL_Pos (10U)
15500#define RCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
15501#define RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk
15502#define RCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
15503#define RCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
15504#define RCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
15506#define RCC_D3CCIPR_LPTIM345SEL_Pos (13U)
15507#define RCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
15508#define RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk
15509#define RCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
15510#define RCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
15511#define RCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
15513#define RCC_D3CCIPR_SAI4ASEL_Pos (21U)
15514#define RCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos)
15515#define RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk
15516#define RCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos)
15517#define RCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos)
15518#define RCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos)
15520#define RCC_D3CCIPR_SAI4BSEL_Pos (24U)
15521#define RCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos)
15522#define RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk
15523#define RCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos)
15524#define RCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos)
15525#define RCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos)
15527#define RCC_D3CCIPR_ADCSEL_Pos (16U)
15528#define RCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos)
15529#define RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk
15530#define RCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos)
15531#define RCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos)
15533#define RCC_D3CCIPR_SPI6SEL_Pos (28U)
15534#define RCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos)
15535#define RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk
15536#define RCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos)
15537#define RCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos)
15538#define RCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos)
15539/******************** Bit definition for RCC_CIER register ******************/
15540#define RCC_CIER_LSIRDYIE_Pos (0U)
15541#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)
15542#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
15543#define RCC_CIER_LSERDYIE_Pos (1U)
15544#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)
15545#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
15546#define RCC_CIER_HSIRDYIE_Pos (2U)
15547#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)
15548#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
15549#define RCC_CIER_HSERDYIE_Pos (3U)
15550#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)
15551#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
15552#define RCC_CIER_CSIRDYIE_Pos (4U)
15553#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos)
15554#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
15555#define RCC_CIER_HSI48RDYIE_Pos (5U)
15556#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)
15557#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
15558#define RCC_CIER_PLL1RDYIE_Pos (6U)
15559#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos)
15560#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
15561#define RCC_CIER_PLL2RDYIE_Pos (7U)
15562#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos)
15563#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
15564#define RCC_CIER_PLL3RDYIE_Pos (8U)
15565#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos)
15566#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
15567#define RCC_CIER_LSECSSIE_Pos (9U)
15568#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)
15569#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
15570
15571/******************** Bit definition for RCC_CIFR register ******************/
15572#define RCC_CIFR_LSIRDYF_Pos (0U)
15573#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)
15574#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
15575#define RCC_CIFR_LSERDYF_Pos (1U)
15576#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)
15577#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
15578#define RCC_CIFR_HSIRDYF_Pos (2U)
15579#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)
15580#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
15581#define RCC_CIFR_HSERDYF_Pos (3U)
15582#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)
15583#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
15584#define RCC_CIFR_CSIRDYF_Pos (4U)
15585#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos)
15586#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
15587#define RCC_CIFR_HSI48RDYF_Pos (5U)
15588#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos)
15589#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
15590#define RCC_CIFR_PLLRDYF_Pos (6U)
15591#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)
15592#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
15593#define RCC_CIFR_PLL2RDYF_Pos (7U)
15594#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos)
15595#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
15596#define RCC_CIFR_PLL3RDYF_Pos (8U)
15597#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos)
15598#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
15599#define RCC_CIFR_LSECSSF_Pos (9U)
15600#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)
15601#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
15602#define RCC_CIFR_HSECSSF_Pos (10U)
15603#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos)
15604#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
15605
15606/******************** Bit definition for RCC_CICR register ******************/
15607#define RCC_CICR_LSIRDYC_Pos (0U)
15608#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)
15609#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
15610#define RCC_CICR_LSERDYC_Pos (1U)
15611#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)
15612#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
15613#define RCC_CICR_HSIRDYC_Pos (2U)
15614#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)
15615#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
15616#define RCC_CICR_HSERDYC_Pos (3U)
15617#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)
15618#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
15619#define RCC_CICR_CSIRDYC_Pos (4U)
15620#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos)
15621#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
15622#define RCC_CICR_HSI48RDYC_Pos (5U)
15623#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos)
15624#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
15625#define RCC_CICR_PLLRDYC_Pos (6U)
15626#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)
15627#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
15628#define RCC_CICR_PLL2RDYC_Pos (7U)
15629#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos)
15630#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
15631#define RCC_CICR_PLL3RDYC_Pos (8U)
15632#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos)
15633#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
15634#define RCC_CICR_LSECSSC_Pos (9U)
15635#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)
15636#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
15637#define RCC_CICR_HSECSSC_Pos (10U)
15638#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos)
15639#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
15640
15641/******************** Bit definition for RCC_BDCR register ******************/
15642#define RCC_BDCR_LSEON_Pos (0U)
15643#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
15644#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
15645#define RCC_BDCR_LSERDY_Pos (1U)
15646#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
15647#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
15648#define RCC_BDCR_LSEBYP_Pos (2U)
15649#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
15650#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
15651
15652#define RCC_BDCR_LSEDRV_Pos (3U)
15653#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
15654#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
15655#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
15656#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
15658#define RCC_BDCR_LSECSSON_Pos (5U)
15659#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)
15660#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
15661#define RCC_BDCR_LSECSSD_Pos (6U)
15662#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)
15663#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
15664
15665#define RCC_BDCR_RTCSEL_Pos (8U)
15666#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
15667#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
15668#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
15669#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
15671#define RCC_BDCR_RTCEN_Pos (15U)
15672#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
15673#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
15674#define RCC_BDCR_VSWRST_Pos (16U)
15675#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos)
15676#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk
15677/* Legacy define */
15678#define RCC_BDCR_BDRST_Pos RCC_BDCR_VSWRST_Pos
15679#define RCC_BDCR_BDRST_Msk RCC_BDCR_VSWRST_Msk
15680#define RCC_BDCR_BDRST RCC_BDCR_VSWRST
15681/******************** Bit definition for RCC_CSR register *******************/
15682#define RCC_CSR_LSION_Pos (0U)
15683#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
15684#define RCC_CSR_LSION RCC_CSR_LSION_Msk
15685#define RCC_CSR_LSIRDY_Pos (1U)
15686#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
15687#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
15688
15689
15690/******************** Bit definition for RCC_AHB3ENR register **************/
15691#define RCC_AHB3ENR_MDMAEN_Pos (0U)
15692#define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)
15693#define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
15694#define RCC_AHB3ENR_DMA2DEN_Pos (4U)
15695#define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)
15696#define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
15697#define RCC_AHB3ENR_FMCEN_Pos (12U)
15698#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
15699#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
15700#define RCC_AHB3ENR_OSPI1EN_Pos (14U)
15701#define RCC_AHB3ENR_OSPI1EN_Msk (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)
15702#define RCC_AHB3ENR_OSPI1EN RCC_AHB3ENR_OSPI1EN_Msk
15703#define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
15704#define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)
15705#define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
15706#define RCC_AHB3ENR_OSPI2EN_Pos (19U)
15707#define RCC_AHB3ENR_OSPI2EN_Msk (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)
15708#define RCC_AHB3ENR_OSPI2EN RCC_AHB3ENR_OSPI2EN_Msk
15709#define RCC_AHB3ENR_IOMNGREN_Pos (21U)
15710#define RCC_AHB3ENR_IOMNGREN_Msk (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)
15711#define RCC_AHB3ENR_IOMNGREN RCC_AHB3ENR_IOMNGREN_Msk
15712#define RCC_AHB3ENR_OTFDEC1EN_Pos (22U)
15713#define RCC_AHB3ENR_OTFDEC1EN_Msk (0x1UL << RCC_AHB3ENR_OTFDEC1EN_Pos)
15714#define RCC_AHB3ENR_OTFDEC1EN RCC_AHB3ENR_OTFDEC1EN_Msk
15715#define RCC_AHB3ENR_OTFDEC2EN_Pos (23U)
15716#define RCC_AHB3ENR_OTFDEC2EN_Msk (0x1UL << RCC_AHB3ENR_OTFDEC2EN_Pos)
15717#define RCC_AHB3ENR_OTFDEC2EN RCC_AHB3ENR_OTFDEC2EN_Msk
15718
15719/******************** Bit definition for RCC_AHB1ENR register ***************/
15720#define RCC_AHB1ENR_DMA1EN_Pos (0U)
15721#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
15722#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
15723#define RCC_AHB1ENR_DMA2EN_Pos (1U)
15724#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
15725#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
15726#define RCC_AHB1ENR_ADC12EN_Pos (5U)
15727#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)
15728#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
15729#define RCC_AHB1ENR_ETH1MACEN_Pos (15U)
15730#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)
15731#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk
15732#define RCC_AHB1ENR_ETH1TXEN_Pos (16U)
15733#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)
15734#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk
15735#define RCC_AHB1ENR_ETH1RXEN_Pos (17U)
15736#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)
15737#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk
15738#define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
15739#define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)
15740#define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
15741#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
15742#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos)
15743#define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
15744
15745/******************** Bit definition for RCC_AHB2ENR register ***************/
15746#define RCC_AHB2ENR_DCMI_PSSIEN_Pos (0U)
15747#define RCC_AHB2ENR_DCMI_PSSIEN_Msk (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)
15748#define RCC_AHB2ENR_DCMI_PSSIEN RCC_AHB2ENR_DCMI_PSSIEN_Msk
15749#define RCC_AHB2ENR_CRYPEN_Pos (4U)
15750#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)
15751#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
15752#define RCC_AHB2ENR_HASHEN_Pos (5U)
15753#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos)
15754#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
15755#define RCC_AHB2ENR_RNGEN_Pos (6U)
15756#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
15757#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
15758#define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
15759#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)
15760#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
15761#define RCC_AHB2ENR_FMACEN_Pos (16U)
15762#define RCC_AHB2ENR_FMACEN_Msk (0x1UL << RCC_AHB2ENR_FMACEN_Pos)
15763#define RCC_AHB2ENR_FMACEN RCC_AHB2ENR_FMACEN_Msk
15764#define RCC_AHB2ENR_CORDICEN_Pos (17U)
15765#define RCC_AHB2ENR_CORDICEN_Msk (0x1UL << RCC_AHB2ENR_CORDICEN_Pos)
15766#define RCC_AHB2ENR_CORDICEN RCC_AHB2ENR_CORDICEN_Msk
15767#define RCC_AHB2ENR_SRAM1EN_Pos (29U)
15768#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)
15769#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk
15770#define RCC_AHB2ENR_SRAM2EN_Pos (30U)
15771#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)
15772#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk
15773
15774/* Legacy define */
15775#define RCC_AHB2ENR_DCMIEN_Pos RCC_AHB2ENR_DCMI_PSSIEN_Pos
15776#define RCC_AHB2ENR_DCMIEN_Msk RCC_AHB2ENR_DCMI_PSSIEN_Msk
15777#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMI_PSSIEN
15778/* Legacy define */
15779#define RCC_AHB2ENR_D2SRAM1EN_Pos RCC_AHB2ENR_SRAM1EN_Pos
15780#define RCC_AHB2ENR_D2SRAM1EN_Msk RCC_AHB2ENR_SRAM1EN_Msk
15781#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_SRAM1EN
15782#define RCC_AHB2ENR_D2SRAM2EN_Pos RCC_AHB2ENR_SRAM2EN_Pos
15783#define RCC_AHB2ENR_D2SRAM2EN_Msk RCC_AHB2ENR_SRAM2EN_Msk
15784#define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_SRAM2EN
15785
15786/******************** Bit definition for RCC_AHB4ENR register ******************/
15787#define RCC_AHB4ENR_GPIOAEN_Pos (0U)
15788#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)
15789#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
15790#define RCC_AHB4ENR_GPIOBEN_Pos (1U)
15791#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)
15792#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
15793#define RCC_AHB4ENR_GPIOCEN_Pos (2U)
15794#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)
15795#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
15796#define RCC_AHB4ENR_GPIODEN_Pos (3U)
15797#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)
15798#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
15799#define RCC_AHB4ENR_GPIOEEN_Pos (4U)
15800#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)
15801#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
15802#define RCC_AHB4ENR_GPIOFEN_Pos (5U)
15803#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)
15804#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
15805#define RCC_AHB4ENR_GPIOGEN_Pos (6U)
15806#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)
15807#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
15808#define RCC_AHB4ENR_GPIOHEN_Pos (7U)
15809#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)
15810#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
15811#define RCC_AHB4ENR_GPIOJEN_Pos (9U)
15812#define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)
15813#define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
15814#define RCC_AHB4ENR_GPIOKEN_Pos (10U)
15815#define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)
15816#define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
15817#define RCC_AHB4ENR_CRCEN_Pos (19U)
15818#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos)
15819#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk
15820#define RCC_AHB4ENR_BDMAEN_Pos (21U)
15821#define RCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)
15822#define RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk
15823#define RCC_AHB4ENR_ADC3EN_Pos (24U)
15824#define RCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)
15825#define RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk
15826#define RCC_AHB4ENR_HSEMEN_Pos (25U)
15827#define RCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)
15828#define RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk
15829#define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
15830#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)
15831#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
15832
15833/******************** Bit definition for RCC_APB3ENR register ******************/
15834#define RCC_APB3ENR_LTDCEN_Pos (3U)
15835#define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos)
15836#define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
15837#define RCC_APB3ENR_WWDG1EN_Pos (6U)
15838#define RCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos)
15839#define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk
15840
15841/******************** Bit definition for RCC_APB1LENR register ******************/
15842
15843#define RCC_APB1LENR_TIM2EN_Pos (0U)
15844#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos)
15845#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
15846#define RCC_APB1LENR_TIM3EN_Pos (1U)
15847#define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos)
15848#define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
15849#define RCC_APB1LENR_TIM4EN_Pos (2U)
15850#define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos)
15851#define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
15852#define RCC_APB1LENR_TIM5EN_Pos (3U)
15853#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos)
15854#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
15855#define RCC_APB1LENR_TIM6EN_Pos (4U)
15856#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos)
15857#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
15858#define RCC_APB1LENR_TIM7EN_Pos (5U)
15859#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos)
15860#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
15861#define RCC_APB1LENR_TIM12EN_Pos (6U)
15862#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos)
15863#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
15864#define RCC_APB1LENR_TIM13EN_Pos (7U)
15865#define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos)
15866#define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
15867#define RCC_APB1LENR_TIM14EN_Pos (8U)
15868#define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos)
15869#define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
15870#define RCC_APB1LENR_LPTIM1EN_Pos (9U)
15871#define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos)
15872#define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
15873
15874
15875#define RCC_APB1LENR_SPI2EN_Pos (14U)
15876#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos)
15877#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
15878#define RCC_APB1LENR_SPI3EN_Pos (15U)
15879#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos)
15880#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
15881#define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
15882#define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos)
15883#define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
15884#define RCC_APB1LENR_USART2EN_Pos (17U)
15885#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos)
15886#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
15887#define RCC_APB1LENR_USART3EN_Pos (18U)
15888#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos)
15889#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
15890#define RCC_APB1LENR_UART4EN_Pos (19U)
15891#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos)
15892#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
15893#define RCC_APB1LENR_UART5EN_Pos (20U)
15894#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos)
15895#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
15896#define RCC_APB1LENR_I2C1EN_Pos (21U)
15897#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos)
15898#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
15899#define RCC_APB1LENR_I2C2EN_Pos (22U)
15900#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos)
15901#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
15902#define RCC_APB1LENR_I2C3EN_Pos (23U)
15903#define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos)
15904#define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
15905#define RCC_APB1LENR_I2C5EN_Pos (25U)
15906#define RCC_APB1LENR_I2C5EN_Msk (0x1UL << RCC_APB1LENR_I2C5EN_Pos)
15907#define RCC_APB1LENR_I2C5EN RCC_APB1LENR_I2C5EN_Msk
15908#define RCC_APB1LENR_CECEN_Pos (27U)
15909#define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos)
15910#define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
15911#define RCC_APB1LENR_DAC12EN_Pos (29U)
15912#define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos)
15913#define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
15914#define RCC_APB1LENR_UART7EN_Pos (30U)
15915#define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos)
15916#define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
15917#define RCC_APB1LENR_UART8EN_Pos (31U)
15918#define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos)
15919#define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
15920
15921/* Legacy define */
15922#define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
15923#define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
15924#define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
15925/******************** Bit definition for RCC_APB1HENR register ******************/
15926#define RCC_APB1HENR_CRSEN_Pos (1U)
15927#define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos)
15928#define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
15929#define RCC_APB1HENR_SWPMIEN_Pos (2U)
15930#define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos)
15931#define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
15932#define RCC_APB1HENR_OPAMPEN_Pos (4U)
15933#define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos)
15934#define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
15935#define RCC_APB1HENR_MDIOSEN_Pos (5U)
15936#define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos)
15937#define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
15938#define RCC_APB1HENR_FDCANEN_Pos (8U)
15939#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos)
15940#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
15941#define RCC_APB1HENR_TIM23EN_Pos (24U)
15942#define RCC_APB1HENR_TIM23EN_Msk (0x1UL << RCC_APB1HENR_TIM23EN_Pos)
15943#define RCC_APB1HENR_TIM23EN RCC_APB1HENR_TIM23EN_Msk
15944#define RCC_APB1HENR_TIM24EN_Pos (25U)
15945#define RCC_APB1HENR_TIM24EN_Msk (0x1UL << RCC_APB1HENR_TIM24EN_Pos)
15946#define RCC_APB1HENR_TIM24EN RCC_APB1HENR_TIM24EN_Msk
15947
15948/******************** Bit definition for RCC_APB2ENR register ******************/
15949#define RCC_APB2ENR_TIM1EN_Pos (0U)
15950#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
15951#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
15952#define RCC_APB2ENR_TIM8EN_Pos (1U)
15953#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
15954#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
15955#define RCC_APB2ENR_USART1EN_Pos (4U)
15956#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
15957#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
15958#define RCC_APB2ENR_USART6EN_Pos (5U)
15959#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
15960#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
15961#define RCC_APB2ENR_UART9EN_Pos (6U)
15962#define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos)
15963#define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk
15964#define RCC_APB2ENR_USART10EN_Pos (7U)
15965#define RCC_APB2ENR_USART10EN_Msk (0x1UL << RCC_APB2ENR_USART10EN_Pos)
15966#define RCC_APB2ENR_USART10EN RCC_APB2ENR_USART10EN_Msk
15967#define RCC_APB2ENR_SPI1EN_Pos (12U)
15968#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
15969#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
15970#define RCC_APB2ENR_SPI4EN_Pos (13U)
15971#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
15972#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
15973#define RCC_APB2ENR_TIM15EN_Pos (16U)
15974#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
15975#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
15976#define RCC_APB2ENR_TIM16EN_Pos (17U)
15977#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
15978#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
15979#define RCC_APB2ENR_TIM17EN_Pos (18U)
15980#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
15981#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
15982#define RCC_APB2ENR_SPI5EN_Pos (20U)
15983#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
15984#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
15985#define RCC_APB2ENR_SAI1EN_Pos (22U)
15986#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
15987#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
15988#define RCC_APB2ENR_DFSDM1EN_Pos (30U)
15989#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
15990#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
15991
15992/******************** Bit definition for RCC_APB4ENR register ******************/
15993#define RCC_APB4ENR_SYSCFGEN_Pos (1U)
15994#define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos)
15995#define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
15996#define RCC_APB4ENR_LPUART1EN_Pos (3U)
15997#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos)
15998#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
15999#define RCC_APB4ENR_SPI6EN_Pos (5U)
16000#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos)
16001#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
16002#define RCC_APB4ENR_I2C4EN_Pos (7U)
16003#define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos)
16004#define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
16005#define RCC_APB4ENR_LPTIM2EN_Pos (9U)
16006#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos)
16007#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
16008#define RCC_APB4ENR_LPTIM3EN_Pos (10U)
16009#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos)
16010#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
16011#define RCC_APB4ENR_LPTIM4EN_Pos (11U)
16012#define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos)
16013#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk
16014#define RCC_APB4ENR_LPTIM5EN_Pos (12U)
16015#define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos)
16016#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk
16017#define RCC_APB4ENR_COMP12EN_Pos (14U)
16018#define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos)
16019#define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
16020#define RCC_APB4ENR_VREFEN_Pos (15U)
16021#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos)
16022#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
16023#define RCC_APB4ENR_RTCAPBEN_Pos (16U)
16024#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos)
16025#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
16026#define RCC_APB4ENR_SAI4EN_Pos (21U)
16027#define RCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos)
16028#define RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk
16029
16030#define RCC_APB4ENR_DTSEN_Pos (26U)
16031#define RCC_APB4ENR_DTSEN_Msk (0x1UL << RCC_APB4ENR_DTSEN_Pos)
16032#define RCC_APB4ENR_DTSEN RCC_APB4ENR_DTSEN_Msk
16033
16034/******************** Bit definition for RCC_AHB3RSTR register ***************/
16035#define RCC_AHB3RSTR_MDMARST_Pos (0U)
16036#define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)
16037#define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
16038#define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
16039#define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)
16040#define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
16041#define RCC_AHB3RSTR_FMCRST_Pos (12U)
16042#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
16043#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
16044#define RCC_AHB3RSTR_OSPI1RST_Pos (14U)
16045#define RCC_AHB3RSTR_OSPI1RST_Msk (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)
16046#define RCC_AHB3RSTR_OSPI1RST RCC_AHB3RSTR_OSPI1RST_Msk
16047#define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
16048#define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)
16049#define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
16050#define RCC_AHB3RSTR_OSPI2RST_Pos (19U)
16051#define RCC_AHB3RSTR_OSPI2RST_Msk (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)
16052#define RCC_AHB3RSTR_OSPI2RST RCC_AHB3RSTR_OSPI2RST_Msk
16053#define RCC_AHB3RSTR_IOMNGRRST_Pos (21U)
16054#define RCC_AHB3RSTR_IOMNGRRST_Msk (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)
16055#define RCC_AHB3RSTR_IOMNGRRST RCC_AHB3RSTR_IOMNGRRST_Msk
16056#define RCC_AHB3RSTR_OTFDEC1RST_Pos (22U)
16057#define RCC_AHB3RSTR_OTFDEC1RST_Msk (0x1UL << RCC_AHB3RSTR_OTFDEC1RST_Pos)
16058#define RCC_AHB3RSTR_OTFDEC1RST RCC_AHB3RSTR_OTFDEC1RST_Msk
16059#define RCC_AHB3RSTR_OTFDEC2RST_Pos (23U)
16060#define RCC_AHB3RSTR_OTFDEC2RST_Msk (0x1UL << RCC_AHB3RSTR_OTFDEC2RST_Pos)
16061#define RCC_AHB3RSTR_OTFDEC2RST RCC_AHB3RSTR_OTFDEC2RST_Msk
16062#define RCC_AHB3RSTR_CPURST_Pos (31U)
16063#define RCC_AHB3RSTR_CPURST_Msk (0x1UL << RCC_AHB3RSTR_CPURST_Pos)
16064#define RCC_AHB3RSTR_CPURST RCC_AHB3RSTR_CPURST_Msk
16065
16066
16067/******************** Bit definition for RCC_AHB1RSTR register ***************/
16068#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
16069#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
16070#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
16071#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
16072#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
16073#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
16074#define RCC_AHB1RSTR_ADC12RST_Pos (5U)
16075#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)
16076#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
16077#define RCC_AHB1RSTR_ETH1MACRST_Pos (15U)
16078#define RCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)
16079#define RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk
16080#define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
16081#define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos)
16082#define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
16083
16084/******************** Bit definition for RCC_AHB2RSTR register ***************/
16085#define RCC_AHB2RSTR_DCMI_PSSIRST_Pos (0U)
16086#define RCC_AHB2RSTR_DCMI_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)
16087#define RCC_AHB2RSTR_DCMI_PSSIRST RCC_AHB2RSTR_DCMI_PSSIRST_Msk
16088#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
16089#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)
16090#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
16091#define RCC_AHB2RSTR_HASHRST_Pos (5U)
16092#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)
16093#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
16094#define RCC_AHB2RSTR_RNGRST_Pos (6U)
16095#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
16096#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
16097#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
16098#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)
16099#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
16100#define RCC_AHB2RSTR_FMACRST_Pos (16U)
16101#define RCC_AHB2RSTR_FMACRST_Msk (0x1UL << RCC_AHB2RSTR_FMACRST_Pos)
16102#define RCC_AHB2RSTR_FMACRST RCC_AHB2RSTR_FMACRST_Msk
16103#define RCC_AHB2RSTR_CORDICRST_Pos (17U)
16104#define RCC_AHB2RSTR_CORDICRST_Msk (0x1UL << RCC_AHB2RSTR_CORDICRST_Pos)
16105#define RCC_AHB2RSTR_CORDICRST RCC_AHB2RSTR_CORDICRST_Msk
16106
16107/* Legacy define */
16108#define RCC_AHB2RSTR_DCMIRST_Pos RCC_AHB2RSTR_DCMI_PSSIRST_Pos
16109#define RCC_AHB2RSTR_DCMIRST_Msk RCC_AHB2RSTR_DCMI_PSSIRST_Msk
16110#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMI_PSSIRST
16111/******************** Bit definition for RCC_AHB4RSTR register ******************/
16112#define RCC_AHB4RSTR_GPIOARST_Pos (0U)
16113#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)
16114#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
16115#define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
16116#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)
16117#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
16118#define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
16119#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)
16120#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
16121#define RCC_AHB4RSTR_GPIODRST_Pos (3U)
16122#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)
16123#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
16124#define RCC_AHB4RSTR_GPIOERST_Pos (4U)
16125#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)
16126#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
16127#define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
16128#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)
16129#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
16130#define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
16131#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)
16132#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
16133#define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
16134#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)
16135#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
16136#define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
16137#define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)
16138#define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
16139#define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
16140#define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)
16141#define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
16142#define RCC_AHB4RSTR_CRCRST_Pos (19U)
16143#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)
16144#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk
16145#define RCC_AHB4RSTR_BDMARST_Pos (21U)
16146#define RCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)
16147#define RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk
16148#define RCC_AHB4RSTR_ADC3RST_Pos (24U)
16149#define RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)
16150#define RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk
16151#define RCC_AHB4RSTR_HSEMRST_Pos (25U)
16152#define RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)
16153#define RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk
16154
16155
16156/******************** Bit definition for RCC_APB3RSTR register ******************/
16157#define RCC_APB3RSTR_LTDCRST_Pos (3U)
16158#define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos)
16159#define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
16160
16161/******************** Bit definition for RCC_APB1LRSTR register ******************/
16162
16163#define RCC_APB1LRSTR_TIM2RST_Pos (0U)
16164#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos)
16165#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
16166#define RCC_APB1LRSTR_TIM3RST_Pos (1U)
16167#define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos)
16168#define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
16169#define RCC_APB1LRSTR_TIM4RST_Pos (2U)
16170#define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos)
16171#define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
16172#define RCC_APB1LRSTR_TIM5RST_Pos (3U)
16173#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos)
16174#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
16175#define RCC_APB1LRSTR_TIM6RST_Pos (4U)
16176#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos)
16177#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
16178#define RCC_APB1LRSTR_TIM7RST_Pos (5U)
16179#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos)
16180#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
16181#define RCC_APB1LRSTR_TIM12RST_Pos (6U)
16182#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos)
16183#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
16184#define RCC_APB1LRSTR_TIM13RST_Pos (7U)
16185#define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos)
16186#define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
16187#define RCC_APB1LRSTR_TIM14RST_Pos (8U)
16188#define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos)
16189#define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
16190#define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
16191#define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos)
16192#define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
16193#define RCC_APB1LRSTR_SPI2RST_Pos (14U)
16194#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos)
16195#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
16196#define RCC_APB1LRSTR_SPI3RST_Pos (15U)
16197#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos)
16198#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
16199#define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
16200#define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos)
16201#define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
16202#define RCC_APB1LRSTR_USART2RST_Pos (17U)
16203#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos)
16204#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
16205#define RCC_APB1LRSTR_USART3RST_Pos (18U)
16206#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos)
16207#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
16208#define RCC_APB1LRSTR_UART4RST_Pos (19U)
16209#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos)
16210#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
16211#define RCC_APB1LRSTR_UART5RST_Pos (20U)
16212#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos)
16213#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
16214#define RCC_APB1LRSTR_I2C1RST_Pos (21U)
16215#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos)
16216#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
16217#define RCC_APB1LRSTR_I2C2RST_Pos (22U)
16218#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos)
16219#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
16220#define RCC_APB1LRSTR_I2C3RST_Pos (23U)
16221#define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos)
16222#define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
16223#define RCC_APB1LRSTR_I2C5RST_Pos (25U)
16224#define RCC_APB1LRSTR_I2C5RST_Msk (0x1UL << RCC_APB1LRSTR_I2C5RST_Pos)
16225#define RCC_APB1LRSTR_I2C5RST RCC_APB1LRSTR_I2C5RST_Msk
16226#define RCC_APB1LRSTR_CECRST_Pos (27U)
16227#define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos)
16228#define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
16229#define RCC_APB1LRSTR_DAC12RST_Pos (29U)
16230#define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos)
16231#define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
16232#define RCC_APB1LRSTR_UART7RST_Pos (30U)
16233#define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos)
16234#define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
16235#define RCC_APB1LRSTR_UART8RST_Pos (31U)
16236#define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos)
16237#define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
16238
16239/* Legacy define */
16240#define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
16241#define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
16242#define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
16243/******************** Bit definition for RCC_APB1HRSTR register ******************/
16244#define RCC_APB1HRSTR_CRSRST_Pos (1U)
16245#define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos)
16246#define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
16247#define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
16248#define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos)
16249#define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
16250#define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
16251#define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos)
16252#define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
16253#define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
16254#define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos)
16255#define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
16256#define RCC_APB1HRSTR_FDCANRST_Pos (8U)
16257#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos)
16258#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
16259#define RCC_APB1HRSTR_TIM23RST_Pos (24U)
16260#define RCC_APB1HRSTR_TIM23RST_Msk (0x1UL << RCC_APB1HRSTR_TIM23RST_Pos)
16261#define RCC_APB1HRSTR_TIM23RST RCC_APB1HRSTR_TIM23RST_Msk
16262#define RCC_APB1HRSTR_TIM24RST_Pos (25U)
16263#define RCC_APB1HRSTR_TIM24RST_Msk (0x1UL << RCC_APB1HRSTR_TIM24RST_Pos)
16264#define RCC_APB1HRSTR_TIM24RST RCC_APB1HRSTR_TIM24RST_Msk
16265
16266/******************** Bit definition for RCC_APB2RSTR register ******************/
16267#define RCC_APB2RSTR_TIM1RST_Pos (0U)
16268#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
16269#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
16270#define RCC_APB2RSTR_TIM8RST_Pos (1U)
16271#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
16272#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
16273#define RCC_APB2RSTR_USART1RST_Pos (4U)
16274#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
16275#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
16276#define RCC_APB2RSTR_USART6RST_Pos (5U)
16277#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
16278#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
16279#define RCC_APB2RSTR_UART9RST_Pos (6U)
16280#define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos)
16281#define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk
16282#define RCC_APB2RSTR_USART10RST_Pos (7U)
16283#define RCC_APB2RSTR_USART10RST_Msk (0x1UL << RCC_APB2RSTR_USART10RST_Pos)
16284#define RCC_APB2RSTR_USART10RST RCC_APB2RSTR_USART10RST_Msk
16285#define RCC_APB2RSTR_SPI1RST_Pos (12U)
16286#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
16287#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
16288#define RCC_APB2RSTR_SPI4RST_Pos (13U)
16289#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
16290#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
16291#define RCC_APB2RSTR_TIM15RST_Pos (16U)
16292#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
16293#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
16294#define RCC_APB2RSTR_TIM16RST_Pos (17U)
16295#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
16296#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
16297#define RCC_APB2RSTR_TIM17RST_Pos (18U)
16298#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
16299#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
16300#define RCC_APB2RSTR_SPI5RST_Pos (20U)
16301#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
16302#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
16303#define RCC_APB2RSTR_SAI1RST_Pos (22U)
16304#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
16305#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
16306#define RCC_APB2RSTR_DFSDM1RST_Pos (30U)
16307#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
16308#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
16309
16310/******************** Bit definition for RCC_APB4RSTR register ******************/
16311#define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
16312#define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos)
16313#define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
16314#define RCC_APB4RSTR_LPUART1RST_Pos (3U)
16315#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos)
16316#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
16317#define RCC_APB4RSTR_SPI6RST_Pos (5U)
16318#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos)
16319#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
16320#define RCC_APB4RSTR_I2C4RST_Pos (7U)
16321#define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos)
16322#define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
16323#define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
16324#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos)
16325#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
16326#define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
16327#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos)
16328#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
16329#define RCC_APB4RSTR_LPTIM4RST_Pos (11U)
16330#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos)
16331#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk
16332#define RCC_APB4RSTR_LPTIM5RST_Pos (12U)
16333#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos)
16334#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk
16335#define RCC_APB4RSTR_COMP12RST_Pos (14U)
16336#define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos)
16337#define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
16338#define RCC_APB4RSTR_VREFRST_Pos (15U)
16339#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos)
16340#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
16341#define RCC_APB4RSTR_SAI4RST_Pos (21U)
16342#define RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos)
16343#define RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk
16344
16345#define RCC_APB4RSTR_DTSRST_Pos (26U)
16346#define RCC_APB4RSTR_DTSRST_Msk (0x1UL << RCC_APB4RSTR_DTSRST_Pos)
16347#define RCC_APB4RSTR_DTSRST RCC_APB4RSTR_DTSRST_Msk
16348
16349/******************** Bit definition for RCC_GCR register ********************/
16350#define RCC_GCR_WW1RSC_Pos (0U)
16351#define RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos)
16352#define RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk
16353
16354/******************** Bit definition for RCC_D3AMR register ********************/
16355#define RCC_D3AMR_BDMAAMEN_Pos (0U)
16356#define RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos)
16357#define RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk
16358#define RCC_D3AMR_LPUART1AMEN_Pos (3U)
16359#define RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos)
16360#define RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk
16361#define RCC_D3AMR_SPI6AMEN_Pos (5U)
16362#define RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos)
16363#define RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk
16364#define RCC_D3AMR_I2C4AMEN_Pos (7U)
16365#define RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos)
16366#define RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk
16367#define RCC_D3AMR_LPTIM2AMEN_Pos (9U)
16368#define RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos)
16369#define RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk
16370#define RCC_D3AMR_LPTIM3AMEN_Pos (10U)
16371#define RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos)
16372#define RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk
16373#define RCC_D3AMR_LPTIM4AMEN_Pos (11U)
16374#define RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos)
16375#define RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk
16376#define RCC_D3AMR_LPTIM5AMEN_Pos (12U)
16377#define RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos)
16378#define RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk
16379#define RCC_D3AMR_COMP12AMEN_Pos (14U)
16380#define RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos)
16381#define RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk
16382#define RCC_D3AMR_VREFAMEN_Pos (15U)
16383#define RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos)
16384#define RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk
16385#define RCC_D3AMR_RTCAMEN_Pos (16U)
16386#define RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos)
16387#define RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk
16388#define RCC_D3AMR_CRCAMEN_Pos (19U)
16389#define RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos)
16390#define RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk
16391#define RCC_D3AMR_SAI4AMEN_Pos (21U)
16392#define RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos)
16393#define RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk
16394#define RCC_D3AMR_ADC3AMEN_Pos (24U)
16395#define RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos)
16396#define RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk
16397
16398#define RCC_D3AMR_DTSAMEN_Pos (26U)
16399#define RCC_D3AMR_DTSAMEN_Msk (0x1UL << RCC_D3AMR_DTSAMEN_Pos)
16400#define RCC_D3AMR_DTSAMEN RCC_D3AMR_DTSAMEN_Msk
16401
16402#define RCC_D3AMR_BKPRAMAMEN_Pos (28U)
16403#define RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos)
16404#define RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk
16405#define RCC_D3AMR_SRAM4AMEN_Pos (29U)
16406#define RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos)
16407#define RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk
16408/******************** Bit definition for RCC_AHB3LPENR register **************/
16409#define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
16410#define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)
16411#define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
16412#define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
16413#define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)
16414#define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
16415#define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
16416#define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)
16417#define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
16418#define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
16419#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
16420#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
16421#define RCC_AHB3LPENR_OSPI1LPEN_Pos (14U)
16422#define RCC_AHB3LPENR_OSPI1LPEN_Msk (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)
16423#define RCC_AHB3LPENR_OSPI1LPEN RCC_AHB3LPENR_OSPI1LPEN_Msk
16424#define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
16425#define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)
16426#define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
16427#define RCC_AHB3LPENR_OSPI2LPEN_Pos (19U)
16428#define RCC_AHB3LPENR_OSPI2LPEN_Msk (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)
16429#define RCC_AHB3LPENR_OSPI2LPEN RCC_AHB3LPENR_OSPI2LPEN_Msk
16430#define RCC_AHB3LPENR_IOMNGRLPEN_Pos (21U)
16431#define RCC_AHB3LPENR_IOMNGRLPEN_Msk (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)
16432#define RCC_AHB3LPENR_IOMNGRLPEN RCC_AHB3LPENR_IOMNGRLPEN_Msk
16433#define RCC_AHB3LPENR_OTFDEC1LPEN_Pos (22U)
16434#define RCC_AHB3LPENR_OTFDEC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_OTFDEC1LPEN_Pos)
16435#define RCC_AHB3LPENR_OTFDEC1LPEN RCC_AHB3LPENR_OTFDEC1LPEN_Msk
16436#define RCC_AHB3LPENR_OTFDEC2LPEN_Pos (23U)
16437#define RCC_AHB3LPENR_OTFDEC2LPEN_Msk (0x1UL << RCC_AHB3LPENR_OTFDEC2LPEN_Pos)
16438#define RCC_AHB3LPENR_OTFDEC2LPEN RCC_AHB3LPENR_OTFDEC2LPEN_Msk
16439#define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
16440#define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)
16441#define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
16442#define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
16443#define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)
16444#define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
16445#define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
16446#define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)
16447#define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
16448#define RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U)
16449#define RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)
16450#define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk
16451
16452
16453/******************** Bit definition for RCC_AHB1LPENR register ***************/
16454#define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
16455#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
16456#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
16457#define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
16458#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
16459#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
16460#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
16461#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)
16462#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
16463#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U)
16464#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos)
16465#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk
16466#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U)
16467#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos)
16468#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk
16469#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U)
16470#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos)
16471#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk
16472#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
16473#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos)
16474#define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
16475#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
16476#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos)
16477#define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
16478
16479/******************** Bit definition for RCC_AHB2LPENR register ***************/
16480#define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos (0U)
16481#define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos)
16482#define RCC_AHB2LPENR_DCMI_PSSILPEN RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
16483#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
16484#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos)
16485#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
16486#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
16487#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos)
16488#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
16489#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
16490#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
16491#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
16492#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
16493#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos)
16494#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
16495#define RCC_AHB2LPENR_FMACLPEN_Pos (16U)
16496#define RCC_AHB2LPENR_FMACLPEN_Msk (0x1UL << RCC_AHB2LPENR_FMACLPEN_Pos)
16497#define RCC_AHB2LPENR_FMACLPEN RCC_AHB2LPENR_FMACLPEN_Msk
16498#define RCC_AHB2LPENR_CORDICLPEN_Pos (17U)
16499#define RCC_AHB2LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB2LPENR_CORDICLPEN_Pos)
16500#define RCC_AHB2LPENR_CORDICLPEN RCC_AHB2LPENR_CORDICLPEN_Msk
16501#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U)
16502#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos)
16503#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk
16504#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
16505#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos)
16506#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
16507
16508/* Legacy define */
16509#define RCC_AHB2LPENR_DCMILPEN_Pos RCC_AHB2LPENR_DCMI_PSSILPEN_Pos
16510#define RCC_AHB2LPENR_DCMILPEN_Msk RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
16511#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMI_PSSILPEN
16512#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos RCC_AHB2LPENR_SRAM1LPEN_Pos
16513#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk RCC_AHB2LPENR_SRAM1LPEN_Msk
16514#define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN
16515#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos RCC_AHB2LPENR_SRAM2LPEN_Pos
16516#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk RCC_AHB2LPENR_SRAM2LPEN_Msk
16517#define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN
16518
16519/******************** Bit definition for RCC_AHB4LPENR register ******************/
16520#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
16521#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)
16522#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
16523#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
16524#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)
16525#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
16526#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
16527#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)
16528#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
16529#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
16530#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)
16531#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
16532#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
16533#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)
16534#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
16535#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
16536#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)
16537#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
16538#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
16539#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)
16540#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
16541#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
16542#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)
16543#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
16544#define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
16545#define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos)
16546#define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
16547#define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
16548#define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos)
16549#define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
16550#define RCC_AHB4LPENR_CRCLPEN_Pos (19U)
16551#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos)
16552#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk
16553#define RCC_AHB4LPENR_BDMALPEN_Pos (21U)
16554#define RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos)
16555#define RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk
16556#define RCC_AHB4LPENR_ADC3LPEN_Pos (24U)
16557#define RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos)
16558#define RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk
16559#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
16560#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos)
16561#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
16562#define RCC_AHB4LPENR_SRAM4LPEN_Pos (29U)
16563#define RCC_AHB4LPENR_SRAM4LPEN_Msk (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos)
16564#define RCC_AHB4LPENR_SRAM4LPEN RCC_AHB4LPENR_SRAM4LPEN_Msk
16565
16566/* Legacy define */
16567#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos RCC_AHB4LPENR_SRAM4LPEN_Pos
16568#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk RCC_AHB4LPENR_SRAM4LPEN_Msk
16569#define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_SRAM4LPEN
16570/******************** Bit definition for RCC_APB3LPENR register ******************/
16571#define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
16572#define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos)
16573#define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
16574#define RCC_APB3LPENR_WWDG1LPEN_Pos (6U)
16575#define RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos)
16576#define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk
16577
16578/******************** Bit definition for RCC_APB1LLPENR register ******************/
16579
16580#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
16581#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos)
16582#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
16583#define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
16584#define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos)
16585#define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
16586#define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
16587#define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos)
16588#define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
16589#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
16590#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos)
16591#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
16592#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
16593#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos)
16594#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
16595#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
16596#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos)
16597#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
16598#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
16599#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos)
16600#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
16601#define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
16602#define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos)
16603#define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
16604#define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
16605#define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos)
16606#define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
16607#define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
16608#define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos)
16609#define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
16610
16611
16612#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
16613#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos)
16614#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
16615#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
16616#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos)
16617#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
16618#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
16619#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos)
16620#define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
16621#define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
16622#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos)
16623#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
16624#define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
16625#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos)
16626#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
16627#define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
16628#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos)
16629#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
16630#define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
16631#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos)
16632#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
16633#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
16634#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos)
16635#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
16636#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
16637#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos)
16638#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
16639#define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
16640#define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos)
16641#define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
16642#define RCC_APB1LLPENR_I2C5LPEN_Pos (25U)
16643#define RCC_APB1LLPENR_I2C5LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C5LPEN_Pos)
16644#define RCC_APB1LLPENR_I2C5LPEN RCC_APB1LLPENR_I2C5LPEN_Msk
16645#define RCC_APB1LLPENR_CECLPEN_Pos (27U)
16646#define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos)
16647#define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
16648#define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
16649#define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos)
16650#define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
16651#define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
16652#define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos)
16653#define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
16654#define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
16655#define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos)
16656#define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
16657
16658/* Legacy define */
16659#define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
16660#define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
16661#define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
16662/******************** Bit definition for RCC_APB1HLPENR register ******************/
16663#define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
16664#define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos)
16665#define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
16666#define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
16667#define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos)
16668#define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
16669#define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
16670#define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos)
16671#define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
16672#define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
16673#define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos)
16674#define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
16675#define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
16676#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos)
16677#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
16678#define RCC_APB1HLPENR_TIM23LPEN_Pos (24U)
16679#define RCC_APB1HLPENR_TIM23LPEN_Msk (0x1UL << RCC_APB1HLPENR_TIM23LPEN_Pos)
16680#define RCC_APB1HLPENR_TIM23LPEN RCC_APB1HLPENR_TIM23LPEN_Msk
16681#define RCC_APB1HLPENR_TIM24LPEN_Pos (25U)
16682#define RCC_APB1HLPENR_TIM24LPEN_Msk (0x1UL << RCC_APB1HLPENR_TIM24LPEN_Pos)
16683#define RCC_APB1HLPENR_TIM24LPEN RCC_APB1HLPENR_TIM24LPEN_Msk
16684
16685/******************** Bit definition for RCC_APB2LPENR register ******************/
16686#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
16687#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
16688#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
16689#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
16690#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
16691#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
16692#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
16693#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
16694#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
16695#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
16696#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
16697#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
16698#define RCC_APB2LPENR_UART9LPEN_Pos (6U)
16699#define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)
16700#define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk
16701#define RCC_APB2LPENR_USART10LPEN_Pos (7U)
16702#define RCC_APB2LPENR_USART10LPEN_Msk (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos)
16703#define RCC_APB2LPENR_USART10LPEN RCC_APB2LPENR_USART10LPEN_Msk
16704#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
16705#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
16706#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
16707#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
16708#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
16709#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
16710#define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
16711#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)
16712#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
16713#define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
16714#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)
16715#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
16716#define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
16717#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)
16718#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
16719#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
16720#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
16721#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
16722#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
16723#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
16724#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
16725#define RCC_APB2LPENR_DFSDM1LPEN_Pos (30U)
16726#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos)
16727#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
16728
16729/******************** Bit definition for RCC_APB4LPENR register ******************/
16730#define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
16731#define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos)
16732#define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
16733#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
16734#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)
16735#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
16736#define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
16737#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos)
16738#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
16739#define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
16740#define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos)
16741#define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
16742#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
16743#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos)
16744#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
16745#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
16746#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos)
16747#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
16748#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U)
16749#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos)
16750#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk
16751#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U)
16752#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos)
16753#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk
16754#define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
16755#define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos)
16756#define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
16757#define RCC_APB4LPENR_VREFLPEN_Pos (15U)
16758#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos)
16759#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
16760#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
16761#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos)
16762#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
16763#define RCC_APB4LPENR_SAI4LPEN_Pos (21U)
16764#define RCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos)
16765#define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk
16766
16767#define RCC_APB4LPENR_DTSLPEN_Pos (26U)
16768#define RCC_APB4LPENR_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos)
16769#define RCC_APB4LPENR_DTSLPEN RCC_APB4LPENR_DTSLPEN_Msk
16770
16771/******************** Bit definition for RCC_RSR register *******************/
16772#define RCC_RSR_RMVF_Pos (16U)
16773#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos)
16774#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
16775#define RCC_RSR_CPURSTF_Pos (17U)
16776#define RCC_RSR_CPURSTF_Msk (0x1UL << RCC_RSR_CPURSTF_Pos)
16777#define RCC_RSR_CPURSTF RCC_RSR_CPURSTF_Msk
16778#define RCC_RSR_D1RSTF_Pos (19U)
16779#define RCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos)
16780#define RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk
16781#define RCC_RSR_D2RSTF_Pos (20U)
16782#define RCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos)
16783#define RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk
16784#define RCC_RSR_BORRSTF_Pos (21U)
16785#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos)
16786#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
16787#define RCC_RSR_PINRSTF_Pos (22U)
16788#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos)
16789#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
16790#define RCC_RSR_PORRSTF_Pos (23U)
16791#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos)
16792#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
16793#define RCC_RSR_SFTRSTF_Pos (24U)
16794#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos)
16795#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk
16796#define RCC_RSR_IWDG1RSTF_Pos (26U)
16797#define RCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos)
16798#define RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk
16799#define RCC_RSR_WWDG1RSTF_Pos (28U)
16800#define RCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos)
16801#define RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk
16802
16803#define RCC_RSR_LPWRRSTF_Pos (30U)
16804#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos)
16805#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk
16806
16807
16808/******************************************************************************/
16809/* */
16810/* RNG */
16811/* */
16812/******************************************************************************/
16813/*************************** RNG VER **************************************/
16814#define RNG_VER_3_2
16815/******************** Bits definition for RNG_CR register *******************/
16816#define RNG_CR_RNGEN_Pos (2U)
16817#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
16818#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
16819#define RNG_CR_IE_Pos (3U)
16820#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
16821#define RNG_CR_IE RNG_CR_IE_Msk
16822#define RNG_CR_CED_Pos (5U)
16823#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos)
16824#define RNG_CR_CED RNG_CR_CED_Msk
16825#define RNG_CR_RNG_CONFIG3_Pos (8U)
16826#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
16827#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
16828#define RNG_CR_NISTC_Pos (12U)
16829#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos)
16830#define RNG_CR_NISTC RNG_CR_NISTC_Msk
16831#define RNG_CR_RNG_CONFIG2_Pos (13U)
16832#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
16833#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
16834#define RNG_CR_CLKDIV_Pos (16U)
16835#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos)
16836#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
16837#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos)
16838#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos)
16839#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos)
16840#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos)
16841#define RNG_CR_RNG_CONFIG1_Pos (20U)
16842#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
16843#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
16844#define RNG_CR_CONDRST_Pos (30U)
16845#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos)
16846#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
16847#define RNG_CR_CONFIGLOCK_Pos (31U)
16848#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos)
16849#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
16850
16851/******************** Bits definition for RNG_SR register *******************/
16852#define RNG_SR_DRDY_Pos (0U)
16853#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
16854#define RNG_SR_DRDY RNG_SR_DRDY_Msk
16855#define RNG_SR_CECS_Pos (1U)
16856#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
16857#define RNG_SR_CECS RNG_SR_CECS_Msk
16858#define RNG_SR_SECS_Pos (2U)
16859#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
16860#define RNG_SR_SECS RNG_SR_SECS_Msk
16861#define RNG_SR_CEIS_Pos (5U)
16862#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
16863#define RNG_SR_CEIS RNG_SR_CEIS_Msk
16864#define RNG_SR_SEIS_Pos (6U)
16865#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
16866#define RNG_SR_SEIS RNG_SR_SEIS_Msk
16867
16868/******************************************************************************/
16869/* */
16870/* Real-Time Clock (RTC) */
16871/* */
16872/******************************************************************************/
16873/******************** Bits definition for RTC_TR register *******************/
16874#define RTC_TR_PM_Pos (22U)
16875#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
16876#define RTC_TR_PM RTC_TR_PM_Msk
16877#define RTC_TR_HT_Pos (20U)
16878#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
16879#define RTC_TR_HT RTC_TR_HT_Msk
16880#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
16881#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
16882#define RTC_TR_HU_Pos (16U)
16883#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
16884#define RTC_TR_HU RTC_TR_HU_Msk
16885#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
16886#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
16887#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
16888#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
16889#define RTC_TR_MNT_Pos (12U)
16890#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
16891#define RTC_TR_MNT RTC_TR_MNT_Msk
16892#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
16893#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
16894#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
16895#define RTC_TR_MNU_Pos (8U)
16896#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
16897#define RTC_TR_MNU RTC_TR_MNU_Msk
16898#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
16899#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
16900#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
16901#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
16902#define RTC_TR_ST_Pos (4U)
16903#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
16904#define RTC_TR_ST RTC_TR_ST_Msk
16905#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
16906#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
16907#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
16908#define RTC_TR_SU_Pos (0U)
16909#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
16910#define RTC_TR_SU RTC_TR_SU_Msk
16911#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
16912#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
16913#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
16914#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
16916/******************** Bits definition for RTC_DR register *******************/
16917#define RTC_DR_YT_Pos (20U)
16918#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
16919#define RTC_DR_YT RTC_DR_YT_Msk
16920#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
16921#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
16922#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
16923#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
16924#define RTC_DR_YU_Pos (16U)
16925#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
16926#define RTC_DR_YU RTC_DR_YU_Msk
16927#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
16928#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
16929#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
16930#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
16931#define RTC_DR_WDU_Pos (13U)
16932#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
16933#define RTC_DR_WDU RTC_DR_WDU_Msk
16934#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
16935#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
16936#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
16937#define RTC_DR_MT_Pos (12U)
16938#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
16939#define RTC_DR_MT RTC_DR_MT_Msk
16940#define RTC_DR_MU_Pos (8U)
16941#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
16942#define RTC_DR_MU RTC_DR_MU_Msk
16943#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
16944#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
16945#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
16946#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
16947#define RTC_DR_DT_Pos (4U)
16948#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
16949#define RTC_DR_DT RTC_DR_DT_Msk
16950#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
16951#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
16952#define RTC_DR_DU_Pos (0U)
16953#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
16954#define RTC_DR_DU RTC_DR_DU_Msk
16955#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
16956#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
16957#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
16958#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
16960/******************** Bits definition for RTC_CR register *******************/
16961#define RTC_CR_ITSE_Pos (24U)
16962#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
16963#define RTC_CR_ITSE RTC_CR_ITSE_Msk
16964#define RTC_CR_COE_Pos (23U)
16965#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
16966#define RTC_CR_COE RTC_CR_COE_Msk
16967#define RTC_CR_OSEL_Pos (21U)
16968#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
16969#define RTC_CR_OSEL RTC_CR_OSEL_Msk
16970#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
16971#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
16972#define RTC_CR_POL_Pos (20U)
16973#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
16974#define RTC_CR_POL RTC_CR_POL_Msk
16975#define RTC_CR_COSEL_Pos (19U)
16976#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
16977#define RTC_CR_COSEL RTC_CR_COSEL_Msk
16978#define RTC_CR_BKP_Pos (18U)
16979#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
16980#define RTC_CR_BKP RTC_CR_BKP_Msk
16981#define RTC_CR_SUB1H_Pos (17U)
16982#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
16983#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
16984#define RTC_CR_ADD1H_Pos (16U)
16985#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
16986#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
16987#define RTC_CR_TSIE_Pos (15U)
16988#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
16989#define RTC_CR_TSIE RTC_CR_TSIE_Msk
16990#define RTC_CR_WUTIE_Pos (14U)
16991#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
16992#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
16993#define RTC_CR_ALRBIE_Pos (13U)
16994#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
16995#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
16996#define RTC_CR_ALRAIE_Pos (12U)
16997#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
16998#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
16999#define RTC_CR_TSE_Pos (11U)
17000#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
17001#define RTC_CR_TSE RTC_CR_TSE_Msk
17002#define RTC_CR_WUTE_Pos (10U)
17003#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
17004#define RTC_CR_WUTE RTC_CR_WUTE_Msk
17005#define RTC_CR_ALRBE_Pos (9U)
17006#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
17007#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
17008#define RTC_CR_ALRAE_Pos (8U)
17009#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
17010#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
17011#define RTC_CR_FMT_Pos (6U)
17012#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
17013#define RTC_CR_FMT RTC_CR_FMT_Msk
17014#define RTC_CR_BYPSHAD_Pos (5U)
17015#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
17016#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
17017#define RTC_CR_REFCKON_Pos (4U)
17018#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
17019#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
17020#define RTC_CR_TSEDGE_Pos (3U)
17021#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
17022#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
17023#define RTC_CR_WUCKSEL_Pos (0U)
17024#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
17025#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
17026#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
17027#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
17028#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
17030/******************** Bits definition for RTC_ISR register ******************/
17031#define RTC_ISR_ITSF_Pos (17U)
17032#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
17033#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
17034#define RTC_ISR_RECALPF_Pos (16U)
17035#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
17036#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
17037#define RTC_ISR_TAMP3F_Pos (15U)
17038#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
17039#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
17040#define RTC_ISR_TAMP2F_Pos (14U)
17041#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
17042#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
17043#define RTC_ISR_TAMP1F_Pos (13U)
17044#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
17045#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
17046#define RTC_ISR_TSOVF_Pos (12U)
17047#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
17048#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
17049#define RTC_ISR_TSF_Pos (11U)
17050#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
17051#define RTC_ISR_TSF RTC_ISR_TSF_Msk
17052#define RTC_ISR_WUTF_Pos (10U)
17053#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
17054#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
17055#define RTC_ISR_ALRBF_Pos (9U)
17056#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
17057#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
17058#define RTC_ISR_ALRAF_Pos (8U)
17059#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
17060#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
17061#define RTC_ISR_INIT_Pos (7U)
17062#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
17063#define RTC_ISR_INIT RTC_ISR_INIT_Msk
17064#define RTC_ISR_INITF_Pos (6U)
17065#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
17066#define RTC_ISR_INITF RTC_ISR_INITF_Msk
17067#define RTC_ISR_RSF_Pos (5U)
17068#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
17069#define RTC_ISR_RSF RTC_ISR_RSF_Msk
17070#define RTC_ISR_INITS_Pos (4U)
17071#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
17072#define RTC_ISR_INITS RTC_ISR_INITS_Msk
17073#define RTC_ISR_SHPF_Pos (3U)
17074#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
17075#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
17076#define RTC_ISR_WUTWF_Pos (2U)
17077#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
17078#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
17079#define RTC_ISR_ALRBWF_Pos (1U)
17080#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
17081#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
17082#define RTC_ISR_ALRAWF_Pos (0U)
17083#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
17084#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
17085
17086/******************** Bits definition for RTC_PRER register *****************/
17087#define RTC_PRER_PREDIV_A_Pos (16U)
17088#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
17089#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
17090#define RTC_PRER_PREDIV_S_Pos (0U)
17091#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
17092#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
17093
17094/******************** Bits definition for RTC_WUTR register *****************/
17095#define RTC_WUTR_WUT_Pos (0U)
17096#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
17097#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
17098
17099/******************** Bits definition for RTC_ALRMAR register ***************/
17100#define RTC_ALRMAR_MSK4_Pos (31U)
17101#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
17102#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
17103#define RTC_ALRMAR_WDSEL_Pos (30U)
17104#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
17105#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
17106#define RTC_ALRMAR_DT_Pos (28U)
17107#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
17108#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
17109#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
17110#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
17111#define RTC_ALRMAR_DU_Pos (24U)
17112#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
17113#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
17114#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
17115#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
17116#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
17117#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
17118#define RTC_ALRMAR_MSK3_Pos (23U)
17119#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
17120#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
17121#define RTC_ALRMAR_PM_Pos (22U)
17122#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
17123#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
17124#define RTC_ALRMAR_HT_Pos (20U)
17125#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
17126#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
17127#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
17128#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
17129#define RTC_ALRMAR_HU_Pos (16U)
17130#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
17131#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
17132#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
17133#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
17134#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
17135#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
17136#define RTC_ALRMAR_MSK2_Pos (15U)
17137#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
17138#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
17139#define RTC_ALRMAR_MNT_Pos (12U)
17140#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
17141#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
17142#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
17143#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
17144#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
17145#define RTC_ALRMAR_MNU_Pos (8U)
17146#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
17147#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
17148#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
17149#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
17150#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
17151#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
17152#define RTC_ALRMAR_MSK1_Pos (7U)
17153#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
17154#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
17155#define RTC_ALRMAR_ST_Pos (4U)
17156#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
17157#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
17158#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
17159#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
17160#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
17161#define RTC_ALRMAR_SU_Pos (0U)
17162#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
17163#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
17164#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
17165#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
17166#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
17167#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
17169/******************** Bits definition for RTC_ALRMBR register ***************/
17170#define RTC_ALRMBR_MSK4_Pos (31U)
17171#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
17172#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
17173#define RTC_ALRMBR_WDSEL_Pos (30U)
17174#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
17175#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
17176#define RTC_ALRMBR_DT_Pos (28U)
17177#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
17178#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
17179#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
17180#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
17181#define RTC_ALRMBR_DU_Pos (24U)
17182#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
17183#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
17184#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
17185#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
17186#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
17187#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
17188#define RTC_ALRMBR_MSK3_Pos (23U)
17189#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
17190#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
17191#define RTC_ALRMBR_PM_Pos (22U)
17192#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
17193#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
17194#define RTC_ALRMBR_HT_Pos (20U)
17195#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
17196#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
17197#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
17198#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
17199#define RTC_ALRMBR_HU_Pos (16U)
17200#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
17201#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
17202#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
17203#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
17204#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
17205#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
17206#define RTC_ALRMBR_MSK2_Pos (15U)
17207#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
17208#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
17209#define RTC_ALRMBR_MNT_Pos (12U)
17210#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
17211#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
17212#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
17213#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
17214#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
17215#define RTC_ALRMBR_MNU_Pos (8U)
17216#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
17217#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
17218#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
17219#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
17220#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
17221#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
17222#define RTC_ALRMBR_MSK1_Pos (7U)
17223#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
17224#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
17225#define RTC_ALRMBR_ST_Pos (4U)
17226#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
17227#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
17228#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
17229#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
17230#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
17231#define RTC_ALRMBR_SU_Pos (0U)
17232#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
17233#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
17234#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
17235#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
17236#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
17237#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
17239/******************** Bits definition for RTC_WPR register ******************/
17240#define RTC_WPR_KEY_Pos (0U)
17241#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
17242#define RTC_WPR_KEY RTC_WPR_KEY_Msk
17243
17244/******************** Bits definition for RTC_SSR register ******************/
17245#define RTC_SSR_SS_Pos (0U)
17246#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
17247#define RTC_SSR_SS RTC_SSR_SS_Msk
17248
17249/******************** Bits definition for RTC_SHIFTR register ***************/
17250#define RTC_SHIFTR_SUBFS_Pos (0U)
17251#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
17252#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
17253#define RTC_SHIFTR_ADD1S_Pos (31U)
17254#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
17255#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
17256
17257/******************** Bits definition for RTC_TSTR register *****************/
17258#define RTC_TSTR_PM_Pos (22U)
17259#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
17260#define RTC_TSTR_PM RTC_TSTR_PM_Msk
17261#define RTC_TSTR_HT_Pos (20U)
17262#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
17263#define RTC_TSTR_HT RTC_TSTR_HT_Msk
17264#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
17265#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
17266#define RTC_TSTR_HU_Pos (16U)
17267#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
17268#define RTC_TSTR_HU RTC_TSTR_HU_Msk
17269#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
17270#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
17271#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
17272#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
17273#define RTC_TSTR_MNT_Pos (12U)
17274#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
17275#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
17276#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
17277#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
17278#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
17279#define RTC_TSTR_MNU_Pos (8U)
17280#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
17281#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
17282#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
17283#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
17284#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
17285#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
17286#define RTC_TSTR_ST_Pos (4U)
17287#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
17288#define RTC_TSTR_ST RTC_TSTR_ST_Msk
17289#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
17290#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
17291#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
17292#define RTC_TSTR_SU_Pos (0U)
17293#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
17294#define RTC_TSTR_SU RTC_TSTR_SU_Msk
17295#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
17296#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
17297#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
17298#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
17300/******************** Bits definition for RTC_TSDR register *****************/
17301#define RTC_TSDR_WDU_Pos (13U)
17302#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
17303#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
17304#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
17305#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
17306#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
17307#define RTC_TSDR_MT_Pos (12U)
17308#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
17309#define RTC_TSDR_MT RTC_TSDR_MT_Msk
17310#define RTC_TSDR_MU_Pos (8U)
17311#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
17312#define RTC_TSDR_MU RTC_TSDR_MU_Msk
17313#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
17314#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
17315#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
17316#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
17317#define RTC_TSDR_DT_Pos (4U)
17318#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
17319#define RTC_TSDR_DT RTC_TSDR_DT_Msk
17320#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
17321#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
17322#define RTC_TSDR_DU_Pos (0U)
17323#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
17324#define RTC_TSDR_DU RTC_TSDR_DU_Msk
17325#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
17326#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
17327#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
17328#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
17330/******************** Bits definition for RTC_TSSSR register ****************/
17331#define RTC_TSSSR_SS_Pos (0U)
17332#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
17333#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
17334
17335/******************** Bits definition for RTC_CALR register *****************/
17336#define RTC_CALR_CALP_Pos (15U)
17337#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
17338#define RTC_CALR_CALP RTC_CALR_CALP_Msk
17339#define RTC_CALR_CALW8_Pos (14U)
17340#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
17341#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
17342#define RTC_CALR_CALW16_Pos (13U)
17343#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
17344#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
17345#define RTC_CALR_CALM_Pos (0U)
17346#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
17347#define RTC_CALR_CALM RTC_CALR_CALM_Msk
17348#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
17349#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
17350#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
17351#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
17352#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
17353#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
17354#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
17355#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
17356#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
17358/******************** Bits definition for RTC_TAMPCR register ***************/
17359#define RTC_TAMPCR_TAMP3MF_Pos (24U)
17360#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
17361#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
17362#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
17363#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
17364#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
17365#define RTC_TAMPCR_TAMP3IE_Pos (22U)
17366#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
17367#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
17368#define RTC_TAMPCR_TAMP2MF_Pos (21U)
17369#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
17370#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
17371#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
17372#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
17373#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
17374#define RTC_TAMPCR_TAMP2IE_Pos (19U)
17375#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
17376#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
17377#define RTC_TAMPCR_TAMP1MF_Pos (18U)
17378#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
17379#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
17380#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
17381#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
17382#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
17383#define RTC_TAMPCR_TAMP1IE_Pos (16U)
17384#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
17385#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
17386#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
17387#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
17388#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
17389#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
17390#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
17391#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
17392#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
17393#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
17394#define RTC_TAMPCR_TAMPFLT_Pos (11U)
17395#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
17396#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
17397#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
17398#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
17399#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
17400#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
17401#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
17402#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
17403#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
17404#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
17405#define RTC_TAMPCR_TAMPTS_Pos (7U)
17406#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
17407#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
17408#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
17409#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
17410#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
17411#define RTC_TAMPCR_TAMP3E_Pos (5U)
17412#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
17413#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
17414#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
17415#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
17416#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
17417#define RTC_TAMPCR_TAMP2E_Pos (3U)
17418#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
17419#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
17420#define RTC_TAMPCR_TAMPIE_Pos (2U)
17421#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
17422#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
17423#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
17424#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
17425#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
17426#define RTC_TAMPCR_TAMP1E_Pos (0U)
17427#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
17428#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
17429
17430/******************** Bits definition for RTC_ALRMASSR register *************/
17431#define RTC_ALRMASSR_MASKSS_Pos (24U)
17432#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
17433#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
17434#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
17435#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
17436#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
17437#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
17438#define RTC_ALRMASSR_SS_Pos (0U)
17439#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
17440#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
17441
17442/******************** Bits definition for RTC_ALRMBSSR register *************/
17443#define RTC_ALRMBSSR_MASKSS_Pos (24U)
17444#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
17445#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
17446#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
17447#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
17448#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
17449#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
17450#define RTC_ALRMBSSR_SS_Pos (0U)
17451#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
17452#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
17453
17454/******************** Bits definition for RTC_OR register *******************/
17455#define RTC_OR_OUT_RMP_Pos (1U)
17456#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos)
17457#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
17458#define RTC_OR_ALARMOUTTYPE_Pos (0U)
17459#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
17460#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
17461
17462/******************** Bits definition for RTC_BKP0R register ****************/
17463#define RTC_BKP0R_Pos (0U)
17464#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
17465#define RTC_BKP0R RTC_BKP0R_Msk
17466
17467/******************** Bits definition for RTC_BKP1R register ****************/
17468#define RTC_BKP1R_Pos (0U)
17469#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
17470#define RTC_BKP1R RTC_BKP1R_Msk
17471
17472/******************** Bits definition for RTC_BKP2R register ****************/
17473#define RTC_BKP2R_Pos (0U)
17474#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
17475#define RTC_BKP2R RTC_BKP2R_Msk
17476
17477/******************** Bits definition for RTC_BKP3R register ****************/
17478#define RTC_BKP3R_Pos (0U)
17479#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
17480#define RTC_BKP3R RTC_BKP3R_Msk
17481
17482/******************** Bits definition for RTC_BKP4R register ****************/
17483#define RTC_BKP4R_Pos (0U)
17484#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
17485#define RTC_BKP4R RTC_BKP4R_Msk
17486
17487/******************** Bits definition for RTC_BKP5R register ****************/
17488#define RTC_BKP5R_Pos (0U)
17489#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
17490#define RTC_BKP5R RTC_BKP5R_Msk
17491
17492/******************** Bits definition for RTC_BKP6R register ****************/
17493#define RTC_BKP6R_Pos (0U)
17494#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
17495#define RTC_BKP6R RTC_BKP6R_Msk
17496
17497/******************** Bits definition for RTC_BKP7R register ****************/
17498#define RTC_BKP7R_Pos (0U)
17499#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
17500#define RTC_BKP7R RTC_BKP7R_Msk
17501
17502/******************** Bits definition for RTC_BKP8R register ****************/
17503#define RTC_BKP8R_Pos (0U)
17504#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
17505#define RTC_BKP8R RTC_BKP8R_Msk
17506
17507/******************** Bits definition for RTC_BKP9R register ****************/
17508#define RTC_BKP9R_Pos (0U)
17509#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
17510#define RTC_BKP9R RTC_BKP9R_Msk
17511
17512/******************** Bits definition for RTC_BKP10R register ***************/
17513#define RTC_BKP10R_Pos (0U)
17514#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
17515#define RTC_BKP10R RTC_BKP10R_Msk
17516
17517/******************** Bits definition for RTC_BKP11R register ***************/
17518#define RTC_BKP11R_Pos (0U)
17519#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
17520#define RTC_BKP11R RTC_BKP11R_Msk
17521
17522/******************** Bits definition for RTC_BKP12R register ***************/
17523#define RTC_BKP12R_Pos (0U)
17524#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
17525#define RTC_BKP12R RTC_BKP12R_Msk
17526
17527/******************** Bits definition for RTC_BKP13R register ***************/
17528#define RTC_BKP13R_Pos (0U)
17529#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
17530#define RTC_BKP13R RTC_BKP13R_Msk
17531
17532/******************** Bits definition for RTC_BKP14R register ***************/
17533#define RTC_BKP14R_Pos (0U)
17534#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
17535#define RTC_BKP14R RTC_BKP14R_Msk
17536
17537/******************** Bits definition for RTC_BKP15R register ***************/
17538#define RTC_BKP15R_Pos (0U)
17539#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
17540#define RTC_BKP15R RTC_BKP15R_Msk
17541
17542/******************** Bits definition for RTC_BKP16R register ***************/
17543#define RTC_BKP16R_Pos (0U)
17544#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
17545#define RTC_BKP16R RTC_BKP16R_Msk
17546
17547/******************** Bits definition for RTC_BKP17R register ***************/
17548#define RTC_BKP17R_Pos (0U)
17549#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
17550#define RTC_BKP17R RTC_BKP17R_Msk
17551
17552/******************** Bits definition for RTC_BKP18R register ***************/
17553#define RTC_BKP18R_Pos (0U)
17554#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
17555#define RTC_BKP18R RTC_BKP18R_Msk
17556
17557/******************** Bits definition for RTC_BKP19R register ***************/
17558#define RTC_BKP19R_Pos (0U)
17559#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
17560#define RTC_BKP19R RTC_BKP19R_Msk
17561
17562/******************** Bits definition for RTC_BKP20R register ***************/
17563#define RTC_BKP20R_Pos (0U)
17564#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
17565#define RTC_BKP20R RTC_BKP20R_Msk
17566
17567/******************** Bits definition for RTC_BKP21R register ***************/
17568#define RTC_BKP21R_Pos (0U)
17569#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
17570#define RTC_BKP21R RTC_BKP21R_Msk
17571
17572/******************** Bits definition for RTC_BKP22R register ***************/
17573#define RTC_BKP22R_Pos (0U)
17574#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
17575#define RTC_BKP22R RTC_BKP22R_Msk
17576
17577/******************** Bits definition for RTC_BKP23R register ***************/
17578#define RTC_BKP23R_Pos (0U)
17579#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
17580#define RTC_BKP23R RTC_BKP23R_Msk
17581
17582/******************** Bits definition for RTC_BKP24R register ***************/
17583#define RTC_BKP24R_Pos (0U)
17584#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
17585#define RTC_BKP24R RTC_BKP24R_Msk
17586
17587/******************** Bits definition for RTC_BKP25R register ***************/
17588#define RTC_BKP25R_Pos (0U)
17589#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
17590#define RTC_BKP25R RTC_BKP25R_Msk
17591
17592/******************** Bits definition for RTC_BKP26R register ***************/
17593#define RTC_BKP26R_Pos (0U)
17594#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
17595#define RTC_BKP26R RTC_BKP26R_Msk
17596
17597/******************** Bits definition for RTC_BKP27R register ***************/
17598#define RTC_BKP27R_Pos (0U)
17599#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
17600#define RTC_BKP27R RTC_BKP27R_Msk
17601
17602/******************** Bits definition for RTC_BKP28R register ***************/
17603#define RTC_BKP28R_Pos (0U)
17604#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
17605#define RTC_BKP28R RTC_BKP28R_Msk
17606
17607/******************** Bits definition for RTC_BKP29R register ***************/
17608#define RTC_BKP29R_Pos (0U)
17609#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
17610#define RTC_BKP29R RTC_BKP29R_Msk
17611
17612/******************** Bits definition for RTC_BKP30R register ***************/
17613#define RTC_BKP30R_Pos (0U)
17614#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
17615#define RTC_BKP30R RTC_BKP30R_Msk
17616
17617/******************** Bits definition for RTC_BKP31R register ***************/
17618#define RTC_BKP31R_Pos (0U)
17619#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
17620#define RTC_BKP31R RTC_BKP31R_Msk
17621
17622/******************** Number of backup registers ******************************/
17623#define RTC_BKP_NUMBER_Pos (5U)
17624#define RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos)
17625#define RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk
17626
17627/******************************************************************************/
17628/* */
17629/* SPDIF-RX Interface */
17630/* */
17631/******************************************************************************/
17632/******************** Bit definition for SPDIF_CR register ******************/
17633#define SPDIFRX_CR_SPDIFEN_Pos (0U)
17634#define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)
17635#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk
17636#define SPDIFRX_CR_RXDMAEN_Pos (2U)
17637#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)
17638#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk
17639#define SPDIFRX_CR_RXSTEO_Pos (3U)
17640#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos)
17641#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk
17642#define SPDIFRX_CR_DRFMT_Pos (4U)
17643#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos)
17644#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk
17645#define SPDIFRX_CR_PMSK_Pos (6U)
17646#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos)
17647#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk
17648#define SPDIFRX_CR_VMSK_Pos (7U)
17649#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos)
17650#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk
17651#define SPDIFRX_CR_CUMSK_Pos (8U)
17652#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos)
17653#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk
17654#define SPDIFRX_CR_PTMSK_Pos (9U)
17655#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos)
17656#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk
17657#define SPDIFRX_CR_CBDMAEN_Pos (10U)
17658#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)
17659#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk
17660#define SPDIFRX_CR_CHSEL_Pos (11U)
17661#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos)
17662#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk
17663#define SPDIFRX_CR_NBTR_Pos (12U)
17664#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos)
17665#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk
17666#define SPDIFRX_CR_WFA_Pos (14U)
17667#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos)
17668#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk
17669#define SPDIFRX_CR_INSEL_Pos (16U)
17670#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos)
17671#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk
17672#define SPDIFRX_CR_CKSEN_Pos (20U)
17673#define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos)
17674#define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk
17675#define SPDIFRX_CR_CKSBKPEN_Pos (21U)
17676#define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)
17677#define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk
17679/******************* Bit definition for SPDIFRX_IMR register *******************/
17680#define SPDIFRX_IMR_RXNEIE_Pos (0U)
17681#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)
17682#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk
17683#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
17684#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)
17685#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk
17686#define SPDIFRX_IMR_PERRIE_Pos (2U)
17687#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos)
17688#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk
17689#define SPDIFRX_IMR_OVRIE_Pos (3U)
17690#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos)
17691#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk
17692#define SPDIFRX_IMR_SBLKIE_Pos (4U)
17693#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)
17694#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk
17695#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
17696#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)
17697#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk
17698#define SPDIFRX_IMR_IFEIE_Pos (6U)
17699#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos)
17700#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk
17702/******************* Bit definition for SPDIFRX_SR register *******************/
17703#define SPDIFRX_SR_RXNE_Pos (0U)
17704#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos)
17705#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk
17706#define SPDIFRX_SR_CSRNE_Pos (1U)
17707#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos)
17708#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk
17709#define SPDIFRX_SR_PERR_Pos (2U)
17710#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos)
17711#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk
17712#define SPDIFRX_SR_OVR_Pos (3U)
17713#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos)
17714#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk
17715#define SPDIFRX_SR_SBD_Pos (4U)
17716#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos)
17717#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk
17718#define SPDIFRX_SR_SYNCD_Pos (5U)
17719#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos)
17720#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk
17721#define SPDIFRX_SR_FERR_Pos (6U)
17722#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos)
17723#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk
17724#define SPDIFRX_SR_SERR_Pos (7U)
17725#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos)
17726#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk
17727#define SPDIFRX_SR_TERR_Pos (8U)
17728#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos)
17729#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk
17730#define SPDIFRX_SR_WIDTH5_Pos (16U)
17731#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)
17732#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk
17734/******************* Bit definition for SPDIFRX_IFCR register *******************/
17735#define SPDIFRX_IFCR_PERRCF_Pos (2U)
17736#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)
17737#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk
17738#define SPDIFRX_IFCR_OVRCF_Pos (3U)
17739#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)
17740#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk
17741#define SPDIFRX_IFCR_SBDCF_Pos (4U)
17742#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)
17743#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk
17744#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
17745#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)
17746#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk
17748/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
17749#define SPDIFRX_DR0_DR_Pos (0U)
17750#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)
17751#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk
17752#define SPDIFRX_DR0_PE_Pos (24U)
17753#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos)
17754#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk
17755#define SPDIFRX_DR0_V_Pos (25U)
17756#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos)
17757#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk
17758#define SPDIFRX_DR0_U_Pos (26U)
17759#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos)
17760#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk
17761#define SPDIFRX_DR0_C_Pos (27U)
17762#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos)
17763#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk
17764#define SPDIFRX_DR0_PT_Pos (28U)
17765#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos)
17766#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk
17768/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
17769#define SPDIFRX_DR1_DR_Pos (8U)
17770#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)
17771#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk
17772#define SPDIFRX_DR1_PT_Pos (4U)
17773#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos)
17774#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk
17775#define SPDIFRX_DR1_C_Pos (3U)
17776#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos)
17777#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk
17778#define SPDIFRX_DR1_U_Pos (2U)
17779#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos)
17780#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk
17781#define SPDIFRX_DR1_V_Pos (1U)
17782#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos)
17783#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk
17784#define SPDIFRX_DR1_PE_Pos (0U)
17785#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos)
17786#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk
17788/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
17789#define SPDIFRX_DR1_DRNL1_Pos (16U)
17790#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)
17791#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk
17792#define SPDIFRX_DR1_DRNL2_Pos (0U)
17793#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)
17794#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk
17796/******************* Bit definition for SPDIFRX_CSR register *******************/
17797#define SPDIFRX_CSR_USR_Pos (0U)
17798#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos)
17799#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk
17800#define SPDIFRX_CSR_CS_Pos (16U)
17801#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos)
17802#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk
17803#define SPDIFRX_CSR_SOB_Pos (24U)
17804#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos)
17805#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk
17807/******************* Bit definition for SPDIFRX_DIR register *******************/
17808#define SPDIFRX_DIR_THI_Pos (0U)
17809#define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos)
17810#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk
17811#define SPDIFRX_DIR_TLO_Pos (16U)
17812#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)
17813#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk
17815/******************* Bit definition for SPDIFRX_VERR register *******************/
17816#define SPDIFRX_VERR_MINREV_Pos (0U)
17817#define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos)
17818#define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk
17819#define SPDIFRX_VERR_MAJREV_Pos (4U)
17820#define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos)
17821#define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk
17823/******************* Bit definition for SPDIFRX_IDR register *******************/
17824#define SPDIFRX_IDR_ID_Pos (0U)
17825#define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)
17826#define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk
17828/******************* Bit definition for SPDIFRX_SIDR register *******************/
17829#define SPDIFRX_SIDR_SID_Pos (0U)
17830#define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)
17831#define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk
17833/******************************************************************************/
17834/* */
17835/* Serial Audio Interface */
17836/* */
17837/******************************************************************************/
17838/******************************* SAI VERSION ********************************/
17839#define SAI_VER_V2_1
17840
17841/******************** Bit definition for SAI_GCR register *******************/
17842#define SAI_GCR_SYNCIN_Pos (0U)
17843#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
17844#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
17845#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
17846#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
17848#define SAI_GCR_SYNCOUT_Pos (4U)
17849#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
17850#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
17851#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
17852#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
17854/******************* Bit definition for SAI_xCR1 register *******************/
17855#define SAI_xCR1_MODE_Pos (0U)
17856#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
17857#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
17858#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
17859#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
17861#define SAI_xCR1_PRTCFG_Pos (2U)
17862#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
17863#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
17864#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
17865#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
17867#define SAI_xCR1_DS_Pos (5U)
17868#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
17869#define SAI_xCR1_DS SAI_xCR1_DS_Msk
17870#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
17871#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
17872#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
17874#define SAI_xCR1_LSBFIRST_Pos (8U)
17875#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
17876#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
17877#define SAI_xCR1_CKSTR_Pos (9U)
17878#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
17879#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
17881#define SAI_xCR1_SYNCEN_Pos (10U)
17882#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
17883#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
17884#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
17885#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
17887#define SAI_xCR1_MONO_Pos (12U)
17888#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
17889#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
17890#define SAI_xCR1_OUTDRIV_Pos (13U)
17891#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
17892#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
17893#define SAI_xCR1_SAIEN_Pos (16U)
17894#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
17895#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
17896#define SAI_xCR1_DMAEN_Pos (17U)
17897#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
17898#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
17899#define SAI_xCR1_NODIV_Pos (19U)
17900#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
17901#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
17903#define SAI_xCR1_MCKDIV_Pos (20U)
17904#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos)
17905#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
17906#define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos)
17907#define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos)
17908#define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos)
17909#define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos)
17910#define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos)
17911#define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos)
17913#define SAI_xCR1_MCKEN_Pos (27U)
17914#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos)
17915#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk
17917#define SAI_xCR1_OSR_Pos (26U)
17918#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos)
17919#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk
17921/* Legacy define */
17922#define SAI_xCR1_NOMCK SAI_xCR1_NODIV
17923
17924/******************* Bit definition for SAI_xCR2 register *******************/
17925#define SAI_xCR2_FTH_Pos (0U)
17926#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
17927#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
17928#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
17929#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
17930#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
17932#define SAI_xCR2_FFLUSH_Pos (3U)
17933#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
17934#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
17935#define SAI_xCR2_TRIS_Pos (4U)
17936#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
17937#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
17938#define SAI_xCR2_MUTE_Pos (5U)
17939#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
17940#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
17941#define SAI_xCR2_MUTEVAL_Pos (6U)
17942#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
17943#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
17945#define SAI_xCR2_MUTECNT_Pos (7U)
17946#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
17947#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
17948#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
17949#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
17950#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
17951#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
17952#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
17953#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
17955#define SAI_xCR2_CPL_Pos (13U)
17956#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
17957#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
17959#define SAI_xCR2_COMP_Pos (14U)
17960#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
17961#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
17962#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
17963#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
17965/****************** Bit definition for SAI_xFRCR register *******************/
17966#define SAI_xFRCR_FRL_Pos (0U)
17967#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
17968#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
17969#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
17970#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
17971#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
17972#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
17973#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
17974#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
17975#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
17976#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
17978#define SAI_xFRCR_FSALL_Pos (8U)
17979#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
17980#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
17981#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
17982#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
17983#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
17984#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
17985#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
17986#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
17987#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
17989#define SAI_xFRCR_FSDEF_Pos (16U)
17990#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
17991#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
17992#define SAI_xFRCR_FSPOL_Pos (17U)
17993#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
17994#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
17995#define SAI_xFRCR_FSOFF_Pos (18U)
17996#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
17997#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
17999/* Legacy define */
18000#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
18001
18002/****************** Bit definition for SAI_xSLOTR register *******************/
18003#define SAI_xSLOTR_FBOFF_Pos (0U)
18004#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
18005#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
18006#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
18007#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
18008#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
18009#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
18010#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
18012#define SAI_xSLOTR_SLOTSZ_Pos (6U)
18013#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
18014#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
18015#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
18016#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
18018#define SAI_xSLOTR_NBSLOT_Pos (8U)
18019#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
18020#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
18021#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
18022#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
18023#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
18024#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
18026#define SAI_xSLOTR_SLOTEN_Pos (16U)
18027#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
18028#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
18030/******************* Bit definition for SAI_xIMR register *******************/
18031#define SAI_xIMR_OVRUDRIE_Pos (0U)
18032#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
18033#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
18034#define SAI_xIMR_MUTEDETIE_Pos (1U)
18035#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
18036#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
18037#define SAI_xIMR_WCKCFGIE_Pos (2U)
18038#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
18039#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
18040#define SAI_xIMR_FREQIE_Pos (3U)
18041#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
18042#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
18043#define SAI_xIMR_CNRDYIE_Pos (4U)
18044#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
18045#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
18046#define SAI_xIMR_AFSDETIE_Pos (5U)
18047#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
18048#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
18049#define SAI_xIMR_LFSDETIE_Pos (6U)
18050#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
18051#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
18053/******************** Bit definition for SAI_xSR register *******************/
18054#define SAI_xSR_OVRUDR_Pos (0U)
18055#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
18056#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
18057#define SAI_xSR_MUTEDET_Pos (1U)
18058#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
18059#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
18060#define SAI_xSR_WCKCFG_Pos (2U)
18061#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
18062#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
18063#define SAI_xSR_FREQ_Pos (3U)
18064#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
18065#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
18066#define SAI_xSR_CNRDY_Pos (4U)
18067#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
18068#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
18069#define SAI_xSR_AFSDET_Pos (5U)
18070#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
18071#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
18072#define SAI_xSR_LFSDET_Pos (6U)
18073#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
18074#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
18076#define SAI_xSR_FLVL_Pos (16U)
18077#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
18078#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
18079#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
18080#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
18081#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
18083/****************** Bit definition for SAI_xCLRFR register ******************/
18084#define SAI_xCLRFR_COVRUDR_Pos (0U)
18085#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
18086#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
18087#define SAI_xCLRFR_CMUTEDET_Pos (1U)
18088#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
18089#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
18090#define SAI_xCLRFR_CWCKCFG_Pos (2U)
18091#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
18092#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
18093#define SAI_xCLRFR_CFREQ_Pos (3U)
18094#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
18095#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
18096#define SAI_xCLRFR_CCNRDY_Pos (4U)
18097#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
18098#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
18099#define SAI_xCLRFR_CAFSDET_Pos (5U)
18100#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
18101#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
18102#define SAI_xCLRFR_CLFSDET_Pos (6U)
18103#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
18104#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
18106/****************** Bit definition for SAI_xDR register *********************/
18107#define SAI_xDR_DATA_Pos (0U)
18108#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
18109#define SAI_xDR_DATA SAI_xDR_DATA_Msk
18110
18111/******************* Bit definition for SAI_PDMCR register ******************/
18112#define SAI_PDMCR_PDMEN_Pos (0U)
18113#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos)
18114#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk
18116#define SAI_PDMCR_MICNBR_Pos (4U)
18117#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos)
18118#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk
18119#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos)
18120#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos)
18122#define SAI_PDMCR_CKEN1_Pos (8U)
18123#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos)
18124#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk
18125#define SAI_PDMCR_CKEN2_Pos (9U)
18126#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos)
18127#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk
18128#define SAI_PDMCR_CKEN3_Pos (10U)
18129#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos)
18130#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk
18131#define SAI_PDMCR_CKEN4_Pos (11U)
18132#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos)
18133#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk
18135/****************** Bit definition for SAI_PDMDLY register ******************/
18136#define SAI_PDMDLY_DLYM1L_Pos (0U)
18137#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos)
18138#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk
18139#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)
18140#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)
18141#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)
18143#define SAI_PDMDLY_DLYM1R_Pos (4U)
18144#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos)
18145#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk
18146#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)
18147#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)
18148#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)
18150#define SAI_PDMDLY_DLYM2L_Pos (8U)
18151#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos)
18152#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk
18153#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)
18154#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)
18155#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)
18157#define SAI_PDMDLY_DLYM2R_Pos (12U)
18158#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos)
18159#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk
18160#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)
18161#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)
18162#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)
18164#define SAI_PDMDLY_DLYM3L_Pos (16U)
18165#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos)
18166#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk
18167#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)
18168#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)
18169#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)
18171#define SAI_PDMDLY_DLYM3R_Pos (20U)
18172#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos)
18173#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk
18174#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)
18175#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)
18176#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)
18178#define SAI_PDMDLY_DLYM4L_Pos (24U)
18179#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos)
18180#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk
18181#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)
18182#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)
18183#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)
18185#define SAI_PDMDLY_DLYM4R_Pos (28U)
18186#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos)
18187#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk
18188#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)
18189#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)
18190#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)
18192/******************************************************************************/
18193/* */
18194/* SDMMC Interface */
18195/* */
18196/******************************************************************************/
18197/****************** Bit definition for SDMMC_POWER register ******************/
18198#define SDMMC_POWER_PWRCTRL_Pos (0U)
18199#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
18200#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
18201#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
18202#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
18203#define SDMMC_POWER_VSWITCH_Pos (2U)
18204#define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos)
18205#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk
18206#define SDMMC_POWER_VSWITCHEN_Pos (3U)
18207#define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)
18208#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk
18209#define SDMMC_POWER_DIRPOL_Pos (4U)
18210#define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos)
18211#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk
18213/****************** Bit definition for SDMMC_CLKCR register ******************/
18214#define SDMMC_CLKCR_CLKDIV_Pos (0U)
18215#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)
18216#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
18217#define SDMMC_CLKCR_PWRSAV_Pos (12U)
18218#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
18219#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
18221#define SDMMC_CLKCR_WIDBUS_Pos (14U)
18222#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
18223#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
18224#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
18225#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
18227#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
18228#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
18229#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
18230#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
18231#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
18232#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
18233#define SDMMC_CLKCR_DDR_Pos (18U)
18234#define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos)
18235#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk
18236#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
18237#define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)
18238#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk
18239#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
18240#define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)
18241#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk
18242#define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)
18243#define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)
18245/******************* Bit definition for SDMMC_ARG register *******************/
18246#define SDMMC_ARG_CMDARG_Pos (0U)
18247#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
18248#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
18250/******************* Bit definition for SDMMC_CMD register *******************/
18251#define SDMMC_CMD_CMDINDEX_Pos (0U)
18252#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
18253#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
18254#define SDMMC_CMD_CMDTRANS_Pos (6U)
18255#define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos)
18256#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk
18257#define SDMMC_CMD_CMDSTOP_Pos (7U)
18258#define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos)
18259#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk
18261#define SDMMC_CMD_WAITRESP_Pos (8U)
18262#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
18263#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
18264#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
18265#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
18267#define SDMMC_CMD_WAITINT_Pos (10U)
18268#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
18269#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
18270#define SDMMC_CMD_WAITPEND_Pos (11U)
18271#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
18272#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
18273#define SDMMC_CMD_CPSMEN_Pos (12U)
18274#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
18275#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
18276#define SDMMC_CMD_DTHOLD_Pos (13U)
18277#define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos)
18278#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk
18279#define SDMMC_CMD_BOOTMODE_Pos (14U)
18280#define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos)
18281#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk
18282#define SDMMC_CMD_BOOTEN_Pos (15U)
18283#define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos)
18284#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk
18285#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
18286#define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)
18287#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk
18289/***************** Bit definition for SDMMC_RESPCMD register *****************/
18290#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
18291#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
18292#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
18294/****************** Bit definition for SDMMC_RESP0 register ******************/
18295#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
18296#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos)
18297#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk
18299/****************** Bit definition for SDMMC_RESP1 register ******************/
18300#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
18301#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
18302#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
18304/****************** Bit definition for SDMMC_RESP2 register ******************/
18305#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
18306#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
18307#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
18309/****************** Bit definition for SDMMC_RESP3 register ******************/
18310#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
18311#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
18312#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
18314/****************** Bit definition for SDMMC_RESP4 register ******************/
18315#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
18316#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
18317#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
18319/****************** Bit definition for SDMMC_DTIMER register *****************/
18320#define SDMMC_DTIMER_DATATIME_Pos (0U)
18321#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
18322#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
18324/****************** Bit definition for SDMMC_DLEN register *******************/
18325#define SDMMC_DLEN_DATALENGTH_Pos (0U)
18326#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
18327#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
18329/****************** Bit definition for SDMMC_DCTRL register ******************/
18330#define SDMMC_DCTRL_DTEN_Pos (0U)
18331#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
18332#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
18333#define SDMMC_DCTRL_DTDIR_Pos (1U)
18334#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
18335#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
18336#define SDMMC_DCTRL_DTMODE_Pos (2U)
18337#define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos)
18338#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
18339#define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
18340#define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos)
18342#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
18343#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18344#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
18345#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18346#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18347#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18348#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18350#define SDMMC_DCTRL_RWSTART_Pos (8U)
18351#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
18352#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
18353#define SDMMC_DCTRL_RWSTOP_Pos (9U)
18354#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
18355#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
18356#define SDMMC_DCTRL_RWMOD_Pos (10U)
18357#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
18358#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
18359#define SDMMC_DCTRL_SDIOEN_Pos (11U)
18360#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
18361#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
18362#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
18363#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)
18364#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk
18365#define SDMMC_DCTRL_FIFORST_Pos (13U)
18366#define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos)
18367#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk
18369/****************** Bit definition for SDMMC_DCOUNT register *****************/
18370#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
18371#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
18372#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
18374/****************** Bit definition for SDMMC_STA register ********************/
18375#define SDMMC_STA_CCRCFAIL_Pos (0U)
18376#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
18377#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
18378#define SDMMC_STA_DCRCFAIL_Pos (1U)
18379#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
18380#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
18381#define SDMMC_STA_CTIMEOUT_Pos (2U)
18382#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
18383#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
18384#define SDMMC_STA_DTIMEOUT_Pos (3U)
18385#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
18386#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
18387#define SDMMC_STA_TXUNDERR_Pos (4U)
18388#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
18389#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
18390#define SDMMC_STA_RXOVERR_Pos (5U)
18391#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
18392#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
18393#define SDMMC_STA_CMDREND_Pos (6U)
18394#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
18395#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
18396#define SDMMC_STA_CMDSENT_Pos (7U)
18397#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
18398#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
18399#define SDMMC_STA_DATAEND_Pos (8U)
18400#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
18401#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
18402#define SDMMC_STA_DHOLD_Pos (9U)
18403#define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos)
18404#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk
18405#define SDMMC_STA_DBCKEND_Pos (10U)
18406#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
18407#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
18408#define SDMMC_STA_DABORT_Pos (11U)
18409#define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos)
18410#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk
18411#define SDMMC_STA_DPSMACT_Pos (12U)
18412#define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos)
18413#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk
18414#define SDMMC_STA_CPSMACT_Pos (13U)
18415#define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos)
18416#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk
18417#define SDMMC_STA_TXFIFOHE_Pos (14U)
18418#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
18419#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
18420#define SDMMC_STA_RXFIFOHF_Pos (15U)
18421#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
18422#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
18423#define SDMMC_STA_TXFIFOF_Pos (16U)
18424#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
18425#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
18426#define SDMMC_STA_RXFIFOF_Pos (17U)
18427#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
18428#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
18429#define SDMMC_STA_TXFIFOE_Pos (18U)
18430#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
18431#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
18432#define SDMMC_STA_RXFIFOE_Pos (19U)
18433#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
18434#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
18435#define SDMMC_STA_BUSYD0_Pos (20U)
18436#define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos)
18437#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk
18438#define SDMMC_STA_BUSYD0END_Pos (21U)
18439#define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos)
18440#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk
18441#define SDMMC_STA_SDIOIT_Pos (22U)
18442#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
18443#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
18444#define SDMMC_STA_ACKFAIL_Pos (23U)
18445#define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos)
18446#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk
18447#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
18448#define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)
18449#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk
18450#define SDMMC_STA_VSWEND_Pos (25U)
18451#define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos)
18452#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk
18453#define SDMMC_STA_CKSTOP_Pos (26U)
18454#define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos)
18455#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk
18456#define SDMMC_STA_IDMATE_Pos (27U)
18457#define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos)
18458#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk
18459#define SDMMC_STA_IDMABTC_Pos (28U)
18460#define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos)
18461#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk
18463/******************* Bit definition for SDMMC_ICR register *******************/
18464#define SDMMC_ICR_CCRCFAILC_Pos (0U)
18465#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
18466#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
18467#define SDMMC_ICR_DCRCFAILC_Pos (1U)
18468#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
18469#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
18470#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
18471#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
18472#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
18473#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
18474#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
18475#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
18476#define SDMMC_ICR_TXUNDERRC_Pos (4U)
18477#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
18478#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
18479#define SDMMC_ICR_RXOVERRC_Pos (5U)
18480#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
18481#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
18482#define SDMMC_ICR_CMDRENDC_Pos (6U)
18483#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
18484#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
18485#define SDMMC_ICR_CMDSENTC_Pos (7U)
18486#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
18487#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
18488#define SDMMC_ICR_DATAENDC_Pos (8U)
18489#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
18490#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
18491#define SDMMC_ICR_DHOLDC_Pos (9U)
18492#define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos)
18493#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk
18494#define SDMMC_ICR_DBCKENDC_Pos (10U)
18495#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
18496#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
18497#define SDMMC_ICR_DABORTC_Pos (11U)
18498#define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos)
18499#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk
18500#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
18501#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)
18502#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk
18503#define SDMMC_ICR_SDIOITC_Pos (22U)
18504#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
18505#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
18506#define SDMMC_ICR_ACKFAILC_Pos (23U)
18507#define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos)
18508#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk
18509#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
18510#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)
18511#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk
18512#define SDMMC_ICR_VSWENDC_Pos (25U)
18513#define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos)
18514#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk
18515#define SDMMC_ICR_CKSTOPC_Pos (26U)
18516#define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos)
18517#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk
18518#define SDMMC_ICR_IDMATEC_Pos (27U)
18519#define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos)
18520#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk
18521#define SDMMC_ICR_IDMABTCC_Pos (28U)
18522#define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos)
18523#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk
18525/****************** Bit definition for SDMMC_MASK register *******************/
18526#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
18527#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
18528#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
18529#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
18530#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
18531#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
18532#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
18533#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
18534#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
18535#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
18536#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
18537#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
18538#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
18539#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
18540#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
18541#define SDMMC_MASK_RXOVERRIE_Pos (5U)
18542#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
18543#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
18544#define SDMMC_MASK_CMDRENDIE_Pos (6U)
18545#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
18546#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
18547#define SDMMC_MASK_CMDSENTIE_Pos (7U)
18548#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
18549#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
18550#define SDMMC_MASK_DATAENDIE_Pos (8U)
18551#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
18552#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
18553#define SDMMC_MASK_DHOLDIE_Pos (9U)
18554#define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos)
18555#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk
18556#define SDMMC_MASK_DBCKENDIE_Pos (10U)
18557#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
18558#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
18559#define SDMMC_MASK_DABORTIE_Pos (11U)
18560#define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos)
18561#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk
18563#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
18564#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
18565#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
18566#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
18567#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
18568#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
18570#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
18571#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
18572#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
18573#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
18574#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
18575#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
18577#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
18578#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)
18579#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk
18580#define SDMMC_MASK_SDIOITIE_Pos (22U)
18581#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
18582#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
18583#define SDMMC_MASK_ACKFAILIE_Pos (23U)
18584#define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)
18585#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk
18586#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
18587#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)
18588#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk
18589#define SDMMC_MASK_VSWENDIE_Pos (25U)
18590#define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos)
18591#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk
18592#define SDMMC_MASK_CKSTOPIE_Pos (26U)
18593#define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)
18594#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk
18595#define SDMMC_MASK_IDMABTCIE_Pos (28U)
18596#define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)
18597#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk
18599/***************** Bit definition for SDMMC_ACKTIME register *****************/
18600#define SDMMC_ACKTIME_ACKTIME_Pos (0U)
18601#define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos)
18602#define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk
18604/****************** Bit definition for SDMMC_FIFO register *******************/
18605#define SDMMC_FIFO_FIFODATA_Pos (0U)
18606#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
18607#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
18609/****************** Bit definition for SDMMC_IDMACTRL register ****************/
18610#define SDMMC_IDMA_IDMAEN_Pos (0U)
18611#define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos)
18612#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk
18613#define SDMMC_IDMA_IDMABMODE_Pos (1U)
18614#define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)
18615#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk
18616#define SDMMC_IDMA_IDMABACT_Pos (2U)
18617#define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos)
18618#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk
18620/***************** Bit definition for SDMMC_IDMABSIZE register ***************/
18621#define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
18622#define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos)
18623#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk
18625/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
18626#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU)
18628/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
18629#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU)
18631/******************************************************************************/
18632/* */
18633/* Delay Block Interface (DLYB) */
18634/* */
18635/******************************************************************************/
18636/******************* Bit definition for DLYB_CR register ********************/
18637#define DLYB_CR_DEN_Pos (0U)
18638#define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos)
18639#define DLYB_CR_DEN DLYB_CR_DEN_Msk
18640#define DLYB_CR_SEN_Pos (1U)
18641#define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos)
18642#define DLYB_CR_SEN DLYB_CR_SEN_Msk
18645/******************* Bit definition for DLYB_CFGR register ********************/
18646#define DLYB_CFGR_SEL_Pos (0U)
18647#define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos)
18648#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk
18649#define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos)
18650#define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos)
18651#define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos)
18652#define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos)
18654#define DLYB_CFGR_UNIT_Pos (8U)
18655#define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos)
18656#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk
18657#define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos)
18658#define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos)
18659#define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos)
18660#define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos)
18661#define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos)
18662#define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos)
18663#define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos)
18665#define DLYB_CFGR_LNG_Pos (16U)
18666#define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos)
18667#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk
18668#define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos)
18669#define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos)
18670#define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos)
18671#define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos)
18672#define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos)
18673#define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos)
18674#define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos)
18675#define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos)
18676#define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos)
18677#define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos)
18678#define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos)
18679#define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos)
18681#define DLYB_CFGR_LNGF_Pos (31U)
18682#define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos)
18683#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk
18685/******************************************************************************/
18686/* */
18687/* Serial Peripheral Interface (SPI/I2S) */
18688/* */
18689/******************************************************************************/
18690/******************* Bit definition for SPI_CR1 register ********************/
18691#define SPI_CR1_SPE_Pos (0U)
18692#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
18693#define SPI_CR1_SPE SPI_CR1_SPE_Msk
18694#define SPI_CR1_MASRX_Pos (8U)
18695#define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos)
18696#define SPI_CR1_MASRX SPI_CR1_MASRX_Msk
18697#define SPI_CR1_CSTART_Pos (9U)
18698#define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos)
18699#define SPI_CR1_CSTART SPI_CR1_CSTART_Msk
18700#define SPI_CR1_CSUSP_Pos (10U)
18701#define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos)
18702#define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk
18703#define SPI_CR1_HDDIR_Pos (11U)
18704#define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos)
18705#define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk
18706#define SPI_CR1_SSI_Pos (12U)
18707#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
18708#define SPI_CR1_SSI SPI_CR1_SSI_Msk
18709#define SPI_CR1_CRC33_17_Pos (13U)
18710#define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos)
18711#define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk
18712#define SPI_CR1_RCRCINI_Pos (14U)
18713#define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos)
18714#define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk
18715#define SPI_CR1_TCRCINI_Pos (15U)
18716#define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos)
18717#define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk
18718#define SPI_CR1_IOLOCK_Pos (16U)
18719#define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos)
18720#define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk
18722/******************* Bit definition for SPI_CR2 register ********************/
18723#define SPI_CR2_TSER_Pos (16U)
18724#define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos)
18725#define SPI_CR2_TSER SPI_CR2_TSER_Msk
18726#define SPI_CR2_TSIZE_Pos (0U)
18727#define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos)
18728#define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk
18730/******************* Bit definition for SPI_CFG1 register ********************/
18731#define SPI_CFG1_DSIZE_Pos (0U)
18732#define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos)
18733#define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk
18734#define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos)
18735#define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos)
18736#define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos)
18737#define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos)
18738#define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos)
18740#define SPI_CFG1_FTHLV_Pos (5U)
18741#define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos)
18742#define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk
18743#define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos)
18744#define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos)
18745#define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos)
18746#define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos)
18748#define SPI_CFG1_UDRCFG_Pos (9U)
18749#define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos)
18750#define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk
18751#define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos)
18752#define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos)
18755#define SPI_CFG1_UDRDET_Pos (11U)
18756#define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos)
18757#define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk
18758#define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos)
18759#define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos)
18761#define SPI_CFG1_RXDMAEN_Pos (14U)
18762#define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos)
18763#define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk
18764#define SPI_CFG1_TXDMAEN_Pos (15U)
18765#define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos)
18766#define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk
18768#define SPI_CFG1_CRCSIZE_Pos (16U)
18769#define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos)
18770#define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk
18771#define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos)
18772#define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos)
18773#define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos)
18774#define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos)
18775#define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos)
18777#define SPI_CFG1_CRCEN_Pos (22U)
18778#define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos)
18779#define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk
18781#define SPI_CFG1_MBR_Pos (28U)
18782#define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos)
18783#define SPI_CFG1_MBR SPI_CFG1_MBR_Msk
18784#define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos)
18785#define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos)
18786#define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos)
18788/******************* Bit definition for SPI_CFG2 register ********************/
18789#define SPI_CFG2_MSSI_Pos (0U)
18790#define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos)
18791#define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk
18792#define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos)
18793#define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos)
18794#define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos)
18795#define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos)
18797#define SPI_CFG2_MIDI_Pos (4U)
18798#define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos)
18799#define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk
18800#define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos)
18801#define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos)
18802#define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos)
18803#define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos)
18805#define SPI_CFG2_IOSWP_Pos (15U)
18806#define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos)
18807#define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk
18809#define SPI_CFG2_COMM_Pos (17U)
18810#define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos)
18811#define SPI_CFG2_COMM SPI_CFG2_COMM_Msk
18812#define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos)
18813#define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos)
18815#define SPI_CFG2_SP_Pos (19U)
18816#define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos)
18817#define SPI_CFG2_SP SPI_CFG2_SP_Msk
18818#define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos)
18819#define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos)
18820#define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos)
18822#define SPI_CFG2_MASTER_Pos (22U)
18823#define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos)
18824#define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk
18825#define SPI_CFG2_LSBFRST_Pos (23U)
18826#define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos)
18827#define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk
18828#define SPI_CFG2_CPHA_Pos (24U)
18829#define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos)
18830#define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk
18831#define SPI_CFG2_CPOL_Pos (25U)
18832#define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos)
18833#define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk
18834#define SPI_CFG2_SSM_Pos (26U)
18835#define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos)
18836#define SPI_CFG2_SSM SPI_CFG2_SSM_Msk
18838#define SPI_CFG2_SSIOP_Pos (28U)
18839#define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos)
18840#define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk
18841#define SPI_CFG2_SSOE_Pos (29U)
18842#define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos)
18843#define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk
18844#define SPI_CFG2_SSOM_Pos (30U)
18845#define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos)
18846#define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk
18848#define SPI_CFG2_AFCNTR_Pos (31U)
18849#define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos)
18850#define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk
18852/******************* Bit definition for SPI_IER register ********************/
18853#define SPI_IER_RXPIE_Pos (0U)
18854#define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos)
18855#define SPI_IER_RXPIE SPI_IER_RXPIE_Msk
18856#define SPI_IER_TXPIE_Pos (1U)
18857#define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos)
18858#define SPI_IER_TXPIE SPI_IER_TXPIE_Msk
18859#define SPI_IER_DXPIE_Pos (2U)
18860#define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos)
18861#define SPI_IER_DXPIE SPI_IER_DXPIE_Msk
18862#define SPI_IER_EOTIE_Pos (3U)
18863#define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos)
18864#define SPI_IER_EOTIE SPI_IER_EOTIE_Msk
18865#define SPI_IER_TXTFIE_Pos (4U)
18866#define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos)
18867#define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk
18868#define SPI_IER_UDRIE_Pos (5U)
18869#define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos)
18870#define SPI_IER_UDRIE SPI_IER_UDRIE_Msk
18871#define SPI_IER_OVRIE_Pos (6U)
18872#define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos)
18873#define SPI_IER_OVRIE SPI_IER_OVRIE_Msk
18874#define SPI_IER_CRCEIE_Pos (7U)
18875#define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos)
18876#define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk
18877#define SPI_IER_TIFREIE_Pos (8U)
18878#define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos)
18879#define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk
18880#define SPI_IER_MODFIE_Pos (9U)
18881#define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos)
18882#define SPI_IER_MODFIE SPI_IER_MODFIE_Msk
18883#define SPI_IER_TSERFIE_Pos (10U)
18884#define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos)
18885#define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk
18887/******************* Bit definition for SPI_SR register ********************/
18888#define SPI_SR_RXP_Pos (0U)
18889#define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos)
18890#define SPI_SR_RXP SPI_SR_RXP_Msk
18891#define SPI_SR_TXP_Pos (1U)
18892#define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos)
18893#define SPI_SR_TXP SPI_SR_TXP_Msk
18894#define SPI_SR_DXP_Pos (2U)
18895#define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos)
18896#define SPI_SR_DXP SPI_SR_DXP_Msk
18897#define SPI_SR_EOT_Pos (3U)
18898#define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos)
18899#define SPI_SR_EOT SPI_SR_EOT_Msk
18900#define SPI_SR_TXTF_Pos (4U)
18901#define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos)
18902#define SPI_SR_TXTF SPI_SR_TXTF_Msk
18903#define SPI_SR_UDR_Pos (5U)
18904#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
18905#define SPI_SR_UDR SPI_SR_UDR_Msk
18906#define SPI_SR_OVR_Pos (6U)
18907#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
18908#define SPI_SR_OVR SPI_SR_OVR_Msk
18909#define SPI_SR_CRCE_Pos (7U)
18910#define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos)
18911#define SPI_SR_CRCE SPI_SR_CRCE_Msk
18912#define SPI_SR_TIFRE_Pos (8U)
18913#define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos)
18914#define SPI_SR_TIFRE SPI_SR_TIFRE_Msk
18915#define SPI_SR_MODF_Pos (9U)
18916#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
18917#define SPI_SR_MODF SPI_SR_MODF_Msk
18918#define SPI_SR_TSERF_Pos (10U)
18919#define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos)
18920#define SPI_SR_TSERF SPI_SR_TSERF_Msk
18921#define SPI_SR_SUSP_Pos (11U)
18922#define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos)
18923#define SPI_SR_SUSP SPI_SR_SUSP_Msk
18924#define SPI_SR_TXC_Pos (12U)
18925#define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos)
18926#define SPI_SR_TXC SPI_SR_TXC_Msk
18927#define SPI_SR_RXPLVL_Pos (13U)
18928#define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos)
18929#define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk
18930#define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos)
18931#define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos)
18932#define SPI_SR_RXWNE_Pos (15U)
18933#define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos)
18934#define SPI_SR_RXWNE SPI_SR_RXWNE_Msk
18935#define SPI_SR_CTSIZE_Pos (16U)
18936#define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos)
18937#define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk
18939/******************* Bit definition for SPI_IFCR register ********************/
18940#define SPI_IFCR_EOTC_Pos (3U)
18941#define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos)
18942#define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk
18943#define SPI_IFCR_TXTFC_Pos (4U)
18944#define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos)
18945#define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk
18946#define SPI_IFCR_UDRC_Pos (5U)
18947#define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos)
18948#define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk
18949#define SPI_IFCR_OVRC_Pos (6U)
18950#define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos)
18951#define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk
18952#define SPI_IFCR_CRCEC_Pos (7U)
18953#define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos)
18954#define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk
18955#define SPI_IFCR_TIFREC_Pos (8U)
18956#define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos)
18957#define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk
18958#define SPI_IFCR_MODFC_Pos (9U)
18959#define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos)
18960#define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk
18961#define SPI_IFCR_TSERFC_Pos (10U)
18962#define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos)
18963#define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk
18964#define SPI_IFCR_SUSPC_Pos (11U)
18965#define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos)
18966#define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk
18968/******************* Bit definition for SPI_TXDR register ********************/
18969#define SPI_TXDR_TXDR_Pos (0U)
18970#define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)
18971#define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
18972
18973/******************* Bit definition for SPI_RXDR register ********************/
18974#define SPI_RXDR_RXDR_Pos (0U)
18975#define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)
18976#define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
18977
18978/******************* Bit definition for SPI_CRCPOLY register ********************/
18979#define SPI_CRCPOLY_CRCPOLY_Pos (0U)
18980#define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)
18981#define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
18982
18983/******************* Bit definition for SPI_TXCRC register ********************/
18984#define SPI_TXCRC_TXCRC_Pos (0U)
18985#define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)
18986#define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
18987
18988/******************* Bit definition for SPI_RXCRC register ********************/
18989#define SPI_RXCRC_RXCRC_Pos (0U)
18990#define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)
18991#define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
18992
18993/******************* Bit definition for SPI_UDRDR register ********************/
18994#define SPI_UDRDR_UDRDR_Pos (0U)
18995#define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)
18996#define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
18997
18998/****************** Bit definition for SPI_I2SCFGR register *****************/
18999#define SPI_I2SCFGR_I2SMOD_Pos (0U)
19000#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
19001#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
19002#define SPI_I2SCFGR_I2SCFG_Pos (1U)
19003#define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)
19004#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
19005#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
19006#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
19007#define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)
19008#define SPI_I2SCFGR_I2SSTD_Pos (4U)
19009#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
19010#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
19011#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
19012#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
19013#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
19014#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
19015#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
19016#define SPI_I2SCFGR_DATLEN_Pos (8U)
19017#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
19018#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
19019#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
19020#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
19021#define SPI_I2SCFGR_CHLEN_Pos (10U)
19022#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
19023#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
19024#define SPI_I2SCFGR_CKPOL_Pos (11U)
19025#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
19026#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
19027#define SPI_I2SCFGR_FIXCH_Pos (12U)
19028#define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos)
19029#define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk
19030#define SPI_I2SCFGR_WSINV_Pos (13U)
19031#define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos)
19032#define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk
19033#define SPI_I2SCFGR_DATFMT_Pos (14U)
19034#define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos)
19035#define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk
19036#define SPI_I2SCFGR_I2SDIV_Pos (16U)
19037#define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)
19038#define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk
19039#define SPI_I2SCFGR_ODD_Pos (24U)
19040#define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos)
19041#define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk
19042#define SPI_I2SCFGR_MCKOE_Pos (25U)
19043#define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos)
19044#define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk
19048/******************************************************************************/
19049/* */
19050/* SYSCFG */
19051/* */
19052/******************************************************************************/
19053
19054/****************** Bit definition for SYSCFG_PMCR register ******************/
19055#define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
19056#define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)
19057#define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk
19058#define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
19059#define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)
19060#define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk
19061#define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
19062#define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)
19063#define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk
19064#define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
19065#define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)
19066#define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk
19067#define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
19068#define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos)
19069#define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk
19070#define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
19071#define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos)
19072#define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk
19073#define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
19074#define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos)
19075#define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk
19076#define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
19077#define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos)
19078#define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk
19079#define SYSCFG_PMCR_BOOSTEN_Pos (8U)
19080#define SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)
19081#define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk
19083#define SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U)
19084#define SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos)
19085#define SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk
19087#define SYSCFG_PMCR_I2C5_FMP_Pos (10U)
19088#define SYSCFG_PMCR_I2C5_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C5_FMP_Pos)
19089#define SYSCFG_PMCR_I2C5_FMP SYSCFG_PMCR_I2C5_FMP_Msk
19091#define SYSCFG_PMCR_EPIS_SEL_Pos (21U)
19092#define SYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)
19093#define SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk
19094#define SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)
19095#define SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)
19096#define SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)
19097#define SYSCFG_PMCR_PA0SO_Pos (24U)
19098#define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos)
19099#define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk
19100#define SYSCFG_PMCR_PA1SO_Pos (25U)
19101#define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos)
19102#define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk
19103#define SYSCFG_PMCR_PC2SO_Pos (26U)
19104#define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos)
19105#define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk
19106#define SYSCFG_PMCR_PC3SO_Pos (27U)
19107#define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos)
19108#define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk
19110/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
19111#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
19112#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
19113#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
19114#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
19115#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
19116#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
19117#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
19118#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
19119#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
19120#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
19121#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
19122#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
19126#define SYSCFG_EXTICR1_EXTI0_PA (0U)
19127#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)
19128#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)
19129#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)
19130#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)
19131#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)
19132#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U)
19133#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U)
19134#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U)
19135#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU)
19140#define SYSCFG_EXTICR1_EXTI1_PA (0U)
19141#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)
19142#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)
19143#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)
19144#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)
19145#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)
19146#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U)
19147#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U)
19148#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U)
19149#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U)
19153#define SYSCFG_EXTICR1_EXTI2_PA (0U)
19154#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)
19155#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)
19156#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)
19157#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)
19158#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)
19159#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U)
19160#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U)
19161#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U)
19162#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U)
19167#define SYSCFG_EXTICR1_EXTI3_PA (0U)
19168#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)
19169#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)
19170#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)
19171#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)
19172#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U)
19173#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U)
19174#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U)
19175#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U)
19176#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U)
19178/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
19179#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
19180#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
19181#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
19182#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
19183#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
19184#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
19185#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
19186#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
19187#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
19188#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
19189#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
19190#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
19194#define SYSCFG_EXTICR2_EXTI4_PA (0U)
19195#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)
19196#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)
19197#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)
19198#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)
19199#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)
19200#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U)
19201#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U)
19202#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U)
19203#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU)
19207#define SYSCFG_EXTICR2_EXTI5_PA (0U)
19208#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)
19209#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)
19210#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)
19211#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)
19212#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)
19213#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U)
19214#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U)
19215#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U)
19216#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U)
19220#define SYSCFG_EXTICR2_EXTI6_PA (0U)
19221#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)
19222#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)
19223#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)
19224#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)
19225#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)
19226#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U)
19227#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U)
19228#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U)
19229#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U)
19234#define SYSCFG_EXTICR2_EXTI7_PA (0U)
19235#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)
19236#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)
19237#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)
19238#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)
19239#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U)
19240#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U)
19241#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U)
19242#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U)
19243#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U)
19245/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
19246#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
19247#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
19248#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
19249#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
19250#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
19251#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
19252#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
19253#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
19254#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
19255#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
19256#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
19257#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
19262#define SYSCFG_EXTICR3_EXTI8_PA (0U)
19263#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)
19264#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)
19265#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)
19266#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)
19267#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U)
19268#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U)
19269#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U)
19270#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U)
19271#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU)
19276#define SYSCFG_EXTICR3_EXTI9_PA (0U)
19277#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)
19278#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)
19279#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)
19280#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)
19281#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)
19282#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U)
19283#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U)
19284#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U)
19285#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U)
19290#define SYSCFG_EXTICR3_EXTI10_PA (0U)
19291#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)
19292#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)
19293#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)
19294#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)
19295#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)
19296#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U)
19297#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U)
19298#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U)
19299#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U)
19304#define SYSCFG_EXTICR3_EXTI11_PA (0U)
19305#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)
19306#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)
19307#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)
19308#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)
19309#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U)
19310#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U)
19311#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U)
19312#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U)
19313#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U)
19315/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
19316#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
19317#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
19318#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
19319#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
19320#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
19321#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
19322#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
19323#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
19324#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
19325#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
19326#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
19327#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
19331#define SYSCFG_EXTICR4_EXTI12_PA (0U)
19332#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)
19333#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)
19334#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)
19335#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)
19336#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U)
19337#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U)
19338#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U)
19339#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U)
19340#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU)
19344#define SYSCFG_EXTICR4_EXTI13_PA (0U)
19345#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)
19346#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)
19347#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)
19348#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)
19349#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U)
19350#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U)
19351#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U)
19352#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U)
19353#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U)
19357#define SYSCFG_EXTICR4_EXTI14_PA (0U)
19358#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)
19359#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)
19360#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)
19361#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)
19362#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U)
19363#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U)
19364#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U)
19365#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U)
19366#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U)
19370#define SYSCFG_EXTICR4_EXTI15_PA (0U)
19371#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)
19372#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)
19373#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)
19374#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)
19375#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U)
19376#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U)
19377#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U)
19378#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U)
19379#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U)
19381/****************** Bit definition for SYSCFG_CFGR register ******************/
19382#define SYSCFG_CFGR_PVDL_Pos (2U)
19383#define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos)
19384#define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk
19385#define SYSCFG_CFGR_FLASHL_Pos (3U)
19386#define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos)
19387#define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk
19388#define SYSCFG_CFGR_CM7L_Pos (6U)
19389#define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos)
19390#define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk
19391#define SYSCFG_CFGR_BKRAML_Pos (7U)
19392#define SYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos)
19393#define SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk
19394#define SYSCFG_CFGR_SRAM4L_Pos (9U)
19395#define SYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)
19396#define SYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk
19397#define SYSCFG_CFGR_SRAM2L_Pos (11U)
19398#define SYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)
19399#define SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk
19400#define SYSCFG_CFGR_SRAM1L_Pos (12U)
19401#define SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)
19402#define SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk
19403#define SYSCFG_CFGR_DTCML_Pos (13U)
19404#define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos)
19405#define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk
19406#define SYSCFG_CFGR_ITCML_Pos (14U)
19407#define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos)
19408#define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk
19409#define SYSCFG_CFGR_AXISRAML_Pos (15U)
19410#define SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)
19411#define SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk
19413/****************** Bit definition for SYSCFG_CCCSR register ******************/
19414#define SYSCFG_CCCSR_EN_Pos (0U)
19415#define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos)
19416#define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk
19417#define SYSCFG_CCCSR_CS_Pos (1U)
19418#define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos)
19419#define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk
19420#define SYSCFG_CCCSR_READY_Pos (8U)
19421#define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos)
19422#define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk
19423#define SYSCFG_CCCSR_HSLV_Pos (16U)
19424#define SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos)
19425#define SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk
19427/****************** Bit definition for SYSCFG_CCVR register *******************/
19428#define SYSCFG_CCVR_NCV_Pos (0U)
19429#define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos)
19430#define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk
19431#define SYSCFG_CCVR_PCV_Pos (4U)
19432#define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos)
19433#define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk
19435/****************** Bit definition for SYSCFG_CCCR register *******************/
19436#define SYSCFG_CCCR_NCC_Pos (0U)
19437#define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos)
19438#define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk
19439#define SYSCFG_CCCR_PCC_Pos (4U)
19440#define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos)
19441#define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk
19442/****************** Bit definition for SYSCFG_ADC2ALT register *******************/
19443#define SYSCFG_ADC2ALT_ADC2_ROUT0_Pos (0U)
19444#define SYSCFG_ADC2ALT_ADC2_ROUT0_Msk (0x1UL << SYSCFG_ADC2ALT_ADC2_ROUT0_Pos)
19445#define SYSCFG_ADC2ALT_ADC2_ROUT0 SYSCFG_ADC2ALT_ADC2_ROUT0_Msk
19446#define SYSCFG_ADC2ALT_ADC2_ROUT1_Pos (1U)
19447#define SYSCFG_ADC2ALT_ADC2_ROUT1_Msk (0x1UL << SYSCFG_ADC2ALT_ADC2_ROUT1_Pos)
19448#define SYSCFG_ADC2ALT_ADC2_ROUT1 SYSCFG_ADC2ALT_ADC2_ROUT1_Msk
19450/****************** Bit definition for SYSCFG_PKGR register *******************/
19451#define SYSCFG_PKGR_PKG_Pos (0U)
19452#define SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos)
19453#define SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk
19455/****************** Bit definition for SYSCFG_UR0 register *******************/
19456#define SYSCFG_UR0_RDP_Pos (16U)
19457#define SYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos)
19458#define SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk
19460/****************** Bit definition for SYSCFG_UR2 register *******************/
19461#define SYSCFG_UR2_BORH_Pos (0U)
19462#define SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos)
19463#define SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk
19464#define SYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos)
19465#define SYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos)
19466#define SYSCFG_UR2_BOOT_ADD0_Pos (16U)
19467#define SYSCFG_UR2_BOOT_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos)
19468#define SYSCFG_UR2_BOOT_ADD0 SYSCFG_UR2_BOOT_ADD0_Msk
19469/****************** Bit definition for SYSCFG_UR3 register *******************/
19470#define SYSCFG_UR3_BOOT_ADD1_Pos (0U)
19471#define SYSCFG_UR3_BOOT_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos)
19472#define SYSCFG_UR3_BOOT_ADD1 SYSCFG_UR3_BOOT_ADD1_Msk
19474 /****************** Bit definition for SYSCFG_UR4 register *******************/
19475
19476#define SYSCFG_UR4_MEPAD_BANK1_Pos (16U)
19477#define SYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)
19478#define SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk
19480/****************** Bit definition for SYSCFG_UR5 register *******************/
19481#define SYSCFG_UR5_MESAD_BANK1_Pos (0U)
19482#define SYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)
19483#define SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk
19484#define SYSCFG_UR5_WRPN_BANK1_Pos (16U)
19485#define SYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)
19486#define SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk
19488/****************** Bit definition for SYSCFG_UR6 register *******************/
19489#define SYSCFG_UR6_PABEG_BANK1_Pos (0U)
19490#define SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos)
19491#define SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk
19492#define SYSCFG_UR6_PAEND_BANK1_Pos (16U)
19493#define SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos)
19494#define SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk
19496/****************** Bit definition for SYSCFG_UR7 register *******************/
19497#define SYSCFG_UR7_SABEG_BANK1_Pos (0U)
19498#define SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos)
19499#define SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk
19500#define SYSCFG_UR7_SAEND_BANK1_Pos (16U)
19501#define SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos)
19502#define SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk
19505/****************** Bit definition for SYSCFG_UR11 register *******************/
19506#define SYSCFG_UR11_IWDG1M_Pos (16U)
19507#define SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos)
19508#define SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk
19510/****************** Bit definition for SYSCFG_UR12 register *******************/
19511
19512#define SYSCFG_UR12_SECURE_Pos (16U)
19513#define SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos)
19514#define SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk
19516/****************** Bit definition for SYSCFG_UR13 register *******************/
19517#define SYSCFG_UR13_SDRS_Pos (0U)
19518#define SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos)
19519#define SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk
19520#define SYSCFG_UR13_D1SBRST_Pos (16U)
19521#define SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos)
19522#define SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk
19524/****************** Bit definition for SYSCFG_UR14 register *******************/
19525#define SYSCFG_UR14_D1STPRST_Pos (0U)
19526#define SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos)
19527#define SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk
19529/****************** Bit definition for SYSCFG_UR15 register *******************/
19530#define SYSCFG_UR15_FZIWDGSTB_Pos (16U)
19531#define SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)
19532#define SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk
19534/****************** Bit definition for SYSCFG_UR16 register *******************/
19535#define SYSCFG_UR16_FZIWDGSTP_Pos (0U)
19536#define SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)
19537#define SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk
19538#define SYSCFG_UR16_PKP_Pos (16U)
19539#define SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos)
19540#define SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk
19542/****************** Bit definition for SYSCFG_UR17 register *******************/
19543#define SYSCFG_UR17_IOHSLV_Pos (0U)
19544#define SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos)
19545#define SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk
19546#define SYSCFG_UR17_TCM_AXI_CFG_Pos (16U)
19547#define SYSCFG_UR17_TCM_AXI_CFG_Msk (0x3UL << SYSCFG_UR17_TCM_AXI_CFG_Pos)
19548#define SYSCFG_UR17_TCM_AXI_CFG SYSCFG_UR17_TCM_AXI_CFG_Msk
19550/****************** Bit definition for SYSCFG_UR18 register *******************/
19551#define SYSCFG_UR18_CPU_FREQ_BOOST_Pos (0U)
19552#define SYSCFG_UR18_CPU_FREQ_BOOST_Msk (0x1UL << SYSCFG_UR18_CPU_FREQ_BOOST_Pos)
19553#define SYSCFG_UR18_CPU_FREQ_BOOST SYSCFG_UR18_CPU_FREQ_BOOST_Msk
19555/******************************************************************************/
19556/* */
19557/* Digital Temperature Sensor (DTS) */
19558/* */
19559/******************************************************************************/
19560
19561/****************** Bit definition for DTS_CFGR1 register ******************/
19562#define DTS_CFGR1_TS1_EN_Pos (0U)
19563#define DTS_CFGR1_TS1_EN_Msk (0x1UL << DTS_CFGR1_TS1_EN_Pos)
19564#define DTS_CFGR1_TS1_EN DTS_CFGR1_TS1_EN_Msk
19565#define DTS_CFGR1_TS1_START_Pos (4U)
19566#define DTS_CFGR1_TS1_START_Msk (0x1UL << DTS_CFGR1_TS1_START_Pos)
19567#define DTS_CFGR1_TS1_START DTS_CFGR1_TS1_START_Msk
19568#define DTS_CFGR1_TS1_INTRIG_SEL_Pos (8U)
19569#define DTS_CFGR1_TS1_INTRIG_SEL_Msk (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
19570#define DTS_CFGR1_TS1_INTRIG_SEL DTS_CFGR1_TS1_INTRIG_SEL_Msk
19571#define DTS_CFGR1_TS1_INTRIG_SEL_0 (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
19572#define DTS_CFGR1_TS1_INTRIG_SEL_1 (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
19573#define DTS_CFGR1_TS1_INTRIG_SEL_2 (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
19574#define DTS_CFGR1_TS1_INTRIG_SEL_3 (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
19575#define DTS_CFGR1_TS1_SMP_TIME_Pos (16U)
19576#define DTS_CFGR1_TS1_SMP_TIME_Msk (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos)
19577#define DTS_CFGR1_TS1_SMP_TIME DTS_CFGR1_TS1_SMP_TIME_Msk
19578#define DTS_CFGR1_TS1_SMP_TIME_0 (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
19579#define DTS_CFGR1_TS1_SMP_TIME_1 (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
19580#define DTS_CFGR1_TS1_SMP_TIME_2 (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
19581#define DTS_CFGR1_TS1_SMP_TIME_3 (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
19582#define DTS_CFGR1_REFCLK_SEL_Pos (20U)
19583#define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos)
19584#define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk
19585#define DTS_CFGR1_Q_MEAS_OPT_Pos (21U)
19586#define DTS_CFGR1_Q_MEAS_OPT_Msk (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos)
19587#define DTS_CFGR1_Q_MEAS_OPT DTS_CFGR1_Q_MEAS_OPT_Msk
19588#define DTS_CFGR1_HSREF_CLK_DIV_Pos (24U)
19589#define DTS_CFGR1_HSREF_CLK_DIV_Msk (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos)
19590#define DTS_CFGR1_HSREF_CLK_DIV DTS_CFGR1_HSREF_CLK_DIV_Msk
19592/****************** Bit definition for DTS_T0VALR1 register ******************/
19593#define DTS_T0VALR1_TS1_FMT0_Pos (0U)
19594#define DTS_T0VALR1_TS1_FMT0_Msk (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos)
19595#define DTS_T0VALR1_TS1_FMT0 DTS_T0VALR1_TS1_FMT0_Msk
19596#define DTS_T0VALR1_TS1_T0_Pos (16U)
19597#define DTS_T0VALR1_TS1_T0_Msk (0x3UL << DTS_T0VALR1_TS1_T0_Pos)
19598#define DTS_T0VALR1_TS1_T0 DTS_T0VALR1_TS1_T0_Msk
19600/****************** Bit definition for DTS_RAMPVALR register ******************/
19601#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos (0U)
19602#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos)
19603#define DTS_RAMPVALR_TS1_RAMP_COEFF DTS_RAMPVALR_TS1_RAMP_COEFF_Msk
19605/****************** Bit definition for DTS_ITR1 register ******************/
19606#define DTS_ITR1_TS1_LITTHD_Pos (0U)
19607#define DTS_ITR1_TS1_LITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos)
19608#define DTS_ITR1_TS1_LITTHD DTS_ITR1_TS1_LITTHD_Msk
19609#define DTS_ITR1_TS1_HITTHD_Pos (16U)
19610#define DTS_ITR1_TS1_HITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos)
19611#define DTS_ITR1_TS1_HITTHD DTS_ITR1_TS1_HITTHD_Msk
19613/****************** Bit definition for DTS_DR register ******************/
19614#define DTS_DR_TS1_MFREQ_Pos (0U)
19615#define DTS_DR_TS1_MFREQ_Msk (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos)
19616#define DTS_DR_TS1_MFREQ DTS_DR_TS1_MFREQ_Msk
19618/****************** Bit definition for DTS_SR register ******************/
19619#define DTS_SR_TS1_ITEF_Pos (0U)
19620#define DTS_SR_TS1_ITEF_Msk (0x1UL << DTS_SR_TS1_ITEF_Pos)
19621#define DTS_SR_TS1_ITEF DTS_SR_TS1_ITEF_Msk
19622#define DTS_SR_TS1_ITLF_Pos (1U)
19623#define DTS_SR_TS1_ITLF_Msk (0x1UL << DTS_SR_TS1_ITLF_Pos)
19624#define DTS_SR_TS1_ITLF DTS_SR_TS1_ITLF_Msk
19625#define DTS_SR_TS1_ITHF_Pos (2U)
19626#define DTS_SR_TS1_ITHF_Msk (0x1UL << DTS_SR_TS1_ITHF_Pos)
19627#define DTS_SR_TS1_ITHF DTS_SR_TS1_ITHF_Msk
19628#define DTS_SR_TS1_AITEF_Pos (4U)
19629#define DTS_SR_TS1_AITEF_Msk (0x1UL << DTS_SR_TS1_AITEF_Pos)
19630#define DTS_SR_TS1_AITEF DTS_SR_TS1_AITEF_Msk
19631#define DTS_SR_TS1_AITLF_Pos (5U)
19632#define DTS_SR_TS1_AITLF_Msk (0x1UL << DTS_SR_TS1_AITLF_Pos)
19633#define DTS_SR_TS1_AITLF DTS_SR_TS1_AITLF_Msk
19634#define DTS_SR_TS1_AITHF_Pos (6U)
19635#define DTS_SR_TS1_AITHF_Msk (0x1UL << DTS_SR_TS1_AITHF_Pos)
19636#define DTS_SR_TS1_AITHF DTS_SR_TS1_AITHF_Msk
19637#define DTS_SR_TS1_RDY_Pos (15U)
19638#define DTS_SR_TS1_RDY_Msk (0x1UL << DTS_SR_TS1_RDY_Pos)
19639#define DTS_SR_TS1_RDY DTS_SR_TS1_RDY_Msk
19641/****************** Bit definition for DTS_ITENR register ******************/
19642#define DTS_ITENR_TS1_ITEEN_Pos (0U)
19643#define DTS_ITENR_TS1_ITEEN_Msk (0x1UL << DTS_ITENR_TS1_ITEEN_Pos)
19644#define DTS_ITENR_TS1_ITEEN DTS_ITENR_TS1_ITEEN_Msk
19645#define DTS_ITENR_TS1_ITLEN_Pos (1U)
19646#define DTS_ITENR_TS1_ITLEN_Msk (0x1UL << DTS_ITENR_TS1_ITLEN_Pos)
19647#define DTS_ITENR_TS1_ITLEN DTS_ITENR_TS1_ITLEN_Msk
19648#define DTS_ITENR_TS1_ITHEN_Pos (2U)
19649#define DTS_ITENR_TS1_ITHEN_Msk (0x1UL << DTS_ITENR_TS1_ITHEN_Pos)
19650#define DTS_ITENR_TS1_ITHEN DTS_ITENR_TS1_ITHEN_Msk
19651#define DTS_ITENR_TS1_AITEEN_Pos (4U)
19652#define DTS_ITENR_TS1_AITEEN_Msk (0x1UL << DTS_ITENR_TS1_AITEEN_Pos)
19653#define DTS_ITENR_TS1_AITEEN DTS_ITENR_TS1_AITEEN_Msk
19654#define DTS_ITENR_TS1_AITLEN_Pos (5U)
19655#define DTS_ITENR_TS1_AITLEN_Msk (0x1UL << DTS_ITENR_TS1_AITLEN_Pos)
19656#define DTS_ITENR_TS1_AITLEN DTS_ITENR_TS1_AITLEN_Msk
19657#define DTS_ITENR_TS1_AITHEN_Pos (6U)
19658#define DTS_ITENR_TS1_AITHEN_Msk (0x1UL << DTS_ITENR_TS1_AITHEN_Pos)
19659#define DTS_ITENR_TS1_AITHEN DTS_ITENR_TS1_AITHEN_Msk
19661/****************** Bit definition for DTS_ICIFR register ******************/
19662#define DTS_ICIFR_TS1_CITEF_Pos (0U)
19663#define DTS_ICIFR_TS1_CITEF_Msk (0x1UL << DTS_ICIFR_TS1_CITEF_Pos)
19664#define DTS_ICIFR_TS1_CITEF DTS_ICIFR_TS1_CITEF_Msk
19665#define DTS_ICIFR_TS1_CITLF_Pos (1U)
19666#define DTS_ICIFR_TS1_CITLF_Msk (0x1UL << DTS_ICIFR_TS1_CITLF_Pos)
19667#define DTS_ICIFR_TS1_CITLF DTS_ICIFR_TS1_CITLF_Msk
19668#define DTS_ICIFR_TS1_CITHF_Pos (2U)
19669#define DTS_ICIFR_TS1_CITHF_Msk (0x1UL << DTS_ICIFR_TS1_CITHF_Pos)
19670#define DTS_ICIFR_TS1_CITHF DTS_ICIFR_TS1_CITHF_Msk
19671#define DTS_ICIFR_TS1_CAITEF_Pos (4U)
19672#define DTS_ICIFR_TS1_CAITEF_Msk (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos)
19673#define DTS_ICIFR_TS1_CAITEF DTS_ICIFR_TS1_CAITEF_Msk
19674#define DTS_ICIFR_TS1_CAITLF_Pos (5U)
19675#define DTS_ICIFR_TS1_CAITLF_Msk (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos)
19676#define DTS_ICIFR_TS1_CAITLF DTS_ICIFR_TS1_CAITLF_Msk
19677#define DTS_ICIFR_TS1_CAITHF_Pos (6U)
19678#define DTS_ICIFR_TS1_CAITHF_Msk (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos)
19679#define DTS_ICIFR_TS1_CAITHF DTS_ICIFR_TS1_CAITHF_Msk
19682/******************************************************************************/
19683/* */
19684/* TIM */
19685/* */
19686/******************************************************************************/
19687#define TIM_BREAK_INPUT_SUPPORT
19689/******************* Bit definition for TIM_CR1 register ********************/
19690#define TIM_CR1_CEN_Pos (0U)
19691#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
19692#define TIM_CR1_CEN TIM_CR1_CEN_Msk
19693#define TIM_CR1_UDIS_Pos (1U)
19694#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
19695#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
19696#define TIM_CR1_URS_Pos (2U)
19697#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
19698#define TIM_CR1_URS TIM_CR1_URS_Msk
19699#define TIM_CR1_OPM_Pos (3U)
19700#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
19701#define TIM_CR1_OPM TIM_CR1_OPM_Msk
19702#define TIM_CR1_DIR_Pos (4U)
19703#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
19704#define TIM_CR1_DIR TIM_CR1_DIR_Msk
19706#define TIM_CR1_CMS_Pos (5U)
19707#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
19708#define TIM_CR1_CMS TIM_CR1_CMS_Msk
19709#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
19710#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
19712#define TIM_CR1_ARPE_Pos (7U)
19713#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
19714#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
19716#define TIM_CR1_CKD_Pos (8U)
19717#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
19718#define TIM_CR1_CKD TIM_CR1_CKD_Msk
19719#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
19720#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
19722#define TIM_CR1_UIFREMAP_Pos (11U)
19723#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
19724#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
19726/******************* Bit definition for TIM_CR2 register ********************/
19727#define TIM_CR2_CCPC_Pos (0U)
19728#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
19729#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
19730#define TIM_CR2_CCUS_Pos (2U)
19731#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
19732#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
19733#define TIM_CR2_CCDS_Pos (3U)
19734#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
19735#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
19737#define TIM_CR2_MMS_Pos (4U)
19738#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
19739#define TIM_CR2_MMS TIM_CR2_MMS_Msk
19740#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
19741#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
19742#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
19744#define TIM_CR2_TI1S_Pos (7U)
19745#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
19746#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
19747#define TIM_CR2_OIS1_Pos (8U)
19748#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
19749#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
19750#define TIM_CR2_OIS1N_Pos (9U)
19751#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
19752#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
19753#define TIM_CR2_OIS2_Pos (10U)
19754#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
19755#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
19756#define TIM_CR2_OIS2N_Pos (11U)
19757#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
19758#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
19759#define TIM_CR2_OIS3_Pos (12U)
19760#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
19761#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
19762#define TIM_CR2_OIS3N_Pos (13U)
19763#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
19764#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
19765#define TIM_CR2_OIS4_Pos (14U)
19766#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
19767#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
19768#define TIM_CR2_OIS5_Pos (16U)
19769#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
19770#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
19771#define TIM_CR2_OIS6_Pos (18U)
19772#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
19773#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
19775#define TIM_CR2_MMS2_Pos (20U)
19776#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
19777#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
19778#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
19779#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
19780#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
19781#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
19783/******************* Bit definition for TIM_SMCR register *******************/
19784#define TIM_SMCR_SMS_Pos (0U)
19785#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
19786#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
19787#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
19788#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
19789#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
19790#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
19792#define TIM_SMCR_TS_Pos (4U)
19793#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos)
19794#define TIM_SMCR_TS TIM_SMCR_TS_Msk
19795#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos)
19796#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos)
19797#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos)
19798#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos)
19799#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos)
19801#define TIM_SMCR_MSM_Pos (7U)
19802#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
19803#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
19805#define TIM_SMCR_ETF_Pos (8U)
19806#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
19807#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
19808#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
19809#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
19810#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
19811#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
19813#define TIM_SMCR_ETPS_Pos (12U)
19814#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
19815#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
19816#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
19817#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
19819#define TIM_SMCR_ECE_Pos (14U)
19820#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
19821#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
19822#define TIM_SMCR_ETP_Pos (15U)
19823#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
19824#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
19826/******************* Bit definition for TIM_DIER register *******************/
19827#define TIM_DIER_UIE_Pos (0U)
19828#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
19829#define TIM_DIER_UIE TIM_DIER_UIE_Msk
19830#define TIM_DIER_CC1IE_Pos (1U)
19831#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
19832#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
19833#define TIM_DIER_CC2IE_Pos (2U)
19834#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
19835#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
19836#define TIM_DIER_CC3IE_Pos (3U)
19837#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
19838#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
19839#define TIM_DIER_CC4IE_Pos (4U)
19840#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
19841#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
19842#define TIM_DIER_COMIE_Pos (5U)
19843#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
19844#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
19845#define TIM_DIER_TIE_Pos (6U)
19846#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
19847#define TIM_DIER_TIE TIM_DIER_TIE_Msk
19848#define TIM_DIER_BIE_Pos (7U)
19849#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
19850#define TIM_DIER_BIE TIM_DIER_BIE_Msk
19851#define TIM_DIER_UDE_Pos (8U)
19852#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
19853#define TIM_DIER_UDE TIM_DIER_UDE_Msk
19854#define TIM_DIER_CC1DE_Pos (9U)
19855#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
19856#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
19857#define TIM_DIER_CC2DE_Pos (10U)
19858#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
19859#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
19860#define TIM_DIER_CC3DE_Pos (11U)
19861#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
19862#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
19863#define TIM_DIER_CC4DE_Pos (12U)
19864#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
19865#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
19866#define TIM_DIER_COMDE_Pos (13U)
19867#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
19868#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
19869#define TIM_DIER_TDE_Pos (14U)
19870#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
19871#define TIM_DIER_TDE TIM_DIER_TDE_Msk
19873/******************** Bit definition for TIM_SR register ********************/
19874#define TIM_SR_UIF_Pos (0U)
19875#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
19876#define TIM_SR_UIF TIM_SR_UIF_Msk
19877#define TIM_SR_CC1IF_Pos (1U)
19878#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
19879#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
19880#define TIM_SR_CC2IF_Pos (2U)
19881#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
19882#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
19883#define TIM_SR_CC3IF_Pos (3U)
19884#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
19885#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
19886#define TIM_SR_CC4IF_Pos (4U)
19887#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
19888#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
19889#define TIM_SR_COMIF_Pos (5U)
19890#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
19891#define TIM_SR_COMIF TIM_SR_COMIF_Msk
19892#define TIM_SR_TIF_Pos (6U)
19893#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
19894#define TIM_SR_TIF TIM_SR_TIF_Msk
19895#define TIM_SR_BIF_Pos (7U)
19896#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
19897#define TIM_SR_BIF TIM_SR_BIF_Msk
19898#define TIM_SR_B2IF_Pos (8U)
19899#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
19900#define TIM_SR_B2IF TIM_SR_B2IF_Msk
19901#define TIM_SR_CC1OF_Pos (9U)
19902#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
19903#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
19904#define TIM_SR_CC2OF_Pos (10U)
19905#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
19906#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
19907#define TIM_SR_CC3OF_Pos (11U)
19908#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
19909#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
19910#define TIM_SR_CC4OF_Pos (12U)
19911#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
19912#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
19913#define TIM_SR_CC5IF_Pos (16U)
19914#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
19915#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
19916#define TIM_SR_CC6IF_Pos (17U)
19917#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
19918#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
19919#define TIM_SR_SBIF_Pos (13U)
19920#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
19921#define TIM_SR_SBIF TIM_SR_SBIF_Msk
19923/******************* Bit definition for TIM_EGR register ********************/
19924#define TIM_EGR_UG_Pos (0U)
19925#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
19926#define TIM_EGR_UG TIM_EGR_UG_Msk
19927#define TIM_EGR_CC1G_Pos (1U)
19928#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
19929#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
19930#define TIM_EGR_CC2G_Pos (2U)
19931#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
19932#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
19933#define TIM_EGR_CC3G_Pos (3U)
19934#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
19935#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
19936#define TIM_EGR_CC4G_Pos (4U)
19937#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
19938#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
19939#define TIM_EGR_COMG_Pos (5U)
19940#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
19941#define TIM_EGR_COMG TIM_EGR_COMG_Msk
19942#define TIM_EGR_TG_Pos (6U)
19943#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
19944#define TIM_EGR_TG TIM_EGR_TG_Msk
19945#define TIM_EGR_BG_Pos (7U)
19946#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
19947#define TIM_EGR_BG TIM_EGR_BG_Msk
19948#define TIM_EGR_B2G_Pos (8U)
19949#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
19950#define TIM_EGR_B2G TIM_EGR_B2G_Msk
19953/****************** Bit definition for TIM_CCMR1 register *******************/
19954#define TIM_CCMR1_CC1S_Pos (0U)
19955#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
19956#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
19957#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
19958#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
19960#define TIM_CCMR1_OC1FE_Pos (2U)
19961#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
19962#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
19963#define TIM_CCMR1_OC1PE_Pos (3U)
19964#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
19965#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
19967#define TIM_CCMR1_OC1M_Pos (4U)
19968#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
19969#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
19970#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
19971#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
19972#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
19973#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
19975#define TIM_CCMR1_OC1CE_Pos (7U)
19976#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
19977#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
19979#define TIM_CCMR1_CC2S_Pos (8U)
19980#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
19981#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
19982#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
19983#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
19985#define TIM_CCMR1_OC2FE_Pos (10U)
19986#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
19987#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
19988#define TIM_CCMR1_OC2PE_Pos (11U)
19989#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
19990#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
19992#define TIM_CCMR1_OC2M_Pos (12U)
19993#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
19994#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
19995#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
19996#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
19997#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
19998#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
20000#define TIM_CCMR1_OC2CE_Pos (15U)
20001#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
20002#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
20004/*----------------------------------------------------------------------------*/
20005
20006#define TIM_CCMR1_IC1PSC_Pos (2U)
20007#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
20008#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
20009#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
20010#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
20012#define TIM_CCMR1_IC1F_Pos (4U)
20013#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
20014#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
20015#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
20016#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
20017#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
20018#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
20020#define TIM_CCMR1_IC2PSC_Pos (10U)
20021#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
20022#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
20023#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
20024#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
20026#define TIM_CCMR1_IC2F_Pos (12U)
20027#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
20028#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
20029#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
20030#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
20031#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
20032#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
20034/****************** Bit definition for TIM_CCMR2 register *******************/
20035#define TIM_CCMR2_CC3S_Pos (0U)
20036#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
20037#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
20038#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
20039#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
20041#define TIM_CCMR2_OC3FE_Pos (2U)
20042#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
20043#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
20044#define TIM_CCMR2_OC3PE_Pos (3U)
20045#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
20046#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
20048#define TIM_CCMR2_OC3M_Pos (4U)
20049#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
20050#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
20051#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
20052#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
20053#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
20054#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
20056#define TIM_CCMR2_OC3CE_Pos (7U)
20057#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
20058#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
20060#define TIM_CCMR2_CC4S_Pos (8U)
20061#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
20062#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
20063#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
20064#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
20066#define TIM_CCMR2_OC4FE_Pos (10U)
20067#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
20068#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
20069#define TIM_CCMR2_OC4PE_Pos (11U)
20070#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
20071#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
20073#define TIM_CCMR2_OC4M_Pos (12U)
20074#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
20075#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
20076#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
20077#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
20078#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
20079#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
20081#define TIM_CCMR2_OC4CE_Pos (15U)
20082#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
20083#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
20085/*----------------------------------------------------------------------------*/
20086
20087#define TIM_CCMR2_IC3PSC_Pos (2U)
20088#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
20089#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
20090#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
20091#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
20093#define TIM_CCMR2_IC3F_Pos (4U)
20094#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
20095#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
20096#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
20097#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
20098#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
20099#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
20101#define TIM_CCMR2_IC4PSC_Pos (10U)
20102#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
20103#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
20104#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
20105#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
20107#define TIM_CCMR2_IC4F_Pos (12U)
20108#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
20109#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
20110#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
20111#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
20112#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
20113#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
20115/******************* Bit definition for TIM_CCER register *******************/
20116#define TIM_CCER_CC1E_Pos (0U)
20117#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
20118#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
20119#define TIM_CCER_CC1P_Pos (1U)
20120#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
20121#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
20122#define TIM_CCER_CC1NE_Pos (2U)
20123#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
20124#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
20125#define TIM_CCER_CC1NP_Pos (3U)
20126#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
20127#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
20128#define TIM_CCER_CC2E_Pos (4U)
20129#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
20130#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
20131#define TIM_CCER_CC2P_Pos (5U)
20132#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
20133#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
20134#define TIM_CCER_CC2NE_Pos (6U)
20135#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
20136#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
20137#define TIM_CCER_CC2NP_Pos (7U)
20138#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
20139#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
20140#define TIM_CCER_CC3E_Pos (8U)
20141#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
20142#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
20143#define TIM_CCER_CC3P_Pos (9U)
20144#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
20145#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
20146#define TIM_CCER_CC3NE_Pos (10U)
20147#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
20148#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
20149#define TIM_CCER_CC3NP_Pos (11U)
20150#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
20151#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
20152#define TIM_CCER_CC4E_Pos (12U)
20153#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
20154#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
20155#define TIM_CCER_CC4P_Pos (13U)
20156#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
20157#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
20158#define TIM_CCER_CC4NP_Pos (15U)
20159#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
20160#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
20161#define TIM_CCER_CC5E_Pos (16U)
20162#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
20163#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
20164#define TIM_CCER_CC5P_Pos (17U)
20165#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
20166#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
20167#define TIM_CCER_CC6E_Pos (20U)
20168#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
20169#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
20170#define TIM_CCER_CC6P_Pos (21U)
20171#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
20172#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
20173/******************* Bit definition for TIM_CNT register ********************/
20174#define TIM_CNT_CNT_Pos (0U)
20175#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
20176#define TIM_CNT_CNT TIM_CNT_CNT_Msk
20177#define TIM_CNT_UIFCPY_Pos (31U)
20178#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
20179#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
20180/******************* Bit definition for TIM_PSC register ********************/
20181#define TIM_PSC_PSC_Pos (0U)
20182#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
20183#define TIM_PSC_PSC TIM_PSC_PSC_Msk
20185/******************* Bit definition for TIM_ARR register ********************/
20186#define TIM_ARR_ARR_Pos (0U)
20187#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
20188#define TIM_ARR_ARR TIM_ARR_ARR_Msk
20190/******************* Bit definition for TIM_RCR register ********************/
20191#define TIM_RCR_REP_Pos (0U)
20192#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
20193#define TIM_RCR_REP TIM_RCR_REP_Msk
20195/******************* Bit definition for TIM_CCR1 register *******************/
20196#define TIM_CCR1_CCR1_Pos (0U)
20197#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
20198#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
20200/******************* Bit definition for TIM_CCR2 register *******************/
20201#define TIM_CCR2_CCR2_Pos (0U)
20202#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
20203#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
20205/******************* Bit definition for TIM_CCR3 register *******************/
20206#define TIM_CCR3_CCR3_Pos (0U)
20207#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
20208#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
20210/******************* Bit definition for TIM_CCR4 register *******************/
20211#define TIM_CCR4_CCR4_Pos (0U)
20212#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
20213#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
20215/******************* Bit definition for TIM_CCR5 register *******************/
20216#define TIM_CCR5_CCR5_Pos (0U)
20217#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
20218#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
20219#define TIM_CCR5_GC5C1_Pos (29U)
20220#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
20221#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
20222#define TIM_CCR5_GC5C2_Pos (30U)
20223#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
20224#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
20225#define TIM_CCR5_GC5C3_Pos (31U)
20226#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
20227#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
20229/******************* Bit definition for TIM_CCR6 register *******************/
20230#define TIM_CCR6_CCR6_Pos (0U)
20231#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)
20232#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk
20234/******************* Bit definition for TIM_BDTR register *******************/
20235#define TIM_BDTR_DTG_Pos (0U)
20236#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
20237#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
20238#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
20239#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
20240#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
20241#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
20242#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
20243#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
20244#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
20245#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
20247#define TIM_BDTR_LOCK_Pos (8U)
20248#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
20249#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
20250#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
20251#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
20253#define TIM_BDTR_OSSI_Pos (10U)
20254#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
20255#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
20256#define TIM_BDTR_OSSR_Pos (11U)
20257#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
20258#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
20259#define TIM_BDTR_BKE_Pos (12U)
20260#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
20261#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
20262#define TIM_BDTR_BKP_Pos (13U)
20263#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
20264#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
20265#define TIM_BDTR_AOE_Pos (14U)
20266#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
20267#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
20268#define TIM_BDTR_MOE_Pos (15U)
20269#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
20270#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
20272#define TIM_BDTR_BKF_Pos (16U)
20273#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
20274#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
20275#define TIM_BDTR_BK2F_Pos (20U)
20276#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
20277#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
20279#define TIM_BDTR_BK2E_Pos (24U)
20280#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
20281#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
20282#define TIM_BDTR_BK2P_Pos (25U)
20283#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
20284#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
20285#define TIM_BDTR_BKDSRM_Pos (26U)
20286#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos)
20287#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk
20288#define TIM_BDTR_BK2DSRM_Pos (27U)
20289#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos)
20290#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk
20291#define TIM_BDTR_BKBID_Pos (28U)
20292#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos)
20293#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk
20294#define TIM_BDTR_BK2BID_Pos (29U)
20295#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos)
20296#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk
20298/******************* Bit definition for TIM_DCR register ********************/
20299#define TIM_DCR_DBA_Pos (0U)
20300#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
20301#define TIM_DCR_DBA TIM_DCR_DBA_Msk
20302#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
20303#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
20304#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
20305#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
20306#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
20308#define TIM_DCR_DBL_Pos (8U)
20309#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
20310#define TIM_DCR_DBL TIM_DCR_DBL_Msk
20311#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
20312#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
20313#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
20314#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
20315#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
20317/******************* Bit definition for TIM_DMAR register *******************/
20318#define TIM_DMAR_DMAB_Pos (0U)
20319#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
20320#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
20322/****************** Bit definition for TIM_CCMR3 register *******************/
20323#define TIM_CCMR3_OC5FE_Pos (2U)
20324#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
20325#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
20326#define TIM_CCMR3_OC5PE_Pos (3U)
20327#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
20328#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
20330#define TIM_CCMR3_OC5M_Pos (4U)
20331#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
20332#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
20333#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos)
20334#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos)
20335#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos)
20336#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
20338#define TIM_CCMR3_OC5CE_Pos (7U)
20339#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
20340#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
20342#define TIM_CCMR3_OC6FE_Pos (10U)
20343#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
20344#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
20345#define TIM_CCMR3_OC6PE_Pos (11U)
20346#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
20347#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
20349#define TIM_CCMR3_OC6M_Pos (12U)
20350#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
20351#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
20352#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos)
20353#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos)
20354#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos)
20355#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
20357#define TIM_CCMR3_OC6CE_Pos (15U)
20358#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
20359#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
20360/******************* Bit definition for TIM1_AF1 register *********************/
20361#define TIM1_AF1_BKINE_Pos (0U)
20362#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)
20363#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk
20364#define TIM1_AF1_BKCMP1E_Pos (1U)
20365#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos)
20366#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk
20367#define TIM1_AF1_BKCMP2E_Pos (2U)
20368#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos)
20369#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk
20370#define TIM1_AF1_BKDF1BK0E_Pos (8U)
20371#define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)
20372#define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk
20373#define TIM1_AF1_BKINP_Pos (9U)
20374#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)
20375#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk
20376#define TIM1_AF1_BKCMP1P_Pos (10U)
20377#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos)
20378#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk
20379#define TIM1_AF1_BKCMP2P_Pos (11U)
20380#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos)
20381#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk
20383#define TIM1_AF1_ETRSEL_Pos (14U)
20384#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos)
20385#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk
20386#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos)
20387#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos)
20388#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos)
20389#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos)
20391/******************* Bit definition for TIM1_AF2 register *********************/
20392#define TIM1_AF2_BK2INE_Pos (0U)
20393#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)
20394#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk
20395#define TIM1_AF2_BK2CMP1E_Pos (1U)
20396#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos)
20397#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk
20398#define TIM1_AF2_BK2CMP2E_Pos (2U)
20399#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos)
20400#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk
20401#define TIM1_AF2_BK2DFBK1E_Pos (8U)
20402#define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)
20403#define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk
20404#define TIM1_AF2_BK2INP_Pos (9U)
20405#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)
20406#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk
20407#define TIM1_AF2_BK2CMP1P_Pos (10U)
20408#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos)
20409#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk
20410#define TIM1_AF2_BK2CMP2P_Pos (11U)
20411#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos)
20412#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk
20414/******************* Bit definition for TIM_TISEL register *********************/
20415#define TIM_TISEL_TI1SEL_Pos (0U)
20416#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos)
20417#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk
20418#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos)
20419#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos)
20420#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos)
20421#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos)
20423#define TIM_TISEL_TI2SEL_Pos (8U)
20424#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos)
20425#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk
20426#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos)
20427#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos)
20428#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos)
20429#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos)
20431#define TIM_TISEL_TI3SEL_Pos (16U)
20432#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos)
20433#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk
20434#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos)
20435#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos)
20436#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos)
20437#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos)
20439#define TIM_TISEL_TI4SEL_Pos (24U)
20440#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos)
20441#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk
20442#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos)
20443#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos)
20444#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos)
20445#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos)
20447/******************* Bit definition for TIM8_AF1 register *********************/
20448#define TIM8_AF1_BKINE_Pos (0U)
20449#define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos)
20450#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk
20451#define TIM8_AF1_BKCMP1E_Pos (1U)
20452#define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos)
20453#define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk
20454#define TIM8_AF1_BKCMP2E_Pos (2U)
20455#define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos)
20456#define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk
20457#define TIM8_AF1_BKDFBK2E_Pos (8U)
20458#define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos)
20459#define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk
20460#define TIM8_AF1_BKINP_Pos (9U)
20461#define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos)
20462#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk
20463#define TIM8_AF1_BKCMP1P_Pos (10U)
20464#define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos)
20465#define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk
20466#define TIM8_AF1_BKCMP2P_Pos (11U)
20467#define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos)
20468#define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk
20470#define TIM8_AF1_ETRSEL_Pos (14U)
20471#define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos)
20472#define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk
20473#define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos)
20474#define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos)
20475#define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos)
20476#define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos)
20477/******************* Bit definition for TIM8_AF2 register *********************/
20478#define TIM8_AF2_BK2INE_Pos (0U)
20479#define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos)
20480#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk
20481#define TIM8_AF2_BK2CMP1E_Pos (1U)
20482#define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos)
20483#define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk
20484#define TIM8_AF2_BK2CMP2E_Pos (2U)
20485#define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos)
20486#define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk
20487#define TIM8_AF2_BK2DFBK3E_Pos (8U)
20488#define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)
20489#define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk
20490#define TIM8_AF2_BK2INP_Pos (9U)
20491#define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos)
20492#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk
20493#define TIM8_AF2_BK2CMP1P_Pos (10U)
20494#define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos)
20495#define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk
20496#define TIM8_AF2_BK2CMP2P_Pos (11U)
20497#define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos)
20498#define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk
20500/******************* Bit definition for TIM2_AF1 register *********************/
20501#define TIM2_AF1_ETRSEL_Pos (14U)
20502#define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos)
20503#define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk
20504#define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos)
20505#define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos)
20506#define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos)
20507#define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos)
20509/******************* Bit definition for TIM3_AF1 register *********************/
20510#define TIM3_AF1_ETRSEL_Pos (14U)
20511#define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos)
20512#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk
20513#define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos)
20514#define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos)
20515#define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos)
20516#define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos)
20518/******************* Bit definition for TIM5_AF1 register *********************/
20519#define TIM5_AF1_ETRSEL_Pos (14U)
20520#define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos)
20521#define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk
20522#define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos)
20523#define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos)
20524#define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos)
20525#define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos)
20527/******************* Bit definition for TIM15_AF1 register *********************/
20528#define TIM15_AF1_BKINE_Pos (0U)
20529#define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos)
20530#define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk
20531#define TIM15_AF1_BKCMP1E_Pos (1U)
20532#define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos)
20533#define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk
20534#define TIM15_AF1_BKCMP2E_Pos (2U)
20535#define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos)
20536#define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk
20537#define TIM15_AF1_BKDF1BK2E_Pos (8U)
20538#define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)
20539#define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk
20540#define TIM15_AF1_BKINP_Pos (9U)
20541#define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos)
20542#define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk
20543#define TIM15_AF1_BKCMP1P_Pos (10U)
20544#define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos)
20545#define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk
20546#define TIM15_AF1_BKCMP2P_Pos (11U)
20547#define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos)
20548#define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk
20550/******************* Bit definition for TIM16_ register *********************/
20551#define TIM16_AF1_BKINE_Pos (0U)
20552#define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos)
20553#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk
20554#define TIM16_AF1_BKCMP1E_Pos (1U)
20555#define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos)
20556#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk
20557#define TIM16_AF1_BKCMP2E_Pos (2U)
20558#define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos)
20559#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk
20560#define TIM16_AF1_BKDF1BK2E_Pos (8U)
20561#define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)
20562#define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk
20563#define TIM16_AF1_BKINP_Pos (9U)
20564#define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos)
20565#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk
20566#define TIM16_AF1_BKCMP1P_Pos (10U)
20567#define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos)
20568#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk
20569#define TIM16_AF1_BKCMP2P_Pos (11U)
20570#define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos)
20571#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk
20573/******************* Bit definition for TIM17_AF1 register *********************/
20574#define TIM17_AF1_BKINE_Pos (0U)
20575#define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos)
20576#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk
20577#define TIM17_AF1_BKCMP1E_Pos (1U)
20578#define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos)
20579#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk
20580#define TIM17_AF1_BKCMP2E_Pos (2U)
20581#define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos)
20582#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk
20583#define TIM17_AF1_BKDF1BK2E_Pos (8U)
20584#define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)
20585#define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk
20586#define TIM17_AF1_BKINP_Pos (9U)
20587#define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos)
20588#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk
20589#define TIM17_AF1_BKCMP1P_Pos (10U)
20590#define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos)
20591#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk
20592#define TIM17_AF1_BKCMP2P_Pos (11U)
20593#define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos)
20594#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk
20596/******************************************************************************/
20597/* */
20598/* Low Power Timer (LPTTIM) */
20599/* */
20600/******************************************************************************/
20601/****************** Bit definition for LPTIM_ISR register *******************/
20602#define LPTIM_ISR_CMPM_Pos (0U)
20603#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
20604#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
20605#define LPTIM_ISR_ARRM_Pos (1U)
20606#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
20607#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
20608#define LPTIM_ISR_EXTTRIG_Pos (2U)
20609#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
20610#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
20611#define LPTIM_ISR_CMPOK_Pos (3U)
20612#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
20613#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
20614#define LPTIM_ISR_ARROK_Pos (4U)
20615#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
20616#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
20617#define LPTIM_ISR_UP_Pos (5U)
20618#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
20619#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
20620#define LPTIM_ISR_DOWN_Pos (6U)
20621#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
20622#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
20624/****************** Bit definition for LPTIM_ICR register *******************/
20625#define LPTIM_ICR_CMPMCF_Pos (0U)
20626#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
20627#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
20628#define LPTIM_ICR_ARRMCF_Pos (1U)
20629#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
20630#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
20631#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
20632#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
20633#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
20634#define LPTIM_ICR_CMPOKCF_Pos (3U)
20635#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
20636#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
20637#define LPTIM_ICR_ARROKCF_Pos (4U)
20638#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
20639#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
20640#define LPTIM_ICR_UPCF_Pos (5U)
20641#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
20642#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
20643#define LPTIM_ICR_DOWNCF_Pos (6U)
20644#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
20645#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
20647/****************** Bit definition for LPTIM_IER register ********************/
20648#define LPTIM_IER_CMPMIE_Pos (0U)
20649#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
20650#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
20651#define LPTIM_IER_ARRMIE_Pos (1U)
20652#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
20653#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
20654#define LPTIM_IER_EXTTRIGIE_Pos (2U)
20655#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
20656#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
20657#define LPTIM_IER_CMPOKIE_Pos (3U)
20658#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
20659#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
20660#define LPTIM_IER_ARROKIE_Pos (4U)
20661#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
20662#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
20663#define LPTIM_IER_UPIE_Pos (5U)
20664#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
20665#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
20666#define LPTIM_IER_DOWNIE_Pos (6U)
20667#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
20668#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
20670/****************** Bit definition for LPTIM_CFGR register *******************/
20671#define LPTIM_CFGR_CKSEL_Pos (0U)
20672#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
20673#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
20675#define LPTIM_CFGR_CKPOL_Pos (1U)
20676#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
20677#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
20678#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
20679#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
20681#define LPTIM_CFGR_CKFLT_Pos (3U)
20682#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
20683#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
20684#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
20685#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
20687#define LPTIM_CFGR_TRGFLT_Pos (6U)
20688#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
20689#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
20690#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
20691#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
20693#define LPTIM_CFGR_PRESC_Pos (9U)
20694#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
20695#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
20696#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
20697#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
20698#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
20700#define LPTIM_CFGR_TRIGSEL_Pos (13U)
20701#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
20702#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
20703#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
20704#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
20705#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
20707#define LPTIM_CFGR_TRIGEN_Pos (17U)
20708#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
20709#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
20710#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
20711#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
20713#define LPTIM_CFGR_TIMOUT_Pos (19U)
20714#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
20715#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
20716#define LPTIM_CFGR_WAVE_Pos (20U)
20717#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
20718#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
20719#define LPTIM_CFGR_WAVPOL_Pos (21U)
20720#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
20721#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
20722#define LPTIM_CFGR_PRELOAD_Pos (22U)
20723#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
20724#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
20725#define LPTIM_CFGR_COUNTMODE_Pos (23U)
20726#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
20727#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
20728#define LPTIM_CFGR_ENC_Pos (24U)
20729#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
20730#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
20732/****************** Bit definition for LPTIM_CR register ********************/
20733#define LPTIM_CR_ENABLE_Pos (0U)
20734#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
20735#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
20736#define LPTIM_CR_SNGSTRT_Pos (1U)
20737#define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos)
20738#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
20739#define LPTIM_CR_CNTSTRT_Pos (2U)
20740#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
20741#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
20742#define LPTIM_CR_COUNTRST_Pos (3U)
20743#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos)
20744#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk
20745#define LPTIM_CR_RSTARE_Pos (4U)
20746#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos)
20747#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk
20750/****************** Bit definition for LPTIM_CMP register *******************/
20751#define LPTIM_CMP_CMP_Pos (0U)
20752#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
20753#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
20755/****************** Bit definition for LPTIM_ARR register *******************/
20756#define LPTIM_ARR_ARR_Pos (0U)
20757#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
20758#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
20760/****************** Bit definition for LPTIM_CNT register *******************/
20761#define LPTIM_CNT_CNT_Pos (0U)
20762#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
20763#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
20765/****************** Bit definition for LPTIM_CFGR2 register *****************/
20766#define LPTIM_CFGR2_IN1SEL_Pos (0U)
20767#define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)
20768#define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk
20769#define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)
20770#define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)
20771#define LPTIM_CFGR2_IN2SEL_Pos (4U)
20772#define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)
20773#define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk
20774#define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)
20775#define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)
20777/******************************************************************************/
20778/* */
20779/* OCTOSPI */
20780/* */
20781/******************************************************************************/
20782/***************** Bit definition for OCTOSPI_CR register *******************/
20783#define OCTOSPI_CR_EN_Pos (0U)
20784#define OCTOSPI_CR_EN_Msk (0x1UL << OCTOSPI_CR_EN_Pos)
20785#define OCTOSPI_CR_EN OCTOSPI_CR_EN_Msk
20786#define OCTOSPI_CR_ABORT_Pos (1U)
20787#define OCTOSPI_CR_ABORT_Msk (0x1UL << OCTOSPI_CR_ABORT_Pos)
20788#define OCTOSPI_CR_ABORT OCTOSPI_CR_ABORT_Msk
20789#define OCTOSPI_CR_DMAEN_Pos (2U)
20790#define OCTOSPI_CR_DMAEN_Msk (0x1UL << OCTOSPI_CR_DMAEN_Pos)
20791#define OCTOSPI_CR_DMAEN OCTOSPI_CR_DMAEN_Msk
20792#define OCTOSPI_CR_TCEN_Pos (3U)
20793#define OCTOSPI_CR_TCEN_Msk (0x1UL << OCTOSPI_CR_TCEN_Pos)
20794#define OCTOSPI_CR_TCEN OCTOSPI_CR_TCEN_Msk
20795#define OCTOSPI_CR_DQM_Pos (6U)
20796#define OCTOSPI_CR_DQM_Msk (0x1UL << OCTOSPI_CR_DQM_Pos)
20797#define OCTOSPI_CR_DQM OCTOSPI_CR_DQM_Msk
20798#define OCTOSPI_CR_FSEL_Pos (7U)
20799#define OCTOSPI_CR_FSEL_Msk (0x1UL << OCTOSPI_CR_FSEL_Pos)
20800#define OCTOSPI_CR_FSEL OCTOSPI_CR_FSEL_Msk
20801#define OCTOSPI_CR_FTHRES_Pos (8U)
20802#define OCTOSPI_CR_FTHRES_Msk (0x1FUL << OCTOSPI_CR_FTHRES_Pos)
20803#define OCTOSPI_CR_FTHRES OCTOSPI_CR_FTHRES_Msk
20804#define OCTOSPI_CR_TEIE_Pos (16U)
20805#define OCTOSPI_CR_TEIE_Msk (0x1UL << OCTOSPI_CR_TEIE_Pos)
20806#define OCTOSPI_CR_TEIE OCTOSPI_CR_TEIE_Msk
20807#define OCTOSPI_CR_TCIE_Pos (17U)
20808#define OCTOSPI_CR_TCIE_Msk (0x1UL << OCTOSPI_CR_TCIE_Pos)
20809#define OCTOSPI_CR_TCIE OCTOSPI_CR_TCIE_Msk
20810#define OCTOSPI_CR_FTIE_Pos (18U)
20811#define OCTOSPI_CR_FTIE_Msk (0x1UL << OCTOSPI_CR_FTIE_Pos)
20812#define OCTOSPI_CR_FTIE OCTOSPI_CR_FTIE_Msk
20813#define OCTOSPI_CR_SMIE_Pos (19U)
20814#define OCTOSPI_CR_SMIE_Msk (0x1UL << OCTOSPI_CR_SMIE_Pos)
20815#define OCTOSPI_CR_SMIE OCTOSPI_CR_SMIE_Msk
20816#define OCTOSPI_CR_TOIE_Pos (20U)
20817#define OCTOSPI_CR_TOIE_Msk (0x1UL << OCTOSPI_CR_TOIE_Pos)
20818#define OCTOSPI_CR_TOIE OCTOSPI_CR_TOIE_Msk
20819#define OCTOSPI_CR_APMS_Pos (22U)
20820#define OCTOSPI_CR_APMS_Msk (0x1UL << OCTOSPI_CR_APMS_Pos)
20821#define OCTOSPI_CR_APMS OCTOSPI_CR_APMS_Msk
20822#define OCTOSPI_CR_PMM_Pos (23U)
20823#define OCTOSPI_CR_PMM_Msk (0x1UL << OCTOSPI_CR_PMM_Pos)
20824#define OCTOSPI_CR_PMM OCTOSPI_CR_PMM_Msk
20825#define OCTOSPI_CR_FMODE_Pos (28U)
20826#define OCTOSPI_CR_FMODE_Msk (0x3UL << OCTOSPI_CR_FMODE_Pos)
20827#define OCTOSPI_CR_FMODE OCTOSPI_CR_FMODE_Msk
20828#define OCTOSPI_CR_FMODE_0 (0x1UL << OCTOSPI_CR_FMODE_Pos)
20829#define OCTOSPI_CR_FMODE_1 (0x2UL << OCTOSPI_CR_FMODE_Pos)
20831/**************** Bit definition for OCTOSPI_DCR1 register ******************/
20832#define OCTOSPI_DCR1_CKMODE_Pos (0U)
20833#define OCTOSPI_DCR1_CKMODE_Msk (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)
20834#define OCTOSPI_DCR1_CKMODE OCTOSPI_DCR1_CKMODE_Msk
20835#define OCTOSPI_DCR1_FRCK_Pos (1U)
20836#define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos)
20837#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk
20838#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
20839#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)
20840#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk
20841#define OCTOSPI_DCR1_CSHT_Pos (8U)
20842#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos)
20843#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk
20844#define OCTOSPI_DCR1_DEVSIZE_Pos (16U)
20845#define OCTOSPI_DCR1_DEVSIZE_Msk (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)
20846#define OCTOSPI_DCR1_DEVSIZE OCTOSPI_DCR1_DEVSIZE_Msk
20847#define OCTOSPI_DCR1_MTYP_Pos (24U)
20848#define OCTOSPI_DCR1_MTYP_Msk (0x7UL << OCTOSPI_DCR1_MTYP_Pos)
20849#define OCTOSPI_DCR1_MTYP OCTOSPI_DCR1_MTYP_Msk
20850#define OCTOSPI_DCR1_MTYP_0 (0x1UL << OCTOSPI_DCR1_MTYP_Pos)
20851#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos)
20852#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos)
20854/* Legacy define */
20855#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20856#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)
20857#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk
20859/**************** Bit definition for OCTOSPI_DCR2 register ******************/
20860#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
20861#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)
20862#define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk
20863#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U)
20864#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
20865#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk
20866#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
20867#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
20868#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
20870/**************** Bit definition for OCTOSPI_DCR3 register ******************/
20871#define OCTOSPI_DCR3_MAXTRAN_Pos (0U)
20872#define OCTOSPI_DCR3_MAXTRAN_Msk (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)
20873#define OCTOSPI_DCR3_MAXTRAN OCTOSPI_DCR3_MAXTRAN_Msk
20874#define OCTOSPI_DCR3_CSBOUND_Pos (16U)
20875#define OCTOSPI_DCR3_CSBOUND_Msk (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)
20876#define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk
20878/**************** Bit definition for OCTOSPI_DCR4 register ******************/
20879#define OCTOSPI_DCR4_REFRESH_Pos (0U)
20880#define OCTOSPI_DCR4_REFRESH_Msk (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos)
20881#define OCTOSPI_DCR4_REFRESH OCTOSPI_DCR4_REFRESH_Msk
20883/***************** Bit definition for OCTOSPI_SR register *******************/
20884#define OCTOSPI_SR_TEF_Pos (0U)
20885#define OCTOSPI_SR_TEF_Msk (0x1UL << OCTOSPI_SR_TEF_Pos)
20886#define OCTOSPI_SR_TEF OCTOSPI_SR_TEF_Msk
20887#define OCTOSPI_SR_TCF_Pos (1U)
20888#define OCTOSPI_SR_TCF_Msk (0x1UL << OCTOSPI_SR_TCF_Pos)
20889#define OCTOSPI_SR_TCF OCTOSPI_SR_TCF_Msk
20890#define OCTOSPI_SR_FTF_Pos (2U)
20891#define OCTOSPI_SR_FTF_Msk (0x1UL << OCTOSPI_SR_FTF_Pos)
20892#define OCTOSPI_SR_FTF OCTOSPI_SR_FTF_Msk
20893#define OCTOSPI_SR_SMF_Pos (3U)
20894#define OCTOSPI_SR_SMF_Msk (0x1UL << OCTOSPI_SR_SMF_Pos)
20895#define OCTOSPI_SR_SMF OCTOSPI_SR_SMF_Msk
20896#define OCTOSPI_SR_TOF_Pos (4U)
20897#define OCTOSPI_SR_TOF_Msk (0x1UL << OCTOSPI_SR_TOF_Pos)
20898#define OCTOSPI_SR_TOF OCTOSPI_SR_TOF_Msk
20899#define OCTOSPI_SR_BUSY_Pos (5U)
20900#define OCTOSPI_SR_BUSY_Msk (0x1UL << OCTOSPI_SR_BUSY_Pos)
20901#define OCTOSPI_SR_BUSY OCTOSPI_SR_BUSY_Msk
20902#define OCTOSPI_SR_FLEVEL_Pos (8U)
20903#define OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)
20904#define OCTOSPI_SR_FLEVEL OCTOSPI_SR_FLEVEL_Msk
20906/**************** Bit definition for OCTOSPI_FCR register *******************/
20907#define OCTOSPI_FCR_CTEF_Pos (0U)
20908#define OCTOSPI_FCR_CTEF_Msk (0x1UL << OCTOSPI_FCR_CTEF_Pos)
20909#define OCTOSPI_FCR_CTEF OCTOSPI_FCR_CTEF_Msk
20910#define OCTOSPI_FCR_CTCF_Pos (1U)
20911#define OCTOSPI_FCR_CTCF_Msk (0x1UL << OCTOSPI_FCR_CTCF_Pos)
20912#define OCTOSPI_FCR_CTCF OCTOSPI_FCR_CTCF_Msk
20913#define OCTOSPI_FCR_CSMF_Pos (3U)
20914#define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos)
20915#define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk
20916#define OCTOSPI_FCR_CTOF_Pos (4U)
20917#define OCTOSPI_FCR_CTOF_Msk (0x1UL << OCTOSPI_FCR_CTOF_Pos)
20918#define OCTOSPI_FCR_CTOF OCTOSPI_FCR_CTOF_Msk
20920/**************** Bit definition for OCTOSPI_DLR register *******************/
20921#define OCTOSPI_DLR_DL_Pos (0U)
20922#define OCTOSPI_DLR_DL_Msk (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)
20923#define OCTOSPI_DLR_DL OCTOSPI_DLR_DL_Msk
20925/***************** Bit definition for OCTOSPI_AR register *******************/
20926#define OCTOSPI_AR_ADDRESS_Pos (0U)
20927#define OCTOSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos)
20928#define OCTOSPI_AR_ADDRESS OCTOSPI_AR_ADDRESS_Msk
20930/***************** Bit definition for OCTOSPI_DR register *******************/
20931#define OCTOSPI_DR_DATA_Pos (0U)
20932#define OCTOSPI_DR_DATA_Msk (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)
20933#define OCTOSPI_DR_DATA OCTOSPI_DR_DATA_Msk
20935/*************** Bit definition for OCTOSPI_PSMKR register ******************/
20936#define OCTOSPI_PSMKR_MASK_Pos (0U)
20937#define OCTOSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos)
20938#define OCTOSPI_PSMKR_MASK OCTOSPI_PSMKR_MASK_Msk
20940/*************** Bit definition for OCTOSPI_PSMAR register ******************/
20941#define OCTOSPI_PSMAR_MATCH_Pos (0U)
20942#define OCTOSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos)
20943#define OCTOSPI_PSMAR_MATCH OCTOSPI_PSMAR_MATCH_Msk
20945/**************** Bit definition for OCTOSPI_PIR register *******************/
20946#define OCTOSPI_PIR_INTERVAL_Pos (0U)
20947#define OCTOSPI_PIR_INTERVAL_Msk (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)
20948#define OCTOSPI_PIR_INTERVAL OCTOSPI_PIR_INTERVAL_Msk
20950/**************** Bit definition for OCTOSPI_CCR register *******************/
20951#define OCTOSPI_CCR_IMODE_Pos (0U)
20952#define OCTOSPI_CCR_IMODE_Msk (0x7UL << OCTOSPI_CCR_IMODE_Pos)
20953#define OCTOSPI_CCR_IMODE OCTOSPI_CCR_IMODE_Msk
20954#define OCTOSPI_CCR_IMODE_0 (0x1UL << OCTOSPI_CCR_IMODE_Pos)
20955#define OCTOSPI_CCR_IMODE_1 (0x2UL << OCTOSPI_CCR_IMODE_Pos)
20956#define OCTOSPI_CCR_IMODE_2 (0x4UL << OCTOSPI_CCR_IMODE_Pos)
20957#define OCTOSPI_CCR_IDTR_Pos (3U)
20958#define OCTOSPI_CCR_IDTR_Msk (0x1UL << OCTOSPI_CCR_IDTR_Pos)
20959#define OCTOSPI_CCR_IDTR OCTOSPI_CCR_IDTR_Msk
20960#define OCTOSPI_CCR_ISIZE_Pos (4U)
20961#define OCTOSPI_CCR_ISIZE_Msk (0x3UL << OCTOSPI_CCR_ISIZE_Pos)
20962#define OCTOSPI_CCR_ISIZE OCTOSPI_CCR_ISIZE_Msk
20963#define OCTOSPI_CCR_ISIZE_0 (0x1UL << OCTOSPI_CCR_ISIZE_Pos)
20964#define OCTOSPI_CCR_ISIZE_1 (0x2UL << OCTOSPI_CCR_ISIZE_Pos)
20965#define OCTOSPI_CCR_ADMODE_Pos (8U)
20966#define OCTOSPI_CCR_ADMODE_Msk (0x7UL << OCTOSPI_CCR_ADMODE_Pos)
20967#define OCTOSPI_CCR_ADMODE OCTOSPI_CCR_ADMODE_Msk
20968#define OCTOSPI_CCR_ADMODE_0 (0x1UL << OCTOSPI_CCR_ADMODE_Pos)
20969#define OCTOSPI_CCR_ADMODE_1 (0x2UL << OCTOSPI_CCR_ADMODE_Pos)
20970#define OCTOSPI_CCR_ADMODE_2 (0x4UL << OCTOSPI_CCR_ADMODE_Pos)
20971#define OCTOSPI_CCR_ADDTR_Pos (11U)
20972#define OCTOSPI_CCR_ADDTR_Msk (0x1UL << OCTOSPI_CCR_ADDTR_Pos)
20973#define OCTOSPI_CCR_ADDTR OCTOSPI_CCR_ADDTR_Msk
20974#define OCTOSPI_CCR_ADSIZE_Pos (12U)
20975#define OCTOSPI_CCR_ADSIZE_Msk (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)
20976#define OCTOSPI_CCR_ADSIZE OCTOSPI_CCR_ADSIZE_Msk
20977#define OCTOSPI_CCR_ADSIZE_0 (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)
20978#define OCTOSPI_CCR_ADSIZE_1 (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)
20979#define OCTOSPI_CCR_ABMODE_Pos (16U)
20980#define OCTOSPI_CCR_ABMODE_Msk (0x7UL << OCTOSPI_CCR_ABMODE_Pos)
20981#define OCTOSPI_CCR_ABMODE OCTOSPI_CCR_ABMODE_Msk
20982#define OCTOSPI_CCR_ABMODE_0 (0x1UL << OCTOSPI_CCR_ABMODE_Pos)
20983#define OCTOSPI_CCR_ABMODE_1 (0x2UL << OCTOSPI_CCR_ABMODE_Pos)
20984#define OCTOSPI_CCR_ABMODE_2 (0x4UL << OCTOSPI_CCR_ABMODE_Pos)
20985#define OCTOSPI_CCR_ABDTR_Pos (19U)
20986#define OCTOSPI_CCR_ABDTR_Msk (0x1UL << OCTOSPI_CCR_ABDTR_Pos)
20987#define OCTOSPI_CCR_ABDTR OCTOSPI_CCR_ABDTR_Msk
20988#define OCTOSPI_CCR_ABSIZE_Pos (20U)
20989#define OCTOSPI_CCR_ABSIZE_Msk (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)
20990#define OCTOSPI_CCR_ABSIZE OCTOSPI_CCR_ABSIZE_Msk
20991#define OCTOSPI_CCR_ABSIZE_0 (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)
20992#define OCTOSPI_CCR_ABSIZE_1 (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)
20993#define OCTOSPI_CCR_DMODE_Pos (24U)
20994#define OCTOSPI_CCR_DMODE_Msk (0x7UL << OCTOSPI_CCR_DMODE_Pos)
20995#define OCTOSPI_CCR_DMODE OCTOSPI_CCR_DMODE_Msk
20996#define OCTOSPI_CCR_DMODE_0 (0x1UL << OCTOSPI_CCR_DMODE_Pos)
20997#define OCTOSPI_CCR_DMODE_1 (0x2UL << OCTOSPI_CCR_DMODE_Pos)
20998#define OCTOSPI_CCR_DMODE_2 (0x4UL << OCTOSPI_CCR_DMODE_Pos)
20999#define OCTOSPI_CCR_DDTR_Pos (27U)
21000#define OCTOSPI_CCR_DDTR_Msk (0x1UL << OCTOSPI_CCR_DDTR_Pos)
21001#define OCTOSPI_CCR_DDTR OCTOSPI_CCR_DDTR_Msk
21002#define OCTOSPI_CCR_DQSE_Pos (29U)
21003#define OCTOSPI_CCR_DQSE_Msk (0x1UL << OCTOSPI_CCR_DQSE_Pos)
21004#define OCTOSPI_CCR_DQSE OCTOSPI_CCR_DQSE_Msk
21005#define OCTOSPI_CCR_SIOO_Pos (31U)
21006#define OCTOSPI_CCR_SIOO_Msk (0x1UL << OCTOSPI_CCR_SIOO_Pos)
21007#define OCTOSPI_CCR_SIOO OCTOSPI_CCR_SIOO_Msk
21009/**************** Bit definition for OCTOSPI_TCR register *******************/
21010#define OCTOSPI_TCR_DCYC_Pos (0U)
21011#define OCTOSPI_TCR_DCYC_Msk (0x1FUL << OCTOSPI_TCR_DCYC_Pos)
21012#define OCTOSPI_TCR_DCYC OCTOSPI_TCR_DCYC_Msk
21013#define OCTOSPI_TCR_DHQC_Pos (28U)
21014#define OCTOSPI_TCR_DHQC_Msk (0x1UL << OCTOSPI_TCR_DHQC_Pos)
21015#define OCTOSPI_TCR_DHQC OCTOSPI_TCR_DHQC_Msk
21016#define OCTOSPI_TCR_SSHIFT_Pos (30U)
21017#define OCTOSPI_TCR_SSHIFT_Msk (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)
21018#define OCTOSPI_TCR_SSHIFT OCTOSPI_TCR_SSHIFT_Msk
21020/***************** Bit definition for OCTOSPI_IR register *******************/
21021#define OCTOSPI_IR_INSTRUCTION_Pos (0U)
21022#define OCTOSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos)
21023#define OCTOSPI_IR_INSTRUCTION OCTOSPI_IR_INSTRUCTION_Msk
21025/**************** Bit definition for OCTOSPI_ABR register *******************/
21026#define OCTOSPI_ABR_ALTERNATE_Pos (0U)
21027#define OCTOSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos)
21028#define OCTOSPI_ABR_ALTERNATE OCTOSPI_ABR_ALTERNATE_Msk
21030/**************** Bit definition for OCTOSPI_LPTR register ******************/
21031#define OCTOSPI_LPTR_TIMEOUT_Pos (0U)
21032#define OCTOSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)
21033#define OCTOSPI_LPTR_TIMEOUT OCTOSPI_LPTR_TIMEOUT_Msk
21035/**************** Bit definition for OCTOSPI_WPCCR register *******************/
21036#define OCTOSPI_WPCCR_IMODE_Pos (0U)
21037#define OCTOSPI_WPCCR_IMODE_Msk (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)
21038#define OCTOSPI_WPCCR_IMODE OCTOSPI_WPCCR_IMODE_Msk
21039#define OCTOSPI_WPCCR_IMODE_0 (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)
21040#define OCTOSPI_WPCCR_IMODE_1 (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)
21041#define OCTOSPI_WPCCR_IMODE_2 (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)
21042#define OCTOSPI_WPCCR_IDTR_Pos (3U)
21043#define OCTOSPI_WPCCR_IDTR_Msk (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)
21044#define OCTOSPI_WPCCR_IDTR OCTOSPI_WPCCR_IDTR_Msk
21045#define OCTOSPI_WPCCR_ISIZE_Pos (4U)
21046#define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)
21047#define OCTOSPI_WPCCR_ISIZE OCTOSPI_WPCCR_ISIZE_Msk
21048#define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)
21049#define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)
21050#define OCTOSPI_WPCCR_ADMODE_Pos (8U)
21051#define OCTOSPI_WPCCR_ADMODE_Msk (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)
21052#define OCTOSPI_WPCCR_ADMODE OCTOSPI_WPCCR_ADMODE_Msk
21053#define OCTOSPI_WPCCR_ADMODE_0 (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)
21054#define OCTOSPI_WPCCR_ADMODE_1 (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)
21055#define OCTOSPI_WPCCR_ADMODE_2 (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)
21056#define OCTOSPI_WPCCR_ADDTR_Pos (11U)
21057#define OCTOSPI_WPCCR_ADDTR_Msk (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)
21058#define OCTOSPI_WPCCR_ADDTR OCTOSPI_WPCCR_ADDTR_Msk
21059#define OCTOSPI_WPCCR_ADSIZE_Pos (12U)
21060#define OCTOSPI_WPCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)
21061#define OCTOSPI_WPCCR_ADSIZE OCTOSPI_WPCCR_ADSIZE_Msk
21062#define OCTOSPI_WPCCR_ADSIZE_0 (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)
21063#define OCTOSPI_WPCCR_ADSIZE_1 (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)
21064#define OCTOSPI_WPCCR_ABMODE_Pos (16U)
21065#define OCTOSPI_WPCCR_ABMODE_Msk (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)
21066#define OCTOSPI_WPCCR_ABMODE OCTOSPI_WPCCR_ABMODE_Msk
21067#define OCTOSPI_WPCCR_ABMODE_0 (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)
21068#define OCTOSPI_WPCCR_ABMODE_1 (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)
21069#define OCTOSPI_WPCCR_ABMODE_2 (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)
21070#define OCTOSPI_WPCCR_ABDTR_Pos (19U)
21071#define OCTOSPI_WPCCR_ABDTR_Msk (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)
21072#define OCTOSPI_WPCCR_ABDTR OCTOSPI_WPCCR_ABDTR_Msk
21073#define OCTOSPI_WPCCR_ABSIZE_Pos (20U)
21074#define OCTOSPI_WPCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)
21075#define OCTOSPI_WPCCR_ABSIZE OCTOSPI_WPCCR_ABSIZE_Msk
21076#define OCTOSPI_WPCCR_ABSIZE_0 (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)
21077#define OCTOSPI_WPCCR_ABSIZE_1 (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)
21078#define OCTOSPI_WPCCR_DMODE_Pos (24U)
21079#define OCTOSPI_WPCCR_DMODE_Msk (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)
21080#define OCTOSPI_WPCCR_DMODE OCTOSPI_WPCCR_DMODE_Msk
21081#define OCTOSPI_WPCCR_DMODE_0 (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)
21082#define OCTOSPI_WPCCR_DMODE_1 (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)
21083#define OCTOSPI_WPCCR_DMODE_2 (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)
21084#define OCTOSPI_WPCCR_DDTR_Pos (27U)
21085#define OCTOSPI_WPCCR_DDTR_Msk (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)
21086#define OCTOSPI_WPCCR_DDTR OCTOSPI_WPCCR_DDTR_Msk
21087#define OCTOSPI_WPCCR_DQSE_Pos (29U)
21088#define OCTOSPI_WPCCR_DQSE_Msk (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)
21089#define OCTOSPI_WPCCR_DQSE OCTOSPI_WPCCR_DQSE_Msk
21090#define OCTOSPI_WPCCR_SIOO_Pos (31U)
21091#define OCTOSPI_WPCCR_SIOO_Msk (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)
21092#define OCTOSPI_WPCCR_SIOO OCTOSPI_WPCCR_SIOO_Msk
21094/**************** Bit definition for OCTOSPI_WPTCR register *******************/
21095#define OCTOSPI_WPTCR_DCYC_Pos (0U)
21096#define OCTOSPI_WPTCR_DCYC_Msk (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)
21097#define OCTOSPI_WPTCR_DCYC OCTOSPI_WPTCR_DCYC_Msk
21098#define OCTOSPI_WPTCR_DHQC_Pos (28U)
21099#define OCTOSPI_WPTCR_DHQC_Msk (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)
21100#define OCTOSPI_WPTCR_DHQC OCTOSPI_WPTCR_DHQC_Msk
21101#define OCTOSPI_WPTCR_SSHIFT_Pos (30U)
21102#define OCTOSPI_WPTCR_SSHIFT_Msk (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)
21103#define OCTOSPI_WPTCR_SSHIFT OCTOSPI_WPTCR_SSHIFT_Msk
21105/***************** Bit definition for OCTOSPI_WPIR register *******************/
21106#define OCTOSPI_WPIR_INSTRUCTION_Pos (0U)
21107#define OCTOSPI_WPIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos)
21108#define OCTOSPI_WPIR_INSTRUCTION OCTOSPI_WPIR_INSTRUCTION_Msk
21110/**************** Bit definition for OCTOSPI_WPABR register *******************/
21111#define OCTOSPI_WPABR_ALTERNATE_Pos (0U)
21112#define OCTOSPI_WPABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos)
21113#define OCTOSPI_WPABR_ALTERNATE OCTOSPI_WPABR_ALTERNATE_Msk
21115/**************** Bit definition for OCTOSPI_WCCR register ******************/
21116#define OCTOSPI_WCCR_IMODE_Pos (0U)
21117#define OCTOSPI_WCCR_IMODE_Msk (0x7UL << OCTOSPI_WCCR_IMODE_Pos)
21118#define OCTOSPI_WCCR_IMODE OCTOSPI_WCCR_IMODE_Msk
21119#define OCTOSPI_WCCR_IMODE_0 (0x1UL << OCTOSPI_WCCR_IMODE_Pos)
21120#define OCTOSPI_WCCR_IMODE_1 (0x2UL << OCTOSPI_WCCR_IMODE_Pos)
21121#define OCTOSPI_WCCR_IMODE_2 (0x4UL << OCTOSPI_WCCR_IMODE_Pos)
21122#define OCTOSPI_WCCR_IDTR_Pos (3U)
21123#define OCTOSPI_WCCR_IDTR_Msk (0x1UL << OCTOSPI_WCCR_IDTR_Pos)
21124#define OCTOSPI_WCCR_IDTR OCTOSPI_WCCR_IDTR_Msk
21125#define OCTOSPI_WCCR_ISIZE_Pos (4U)
21126#define OCTOSPI_WCCR_ISIZE_Msk (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)
21127#define OCTOSPI_WCCR_ISIZE OCTOSPI_WCCR_ISIZE_Msk
21128#define OCTOSPI_WCCR_ISIZE_0 (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)
21129#define OCTOSPI_WCCR_ISIZE_1 (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)
21130#define OCTOSPI_WCCR_ADMODE_Pos (8U)
21131#define OCTOSPI_WCCR_ADMODE_Msk (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)
21132#define OCTOSPI_WCCR_ADMODE OCTOSPI_WCCR_ADMODE_Msk
21133#define OCTOSPI_WCCR_ADMODE_0 (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)
21134#define OCTOSPI_WCCR_ADMODE_1 (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)
21135#define OCTOSPI_WCCR_ADMODE_2 (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)
21136#define OCTOSPI_WCCR_ADDTR_Pos (11U)
21137#define OCTOSPI_WCCR_ADDTR_Msk (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)
21138#define OCTOSPI_WCCR_ADDTR OCTOSPI_WCCR_ADDTR_Msk
21139#define OCTOSPI_WCCR_ADSIZE_Pos (12U)
21140#define OCTOSPI_WCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)
21141#define OCTOSPI_WCCR_ADSIZE OCTOSPI_WCCR_ADSIZE_Msk
21142#define OCTOSPI_WCCR_ADSIZE_0 (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)
21143#define OCTOSPI_WCCR_ADSIZE_1 (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)
21144#define OCTOSPI_WCCR_ABMODE_Pos (16U)
21145#define OCTOSPI_WCCR_ABMODE_Msk (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)
21146#define OCTOSPI_WCCR_ABMODE OCTOSPI_WCCR_ABMODE_Msk
21147#define OCTOSPI_WCCR_ABMODE_0 (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)
21148#define OCTOSPI_WCCR_ABMODE_1 (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)
21149#define OCTOSPI_WCCR_ABMODE_2 (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)
21150#define OCTOSPI_WCCR_ABDTR_Pos (19U)
21151#define OCTOSPI_WCCR_ABDTR_Msk (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)
21152#define OCTOSPI_WCCR_ABDTR OCTOSPI_WCCR_ABDTR_Msk
21153#define OCTOSPI_WCCR_ABSIZE_Pos (20U)
21154#define OCTOSPI_WCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)
21155#define OCTOSPI_WCCR_ABSIZE OCTOSPI_WCCR_ABSIZE_Msk
21156#define OCTOSPI_WCCR_ABSIZE_0 (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)
21157#define OCTOSPI_WCCR_ABSIZE_1 (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)
21158#define OCTOSPI_WCCR_DMODE_Pos (24U)
21159#define OCTOSPI_WCCR_DMODE_Msk (0x7UL << OCTOSPI_WCCR_DMODE_Pos)
21160#define OCTOSPI_WCCR_DMODE OCTOSPI_WCCR_DMODE_Msk
21161#define OCTOSPI_WCCR_DMODE_0 (0x1UL << OCTOSPI_WCCR_DMODE_Pos)
21162#define OCTOSPI_WCCR_DMODE_1 (0x2UL << OCTOSPI_WCCR_DMODE_Pos)
21163#define OCTOSPI_WCCR_DMODE_2 (0x4UL << OCTOSPI_WCCR_DMODE_Pos)
21164#define OCTOSPI_WCCR_DDTR_Pos (27U)
21165#define OCTOSPI_WCCR_DDTR_Msk (0x1UL << OCTOSPI_WCCR_DDTR_Pos)
21166#define OCTOSPI_WCCR_DDTR OCTOSPI_WCCR_DDTR_Msk
21167#define OCTOSPI_WCCR_DQSE_Pos (29U)
21168#define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos)
21169#define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk
21170#define OCTOSPI_WCCR_SIOO_Pos (31U)
21171#define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos)
21172#define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk
21174/**************** Bit definition for OCTOSPI_WTCR register ******************/
21175#define OCTOSPI_WTCR_DCYC_Pos (0U)
21176#define OCTOSPI_WTCR_DCYC_Msk (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)
21177#define OCTOSPI_WTCR_DCYC OCTOSPI_WTCR_DCYC_Msk
21179/**************** Bit definition for OCTOSPI_WIR register *******************/
21180#define OCTOSPI_WIR_INSTRUCTION_Pos (0U)
21181#define OCTOSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos)
21182#define OCTOSPI_WIR_INSTRUCTION OCTOSPI_WIR_INSTRUCTION_Msk
21184/**************** Bit definition for OCTOSPI_WABR register ******************/
21185#define OCTOSPI_WABR_ALTERNATE_Pos (0U)
21186#define OCTOSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos)
21187#define OCTOSPI_WABR_ALTERNATE OCTOSPI_WABR_ALTERNATE_Msk
21189/**************** Bit definition for OCTOSPI_HLCR register ******************/
21190#define OCTOSPI_HLCR_LM_Pos (0U)
21191#define OCTOSPI_HLCR_LM_Msk (0x1UL << OCTOSPI_HLCR_LM_Pos)
21192#define OCTOSPI_HLCR_LM OCTOSPI_HLCR_LM_Msk
21193#define OCTOSPI_HLCR_WZL_Pos (1U)
21194#define OCTOSPI_HLCR_WZL_Msk (0x1UL << OCTOSPI_HLCR_WZL_Pos)
21195#define OCTOSPI_HLCR_WZL OCTOSPI_HLCR_WZL_Msk
21196#define OCTOSPI_HLCR_TACC_Pos (8U)
21197#define OCTOSPI_HLCR_TACC_Msk (0xFFUL << OCTOSPI_HLCR_TACC_Pos)
21198#define OCTOSPI_HLCR_TACC OCTOSPI_HLCR_TACC_Msk
21199#define OCTOSPI_HLCR_TRWR_Pos (16U)
21200#define OCTOSPI_HLCR_TRWR_Msk (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)
21201#define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk
21203/**************** Bit definition for OCTOSPI_VER register *******************/
21204#define OCTOSPI_VER_VER_Pos (0U)
21205#define OCTOSPI_VER_VER_Msk (0xFFUL << OCTOSPI_VER_VER_Pos)
21206#define OCTOSPI_VER_VER OCTOSPI_VER_VER_Msk
21208/***************** Bit definition for OCTOSPI_ID register *******************/
21209#define OCTOSPI_ID_ID_Pos (0U)
21210#define OCTOSPI_ID_ID_Msk (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)
21211#define OCTOSPI_ID_ID OCTOSPI_ID_ID_Msk
21213/**************** Bit definition for OCTOSPI_MID register *******************/
21214#define OCTOSPI_MID_MID_Pos (0U)
21215#define OCTOSPI_MID_MID_Msk (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)
21216#define OCTOSPI_MID_MID OCTOSPI_MID_MID_Msk
21218/******************************************************************************/
21219/* */
21220/* OCTOSPIM */
21221/* */
21222/******************************************************************************/
21223
21224/*************** Bit definition for OCTOSPIM_CR register ********************/
21225#define OCTOSPIM_CR_MUXEN_Pos (0U)
21226#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos)
21227#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk
21228#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U)
21229#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)
21230#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk
21232/*************** Bit definition for OCTOSPIM_PCR register *******************/
21233#define OCTOSPIM_PCR_CLKEN_Pos (0U)
21234#define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)
21235#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk
21236#define OCTOSPIM_PCR_CLKSRC_Pos (1U)
21237#define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)
21238#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk
21239#define OCTOSPIM_PCR_DQSEN_Pos (4U)
21240#define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)
21241#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk
21242#define OCTOSPIM_PCR_DQSSRC_Pos (5U)
21243#define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)
21244#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk
21245#define OCTOSPIM_PCR_NCSEN_Pos (8U)
21246#define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)
21247#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk
21248#define OCTOSPIM_PCR_NCSSRC_Pos (9U)
21249#define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)
21250#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk
21251#define OCTOSPIM_PCR_IOLEN_Pos (16U)
21252#define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)
21253#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk
21254#define OCTOSPIM_PCR_IOLSRC_Pos (17U)
21255#define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)
21256#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk
21257#define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)
21258#define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)
21259#define OCTOSPIM_PCR_IOHEN_Pos (24U)
21260#define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)
21261#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk
21262#define OCTOSPIM_PCR_IOHSRC_Pos (25U)
21263#define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)
21264#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk
21265#define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)
21266#define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)
21267/******************************************************************************/
21268/* */
21269/* Analog Comparators (COMP) */
21270/* */
21271/******************************************************************************/
21272
21273/******************* Bit definition for COMP_SR register ********************/
21274#define COMP_SR_C1VAL_Pos (0U)
21275#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos)
21276#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
21277#define COMP_SR_C2VAL_Pos (1U)
21278#define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos)
21279#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
21280#define COMP_SR_C1IF_Pos (16U)
21281#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos)
21282#define COMP_SR_C1IF COMP_SR_C1IF_Msk
21283#define COMP_SR_C2IF_Pos (17U)
21284#define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos)
21285#define COMP_SR_C2IF COMP_SR_C2IF_Msk
21286/******************* Bit definition for COMP_ICFR register ********************/
21287#define COMP_ICFR_C1IF_Pos (16U)
21288#define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos)
21289#define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
21290#define COMP_ICFR_C2IF_Pos (17U)
21291#define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos)
21292#define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
21293/******************* Bit definition for COMP_OR register ********************/
21294#define COMP_OR_AFOPA6_Pos (0U)
21295#define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos)
21296#define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
21297#define COMP_OR_AFOPA8_Pos (1U)
21298#define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos)
21299#define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
21300#define COMP_OR_AFOPB12_Pos (2U)
21301#define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos)
21302#define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
21303#define COMP_OR_AFOPE6_Pos (3U)
21304#define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos)
21305#define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
21306#define COMP_OR_AFOPE15_Pos (4U)
21307#define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos)
21308#define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
21309#define COMP_OR_AFOPG2_Pos (5U)
21310#define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos)
21311#define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
21312#define COMP_OR_AFOPG3_Pos (6U)
21313#define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos)
21314#define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
21315#define COMP_OR_AFOPG4_Pos (7U)
21316#define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos)
21317#define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
21318#define COMP_OR_AFOPI1_Pos (8U)
21319#define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos)
21320#define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
21321#define COMP_OR_AFOPI4_Pos (9U)
21322#define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos)
21323#define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
21324#define COMP_OR_AFOPK2_Pos (10U)
21325#define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos)
21326#define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
21327
21329#define COMP_CFGRx_EN_Pos (0U)
21330#define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos)
21331#define COMP_CFGRx_EN COMP_CFGRx_EN_Msk
21332#define COMP_CFGRx_BRGEN_Pos (1U)
21333#define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos)
21334#define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk
21335#define COMP_CFGRx_SCALEN_Pos (2U)
21336#define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos)
21337#define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk
21338#define COMP_CFGRx_POLARITY_Pos (3U)
21339#define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos)
21340#define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk
21341#define COMP_CFGRx_WINMODE_Pos (4U)
21342#define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos)
21343#define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk
21344#define COMP_CFGRx_ITEN_Pos (6U)
21345#define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos)
21346#define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk
21347#define COMP_CFGRx_HYST_Pos (8U)
21348#define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos)
21349#define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk
21350#define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos)
21351#define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos)
21352#define COMP_CFGRx_PWRMODE_Pos (12U)
21353#define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos)
21354#define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk
21355#define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos)
21356#define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos)
21357#define COMP_CFGRx_INMSEL_Pos (16U)
21358#define COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos)
21359#define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk
21360#define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos)
21361#define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos)
21362#define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos)
21363#define COMP_CFGRx_INPSEL_Pos (20U)
21364#define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos)
21365#define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk
21366#define COMP_CFGRx_BLANKING_Pos (24U)
21367#define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos)
21368#define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk
21369#define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos)
21370#define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos)
21371#define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos)
21372#define COMP_CFGRx_LOCK_Pos (31U)
21373#define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos)
21374#define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk
21377/******************************************************************************/
21378/* */
21379/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
21380/* */
21381/******************************************************************************/
21382/****************** Bit definition for USART_CR1 register *******************/
21383#define USART_CR1_UE_Pos (0U)
21384#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
21385#define USART_CR1_UE USART_CR1_UE_Msk
21386#define USART_CR1_UESM_Pos (1U)
21387#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
21388#define USART_CR1_UESM USART_CR1_UESM_Msk
21389#define USART_CR1_RE_Pos (2U)
21390#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
21391#define USART_CR1_RE USART_CR1_RE_Msk
21392#define USART_CR1_TE_Pos (3U)
21393#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
21394#define USART_CR1_TE USART_CR1_TE_Msk
21395#define USART_CR1_IDLEIE_Pos (4U)
21396#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
21397#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
21398#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
21399#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos)
21400#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk
21401#define USART_CR1_TCIE_Pos (6U)
21402#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
21403#define USART_CR1_TCIE USART_CR1_TCIE_Msk
21404#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
21405#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)
21406#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk
21407#define USART_CR1_PEIE_Pos (8U)
21408#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
21409#define USART_CR1_PEIE USART_CR1_PEIE_Msk
21410#define USART_CR1_PS_Pos (9U)
21411#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
21412#define USART_CR1_PS USART_CR1_PS_Msk
21413#define USART_CR1_PCE_Pos (10U)
21414#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
21415#define USART_CR1_PCE USART_CR1_PCE_Msk
21416#define USART_CR1_WAKE_Pos (11U)
21417#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
21418#define USART_CR1_WAKE USART_CR1_WAKE_Msk
21419#define USART_CR1_M_Pos (12U)
21420#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
21421#define USART_CR1_M USART_CR1_M_Msk
21422#define USART_CR1_M0_Pos (12U)
21423#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
21424#define USART_CR1_M0 USART_CR1_M0_Msk
21425#define USART_CR1_MME_Pos (13U)
21426#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
21427#define USART_CR1_MME USART_CR1_MME_Msk
21428#define USART_CR1_CMIE_Pos (14U)
21429#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
21430#define USART_CR1_CMIE USART_CR1_CMIE_Msk
21431#define USART_CR1_OVER8_Pos (15U)
21432#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
21433#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
21434#define USART_CR1_DEDT_Pos (16U)
21435#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
21436#define USART_CR1_DEDT USART_CR1_DEDT_Msk
21437#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
21438#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
21439#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
21440#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
21441#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
21442#define USART_CR1_DEAT_Pos (21U)
21443#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
21444#define USART_CR1_DEAT USART_CR1_DEAT_Msk
21445#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
21446#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
21447#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
21448#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
21449#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
21450#define USART_CR1_RTOIE_Pos (26U)
21451#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
21452#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
21453#define USART_CR1_EOBIE_Pos (27U)
21454#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
21455#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
21456#define USART_CR1_M1_Pos (28U)
21457#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
21458#define USART_CR1_M1 USART_CR1_M1_Msk
21459#define USART_CR1_FIFOEN_Pos (29U)
21460#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos)
21461#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk
21462#define USART_CR1_TXFEIE_Pos (30U)
21463#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos)
21464#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk
21465#define USART_CR1_RXFFIE_Pos (31U)
21466#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos)
21467#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk
21469/* Legacy define */
21470#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
21471#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
21472
21473/****************** Bit definition for USART_CR2 register *******************/
21474#define USART_CR2_SLVEN_Pos (0U)
21475#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos)
21476#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk
21477#define USART_CR2_DIS_NSS_Pos (3U)
21478#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos)
21479#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk
21480#define USART_CR2_ADDM7_Pos (4U)
21481#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
21482#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
21483#define USART_CR2_LBDL_Pos (5U)
21484#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
21485#define USART_CR2_LBDL USART_CR2_LBDL_Msk
21486#define USART_CR2_LBDIE_Pos (6U)
21487#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
21488#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
21489#define USART_CR2_LBCL_Pos (8U)
21490#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
21491#define USART_CR2_LBCL USART_CR2_LBCL_Msk
21492#define USART_CR2_CPHA_Pos (9U)
21493#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
21494#define USART_CR2_CPHA USART_CR2_CPHA_Msk
21495#define USART_CR2_CPOL_Pos (10U)
21496#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
21497#define USART_CR2_CPOL USART_CR2_CPOL_Msk
21498#define USART_CR2_CLKEN_Pos (11U)
21499#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
21500#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
21501#define USART_CR2_STOP_Pos (12U)
21502#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
21503#define USART_CR2_STOP USART_CR2_STOP_Msk
21504#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
21505#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
21506#define USART_CR2_LINEN_Pos (14U)
21507#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
21508#define USART_CR2_LINEN USART_CR2_LINEN_Msk
21509#define USART_CR2_SWAP_Pos (15U)
21510#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
21511#define USART_CR2_SWAP USART_CR2_SWAP_Msk
21512#define USART_CR2_RXINV_Pos (16U)
21513#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
21514#define USART_CR2_RXINV USART_CR2_RXINV_Msk
21515#define USART_CR2_TXINV_Pos (17U)
21516#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
21517#define USART_CR2_TXINV USART_CR2_TXINV_Msk
21518#define USART_CR2_DATAINV_Pos (18U)
21519#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
21520#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
21521#define USART_CR2_MSBFIRST_Pos (19U)
21522#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
21523#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
21524#define USART_CR2_ABREN_Pos (20U)
21525#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
21526#define USART_CR2_ABREN USART_CR2_ABREN_Msk
21527#define USART_CR2_ABRMODE_Pos (21U)
21528#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
21529#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
21530#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
21531#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
21532#define USART_CR2_RTOEN_Pos (23U)
21533#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
21534#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
21535#define USART_CR2_ADD_Pos (24U)
21536#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
21537#define USART_CR2_ADD USART_CR2_ADD_Msk
21539/****************** Bit definition for USART_CR3 register *******************/
21540#define USART_CR3_EIE_Pos (0U)
21541#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
21542#define USART_CR3_EIE USART_CR3_EIE_Msk
21543#define USART_CR3_IREN_Pos (1U)
21544#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
21545#define USART_CR3_IREN USART_CR3_IREN_Msk
21546#define USART_CR3_IRLP_Pos (2U)
21547#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
21548#define USART_CR3_IRLP USART_CR3_IRLP_Msk
21549#define USART_CR3_HDSEL_Pos (3U)
21550#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
21551#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
21552#define USART_CR3_NACK_Pos (4U)
21553#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
21554#define USART_CR3_NACK USART_CR3_NACK_Msk
21555#define USART_CR3_SCEN_Pos (5U)
21556#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
21557#define USART_CR3_SCEN USART_CR3_SCEN_Msk
21558#define USART_CR3_DMAR_Pos (6U)
21559#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
21560#define USART_CR3_DMAR USART_CR3_DMAR_Msk
21561#define USART_CR3_DMAT_Pos (7U)
21562#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
21563#define USART_CR3_DMAT USART_CR3_DMAT_Msk
21564#define USART_CR3_RTSE_Pos (8U)
21565#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
21566#define USART_CR3_RTSE USART_CR3_RTSE_Msk
21567#define USART_CR3_CTSE_Pos (9U)
21568#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
21569#define USART_CR3_CTSE USART_CR3_CTSE_Msk
21570#define USART_CR3_CTSIE_Pos (10U)
21571#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
21572#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
21573#define USART_CR3_ONEBIT_Pos (11U)
21574#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
21575#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
21576#define USART_CR3_OVRDIS_Pos (12U)
21577#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
21578#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
21579#define USART_CR3_DDRE_Pos (13U)
21580#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
21581#define USART_CR3_DDRE USART_CR3_DDRE_Msk
21582#define USART_CR3_DEM_Pos (14U)
21583#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
21584#define USART_CR3_DEM USART_CR3_DEM_Msk
21585#define USART_CR3_DEP_Pos (15U)
21586#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
21587#define USART_CR3_DEP USART_CR3_DEP_Msk
21588#define USART_CR3_SCARCNT_Pos (17U)
21589#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
21590#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
21591#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
21592#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
21593#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
21594#define USART_CR3_WUS_Pos (20U)
21595#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
21596#define USART_CR3_WUS USART_CR3_WUS_Msk
21597#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
21598#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
21599#define USART_CR3_WUFIE_Pos (22U)
21600#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
21601#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
21602#define USART_CR3_TXFTIE_Pos (23U)
21603#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos)
21604#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk
21605#define USART_CR3_TCBGTIE_Pos (24U)
21606#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)
21607#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk
21608#define USART_CR3_RXFTCFG_Pos (25U)
21609#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos)
21610#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk
21611#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos)
21612#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos)
21613#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos)
21614#define USART_CR3_RXFTIE_Pos (28U)
21615#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos)
21616#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk
21617#define USART_CR3_TXFTCFG_Pos (29U)
21618#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos)
21619#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk
21620#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos)
21621#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos)
21622#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos)
21624/****************** Bit definition for USART_BRR register *******************/
21625#define USART_BRR_DIV_FRACTION_Pos (0U)
21626#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
21627#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
21628#define USART_BRR_DIV_MANTISSA_Pos (4U)
21629#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
21630#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
21632/****************** Bit definition for USART_GTPR register ******************/
21633#define USART_GTPR_PSC_Pos (0U)
21634#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
21635#define USART_GTPR_PSC USART_GTPR_PSC_Msk
21636#define USART_GTPR_GT_Pos (8U)
21637#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
21638#define USART_GTPR_GT USART_GTPR_GT_Msk
21640/******************* Bit definition for USART_RTOR register *****************/
21641#define USART_RTOR_RTO_Pos (0U)
21642#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
21643#define USART_RTOR_RTO USART_RTOR_RTO_Msk
21644#define USART_RTOR_BLEN_Pos (24U)
21645#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
21646#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
21648/******************* Bit definition for USART_RQR register ******************/
21649#define USART_RQR_ABRRQ_Pos (0U)
21650#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
21651#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
21652#define USART_RQR_SBKRQ_Pos (1U)
21653#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
21654#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
21655#define USART_RQR_MMRQ_Pos (2U)
21656#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
21657#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
21658#define USART_RQR_RXFRQ_Pos (3U)
21659#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
21660#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
21661#define USART_RQR_TXFRQ_Pos (4U)
21662#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
21663#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
21665/******************* Bit definition for USART_ISR register ******************/
21666#define USART_ISR_PE_Pos (0U)
21667#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
21668#define USART_ISR_PE USART_ISR_PE_Msk
21669#define USART_ISR_FE_Pos (1U)
21670#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
21671#define USART_ISR_FE USART_ISR_FE_Msk
21672#define USART_ISR_NE_Pos (2U)
21673#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
21674#define USART_ISR_NE USART_ISR_NE_Msk
21675#define USART_ISR_ORE_Pos (3U)
21676#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
21677#define USART_ISR_ORE USART_ISR_ORE_Msk
21678#define USART_ISR_IDLE_Pos (4U)
21679#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
21680#define USART_ISR_IDLE USART_ISR_IDLE_Msk
21681#define USART_ISR_RXNE_RXFNE_Pos (5U)
21682#define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos)
21683#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk
21684#define USART_ISR_TC_Pos (6U)
21685#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
21686#define USART_ISR_TC USART_ISR_TC_Msk
21687#define USART_ISR_TXE_TXFNF_Pos (7U)
21688#define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos)
21689#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk
21690#define USART_ISR_LBDF_Pos (8U)
21691#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
21692#define USART_ISR_LBDF USART_ISR_LBDF_Msk
21693#define USART_ISR_CTSIF_Pos (9U)
21694#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
21695#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
21696#define USART_ISR_CTS_Pos (10U)
21697#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
21698#define USART_ISR_CTS USART_ISR_CTS_Msk
21699#define USART_ISR_RTOF_Pos (11U)
21700#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
21701#define USART_ISR_RTOF USART_ISR_RTOF_Msk
21702#define USART_ISR_EOBF_Pos (12U)
21703#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
21704#define USART_ISR_EOBF USART_ISR_EOBF_Msk
21705#define USART_ISR_UDR_Pos (13U)
21706#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos)
21707#define USART_ISR_UDR USART_ISR_UDR_Msk
21708#define USART_ISR_ABRE_Pos (14U)
21709#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
21710#define USART_ISR_ABRE USART_ISR_ABRE_Msk
21711#define USART_ISR_ABRF_Pos (15U)
21712#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
21713#define USART_ISR_ABRF USART_ISR_ABRF_Msk
21714#define USART_ISR_BUSY_Pos (16U)
21715#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
21716#define USART_ISR_BUSY USART_ISR_BUSY_Msk
21717#define USART_ISR_CMF_Pos (17U)
21718#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
21719#define USART_ISR_CMF USART_ISR_CMF_Msk
21720#define USART_ISR_SBKF_Pos (18U)
21721#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
21722#define USART_ISR_SBKF USART_ISR_SBKF_Msk
21723#define USART_ISR_RWU_Pos (19U)
21724#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
21725#define USART_ISR_RWU USART_ISR_RWU_Msk
21726#define USART_ISR_WUF_Pos (20U)
21727#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
21728#define USART_ISR_WUF USART_ISR_WUF_Msk
21729#define USART_ISR_TEACK_Pos (21U)
21730#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
21731#define USART_ISR_TEACK USART_ISR_TEACK_Msk
21732#define USART_ISR_REACK_Pos (22U)
21733#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
21734#define USART_ISR_REACK USART_ISR_REACK_Msk
21735#define USART_ISR_TXFE_Pos (23U)
21736#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos)
21737#define USART_ISR_TXFE USART_ISR_TXFE_Msk
21738#define USART_ISR_RXFF_Pos (24U)
21739#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos)
21740#define USART_ISR_RXFF USART_ISR_RXFF_Msk
21741#define USART_ISR_TCBGT_Pos (25U)
21742#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)
21743#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk
21744#define USART_ISR_RXFT_Pos (26U)
21745#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos)
21746#define USART_ISR_RXFT USART_ISR_RXFT_Msk
21747#define USART_ISR_TXFT_Pos (27U)
21748#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos)
21749#define USART_ISR_TXFT USART_ISR_TXFT_Msk
21751/******************* Bit definition for USART_ICR register ******************/
21752#define USART_ICR_PECF_Pos (0U)
21753#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
21754#define USART_ICR_PECF USART_ICR_PECF_Msk
21755#define USART_ICR_FECF_Pos (1U)
21756#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
21757#define USART_ICR_FECF USART_ICR_FECF_Msk
21758#define USART_ICR_NECF_Pos (2U)
21759#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)
21760#define USART_ICR_NECF USART_ICR_NECF_Msk
21761#define USART_ICR_ORECF_Pos (3U)
21762#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
21763#define USART_ICR_ORECF USART_ICR_ORECF_Msk
21764#define USART_ICR_IDLECF_Pos (4U)
21765#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
21766#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
21767#define USART_ICR_TXFECF_Pos (5U)
21768#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos)
21769#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk
21770#define USART_ICR_TCCF_Pos (6U)
21771#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
21772#define USART_ICR_TCCF USART_ICR_TCCF_Msk
21773#define USART_ICR_TCBGTCF_Pos (7U)
21774#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)
21775#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk
21776#define USART_ICR_LBDCF_Pos (8U)
21777#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
21778#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
21779#define USART_ICR_CTSCF_Pos (9U)
21780#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
21781#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
21782#define USART_ICR_RTOCF_Pos (11U)
21783#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
21784#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
21785#define USART_ICR_EOBCF_Pos (12U)
21786#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
21787#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
21788#define USART_ICR_UDRCF_Pos (13U)
21789#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos)
21790#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk
21791#define USART_ICR_CMCF_Pos (17U)
21792#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
21793#define USART_ICR_CMCF USART_ICR_CMCF_Msk
21794#define USART_ICR_WUCF_Pos (20U)
21795#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
21796#define USART_ICR_WUCF USART_ICR_WUCF_Msk
21798/******************* Bit definition for USART_RDR register ******************/
21799#define USART_RDR_RDR_Pos (0U)
21800#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
21801#define USART_RDR_RDR USART_RDR_RDR_Msk
21803/******************* Bit definition for USART_TDR register ******************/
21804#define USART_TDR_TDR_Pos (0U)
21805#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
21806#define USART_TDR_TDR USART_TDR_TDR_Msk
21808/******************* Bit definition for USART_PRESC register ******************/
21809#define USART_PRESC_PRESCALER_Pos (0U)
21810#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos)
21811#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk
21812#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos)
21813#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos)
21814#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos)
21815#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos)
21817/******************************************************************************/
21818/* */
21819/* Single Wire Protocol Master Interface (SWPMI) */
21820/* */
21821/******************************************************************************/
21822
21823/******************* Bit definition for SWPMI_CR register ********************/
21824#define SWPMI_CR_RXDMA_Pos (0U)
21825#define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos)
21826#define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk
21827#define SWPMI_CR_TXDMA_Pos (1U)
21828#define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos)
21829#define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk
21830#define SWPMI_CR_RXMODE_Pos (2U)
21831#define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos)
21832#define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk
21833#define SWPMI_CR_TXMODE_Pos (3U)
21834#define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos)
21835#define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk
21836#define SWPMI_CR_LPBK_Pos (4U)
21837#define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos)
21838#define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk
21839#define SWPMI_CR_SWPACT_Pos (5U)
21840#define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos)
21841#define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk
21842#define SWPMI_CR_DEACT_Pos (10U)
21843#define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos)
21844#define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk
21845#define SWPMI_CR_SWPEN_Pos (11U)
21846#define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos)
21847#define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk
21849/******************* Bit definition for SWPMI_BRR register ********************/
21850#define SWPMI_BRR_BR_Pos (0U)
21851#define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos)
21852#define SWPMI_BRR_BR SWPMI_BRR_BR_Msk
21854/******************* Bit definition for SWPMI_ISR register ********************/
21855#define SWPMI_ISR_RXBFF_Pos (0U)
21856#define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos)
21857#define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk
21858#define SWPMI_ISR_TXBEF_Pos (1U)
21859#define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos)
21860#define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk
21861#define SWPMI_ISR_RXBERF_Pos (2U)
21862#define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos)
21863#define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk
21864#define SWPMI_ISR_RXOVRF_Pos (3U)
21865#define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos)
21866#define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk
21867#define SWPMI_ISR_TXUNRF_Pos (4U)
21868#define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos)
21869#define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk
21870#define SWPMI_ISR_RXNE_Pos (5U)
21871#define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos)
21872#define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk
21873#define SWPMI_ISR_TXE_Pos (6U)
21874#define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos)
21875#define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk
21876#define SWPMI_ISR_TCF_Pos (7U)
21877#define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos)
21878#define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk
21879#define SWPMI_ISR_SRF_Pos (8U)
21880#define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos)
21881#define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk
21882#define SWPMI_ISR_SUSP_Pos (9U)
21883#define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos)
21884#define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk
21885#define SWPMI_ISR_DEACTF_Pos (10U)
21886#define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos)
21887#define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk
21888#define SWPMI_ISR_RDYF_Pos (11U)
21889#define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos)
21890#define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk
21892/******************* Bit definition for SWPMI_ICR register ********************/
21893#define SWPMI_ICR_CRXBFF_Pos (0U)
21894#define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos)
21895#define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk
21896#define SWPMI_ICR_CTXBEF_Pos (1U)
21897#define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos)
21898#define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk
21899#define SWPMI_ICR_CRXBERF_Pos (2U)
21900#define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos)
21901#define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk
21902#define SWPMI_ICR_CRXOVRF_Pos (3U)
21903#define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos)
21904#define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk
21905#define SWPMI_ICR_CTXUNRF_Pos (4U)
21906#define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos)
21907#define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk
21908#define SWPMI_ICR_CTCF_Pos (7U)
21909#define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos)
21910#define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk
21911#define SWPMI_ICR_CSRF_Pos (8U)
21912#define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos)
21913#define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk
21914#define SWPMI_ICR_CRDYF_Pos (11U)
21915#define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos)
21916#define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk
21918/******************* Bit definition for SWPMI_IER register ********************/
21919#define SWPMI_IER_RXBFIE_Pos (0U)
21920#define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos)
21921#define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk
21922#define SWPMI_IER_TXBEIE_Pos (1U)
21923#define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos)
21924#define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk
21925#define SWPMI_IER_RXBERIE_Pos (2U)
21926#define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos)
21927#define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk
21928#define SWPMI_IER_RXOVRIE_Pos (3U)
21929#define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos)
21930#define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk
21931#define SWPMI_IER_TXUNRIE_Pos (4U)
21932#define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos)
21933#define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk
21934#define SWPMI_IER_RIE_Pos (5U)
21935#define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos)
21936#define SWPMI_IER_RIE SWPMI_IER_RIE_Msk
21937#define SWPMI_IER_TIE_Pos (6U)
21938#define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos)
21939#define SWPMI_IER_TIE SWPMI_IER_TIE_Msk
21940#define SWPMI_IER_TCIE_Pos (7U)
21941#define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos)
21942#define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk
21943#define SWPMI_IER_SRIE_Pos (8U)
21944#define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos)
21945#define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk
21946#define SWPMI_IER_RDYIE_Pos (11U)
21947#define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos)
21948#define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk
21950/******************* Bit definition for SWPMI_RFL register ********************/
21951#define SWPMI_RFL_RFL_Pos (0U)
21952#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos)
21953#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk
21954#define SWPMI_RFL_RFL_0_1 (0x00000003U)
21956/******************* Bit definition for SWPMI_TDR register ********************/
21957#define SWPMI_TDR_TD_Pos (0U)
21958#define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)
21959#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk
21961/******************* Bit definition for SWPMI_RDR register ********************/
21962#define SWPMI_RDR_RD_Pos (0U)
21963#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)
21964#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk
21967/******************* Bit definition for SWPMI_OR register ********************/
21968#define SWPMI_OR_TBYP_Pos (0U)
21969#define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos)
21970#define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk
21971#define SWPMI_OR_CLASS_Pos (1U)
21972#define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos)
21973#define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk
21975/******************************************************************************/
21976/* */
21977/* Window WATCHDOG */
21978/* */
21979/******************************************************************************/
21980/******************* Bit definition for WWDG_CR register ********************/
21981#define WWDG_CR_T_Pos (0U)
21982#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
21983#define WWDG_CR_T WWDG_CR_T_Msk
21984#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
21985#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
21986#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
21987#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
21988#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
21989#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
21990#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
21992#define WWDG_CR_WDGA_Pos (7U)
21993#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
21994#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
21996/******************* Bit definition for WWDG_CFR register *******************/
21997#define WWDG_CFR_W_Pos (0U)
21998#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
21999#define WWDG_CFR_W WWDG_CFR_W_Msk
22000#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
22001#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
22002#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
22003#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
22004#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
22005#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
22006#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
22008#define WWDG_CFR_EWI_Pos (9U)
22009#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
22010#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
22012#define WWDG_CFR_WDGTB_Pos (11U)
22013#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos)
22014#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
22015#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
22016#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
22017#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos)
22019/******************* Bit definition for WWDG_SR register ********************/
22020#define WWDG_SR_EWIF_Pos (0U)
22021#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
22022#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
22025/******************************************************************************/
22026/* */
22027/* DBG */
22028/* */
22029/******************************************************************************/
22030/********************************* DEVICE ID ********************************/
22031#define STM32H7_DEV_ID 0x483UL
22032
22033/******************** Bit definition for DBGMCU_IDCODE register *************/
22034#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
22035#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
22036#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
22037#define DBGMCU_IDCODE_REV_ID_Pos (16U)
22038#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
22039#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
22040
22041/******************** Bit definition for DBGMCU_CR register *****************/
22042#define DBGMCU_CR_DBG_SLEEPD1_Pos (0U)
22043#define DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos)
22044#define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk
22045#define DBGMCU_CR_DBG_STOPD1_Pos (1U)
22046#define DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)
22047#define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk
22048#define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
22049#define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos)
22050#define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
22051#define DBGMCU_CR_DBG_STOPD3_Pos (7U)
22052#define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)
22053#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
22054#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
22055#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos)
22056#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
22057#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
22058#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos)
22059#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
22060#define DBGMCU_CR_DBG_CKD1EN_Pos (21U)
22061#define DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)
22062#define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk
22063#define DBGMCU_CR_DBG_CKD3EN_Pos (22U)
22064#define DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)
22065#define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk
22066#define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
22067#define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)
22068#define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
22069
22070/******************** Bit definition for APB3FZ1 register ************/
22071#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
22072#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos)
22073#define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
22074/******************** Bit definition for APB1LFZ1 register ************/
22075#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
22076#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos)
22077#define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
22078#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
22079#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos)
22080#define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
22081#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
22082#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos)
22083#define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
22084#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
22085#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos)
22086#define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
22087#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
22088#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos)
22089#define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
22090#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
22091#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos)
22092#define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
22093#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
22094#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos)
22095#define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
22096#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
22097#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos)
22098#define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
22099#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
22100#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos)
22101#define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
22102#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
22103#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos)
22104#define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
22105#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
22106#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos)
22107#define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
22108#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
22109#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos)
22110#define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
22111#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
22112#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos)
22113#define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
22114#define DBGMCU_APB1LFZ1_DBG_I2C5_Pos (25U)
22115#define DBGMCU_APB1LFZ1_DBG_I2C5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C5_Pos)
22116#define DBGMCU_APB1LFZ1_DBG_I2C5 DBGMCU_APB1LFZ1_DBG_I2C5_Msk
22117
22118/******************** Bit definition for APB1HFZ1 register ************/
22119#define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U)
22120#define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos)
22121#define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk
22122#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U)
22123#define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos)
22124#define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk
22125/******************** Bit definition for APB2FZ1 register ************/
22126#define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
22127#define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos)
22128#define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
22129#define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
22130#define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos)
22131#define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
22132#define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
22133#define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos)
22134#define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
22135#define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
22136#define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos)
22137#define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
22138#define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
22139#define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos)
22140#define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
22141/******************** Bit definition for APB4FZ1 register ************/
22142#define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
22143#define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos)
22144#define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
22145#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
22146#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos)
22147#define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
22148#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
22149#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos)
22150#define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
22151#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U)
22152#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos)
22153#define DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
22154#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U)
22155#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos)
22156#define DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
22157#define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
22158#define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos)
22159#define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
22160#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
22161#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos)
22162#define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
22163/******************** Bit definition for DBGMCU_PIDR4 register ************/
22164#define DBGMCU_PIDR4_JEP106CON_Pos (0U)
22165#define DBGMCU_PIDR4_JEP106CON_Msk (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos)
22166#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_Msk
22167#define DBGMCU_PIDR4_4KCOUNT_Pos (4U)
22168#define DBGMCU_PIDR4_4KCOUNT_Msk (0xFUL << DBGMCU_PIDR4_4KCOUNT_Pos)
22169#define DBGMCU_PIDR4_4KCOUNT DBGMCU_PIDR4_4KCOUNT_Msk
22170/******************** Bit definition for DBGMCU_PIDR0 register ************/
22171#define DBGMCU_PIDR0_PARTNUM_Pos (0U)
22172#define DBGMCU_PIDR0_PARTNUM_Msk (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos)
22173#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_Msk
22174/******************** Bit definition for DBGMCU_PIDR1 register ************/
22175#define DBGMCU_PIDR1_PARTNUM_Pos (0U)
22176#define DBGMCU_PIDR1_PARTNUM_Msk (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos)
22177#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_Msk
22178#define DBGMCU_PIDR1_JEP106ID_Pos (4U)
22179#define DBGMCU_PIDR1_JEP106ID_Msk (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos)
22180#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_Msk
22181/******************** Bit definition for DBGMCU_PIDR2 register ************/
22182#define DBGMCU_PIDR2_JEP106ID_Pos (0U)
22183#define DBGMCU_PIDR2_JEP106ID_Msk (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos)
22184#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_Msk
22185#define DBGMCU_PIDR2_JEDEC_Pos (3U)
22186#define DBGMCU_PIDR2_JEDEC_Msk (0x1UL << DBGMCU_PIDR2_JEDEC_Pos)
22187#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_Msk
22188#define DBGMCU_PIDR2_REVISION_Pos (4U)
22189#define DBGMCU_PIDR2_REVISION_Msk (0xFUL << DBGMCU_PIDR2_REVISION_Pos)
22190#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_Msk
22191/******************** Bit definition for DBGMCU_PIDR3 register ************/
22192#define DBGMCU_PIDR3_CMOD_Pos (0U)
22193#define DBGMCU_PIDR3_CMOD_Msk (0xFUL << DBGMCU_PIDR3_CMOD_Pos)
22194#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_Msk
22195#define DBGMCU_PIDR3_REVAND_Pos (4U)
22196#define DBGMCU_PIDR3_REVAND_Msk (0xFUL << DBGMCU_PIDR3_REVAND_Pos)
22197#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_Msk
22198/******************** Bit definition for DBGMCU_CIDR0 register ************/
22199#define DBGMCU_CIR0_PREAMBLE_Pos (0U)
22200#define DBGMCU_CIR0_PREAMBLE_Msk (0xFFUL << DBGMCU_CIR0_PREAMBLE_Pos)
22201#define DBGMCU_CIR0_PREAMBLE DBGMCU_CIR0_PREAMBLE_Msk
22202/******************** Bit definition for DBGMCU_CIDR1 register ************/
22203#define DBGMCU_CIR1_PREAMBLE_Pos (0U)
22204#define DBGMCU_CIR1_PREAMBLE_Msk (0xFUL << DBGMCU_CIR1_PREAMBLE_Pos)
22205#define DBGMCU_CIR1_PREAMBLE DBGMCU_CIR1_PREAMBLE_Msk
22206#define DBGMCU_CIR1_CLASS_Pos (4U)
22207#define DBGMCU_CIR1_CLASS_Msk (0xFUL << DBGMCU_CIR1_CLASS_Pos)
22208#define DBGMCU_CIR1_CLASS DBGMCU_CIR1_CLASS_Msk
22209/******************** Bit definition for DBGMCU_CIDR2 register ************/
22210#define DBGMCU_CIR2_PREAMBLE_Pos (0U)
22211#define DBGMCU_CIR2_PREAMBLE_Msk (0xFFUL << DBGMCU_CIR2_PREAMBLE_Pos)
22212#define DBGMCU_CIR2_PREAMBLE DBGMCU_CIR2_PREAMBLE_Msk
22213/******************** Bit definition for DBGMCU_CIDR3 register ************/
22214#define DBGMCU_CIR3_PREAMBLE_Pos (0U)
22215#define DBGMCU_CIR3_PREAMBLE_Msk (0xFFUL << DBGMCU_CIR3_PREAMBLE_Pos)
22216#define DBGMCU_CIR3_PREAMBLE DBGMCU_CIR3_PREAMBLE_Msk
22217/******************************************************************************/
22218/* */
22219/* RAM ECC monitoring */
22220/* */
22221/******************************************************************************/
22222/****************** Bit definition for RAMECC_IER register ******************/
22223#define RAMECC_IER_GECCDEBWIE_Pos (3U)
22224#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)
22225#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk
22226#define RAMECC_IER_GECCDEIE_Pos (2U)
22227#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos)
22228#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk
22229#define RAMECC_IER_GECCSEIE_Pos (1U)
22230#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos)
22231#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk
22232#define RAMECC_IER_GIE_Pos (0U)
22233#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos)
22234#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk
22236/******************* Bit definition for RAMECC_CR register ******************/
22237#define RAMECC_CR_ECCELEN_Pos (5U)
22238#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos)
22239#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk
22240#define RAMECC_CR_ECCDEBWIE_Pos (4U)
22241#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)
22242#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk
22243#define RAMECC_CR_ECCDEIE_Pos (3U)
22244#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos)
22245#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk
22246#define RAMECC_CR_ECCSEIE_Pos (2U)
22247#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos)
22248#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk
22250/******************* Bit definition for RAMECC_SR register ******************/
22251#define RAMECC_SR_DEBWDF_Pos (2U)
22252#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos)
22253#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk
22254#define RAMECC_SR_DEDF_Pos (1U)
22255#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos)
22256#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk
22257#define RAMECC_SR_SEDCF_Pos (0U)
22258#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos)
22259#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk
22261/****************** Bit definition for RAMECC_FAR register ******************/
22262#define RAMECC_FAR_FADD_Pos (0U)
22263#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)
22264#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk
22266/****************** Bit definition for RAMECC_FDRL register *****************/
22267#define RAMECC_FAR_FDATAL_Pos (0U)
22268#define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)
22269#define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk
22271/****************** Bit definition for RAMECC_FDRH register *****************/
22272#define RAMECC_FAR_FDATAH_Pos (0U)
22273#define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)
22274#define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
22275
22276/***************** Bit definition for RAMECC_FECR register ******************/
22277#define RAMECC_FECR_FEC_Pos (0U)
22278#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)
22279#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk
22281/******************************************************************************/
22282/* */
22283/* MDIOS */
22284/* */
22285/******************************************************************************/
22286/******************** Bit definition for MDIOS_CR register *******************/
22287#define MDIOS_CR_EN_Pos (0U)
22288#define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos)
22289#define MDIOS_CR_EN MDIOS_CR_EN_Msk
22290#define MDIOS_CR_WRIE_Pos (1U)
22291#define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos)
22292#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk
22293#define MDIOS_CR_RDIE_Pos (2U)
22294#define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos)
22295#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk
22296#define MDIOS_CR_EIE_Pos (3U)
22297#define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos)
22298#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk
22299#define MDIOS_CR_DPC_Pos (7U)
22300#define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos)
22301#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk
22302#define MDIOS_CR_PORT_ADDRESS_Pos (8U)
22303#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)
22304#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk
22305#define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)
22306#define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)
22307#define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)
22308#define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)
22309#define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)
22311/******************** Bit definition for MDIOS_SR register *******************/
22312#define MDIOS_SR_PERF_Pos (0U)
22313#define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos)
22314#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk
22315#define MDIOS_SR_SERF_Pos (1U)
22316#define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos)
22317#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk
22318#define MDIOS_SR_TERF_Pos (2U)
22319#define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos)
22320#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk
22322/******************** Bit definition for MDIOS_CLRFR register *******************/
22323#define MDIOS_SR_CPERF_Pos (0U)
22324#define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos)
22325#define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk
22326#define MDIOS_SR_CSERF_Pos (1U)
22327#define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos)
22328#define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk
22329#define MDIOS_SR_CTERF_Pos (2U)
22330#define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos)
22331#define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk
22333/******************************************************************************/
22334/* */
22335/* USB_OTG */
22336/* */
22337/******************************************************************************/
22338/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
22339#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
22340#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
22341#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
22342#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
22343#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
22344#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
22345#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
22346#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
22347#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
22348#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
22349#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
22350#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
22351#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
22352#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
22353#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
22354#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
22355#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
22356#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
22357#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
22358#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
22359#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
22360#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
22361#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
22362#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
22363#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
22364#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
22365#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
22366#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
22367#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
22368#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
22369#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
22370#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
22371#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
22372#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
22373#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
22374#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
22375#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
22376#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
22377#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
22378#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
22379#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
22380#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
22381#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
22382#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
22383#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
22384#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
22385#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
22386#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
22387#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
22388#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
22389#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
22390#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
22391#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
22392#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
22394/******************** Bit definition forUSB_OTG_HCFG register ********************/
22395
22396#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
22397#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
22398#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
22399#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
22400#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
22401#define USB_OTG_HCFG_FSLSS_Pos (2U)
22402#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
22403#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
22405/******************** Bit definition forUSB_OTG_DCFG register ********************/
22406
22407#define USB_OTG_DCFG_DSPD_Pos (0U)
22408#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
22409#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
22410#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
22411#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
22412#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
22413#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
22414#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
22416#define USB_OTG_DCFG_DAD_Pos (4U)
22417#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
22418#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
22419#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
22420#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
22421#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
22422#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
22423#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
22424#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
22425#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
22427#define USB_OTG_DCFG_PFIVL_Pos (11U)
22428#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
22429#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
22430#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
22431#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
22433#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
22434#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
22435#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
22436#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
22437#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
22439/******************** Bit definition forUSB_OTG_PCGCR register ********************/
22440#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
22441#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
22442#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
22443#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
22444#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
22445#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
22446#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
22447#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
22448#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
22450/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
22451#define USB_OTG_GOTGINT_SEDET_Pos (2U)
22452#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
22453#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
22454#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
22455#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
22456#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
22457#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
22458#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
22459#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
22460#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
22461#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
22462#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
22463#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
22464#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
22465#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
22466#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
22467#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
22468#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
22470/******************** Bit definition forUSB_OTG_DCTL register ********************/
22471#define USB_OTG_DCTL_RWUSIG_Pos (0U)
22472#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
22473#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
22474#define USB_OTG_DCTL_SDIS_Pos (1U)
22475#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
22476#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
22477#define USB_OTG_DCTL_GINSTS_Pos (2U)
22478#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
22479#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
22480#define USB_OTG_DCTL_GONSTS_Pos (3U)
22481#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
22482#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
22484#define USB_OTG_DCTL_TCTL_Pos (4U)
22485#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
22486#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
22487#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
22488#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
22489#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
22490#define USB_OTG_DCTL_SGINAK_Pos (7U)
22491#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
22492#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
22493#define USB_OTG_DCTL_CGINAK_Pos (8U)
22494#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
22495#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
22496#define USB_OTG_DCTL_SGONAK_Pos (9U)
22497#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
22498#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
22499#define USB_OTG_DCTL_CGONAK_Pos (10U)
22500#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
22501#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
22502#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
22503#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
22504#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
22506/******************** Bit definition forUSB_OTG_HFIR register ********************/
22507#define USB_OTG_HFIR_FRIVL_Pos (0U)
22508#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
22509#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
22511/******************** Bit definition forUSB_OTG_HFNUM register ********************/
22512#define USB_OTG_HFNUM_FRNUM_Pos (0U)
22513#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
22514#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
22515#define USB_OTG_HFNUM_FTREM_Pos (16U)
22516#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
22517#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
22519/******************** Bit definition forUSB_OTG_DSTS register ********************/
22520#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
22521#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
22522#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
22524#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
22525#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
22526#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
22527#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
22528#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
22529#define USB_OTG_DSTS_EERR_Pos (3U)
22530#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
22531#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
22532#define USB_OTG_DSTS_FNSOF_Pos (8U)
22533#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
22534#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
22536/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
22537#define USB_OTG_GAHBCFG_GINT_Pos (0U)
22538#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
22539#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
22541#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
22542#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
22543#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
22544#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
22545#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
22546#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
22547#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
22548#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
22549#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
22550#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
22551#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
22552#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
22553#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
22554#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
22555#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
22556#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
22557#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
22559/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
22560
22561#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
22562#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
22563#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
22564#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
22565#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
22566#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
22567#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
22568#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
22569#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
22570#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
22571#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
22572#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
22573#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
22574#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
22575#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
22577#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
22578#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
22579#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
22580#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
22581#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
22582#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
22583#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
22584#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
22585#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
22586#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
22587#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
22588#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
22589#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
22590#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
22591#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
22592#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
22593#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
22594#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
22595#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
22596#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
22597#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
22598#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
22599#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
22600#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
22601#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
22602#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
22603#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
22604#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
22605#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
22606#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
22607#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
22608#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
22609#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
22610#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
22611#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
22612#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
22613#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
22614#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
22615#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
22616#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
22617#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
22618#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
22619#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
22620#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
22621#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
22622#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
22624/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
22625#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
22626#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
22627#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
22628#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
22629#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
22630#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
22631#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
22632#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
22633#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
22634#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
22635#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
22636#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
22637#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
22638#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
22639#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
22641#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
22642#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
22643#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
22644#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
22645#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
22646#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
22647#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
22648#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
22649#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
22650#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
22651#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
22652#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
22653#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
22654#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
22656/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
22657#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
22658#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
22659#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
22660#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
22661#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
22662#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
22663#define USB_OTG_DIEPMSK_TOM_Pos (3U)
22664#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
22665#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
22666#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
22667#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
22668#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
22669#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
22670#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
22671#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
22672#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
22673#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
22674#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
22675#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
22676#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
22677#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
22678#define USB_OTG_DIEPMSK_BIM_Pos (9U)
22679#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
22680#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
22682/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
22683#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
22684#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
22685#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
22687#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
22688#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22689#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
22690#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22691#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22692#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22693#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22694#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22695#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22696#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22697#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
22699#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
22700#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22701#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
22702#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22703#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22704#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22705#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22706#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22707#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22708#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22709#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
22711/******************** Bit definition forUSB_OTG_HAINT register ********************/
22712#define USB_OTG_HAINT_HAINT_Pos (0U)
22713#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
22714#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
22716/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
22717#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
22718#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
22719#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
22720#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
22721#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
22722#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
22723#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
22724#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
22725#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
22726#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
22727#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
22728#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
22729#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
22730#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
22731#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
22732#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
22733#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
22734#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
22735#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
22736#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
22737#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
22738#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
22739#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
22740#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
22741#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
22742#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
22743#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
22744#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
22745#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
22746#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
22747#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
22748#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
22749#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
22750#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
22751#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
22752#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
22754/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
22755#define USB_OTG_GINTSTS_CMOD_Pos (0U)
22756#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
22757#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
22758#define USB_OTG_GINTSTS_MMIS_Pos (1U)
22759#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
22760#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
22761#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
22762#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
22763#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
22764#define USB_OTG_GINTSTS_SOF_Pos (3U)
22765#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
22766#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
22767#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
22768#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
22769#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
22770#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
22771#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
22772#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
22773#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
22774#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
22775#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
22776#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
22777#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
22778#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
22779#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
22780#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
22781#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
22782#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
22783#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
22784#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
22785#define USB_OTG_GINTSTS_USBRST_Pos (12U)
22786#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
22787#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
22788#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
22789#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
22790#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
22791#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
22792#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
22793#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
22794#define USB_OTG_GINTSTS_EOPF_Pos (15U)
22795#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
22796#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
22797#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
22798#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
22799#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
22800#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
22801#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
22802#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
22803#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
22804#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
22805#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
22806#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
22807#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
22808#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
22809#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
22810#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
22811#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
22812#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
22813#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
22814#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
22815#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
22816#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
22817#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
22818#define USB_OTG_GINTSTS_HCINT_Pos (25U)
22819#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
22820#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
22821#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
22822#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
22823#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
22824#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
22825#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
22826#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
22827#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
22828#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
22829#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
22830#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
22831#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
22832#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
22833#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
22834#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
22835#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
22836#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
22837#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
22838#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
22840/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
22841#define USB_OTG_GINTMSK_MMISM_Pos (1U)
22842#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
22843#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
22844#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
22845#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
22846#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
22847#define USB_OTG_GINTMSK_SOFM_Pos (3U)
22848#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
22849#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
22850#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
22851#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
22852#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
22853#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
22854#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
22855#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
22856#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
22857#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
22858#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
22859#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
22860#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
22861#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
22862#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
22863#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
22864#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
22865#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
22866#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
22867#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
22868#define USB_OTG_GINTMSK_USBRST_Pos (12U)
22869#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
22870#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
22871#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
22872#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
22873#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
22874#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
22875#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
22876#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
22877#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
22878#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
22879#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
22880#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
22881#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
22882#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
22883#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
22884#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
22885#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
22886#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
22887#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
22888#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
22889#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
22890#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
22891#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
22892#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
22893#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
22894#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
22895#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
22896#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
22897#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
22898#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
22899#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
22900#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
22901#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
22902#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
22903#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
22904#define USB_OTG_GINTMSK_HCIM_Pos (25U)
22905#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
22906#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
22907#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
22908#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
22909#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
22910#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
22911#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
22912#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
22913#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
22914#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
22915#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
22916#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
22917#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
22918#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
22919#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
22920#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
22921#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
22922#define USB_OTG_GINTMSK_WUIM_Pos (31U)
22923#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
22924#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
22926/******************** Bit definition forUSB_OTG_DAINT register ********************/
22927#define USB_OTG_DAINT_IEPINT_Pos (0U)
22928#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
22929#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
22930#define USB_OTG_DAINT_OEPINT_Pos (16U)
22931#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
22932#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
22934/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
22935#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
22936#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
22937#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
22939/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
22940#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
22941#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
22942#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
22943#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
22944#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
22945#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
22946#define USB_OTG_GRXSTSP_DPID_Pos (15U)
22947#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
22948#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
22949#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
22950#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
22951#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
22953/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
22954#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
22955#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
22956#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
22957#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
22958#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
22959#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
22961/******************** Bit definition for OTG register ********************/
22962
22963#define USB_OTG_CHNUM_Pos (0U)
22964#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
22965#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
22966#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
22967#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
22968#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
22969#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
22970#define USB_OTG_BCNT_Pos (4U)
22971#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
22972#define USB_OTG_BCNT USB_OTG_BCNT_Msk
22974#define USB_OTG_DPID_Pos (15U)
22975#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
22976#define USB_OTG_DPID USB_OTG_DPID_Msk
22977#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
22978#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
22980#define USB_OTG_PKTSTS_Pos (17U)
22981#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
22982#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
22983#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
22984#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
22985#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
22986#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
22988#define USB_OTG_EPNUM_Pos (0U)
22989#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
22990#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
22991#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
22992#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
22993#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
22994#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
22996#define USB_OTG_FRMNUM_Pos (21U)
22997#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
22998#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
22999#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
23000#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
23001#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
23002#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
23004/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
23005#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
23006#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
23007#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
23009/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
23010#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
23011#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
23012#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
23014/******************** Bit definition for OTG register ********************/
23015#define USB_OTG_NPTXFSA_Pos (0U)
23016#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
23017#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
23018#define USB_OTG_NPTXFD_Pos (16U)
23019#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
23020#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
23021#define USB_OTG_TX0FSA_Pos (0U)
23022#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
23023#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
23024#define USB_OTG_TX0FD_Pos (16U)
23025#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
23026#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
23028/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
23029#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
23030#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
23031#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
23033/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
23034#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
23035#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
23036#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
23038#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
23039#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23040#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
23041#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23042#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23043#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23044#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23045#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23046#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23047#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23048#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
23050#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
23051#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23052#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
23053#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23054#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23055#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23056#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23057#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23058#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23059#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
23061/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
23062#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
23063#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
23064#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
23065#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
23066#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
23067#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
23069#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
23070#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23071#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
23072#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23073#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23074#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23075#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23076#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23077#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23078#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23079#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23080#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
23081#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
23082#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
23083#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
23085#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
23086#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23087#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
23088#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23089#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23090#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23091#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23092#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23093#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23094#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23095#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23096#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
23097#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
23098#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
23099#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
23101/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
23102#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
23103#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
23104#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
23106/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
23107#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
23108#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
23109#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
23110#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
23111#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
23112#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
23114/******************** Bit definition forUSB_OTG_GCCFG register ********************/
23115#define USB_OTG_GCCFG_DCDET_Pos (0U)
23116#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos)
23117#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk
23118#define USB_OTG_GCCFG_PDET_Pos (1U)
23119#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos)
23120#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk
23121#define USB_OTG_GCCFG_SDET_Pos (2U)
23122#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos)
23123#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk
23124#define USB_OTG_GCCFG_PS2DET_Pos (3U)
23125#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos)
23126#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk
23127#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
23128#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
23129#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
23130#define USB_OTG_GCCFG_BCDEN_Pos (17U)
23131#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos)
23132#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk
23133#define USB_OTG_GCCFG_DCDEN_Pos (18U)
23134#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos)
23135#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk
23136#define USB_OTG_GCCFG_PDEN_Pos (19U)
23137#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos)
23138#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk
23139#define USB_OTG_GCCFG_SDEN_Pos (20U)
23140#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos)
23141#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk
23142#define USB_OTG_GCCFG_VBDEN_Pos (21U)
23143#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
23144#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
23146/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
23147#define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
23148#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos)
23149#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk
23150#define USB_OTG_GPWRDN_ADPIF_Pos (23U)
23151#define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos)
23152#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk
23154/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
23155#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
23156#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
23157#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
23158#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
23159#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
23160#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
23162/******************** Bit definition forUSB_OTG_CID register ********************/
23163#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
23164#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
23165#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
23167/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
23168#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
23169#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
23170#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
23171#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
23172#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
23173#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
23174#define USB_OTG_GLPMCFG_BESL_Pos (2U)
23175#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
23176#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
23177#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
23178#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
23179#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
23180#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
23181#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
23182#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
23183#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
23184#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
23185#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
23186#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
23187#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
23188#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
23189#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
23190#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
23191#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
23192#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
23193#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
23194#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
23195#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
23196#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
23197#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
23198#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
23199#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
23200#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
23201#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
23202#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
23203#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
23204#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
23205#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
23206#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
23207#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
23208#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
23209#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
23210#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
23211#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
23212#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
23214/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
23215#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
23216#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
23217#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
23218#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
23219#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
23220#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
23221#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
23222#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
23223#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
23224#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
23225#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
23226#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
23227#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
23228#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
23229#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
23230#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
23231#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
23232#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
23233#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
23234#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
23235#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
23236#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
23237#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
23238#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
23239#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
23240#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
23241#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
23243/******************** Bit definition forUSB_OTG_HPRT register ********************/
23244#define USB_OTG_HPRT_PCSTS_Pos (0U)
23245#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
23246#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
23247#define USB_OTG_HPRT_PCDET_Pos (1U)
23248#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
23249#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
23250#define USB_OTG_HPRT_PENA_Pos (2U)
23251#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
23252#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
23253#define USB_OTG_HPRT_PENCHNG_Pos (3U)
23254#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
23255#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
23256#define USB_OTG_HPRT_POCA_Pos (4U)
23257#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
23258#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
23259#define USB_OTG_HPRT_POCCHNG_Pos (5U)
23260#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
23261#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
23262#define USB_OTG_HPRT_PRES_Pos (6U)
23263#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
23264#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
23265#define USB_OTG_HPRT_PSUSP_Pos (7U)
23266#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
23267#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
23268#define USB_OTG_HPRT_PRST_Pos (8U)
23269#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
23270#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
23272#define USB_OTG_HPRT_PLSTS_Pos (10U)
23273#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
23274#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
23275#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
23276#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
23277#define USB_OTG_HPRT_PPWR_Pos (12U)
23278#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
23279#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
23281#define USB_OTG_HPRT_PTCTL_Pos (13U)
23282#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
23283#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
23284#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
23285#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
23286#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
23287#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
23289#define USB_OTG_HPRT_PSPD_Pos (17U)
23290#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
23291#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
23292#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
23293#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
23295/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
23296#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
23297#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
23298#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
23299#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
23300#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
23301#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
23302#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
23303#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
23304#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
23305#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
23306#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
23307#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
23308#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
23309#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
23310#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
23311#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
23312#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
23313#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
23314#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
23315#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
23316#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
23317#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
23318#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
23319#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
23320#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
23321#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
23322#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
23323#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
23324#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
23325#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
23326#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
23327#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
23328#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
23330/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
23331#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
23332#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
23333#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
23334#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
23335#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
23336#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
23338/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
23339#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
23340#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
23341#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
23342#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
23343#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
23344#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
23345#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
23346#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
23347#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
23348#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
23349#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
23350#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
23352#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
23353#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
23354#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
23355#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
23356#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
23357#define USB_OTG_DIEPCTL_STALL_Pos (21U)
23358#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
23359#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
23361#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
23362#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
23363#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
23364#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
23365#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
23366#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
23367#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
23368#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
23369#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
23370#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
23371#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
23372#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
23373#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
23374#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
23375#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
23376#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
23377#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
23378#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
23379#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
23380#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
23381#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
23382#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
23383#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
23384#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
23385#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
23387/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
23388#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
23389#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
23390#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
23392#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
23393#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
23394#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
23395#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
23396#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
23397#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
23398#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
23399#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
23400#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
23401#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
23402#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
23403#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
23404#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
23406#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
23407#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
23408#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
23409#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
23410#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
23412#define USB_OTG_HCCHAR_MC_Pos (20U)
23413#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
23414#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
23415#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
23416#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
23418#define USB_OTG_HCCHAR_DAD_Pos (22U)
23419#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
23420#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
23421#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
23422#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
23423#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
23424#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
23425#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
23426#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
23427#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
23428#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
23429#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
23430#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
23431#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
23432#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
23433#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
23434#define USB_OTG_HCCHAR_CHENA_Pos (31U)
23435#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
23436#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
23438/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
23439
23440#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
23441#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
23442#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
23443#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23444#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23445#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23446#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23447#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23448#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23449#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
23451#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
23452#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
23453#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
23454#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23455#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23456#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23457#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23458#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23459#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23460#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
23462#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
23463#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
23464#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
23465#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
23466#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
23467#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
23468#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
23469#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
23470#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
23471#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
23472#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
23474/******************** Bit definition forUSB_OTG_HCINT register ********************/
23475#define USB_OTG_HCINT_XFRC_Pos (0U)
23476#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
23477#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
23478#define USB_OTG_HCINT_CHH_Pos (1U)
23479#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
23480#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
23481#define USB_OTG_HCINT_AHBERR_Pos (2U)
23482#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
23483#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
23484#define USB_OTG_HCINT_STALL_Pos (3U)
23485#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
23486#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
23487#define USB_OTG_HCINT_NAK_Pos (4U)
23488#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
23489#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
23490#define USB_OTG_HCINT_ACK_Pos (5U)
23491#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
23492#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
23493#define USB_OTG_HCINT_NYET_Pos (6U)
23494#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
23495#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
23496#define USB_OTG_HCINT_TXERR_Pos (7U)
23497#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
23498#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
23499#define USB_OTG_HCINT_BBERR_Pos (8U)
23500#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
23501#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
23502#define USB_OTG_HCINT_FRMOR_Pos (9U)
23503#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
23504#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
23505#define USB_OTG_HCINT_DTERR_Pos (10U)
23506#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
23507#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
23509/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
23510#define USB_OTG_DIEPINT_XFRC_Pos (0U)
23511#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
23512#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
23513#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
23514#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
23515#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
23516#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
23517#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
23518#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
23519#define USB_OTG_DIEPINT_TOC_Pos (3U)
23520#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
23521#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
23522#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
23523#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
23524#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
23525#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
23526#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
23527#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
23528#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
23529#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
23530#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
23531#define USB_OTG_DIEPINT_TXFE_Pos (7U)
23532#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
23533#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
23534#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
23535#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
23536#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
23537#define USB_OTG_DIEPINT_BNA_Pos (9U)
23538#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
23539#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
23540#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
23541#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
23542#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
23543#define USB_OTG_DIEPINT_BERR_Pos (12U)
23544#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
23545#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
23546#define USB_OTG_DIEPINT_NAK_Pos (13U)
23547#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
23548#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
23550/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
23551#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
23552#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
23553#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
23554#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
23555#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
23556#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
23557#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
23558#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
23559#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
23560#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
23561#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
23562#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
23563#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
23564#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
23565#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
23566#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
23567#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
23568#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
23569#define USB_OTG_HCINTMSK_NYET_Pos (6U)
23570#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
23571#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
23572#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
23573#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
23574#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
23575#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
23576#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
23577#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
23578#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
23579#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
23580#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
23581#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
23582#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
23583#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
23585/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
23586
23587#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
23588#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
23589#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
23590#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
23591#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
23592#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
23593#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
23594#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
23595#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
23596/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
23597#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
23598#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
23599#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
23600#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
23601#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
23602#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
23603#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
23604#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
23605#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
23606#define USB_OTG_HCTSIZ_DPID_Pos (29U)
23607#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
23608#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
23609#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
23610#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
23612/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
23613#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
23614#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
23615#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
23617/******************** Bit definition forUSB_OTG_HCDMA register ********************/
23618#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
23619#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
23620#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
23622/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
23623#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
23624#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
23625#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
23627/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
23628#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
23629#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
23630#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
23631#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
23632#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
23633#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
23635/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
23636
23637#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
23638#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
23639#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
23640#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
23641#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
23642#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
23643#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
23644#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
23645#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
23646#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
23647#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
23648#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
23649#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
23650#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
23651#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
23652#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
23653#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
23654#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
23655#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
23656#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
23657#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
23658#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
23659#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
23660#define USB_OTG_DOEPCTL_STALL_Pos (21U)
23661#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
23662#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
23663#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
23664#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
23665#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
23666#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
23667#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
23668#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
23669#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
23670#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
23671#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
23672#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
23673#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
23674#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
23676/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
23677#define USB_OTG_DOEPINT_XFRC_Pos (0U)
23678#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
23679#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
23680#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
23681#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
23682#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
23683#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
23684#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
23685#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
23686#define USB_OTG_DOEPINT_STUP_Pos (3U)
23687#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
23688#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
23689#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
23690#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
23691#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
23692#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
23693#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
23694#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
23695#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
23696#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
23697#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
23698#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
23699#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
23700#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
23701#define USB_OTG_DOEPINT_BNA_Pos (9U)
23702#define USB_OTG_DOEPINT_BNA_Msk (0x1UL << USB_OTG_DOEPINT_BNA_Pos)
23703#define USB_OTG_DOEPINT_BNA USB_OTG_DOEPINT_BNA_Msk
23704#define USB_OTG_DOEPINT_BERR_Pos (12U)
23705#define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos)
23706#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk
23707#define USB_OTG_DOEPINT_NAK_Pos (13U)
23708#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
23709#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
23710#define USB_OTG_DOEPINT_NYET_Pos (14U)
23711#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
23712#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
23713#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
23714#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
23715#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
23717/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
23718
23719#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
23720#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
23721#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
23722#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
23723#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
23724#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
23726#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
23727#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
23728#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
23729#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
23730#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
23732/******************** Bit definition for PCGCCTL register ********************/
23733#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
23734#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
23735#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
23736#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
23737#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
23738#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
23739#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
23740#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
23741#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
23755/******************************* ADC Instances ********************************/
23756#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
23757 ((INSTANCE) == ADC2) || \
23758 ((INSTANCE) == ADC3))
23759
23760#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
23761
23762#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
23763 ((INSTANCE) == ADC3_COMMON))
23764
23765/******************************* CORDIC Instances *****************************/
23766#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
23767
23768/******************************** FMAC Instances ******************************/
23769#define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
23770
23771/******************************** COMP Instances ******************************/
23772#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
23773 ((INSTANCE) == COMP2))
23774
23775#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
23776/******************** COMP Instances with window mode capability **************/
23777#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
23778
23779/******************************** DTS Instances ******************************/
23780#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)
23781
23782/******************************* CRC Instances ********************************/
23783#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
23784
23785/******************************* DAC Instances ********************************/
23786#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
23787/******************************* DCMI Instances *******************************/
23788#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
23789
23790/******************************* DELAYBLOCK Instances *******************************/
23791#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
23792 ((INSTANCE) == DLYB_SDMMC2) || \
23793 ((INSTANCE) == DLYB_OCTOSPI1) || \
23794 ((INSTANCE) == DLYB_OCTOSPI2) )
23795/****************************** DFSDM Instances *******************************/
23796#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
23797 ((INSTANCE) == DFSDM1_Filter1) || \
23798 ((INSTANCE) == DFSDM1_Filter2) || \
23799 ((INSTANCE) == DFSDM1_Filter3))
23800
23801#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
23802 ((INSTANCE) == DFSDM1_Channel1) || \
23803 ((INSTANCE) == DFSDM1_Channel2) || \
23804 ((INSTANCE) == DFSDM1_Channel3) || \
23805 ((INSTANCE) == DFSDM1_Channel4) || \
23806 ((INSTANCE) == DFSDM1_Channel5) || \
23807 ((INSTANCE) == DFSDM1_Channel6) || \
23808 ((INSTANCE) == DFSDM1_Channel7))
23809/****************************** RAMECC Instances ******************************/
23810#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1) || \
23811 ((INSTANCE) == RAMECC1_Monitor2) || \
23812 ((INSTANCE) == RAMECC1_Monitor3) || \
23813 ((INSTANCE) == RAMECC1_Monitor4) || \
23814 ((INSTANCE) == RAMECC1_Monitor5) || \
23815 ((INSTANCE) == RAMECC1_Monitor6) || \
23816 ((INSTANCE) == RAMECC2_Monitor1) || \
23817 ((INSTANCE) == RAMECC2_Monitor2) || \
23818 ((INSTANCE) == RAMECC2_Monitor3) || \
23819 ((INSTANCE) == RAMECC3_Monitor1) || \
23820 ((INSTANCE) == RAMECC3_Monitor2))
23821
23822/******************************** DMA Instances *******************************/
23823#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
23824 ((INSTANCE) == DMA1_Stream1) || \
23825 ((INSTANCE) == DMA1_Stream2) || \
23826 ((INSTANCE) == DMA1_Stream3) || \
23827 ((INSTANCE) == DMA1_Stream4) || \
23828 ((INSTANCE) == DMA1_Stream5) || \
23829 ((INSTANCE) == DMA1_Stream6) || \
23830 ((INSTANCE) == DMA1_Stream7) || \
23831 ((INSTANCE) == DMA2_Stream0) || \
23832 ((INSTANCE) == DMA2_Stream1) || \
23833 ((INSTANCE) == DMA2_Stream2) || \
23834 ((INSTANCE) == DMA2_Stream3) || \
23835 ((INSTANCE) == DMA2_Stream4) || \
23836 ((INSTANCE) == DMA2_Stream5) || \
23837 ((INSTANCE) == DMA2_Stream6) || \
23838 ((INSTANCE) == DMA2_Stream7) || \
23839 ((INSTANCE) == BDMA_Channel0) || \
23840 ((INSTANCE) == BDMA_Channel1) || \
23841 ((INSTANCE) == BDMA_Channel2) || \
23842 ((INSTANCE) == BDMA_Channel3) || \
23843 ((INSTANCE) == BDMA_Channel4) || \
23844 ((INSTANCE) == BDMA_Channel5) || \
23845 ((INSTANCE) == BDMA_Channel6) || \
23846 ((INSTANCE) == BDMA_Channel7))
23847
23848/****************************** BDMA CHANNEL Instances ***************************/
23849#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
23850 ((INSTANCE) == BDMA_Channel1) || \
23851 ((INSTANCE) == BDMA_Channel2) || \
23852 ((INSTANCE) == BDMA_Channel3) || \
23853 ((INSTANCE) == BDMA_Channel4) || \
23854 ((INSTANCE) == BDMA_Channel5) || \
23855 ((INSTANCE) == BDMA_Channel6) || \
23856 ((INSTANCE) == BDMA_Channel7))
23857
23858/****************************** DMA DMAMUX ALL Instances ***************************/
23859#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
23860 ((INSTANCE) == DMA1_Stream1) || \
23861 ((INSTANCE) == DMA1_Stream2) || \
23862 ((INSTANCE) == DMA1_Stream3) || \
23863 ((INSTANCE) == DMA1_Stream4) || \
23864 ((INSTANCE) == DMA1_Stream5) || \
23865 ((INSTANCE) == DMA1_Stream6) || \
23866 ((INSTANCE) == DMA1_Stream7) || \
23867 ((INSTANCE) == DMA2_Stream0) || \
23868 ((INSTANCE) == DMA2_Stream1) || \
23869 ((INSTANCE) == DMA2_Stream2) || \
23870 ((INSTANCE) == DMA2_Stream3) || \
23871 ((INSTANCE) == DMA2_Stream4) || \
23872 ((INSTANCE) == DMA2_Stream5) || \
23873 ((INSTANCE) == DMA2_Stream6) || \
23874 ((INSTANCE) == DMA2_Stream7) || \
23875 ((INSTANCE) == BDMA_Channel0) || \
23876 ((INSTANCE) == BDMA_Channel1) || \
23877 ((INSTANCE) == BDMA_Channel2) || \
23878 ((INSTANCE) == BDMA_Channel3) || \
23879 ((INSTANCE) == BDMA_Channel4) || \
23880 ((INSTANCE) == BDMA_Channel5) || \
23881 ((INSTANCE) == BDMA_Channel6) || \
23882 ((INSTANCE) == BDMA_Channel7))
23883
23884/****************************** BDMA DMAMUX Instances ***************************/
23885#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
23886 ((INSTANCE) == BDMA_Channel1) || \
23887 ((INSTANCE) == BDMA_Channel2) || \
23888 ((INSTANCE) == BDMA_Channel3) || \
23889 ((INSTANCE) == BDMA_Channel4) || \
23890 ((INSTANCE) == BDMA_Channel5) || \
23891 ((INSTANCE) == BDMA_Channel6) || \
23892 ((INSTANCE) == BDMA_Channel7))
23893
23894/****************************** DMA STREAM Instances ***************************/
23895#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
23896 ((INSTANCE) == DMA1_Stream1) || \
23897 ((INSTANCE) == DMA1_Stream2) || \
23898 ((INSTANCE) == DMA1_Stream3) || \
23899 ((INSTANCE) == DMA1_Stream4) || \
23900 ((INSTANCE) == DMA1_Stream5) || \
23901 ((INSTANCE) == DMA1_Stream6) || \
23902 ((INSTANCE) == DMA1_Stream7) || \
23903 ((INSTANCE) == DMA2_Stream0) || \
23904 ((INSTANCE) == DMA2_Stream1) || \
23905 ((INSTANCE) == DMA2_Stream2) || \
23906 ((INSTANCE) == DMA2_Stream3) || \
23907 ((INSTANCE) == DMA2_Stream4) || \
23908 ((INSTANCE) == DMA2_Stream5) || \
23909 ((INSTANCE) == DMA2_Stream6) || \
23910 ((INSTANCE) == DMA2_Stream7))
23911
23912/****************************** DMA DMAMUX Instances ***************************/
23913#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
23914 ((INSTANCE) == DMA1_Stream1) || \
23915 ((INSTANCE) == DMA1_Stream2) || \
23916 ((INSTANCE) == DMA1_Stream3) || \
23917 ((INSTANCE) == DMA1_Stream4) || \
23918 ((INSTANCE) == DMA1_Stream5) || \
23919 ((INSTANCE) == DMA1_Stream6) || \
23920 ((INSTANCE) == DMA1_Stream7) || \
23921 ((INSTANCE) == DMA2_Stream0) || \
23922 ((INSTANCE) == DMA2_Stream1) || \
23923 ((INSTANCE) == DMA2_Stream2) || \
23924 ((INSTANCE) == DMA2_Stream3) || \
23925 ((INSTANCE) == DMA2_Stream4) || \
23926 ((INSTANCE) == DMA2_Stream5) || \
23927 ((INSTANCE) == DMA2_Stream6) || \
23928 ((INSTANCE) == DMA2_Stream7))
23929
23930/******************************** DMA Request Generator Instances **************/
23931#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
23932 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
23933 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
23934 ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
23935 ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
23936 ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
23937 ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
23938 ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
23939 ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
23940 ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
23941 ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
23942 ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
23943 ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
23944 ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
23945 ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
23946 ((INSTANCE) == DMAMUX2_RequestGenerator7))
23947
23948/******************************* DMA2D Instances *******************************/
23949#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
23950
23951/******************************* OTFDEC Instances ******************************/
23952#define IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OTFDEC1) || \
23953 ((__INSTANCE__) == OTFDEC2))
23954
23955/****************************** PSSI Instance *********************************/
23956#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)
23957
23958/******************************** MDMA Request Generator Instances **************/
23959#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
23960 ((INSTANCE) == MDMA_Channel1) || \
23961 ((INSTANCE) == MDMA_Channel2) || \
23962 ((INSTANCE) == MDMA_Channel3) || \
23963 ((INSTANCE) == MDMA_Channel4) || \
23964 ((INSTANCE) == MDMA_Channel5) || \
23965 ((INSTANCE) == MDMA_Channel6) || \
23966 ((INSTANCE) == MDMA_Channel7) || \
23967 ((INSTANCE) == MDMA_Channel8) || \
23968 ((INSTANCE) == MDMA_Channel9) || \
23969 ((INSTANCE) == MDMA_Channel10) || \
23970 ((INSTANCE) == MDMA_Channel11) || \
23971 ((INSTANCE) == MDMA_Channel12) || \
23972 ((INSTANCE) == MDMA_Channel13) || \
23973 ((INSTANCE) == MDMA_Channel14) || \
23974 ((INSTANCE) == MDMA_Channel15))
23975
23976
23977/******************************* FDCAN Instances ******************************/
23978#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
23979 ((__INSTANCE__) == FDCAN2) || \
23980 ((__INSTANCE__) == FDCAN3))
23981
23982#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
23983
23984/******************************* GPIO Instances *******************************/
23985#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
23986 ((INSTANCE) == GPIOB) || \
23987 ((INSTANCE) == GPIOC) || \
23988 ((INSTANCE) == GPIOD) || \
23989 ((INSTANCE) == GPIOE) || \
23990 ((INSTANCE) == GPIOF) || \
23991 ((INSTANCE) == GPIOG) || \
23992 ((INSTANCE) == GPIOH) || \
23993 ((INSTANCE) == GPIOJ) || \
23994 ((INSTANCE) == GPIOK))
23995
23996/******************************* GPIO AF Instances ****************************/
23997#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
23998
23999/**************************** GPIO Lock Instances *****************************/
24000/* On H7, all GPIO Bank support the Lock mechanism */
24001#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
24002
24003/******************************** HSEM Instances *******************************/
24004#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
24005#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
24006#define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
24007#define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
24008
24009#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
24010#define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
24011
24012#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
24013#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
24014
24015#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
24016#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
24017
24018/******************************** I2C Instances *******************************/
24019#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
24020 ((INSTANCE) == I2C2) || \
24021 ((INSTANCE) == I2C3) || \
24022 ((INSTANCE) == I2C4) || \
24023 ((INSTANCE) == I2C5))
24024
24025/****************************** SMBUS Instances *******************************/
24026#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
24027 ((INSTANCE) == I2C2) || \
24028 ((INSTANCE) == I2C3) || \
24029 ((INSTANCE) == I2C4) || \
24030 ((INSTANCE) == I2C5))
24031
24032/************** I2C Instances : wakeup capability from stop modes *************/
24033#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
24034
24035/******************************** I2S Instances *******************************/
24036#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
24037 ((INSTANCE) == SPI2) || \
24038 ((INSTANCE) == SPI3))
24039
24040/****************************** LTDC Instances ********************************/
24041#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
24042
24043/******************************* RNG Instances ********************************/
24044#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
24045
24046/****************************** RTC Instances *********************************/
24047#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
24048
24049/****************************** SDMMC Instances *********************************/
24050#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
24051 ((_INSTANCE_) == SDMMC2))
24052
24053/******************************** SPI Instances *******************************/
24054#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
24055 ((INSTANCE) == SPI2) || \
24056 ((INSTANCE) == SPI3) || \
24057 ((INSTANCE) == SPI4) || \
24058 ((INSTANCE) == SPI5) || \
24059 ((INSTANCE) == SPI6))
24060
24061#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
24062 ((INSTANCE) == SPI2) || \
24063 ((INSTANCE) == SPI3))
24064
24065/******************************** SWPMI Instances *****************************/
24066#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
24067
24068/****************** LPTIM Instances : All supported instances *****************/
24069#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
24070 ((INSTANCE) == LPTIM2) || \
24071 ((INSTANCE) == LPTIM3) || \
24072 ((INSTANCE) == LPTIM4) || \
24073 ((INSTANCE) == LPTIM5))
24074
24075/****************** LPTIM Instances : supporting encoder interface **************/
24076#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
24077 ((INSTANCE) == LPTIM2))
24078
24079/****************** TIM Instances : All supported instances *******************/
24080#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24081 ((INSTANCE) == TIM2) || \
24082 ((INSTANCE) == TIM3) || \
24083 ((INSTANCE) == TIM4) || \
24084 ((INSTANCE) == TIM5) || \
24085 ((INSTANCE) == TIM6) || \
24086 ((INSTANCE) == TIM7) || \
24087 ((INSTANCE) == TIM8) || \
24088 ((INSTANCE) == TIM12) || \
24089 ((INSTANCE) == TIM13) || \
24090 ((INSTANCE) == TIM14) || \
24091 ((INSTANCE) == TIM15) || \
24092 ((INSTANCE) == TIM16) || \
24093 ((INSTANCE) == TIM17) || \
24094 ((INSTANCE) == TIM23) || \
24095 ((INSTANCE) == TIM24))
24096
24097/************* TIM Instances : at least 1 capture/compare channel *************/
24098#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24099 ((INSTANCE) == TIM2) || \
24100 ((INSTANCE) == TIM3) || \
24101 ((INSTANCE) == TIM4) || \
24102 ((INSTANCE) == TIM5) || \
24103 ((INSTANCE) == TIM8) || \
24104 ((INSTANCE) == TIM12) || \
24105 ((INSTANCE) == TIM13) || \
24106 ((INSTANCE) == TIM14) || \
24107 ((INSTANCE) == TIM15) || \
24108 ((INSTANCE) == TIM16) || \
24109 ((INSTANCE) == TIM17) || \
24110 ((INSTANCE) == TIM23) || \
24111 ((INSTANCE) == TIM24))
24112
24113/************ TIM Instances : at least 2 capture/compare channels *************/
24114#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24115 ((INSTANCE) == TIM2) || \
24116 ((INSTANCE) == TIM3) || \
24117 ((INSTANCE) == TIM4) || \
24118 ((INSTANCE) == TIM5) || \
24119 ((INSTANCE) == TIM8) || \
24120 ((INSTANCE) == TIM12) || \
24121 ((INSTANCE) == TIM15) || \
24122 ((INSTANCE) == TIM23) || \
24123 ((INSTANCE) == TIM24))
24124
24125/************ TIM Instances : at least 3 capture/compare channels *************/
24126#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24127 ((INSTANCE) == TIM2) || \
24128 ((INSTANCE) == TIM3) || \
24129 ((INSTANCE) == TIM4) || \
24130 ((INSTANCE) == TIM5) || \
24131 ((INSTANCE) == TIM8) || \
24132 ((INSTANCE) == TIM23) || \
24133 ((INSTANCE) == TIM24))
24134
24135/************ TIM Instances : at least 4 capture/compare channels *************/
24136#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24137 ((INSTANCE) == TIM2) || \
24138 ((INSTANCE) == TIM3) || \
24139 ((INSTANCE) == TIM4) || \
24140 ((INSTANCE) == TIM5) || \
24141 ((INSTANCE) == TIM8) || \
24142 ((INSTANCE) == TIM23) || \
24143 ((INSTANCE) == TIM24))
24144
24145/************ TIM Instances : at least 5 capture/compare channels *************/
24146#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24147 ((INSTANCE) == TIM8))
24148/************ TIM Instances : at least 6 capture/compare channels *************/
24149#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24150 ((INSTANCE) == TIM8))
24151
24152/******************** TIM Instances : Advanced-control timers *****************/
24153#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
24154 ((__INSTANCE__) == TIM8))
24155
24156/******************** TIM Instances : Advanced-control timers *****************/
24157
24158/******************* TIM Instances : Timer input XOR function *****************/
24159#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24160 ((INSTANCE) == TIM2) || \
24161 ((INSTANCE) == TIM3) || \
24162 ((INSTANCE) == TIM4) || \
24163 ((INSTANCE) == TIM5) || \
24164 ((INSTANCE) == TIM8) || \
24165 ((INSTANCE) == TIM15) || \
24166 ((INSTANCE) == TIM23) || \
24167 ((INSTANCE) == TIM24))
24168
24169/****************** TIM Instances : DMA requests generation (UDE) *************/
24170#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24171 ((INSTANCE) == TIM2) || \
24172 ((INSTANCE) == TIM3) || \
24173 ((INSTANCE) == TIM4) || \
24174 ((INSTANCE) == TIM5) || \
24175 ((INSTANCE) == TIM6) || \
24176 ((INSTANCE) == TIM7) || \
24177 ((INSTANCE) == TIM8) || \
24178 ((INSTANCE) == TIM15) || \
24179 ((INSTANCE) == TIM16) || \
24180 ((INSTANCE) == TIM17) || \
24181 ((INSTANCE) == TIM23) || \
24182 ((INSTANCE) == TIM24))
24183
24184/************ TIM Instances : DMA requests generation (CCxDE) *****************/
24185#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24186 ((INSTANCE) == TIM2) || \
24187 ((INSTANCE) == TIM3) || \
24188 ((INSTANCE) == TIM4) || \
24189 ((INSTANCE) == TIM5) || \
24190 ((INSTANCE) == TIM8) || \
24191 ((INSTANCE) == TIM15) || \
24192 ((INSTANCE) == TIM16) || \
24193 ((INSTANCE) == TIM17) || \
24194 ((INSTANCE) == TIM23) || \
24195 ((INSTANCE) == TIM24))
24196
24197/************ TIM Instances : DMA requests generation (COMDE) *****************/
24198#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24199 ((INSTANCE) == TIM2) || \
24200 ((INSTANCE) == TIM3) || \
24201 ((INSTANCE) == TIM4) || \
24202 ((INSTANCE) == TIM5) || \
24203 ((INSTANCE) == TIM8) || \
24204 ((INSTANCE) == TIM15))
24205
24206/******************** TIM Instances : DMA burst feature ***********************/
24207#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24208 ((INSTANCE) == TIM2) || \
24209 ((INSTANCE) == TIM3) || \
24210 ((INSTANCE) == TIM4) || \
24211 ((INSTANCE) == TIM5) || \
24212 ((INSTANCE) == TIM8))
24213
24214/*************** TIM Instances : external trigger reamp input available *******/
24215#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24216 ((INSTANCE) == TIM2) || \
24217 ((INSTANCE) == TIM3) || \
24218 ((INSTANCE) == TIM4) || \
24219 ((INSTANCE) == TIM5) || \
24220 ((INSTANCE) == TIM8) || \
24221 ((INSTANCE) == TIM23) || \
24222 ((INSTANCE) == TIM24))
24223
24224/****************** TIM Instances : remapping capability **********************/
24225#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24226 ((INSTANCE) == TIM2) || \
24227 ((INSTANCE) == TIM3) || \
24228 ((INSTANCE) == TIM5) || \
24229 ((INSTANCE) == TIM8) || \
24230 ((INSTANCE) == TIM16) || \
24231 ((INSTANCE) == TIM17) || \
24232 ((INSTANCE) == TIM23) || \
24233 ((INSTANCE) == TIM24))
24234
24235/*************** TIM Instances : external trigger reamp input available *******/
24236#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24237 ((INSTANCE) == TIM2) || \
24238 ((INSTANCE) == TIM3) || \
24239 ((INSTANCE) == TIM5) || \
24240 ((INSTANCE) == TIM8) || \
24241 ((INSTANCE) == TIM23) || \
24242 ((INSTANCE) == TIM24)))
24243
24244/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
24245#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24246 ((INSTANCE) == TIM2) || \
24247 ((INSTANCE) == TIM3) || \
24248 ((INSTANCE) == TIM4) || \
24249 ((INSTANCE) == TIM5) || \
24250 ((INSTANCE) == TIM6) || \
24251 ((INSTANCE) == TIM7) || \
24252 ((INSTANCE) == TIM8) || \
24253 ((INSTANCE) == TIM12) || \
24254 ((INSTANCE) == TIM15) || \
24255 ((INSTANCE) == TIM23) || \
24256 ((INSTANCE) == TIM24))
24257
24258/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
24259#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24260 ((INSTANCE) == TIM2) || \
24261 ((INSTANCE) == TIM3) || \
24262 ((INSTANCE) == TIM4) || \
24263 ((INSTANCE) == TIM5) || \
24264 ((INSTANCE) == TIM8) || \
24265 ((INSTANCE) == TIM12) || \
24266 ((INSTANCE) == TIM15) || \
24267 ((INSTANCE) == TIM23) || \
24268 ((INSTANCE) == TIM24))
24269
24270/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
24271#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24272 ((INSTANCE) == TIM8))
24273
24274/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
24275#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24276 ((INSTANCE) == TIM2) || \
24277 ((INSTANCE) == TIM3) || \
24278 ((INSTANCE) == TIM4) || \
24279 ((INSTANCE) == TIM5) || \
24280 ((INSTANCE) == TIM8) || \
24281 ((INSTANCE) == TIM15) || \
24282 ((INSTANCE) == TIM16) || \
24283 ((INSTANCE) == TIM17) || \
24284 ((INSTANCE) == TIM23) || \
24285 ((INSTANCE) == TIM24))
24286
24287/****************** TIM Instances : supporting commutation event *************/
24288#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24289 ((INSTANCE) == TIM8) || \
24290 ((INSTANCE) == TIM15) || \
24291 ((INSTANCE) == TIM16) || \
24292 ((INSTANCE) == TIM17))
24293
24294/****************** TIM Instances : supporting encoder interface **************/
24295#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
24296 ((__INSTANCE__) == TIM2) || \
24297 ((__INSTANCE__) == TIM3) || \
24298 ((__INSTANCE__) == TIM4) || \
24299 ((__INSTANCE__) == TIM5) || \
24300 ((__INSTANCE__) == TIM8) || \
24301 ((__INSTANCE__) == TIM23) || \
24302 ((__INSTANCE__) == TIM24))
24303
24304/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
24305#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24306 ((INSTANCE) == TIM8))
24307/******************* TIM Instances : output(s) available **********************/
24308#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
24309 ((((INSTANCE) == TIM1) && \
24310 (((CHANNEL) == TIM_CHANNEL_1) || \
24311 ((CHANNEL) == TIM_CHANNEL_2) || \
24312 ((CHANNEL) == TIM_CHANNEL_3) || \
24313 ((CHANNEL) == TIM_CHANNEL_4) || \
24314 ((CHANNEL) == TIM_CHANNEL_5) || \
24315 ((CHANNEL) == TIM_CHANNEL_6))) \
24316 || \
24317 (((INSTANCE) == TIM2) && \
24318 (((CHANNEL) == TIM_CHANNEL_1) || \
24319 ((CHANNEL) == TIM_CHANNEL_2) || \
24320 ((CHANNEL) == TIM_CHANNEL_3) || \
24321 ((CHANNEL) == TIM_CHANNEL_4))) \
24322 || \
24323 (((INSTANCE) == TIM3) && \
24324 (((CHANNEL) == TIM_CHANNEL_1)|| \
24325 ((CHANNEL) == TIM_CHANNEL_2) || \
24326 ((CHANNEL) == TIM_CHANNEL_3) || \
24327 ((CHANNEL) == TIM_CHANNEL_4))) \
24328 || \
24329 (((INSTANCE) == TIM4) && \
24330 (((CHANNEL) == TIM_CHANNEL_1) || \
24331 ((CHANNEL) == TIM_CHANNEL_2) || \
24332 ((CHANNEL) == TIM_CHANNEL_3) || \
24333 ((CHANNEL) == TIM_CHANNEL_4))) \
24334 || \
24335 (((INSTANCE) == TIM5) && \
24336 (((CHANNEL) == TIM_CHANNEL_1) || \
24337 ((CHANNEL) == TIM_CHANNEL_2) || \
24338 ((CHANNEL) == TIM_CHANNEL_3) || \
24339 ((CHANNEL) == TIM_CHANNEL_4))) \
24340 || \
24341 (((INSTANCE) == TIM8) && \
24342 (((CHANNEL) == TIM_CHANNEL_1) || \
24343 ((CHANNEL) == TIM_CHANNEL_2) || \
24344 ((CHANNEL) == TIM_CHANNEL_3) || \
24345 ((CHANNEL) == TIM_CHANNEL_4) || \
24346 ((CHANNEL) == TIM_CHANNEL_5) || \
24347 ((CHANNEL) == TIM_CHANNEL_6))) \
24348 || \
24349 (((INSTANCE) == TIM12) && \
24350 (((CHANNEL) == TIM_CHANNEL_1) || \
24351 ((CHANNEL) == TIM_CHANNEL_2))) \
24352 || \
24353 (((INSTANCE) == TIM13) && \
24354 (((CHANNEL) == TIM_CHANNEL_1))) \
24355 || \
24356 (((INSTANCE) == TIM14) && \
24357 (((CHANNEL) == TIM_CHANNEL_1))) \
24358 || \
24359 (((INSTANCE) == TIM15) && \
24360 (((CHANNEL) == TIM_CHANNEL_1) || \
24361 ((CHANNEL) == TIM_CHANNEL_2))) \
24362 || \
24363 (((INSTANCE) == TIM16) && \
24364 (((CHANNEL) == TIM_CHANNEL_1))) \
24365 || \
24366 (((INSTANCE) == TIM17) && \
24367 (((CHANNEL) == TIM_CHANNEL_1))) \
24368 || \
24369 (((INSTANCE) == TIM23) && \
24370 (((CHANNEL) == TIM_CHANNEL_1) || \
24371 ((CHANNEL) == TIM_CHANNEL_2) || \
24372 ((CHANNEL) == TIM_CHANNEL_3) || \
24373 ((CHANNEL) == TIM_CHANNEL_4))) \
24374 || \
24375 (((INSTANCE) == TIM24) && \
24376 (((CHANNEL) == TIM_CHANNEL_1) || \
24377 ((CHANNEL) == TIM_CHANNEL_2) || \
24378 ((CHANNEL) == TIM_CHANNEL_3) || \
24379 ((CHANNEL) == TIM_CHANNEL_4))))
24380
24381/****************** TIM Instances : supporting the break function *************/
24382#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
24383 (((INSTANCE) == TIM1) || \
24384 ((INSTANCE) == TIM8) || \
24385 ((INSTANCE) == TIM15) || \
24386 ((INSTANCE) == TIM16) || \
24387 ((INSTANCE) == TIM17))
24388
24389/************** TIM Instances : supporting Break source selection *************/
24390#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
24391 ((INSTANCE) == TIM8))
24392
24393/****************** TIM Instances : supporting complementary output(s) ********/
24394#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
24395 ((((INSTANCE) == TIM1) && \
24396 (((CHANNEL) == TIM_CHANNEL_1) || \
24397 ((CHANNEL) == TIM_CHANNEL_2) || \
24398 ((CHANNEL) == TIM_CHANNEL_3))) \
24399 || \
24400 (((INSTANCE) == TIM8) && \
24401 (((CHANNEL) == TIM_CHANNEL_1) || \
24402 ((CHANNEL) == TIM_CHANNEL_2) || \
24403 ((CHANNEL) == TIM_CHANNEL_3))) \
24404 || \
24405 (((INSTANCE) == TIM15) && \
24406 ((CHANNEL) == TIM_CHANNEL_1)) \
24407 || \
24408 (((INSTANCE) == TIM16) && \
24409 ((CHANNEL) == TIM_CHANNEL_1)) \
24410 || \
24411 (((INSTANCE) == TIM17) && \
24412 ((CHANNEL) == TIM_CHANNEL_1)))
24413
24414/****************** TIM Instances : supporting counting mode selection ********/
24415#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
24416 (((INSTANCE) == TIM1) || \
24417 ((INSTANCE) == TIM2) || \
24418 ((INSTANCE) == TIM3) || \
24419 ((INSTANCE) == TIM4) || \
24420 ((INSTANCE) == TIM5) || \
24421 ((INSTANCE) == TIM8))
24422
24423/****************** TIM Instances : supporting repetition counter *************/
24424#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
24425 (((INSTANCE) == TIM1) || \
24426 ((INSTANCE) == TIM8) || \
24427 ((INSTANCE) == TIM15) || \
24428 ((INSTANCE) == TIM16) || \
24429 ((INSTANCE) == TIM17))
24430
24431/****************** TIM Instances : supporting synchronization ****************/
24432#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
24433 (((__INSTANCE__) == TIM1) || \
24434 ((__INSTANCE__) == TIM2) || \
24435 ((__INSTANCE__) == TIM3) || \
24436 ((__INSTANCE__) == TIM4) || \
24437 ((__INSTANCE__) == TIM5) || \
24438 ((__INSTANCE__) == TIM6) || \
24439 ((__INSTANCE__) == TIM8) || \
24440 ((__INSTANCE__) == TIM12) || \
24441 ((__INSTANCE__) == TIM15) || \
24442 ((__INSTANCE__) == TIM23) || \
24443 ((__INSTANCE__) == TIM24))
24444
24445/****************** TIM Instances : supporting clock division *****************/
24446#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
24447 (((INSTANCE) == TIM1) || \
24448 ((INSTANCE) == TIM2) || \
24449 ((INSTANCE) == TIM3) || \
24450 ((INSTANCE) == TIM4) || \
24451 ((INSTANCE) == TIM5) || \
24452 ((INSTANCE) == TIM8) || \
24453 ((INSTANCE) == TIM15) || \
24454 ((INSTANCE) == TIM16) || \
24455 ((INSTANCE) == TIM17) || \
24456 ((INSTANCE) == TIM23) || \
24457 ((INSTANCE) == TIM24))
24458
24459/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
24460#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
24461 (((INSTANCE) == TIM1) || \
24462 ((INSTANCE) == TIM2) || \
24463 ((INSTANCE) == TIM3) || \
24464 ((INSTANCE) == TIM4) || \
24465 ((INSTANCE) == TIM5) || \
24466 ((INSTANCE) == TIM8) || \
24467 ((INSTANCE) == TIM23) || \
24468 ((INSTANCE) == TIM24))
24469
24470/****************** TIM Instances : supporting external clock mode 2 **********/
24471#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
24472 (((INSTANCE) == TIM1) || \
24473 ((INSTANCE) == TIM2) || \
24474 ((INSTANCE) == TIM3) || \
24475 ((INSTANCE) == TIM4) || \
24476 ((INSTANCE) == TIM5) || \
24477 ((INSTANCE) == TIM8) || \
24478 ((INSTANCE) == TIM23) || \
24479 ((INSTANCE) == TIM24))
24480
24481/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
24482#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
24483 (((INSTANCE) == TIM1) || \
24484 ((INSTANCE) == TIM2) || \
24485 ((INSTANCE) == TIM3) || \
24486 ((INSTANCE) == TIM4) || \
24487 ((INSTANCE) == TIM5) || \
24488 ((INSTANCE) == TIM8) || \
24489 ((INSTANCE) == TIM12) || \
24490 ((INSTANCE) == TIM15) || \
24491 ((INSTANCE) == TIM23) || \
24492 ((INSTANCE) == TIM24))
24493
24494/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
24495#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
24496 (((INSTANCE) == TIM1) || \
24497 ((INSTANCE) == TIM2) || \
24498 ((INSTANCE) == TIM3) || \
24499 ((INSTANCE) == TIM4) || \
24500 ((INSTANCE) == TIM5) || \
24501 ((INSTANCE) == TIM8) || \
24502 ((INSTANCE) == TIM12) || \
24503 ((INSTANCE) == TIM15) || \
24504 ((INSTANCE) == TIM23) || \
24505 ((INSTANCE) == TIM24))
24506
24507/****************** TIM Instances : supporting OCxREF clear *******************/
24508#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
24509 (((INSTANCE) == TIM1) || \
24510 ((INSTANCE) == TIM2) || \
24511 ((INSTANCE) == TIM3))
24512
24513/****************** TIM Instances : TIM_32B_COUNTER ***************************/
24514#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
24515 (((INSTANCE) == TIM2) || \
24516 ((INSTANCE) == TIM5) || \
24517 ((INSTANCE) == TIM23) || \
24518 ((INSTANCE) == TIM24))
24519
24520/****************** TIM Instances : TIM_BKIN2 ***************************/
24521#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
24522 (((INSTANCE) == TIM1) || \
24523 ((INSTANCE) == TIM8))
24524
24525/****************** TIM Instances : supporting Hall sensor interface **********/
24526#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
24527 ((__INSTANCE__) == TIM2) || \
24528 ((__INSTANCE__) == TIM3) || \
24529 ((__INSTANCE__) == TIM4) || \
24530 ((__INSTANCE__) == TIM5) || \
24531 ((__INSTANCE__) == TIM15) || \
24532 ((__INSTANCE__) == TIM8) || \
24533 ((__INSTANCE__) == TIM23) || \
24534 ((__INSTANCE__) == TIM24))
24535
24536/******************** USART Instances : Synchronous mode **********************/
24537#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24538 ((INSTANCE) == USART2) || \
24539 ((INSTANCE) == USART3) || \
24540 ((INSTANCE) == USART6) || \
24541 ((INSTANCE) == USART10))
24542
24543/******************** USART Instances : SPI slave mode ************************/
24544#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24545 ((INSTANCE) == USART2) || \
24546 ((INSTANCE) == USART3) || \
24547 ((INSTANCE) == USART6) || \
24548 ((INSTANCE) == USART10))
24549
24550/******************** UART Instances : Asynchronous mode **********************/
24551#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24552 ((INSTANCE) == USART2) || \
24553 ((INSTANCE) == USART3) || \
24554 ((INSTANCE) == UART4) || \
24555 ((INSTANCE) == UART5) || \
24556 ((INSTANCE) == USART6) || \
24557 ((INSTANCE) == UART7) || \
24558 ((INSTANCE) == UART8) || \
24559 ((INSTANCE) == UART9) || \
24560 ((INSTANCE) == USART10))
24561
24562/******************** UART Instances : FIFO mode.******************************/
24563#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24564 ((INSTANCE) == USART2) || \
24565 ((INSTANCE) == USART3) || \
24566 ((INSTANCE) == UART4) || \
24567 ((INSTANCE) == UART5) || \
24568 ((INSTANCE) == USART6) || \
24569 ((INSTANCE) == UART7) || \
24570 ((INSTANCE) == UART8) || \
24571 ((INSTANCE) == UART9) || \
24572 ((INSTANCE) == USART10)|| \
24573 ((INSTANCE) == LPUART1))
24574
24575/****************** UART Instances : Auto Baud Rate detection *****************/
24576#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24577 ((INSTANCE) == USART2) || \
24578 ((INSTANCE) == USART3) || \
24579 ((INSTANCE) == UART4) || \
24580 ((INSTANCE) == UART5) || \
24581 ((INSTANCE) == USART6) || \
24582 ((INSTANCE) == UART7) || \
24583 ((INSTANCE) == UART8) || \
24584 ((INSTANCE) == UART9) || \
24585 ((INSTANCE) == USART10))
24586
24587/*********************** UART Instances : Driver Enable ***********************/
24588#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24589 ((INSTANCE) == USART2) || \
24590 ((INSTANCE) == USART3) || \
24591 ((INSTANCE) == UART4) || \
24592 ((INSTANCE) == UART5) || \
24593 ((INSTANCE) == USART6) || \
24594 ((INSTANCE) == UART7) || \
24595 ((INSTANCE) == UART8) || \
24596 ((INSTANCE) == UART9) || \
24597 ((INSTANCE) == USART10)|| \
24598 ((INSTANCE) == LPUART1))
24599
24600/********************* UART Instances : Half-Duplex mode **********************/
24601#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24602 ((INSTANCE) == USART2) || \
24603 ((INSTANCE) == USART3) || \
24604 ((INSTANCE) == UART4) || \
24605 ((INSTANCE) == UART5) || \
24606 ((INSTANCE) == USART6) || \
24607 ((INSTANCE) == UART7) || \
24608 ((INSTANCE) == UART8) || \
24609 ((INSTANCE) == UART9) || \
24610 ((INSTANCE) == USART10)|| \
24611 ((INSTANCE) == LPUART1))
24612
24613/******************* UART Instances : Hardware Flow control *******************/
24614#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24615 ((INSTANCE) == USART2) || \
24616 ((INSTANCE) == USART3) || \
24617 ((INSTANCE) == UART4) || \
24618 ((INSTANCE) == UART5) || \
24619 ((INSTANCE) == USART6) || \
24620 ((INSTANCE) == UART7) || \
24621 ((INSTANCE) == UART8) || \
24622 ((INSTANCE) == UART9) || \
24623 ((INSTANCE) == USART10)|| \
24624 ((INSTANCE) == LPUART1))
24625
24626/************************* UART Instances : LIN mode **************************/
24627#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24628 ((INSTANCE) == USART2) || \
24629 ((INSTANCE) == USART3) || \
24630 ((INSTANCE) == UART4) || \
24631 ((INSTANCE) == UART5) || \
24632 ((INSTANCE) == USART6) || \
24633 ((INSTANCE) == UART7) || \
24634 ((INSTANCE) == UART8) || \
24635 ((INSTANCE) == UART9) || \
24636 ((INSTANCE) == USART10))
24637
24638/****************** UART Instances : Wake-up from Stop mode *******************/
24639#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24640 ((INSTANCE) == USART2) || \
24641 ((INSTANCE) == USART3) || \
24642 ((INSTANCE) == UART4) || \
24643 ((INSTANCE) == UART5) || \
24644 ((INSTANCE) == USART6) || \
24645 ((INSTANCE) == UART7) || \
24646 ((INSTANCE) == UART8) || \
24647 ((INSTANCE) == UART9) || \
24648 ((INSTANCE) == USART10)|| \
24649 ((INSTANCE) == LPUART1))
24650
24651/************************* UART Instances : IRDA mode *************************/
24652#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24653 ((INSTANCE) == USART2) || \
24654 ((INSTANCE) == USART3) || \
24655 ((INSTANCE) == UART4) || \
24656 ((INSTANCE) == UART5) || \
24657 ((INSTANCE) == USART6) || \
24658 ((INSTANCE) == UART7) || \
24659 ((INSTANCE) == UART8) || \
24660 ((INSTANCE) == UART9) || \
24661 ((INSTANCE) == USART10))
24662
24663/********************* USART Instances : Smard card mode **********************/
24664#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
24665 ((INSTANCE) == USART2) || \
24666 ((INSTANCE) == USART3) || \
24667 ((INSTANCE) == USART6) ||\
24668 ((INSTANCE) == USART10))
24669
24670/****************************** LPUART Instance *******************************/
24671#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
24672
24673/****************************** IWDG Instances ********************************/
24674#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1)
24675/****************************** USB Instances ********************************/
24676#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
24677
24678/****************************** WWDG Instances ********************************/
24679#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1)
24680/****************************** MDIOS Instances ********************************/
24681#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
24682
24683/****************************** CEC Instances *********************************/
24684#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
24685
24686/****************************** SAI Instances ********************************/
24687#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
24688 ((INSTANCE) == SAI1_Block_B) || \
24689 ((INSTANCE) == SAI4_Block_A) || \
24690 ((INSTANCE) == SAI4_Block_B))
24691
24692/****************************** SPDIFRX Instances ********************************/
24693#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
24694
24695/****************************** OPAMP Instances *******************************/
24696#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
24697 ((INSTANCE) == OPAMP2))
24698
24699#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
24700
24701/*********************** USB OTG PCD Instances ********************************/
24702#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)
24703
24704/*********************** USB OTG HCD Instances ********************************/
24705#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)
24706
24707/******************************************************************************/
24708/* For a painless codes migration between the STM32H7xx device product */
24709/* lines, or with STM32F7xx devices the aliases defined below are put */
24710/* in place to overcome the differences in the interrupt handlers and IRQn */
24711/* definitions. No need to update developed interrupt code when moving */
24712/* across product lines within the same STM32H7 Family */
24713/******************************************************************************/
24714
24715/* Aliases for __IRQn */
24716#define RNG_IRQn HASH_RNG_IRQn
24717#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
24718#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
24719#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
24720#define PVD_IRQn PVD_AVD_IRQn
24721
24722
24723/* Aliases for DCMI/PSSI __IRQn */
24724#define DCMI_IRQn DCMI_PSSI_IRQn
24725
24726/* Aliases for __IRQHandler */
24727#define RNG_IRQHandler HASH_RNG_IRQHandler
24728#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
24729#define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
24730#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
24731#define PVD_IRQHandler PVD_AVD_IRQHandler
24732
24733/* Aliases for COMP __IRQHandler */
24734#define COMP_IRQHandler COMP1_IRQHandler
24735
24748#ifdef __cplusplus
24749}
24750#endif /* __cplusplus */
24751
24752#endif /* STM32H730xx_H */
24753
__IO
#define __IO
Definition: core_cm4.h:239
__I
#define __I
Definition: core_cm4.h:236
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h730xx.h:49
CRS_IRQn
@ CRS_IRQn
Definition: stm32h730xx.h:183
FMAC_IRQn
@ FMAC_IRQn
Definition: stm32h730xx.h:191
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32h730xx.h:58
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition: stm32h730xx.h:122
TIM24_IRQn
@ TIM24_IRQn
Definition: stm32h730xx.h:200
FDCAN3_IT1_IRQn
@ FDCAN3_IT1_IRQn
Definition: stm32h730xx.h:198
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32h730xx.h:69
MDIOS_IRQn
@ MDIOS_IRQn
Definition: stm32h730xx.h:163
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition: stm32h730xx.h:74
I2C5_EV_IRQn
@ I2C5_EV_IRQn
Definition: stm32h730xx.h:195
BDMA_Channel7_IRQn
@ BDMA_Channel7_IRQn
Definition: stm32h730xx.h:176
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32h730xx.h:64
SPDIF_RX_IRQn
@ SPDIF_RX_IRQn
Definition: stm32h730xx.h:152
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition: stm32h730xx.h:131
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition: stm32h730xx.h:116
BDMA_Channel3_IRQn
@ BDMA_Channel3_IRQn
Definition: stm32h730xx.h:172
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition: stm32h730xx.h:125
LPTIM3_IRQn
@ LPTIM3_IRQn
Definition: stm32h730xx.h:179
LPTIM4_IRQn
@ LPTIM4_IRQn
Definition: stm32h730xx.h:180
TIM15_IRQn
@ TIM15_IRQn
Definition: stm32h730xx.h:159
BDMA_Channel1_IRQn
@ BDMA_Channel1_IRQn
Definition: stm32h730xx.h:170
DTS_IRQn
@ DTS_IRQn
Definition: stm32h730xx.h:186
UART7_IRQn
@ UART7_IRQn
Definition: stm32h730xx.h:138
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32h730xx.h:93
UART9_IRQn
@ UART9_IRQn
Definition: stm32h730xx.h:193
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32h730xx.h:94
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32h730xx.h:53
TIM17_IRQn
@ TIM17_IRQn
Definition: stm32h730xx.h:161
SAI1_IRQn
@ SAI1_IRQn
Definition: stm32h730xx.h:143
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32h730xx.h:91
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32h730xx.h:89
LTDC_ER_IRQn
@ LTDC_ER_IRQn
Definition: stm32h730xx.h:145
DCMI_PSSI_IRQn
@ DCMI_PSSI_IRQn
Definition: stm32h730xx.h:134
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition: stm32h730xx.h:126
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition: stm32h730xx.h:103
FDCAN1_IT0_IRQn
@ FDCAN1_IT0_IRQn
Definition: stm32h730xx.h:80
USART2_IRQn
@ USART2_IRQn
Definition: stm32h730xx.h:99
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition: stm32h730xx.h:119
BDMA_Channel4_IRQn
@ BDMA_Channel4_IRQn
Definition: stm32h730xx.h:173
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32h730xx.h:56
ADC_IRQn
@ ADC_IRQn
Definition: stm32h730xx.h:79
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32h730xx.h:111
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32h730xx.h:97
TIM1_BRK_IRQn
@ TIM1_BRK_IRQn
Definition: stm32h730xx.h:85
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32h730xx.h:115
UART8_IRQn
@ UART8_IRQn
Definition: stm32h730xx.h:139
FDCAN2_IT0_IRQn
@ FDCAN2_IT0_IRQn
Definition: stm32h730xx.h:81
RCC_IRQn
@ RCC_IRQn
Definition: stm32h730xx.h:66
ADC3_IRQn
@ ADC3_IRQn
Definition: stm32h730xx.h:167
LPTIM2_IRQn
@ LPTIM2_IRQn
Definition: stm32h730xx.h:178
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32h730xx.h:114
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition: stm32h730xx.h:130
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32h730xx.h:95
DFSDM1_FLT0_IRQn
@ DFSDM1_FLT0_IRQn
Definition: stm32h730xx.h:154
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32h730xx.h:106
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32h730xx.h:55
DMAMUX2_OVR_IRQn
@ DMAMUX2_OVR_IRQn
Definition: stm32h730xx.h:168
I2C4_ER_IRQn
@ I2C4_ER_IRQn
Definition: stm32h730xx.h:151
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32h730xx.h:59
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32h730xx.h:129
SAI4_IRQn
@ SAI4_IRQn
Definition: stm32h730xx.h:185
CRYP_IRQn
@ CRYP_IRQn
Definition: stm32h730xx.h:135
DFSDM1_FLT3_IRQn
@ DFSDM1_FLT3_IRQn
Definition: stm32h730xx.h:157
TIM1_UP_IRQn
@ TIM1_UP_IRQn
Definition: stm32h730xx.h:86
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32h730xx.h:128
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32h730xx.h:54
HASH_RNG_IRQn
@ HASH_RNG_IRQn
Definition: stm32h730xx.h:136
DMAMUX1_OVR_IRQn
@ DMAMUX1_OVR_IRQn
Definition: stm32h730xx.h:153
CEC_IRQn
@ CEC_IRQn
Definition: stm32h730xx.h:149
LPTIM5_IRQn
@ LPTIM5_IRQn
Definition: stm32h730xx.h:181
SPI5_IRQn
@ SPI5_IRQn
Definition: stm32h730xx.h:141
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32h730xx.h:57
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32h730xx.h:65
SWPMI1_IRQn
@ SWPMI1_IRQn
Definition: stm32h730xx.h:158
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition: stm32h730xx.h:124
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32h730xx.h:61
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32h730xx.h:92
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32h730xx.h:90
OTFDEC2_IRQn
@ OTFDEC2_IRQn
Definition: stm32h730xx.h:190
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition: stm32h730xx.h:117
OCTOSPI1_IRQn
@ OCTOSPI1_IRQn
Definition: stm32h730xx.h:147
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition: stm32h730xx.h:132
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition: stm32h730xx.h:109
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition: stm32h730xx.h:72
I2C5_ER_IRQn
@ I2C5_ER_IRQn
Definition: stm32h730xx.h:196
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32h730xx.h:101
SPI4_IRQn
@ SPI4_IRQn
Definition: stm32h730xx.h:140
OCTOSPI2_IRQn
@ OCTOSPI2_IRQn
Definition: stm32h730xx.h:188
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32h730xx.h:84
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition: stm32h730xx.h:73
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition: stm32h730xx.h:148
SPI6_IRQn
@ SPI6_IRQn
Definition: stm32h730xx.h:142
FPU_IRQn
@ FPU_IRQn
Definition: stm32h730xx.h:137
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition: stm32h730xx.h:104
USART6_IRQn
@ USART6_IRQn
Definition: stm32h730xx.h:127
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32h730xx.h:96
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition: stm32h730xx.h:133
OTFDEC1_IRQn
@ OTFDEC1_IRQn
Definition: stm32h730xx.h:189
HSEM1_IRQn
@ HSEM1_IRQn
Definition: stm32h730xx.h:166
DFSDM1_FLT2_IRQn
@ DFSDM1_FLT2_IRQn
Definition: stm32h730xx.h:156
HardFault_IRQn
@ HardFault_IRQn
Definition: stm32h730xx.h:52
BDMA_Channel6_IRQn
@ BDMA_Channel6_IRQn
Definition: stm32h730xx.h:175
FMC_IRQn
@ FMC_IRQn
Definition: stm32h730xx.h:108
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32h730xx.h:67
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32h730xx.h:71
USART10_IRQn
@ USART10_IRQn
Definition: stm32h730xx.h:194
FDCAN_CAL_IRQn
@ FDCAN_CAL_IRQn
Definition: stm32h730xx.h:123
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition: stm32h730xx.h:118
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32h730xx.h:63
TIM1_TRG_COM_IRQn
@ TIM1_TRG_COM_IRQn
Definition: stm32h730xx.h:87
UART5_IRQn
@ UART5_IRQn
Definition: stm32h730xx.h:113
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition: stm32h730xx.h:77
DMA2D_IRQn
@ DMA2D_IRQn
Definition: stm32h730xx.h:146
WAKEUP_PIN_IRQn
@ WAKEUP_PIN_IRQn
Definition: stm32h730xx.h:187
I2C4_EV_IRQn
@ I2C4_EV_IRQn
Definition: stm32h730xx.h:150
ECC_IRQn
@ ECC_IRQn
Definition: stm32h730xx.h:184
BDMA_Channel5_IRQn
@ BDMA_Channel5_IRQn
Definition: stm32h730xx.h:174
ETH_IRQn
@ ETH_IRQn
Definition: stm32h730xx.h:121
MDIOS_WKUP_IRQn
@ MDIOS_WKUP_IRQn
Definition: stm32h730xx.h:162
USART1_IRQn
@ USART1_IRQn
Definition: stm32h730xx.h:98
PVD_AVD_IRQn
@ PVD_AVD_IRQn
Definition: stm32h730xx.h:62
COMP_IRQn
@ COMP_IRQn
Definition: stm32h730xx.h:177
MDMA_IRQn
@ MDMA_IRQn
Definition: stm32h730xx.h:164
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32h730xx.h:70
BDMA_Channel0_IRQn
@ BDMA_Channel0_IRQn
Definition: stm32h730xx.h:169
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32h730xx.h:51
UART4_IRQn
@ UART4_IRQn
Definition: stm32h730xx.h:112
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition: stm32h730xx.h:105
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32h730xx.h:68
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition: stm32h730xx.h:120
FDCAN3_IT0_IRQn
@ FDCAN3_IT0_IRQn
Definition: stm32h730xx.h:197
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32h730xx.h:110
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition: stm32h730xx.h:107
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition: stm32h730xx.h:76
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition: stm32h730xx.h:78
TIM23_IRQn
@ TIM23_IRQn
Definition: stm32h730xx.h:199
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32h730xx.h:88
LTDC_IRQn
@ LTDC_IRQn
Definition: stm32h730xx.h:144
FDCAN1_IT1_IRQn
@ FDCAN1_IT1_IRQn
Definition: stm32h730xx.h:82
LPUART1_IRQn
@ LPUART1_IRQn
Definition: stm32h730xx.h:182
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition: stm32h730xx.h:75
SDMMC2_IRQn
@ SDMMC2_IRQn
Definition: stm32h730xx.h:165
CORDIC_IRQn
@ CORDIC_IRQn
Definition: stm32h730xx.h:192
BDMA_Channel2_IRQn
@ BDMA_Channel2_IRQn
Definition: stm32h730xx.h:171
USART3_IRQn
@ USART3_IRQn
Definition: stm32h730xx.h:100
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32h730xx.h:102
DFSDM1_FLT1_IRQn
@ DFSDM1_FLT1_IRQn
Definition: stm32h730xx.h:155
FDCAN2_IT1_IRQn
@ FDCAN2_IT1_IRQn
Definition: stm32h730xx.h:83
TIM16_IRQn
@ TIM16_IRQn
Definition: stm32h730xx.h:160
MCR
#define MCR
Modem Control Register.
Definition: uart.h:91
AFR
#define AFR
Alternate Function register.
Definition: uart.h:99
ADC_Common_TypeDef
Definition: stm32h723xx.h:289
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32h723xx.h:242
BDMA_Channel_TypeDef
Definition: stm32h723xx.h:619
BDMA_TypeDef
Definition: stm32h723xx.h:628
CEC_TypeDef
Consumer Electronics Control.
Definition: stm32h723xx.h:418
COMPOPT_TypeDef
Comparator.
Definition: stm32h723xx.h:1576
COMP_Common_TypeDef
Definition: stm32h723xx.h:1588
COMP_TypeDef
Definition: stm32h723xx.h:1583
CORDIC_TypeDef
COordincate Rotation DIgital Computer.
Definition: stm32h723xx.h:431
CRC_TypeDef
CRC calculation unit.
Definition: stm32h723xx.h:442
CRS_TypeDef
Clock Recovery System.
Definition: stm32h723xx.h:456
CRYP_TypeDef
Crypto Processor.
Definition: stm32h730xx.h:1670
CRYP_TypeDef::CSGCM3R
__IO uint32_t CSGCM3R
Definition: stm32h730xx.h:1702
CRYP_TypeDef::RISR
__IO uint32_t RISR
Definition: stm32h730xx.h:1677
CRYP_TypeDef::CSGCM5R
__IO uint32_t CSGCM5R
Definition: stm32h730xx.h:1704
CRYP_TypeDef::DOUT
__IO uint32_t DOUT
Definition: stm32h730xx.h:1674
CRYP_TypeDef::K3RR
__IO uint32_t K3RR
Definition: stm32h730xx.h:1686
CRYP_TypeDef::SR
__IO uint32_t SR
Definition: stm32h730xx.h:1672
CRYP_TypeDef::CSGCMCCM7R
__IO uint32_t CSGCMCCM7R
Definition: stm32h730xx.h:1698
CRYP_TypeDef::K0RR
__IO uint32_t K0RR
Definition: stm32h730xx.h:1680
CRYP_TypeDef::CSGCMCCM6R
__IO uint32_t CSGCMCCM6R
Definition: stm32h730xx.h:1697
CRYP_TypeDef::DIN
__IO uint32_t DIN
Definition: stm32h730xx.h:1673
CRYP_TypeDef::K3LR
__IO uint32_t K3LR
Definition: stm32h730xx.h:1685
CRYP_TypeDef::CSGCM2R
__IO uint32_t CSGCM2R
Definition: stm32h730xx.h:1701
CRYP_TypeDef::IV0LR
__IO uint32_t IV0LR
Definition: stm32h730xx.h:1687
CRYP_TypeDef::IMSCR
__IO uint32_t IMSCR
Definition: stm32h730xx.h:1676
CRYP_TypeDef::CSGCMCCM1R
__IO uint32_t CSGCMCCM1R
Definition: stm32h730xx.h:1692
CRYP_TypeDef::K1RR
__IO uint32_t K1RR
Definition: stm32h730xx.h:1682
CRYP_TypeDef::CSGCMCCM3R
__IO uint32_t CSGCMCCM3R
Definition: stm32h730xx.h:1694
CRYP_TypeDef::IV0RR
__IO uint32_t IV0RR
Definition: stm32h730xx.h:1688
CRYP_TypeDef::CSGCMCCM5R
__IO uint32_t CSGCMCCM5R
Definition: stm32h730xx.h:1696
CRYP_TypeDef::CR
__IO uint32_t CR
Definition: stm32h730xx.h:1671
CRYP_TypeDef::CSGCM1R
__IO uint32_t CSGCM1R
Definition: stm32h730xx.h:1700
CRYP_TypeDef::K1LR
__IO uint32_t K1LR
Definition: stm32h730xx.h:1681
CRYP_TypeDef::IV1LR
__IO uint32_t IV1LR
Definition: stm32h730xx.h:1689
CRYP_TypeDef::CSGCMCCM0R
__IO uint32_t CSGCMCCM0R
Definition: stm32h730xx.h:1691
CRYP_TypeDef::K2RR
__IO uint32_t K2RR
Definition: stm32h730xx.h:1684
CRYP_TypeDef::K0LR
__IO uint32_t K0LR
Definition: stm32h730xx.h:1679
CRYP_TypeDef::K2LR
__IO uint32_t K2LR
Definition: stm32h730xx.h:1683
CRYP_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32h730xx.h:1678
CRYP_TypeDef::CSGCM4R
__IO uint32_t CSGCM4R
Definition: stm32h730xx.h:1703
CRYP_TypeDef::CSGCM0R
__IO uint32_t CSGCM0R
Definition: stm32h730xx.h:1699
CRYP_TypeDef::IV1RR
__IO uint32_t IV1RR
Definition: stm32h730xx.h:1690
CRYP_TypeDef::DMACR
__IO uint32_t DMACR
Definition: stm32h730xx.h:1675
CRYP_TypeDef::CSGCMCCM2R
__IO uint32_t CSGCMCCM2R
Definition: stm32h730xx.h:1693
CRYP_TypeDef::CSGCM7R
__IO uint32_t CSGCM7R
Definition: stm32h730xx.h:1706
CRYP_TypeDef::CSGCMCCM4R
__IO uint32_t CSGCMCCM4R
Definition: stm32h730xx.h:1695
CRYP_TypeDef::CSGCM6R
__IO uint32_t CSGCM6R
Definition: stm32h730xx.h:1705
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32h723xx.h:469
DBGMCU_TypeDef
Debug MCU.
Definition: stm32h723xx.h:531
DCMI_TypeDef
DCMI.
Definition: stm32h723xx.h:561
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32h723xx.h:518
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32h723xx.h:496
DLYB_TypeDef
Delay Block DLYB.
Definition: stm32h723xx.h:1443
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32h723xx.h:686
DMAMUX_ChannelStatus_TypeDef
Definition: stm32h723xx.h:639
DMAMUX_Channel_TypeDef
Definition: stm32h723xx.h:634
DMAMUX_RequestGenStatus_TypeDef
Definition: stm32h723xx.h:650
DMAMUX_RequestGen_TypeDef
Definition: stm32h723xx.h:645
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32h723xx.h:601
DMA_TypeDef
Definition: stm32h723xx.h:611
DTS_TypeDef
DTS.
Definition: stm32h723xx.h:1504
ETH_TypeDef
Ethernet MAC.
Definition: stm32h723xx.h:717
EXTI_Core_TypeDef
This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx,...
Definition: stm32h723xx.h:936
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32h723xx.h:891
FDCAN_ClockCalibrationUnit_TypeDef
FD Controller Area Network.
Definition: stm32h723xx.h:403
FDCAN_GlobalTypeDef
FD Controller Area Network.
Definition: stm32h723xx.h:315
FLASH_TypeDef
FLASH Registers.
Definition: stm32h723xx.h:956
FMAC_TypeDef
Filter and Mathematical ACcelerator.
Definition: stm32h723xx.h:990
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32h723xx.h:1015
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32h723xx.h:1006
FMC_Bank2_TypeDef
Flexible Memory Controller Bank2.
Definition: stm32h723xx.h:1024
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32h723xx.h:1038
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5 and 6.
Definition: stm32h723xx.h:1053
GPIO_TypeDef
General Purpose I/O.
Definition: stm32h723xx.h:1066
GPV_TypeDef
Global Programmer View.
Definition: stm32h723xx.h:1966
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition: stm32h730xx.h:1730
HASH_TypeDef
HASH.
Definition: stm32h730xx.h:1714
HASH_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32h730xx.h:1719
HASH_TypeDef::STR
__IO uint32_t STR
Definition: stm32h730xx.h:1717
HASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32h730xx.h:1720
HASH_TypeDef::DIN
__IO uint32_t DIN
Definition: stm32h730xx.h:1716
HASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32h730xx.h:1715
HSEM_Common_TypeDef
Definition: stm32h723xx.h:1467
HSEM_TypeDef
HW Semaphore HSEM.
Definition: stm32h723xx.h:1453
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32h723xx.h:1133
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32h723xx.h:1152
LPTIM_TypeDef
LPTIMIMER.
Definition: stm32h723xx.h:1559
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32h723xx.h:1191
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32h723xx.h:1166
MDIOS_TypeDef
MDIOS.
Definition: stm32h723xx.h:1681
MDMA_Channel_TypeDef
Definition: stm32h723xx.h:664
MDMA_TypeDef
MDMA Controller.
Definition: stm32h723xx.h:659
OCTOSPIM_TypeDef
OCTO Serial Peripheral Interface IO Manager.
Definition: stm32h723xx.h:1952
OCTOSPI_TypeDef
OCTO Serial Peripheral Interface.
Definition: stm32h723xx.h:1887
OPAMP_TypeDef
Operational Amplifier (OPAMP)
Definition: stm32h723xx.h:1083
OTFDEC_Region_TypeDef
OTFD register.
Definition: stm32h730xx.h:2037
OTFDEC_TypeDef
Definition: stm32h730xx.h:2050
PSSI_TypeDef
PSSI.
Definition: stm32h723xx.h:580
PWR_TypeDef
Power Control.
Definition: stm32h723xx.h:1214
RAMECC_MonitorTypeDef
RAM_ECC_Specific_Registers.
Definition: stm32h723xx.h:1644
RAMECC_TypeDef
Definition: stm32h723xx.h:1654
RCC_TypeDef
Reset and Clock Control.
Definition: stm32h723xx.h:1233
RNG_TypeDef
RNG.
Definition: stm32h723xx.h:1668
RTC_TypeDef
Real-Time Clock.
Definition: stm32h723xx.h:1307
SAI_Block_TypeDef
Definition: stm32h723xx.h:1375
SAI_TypeDef
Serial Audio Interface.
Definition: stm32h723xx.h:1367
SDMMC_TypeDef
Secure digital input/output Interface.
Definition: stm32h723xx.h:1408
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition: stm32h723xx.h:1391
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32h723xx.h:1479
SWPMI_TypeDef
Single Wire Protocol Master Interface SPWMI.
Definition: stm32h723xx.h:1615
SYSCFG_TypeDef
System configuration controller.
Definition: stm32h723xx.h:1094
TIM_TypeDef
TIM.
Definition: stm32h723xx.h:1525
TTCAN_TypeDef
TTFD Controller Area Network.
Definition: stm32h723xx.h:376
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32h723xx.h:1596
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32h723xx.h:1796
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32h723xx.h:1761
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32h723xx.h:1869
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32h723xx.h:1855
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32h723xx.h:1824
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32h723xx.h:1840
VREFBUF_TypeDef
VREFBUF.
Definition: stm32h723xx.h:304
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32h723xx.h:1633
_pr
Definition: hexdump.h:39
system_stm32h7xx.h
CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
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