RTEMS 6.1-rc2
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sparc64.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
13/*
14 * COPYRIGHT (c) 1989-1999. On-Line Applications Research Corporation (OAR).
15 *
16 * This file is based on the SPARC sparc.h file. Modifications are made
17 * to support the SPARC64 processor.
18 * COPYRIGHT (c) 2010. Gedare Bloom.
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 * 1. Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
33 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef _RTEMS_SCORE_SPARC_H
43#define _RTEMS_SCORE_SPARC_H
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49/*
50 * This file contains the information required to build
51 * RTEMS for a particular member of the "sparc" family. It does
52 * this by setting variables to indicate which implementation
53 * dependent features are present in a particular member
54 * of the family.
55 *
56 * Currently recognized feature flags:
57 *
58 * + SPARC_HAS_FPU
59 * 0 - no HW FPU
60 * 1 - has HW FPU (assumed to be compatible w/90C602)
61 *
62 * + SPARC_HAS_BITSCAN
63 * 0 - does not have scan instructions
64 * 1 - has scan instruction (not currently implemented)
65 *
66 * + SPARC_NUMBER_OF_REGISTER_WINDOWS
67 * 8 is the most common number supported by SPARC implementations.
68 * SPARC_PSR_CWP_MASK is derived from this value.
69 */
70
71/*
72 * Some higher end SPARCs have a bitscan instructions. It would
73 * be nice to take advantage of them. Right now, there is no
74 * port to a CPU model with this feature and no (untested) code
75 * that is based on this feature flag.
76 */
77
78#define SPARC_HAS_BITSCAN 0
79
80/*
81 * This should be OK until a port to a higher end SPARC processor
82 * is made that has more than 8 register windows. If this cannot
83 * be determined based on multilib settings (v7/v8/v9), then the
84 * cpu_asm.S code that depends on this will have to move to libcpu.
85 *
86 * SPARC v9 supports from 3 to 32 register windows.
87 * N_REG_WINDOWS = 8 on UltraSPARC T1 (impl. dep. #2-V8).
88 */
89
90#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
91
92/*
93 * This should be determined based on some soft float derived
94 * cpp predefine but gcc does not currently give us that information.
95 */
96
97
98#if defined(_SOFT_FLOAT)
99#define SPARC_HAS_FPU 0
100#else
101#define SPARC_HAS_FPU 1
102#endif
103
104#if SPARC_HAS_FPU
105#define CPU_MODEL_NAME "w/FPU"
106#else
107#define CPU_MODEL_NAME "w/soft-float"
108#endif
109
110/*
111 * Define the name of the CPU family.
112 */
113
114#define CPU_NAME "SPARC"
115
116/*
117 * Miscellaneous constants
118 */
119
120/*
121 * The PSR is deprecated and deleted.
122 *
123 * The following registers represent fields of the PSR:
124 * PIL - Processor Interrupt Level register
125 * CWP - Current Window Pointer register
126 * VER - Version register
127 * CCR - Condition Codes Register
128 * PSTATE - Processor State register
129 */
130
131/*
132 * PSTATE masks and starting bit positions
133 *
134 * NOTE: Reserved bits are ignored.
135 */
136
137#define SPARC_PSTATE_AG_MASK 0x00000001 /* bit 0 */
138#define SPARC_PSTATE_IE_MASK 0x00000002 /* bit 1 */
139#define SPARC_PSTATE_PRIV_MASK 0x00000004 /* bit 2 */
140#define SPARC_PSTATE_AM_MASK 0x00000008 /* bit 3 */
141#define SPARC_PSTATE_PEF_MASK 0x00000010 /* bit 4 */
142#define SPARC_PSTATE_MM_MASK 0x00000040 /* bit 6 */
143#define SPARC_PSTATE_TLE_MASK 0x00000100 /* bit 8 */
144#define SPARC_PSTATE_CLE_MASK 0x00000200 /* bit 9 */
145
146#define SPARC_PSTATE_AG_BIT_POSITION 0 /* bit 0 */
147#define SPARC_PSTATE_IE_BIT_POSITION 1 /* bit 1 */
148#define SPARC_PSTATE_PRIV_BIT_POSITION 2 /* bit 2 */
149#define SPARC_PSTATE_AM_BIT_POSITION 3 /* bit 3 */
150#define SPARC_PSTATE_PEF_BIT_POSITION 4 /* bit 4 */
151#define SPARC_PSTATE_MM_BIT_POSITION 6 /* bit 6 */
152#define SPARC_PSTATE_TLE_BIT_POSITION 8 /* bit 8 */
153#define SPARC_PSTATE_CLE_BIT_POSITION 9 /* bit 9 */
154
155#define SPARC_FPRS_FEF_MASK 0x0100 /* bit 2 */
156#define SPARC_FPRS_FEF_BIT_POSITION 2 /* bit 2 */
157
158#define SPARC_TSTATE_IE_MASK 0x00000200 /* bit 9 */
159
160#define SPARC_SOFTINT_TM_MASK 0x00000001 /* bit 0 */
161#define SPARC_SOFTINT_SM_MASK 0x00010000 /* bit 16 */
162#define SPARC_SOFTINT_TM_BIT_POSITION 1 /* bit 0 */
163#define SPARC_SOFTINT_SM_BIT_POSITION 17 /* bit 16 */
164
165#define STACK_BIAS (2047)
166
167#ifdef ASM
168
169/*
170 * To enable the FPU we need to set both PSTATE.pef and FPRS.fef
171 */
172
173#define sparc64_enable_FPU(rtmp1) \
174 rdpr %pstate, rtmp1; \
175 or rtmp1, SPARC_PSTATE_PEF_MASK, rtmp1; \
176 wrpr %g0, rtmp1, %pstate; \
177 rd %fprs, rtmp1; \
178 or rtmp1, SPARC_FPRS_FEF_MASK, rtmp1; \
179 wr %g0, rtmp1, %fprs
180
181
182#endif
183
184#ifndef ASM
185
186/*
187 * Standard nop
188 */
189
190#define nop() \
191 do { \
192 __asm__ volatile ( "nop" ); \
193 } while ( 0 )
194
195/*
196 * Get and set the pstate
197 */
198
199#define sparc64_get_pstate( _pstate ) \
200 do { \
201 (_pstate) = 0; \
202 __asm__ volatile( "rdpr %%pstate, %0" : "=r" (_pstate) : "0" (_pstate) ); \
203 } while ( 0 )
204
205#define sparc64_set_pstate( _pstate ) \
206 do { \
207 __asm__ volatile ( \
208 "wrpr %%g0, %0, %%pstate " : "=r" ((_pstate)) : "0" ((_pstate)) ); \
209 } while ( 0 )
210
211/*
212 * Get and set the PIL
213 */
214
215#define sparc64_get_pil( _pil ) \
216 do { \
217 (_pil) = 0; \
218 __asm__ volatile( "rdpr %%pil, %0" : "=r" (_pil) : "0" (_pil) ); \
219 } while ( 0 )
220
221#define sparc64_set_pil( _pil ) \
222 do { \
223 __asm__ volatile ( "wrpr %%g0, %0, %%pil " : "=r" ((_pil)) : "0" ((_pil)) ); \
224 } while ( 0 )
225
226
227/*
228 * Get and set the TBA
229 */
230
231#define sparc64_get_tba( _tba ) \
232 do { \
233 (_tba) = 0; /* to avoid unitialized warnings */ \
234 __asm__ volatile( "rdpr %%tba, %0" : "=r" (_tba) : "0" (_tba) ); \
235 } while ( 0 )
236
237#define sparc64_set_tba( _tba ) \
238 do { \
239 __asm__ volatile( "wrpr %%g0, %0, %%tba" : "=r" (_tba) : "0" (_tba) ); \
240 } while ( 0 )
241
242/*
243 * Get and set the TL (trap level)
244 */
245
246#define sparc64_get_tl( _tl ) \
247 do { \
248 (_tl) = 0; /* to avoid unitialized warnings */ \
249 __asm__ volatile( "rdpr %%tl, %0" : "=r" (_tl) : "0" (_tl) ); \
250 } while ( 0 )
251
252#define sparc64_set_tl( _tl ) \
253 do { \
254 __asm__ volatile( "wrpr %%g0, %0, %%tl" : "=r" (_tl) : "0" (_tl) ); \
255 } while ( 0 )
256
257
258/*
259 * read the stick register
260 *
261 * Note:
262 * stick asr=24, mnemonic=stick
263 * Note: stick does not appear to be a valid ASR for US3, although it is
264 * implemented in US3i.
265 */
266#define sparc64_read_stick( _stick ) \
267 do { \
268 (_stick) = 0; \
269 __asm__ volatile( "rd %%stick, %0" : "=r" (_stick) : "0" (_stick) ); \
270 } while ( 0 )
271
272/*
273 * write the stick_cmpr register
274 *
275 * Note:
276 * stick_cmpr asr=25, mnemonic=stick_cmpr
277 * Note: stick_cmpr does not appear to be a valid ASR for US3, although it is
278 * implemented in US3i.
279 */
280#define sparc64_write_stick_cmpr( _stick_cmpr ) \
281 do { \
282 __asm__ volatile( "wr %%g0, %0, %%stick_cmpr" : "=r" (_stick_cmpr) \
283 : "0" (_stick_cmpr) ); \
284 } while ( 0 )
285
286/*
287 * read the Tick register
288 */
289#define sparc64_read_tick( _tick ) \
290 do { \
291 (_tick) = 0; \
292 __asm__ volatile( "rd %%tick, %0" : "=r" (_tick) : "0" (_tick) ); \
293 } while ( 0 )
294
295/*
296 * write the tick_cmpr register
297 */
298#define sparc64_write_tick_cmpr( _tick_cmpr ) \
299 do { \
300 __asm__ volatile( "wr %%g0, %0, %%tick_cmpr" : "=r" (_tick_cmpr) \
301 : "0" (_tick_cmpr) ); \
302 } while ( 0 )
303
304/*
305 * Clear the softint register.
306 *
307 * sun4u and sun4v: softint_clr asr = 21, with mnemonic clear_softint
308 */
309#define sparc64_clear_interrupt_bits( _bit_mask ) \
310 do { \
311 __asm__ volatile( "wr %%g0, %0, %%clear_softint" : "=r" (_bit_mask) \
312 : "0" (_bit_mask)); \
313 } while ( 0 )
314
315/************* DEPRECATED ****************/
316/* Note: Although the y register is deprecated, gcc still uses it */
317/*
318 * Get and set the Y
319 */
320
321#define sparc_get_y( _y ) \
322 do { \
323 __asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \
324 } while ( 0 )
325
326#define sparc_set_y( _y ) \
327 do { \
328 __asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \
329 } while ( 0 )
330
331/************* /DEPRECATED ****************/
332
333/*
334 * Manipulate the interrupt level in the pstate
335 */
336
337uint32_t sparc_disable_interrupts(void);
338void sparc_enable_interrupts(uint32_t);
339
340#define sparc_flash_interrupts( _level ) \
341 do { \
342 uint32_t _ignored; \
343 \
344 sparc_enable_interrupts( (_level) ); \
345 _ignored = sparc_disable_interrupts(); \
346 (void) _ignored; \
347 } while ( 0 )
348
349#define sparc64_get_interrupt_level( _level ) \
350 do { \
351 _level = 0; \
352 sparc64_get_pil( _level ); \
353 } while ( 0 )
354
355#endif /* !ASM */
356
357#ifdef __cplusplus
358}
359#endif
360
361#endif /* _RTEMS_SCORE_SPARC_H */