RTEMS 6.1-rc2
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sdramc.h
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1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
36// ---------------------------------------------------------------------------
37// SDRAM
38// ---------------------------------------------------------------------------
40#define EBI_SDRAMC_ADDR (0x70000000u)
41
43#define BOARD_SDRAM_BUSWIDTH 16
44
45
46typedef struct _SSdramc_config {
47 uint32_t dwColumnBits; // Number of Column Bits
48 uint32_t dwRowBits; // Number of Row Bits
49 uint32_t dwBanks; // Number of Banks
50 uint32_t dwCAS; // CAS Latency
51 uint32_t dwDataBusWidth; // Data Bus Width
52 uint32_t dwWriteRecoveryDelay; // Write Recovery Delay
53 uint32_t dwRowCycleDelay_RowRefreshCycle; // Row Cycle Delay and Row Refresh Cycle
54 uint32_t dwRowPrechargeDelay; // Row Precharge Delay
55 uint32_t dwRowColumnDelay; // Row to Column Delay
56 uint32_t dwActivePrechargeDelay; // Active to Precharge Delay
57 uint32_t dwExitSelfRefreshActiveDelay; // Exit Self Refresh to Active Delay
58 uint32_t dwBK1; // bk1 addr
59
61
62typedef struct _SSdramc_Memory {
64
66
67extern void SDRAMC_Configure(SSdramc_Memory *pMemory,
68 uint32_t dwClockFrequency);
void SDRAMC_Configure(SSdramc_Memory *pMemory, uint32_t dwClockFrequency)
Configure and initialize the SDRAM controller.
Definition: sdramc.c:106
Definition: sdramc.h:62
Definition: sdramc.h:46