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RTEMS 6.1-rc2
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20#define OMAP3_DM37XX_INTR_BASE 0x48200000
23#define OMAP3_AM335X_INTR_BASE 0x48200000
26#define OMAP3_INTCPS_REVISION 0x000
27#define OMAP3_INTCPS_SYSCONFIG 0x010
28#define OMAP3_INTCPS_SYSSTATUS 0x014
29#define OMAP3_INTCPS_SIR_IRQ 0x040
30#define OMAP3_INTCPS_SIR_FIQ 0x044
31#define OMAP3_INTCPS_CONTROL 0x048
32#define OMAP3_INTCPS_PROTECTION 0x04C
33#define OMAP3_INTCPS_IDLE 0x050
34#define OMAP3_INTCPS_IRQ_PRIORITY 0x060
35#define OMAP3_INTCPS_FIQ_PRIORITY 0x064
36#define OMAP3_INTCPS_THRESHOLD 0x068
37#define OMAP3_INTCPS_ITR0 0x080
38#define OMAP3_INTCPS_MIR0 0x084
39#define OMAP3_INTCPS_MIR1 0x0A4
40#define OMAP3_INTCPS_MIR2 0x0C4
41#define OMAP3_INTCPS_MIR3 0x0E4
42#define OMAP3_INTCPS_MIR_CLEAR0 0x088
43#define OMAP3_INTCPS_MIR_SET0 0x08C
44#define OMAP3_INTCPS_ISR_SET0 0x090
45#define OMAP3_INTCPS_ISR_CLEAR0 0x094
46#define OMAP3_INTCPS_PENDING_IRQ0 0x098
47#define OMAP3_INTCPS_PENDING_IRQ1 0x0b8
48#define OMAP3_INTCPS_PENDING_IRQ2 0x0d8
49#define OMAP3_INTCPS_PENDING_IRQ3 0x0f8
50#define OMAP3_INTCPS_PENDING_FIQ0 0x09C
51#define OMAP3_INTCPS_ILR0 0x100
54#define OMAP3_SYSCONFIG_AUTOIDLE 0x01
56#define OMAP3_INTR_ITR(base,n) \
57 (base + OMAP3_INTCPS_ITR0 + 0x20 * (n))
58#define OMAP3_INTR_MIR(base,n) \
59 (base + OMAP3_INTCPS_MIR0 + 0x20 * (n))
60#define OMAP3_INTR_MIR_CLEAR(base,n) \
61 (base + OMAP3_INTCPS_MIR_CLEAR0 + 0x20 * (n))
62#define OMAP3_INTR_MIR_SET(base,n) \
63 (base + OMAP3_INTCPS_MIR_SET0 + 0x20 * (n))
64#define OMAP3_INTR_ISR_SET(base,n) \
65 (base + OMAP3_INTCPS_ISR_SET0 + 0x20 * (n))
66#define OMAP3_INTR_ISR_CLEAR(base,n) \
67 (base + OMAP3_INTCPS_ISR_CLEAR0 + 0x20 * (n))
68#define OMAP3_INTR_PENDING_IRQ(base,n) \
69 (base + OMAP3_INTCPS_PENDING_IRQ0 + 0x20 * (n))
70#define OMAP3_INTR_PENDING_FIQ(base,n) \
71 (base + OMAP3_INTCPS_PENDING_FIQ0 + 0x20 * (n))
72#define OMAP3_INTR_ILR(base,m) \
73 (base + OMAP3_INTCPS_ILR0 + 0x4 * (m))
75#define OMAP3_INTR_SPURIOUSIRQ_MASK (0x1FFFFFF << 7)
76#define OMAP3_INTR_ACTIVEIRQ_MASK 0x7F
77#define OMAP3_INTR_NEWIRQAGR 0x1
79#define OMAP3_DM337X_NR_IRQ_VECTORS 96
82#define OMAP3_MCBSP2_ST_IRQ 4
83#define OMAP3_MCBSP3_ST_IRQ 5
84#define OMAP3_SYS_NIRQ 7
85#define OMAP3_SMX_DBG_IRQ 9
86#define OMAP3_SMX_APP_IRQ 10
87#define OMAP3_PRCM_IRQ 11
88#define OMAP3_SDMA0_IRQ 12
89#define OMAP3_SDMA1_IRQ 13
90#define OMAP3_SDMA2_IRQ 14
91#define OMAP3_SDMA3_IRQ 15
92#define OMAP3_MCBSP1_IRQ 16
93#define OMAP3_MCBSP2_IRQ 17
94#define OMAP3_GPMC_IRQ 20
95#define OMAP3_SGX_IRQ 21
96#define OMAP3_MCBSP3_IRQ 22
97#define OMAP3_MCBSP4_IRQ 23
98#define OMAP3_CAM0_IRQ 24
99#define OMAP3_DSS_IRQ 25
100#define OMAP3_MAIL_U0_IRQ 26
101#define OMAP3_MCBSP5_IRQ 27
102#define OMAP3_IVA2_MMU_IRQ 28
103#define OMAP3_GPIO1_IRQ 29
104#define OMAP3_GPIO2_IRQ 30
105#define OMAP3_GPIO3_IRQ 31
106#define OMAP3_GPIO4_IRQ 32
107#define OMAP3_GPIO5_IRQ 33
108#define OMAP3_GPIO6_IRQ 34
109#define OMAP3_WDT3_IRQ 36
110#define OMAP3_GPT1_IRQ 37
111#define OMAP3_GPT2_IRQ 38
112#define OMAP3_GPT3_IRQ 39
113#define OMAP3_GPT4_IRQ 40
114#define OMAP3_GPT5_IRQ 41
115#define OMAP3_GPT6_IRQ 42
116#define OMAP3_GPT7_IRQ 43
117#define OMAP3_GPT8_IRQ 44
118#define OMAP3_GPT9_IRQ 45
119#define OMAP3_GPT10_IRQ 46
120#define OMAP3_GPT11_IRQ 47
121#define OMAP3_SPI4_IRQ 48
122#define OMAP3_MCBSP4_TX_IRQ 54
123#define OMAP3_MCBSP4_RX_IRQ 55
124#define OMAP3_I2C1_IRQ 56
125#define OMAP3_I2C2_IRQ 57
126#define OMAP3_HDQ_IRQ 58
127#define OMAP3_MCBSP1_TX_IRQ 59
128#define OMAP3_MCBSP1_RX_IRQ 60
129#define OMAP3_I2C3_IRQ 61
130#define OMAP3_MCBSP2_TX_IRQ 62
131#define OMAP3_MCBSP2_RX_IRQ 63
132#define OMAP3_SPI1_IRQ 65
133#define OMAP3_SPI2_IRQ 66
134#define OMAP3_UART1_IRQ 72
135#define OMAP3_UART2_IRQ 73
136#define OMAP3_UART3_IRQ 74
137#define OMAP3_PBIAS_IRQ 75
138#define OMAP3_OHCI_IRQ 76
139#define OMAP3_EHCI_IRQ 77
140#define OMAP3_TLL_IRQ 78
141#define OMAP3_MCBSP5_TX_IRQ 81
142#define OMAP3_MCBSP5_RX_IRQ 82
143#define OMAP3_MMC1_IRQ 83
144#define OMAP3_MMC2_IRQ 86
145#define OMAP3_ICR_IRQ 87
146#define OMAP3_D2DFRINT_IRQ 88
147#define OMAP3_MCBSP3_TX_IRQ 89
148#define OMAP3_MCBSP3_RX_IRQ 90
149#define OMAP3_SPI3_IRQ 91
150#define OMAP3_HSUSB_MC_IRQ 92
151#define OMAP3_HSUSB_DMA_IRQ 93
152#define OMAP3_MMC3_IRQ 94
155#define OMAP3_GPTIMER1_BASE 0x48318000
157#define OMAP3_GPTIMER2_BASE 0x49032000
159#define OMAP3_GPTIMER3_BASE 0x49034000
161#define OMAP3_GPTIMER4_BASE 0x49036000
163#define OMAP3_GPTIMER5_BASE 0x49038000
165#define OMAP3_GPTIMER6_BASE 0x4903A000
167#define OMAP3_GPTIMER7_BASE 0x4903C000
169#define OMAP3_GPTIMER8_BASE 0x4903E000
171#define OMAP3_GPTIMER9_BASE 0x49040000
173#define OMAP3_GPTIMER10_BASE 0x48086000
175#define OMAP3_GPTIMER11_BASE 0x48088000
180#define OMAP3_TIMER_TIDR 0x000
182#define OMAP3_TIMER_TIOCP_CFG 0x010
184#define OMAP3_TIMER_TISTAT 0x014
186#define OMAP3_TIMER_TISR 0x018
188#define OMAP3_TIMER_TIER 0x01C
190#define OMAP3_TIMER_TWER 0x020
192#define OMAP3_TIMER_TCLR 0x024
194#define OMAP3_TIMER_TCRR 0x028
196#define OMAP3_TIMER_TLDR 0x02C
198#define OMAP3_TIMER_TTGR 0x030
200#define OMAP3_TIMER_TWPS 0x034
202#define OMAP3_TIMER_TMAR 0x038
204#define OMAP3_TIMER_TCAR1 0x03C
206#define OMAP3_TIMER_TSICR 0x040
208#define OMAP3_TIMER_TCAR2 0x044
210#define OMAP3_TIMER_TPIR 0x048
212#define OMAP3_TIMER_TNIR 0x04C
214#define OMAP3_TIMER_TCVR 0x050
216#define OMAP3_TIMER_TOCR 0x054
218#define OMAP3_TIMER_TOWR 0x058
222#define OMAP3_TISR_MAT_IT_FLAG (1 << 0)
223#define OMAP3_TISR_OVF_IT_FLAG (1 << 1)
224#define OMAP3_TISR_TCAR_IT_FLAG (1 << 2)
227#define OMAP3_TIER_MAT_IT_ENA (1 << 0)
228#define OMAP3_TIER_OVF_IT_ENA (1 << 1)
229#define OMAP3_TIER_TCAR_IT_ENA (1 << 2)
232#define OMAP3_TCLR_ST (1 << 0)
233#define OMAP3_TCLR_AR (1 << 1)
234#define OMAP3_TCLR_PRE (1 << 5)
235#define OMAP3_TCLR_PTV (1 << 1)
236#define OMAP3_TCLR_OVF_TRG (1 << 10)
239#define OMAP3_CM_CLKSEL_GFX 0x48004b40
240#define OMAP3_CM_CLKEN_PLL 0x48004d00
241#define OMAP3_CM_FCLKEN1_CORE 0x48004A00
242#define OMAP3_CM_CLKSEL_CORE 0x48004A40
243#define OMAP3_CM_FCLKEN_PER 0x48005000
244#define OMAP3_CM_CLKSEL_PER 0x48005040
245#define OMAP3_CM_CLKSEL_WKUP 0x48004c40
248#define CM_MODULEMODE_MASK (0x3 << 0)
249#define CM_MODULEMODE_ENABLE (0x2 << 0)
250#define CM_MODULEMODE_DISABLED (0x0 << 0)
252#define CM_CLKCTRL_IDLEST (0x3 << 16)
253#define CM_CLKCTRL_IDLEST_FUNC (0x0 << 16)
254#define CM_CLKCTRL_IDLEST_TRANS (0x1 << 16)
255#define CM_CLKCTRL_IDLEST_IDLE (0x2 << 16)
256#define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16)
258#define CM_WKUP_BASE 0x44E00400
260#define CM_WKUP_TIMER1_CLKCTRL (CM_WKUP_BASE + 0xC4)
263#define CM_PER_BASE 0x44E00000
264#define CM_PER_TIMER7_CLKCTRL (CM_PER_BASE + 0x7C)
269#define CM_DPLL_BASE 0x44E00500
271#define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28)
273#define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0)
274#define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0)
276#define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0)
278#define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0)
280#define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0)
282#define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0)
285#define CLKSEL_TIMER7_CLK (CM_DPLL_BASE + 0x04)
286#define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0)
287#define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0)
288#define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0)
289#define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0)
290#define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0)
293#define CM_RTC_BASE 0x44E00800
294#define CM_RTC_RTC_CLKCTRL 0x0
295#define CM_RTC_CLKSTCTRL 0x4
298#define OMAP3_CLKSEL_GPT1 (1 << 0)
299#define OMAP3_CLKSEL_GPT10 (1 << 6)
300#define OMAP3_CLKSEL_GPT11 (1 << 7)
302#define OMAP34XX_CORE_L4_IO_BASE 0x48000000
304#define ARM_TTBR_ADDR_MASK (0xffffc000)
305#define ARM_TTBR_OUTER_NC (0x0 << 3)
306#define ARM_TTBR_OUTER_WBWA (0x1 << 3)
307#define ARM_TTBR_OUTER_WT (0x2 << 3)
308#define ARM_TTBR_OUTER_WBNWA (0x3 << 3)
309#define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA
313#define CPU_CONTROL_MMU_ENABLE 0x00000001
314#define CPU_CONTROL_AFLT_ENABLE 0x00000002
315#define CPU_CONTROL_DC_ENABLE 0x00000004
316#define CPU_CONTROL_WBUF_ENABLE 0x00000008
317#define CPU_CONTROL_32BP_ENABLE 0x00000010
318#define CPU_CONTROL_32BD_ENABLE 0x00000020
319#define CPU_CONTROL_LABT_ENABLE 0x00000040
320#define CPU_CONTROL_BEND_ENABLE 0x00000080
321#define CPU_CONTROL_SYST_ENABLE 0x00000100
322#define CPU_CONTROL_ROM_ENABLE 0x00000200
323#define CPU_CONTROL_CPCLK 0x00000400
324#define CPU_CONTROL_SWP_ENABLE 0x00000400
325#define CPU_CONTROL_BPRD_ENABLE 0x00000800
326#define CPU_CONTROL_IC_ENABLE 0x00001000
327#define CPU_CONTROL_VECRELOC 0x00002000
328#define CPU_CONTROL_ROUNDROBIN 0x00004000
329#define CPU_CONTROL_V4COMPAT 0x00008000
330#define CPU_CONTROL_FI_ENABLE 0x00200000
331#define CPU_CONTROL_UNAL_ENABLE 0x00400000
332#define CPU_CONTROL_XP_ENABLE 0x00800000
333#define CPU_CONTROL_V_ENABLE 0x01000000
334#define CPU_CONTROL_EX_BEND 0x02000000
335#define CPU_CONTROL_NMFI 0x08000000
336#define CPU_CONTROL_TR_ENABLE 0x10000000
337#define CPU_CONTROL_AF_ENABLE 0x20000000
338#define CPU_CONTROL_TE_ENABLE 0x40000000
340#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
345#define ARM_VM_SECTION (1 << 1)
347#define ARM_VM_SECTION_PRESENT (1 << 1)
349#define ARM_VM_SECTION_B (1 << 2)
351#define ARM_VM_SECTION_C (1 << 3)
353#define ARM_VM_SECTION_DOMAIN (0xF << 5)
355#define ARM_VM_SECTION_SUPER (0x1 << 10)
357#define ARM_VM_SECTION_USER (0x3 << 10)
359#define ARM_VM_SECTION_TEX0 (1 << 12)
361#define ARM_VM_SECTION_TEX1 (1 << 13)
363#define ARM_VM_SECTION_TEX2 (1 << 14)
365#define ARM_VM_SECTION_RO (1 << 15)
367#define ARM_VM_SECTION_SHAREABLE (1 << 16)
369#define ARM_VM_SECTION_NOTGLOBAL (1 << 17)
372#define ARM_VM_SECTION_WB \
373 (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B )
375#define ARM_VM_SECTION_WT \
376 (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C )
378#define ARM_VM_SECTION_WTWB \
379 (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C )
383#define ARM_VM_SECTION_CACHED ARM_VM_SECTION_WTWB
384#define ARM_VM_SECTION_DEVICE (ARM_VM_SECTION_B)