RTEMS 6.1-rc2
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m340timer.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Header file for timer driver
13 * defines for accessing M68340 timer registers
14 *
15 * Author:
16 * Geoffroy Montel
17 * France Telecom - CNET/DSM/TAM/CAT
18 * 4, rue du Clos Courtel
19 * 35512 CESSON-SEVIGNE
20 * FRANCE
21 *
22 * e-mail: g_montel@yahoo.com
23 *
24 * COPYRIGHT (c) 1989-1999.
25 * On-Line Applications Research Corporation (OAR).
26 *
27 * Redistribution and use in source and binary forms, with or without
28 * modification, are permitted provided that the following conditions
29 * are met:
30 * 1. Redistributions of source code must retain the above copyright
31 * notice, this list of conditions and the following disclaimer.
32 * 2. Redistributions in binary form must reproduce the above copyright
33 * notice, this list of conditions and the following disclaimer in the
34 * documentation and/or other materials provided with the distribution.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
37 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
39 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
40 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
41 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
42 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
43 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
44 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
45 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
46 * POSSIBILITY OF SUCH DAMAGE.
47 */
48
49#ifndef __m340timer_H__
50#define __m340timer_H__
51
52extern void Fifo_Full_benchmark_timer_initialize (void);
53
54extern void (*Restart_Fifo_Full_A_Timer)(void);
55extern void (*Restart_Check_A_Timer)(void);
56extern void (*Restart_Fifo_Full_B_Timer)(void);
57extern void (*Restart_Check_B_Timer)(void);
58
59/* CR */
60#define m340_SWR (1<<15)
61#define m340_Polling_Mode (0<<12)
62#define m340_TC_Enabled (1<<12)
63#define m340_TG_Enabled (2<<12)
64#define m340_TG_TC_Enabled (3<<12)
65#define m340_TO_Enabled (4<<12)
66#define m340_TO_TC_Enabled (5<<12)
67#define m340_TG_TG_Enabled (6<<12)
68#define m340_TO_TG_TG_Enabled (7<<12)
69#define m340_TGE (1<<11)
70#define m340_PSE (1<<10)
71#define m340_CPE (1<<9)
72#define m340_CLK (1<<8)
73#define m340_Divide_by_2 (1<<5)
74#define m340_Divide_by_4 (2<<5)
75#define m340_Divide_by_8 (3<<5)
76#define m340_Divide_by_16 (4<<5)
77#define m340_Divide_by_32 (5<<5)
78#define m340_Divide_by_64 (6<<5)
79#define m340_Divide_by_128 (7<<5)
80#define m340_Divide_by_256 (0<<5)
81#define m340_ICOC (0<<2)
82#define m340_SWG (1<<2)
83#define m340_VDCSWG (2<<2)
84#define m340_VWSSPG (3<<2)
85#define m340_PWM (4<<2)
86#define m340_PM (5<<2)
87#define m340_EC (6<<2)
88#define m340_TB (7<<2)
89#define m340_Disabled 0
90#define m340_Toggle_Mode 1
91#define m340_Zero_Mode 2
92#define m340_One_Mode 3
93
94/* SR */
95#define m340_IRQ (1<<15)
96#define m340_TO (1<<14)
97#define m340_TG (1<<13)
98#define m340_TC (1<<12)
99#define m340_TGL (1<<11)
100#define m340_ON (1<<10)
101#define m340_OUT (1<<9)
102#define m340_COM (1<<8)
103
104#endif