RTEMS 6.1-rc2
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i8259.h
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1
7/* irq.h
8 *
9 * This include file describe the data structure and the functions implemented
10 * by RTEMS to control the i8259 chip.
11 *
12 * Copyright (C) 1999 valette@crf.canon.fr
13 *
14 * This code is heavilly inspired by the public specification of STREAM V2
15 * that can be found at :
16 *
17 * <http://www.chorus.com/Documentation/index.html> by following
18 * the STREAM API Specification Document link.
19 *
20 * The license and distribution terms for this file may be
21 * found in the file LICENSE in this distribution or at
22 * http://www.rtems.org/license/LICENSE.
23 */
24
25#ifndef I8259_H
26#define I8259_H
27
40#if 1
41#define ISA8259_M_ELCR 0x4d0
42#define ISA8259_S_ELCR 0x4d1
43#endif
44
45#define ELCRS_INT15_LVL 0x80
46#define ELCRS_INT14_LVL 0x40
47#define ELCRS_INT13_LVL 0x20
48#define ELCRS_INT12_LVL 0x10
49#define ELCRS_INT11_LVL 0x08
50#define ELCRS_INT10_LVL 0x04
51#define ELCRS_INT9_LVL 0x02
52#define ELCRS_INT8_LVL 0x01
53#define ELCRM_INT7_LVL 0x80
54#define ELCRM_INT6_LVL 0x40
55#define ELCRM_INT5_LVL 0x20
56#define ELCRM_INT4_LVL 0x10
57#define ELCRM_INT3_LVL 0x8
58#define ELCRM_INT2_LVL 0x4
59#define ELCRM_INT1_LVL 0x2
60#define ELCRM_INT0_LVL 0x1
61
69#define PIC_MASTER_COMMAND_IO_PORT 0x20
70#define PIC_SLAVE_COMMAND_IO_PORT 0xa0
71#define PIC_MASTER_IMR_IO_PORT 0x21
72#define PIC_SLAVE_IMR_IO_PORT 0xa1
73
81#define PIC_EOSI 0x60
82#define SLAVE_PIC_EOSI 0x62
83#define PIC_EOI 0x20
84
87#ifndef ASM
88
89#ifdef __cplusplus
90extern "C" {
91#endif
92
93/*
94 * rtems_irq_number Definitions
95 */
96#if 0
97
103#define BSP_ISA_IRQ_NUMBER (16)
104#define BSP_ISA_IRQ_LOWEST_OFFSET (0)
105#define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
106
109#ifndef qemu
110#define BSP_PCI_IRQ_NUMBER (16)
111#else
112#define BSP_PCI_IRQ_NUMBER (0)
113#endif
114#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER)
115#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
116
117/*
118 * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
119 * handler might be connected
120 */
121#define BSP_PROCESSOR_IRQ_NUMBER (1)
122#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
123#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
124/* Misc vectors for OPENPIC irqs (IPI, timers)
125 */
126#ifndef qemu
127#define BSP_MISC_IRQ_NUMBER (8)
128#else
129#define BSP_MISC_IRQ_NUMBER (0)
130#endif
131
132#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
133#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
134
140#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1)
141#define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET)
142#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
143
151#define BSP_ISA_PERIODIC_TIMER (0)
152#define BSP_ISA_KEYBOARD (1)
153#define BSP_ISA_UART_COM2_IRQ (3)
154#define BSP_ISA_UART_COM1_IRQ (4)
155#define BSP_ISA_RT_TIMER1 (8)
156#define BSP_ISA_RT_TIMER3 (10)
157
165#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET)
166#if BSP_PCI_IRQ_NUMBER > 0
167#define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0)
168#endif
169
172#if defined(mot_ppc_mvme2100)
173#define BSP_DEC21143_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
174#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
175#define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
176#define BSP_PCMIP_TYPE2_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
177#define BSP_PCMIP_TYPE2_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
178#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
179#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
180#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
181#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
182#define BSP_UART_COM1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
183#define BSP_FRONT_PANEL_ABORT_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
184#define BSP_RTC_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
185#else
186#define BSP_UART_COM1_IRQ BSP_ISA_UART_COM1_IRQ
187#define BSP_UART_COM2_IRQ BSP_ISA_UART_COM2_IRQ
188#endif
189
193#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
194#endif
195
201typedef unsigned short rtems_i8259_masks;
202extern volatile rtems_i8259_masks i8259s_cache;
203
206/*-------------------------------------------------------------------------+
207| Function Prototypes.
208+--------------------------------------------------------------------------*/
209/*
210 * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
211 */
212
218void BSP_i8259s_init(void);
219
230int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine);
231
238int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine);
239
248int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine);
249
253int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine);
254
255int BSP_i8259s_int_process(void);
256
257extern void BSP_rtems_irq_mng_init(unsigned cpuId);
258extern void BSP_i8259s_init(void);
259
264#ifdef __cplusplus
265};
266#endif
267
268#endif
269#endif
unsigned short rtems_i8259_masks
Type definition for RTEMS managed interrupts.
Definition: irq.h:89
int BSP_irq_enable_at_i8259s(const rtems_irq_number irqLine)
function to enable a particular irq at 8259 level.
Definition: i8259.c:91
int BSP_irq_disable_at_i8259s(const rtems_irq_number irqLine)
function to disable a particular irq at 8259 level.
Definition: i8259.c:49
int BSP_irq_ack_at_i8259s(const rtems_irq_number irqLine)
function to acknowledge a particular irq at 8259 level.
Definition: i8259.c:143
int BSP_irq_enabled_at_i8259s(const rtems_irq_number irqLine)
function to check if a particular irq is enabled at 8259 level.
Definition: i8259.c:125