RTEMS 6.1-rc2
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gr1553b.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/* GR1553B driver, used by BC, RT and/or BM driver
4 *
5 * COPYRIGHT (c) 2010.
6 * Cobham Gaisler AB.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 *
29 * OVERVIEW
30 * ========
31 * This driver controls the GR1553B device regardless of interfaces supported
32 * (BC, RT and/or BM). The device can be located at an on-chip AMBA or an
33 * AMBA-over-PCI bus. This driver provides an interface for the BC, RT and BM
34 * drivers to use. Since the different interfaces are accessed over the same
35 * register interface on the same core, the other drivers must share a GR1553B
36 * device. Any combination of interface functionality is supported, but the RT
37 * and BC functionality can nnot be used simultaneously due to hardware
38 * limitation.
39 *
40 */
41
42#ifndef __GR1553B_H__
43#define __GR1553B_H__
44
45#include <stdint.h>
46
47#ifdef __cplusplus
48extern "C" {
49#endif
50
51/* The GR1553B registers */
53 /* Common Registers */
54 volatile uint32_t irq; /* 0x00 IRQ register */
55 volatile uint32_t imask; /* 0x04 IRQ enable mask */
56 int unused0[(0x10-0x08)/4];
57 volatile uint32_t hwcfg; /* 0x10 HW config register */
58
59 int unused1[(0x40-0x14)/4]; /* Padding */
60
61 /* BC Registers */
62 volatile uint32_t bc_stat; /* 0x40 BC status */
63 volatile uint32_t bc_ctrl; /* 0x44 BC Action register */
64 volatile uint32_t bc_bd; /* 0x48 BC transfer list pointer */
65 volatile uint32_t bc_abd; /* 0x4c BC async list pointer */
66 volatile uint32_t bc_timer; /* 0x50 BC timer register */
67 volatile uint32_t bc_wake; /* 0x54 BC wakeup control register */
68 volatile uint32_t bc_irqptr; /* 0x58 BC transfer IRQ pointer */
69 volatile uint32_t bc_busmsk; /* 0x5C BC per-RT bus mask register */
70
71 int unused2[(0x68-0x60)/4]; /* Padding */
72
73 volatile uint32_t bc_slot; /* 0x68 BC Current BD pointer */
74 volatile uint32_t bc_aslot; /* 0x6c BC Current async BD pointer */
75
76 int unused3[(0x80-0x70)/4]; /* Padding */
77
78 /* RT Registers */
79 volatile uint32_t rt_stat; /* 0x80 RT status */
80 volatile uint32_t rt_cfg; /* 0x84 RT config register */
81 volatile uint32_t rt_stat2; /* 0x88 RT bus status bits */
82 volatile uint32_t rt_statw; /* 0x8c RT status words */
83 volatile uint32_t rt_sync; /* 0x90 RT bus synchronize */
84 volatile uint32_t rt_tab; /* 0x94 RT subaddress table base */
85 volatile uint32_t rt_mcctrl; /* 0x98 RT valid mode code mask */
86 int unused4[(0xa4-0x9c)/4];
87 volatile uint32_t rt_ttag; /* 0xa4 RT time tag register */
88 int unused5; /* 0xa8 RESERVED */
89 volatile uint32_t rt_evsz; /* 0xac RT event log end pointer */
90 volatile uint32_t rt_evlog; /* 0xb0 RT event log position */
91 volatile uint32_t rt_evirq; /* 0xb4 RT event log IRQ position */
92
93 int unused6[(0xc0-0xb8)/4]; /* Padding */
94
95 /* BM Registers */
96 volatile uint32_t bm_stat; /* 0xc0 BM status */
97 volatile uint32_t bm_ctrl; /* 0xc4 BM control register */
98 volatile uint32_t bm_adr; /* 0xc8 BM address filter */
99 volatile uint32_t bm_subadr; /* 0xcc BM subaddress filter */
100 volatile uint32_t bm_mc; /* 0xd0 BM mode code filter */
101 volatile uint32_t bm_start; /* 0xd4 BM log start address */
102 volatile uint32_t bm_end; /* 0xd8 BM log size/alignment mask */
103 volatile uint32_t bm_pos; /* 0xdc BM log position */
104 volatile uint32_t bm_ttag; /* 0xe0 BM time tag register */
105};
106
107#define GR1553BC_KEY 0x15520000
108#define GR1553RT_KEY 0x15530000
109
110/* IRQ Definitions */
111#define GR1553BC_IRQLOG_SIZE 64
112#define GR1553BC_IRQLOG_CNT (GR1553BC_IRQLOG_SIZE/sizeof(uint32_t))
113
114/*** IRQ Flag Register ***/
115#define GR1553B_IRQ_BCEV_BIT 0
116#define GR1553B_IRQ_BCD_BIT 1
117#define GR1553B_IRQ_BCWK_BIT 2
118#define GR1553B_IRQ_RTEV_BIT 8
119#define GR1553B_IRQ_RTD_BIT 9
120#define GR1553B_IRQ_RTTE_BIT 10
121#define GR1553B_IRQ_BMD_BIT 16
122#define GR1553B_IRQ_BMTOF_BIT 17
123
124#define GR1553B_IRQ_BCEV (1<<GR1553B_IRQ_BCEV_BIT)
125#define GR1553B_IRQ_BCD (1<<GR1553B_IRQ_BCD_BIT)
126#define GR1553B_IRQ_BCWK (1<<GR1553B_IRQ_BCWK_BIT)
127#define GR1553B_IRQ_RTEV (1<<GR1553B_IRQ_RTEV_BIT)
128#define GR1553B_IRQ_RTD (1<<GR1553B_IRQ_RTD_BIT)
129#define GR1553B_IRQ_RTTE (1<<GR1553B_IRQ_RTTE_BIT)
130#define GR1553B_IRQ_BMD (1<<GR1553B_IRQ_BMD_BIT)
131#define GR1553B_IRQ_BMTOF (1<<GR1553B_IRQ_BMTOF_BIT)
132
133/*** IRQ Enable Register ***/
134#define GR1553B_IRQEN_BCEVE_BIT 0
135#define GR1553B_IRQEN_BCDE_BIT 1
136#define GR1553B_IRQEN_BCWKE_BIT 2
137#define GR1553B_IRQEN_RTEVE_BIT 8
138#define GR1553B_IRQEN_RTDE_BIT 9
139#define GR1553B_IRQEN_RTTEE_BIT 10
140#define GR1553B_IRQEN_BMDE_BIT 16
141#define GR1553B_IRQEN_BMTOE_BIT 17
142
143#define GR1553B_IRQEN_BCEVE (1<<GR1553B_IRQEN_BCEVE_BIT)
144#define GR1553B_IRQEN_BCDE (1<<GR1553B_IRQEN_BCDE_BIT)
145#define GR1553B_IRQEN_BCWKE (1<<GR1553B_IRQEN_BCWKE_BIT)
146#define GR1553B_IRQEN_RTEVE (1<<GR1553B_IRQEN_RTEVE_BIT)
147#define GR1553B_IRQEN_RTDE (1<<GR1553B_IRQEN_RTDE_BIT)
148#define GR1553B_IRQEN_RTTEE (1<<GR1553B_IRQEN_RTTEE_BIT)
149#define GR1553B_IRQEN_BMDE (1<<GR1553B_IRQEN_BMDE_BIT)
150#define GR1553B_IRQEN_BMTOE (1<<GR1553B_IRQEN_BMTOE_BIT)
151
152/*** BC Status Register ***/
153#define GR1553B_BC_STAT_SCST_BIT 0
154#define GR1553B_BC_STAT_SCADL_BIT 3
155#define GR1553B_BC_STAT_ASST_BIT 8
156#define GR1553B_BC_STAT_ASADL_BIT 11
157#define GR1553B_BC_STAT_BCSUP_BIT 31
158
159#define GR1553B_BC_STAT_SCST (0x3<<GR1553B_BC_STAT_SCST_BIT)
160#define GR1553B_BC_STAT_SCADL (0x1f<<GR1553B_BC_STAT_SCADL_BIT)
161#define GR1553B_BC_STAT_ASST (0x3<<GR1553B_BC_STAT_ASST_BIT)
162#define GR1553B_BC_STAT_ASADL (0x1f<<GR1553B_BC_STAT_ASADL_BIT)
163#define GR1553B_BC_STAT_BCSUP (1<<GR1553B_BC_STAT_BCSUP_BIT)
164
165/*** BC Action Register ***/
166#define GR1553B_BC_ACT_SCSRT_BIT 0
167#define GR1553B_BC_ACT_SCSUS_BIT 1
168#define GR1553B_BC_ACT_SCSTP_BIT 2
169#define GR1553B_BC_ACT_SETT_BIT 3
170#define GR1553B_BC_ACT_CLRT_BIT 4
171#define GR1553B_BC_ACT_ASSRT_BIT 8
172#define GR1553B_BC_ACT_ASSTP_BIT 9
173#define GR1553B_BC_ACT_BCKEY_BIT 16
174
175#define GR1553B_BC_ACT_SCSRT (1<<GR1553B_BC_ACT_SCSRT_BIT)
176#define GR1553B_BC_ACT_SCSUS (1<<GR1553B_BC_ACT_SCSUS_BIT)
177#define GR1553B_BC_ACT_SCSTP (1<<GR1553B_BC_ACT_SCSTP_BIT)
178#define GR1553B_BC_ACT_SETT (1<<GR1553B_BC_ACT_SETT_BIT)
179#define GR1553B_BC_ACT_CLRT (1<<GR1553B_BC_ACT_CLRT_BIT)
180#define GR1553B_BC_ACT_ASSRT (1<<GR1553B_BC_ACT_ASSRT_BIT)
181#define GR1553B_BC_ACT_ASSTP (1<<GR1553B_BC_ACT_ASSTP_BIT)
182#define GR1553B_BC_ACT_BCKEY (0xffff<<GR1553B_BC_ACT_BCKEY_BIT)
183
184/*** BC Timer Register ***/
185#define GR1553B_BC_TIMER_SCTM_BIT 0
186
187#define GR1553B_BC_TIMER_SCTM (0xffffff<<GR1553B_BC_TIMER_SCTM_BIT)
188
189/*** BC Wake-up control Register ***/
190#define GR1553B_BC_WAKE_TIME_BIT 0
191#define GR1553B_BC_WAKE_WKEN_BIT 31
192
193#define GR1553B_BC_WAKE_TIME (0xffffff<<GR1553B_BC_WAKE_TIME_BIT)
194#define GR1553B_BC_WAKE_WKEN (1<GR1553B_BC_WAKE_WKEN_BIT)
195
196/*** RT status Register ***/
197#define GR1553B_RT_STAT_RUN_BIT 0
198#define GR1553B_RT_STAT_SHDB_BIT 1
199#define GR1553B_RT_STAT_SHDA_BIT 2
200#define GR1553B_RT_STAT_ACT_BIT 3
201#define GR1553B_RT_STAT_RTSUP_BIT 31
202
203#define GR1553B_RT_STAT_RUN (1<<GR1553B_RT_STAT_RUN_BIT)
204#define GR1553B_RT_STAT_SHDB (1<<GR1553B_RT_STAT_SHDB_BIT)
205#define GR1553B_RT_STAT_SHDA (1<<GR1553B_RT_STAT_SHDA_BIT)
206#define GR1553B_RT_STAT_ACT (1<<GR1553B_RT_STAT_ACT_BIT)
207#define GR1553B_RT_STAT_RTSUP (1<<GR1553B_RT_STAT_RTSUP_BIT)
208
209
210/*** RT Config Register ***/
211#define GR1553B_RT_CFG_RTEN_BIT 0
212#define GR1553B_RT_CFG_RTADDR_BIT 1
213#define GR1553B_RT_CFG_RTKEY_BIT 16
214
215#define GR1553B_RT_CFG_RTEN (1<<GR1553B_RT_CFG_RTEN_BIT)
216#define GR1553B_RT_CFG_RTADDR (1<<GR1553B_RT_CFG_RTADDR_BIT)
217#define GR1553B_RT_CFG_RTKEY (0xffff<<GR1553B_RT_CFG_RTKEY_BIT)
218
219/*** RT Bus Status Register ***/
220#define GR1553B_RT_STAT2_TFLG_BIT 0
221#define GR1553B_RT_STAT2_DBCA_BIT 1
222#define GR1553B_RT_STAT2_SSF_BIT 2
223#define GR1553B_RT_STAT2_BUSY_BIT 3
224#define GR1553B_RT_STAT2_SREQ_BIT 4
225#define GR1553B_RT_STAT2_TFDE_BIT 8
226
227#define GR1553B_RT_STAT2_TFLG (1<<GR1553B_RT_STAT2_TFLG_BIT)
228#define GR1553B_RT_STAT2_DBCA (1<<GR1553B_RT_STAT2_DBCA_BIT)
229#define GR1553B_RT_STAT2_SSF (1<<GR1553B_RT_STAT2_SSF_BIT)
230#define GR1553B_RT_STAT2_BUSY (1<<GR1553B_RT_STAT2_BUSY_BIT)
231#define GR1553B_RT_STAT2_SREQ (1<<GR1553B_RT_STAT2_SREQ_BIT)
232#define GR1553B_RT_STAT2_TFDE (1<<GR1553B_RT_STAT2_TFDE_BIT)
233
234/*** RT Status Words Register ***/
235#define GR1553B_RT_STATW_VECW_BIT 0
236#define GR1553B_RT_STATW_BITW_BIT 16
237
238#define GR1553B_RT_STATW_VECW (0xffff<<GR1553B_RT_STATW_VECW_BIT)
239#define GR1553B_RT_STATW_BITW (0xffff<<GR1553B_RT_STATW_BITW_BIT)
240
241/*** RT Sync Register ***/
242#define GR1553B_RT_SYNC_SYD_BIT 0
243#define GR1553B_RT_SYNC_SYTM_BIT 16
244
245#define GR1553B_RT_SYNC_SYD (0xffff<<GR1553B_RT_SYNC_SYD_BIT)
246#define GR1553B_RT_SYNC_SYTM (0xffff<<GR1553B_RT_SYNC_SYTM_BIT)
247
248/*** RT Sub adress table Register ***/
249#define GR1553B_RT_TAB_SATB_BIT 0
250
251#define GR1553B_RT_TAB_SATB (0xffff<<GR1553B_RT_TAB_SATB_BIT)
252
253/*** RT Mode code control Register ***/
254#define GR1553B_RT_MCCTRL_S_BIT 0
255#define GR1553B_RT_MCCTRL_SB_BIT 2
256#define GR1553B_RT_MCCTRL_SD_BIT 4
257#define GR1553B_RT_MCCTRL_SDB_BIT 6
258#define GR1553B_RT_MCCTRL_TS_BIT 8
259#define GR1553B_RT_MCCTRL_TSB_BIT 10
260#define GR1553B_RT_MCCTRL_TVW_BIT 12
261#define GR1553B_RT_MCCTRL_TBW_BIT 14
262#define GR1553B_RT_MCCTRL_DBC_BIT 16
263#define GR1553B_RT_MCCTRL_IST_BIT 18
264#define GR1553B_RT_MCCTRL_ISTB_BIT 20
265#define GR1553B_RT_MCCTRL_ITF_BIT 22
266#define GR1553B_RT_MCCTRL_ITFB_BIT 24
267#define GR1553B_RT_MCCTRL_RRT_BIT 26
268#define GR1553B_RT_MCCTRL_RRTB_BIT 28
269
270#define GR1553B_RT_MCCTRL_S (1<<GR1553B_RT_MCCTRL_S_BIT)
271#define GR1553B_RT_MCCTRL_SB (1<<GR1553B_RT_MCCTRL_SB_BIT)
272#define GR1553B_RT_MCCTRL_SD (1<<GR1553B_RT_MCCTRL_SD_BIT)
273#define GR1553B_RT_MCCTRL_SDB (1<<GR1553B_RT_MCCTRL_SDB_BIT)
274#define GR1553B_RT_MCCTRL_TS (1<<GR1553B_RT_MCCTRL_TS_BIT)
275#define GR1553B_RT_MCCTRL_TSB (1<<GR1553B_RT_MCCTRL_TSB_BIT)
276#define GR1553B_RT_MCCTRL_TVW (1<<GR1553B_RT_MCCTRL_TVW_BIT)
277#define GR1553B_RT_MCCTRL_TBW (1<<GR1553B_RT_MCCTRL_TBW_BIT)
278#define GR1553B_RT_MCCTRL_DBC (1<<GR1553B_RT_MCCTRL_DBC_BIT)
279#define GR1553B_RT_MCCTRL_IST (1<<GR1553B_RT_MCCTRL_IST_BIT)
280#define GR1553B_RT_MCCTRL_ISTB (1<<GR1553B_RT_MCCTRL_ISTB_BIT)
281#define GR1553B_RT_MCCTRL_ITF (1<<GR1553B_RT_MCCTRL_ITF_BIT)
282#define GR1553B_RT_MCCTRL_ITFB (1<<GR1553B_RT_MCCTRL_ITFB_BIT)
283#define GR1553B_RT_MCCTRL_RRT (1<<GR1553B_RT_MCCTRL_RRT_BIT)
284#define GR1553B_RT_MCCTRL_RRTB (1<<GR1553B_RT_MCCTRL_RRTB_BIT)
285
286/*** RT Time Tag control Register ***/
287#define GR1553B_RT_TTAG_TVAL_BIT 0
288#define GR1553B_RT_TTAG_TRES_BIT 16
289
290#define GR1553B_RT_TTAG_TVAL (0xffff<<GR1553B_RT_TTAG_TVAL_BIT)
291#define GR1553B_RT_TTAG_TRES (0xffff<<GR1553B_RT_TTAG_TRES_BIT)
292
293/*** BM Control Register ***/
294#define GR1553B_BM_STAT_BMSUP_BIT 31
295
296#define GR1553B_BM_STAT_BMSUP (1<<GR1553B_BM_STAT_BMSUP_BIT)
297
298/*** BM Control Register ***/
299#define GR1553B_BM_CTRL_BMEN_BIT 0
300#define GR1553B_BM_CTRL_MANL_BIT 1
301#define GR1553B_BM_CTRL_UDWL_BIT 2
302#define GR1553B_BM_CTRL_IMCL_BIT 3
303
304#define GR1553B_BM_CTRL_BMEN (1<<GR1553B_BM_CTRL_BMEN_BIT)
305#define GR1553B_BM_CTRL_MANL (1<<GR1553B_BM_CTRL_MANL_BIT)
306#define GR1553B_BM_CTRL_UDWL (1<<GR1553B_BM_CTRL_UDWL_BIT)
307#define GR1553B_BM_CTRL_IMCL (1<<GR1553B_BM_CTRL_IMCL_BIT)
308
309/*** BM RT Mode code filter Register ***/
310#define GR1553B_BM_MC_S_BIT 0
311#define GR1553B_BM_MC_SB_BIT 1
312#define GR1553B_BM_MC_SD_BIT 2
313#define GR1553B_BM_MC_SDB_BIT 3
314#define GR1553B_BM_MC_TS_BIT 4
315#define GR1553B_BM_MC_TSB_BIT 5
316#define GR1553B_BM_MC_TVW_BIT 6
317#define GR1553B_BM_MC_TBW_BIT 7
318#define GR1553B_BM_MC_DBC_BIT 8
319#define GR1553B_BM_MC_IST_BIT 9
320#define GR1553B_BM_MC_ISTB_BIT 10
321#define GR1553B_BM_MC_ITF_BIT 11
322#define GR1553B_BM_MC_ITFB_BIT 12
323#define GR1553B_BM_MC_RRT_BIT 13
324#define GR1553B_BM_MC_RRTB_BIT 14
325#define GR1553B_BM_MC_TSW_BIT 15
326#define GR1553B_BM_MC_TLC_BIT 16
327#define GR1553B_BM_MC_STS_BIT 17
328#define GR1553B_BM_MC_STSB_BIT 18
329
330#define GR1553B_BM_MC_S (1<<GR1553B_BM_MC_S_BIT)
331#define GR1553B_BM_MC_SB (1<<GR1553B_BM_MC_SB_BIT)
332#define GR1553B_BM_MC_SD (1<<GR1553B_BM_MC_SD_BIT)
333#define GR1553B_BM_MC_SDB (1<<GR1553B_BM_MC_SDB_BIT)
334#define GR1553B_BM_MC_TS (1<<GR1553B_BM_MC_TS_BIT)
335#define GR1553B_BM_MC_TSB (1<<GR1553B_BM_MC_TSB_BIT)
336#define GR1553B_BM_MC_TVW (1<<GR1553B_BM_MC_TVW_BIT)
337#define GR1553B_BM_MC_TBW (1<<GR1553B_BM_MC_TBW_BIT)
338#define GR1553B_BM_MC_DBC (1<<GR1553B_BM_MC_DBC_BIT)
339#define GR1553B_BM_MC_IST (1<<GR1553B_BM_MC_IST_BIT)
340#define GR1553B_BM_MC_ISTB (1<<GR1553B_BM_MC_ISTB_BIT)
341#define GR1553B_BM_MC_ITF (1<<GR1553B_BM_MC_ITF_BIT)
342#define GR1553B_BM_MC_ITFB (1<<GR1553B_BM_MC_ITFB_BIT)
343#define GR1553B_BM_MC_RRT (1<<GR1553B_BM_MC_RRT_BIT)
344#define GR1553B_BM_MC_RRTB (1<<GR1553B_BM_MC_RRTB_BIT)
345#define GR1553B_BM_MC_TSW (1<<GR1553B_BM_MC_TSW_BIT)
346#define GR1553B_BM_MC_TLC (1<<GR1553B_BM_MC_TLC_BIT)
347#define GR1553B_BM_MC_STS (1<<GR1553B_BM_MC_STS_BIT)
348#define GR1553B_BM_MC_STSB (1<<GR1553B_BM_MC_STSB_BIT)
349
350/*** BM RT Mode code filter Register ***/
351#define GR1553B_BM_TTAG_VAL_BIT 0
352#define GR1553B_BM_TTAG_RES_BIT 24
353
354#define GR1553B_BM_TTAG_VAL (0xffffff<<GR1553B_BM_TTAG_VAL_BIT)
355#define GR1553B_BM_TTAG_RES (0xff<<GR1553B_BM_TTAG_RES_BIT)
356
357/* Register GR1553B driver */
358extern void gr1553_register(void);
359
360/*** BC Device allocation ***/
361/* Allocate a BC device. Minor is assigned to a device in the order
362 * they are registered to the driver.
363 */
364extern struct drvmgr_dev **gr1553_bc_open(int minor);
365/* Free a BC device previously allocated */
366extern void gr1553_bc_close(struct drvmgr_dev **dev);
367
368/*** RT Device allocation ***/
369/* Allocate a BC device. Minor is assigned to a device in the order
370 * they are registered to the driver.
371 */
372extern struct drvmgr_dev **gr1553_rt_open(int minor);
373/* Free a BC device previously allocated */
374extern void gr1553_rt_close(struct drvmgr_dev **dev);
375
376/*** BM Device allocation ***/
377/* Allocate a BC device. Minor is assigned to a device in the order
378 * they are registered to the driver.
379 */
380extern struct drvmgr_dev **gr1553_bm_open(int minor);
381/* Free a BC device previously allocated */
382extern void gr1553_bm_close(struct drvmgr_dev **dev);
383
384#ifdef __cplusplus
385}
386#endif
387
388#endif /* __GR1553B_H__ */
Definition: drvmgr.h:297
Definition: gr1553b.h:52