fsl_semc.h

/*
 * Copyright 2017-2022 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
#ifndef _FSL_SEMC_H_
#define _FSL_SEMC_H_
 
#include "fsl_common.h"
 
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 4, 3))
enum
{
    kStatus_SEMC_InvalidDeviceType        = MAKE_STATUS(kStatusGroup_SEMC, 0), 
    kStatus_SEMC_IpCommandExecutionError  = MAKE_STATUS(kStatusGroup_SEMC, 1), 
    kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), 
    kStatus_SEMC_InvalidMemorySize        = MAKE_STATUS(kStatusGroup_SEMC, 3), 
    kStatus_SEMC_InvalidIpcmdDataSize     = MAKE_STATUS(kStatusGroup_SEMC, 4), 
    kStatus_SEMC_InvalidAddressPortWidth  = MAKE_STATUS(kStatusGroup_SEMC, 5), 
    kStatus_SEMC_InvalidDataPortWidth     = MAKE_STATUS(kStatusGroup_SEMC, 6), 
    kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), 
    kStatus_SEMC_InvalidBurstLength       = MAKE_STATUS(kStatusGroup_SEMC, 8), 
    kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9),
    kStatus_SEMC_InvalidBaseAddress           = MAKE_STATUS(kStatusGroup_SEMC, 10), 
    kStatus_SEMC_InvalidTimerSetting          = MAKE_STATUS(kStatusGroup_SEMC, 11), 
};
 
typedef enum _semc_mem_type
{
    kSEMC_MemType_SDRAM = 0, 
    kSEMC_MemType_SRAM,      
    kSEMC_MemType_NOR,       
    kSEMC_MemType_NAND,      
    kSEMC_MemType_8080       
} semc_mem_type_t;
 
typedef enum _semc_waitready_polarity
{
    kSEMC_LowActive = 0, 
    kSEMC_HighActive,    
} semc_waitready_polarity_t;
 
typedef enum _semc_sdram_cs
{
    kSEMC_SDRAM_CS0 = 0, 
    kSEMC_SDRAM_CS1,     
    kSEMC_SDRAM_CS2,     
    kSEMC_SDRAM_CS3      
} semc_sdram_cs_t;
 
typedef enum _semc_sram_cs
{
#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT == 0x04U)
    kSEMC_SRAM_CS0 = 0, 
    kSEMC_SRAM_CS1,     
    kSEMC_SRAM_CS2,     
    kSEMC_SRAM_CS3      
#else
    kSEMC_SRAM_CS0        = 0, 
#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
} semc_sram_cs_t;
 
typedef enum _semc_nand_access_type
{
    kSEMC_NAND_ACCESS_BY_AXI = 0, 
    kSEMC_NAND_ACCESS_BY_IPCMD,   
} semc_nand_access_type_t;
 
typedef enum _semc_interrupt_enable
{
    kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, 
    kSEMC_IPCmdErrInterrupt  = SEMC_INTEN_IPCMDERREN_MASK,  
    kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, 
    kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK  
} semc_interrupt_enable_t;
 
typedef enum _semc_ipcmd_datasize
{
    kSEMC_IPcmdDataSize_1bytes = 1, 
    kSEMC_IPcmdDataSize_2bytes,     
    kSEMC_IPcmdDataSize_3bytes,     
    kSEMC_IPcmdDataSize_4bytes      
} semc_ipcmd_datasize_t;
 
typedef enum _semc_refresh_time
{
    kSEMC_RefreshThreeClocks = 0x0U, 
    kSEMC_RefreshSixClocks,          
    kSEMC_RefreshNineClocks          
} semc_refresh_time_t;
 
typedef enum _semc_caslatency
{
    kSEMC_LatencyOne = 1, 
    kSEMC_LatencyTwo,     
    kSEMC_LatencyThree,   
} semc_caslatency_t;
 
typedef enum _semc_sdram_column_bit_num
{
    kSEMC_SdramColunm_12bit = 0x0U, 
    kSEMC_SdramColunm_11bit,        
    kSEMC_SdramColunm_10bit,        
    kSEMC_SdramColunm_9bit,         
#if defined(FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT) && (FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT)
    kSEMC_SdramColunm_8bit, 
#endif                      /* FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT */
} semc_sdram_column_bit_num_t;
 
typedef enum _semc_sdram_burst_len
{
#if defined(FSL_FEATURE_SEMC_ERRATA_050577) && (FSL_FEATURE_SEMC_ERRATA_050577 == 0x01U)
    kSEMC_Sdram_BurstLen1 = 0, 
#else
    kSEMC_Sdram_BurstLen1 = 0, 
    kSEMC_Sdram_BurstLen2,     
    kSEMC_Sdram_BurstLen4,     
    kSEMC_Sdram_BurstLen8      
#endif /* FSL_FEATURE_SEMC_ERRATA_050577 */
} sem_sdram_burst_len_t;
 
typedef enum _semc_nand_column_bit_num
{
    kSEMC_NandColum_16bit = 0x0U, 
    kSEMC_NandColum_15bit,        
    kSEMC_NandColum_14bit,        
    kSEMC_NandColum_13bit,        
    kSEMC_NandColum_12bit,        
    kSEMC_NandColum_11bit,        
    kSEMC_NandColum_10bit,        
    kSEMC_NandColum_9bit,         
} semc_nand_column_bit_num_t;
 
typedef enum _semc_nand_burst_len
{
    kSEMC_Nand_BurstLen1 = 0, 
    kSEMC_Nand_BurstLen2,     
    kSEMC_Nand_BurstLen4,     
    kSEMC_Nand_BurstLen8,     
    kSEMC_Nand_BurstLen16,    
    kSEMC_Nand_BurstLen32,    
    kSEMC_Nand_BurstLen64     
} sem_nand_burst_len_t;
 
typedef enum _semc_norsram_column_bit_num
{
    kSEMC_NorColum_12bit = 0x0U, 
    kSEMC_NorColum_11bit,        
    kSEMC_NorColum_10bit,        
    kSEMC_NorColum_9bit,         
    kSEMC_NorColum_8bit,         
    kSEMC_NorColum_7bit,         
    kSEMC_NorColum_6bit,         
    kSEMC_NorColum_5bit,         
    kSEMC_NorColum_4bit,         
    kSEMC_NorColum_3bit,         
    kSEMC_NorColum_2bit          
} semc_norsram_column_bit_num_t;
 
typedef enum _semc_norsram_burst_len
{
    kSEMC_Nor_BurstLen1 = 0, 
    kSEMC_Nor_BurstLen2,     
    kSEMC_Nor_BurstLen4,     
    kSEMC_Nor_BurstLen8,     
    kSEMC_Nor_BurstLen16,    
    kSEMC_Nor_BurstLen32,    
    kSEMC_Nor_BurstLen64     
} sem_norsram_burst_len_t;
 
typedef enum _semc_dbi_column_bit_num
{
    kSEMC_Dbi_Colum_12bit = 0x0U, 
    kSEMC_Dbi_Colum_11bit,        
    kSEMC_Dbi_Colum_10bit,        
    kSEMC_Dbi_Colum_9bit,         
    kSEMC_Dbi_Colum_8bit,         
    kSEMC_Dbi_Colum_7bit,         
    kSEMC_Dbi_Colum_6bit,         
    kSEMC_Dbi_Colum_5bit,         
    kSEMC_Dbi_Colum_4bit,         
    kSEMC_Dbi_Colum_3bit,         
    kSEMC_Dbi_Colum_2bit          
} semc_dbi_column_bit_num_t;
 
typedef enum _semc_dbi_burst_len
{
    kSEMC_Dbi_BurstLen1 = 0, 
    kSEMC_Dbi_BurstLen2,     
    kSEMC_Dbi_Dbi_BurstLen4, 
    kSEMC_Dbi_BurstLen8,     
    kSEMC_Dbi_BurstLen16,    
    kSEMC_Dbi_BurstLen32,    
    kSEMC_Dbi_BurstLen64     
} sem_dbi_burst_len_t;
 
typedef enum _semc_iomux_pin
{
    kSEMC_MUXA8   = SEMC_IOCR_MUX_A8_SHIFT,   
    kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, 
    kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, 
    kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, 
    kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, 
    kSEMC_MUXRDY  = SEMC_IOCR_MUX_RDY_SHIFT   
} semc_iomux_pin;
 
typedef enum _semc_iomux_nora27_pin
{
    kSEMC_MORA27_NONE    = 0,                        
    kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, 
    kSEMC_NORA27_MUXRDY  = SEMC_IOCR_MUX_RDY_SHIFT   
} semc_iomux_nora27_pin;
 
typedef enum _semc_port_size
{
    kSEMC_PortSize8Bit = 0, 
    kSEMC_PortSize16Bit,    
#if defined(FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH) && (FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH == 0x02U)
    kSEMC_PortSize32Bit 
#endif                  /* FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH */
} smec_port_size_t;
 
typedef enum _semc_addr_mode
{
    kSEMC_AddrDataMux = 0, 
    kSEMC_AdvAddrdataMux,  
    kSEMC_AddrDataNonMux   
} semc_addr_mode_t;
 
typedef enum _semc_dqs_mode
{
    kSEMC_Loopbackinternal = 0, 
    kSEMC_Loopbackdqspad,       
} semc_dqs_mode_t;
 
typedef enum _semc_adv_polarity
{
    kSEMC_AdvActiveLow = 0, 
    kSEMC_AdvActiveHigh,    
} semc_adv_polarity_t;
 
typedef enum _semc_sync_mode
{
    kSEMC_AsyncMode = 0, 
    kSEMC_SyncMode,      
} semc_sync_mode_t;
 
typedef enum _semc_adv_level_control
{
    kSEMC_AdvHigh = 0, 
    kSEMC_AdvLow,      
} semc_adv_level_control_t;
 
typedef enum _semc_rdy_polarity
{
    kSEMC_RdyActiveLow = 0, 
    kSEMC_RdyActivehigh,    
} semc_rdy_polarity_t;
 
typedef enum _semc_ipcmd_nand_addrmode
{
    kSEMC_NANDAM_ColumnRow = 0x0U, 
    kSEMC_NANDAM_ColumnCA0,        
    kSEMC_NANDAM_ColumnCA0CA1,     
    kSEMC_NANDAM_RawRA0,           
    kSEMC_NANDAM_RawRA0RA1,        
    kSEMC_NANDAM_RawRA0RA1RA2      
} semc_ipcmd_nand_addrmode_t;
 
typedef enum _semc_ipcmd_nand_cmdmode
{
    kSEMC_NANDCM_Command = 0x2U,      
    kSEMC_NANDCM_CommandHold,         
    kSEMC_NANDCM_CommandAddress,      
    kSEMC_NANDCM_CommandAddressHold,  
    kSEMC_NANDCM_CommandAddressRead,  
    kSEMC_NANDCM_CommandAddressWrite, 
    kSEMC_NANDCM_CommandRead,         
    kSEMC_NANDCM_CommandWrite,        
    kSEMC_NANDCM_Read,                
    kSEMC_NANDCM_Write                
} semc_ipcmd_nand_cmdmode_t;
 
typedef enum _semc_nand_address_option
{
    kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, 
    kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, 
    kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, 
    kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, 
    kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, 
    kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, 
} semc_nand_address_option_t;
 
typedef enum _semc_ipcmd_nor_dbi
{
    kSEMC_NORDBICM_Read = 0x2U, 
    kSEMC_NORDBICM_Write        
} semc_ipcmd_nor_dbi_t;
 
typedef enum _semc_ipcmd_sram
{
    kSEMC_SRAMCM_ArrayRead = 0x2U, 
    kSEMC_SRAMCM_ArrayWrite,       
    kSEMC_SRAMCM_RegRead,          
    kSEMC_SRAMCM_RegWrite          
} semc_ipcmd_sram_t;
 
typedef enum _semc_ipcmd_sdram
{
    kSEMC_SDRAMCM_Read = 0x8U, 
    kSEMC_SDRAMCM_Write,       
    kSEMC_SDRAMCM_Modeset,     
    kSEMC_SDRAMCM_Active,      
    kSEMC_SDRAMCM_AutoRefresh, 
    kSEMC_SDRAMCM_SelfRefresh, 
    kSEMC_SDRAMCM_Precharge,   
    kSEMC_SDRAMCM_Prechargeall 
} semc_ipcmd_sdram_t;
 
typedef struct _semc_sdram_config
{
    semc_iomux_pin csxPinMux;       
    uint32_t address;               
    uint32_t memsize_kbytes;        
    smec_port_size_t portSize;      
    sem_sdram_burst_len_t burstLen; 
    semc_sdram_column_bit_num_t columnAddrBitNum; 
    semc_caslatency_t casLatency;                 
    uint8_t tPrecharge2Act_Ns;                    
    uint8_t tAct2ReadWrite_Ns;                    
    uint8_t tRefreshRecovery_Ns;                  
    uint8_t tWriteRecovery_Ns;                    
    uint8_t tCkeOff_Ns;                           
    uint8_t tAct2Prechage_Ns;                     
    uint8_t tSelfRefRecovery_Ns;                  
    uint8_t tRefresh2Refresh_Ns;                  
    uint8_t tAct2Act_Ns;                          
    uint32_t tPrescalePeriod_Ns;     
    uint32_t tIdleTimeout_Ns;        
    uint32_t refreshPeriod_nsPerRow; 
    uint32_t refreshUrgThreshold;    
    uint8_t refreshBurstLen;         
#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
    uint8_t delayChain; 
#endif                  /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
} semc_sdram_config_t;
 
typedef struct _semc_nand_timing_config
{
    uint8_t tCeSetup_Ns;        
    uint8_t tCeHold_Ns;         
    uint8_t tCeInterval_Ns;     
    uint8_t tWeLow_Ns;          
    uint8_t tWeHigh_Ns;         
    uint8_t tReLow_Ns;          
    uint8_t tReHigh_Ns;         
    uint8_t tTurnAround_Ns;     
    uint8_t tWehigh2Relow_Ns;   
    uint8_t tRehigh2Welow_Ns;   
    uint8_t tAle2WriteStart_Ns; 
    uint8_t tReady2Relow_Ns;    
    uint8_t tWehigh2Busy_Ns;    
} semc_nand_timing_config_t;
 
typedef struct _semc_nand_config
{
    semc_iomux_pin cePinMux;    
    uint32_t axiAddress;        
    uint32_t axiMemsize_kbytes; 
    uint32_t ipgAddress;        
    uint32_t ipgMemsize_kbytes; 
    semc_rdy_polarity_t rdyactivePolarity;       
    bool edoModeEnabled;                         
    semc_nand_column_bit_num_t columnAddrBitNum; 
    semc_nand_address_option_t arrayAddrOption;  
    sem_nand_burst_len_t burstLen;               
    smec_port_size_t portSize;                   
    semc_nand_timing_config_t *timingConfig;     
} semc_nand_config_t;
 
typedef struct _semc_nor_config
{
    semc_iomux_pin cePinMux;                        
    semc_iomux_nora27_pin addr27;                   
    uint32_t address;                               
    uint32_t memsize_kbytes;                        
    uint8_t addrPortWidth;                          
    semc_rdy_polarity_t rdyactivePolarity;          
    semc_adv_polarity_t advActivePolarity;          
    semc_norsram_column_bit_num_t columnAddrBitNum; 
    semc_addr_mode_t addrMode;                      
    sem_norsram_burst_len_t burstLen;               
    smec_port_size_t portSize;                      
    uint8_t tCeSetup_Ns;                            
    uint8_t tCeHold_Ns;                             
    uint8_t tCeInterval_Ns;                         
    uint8_t tAddrSetup_Ns;                          
    uint8_t tAddrHold_Ns;                           
    uint8_t tWeLow_Ns;                              
    uint8_t tWeHigh_Ns;                             
    uint8_t tReLow_Ns;                              
    uint8_t tReHigh_Ns;                             
    uint8_t tTurnAround_Ns;                         
    uint8_t tAddr2WriteHold_Ns;                     
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME)
    uint8_t tWriteSetup_Ns; 
#endif
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME)
    uint8_t tWriteHold_Ns; 
#endif
#if defined(FSL_FEATURE_SEMC_HAS_NOR_LC_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_LC_TIME)
    uint8_t latencyCount; 
#endif
#if defined(FSL_FEATURE_SEMC_HAS_NOR_RD_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_RD_TIME)
    uint8_t readCycle; 
#endif
#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
    uint8_t delayChain; 
#endif                  /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
} semc_nor_config_t;
 
typedef struct _semc_sram_config
{
    semc_iomux_pin cePinMux;               
    semc_iomux_nora27_pin addr27;          
    uint32_t address;                      
    uint32_t memsize_kbytes;               
    uint8_t addrPortWidth;                 
    semc_adv_polarity_t advActivePolarity; 
    semc_addr_mode_t addrMode;             
    sem_norsram_burst_len_t burstLen;      
    smec_port_size_t portSize;             
#if defined(SEMC_SRAMCR4_SYNCEN_MASK) && (SEMC_SRAMCR4_SYNCEN_MASK)
    semc_sync_mode_t syncMode; 
#endif                         /* SEMC_SRAMCR4_SYNCEN_MASK */
#if defined(SEMC_SRAMCR0_WAITEN_MASK) && (SEMC_SRAMCR0_WAITEN_MASK)
    bool waitEnable; 
#endif               /* SEMC_SRAMCR0_WAITEN_MASK */
#if defined(SEMC_SRAMCR0_WAITSP_MASK) && (SEMC_SRAMCR0_WAITSP_MASK)
    uint8_t waitSample; 
#endif                  /* SEMC_SRAMCR0_WAITSP_MASK */
#if defined(SEMC_SRAMCR4_ADVH_MASK) && (SEMC_SRAMCR4_ADVH_MASK)
    semc_adv_level_control_t advLevelCtrl; 
#endif                                     /* SEMC_SRAMCR4_ADVH_MASK */
    uint8_t tCeSetup_Ns;                   
    uint8_t tCeHold_Ns;                    
    uint8_t tCeInterval_Ns;                
#if defined(FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME)
    uint8_t readHoldTime_Ns;    
#endif                          /* FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME */
    uint8_t tAddrSetup_Ns;      
    uint8_t tAddrHold_Ns;       
    uint8_t tWeLow_Ns;          
    uint8_t tWeHigh_Ns;         
    uint8_t tReLow_Ns;          
    uint8_t tReHigh_Ns;         
    uint8_t tTurnAround_Ns;     
    uint8_t tAddr2WriteHold_Ns; 
#if defined(FSL_FEATURE_SEMC_HAS_SRAM_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_WDS_TIME)
    uint8_t tWriteSetup_Ns; 
#endif
#if defined(FSL_FEATURE_SEMC_HAS_SRAM_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_WDH_TIME)
    uint8_t tWriteHold_Ns; 
#endif
#if defined(FSL_FEATURE_SEMC_HAS_SRAM_LC_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_LC_TIME)
    uint8_t latencyCount; 
#endif
#if defined(FSL_FEATURE_SEMC_HAS_SRAM_RD_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RD_TIME)
    uint8_t readCycle; 
#endif
#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
    uint8_t delayChain; 
#endif                  /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
} semc_sram_config_t;
 
typedef struct _semc_dbi_config
{
    semc_iomux_pin csxPinMux;                   
    uint32_t address;                           
    uint32_t memsize_kbytes;                    
    semc_dbi_column_bit_num_t columnAddrBitNum; 
    sem_dbi_burst_len_t burstLen;               
    smec_port_size_t portSize;                  
    uint8_t tCsxSetup_Ns;                       
    uint8_t tCsxHold_Ns;                        
    uint8_t tWexLow_Ns;                         
    uint8_t tWexHigh_Ns;                        
    uint8_t tRdxLow_Ns;                         
    uint8_t tRdxHigh_Ns;                        
    uint8_t tCsxInterval_Ns;                    
} semc_dbi_config_t;
 
typedef struct _semc_queuea_weight_struct
{
    uint32_t qos : 4;              
    uint32_t aging : 4;            
    uint32_t slaveHitSwith : 8;    
    uint32_t slaveHitNoswitch : 8; 
} semc_queuea_weight_struct_t;
 
typedef union _semc_queuea_weight
{
    semc_queuea_weight_struct_t queueaConfig; 
    uint32_t queueaValue; 
} semc_queuea_weight_t;
 
typedef struct _semc_queueb_weight_struct
{
    uint32_t qos : 4;           
    uint32_t aging : 4;         
    uint32_t slaveHitSwith : 8; 
    uint32_t weightPagehit : 8; 
    uint32_t bankRotation : 8;  
} semc_queueb_weight_struct_t;
 
typedef union _semc_queueb_weight
{
    semc_queueb_weight_struct_t queuebConfig; 
    uint32_t queuebValue; 
} semc_queueb_weight_t;
 
typedef struct _semc_axi_queueweight
{
    bool queueaEnable;                 
    semc_queuea_weight_t queueaWeight; 
    bool queuebEnable;                 
    semc_queueb_weight_t queuebWeight; 
} semc_axi_queueweight_t;
 
typedef struct _semc_config_t
{
    semc_dqs_mode_t dqsMode;            
    uint8_t cmdTimeoutCycles;           
    uint8_t busTimeoutCycles;           
    semc_axi_queueweight_t queueWeight; 
} semc_config_t;
 
/*******************************************************************************
 * API
 ******************************************************************************/
 
#if defined(__cplusplus)
extern "C" {
#endif
 
void SEMC_GetDefaultConfig(semc_config_t *config);
 
void SEMC_Init(SEMC_Type *base, semc_config_t *configure);
 
void SEMC_Deinit(SEMC_Type *base);
 
/* @} */
 
status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz);
 
status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz);
 
status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz);
 
status_t SEMC_ConfigureSRAMWithChipSelection(SEMC_Type *base,
                                             semc_sram_cs_t cs,
                                             semc_sram_config_t *config,
                                             uint32_t clkSrc_Hz);
 
status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz);
 
status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz);
 
/* @} */
 
static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask)
{
    base->INTEN |= mask;
}
 
static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask)
{
    base->INTEN &= ~mask;
}
 
static inline bool SEMC_GetStatusFlag(SEMC_Type *base)
{
    return (base->INTR != 0x00U) ? true : false;
}
 
static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask)
{
    base->INTR |= mask;
}
 
/* @} */
 
static inline bool SEMC_IsInIdle(SEMC_Type *base)
{
    return ((base->STS0 & SEMC_STS0_IDLE_MASK) != 0x00U) ? true : false;
}
 
status_t SEMC_SendIPCommand(
    SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read);
 
static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand,
                                               semc_ipcmd_nand_addrmode_t addrMode,
                                               semc_ipcmd_nand_cmdmode_t cmdMode)
{
    return ((uint16_t)userCommand << 8U) | ((uint16_t)addrMode << 4U) | ((uint16_t)cmdMode & 0x000FU);
}
 
static inline bool SEMC_IsNandReady(SEMC_Type *base)
{
    return ((base->STS0 & SEMC_STS0_NARDY_MASK) != 0x00U) ? true : false;
}
 
status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
 
status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
 
status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
 
status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
 
/* @} */
 
#if defined(__cplusplus)
}
#endif
 
#endif /* _FSL_SEMC_H_*/