fsl_pmu.h

/*
 * Copyright 2020-2021 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _FSL_PMU_H_
#define _FSL_PMU_H_
 
#include "fsl_common.h"
 
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) 
#if defined(ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK)
#define PMU_HAS_FBB (1U)
#else
#define PMU_HAS_FBB (0U)
#endif /* ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK */
 
enum _pmu_setpoint_map
{
    kPMU_SetPoint0  = 1UL << 0UL,  
    kPMU_SetPoint1  = 1UL << 1UL,  
    kPMU_SetPoint2  = 1UL << 2UL,  
    kPMU_SetPoint3  = 1UL << 3UL,  
    kPMU_SetPoint4  = 1UL << 4UL,  
    kPMU_SetPoint5  = 1UL << 5UL,  
    kPMU_SetPoint6  = 1UL << 6UL,  
    kPMU_SetPoint7  = 1UL << 7UL,  
    kPMU_SetPoint8  = 1UL << 8UL,  
    kPMU_SetPoint9  = 1UL << 9UL,  
    kPMU_SetPoint10 = 1UL << 10UL, 
    kPMU_SetPoint11 = 1UL << 11UL, 
    kPMU_SetPoint12 = 1UL << 12UL, 
    kPMU_SetPoint13 = 1UL << 13UL, 
    kPMU_SetPoint14 = 1UL << 14UL, 
    kPMU_SetPoint15 = 1UL << 15UL  
};
 
typedef enum _pmu_ldo_name
{
    kPMU_PllLdo     = 0U, 
    kPMU_LpsrAnaLdo = 1U, 
    kPMU_LpsrDigLdo = 2U, 
    kPMU_SnvsDigLdo = 3U  
} pmu_ldo_name_t;
 
typedef enum _pmu_body_bias_name
{
#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB)
    kPMU_FBB_CM7  = 0x0U, 
    kPMU_RBB_SOC  = 0x1U, 
    kPMU_RBB_LPSR = 0x2U, 
#else
    kPMU_RBB_SOC  = 0x0U, 
    kPMU_RBB_LPSR = 0x1U, 
#endif /* PMU_HAS_FBB */
} pmu_body_bias_name_t;
 
typedef enum _pmu_control_mode
{
    kPMU_StaticMode = 0U, 
    kPMU_GPCMode    = 1U, 
} pmu_control_mode_t;
 
typedef enum _pmu_ldo_operate_mode
{
    kPMU_LowPowerMode  = 0x0U, 
    kPMU_HighPowerMode = 0x1U, 
} pmu_ldo_operate_mode_t;
 
typedef enum _pmu_lpsr_ana_ldo_charge_pump_current
{
    kPMU_LpsrAnaChargePump300nA = 0U, 
    kPMU_LpsrAnaChargePump400nA = 1U, 
    kPMU_LpsrAnaChargePump500nA = 2U, 
    kPMU_LpsrAnaChargePump600nA = 3U, 
} pmu_lpsr_ana_ldo_charge_pump_current_t;
 
typedef enum _pmu_lpsr_ana_ldo_output_range
{
    kPMU_LpsrAnaLdoOutputFrom1P77To1P83 = 0U, 
    kPMU_LpsrAnaLdoOutputFrom1P72To1P77 = 1U, 
    kPMU_LpsrAnaLdoOutputFrom1P82To1P88 = 2U, 
} pmu_lpsr_ana_ldo_output_range_t;
 
typedef enum _pmu_lpsr_dig_voltage_step_time
{
    kPMU_LpsrDigVoltageStepInc15us  = 0x0U, 
    kPMU_LpsrDigVoltageStepInc25us  = 0x1U, 
    kPMU_LpsrDigVoltageStepInc50us  = 0x2U, 
    kPMU_LpsrDigVoltageStepInc100us = 0x3U, 
} pmu_lpsr_dig_voltage_step_time_t;
 
typedef enum _pmu_lpsr_dig_target_output_voltage
{
    kPMU_LpsrDigTargetStableVoltage0P631V = 0x0U,  
    kPMU_LpsrDigTargetStableVoltage0P65V  = 0x1U,  
    kPMU_LpsrDigTargetStableVoltage0P67V  = 0x2U,  
    kPMU_LpsrDigTargetStableVoltage0P689V = 0x3U,  
    kPMU_LpsrDigTargetStableVoltage0P709V = 0x4U,  
    kPMU_LpsrDigTargetStableVoltage0P728V = 0x5U,  
    kPMU_LpsrDigTargetStableVoltage0P748V = 0x6U,  
    kPMU_LpsrDigTargetStableVoltage0P767V = 0x7U,  
    kPMU_LpsrDigTargetStableVoltage0P786V = 0x8U,  
    kPMU_LpsrDigTargetStableVoltage0P806V = 0x9U,  
    kPMU_LpsrDigTargetStableVoltage0P825V = 0xAU,  
    kPMU_LpsrDigTargetStableVoltage0P845V = 0xBU,  
    kPMU_LpsrDigTargetStableVoltage0P864V = 0xCU,  
    kPMU_LpsrDigTargetStableVoltage0P883V = 0xDU,  
    kPMU_LpsrDigTargetStableVoltage0P903V = 0xEU,  
    kPMU_LpsrDigTargetStableVoltage0P922V = 0xFU,  
    kPMU_LpsrDigTargetStableVoltage0P942V = 0x10U, 
    kPMU_LpsrDigTargetStableVoltage0P961V = 0x11U, 
    kPMU_LpsrDigTargetStableVoltage0P981V = 0x12U, 
    kPMU_LpsrDigTargetStableVoltage1P0V   = 0x13U, 
    kPMU_LpsrDigTargetStableVoltage1P019V = 0x14U, 
    kPMU_LpsrDigTargetStableVoltage1P039V = 0x15U, 
    kPMU_LpsrDigTargetStableVoltage1P058V = 0x16U, 
    kPMU_LpsrDigTargetStableVoltage1P078V = 0x17U, 
    kPMU_LpsrDigTargetStableVoltage1P097V = 0x18U, 
    kPMU_LpsrDigTargetStableVoltage1P117V = 0x19U, 
    kPMU_LpsrDigTargetStableVoltage1P136V = 0x1AU, 
    kPMU_LpsrDigTargetStableVoltage1P155V = 0x1BU, 
    kPMU_LpsrDigTargetStableVoltage1P175V = 0x1CU, 
    kPMU_LpsrDigTargetStableVoltage1P194V = 0x1DU, 
    kPMU_LpsrDigTargetStableVoltage1P214V = 0x1EU, 
    kPMU_LpsrDigTargetStableVoltage1P233V = 0x1FU, 
} pmu_lpsr_dig_target_output_voltage_t;
 
typedef enum _pmu_snvs_dig_charge_pump_current
{
    kPMU_SnvsDigChargePump12P5nA  = 0U, 
    kPMU_SnvsDigChargePump6P25nA  = 1U, 
    kPMU_SnvsDigChargePump18P75nA = 2U, 
} pmu_snvs_dig_charge_pump_current_t;
 
typedef enum _pmu_snvs_dig_discharge_resistor_value
{
    kPMU_SnvsDigDischargeResistor15K = 0U, 
    kPMU_SnvsDigDischargeResistor30K = 1U, 
    kPMU_SnvsDigDischargeResistor9K  = 2U, 
} pmu_snvs_dig_discharge_resistor_value_t;
 
enum _pmu_static_bandgap_power_down_option
{
    kPMU_PowerDownBandgapFully               = 1U << 0U, 
    kPMU_PowerDownVoltageReferenceOutputOnly = 1U << 1U, 
    kPMU_PowerDownBandgapVBGUPDetector = 1U << 2U,       
};
 
typedef enum _pmu_bandgap_output_VBG_voltage_value
{
    kPMU_BandgapOutputVBGVoltageNominal   = 0x0U, 
    kPMU_BandgapOutputVBGVoltagePlus10mV  = 0x1U, 
    kPMU_BandgapOutputVBGVoltagePlus20mV  = 0x2U, 
    kPMU_BandgapOutputVBGVoltagePlus30mV  = 0x3U, 
    kPMU_BandgapOutputVBGVoltageMinus10mV = 0x4U, 
    kPMU_BandgapOutputVBGVoltageMinus20mV = 0x5U, 
    kPMU_BandgapOutputVBGVoltageMinus30mV = 0x6U, 
    kPMU_BandgapOutputVBGVoltageMinus40mV = 0x7U, 
} pmu_bandgap_output_VBG_voltage_value_t;
 
typedef enum _pmu_bandgap_output_current_value
{
    kPMU_OutputCurrent11P5uA = 0x0U, 
    kPMU_OutputCurrent11P8uA = 0x1U, 
    kPMU_OutputCurrent12P1uA = 0x2U, 
    kPMU_OutputCurrent12P4uA = 0x4U, 
    kPMU_OutputCurrent12P7uA = 0x5U, 
    kPMU_OutputCurrent13P0uA = 0x6U, 
    kPMU_OutputCurrent13P3uA = 0x7U, 
} pmu_bandgap_output_current_value_t;
 
typedef enum _pmu_well_bias_power_source
{
    kPMU_WellBiasPowerFromLpsrDigLdo = 0U, 
    kPMU_WellBiasPowerFromDCDC,            
} pmu_well_bias_power_source_t;
 
typedef enum _pmu_bias_area_size
{
    kPMU_180uA_6mm2At125C = 0U, 
    kPMU_150uA_5mm2At125C,      
    kPMU_120uA_4mm2At125C,      
    kPMU_90uA_3mm2At125C,       
    kPMU_60uA_2mm2At125C,       
    kPMU_45uA_1P5mm2At125C,     
    kPMU_30uA_1mm2At125C,       
    kPMU_15uA_0P5mm2At125C,     
} pmu_bias_area_size_t;
 
typedef enum _pmu_well_bias_typical_freq
{
    kPMU_OscFreqDiv128 = 0U, 
    kPMU_OscFreqDiv64  = 1U, 
    kPMU_OscFreqDiv32  = 2U, 
    kPMU_OscFreqDiv16  = 3U, 
    kPMU_OscFreqDiv8   = 4U, 
    kPMU_OscFreqDiv2   = 6U, 
    kPMU_OscFreq       = 7U, 
} pmu_well_bias_typical_freq_t;
 
typedef enum _pmu_adaptive_clock_source
{
    kPMU_AdaptiveClkSourceOscClk = 0U,   
    kPMU_AdaptiveClkSourceChargePumpClk, 
} pmu_adaptive_clock_source_t;
 
typedef enum _pmu_freq_reduction
{
    kPMU_FreqReductionNone = 0U, 
    kPMU_FreqReduction30PCT,     
    kPMU_FreqReduction40PCT,     
    kPMU_FreqReduction50PCT,     
} pmu_freq_reduction_t;
 
typedef enum _pmu_well_bias_1P8_adjustment
{
    kPMU_Cref0fFCspl0fFDeltaC0fF = 0U, 
    kPMU_Cref0fFCspl30fFDeltaCN30fF,   
    kPMU_Cref0fFCspl43fFDeltaCN43fF,   
    kPMU_Cref0fFCspl62fFDeltaCN62fF,   
    kPMU_Cref0fFCspl105fFDeltaCN105fF, 
    kPMU_Cref30fFCspl0fFDeltaC30fF,    
    kPMU_Cref30fFCspl43fFDeltaCN12fF,  
    kPMU_Cref30fFCspl105fFDeltaCN75fF, 
    kPMU_Cref43fFCspl0fFDeltaC43fF,    
    kPMU_Cref43fFCspl30fFDeltaC13fF,   
    kPMU_Cref43fFCspl62fFDeltaCN19fF,  
    kPMU_Cref62fFCspl0fFDeltaC62fF,    
    kPMU_Cref62fFCspl43fFDeltaC19fF,   
    kPMU_Cref105fFCspl0fFDeltaC105fF,  
    kPMU_Cref105fFCspl30fFDeltaC75fF,  
} pmu_well_bias_1P8_adjustment_t;
 
typedef struct _pmu_static_lpsr_ana_ldo_config
{
    pmu_ldo_operate_mode_t mode; 
    bool enable2mALoad;          
    bool enable4mALoad;          
    bool enable20uALoad;         
    bool enableStandbyMode;      
} pmu_static_lpsr_ana_ldo_config_t;
 
typedef struct _pmu_static_lpsr_dig_config
{
    bool enableStableDetect;                            
    pmu_lpsr_dig_voltage_step_time_t voltageStepTime;   
    pmu_lpsr_dig_target_output_voltage_t targetVoltage; 
} pmu_static_lpsr_dig_config_t;
 
typedef struct _pmu_snvs_dig_config
{
    pmu_ldo_operate_mode_t mode;                          
    pmu_snvs_dig_charge_pump_current_t chargePumpCurrent; 
    pmu_snvs_dig_discharge_resistor_value_t dischargeResistorValue; 
    uint8_t trimValue;                                              
    bool enablePullDown;                                            
    bool enableLdoStable;                                           
} pmu_snvs_dig_config_t;
 
typedef struct _pmu_static_bandgap_config
{
    uint8_t powerDownOption; 
    bool enableLowPowerMode; 
    pmu_bandgap_output_VBG_voltage_value_t outputVoltage; 
    pmu_bandgap_output_current_value_t outputCurrent;     
} pmu_static_bandgap_config_t;
 
typedef union _pmu_well_bias_option
{
    uint16_t wellBiasData; 
    struct
    {
        uint16_t enablePWellOnly : 1U;     
        uint16_t reserved1 : 1U;           
        uint16_t biasAreaSize : 3U;        
        uint16_t disableAdaptiveFreq : 1U; 
        uint16_t wellBiasFreq : 3U;        
        uint16_t clkSource : 1U;     
        uint16_t freqReduction : 2U; 
        uint16_t enablePowerDownOption : 1U; 
        uint16_t reserved2 : 1U;             
        uint16_t powerSource : 1U; 
        uint16_t reserved3 : 1U;   
    } wellBiasStruct;
} pmu_well_bias_option_t;
 
typedef struct _pmu_well_bias_config
{
    pmu_well_bias_option_t wellBiasOption;     
    pmu_well_bias_1P8_adjustment_t adjustment; 
} pmu_well_bias_config_t;
 
typedef struct _pmu_gpc_body_bias_config
{
    uint8_t PWELLRegulatorSize; 
    uint8_t NWELLRegulatorSize; 
    uint8_t oscillatorSize;     
    uint8_t regulatorStrength;  
} pmu_gpc_body_bias_config_t;
 
/*******************************************************************************
 * API
 ******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
 
void PMU_SetPllLdoControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode);
 
void PMU_SwitchPllLdoToGPCMode(ANADIG_PMU_Type *base);
 
void PMU_StaticEnablePllLdo(ANADIG_PMU_Type *base);
 
void PMU_StaticDisablePllLdo(void);
 
void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode);
 
void PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable);
 
static inline bool PMU_StaticCheckLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base)
{
    return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) != 0UL);
}
 
void PMU_StaticGetLpsrAnaLdoDefaultConfig(pmu_static_lpsr_ana_ldo_config_t *config);
 
void PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_ana_ldo_config_t *config);
 
void PMU_StaticLpsrAnaLdoDeinit(ANADIG_LDO_SNVS_Type *base);
 
void PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode);
 
void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable);
 
static inline bool PMU_StaticCheckLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base)
{
    return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) != 0UL);
}
 
void PMU_StaticGetLpsrDigLdoDefaultConfig(pmu_static_lpsr_dig_config_t *config);
 
void PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_dig_config_t *config);
 
void PMU_StaticLpsrDigLdoDeinit(ANADIG_LDO_SNVS_Type *base);
 
void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target_output_voltage_t voltageValue);
 
void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config);
 
void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, pmu_ldo_operate_mode_t mode);
 
static inline void PMU_SnvsDigLdoDeinit(ANADIG_LDO_SNVS_DIG_Type *base)
{
    base->PMU_LDO_SNVS_DIG &= ~ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK;
}
 
void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap);
 
void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo_operate_mode_t mode);
 
void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap);
 
void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap);
 
void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap);
 
void PMU_SetBandgapControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode);
 
void PMU_SwitchBandgapToGPCMode(ANADIG_PMU_Type *base);
 
void PMU_DisableBandgapSelfBiasAfterPowerUp(void);
 
void PMU_EnableBandgapSelfBiasBeforePowerDown(void);
 
void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config);
 
static inline void PMU_GPCEnableBandgap(ANADIG_PMU_Type *base, uint32_t setpointMap)
{
    base->BANDGAP_ENABLE_SP = ~setpointMap;
}
 
static inline void PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type *base, uint32_t setpointMap)
{
    base->BANDGAP_STBY_EN_SP = setpointMap;
}
 
void PMU_WellBiasInit(ANADIG_PMU_Type *base, const pmu_well_bias_config_t *config);
 
void PMU_GetWellBiasDefaultConfig(pmu_well_bias_config_t *config);
 
void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, pmu_control_mode_t mode);
 
void PMU_EnableBodyBias(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, bool enable);
 
void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap);
 
void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap);
 
void PMU_GPCGetBodyBiasDefaultConfig(pmu_gpc_body_bias_config_t *config);
 
void PMU_GPCSetBodyBiasConfig(pmu_body_bias_name_t name, const pmu_gpc_body_bias_config_t *config);
 
#if defined(__cplusplus)
}
#endif
#endif /* _FSL_PMU_H_ */