fsl_mipi_csi2rx.h

/*
 * Copyright 2017, 2019-2020 NXP
 * All rights reserved.
 *
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _FSL_MIPI_CSI2RX_H_
#define _FSL_MIPI_CSI2RX_H_
 
#include "fsl_common.h"
 
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
#define FSL_CSI2RX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
#if (defined(FSL_FEATURE_CSI2RX_HAS_NO_REG_PREFIX) && FSL_FEATURE_CSI2RX_HAS_NO_REG_PREFIX)
 
#define CSI2RX_REG_CFG_NUM_LANES(base)             (base)->CFG_NUM_LANES
#define CSI2RX_REG_CFG_DISABLE_DATA_LANES(base)    (base)->CFG_DISABLE_DATA_LANES
#define CSI2RX_REG_BIT_ERR(base)                   (base)->BIT_ERR
#define CSI2RX_REG_IRQ_STATUS(base)                (base)->IRQ_STATUS
#define CSI2RX_REG_IRQ_MASK(base)                  (base)->IRQ_MASK
#define CSI2RX_REG_ULPS_STATUS(base)               (base)->ULPS_STATUS
#define CSI2RX_REG_PPI_ERRSOT_HS(base)             (base)->PPI_ERRSOT_HS
#define CSI2RX_REG_PPI_ERRSOTSYNC_HS(base)         (base)->PPI_ERRSOTSYNC_HS
#define CSI2RX_REG_PPI_ERRESC(base)                (base)->PPI_ERRESC
#define CSI2RX_REG_PPI_ERRSYNCESC(base)            (base)->PPI_ERRSYNCESC
#define CSI2RX_REG_PPI_ERRCONTROL(base)            (base)->PPI_ERRCONTROL
#define CSI2RX_REG_CFG_DISABLE_PAYLOAD_0(base)     (base)->CFG_DISABLE_PAYLOAD_0
#define CSI2RX_REG_CFG_DISABLE_PAYLOAD_1(base)     (base)->CFG_DISABLE_PAYLOAD_1
#define CSI2RX_REG_CFG_IGNORE_VC(base)             (base)->CFG_IGNORE_VC
#define CSI2RX_REG_CFG_VID_VC(base)                (base)->CFG_VID_VC
#define CSI2RX_REG_CFG_VID_P_FIFO_SEND_LEVEL(base) (base)->CFG_VID_P_FIFO_SEND_LEVEL
#define CSI2RX_REG_CFG_VID_VSYNC(base)             (base)->CFG_VID_VSYNC
#define CSI2RX_REG_CFG_VID_HSYNC_FP(base)          (base)->CFG_VID_HSYNC_FP
#define CSI2RX_REG_CFG_VID_HSYNC(base)             (base)->CFG_VID_HSYNC
#define CSI2RX_REG_CFG_VID_HSYNC_BP(base)          (base)->CFG_VID_HSYNC_BP
 
#else
 
#define CSI2RX_REG_CFG_NUM_LANES(base)             (base)->CSI2RX_CFG_NUM_LANES
#define CSI2RX_REG_CFG_DISABLE_DATA_LANES(base)    (base)->CSI2RX_CFG_DISABLE_DATA_LANES
#define CSI2RX_REG_BIT_ERR(base)                   (base)->CSI2RX_BIT_ERR
#define CSI2RX_REG_IRQ_STATUS(base)                (base)->CSI2RX_IRQ_STATUS
#define CSI2RX_REG_IRQ_MASK(base)                  (base)->CSI2RX_IRQ_MASK
#define CSI2RX_REG_ULPS_STATUS(base)               (base)->CSI2RX_ULPS_STATUS
#define CSI2RX_REG_PPI_ERRSOT_HS(base)             (base)->CSI2RX_PPI_ERRSOT_HS
#define CSI2RX_REG_PPI_ERRSOTSYNC_HS(base)         (base)->CSI2RX_PPI_ERRSOTSYNC_HS
#define CSI2RX_REG_PPI_ERRESC(base)                (base)->CSI2RX_PPI_ERRESC
#define CSI2RX_REG_PPI_ERRSYNCESC(base)            (base)->CSI2RX_PPI_ERRSYNCESC
#define CSI2RX_REG_PPI_ERRCONTROL(base)            (base)->CSI2RX_PPI_ERRCONTROL
#define CSI2RX_REG_CFG_DISABLE_PAYLOAD_0(base)     (base)->CSI2RX_CFG_DISABLE_PAYLOAD_0
#define CSI2RX_REG_CFG_DISABLE_PAYLOAD_1(base)     (base)->CSI2RX_CFG_DISABLE_PAYLOAD_1
#define CSI2RX_REG_CFG_IGNORE_VC(base)             (base)->CSI2RX_CFG_IGNORE_VC
#define CSI2RX_REG_CFG_VID_VC(base)                (base)->CSI2RX_CFG_VID_VC
#define CSI2RX_REG_CFG_VID_P_FIFO_SEND_LEVEL(base) (base)->CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL
#define CSI2RX_REG_CFG_VID_VSYNC(base)             (base)->CSI2RX_CFG_VID_VSYNC
#define CSI2RX_REG_CFG_VID_HSYNC_FP(base)          (base)->CSI2RX_CFG_VID_HSYNC_FP
#define CSI2RX_REG_CFG_VID_HSYNC(base)             (base)->CSI2RX_CFG_VID_HSYNC
#define CSI2RX_REG_CFG_VID_HSYNC_BP(base)          (base)->CSI2RX_CFG_VID_HSYNC_BP
 
#endif
 
#ifndef MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK
#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK
#endif
 
#ifndef MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK
#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK
#endif
 
enum _csi2rx_data_lane
{
    kCSI2RX_DataLane0 = (1U << 0U), 
    kCSI2RX_DataLane1 = (1U << 1U), 
    kCSI2RX_DataLane2 = (1U << 2U), 
    kCSI2RX_DataLane3 = (1U << 3U)  
};
 
enum _csi2rx_payload
{
    kCSI2RX_PayloadGroup0Null         = (1U << 0U),  
    kCSI2RX_PayloadGroup0Blank        = (1U << 1U),  
    kCSI2RX_PayloadGroup0Embedded     = (1U << 2U),  
    kCSI2RX_PayloadGroup0YUV420_8Bit  = (1U << 10U), 
    kCSI2RX_PayloadGroup0YUV422_8Bit  = (1U << 14U), 
    kCSI2RX_PayloadGroup0YUV422_10Bit = (1U << 15U), 
    kCSI2RX_PayloadGroup0RGB444       = (1U << 16U), 
    kCSI2RX_PayloadGroup0RGB555       = (1U << 17U), 
    kCSI2RX_PayloadGroup0RGB565       = (1U << 18U), 
    kCSI2RX_PayloadGroup0RGB666       = (1U << 19U), 
    kCSI2RX_PayloadGroup0RGB888       = (1U << 20U), 
    kCSI2RX_PayloadGroup0Raw6         = (1U << 24U), 
    kCSI2RX_PayloadGroup0Raw7         = (1U << 25U), 
    kCSI2RX_PayloadGroup0Raw8         = (1U << 26U), 
    kCSI2RX_PayloadGroup0Raw10        = (1U << 27U), 
    kCSI2RX_PayloadGroup0Raw12        = (1U << 28U), 
    kCSI2RX_PayloadGroup0Raw14        = (1U << 29U), 
    kCSI2RX_PayloadGroup1UserDefined1 = (1U << 0U),  
    kCSI2RX_PayloadGroup1UserDefined2 = (1U << 1U),  
    kCSI2RX_PayloadGroup1UserDefined3 = (1U << 2U),  
    kCSI2RX_PayloadGroup1UserDefined4 = (1U << 3U),  
    kCSI2RX_PayloadGroup1UserDefined5 = (1U << 4U),  
    kCSI2RX_PayloadGroup1UserDefined6 = (1U << 5U),  
    kCSI2RX_PayloadGroup1UserDefined7 = (1U << 6U),  
    kCSI2RX_PayloadGroup1UserDefined8 = (1U << 7U)   
};
 
typedef struct _csi2rx_config
{
    uint8_t laneNum;          
    uint8_t tHsSettle_EscClk; 
} csi2rx_config_t;
 
enum _csi2rx_bit_error
{
    kCSI2RX_BitErrorEccTwoBit = (1U << 0U), 
    kCSI2RX_BitErrorEccOneBit = (1U << 1U)  
};
 
typedef enum _csi2rx_ppi_error
{
    kCSI2RX_PpiErrorSotHs,     
    kCSI2RX_PpiErrorSotSyncHs, 
    kCSI2RX_PpiErrorEsc,       
    kCSI2RX_PpiErrorSyncEsc,   
    kCSI2RX_PpiErrorControl,   
} csi2rx_ppi_error_t;
 
enum _csi2rx_interrupt
{
    kCSI2RX_InterruptCrcError         = (1U << 0U), /* CRC error. */
    kCSI2RX_InterruptEccOneBitError   = (1U << 1U), /* One bit ECC error. */
    kCSI2RX_InterruptEccTwoBitError   = (1U << 2U), /* One bit ECC error. */
    kCSI2RX_InterruptUlpsStatusChange = (1U << 3U), /* ULPS status changed. */
    kCSI2RX_InterruptErrorSotHs       = (1U << 4U), /* D-PHY ErrSotHS occurred. */
    kCSI2RX_InterruptErrorSotSyncHs   = (1U << 5U), /* D-PHY ErrSotSync_HS occurred. */
    kCSI2RX_InterruptErrorEsc         = (1U << 6U), /* D-PHY ErrEsc occurred. */
    kCSI2RX_InterruptErrorSyncEsc     = (1U << 7U), /* D-PHY ErrSyncEsc occurred. */
    kCSI2RX_InterruptErrorControl     = (1U << 8U), /* D-PHY ErrControl occurred. */
};
 
enum _csi2rx_ulps_status
{
    kCSI2RX_ClockLaneUlps = (1U << 0U), 
    kCSI2RX_DataLane0Ulps = (1U << 1U), 
    kCSI2RX_DataLane1Ulps = (1U << 2U), 
    kCSI2RX_DataLane2Ulps = (1U << 3U), 
    kCSI2RX_DataLane3Ulps = (1U << 4U), 
    kCSI2RX_ClockLaneMark = (1U << 5U), 
    kCSI2RX_DataLane0Mark = (1U << 6U), 
    kCSI2RX_DataLane1Mark = (1U << 7U), 
    kCSI2RX_DataLane2Mark = (1U << 8U), 
    kCSI2RX_DataLane3Mark = (1U << 9U), 
};
 
/*******************************************************************************
 * API
 ******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
 
void CSI2RX_Init(MIPI_CSI2RX_Type *base, const csi2rx_config_t *config);
 
void CSI2RX_Deinit(MIPI_CSI2RX_Type *base);
 
static inline uint32_t CSI2RX_GetBitError(MIPI_CSI2RX_Type *base)
{
    return CSI2RX_REG_BIT_ERR(base);
}
 
static inline uint32_t CSI2RX_GetEccBitErrorPosition(uint32_t bitError)
{
    return (bitError >> 2U) & 0x1FU;
}
 
static inline uint32_t CSI2RX_GetUlpsStatus(MIPI_CSI2RX_Type *base)
{
    return CSI2RX_REG_ULPS_STATUS(base);
}
 
static inline uint32_t CSI2RX_GetPpiErrorDataLanes(MIPI_CSI2RX_Type *base, csi2rx_ppi_error_t errorType)
{
    uint32_t errorLanes;
 
    if (kCSI2RX_PpiErrorSotHs == errorType)
    {
        errorLanes = CSI2RX_REG_PPI_ERRSOT_HS(base);
    }
    else if (kCSI2RX_PpiErrorSotSyncHs == errorType)
    {
        errorLanes = CSI2RX_REG_PPI_ERRSOTSYNC_HS(base);
    }
    else if (kCSI2RX_PpiErrorEsc == errorType)
    {
        errorLanes = CSI2RX_REG_PPI_ERRESC(base);
    }
    else if (kCSI2RX_PpiErrorSyncEsc == errorType)
    {
        errorLanes = CSI2RX_REG_PPI_ERRSYNCESC(base);
    }
    else
    {
        errorLanes = CSI2RX_REG_PPI_ERRCONTROL(base);
    }
 
    return errorLanes;
}
 
static inline void CSI2RX_EnableInterrupts(MIPI_CSI2RX_Type *base, uint32_t mask)
{
    CSI2RX_REG_IRQ_MASK(base) &= ~mask;
}
 
static inline void CSI2RX_DisableInterrupts(MIPI_CSI2RX_Type *base, uint32_t mask)
{
    CSI2RX_REG_IRQ_MASK(base) |= mask;
}
 
static inline uint32_t CSI2RX_GetInterruptStatus(MIPI_CSI2RX_Type *base)
{
    return CSI2RX_REG_IRQ_STATUS(base);
}
 
#if defined(__cplusplus)
}
#endif
 
#endif /* _FSL_MIPI_CSI2RX_H_ */