25#if defined ( __ICCARM__ )
26 #pragma system_include
27#elif defined (__clang__)
28 #pragma clang system_header
31#ifndef ARM_CACHEL1_ARMV7_H
32#define ARM_CACHEL1_ARMV7_H
42#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
43#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
45#ifndef __SCB_DCACHE_LINE_SIZE
46#define __SCB_DCACHE_LINE_SIZE 32U
49#ifndef __SCB_ICACHE_LINE_SIZE
50#define __SCB_ICACHE_LINE_SIZE 32U
59 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
80 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
97 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
117 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
120 uint32_t op_addr = (uint32_t)addr ;
125 SCB->ICIMVAU = op_addr;
128 }
while ( op_size > 0 );
143 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
153 ccsidr =
SCB->CCSIDR;
156 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
158 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
162 #if defined ( __CC_ARM )
163 __schedule_barrier();
165 }
while (ways-- != 0U);
166 }
while(sets-- != 0U);
183 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
189 #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__))
200 #if !defined(__OPTIMIZE__)
213 #if defined(__ICCARM__)
215 SCB->DCCIMVAC = (uint32_t)&locals.sets;
216 SCB->DCCIMVAC = (uint32_t)&locals.ways;
217 SCB->DCCIMVAC = (uint32_t)&locals.ccsidr;
219 SCB->DCCIMVAC = (uint32_t)&locals;
225 locals.ccsidr =
SCB->CCSIDR;
227 locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr));
229 locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr));
233 #if defined ( __CC_ARM )
234 __schedule_barrier();
236 }
while (locals.ways-- != 0U);
237 }
while(locals.sets-- != 0U);
251 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
259 ccsidr =
SCB->CCSIDR;
262 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
264 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
268 #if defined ( __CC_ARM )
269 __schedule_barrier();
271 }
while (ways-- != 0U);
272 }
while(sets-- != 0U);
286 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
294 ccsidr =
SCB->CCSIDR;
297 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
299 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
303 #if defined ( __CC_ARM )
304 __schedule_barrier();
306 }
while (ways-- != 0U);
307 }
while(sets-- != 0U);
321 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
329 ccsidr =
SCB->CCSIDR;
332 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
334 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
338 #if defined ( __CC_ARM )
339 __schedule_barrier();
341 }
while (ways-- != 0U);
342 }
while(sets-- != 0U);
360 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
363 uint32_t op_addr = (uint32_t)addr ;
368 SCB->DCIMVAC = op_addr;
371 }
while ( op_size > 0 );
390 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
393 uint32_t op_addr = (uint32_t)addr ;
398 SCB->DCCMVAC = op_addr;
401 }
while ( op_size > 0 );
420 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
423 uint32_t op_addr = (uint32_t)addr ;
428 SCB->DCCIMVAC = op_addr;
431 }
while ( op_size > 0 );
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr(volatile void *addr, int32_t dsize)
D-Cache Invalidate by address.
Definition: cachel1_armv7.h:358
__STATIC_FORCEINLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition: cachel1_armv7.h:141
__STATIC_FORCEINLINE void SCB_DisableICache(void)
Disable I-Cache.
Definition: cachel1_armv7.h:78
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
Definition: cachel1_armv7.h:319
__STATIC_FORCEINLINE void SCB_InvalidateICache(void)
Invalidate I-Cache.
Definition: cachel1_armv7.h:95
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr(volatile void *addr, int32_t dsize)
D-Cache Clean and Invalidate by address.
Definition: cachel1_armv7.h:418
#define __SCB_DCACHE_LINE_SIZE
Definition: cachel1_armv7.h:46
__STATIC_FORCEINLINE void SCB_EnableICache(void)
Enable I-Cache.
Definition: cachel1_armv7.h:57
__STATIC_FORCEINLINE void SCB_InvalidateDCache(void)
Invalidate D-Cache.
Definition: cachel1_armv7.h:249
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr(volatile void *addr, int32_t dsize)
D-Cache Clean by address.
Definition: cachel1_armv7.h:388
#define __SCB_ICACHE_LINE_SIZE
Definition: cachel1_armv7.h:50
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr(volatile void *addr, int32_t isize)
I-Cache Invalidate by address.
Definition: cachel1_armv7.h:115
__STATIC_FORCEINLINE void SCB_CleanDCache(void)
Clean D-Cache.
Definition: cachel1_armv7.h:284
__STATIC_FORCEINLINE void SCB_DisableDCache(void)
Disable D-Cache.
Definition: cachel1_armv7.h:181
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:286
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:275
#define SCB_DCCISW_SET_Pos
Definition: core_cm7.h:851
#define SCB_CCR_DC_Msk
Definition: core_cm7.h:618
#define SCB_DCCSW_SET_Msk
Definition: core_cm7.h:845
#define SCB_DCCSW_WAY_Pos
Definition: core_cm7.h:841
#define SCB_DCCSW_WAY_Msk
Definition: core_cm7.h:842
#define SCB_DCISW_WAY_Pos
Definition: core_cm7.h:834
#define SCB_DCCISW_WAY_Pos
Definition: core_cm7.h:848
#define SCB_DCISW_SET_Msk
Definition: core_cm7.h:838
#define SCB_DCISW_WAY_Msk
Definition: core_cm7.h:835
#define SCB_DCCSW_SET_Pos
Definition: core_cm7.h:844
#define SCB_DCISW_SET_Pos
Definition: core_cm7.h:837
#define SCB_DCCISW_SET_Msk
Definition: core_cm7.h:852
#define SCB_DCCISW_WAY_Msk
Definition: core_cm7.h:849
#define SCB_CCR_IC_Msk
Definition: core_cm7.h:615
#define SCB
Definition: core_cm4.h:1572