RTEMS 6.1-rc2
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at91rm9200_pmc.h
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1
9/*
10 * AT91RM9200 Power Management and Clock definitions
11 *
12 * Copyright (c) 2002 by Cogent Computer Systems
13 * Written by Mike Kelly <mike@cogcomp.com>
14 *
15 * The license and distribution terms for this file may be
16 * found in the file LICENSE in this distribution or at
17 * http://www.rtems.org/license/LICENSE.
18 */
19#ifndef __AT91RM9200_PMC_H__
20#define __AT91RM9200_PMC_H__
21
22#include <bits.h>
23
24/***********************************************************************
25 * Power Management and Clock Control Register Offsets
26 ***********************************************************************/
27int at91rm9200_get_mainclk(void);
28int at91rm9200_get_slck(void);
29int at91rm9200_get_mck(void);
30
31
32#define PMC_SCER 0x00 /* System Clock Enable Register */
33#define PMC_SCDR 0x04 /* System Clock Disable Register */
34#define PMC_SCSR 0x08 /* System Clock Status Register */
35#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */
36#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
37#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */
38#define PMC_MOR 0x20 /* Main Oscillator Register */
39#define PMC_MCFR 0x24 /* Main Clock Frequency Register */
40#define PMC_PLLAR 0x28 /* PLL A Register */
41#define PMC_PLLBR 0x2C /* PLL B Register */
42#define PMC_MCKR 0x30 /* Master Clock Register */
43#define PMC_PCKR0 0x40 /* Programmable Clock Register 0 */
44#define PMC_PCKR1 0x44 /* Programmable Clock Register 1 */
45#define PMC_PCKR2 0x48 /* Programmable Clock Register 2 */
46#define PMC_PCKR3 0x4C /* Programmable Clock Register 3 */
47#define PMC_PCKR4 0x50 /* Programmable Clock Register 4 */
48#define PMC_PCKR5 0x54 /* Programmable Clock Register 5 */
49#define PMC_PCKR6 0x58 /* Programmable Clock Register 6 */
50#define PMC_PCKR7 0x5C /* Programmable Clock Register 7 */
51#define PMC_IER 0x60 /* Interrupt Enable Register */
52#define PMC_IDR 0x64 /* Interrupt Disable Register */
53#define PMC_SR 0x68 /* Status Register */
54#define PMC_IMR 0x6C /* Interrupt Mask Register */
55
56/* Bit Defines */
57
58/* PMC_SCDR - System Clock Disable Register */
59/* PMC_SCSR - System Clock Status Register */
60/* PMC_SCER - System Clock Enable Register */
61#define PMC_SCR_PCK7 BIT15
62#define PMC_SCR_PCK6 BIT14
63#define PMC_SCR_PCK5 BIT13
64#define PMC_SCR_PCK4 BIT12
65#define PMC_SCR_PCK3 BIT11
66#define PMC_SCR_PCK2 BIT10
67#define PMC_SCR_PCK1 BIT9
68#define PMC_SCR_PCK0 BIT8
69#define PMC_SCR_UHP BIT4
70#define PMC_SCR_MCKUDP BIT2
71#define PMC_SCR_UDP BIT1
72#define PMC_SCR_PCK BIT0
73
74/* PMC_PCER - Peripheral Clock Enable Register */
75/* PMC_PCDR - Peripheral Clock Disable Register */
76/* PMC_PCSR - Peripheral Clock Status Register */
77#define PMC_PCR_PID_EMAC BIT24 /* Ethernet Peripheral Clock */
78#define PMC_PCR_PID_UHP BIT23 /* USB Host Ports Peripheral Clock */
79#define PMC_PCR_PID_TC5 BIT22 /* Timer/Counter 5 Peripheral Clock */
80#define PMC_PCR_PID_TC4 BIT21 /* Timer/Counter 4 Peripheral Clock */
81#define PMC_PCR_PID_TC3 BIT20 /* Timer/Counter 3 Peripheral Clock */
82#define PMC_PCR_PID_TC2 BIT19 /* Timer/Counter 2 Peripheral Clock */
83#define PMC_PCR_PID_TC1 BIT18 /* Timer/Counter 1 Peripheral Clock */
84#define PMC_PCR_PID_TC0 BIT17 /* Timer/Counter 0 Peripheral Clock */
85#define PMC_PCR_PID_SSC2 BIT16 /* Synchronous Serial 2 Peripheral Clock */
86#define PMC_PCR_PID_SSC1 BIT15 /* Synchronous Serial 1 Peripheral Clock */
87#define PMC_PCR_PID_SSC0 BIT14 /* Synchronous Serial 0 Peripheral Clock */
88#define PMC_PCR_PID_SPI BIT13 /* Serial Peripheral Interface Peripheral Clock */
89#define PMC_PCR_PID_TWI BIT12 /* Two-Wire Interface Peripheral Clock */
90#define PMC_PCR_PID_UDP BIT11 /* USB Device Port Peripheral Clock */
91#define PMC_PCR_PID_MCI BIT10 /* MMC/SD Card Peripheral Clock */
92#define PMC_PCR_PID_US3 BIT9 /* USART 3 Peripheral Clock */
93#define PMC_PCR_PID_US2 BIT8 /* USART 2 Peripheral Clock */
94#define PMC_PCR_PID_US1 BIT7 /* USART 1 Peripheral Clock */
95#define PMC_PCR_PID_US0 BIT6 /* USART 0 Peripheral Clock */
96#define PMC_PCR_PID_PIOD BIT5 /* Parallel I/O D Peripheral Clock */
97#define PMC_PCR_PID_PIOC BIT4 /* Parallel I/O C Peripheral Clock */
98#define PMC_PCR_PID_PIOB BIT3 /* Parallel I/O B Peripheral Clock */
99#define PMC_PCR_PID_PIOA BIT2 /* Parallel I/O A Peripheral Clock */
100
101/* PMC_MOR - Main Oscillator Register */
102#define PMC_MOR_MOSCEN BIT0
103
104/* PMC_MCFR - Main Clock Frequency Register */
105#define PMC_MCFR_MAINRDY BIT16
106
107/* PMC_PLLAR - PLL A Register */
108#define PMC_PLLAR_MUST_SET BIT29 /* This bit must be set according to the docs */
109#define PMC_PLLAR_MUL(_x_) ((_x_ & 0x7ff) << 16) /* Multiplier */
110#define PMC_PLLAR_MUL_MASK (0x7ff << 16) /* Multiplier mask */
111
112#define PMC_PLLAR_OUT_80_160 (0 << 14) /* select when PLL frequency is 80-160 Mhz */
113#define PMC_PLLAR_OUT_150_240 (2 << 14) /* select when PLL frequency is 150-240 Mhz */
114#define PMC_PLLAR_DIV(_x_) ((_x_ & 0xff) << 0) /* Divider */
115#define PMC_PLLAR_DIV_MASK (0xff) /* Divider mask */
116
117/* PMC_PLLBR - PLL B Register */
118#define PMC_PLLBR_USB_96M BIT28 /* Set when PLL is 96Mhz to divide it by 2 for USB */
119#define PMC_PLLBR_MUL(_x_) ((_x_ & 0x7ff) << 16) /* Multiplier */
120#define PMC_PLLBR_MUL_MASK (0x7ff << 16) /* Multiplier mask */
121#define PMC_PLLBR_OUT_80_160 (0 << 14) /* select when PLL frequency is 80-160 Mhz */
122#define PMC_PLLBR_OUT_150_240 (2 << 14) /* select when PLL frequency is 150-240 Mhz */
123#define PMC_PLLBR_DIV(_x_) ((_x_ & 0xff) << 0) /* Divider */
124#define PMC_PLLBR_DIV_MASK (0xff) /* Divider mask */
125
126/* PMC_MCKR - Master Clock Register */
127#define PMC_MCKR_MDIV_MASK (3 << 8) /* for masking out the MDIV field */
128#define PMC_MCKR_MDIV_1 (0 << 8) /* MCK = Core/1 */
129#define PMC_MCKR_MDIV_2 (1 << 8) /* MCK = Core/2 */
130#define PMC_MCKR_MDIV_3 (2 << 8) /* MCK = Core/3 */
131#define PMC_MCKR_MDIV_4 (3 << 8) /* MCK = Core/4 */
132#define PMC_MCKR_PRES_MASK (7 << 2) /* for masking out the PRES field */
133#define PMC_MCKR_PRES_1 (0 << 2) /* Core = CSS/1 */
134#define PMC_MCKR_PRES_2 (1 << 2) /* Core = CSS/2 */
135#define PMC_MCKR_PRES_4 (2 << 2) /* Core = CSS/4 */
136#define PMC_MCKR_PRES_8 (3 << 2) /* Core = CSS/8 */
137#define PMC_MCKR_PRES_16 (4 << 2) /* Core = CSS/16 */
138#define PMC_MCKR_PRES_32 (5 << 2) /* Core = CSS/32 */
139#define PMC_MCKR_PRES_64 (6 << 2) /* Core = CSS/64 */
140#define PMC_MCKR_CSS_MASK (3 << 0) /* for masking out the CSS field */
141#define PMC_MCKR_CSS_SLOW (0 << 0) /* Core Source = Slow Clock */
142#define PMC_MCKR_CSS_MAIN (1 << 0) /* Core Source = Main Oscillator */
143#define PMC_MCKR_CSS_PLLA (2 << 0) /* Core Source = PLL A */
144#define PMC_MCKR_CSS_PLLB (3 << 0) /* Core Source = PLL B */
145
146/* PMC_PCKR0 - 7 - Programmable Clock Register 0 */
147#define PMC_PCKR_PRES_1 (0 << 2) /* Peripheral Clock = CSS/1 */
148#define PMC_PCKR_PRES_2 (1 << 2) /* Peripheral Clock = CSS/2 */
149#define PMC_PCKR_PRES_4 (2 << 2) /* Peripheral Clock = CSS/4 */
150#define PMC_PCKR_PRES_8 (3 << 2) /* Peripheral Clock = CSS/8 */
151#define PMC_PCKR_PRES_16 (4 << 2) /* Peripheral Clock = CSS/16 */
152#define PMC_PCKR_PRES_32 (5 << 2) /* Peripheral Clock = CSS/32 */
153#define PMC_PCKR_PRES_64 (6 << 2) /* Peripheral Clock = CSS/64 */
154#define PMC_PCKR_CSS_SLOW (0 << 0) /* Peripheral Clock Source = Slow Clock */
155#define PMC_PCKR_CSS_MAIN (1 << 0) /* Peripheral Clock Source = Main Oscillator */
156#define PMC_PCKR_CSS_PLLA (2 << 0) /* Peripheral Clock Source = PLL A */
157#define PMC_PCKR_CSS_PLLB (3 << 0) /* Peripheral Clock Source = PLL B */
158
159/* PMC_IER - Interrupt Enable Register */
160/* PMC_IDR - Interrupt Disable Register */
161/* PMC_SR - Status Register */
162/* PMC_IMR - Interrupt Mask Register */
163#define PMC_INT_PCK7_RDY BIT15
164#define PMC_INT_PCK6_RDY BIT14
165#define PMC_INT_PCK5_RDY BIT13
166#define PMC_INT_PCK4_RDY BIT12
167#define PMC_INT_PCK3_RDY BIT11
168#define PMC_INT_PCK2_RDY BIT10
169#define PMC_INT_PCK1_RDY BIT9
170#define PMC_INT_PCK0_RDY BIT8
171#define PMC_INT_MCK_RDY BIT3
172#define PMC_INT_LOCKB BIT2
173#define PMC_INT_LCKA BIT1
174#define PMC_INT_MOSCS BIT0
175
176
177#endif
bits.h
Contains Defined Bits.
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