36#ifndef LIBBSP_ARM_SHARED_ARM_GIC_H
37#define LIBBSP_ARM_SHARED_ARM_GIC_H
55#define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5)
56#define GIC_ID_TO_ONE_BIT_REG_BIT(id) (1U << ((id) & 0x1fU))
58#define GIC_ID_TO_TWO_BITS_REG_INDEX(id) ((id) >> 4)
59#define GIC_ID_TO_TWO_BITS_REG_OFFSET(id) (((id) & 0xfU) << 1)
61static inline bool gic_id_is_enabled(
volatile gic_dist *dist, uint32_t
id)
63 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
64 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
66 return (dist->icdiser[i] & bit) != 0;
69static inline void gic_id_enable(
volatile gic_dist *dist, uint32_t
id)
71 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
72 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
74 dist->icdiser[i] = bit;
77static inline void gic_id_disable(
volatile gic_dist *dist, uint32_t
id)
79 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
80 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
82 dist->icdicer[i] = bit;
85static inline bool gic_id_is_pending(
volatile gic_dist *dist, uint32_t
id)
87 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
88 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
90 return (dist->icdispr[i] & bit) != 0;
93static inline void gic_id_set_pending(
volatile gic_dist *dist, uint32_t
id)
95 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
96 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
98 dist->icdispr[i] = bit;
101static inline void gic_id_clear_pending(
volatile gic_dist *dist, uint32_t
id)
103 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
104 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
106 dist->icdicpr[i] = bit;
109static inline bool gic_id_is_active(
volatile gic_dist *dist, uint32_t
id)
111 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
112 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
114 return (dist->icdabr[i] & bit) != 0;
122static inline gic_group gic_id_get_group(
127 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
128 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
130 return (dist->icdigr[i] & bit) != 0 ? GIC_GROUP_1 : GIC_GROUP_0;
133static inline void gic_id_set_group(
139 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
140 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
141 uint32_t icdigr = dist->icdigr[i];
145 if (group == GIC_GROUP_1) {
149 dist->icdigr[i] = icdigr;
152static inline void gic_id_set_priority(
158 dist->icdipr[id] = priority;
161static inline uint8_t gic_id_get_priority(
volatile gic_dist *dist, uint32_t
id)
163 return dist->icdipr[id];
166static inline void gic_id_set_targets(
172 dist->icdiptr[id] = targets;
175static inline uint8_t gic_id_get_targets(
volatile gic_dist *dist, uint32_t
id)
177 return dist->icdiptr[id];
185static inline gic_trigger_mode gic_id_get_trigger_mode(
190 uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(
id);
191 uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(
id) + 1;
192 uint32_t bit = 1U << o;
194 return (dist->icdicfr[i] & bit) != 0 ?
195 GIC_EDGE_TRIGGERED : GIC_LEVEL_SENSITIVE;
198static inline void gic_id_set_trigger_mode(
201 gic_trigger_mode mode
204 uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(
id);
205 uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(
id) + 1;
206 uint32_t bit = mode << o;
207 uint32_t mask = 1U << o;
208 uint32_t icdicfr = dist->icdicfr[i];
213 dist->icdicfr[i] = icdicfr;
221static inline gic_handling_model gic_id_get_handling_model(
226 uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(
id);
227 uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(
id);
228 uint32_t bit = 1U << o;
230 return (dist->icdicfr[i] & bit) != 0 ? GIC_1_TO_N : GIC_N_TO_N;
233static inline void gic_id_set_handling_model(
236 gic_handling_model model
239 uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(
id);
240 uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(
id);
241 uint32_t bit = model << o;
242 uint32_t mask = 1U << o;
243 uint32_t icdicfr = dist->icdicfr[i];
248 dist->icdicfr[i] = icdicfr;
ARM GIC Register definitions.
Definition: arm-gic-regs.h:101