36#ifndef _RTEMS_TMTEST27
37#error "This is an RTEMS internal file you must not include directly."
40#ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H
41#define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H
48#define MUST_WAIT_FOR_INTERRUPT 1
50#ifndef ARM_GIC_TM27_IRQ_LOW
51#define ARM_GIC_TM27_IRQ_LOW ARM_GIC_IRQ_SGI_12
54#ifndef ARM_GIC_TM27_IRQ_HIGH
55#define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13
58#define TM27_INTERRUPT_VECTOR_DEFAULT ARM_GIC_TM27_IRQ_LOW
60#define ARM_GIC_TM27_PRIO_LOW 0x80
62#define ARM_GIC_TM27_PRIO_HIGH 0x00
70 rtems_interrupt_entry_initialize(
83 sc = arm_gic_irq_set_priority(
89 rtems_interrupt_entry_initialize(
96 ARM_GIC_TM27_IRQ_HIGH,
102 sc = arm_gic_irq_set_priority(
103 ARM_GIC_TM27_IRQ_HIGH,
104 ARM_GIC_TM27_PRIO_HIGH
109static inline void Cause_tm27_intr(
void)
113 sc = arm_gic_irq_generate_software_irq(
114 ARM_GIC_TM27_IRQ_LOW,
115 1U << _SMP_Get_current_processor()
120static inline void Clear_tm27_intr(
void)
125static inline void Lower_tm27_intr(
void)
129 sc = arm_gic_irq_generate_software_irq(
130 ARM_GIC_TM27_IRQ_HIGH,
131 1U << _SMP_Get_current_processor()
This header file provides the interfaces of the Assert Handler.
rtems_status_code rtems_interrupt_entry_install(rtems_vector_number vector, rtems_option options, rtems_interrupt_entry *entry)
Installs the interrupt entry at the interrupt vector.
Definition: irq-generic.c:264
#define RTEMS_INTERRUPT_UNIQUE
This interrupt handler install option ensures that the interrupt handler is unique.
Definition: intr.h:907
void(* rtems_interrupt_handler)(void *)
Interrupt handler routines shall have this type.
Definition: intr.h:965
rtems_status_code
This enumeration provides status codes for directives of the Classic API.
Definition: status.h:85
@ RTEMS_SUCCESSFUL
This status code indicates successful completion of a requested operation.
Definition: status.h:90
#define _Assert_Unused_variable_equals(_var, _val)
Assert if unused return value is equal.
Definition: assert.h:108
#define NULL
Requests a GPIO pin group configuration.
Definition: xil_types.h:54
This structure represents an interrupt entry.
Definition: intr.h:1005