RTEMS 6.1-rc2
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arm-gic-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H
37#define LIBBSP_ARM_SHARED_ARM_GIC_REGS_H
38
39#include <bsp/utility.h>
40
41typedef struct {
42 uint32_t iccicr;
43#define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4)
44#define GIC_CPUIF_ICCICR_FIQ_EN BSP_BIT32(3)
45#define GIC_CPUIF_ICCICR_ACK_CTL BSP_BIT32(2)
46#define GIC_CPUIF_ICCICR_ENABLE_GRP_1 BSP_BIT32(1)
47#define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0)
48 uint32_t iccpmr;
49#define GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7)
50#define GIC_CPUIF_ICCPMR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7)
51#define GIC_CPUIF_ICCPMR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
52 uint32_t iccbpr;
53#define GIC_CPUIF_ICCBPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2)
54#define GIC_CPUIF_ICCBPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2)
55#define GIC_CPUIF_ICCBPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
56 uint32_t icciar;
57#define GIC_CPUIF_ICCIAR_CPUID(val) BSP_FLD32(val, 10, 12)
58#define GIC_CPUIF_ICCIAR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
59#define GIC_CPUIF_ICCIAR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
60#define GIC_CPUIF_ICCIAR_ACKINTID(val) BSP_FLD32(val, 0, 9)
61#define GIC_CPUIF_ICCIAR_ACKINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
62#define GIC_CPUIF_ICCIAR_ACKINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
63 uint32_t icceoir;
64#define GIC_CPUIF_ICCEOIR_CPUID(val) BSP_FLD32(val, 10, 12)
65#define GIC_CPUIF_ICCEOIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
66#define GIC_CPUIF_ICCEOIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
67#define GIC_CPUIF_ICCEOIR_EOIINTID(val) BSP_FLD32(val, 0, 9)
68#define GIC_CPUIF_ICCEOIR_EOIINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
69#define GIC_CPUIF_ICCEOIR_EOIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
70 uint32_t iccrpr;
71#define GIC_CPUIF_ICCRPR_PRIORITY(val) BSP_FLD32(val, 0, 7)
72#define GIC_CPUIF_ICCRPR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7)
73#define GIC_CPUIF_ICCRPR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
74 uint32_t icchpir;
75#define GIC_CPUIF_ICCHPIR_CPUID(val) BSP_FLD32(val, 10, 12)
76#define GIC_CPUIF_ICCHPIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
77#define GIC_CPUIF_ICCHPIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
78#define GIC_CPUIF_ICCHPIR_PENDINTID(val) BSP_FLD32(val, 0, 9)
79#define GIC_CPUIF_ICCHPIR_PENDINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
80#define GIC_CPUIF_ICCHPIR_PENDINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
81 uint32_t iccabpr;
82#define GIC_CPUIF_ICCABPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2)
83#define GIC_CPUIF_ICCABPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2)
84#define GIC_CPUIF_ICCABPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
85 uint32_t reserved_20[55];
86 uint32_t icciidr;
87#define GIC_CPUIF_ICCIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31)
88#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31)
89#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
90#define GIC_CPUIF_ICCIIDR_ARCH_VERSION(val) BSP_FLD32(val, 16, 19)
91#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_GET(reg) BSP_FLD32GET(reg, 16, 19)
92#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
93#define GIC_CPUIF_ICCIIDR_REVISION(val) BSP_FLD32(val, 12, 15)
94#define GIC_CPUIF_ICCIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15)
95#define GIC_CPUIF_ICCIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
96#define GIC_CPUIF_ICCIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11)
97#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
98#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
99} gic_cpuif;
100
101typedef struct {
102 /* GICD_CTLR */
103 uint32_t icddcr;
104/* GICv3 only */
105#define GIC_DIST_ICDDCR_RWP BSP_BIT32(31)
106#define GIC_DIST_ICDDCR_E1NWF BSP_BIT32(7)
107#define GIC_DIST_ICDDCR_DS BSP_BIT32(6)
108#define GIC_DIST_ICDDCR_ARE_NS BSP_BIT32(5)
109#define GIC_DIST_ICDDCR_ARE_S BSP_BIT32(4)
110#define GIC_DIST_ICDDCR_ENABLE_GRP1S BSP_BIT32(2)
111#define GIC_DIST_ICDDCR_ENABLE_GRP1NS BSP_BIT32(1)
112#define GIC_DIST_ICDDCR_ENABLE_GRP0 BSP_BIT32(0)
113/* GICv1/GICv2 */
114#define GIC_DIST_ICDDCR_ENABLE_GRP_1 BSP_BIT32(1)
115#define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0)
116 uint32_t icdictr;
117#define GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15)
118#define GIC_DIST_ICDICTR_LSPI_GET(reg) BSP_FLD32GET(reg, 11, 15)
119#define GIC_DIST_ICDICTR_LSPI_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15)
120#define GIC_DIST_ICDICTR_SECURITY_EXTN BSP_BIT32(10)
121#define GIC_DIST_ICDICTR_CPU_NUMBER(val) BSP_FLD32(val, 5, 7)
122#define GIC_DIST_ICDICTR_CPU_NUMBER_GET(reg) BSP_FLD32GET(reg, 5, 7)
123#define GIC_DIST_ICDICTR_CPU_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7)
124#define GIC_DIST_ICDICTR_IT_LINES_NUMBER(val) BSP_FLD32(val, 0, 4)
125#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(reg) BSP_FLD32GET(reg, 0, 4)
126#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
127 uint32_t icdiidr;
128#define GIC_DIST_ICDIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31)
129#define GIC_DIST_ICDIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31)
130#define GIC_DIST_ICDIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
131#define GIC_DIST_ICDIIDR_VARIANT(val) BSP_FLD32(val, 16, 19)
132#define GIC_DIST_ICDIIDR_VARIANT_GET(reg) BSP_FLD32GET(reg, 16, 19)
133#define GIC_DIST_ICDIIDR_VARIANT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
134#define GIC_DIST_ICDIIDR_REVISION(val) BSP_FLD32(val, 12, 15)
135#define GIC_DIST_ICDIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15)
136#define GIC_DIST_ICDIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
137#define GIC_DIST_ICDIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11)
138#define GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
139#define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
140 uint32_t reserved_0c[29];
141 uint32_t icdigr[32];
142 uint32_t icdiser[32];
143 uint32_t icdicer[32];
144 uint32_t icdispr[32];
145 uint32_t icdicpr[32];
146 uint32_t icdabr[32];
147 uint32_t reserved_380[32];
148 uint8_t icdipr[256];
149 uint32_t reserved_500[192];
150 uint8_t icdiptr[256];
151 uint32_t reserved_900[192];
152 uint32_t icdicfr[64];
153 /* GICD_IGRPMODR GICv3 only, reserved in GICv1/GICv2 */
154 uint32_t icdigmr[32];
155 uint32_t reserved_d80[96];
156 uint32_t icdsgir;
157#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25)
158#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_GET(reg) BSP_FLD32GET(reg, 24, 25)
159#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25)
160#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST(val) BSP_FLD32(val, 16, 23)
161#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD32GET(reg, 16, 23)
162#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
163#define GIC_DIST_ICDSGIR_NSATT BSP_BIT32(15)
164#define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3)
165#define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3)
166#define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
167} gic_dist;
168
169/* GICv3 only */
170typedef struct {
171 /* GICR_CTLR */
172 uint32_t icrrcr;
173#define GIC_REDIST_ICRRCR_UWP BSP_BIT32(31)
174#define GIC_REDIST_ICRRCR_DPG1S BSP_BIT32(26)
175#define GIC_REDIST_ICRRCR_DPG1NS BSP_BIT32(25)
176#define GIC_REDIST_ICRRCR_DPG0 BSP_BIT32(24)
177#define GIC_REDIST_ICRRCR_RWP BSP_BIT32(4)
178#define GIC_REDIST_ICRRCR_ENABLE_LPI BSP_BIT32(0)
179 uint32_t icriidr;
180 uint64_t icrtyper;
181#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE(val) BSP_FLD64(val, 32, 63)
182#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_GET(reg) BSP_FLD64GET(reg, 32, 63)
183#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_SET(reg, val) BSP_FLD64SET(reg, val, 32, 63)
184#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY(val) BSP_FLD64(val, 24, 25)
185#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_GET(reg) BSP_FLD64GET(reg, 24, 25)
186#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_SET(reg, val) BSP_FLD64SET(reg, val, 24, 25)
187#define GIC_REDIST_ICRTYPER_CPU_NUMBER(val) BSP_FLD64(val, 8, 23)
188#define GIC_REDIST_ICRTYPER_CPU_NUMBER_GET(reg) BSP_FLD64GET(reg, 8, 23)
189#define GIC_REDIST_ICRTYPER_CPU_NUMBER_SET(reg, val) BSP_FLD64SET(reg, val, 8, 23)
190#define GIC_REDIST_ICRTYPER_DPGS BSP_BIT64(5)
191#define GIC_REDIST_ICRTYPER_LAST BSP_BIT64(4)
192#define GIC_REDIST_ICRTYPER_DIRECT_LPI BSP_BIT64(3)
193#define GIC_REDIST_ICRTYPER_VLPIS BSP_BIT64(1)
194#define GIC_REDIST_ICRTYPER_PLPIS BSP_BIT64(0)
195 uint32_t unused_10;
196 uint32_t icrwaker;
197#define GIC_REDIST_ICRWAKER_CHILDREN_ASLEEP BSP_BIT32(2)
198#define GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP BSP_BIT32(1)
199} gic_redist;
200
201/* GICv3 only */
202typedef struct {
203 uint32_t reserved_0_80[32];
204 /* GICR_IGROUPR0 */
205 uint32_t icspigrpr[32];
206 /* GICR_ISENABLER0 */
207 uint32_t icspiser[32];
208 /* GICR_ICENABLER0 */
209 uint32_t icspicer[32];
210 /* GICR_ISPENDR0 */
211 uint32_t icspispendr[32];
212 /* GICR_ICPENDR0 */
213 uint32_t icspicpendr[32];
214 /* GICR_ISACTIVER0 */
215 uint32_t icspisar[32];
216 /* GICR_ICACTIVER0 */
217 uint32_t icspicar[32];
218 /* GICR_IPRIORITYR */
219 uint8_t icspiprior[32];
220 uint32_t reserved_420_bfc[504];
221 /* GICR_ICFGR0 and GICR_ICFGR1 */
222 uint32_t icspicfgr[2];
223 uint32_t reserved_c08_cfc[62];
224 /* GICR_IGRPMODR0 */
225 uint32_t icspigrpmodr[64];
226} gic_sgi_ppi;
227
228#endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */
utility.h
This header file provides utility macros for BSPs.
gic_cpuif
Definition: arm-gic-regs.h:41
gic_dist
Definition: arm-gic-regs.h:101
gic_redist
Definition: arm-gic-regs.h:170
gic_sgi_ppi
Definition: arm-gic-regs.h:202
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